From 09e10d7fe509408d15818db6a0299f563668a7ba Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 16 Mar 2011 22:57:47 +0000 Subject: ASoC: Add WM8958 VSS support With appropriate firmware the WM8958 can support Virtual Surround Sound or VSS, widening the stereo audio image for improved user experience. Enable support for this mode of operation when the appropriate firmware can be loaded at runtime. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- include/linux/mfd/wm8994/pdata.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h index 466b1c777aff..c72174aff1fe 100644 --- a/include/linux/mfd/wm8994/pdata.h +++ b/include/linux/mfd/wm8994/pdata.h @@ -32,6 +32,9 @@ struct wm8994_ldo_pdata { #define WM8994_EQ_REGS 20 #define WM8958_MBC_CUTOFF_REGS 20 #define WM8958_MBC_COEFF_REGS 48 +#define WM8958_MBC_COMBINED_REGS 56 +#define WM8958_VSS_HPF_REGS 2 +#define WM8958_VSS_REGS 148 /** * DRC configurations are specified with a label and a set of register @@ -71,6 +74,31 @@ struct wm8958_mbc_cfg { const char *name; u16 cutoff_regs[WM8958_MBC_CUTOFF_REGS]; u16 coeff_regs[WM8958_MBC_COEFF_REGS]; + + /* Coefficient layout when using MBC+VSS firmware */ + u16 combined_regs[WM8958_MBC_COMBINED_REGS]; +}; + +/** + * VSS HPF configurations are specified with a label and two values to + * write. Configurations are expected to be generated using the + * multiband compressor configuration panel in WISCE - see + * http://www.wolfsonmicro.com/wisce/ + */ +struct wm8958_vss_hpf_cfg { + const char *name; + u16 regs[WM8958_VSS_HPF_REGS]; +}; + +/** + * VSS configurations are specified with a label and array of values + * to write. Configurations are expected to be generated using the + * multiband compressor configuration panel in WISCE - see + * http://www.wolfsonmicro.com/wisce/ + */ +struct wm8958_vss_cfg { + const char *name; + u16 regs[WM8958_VSS_REGS]; }; struct wm8994_pdata { @@ -95,6 +123,12 @@ struct wm8994_pdata { int num_mbc_cfgs; struct wm8958_mbc_cfg *mbc_cfgs; + int num_vss_cfgs; + struct wm8958_vss_cfg *vss_cfgs; + + int num_vss_hpf_cfgs; + struct wm8958_vss_hpf_cfg *vss_hpf_cfgs; + /* LINEOUT can be differential or single ended */ unsigned int lineout1_diff:1; unsigned int lineout2_diff:1; -- cgit v1.2.2 From 312158718fe2056703b2744801165a9574560495 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 17 Mar 2011 20:23:43 +0000 Subject: ASoC: Add WM8958 enhanced EQ support DSP2 in the WM8958 can be used to support an upgraded EQ for use in demanding applications. Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- include/linux/mfd/wm8994/pdata.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h index c72174aff1fe..d12f8d635a81 100644 --- a/include/linux/mfd/wm8994/pdata.h +++ b/include/linux/mfd/wm8994/pdata.h @@ -35,6 +35,7 @@ struct wm8994_ldo_pdata { #define WM8958_MBC_COMBINED_REGS 56 #define WM8958_VSS_HPF_REGS 2 #define WM8958_VSS_REGS 148 +#define WM8958_ENH_EQ_REGS 32 /** * DRC configurations are specified with a label and a set of register @@ -101,6 +102,17 @@ struct wm8958_vss_cfg { u16 regs[WM8958_VSS_REGS]; }; +/** + * Enhanced EQ configurations are specified with a label and array of + * values to write. Configurations are expected to be generated using + * the multiband compressor configuration panel in WISCE - see + * http://www.wolfsonmicro.com/wisce/ + */ +struct wm8958_enh_eq_cfg { + const char *name; + u16 regs[WM8958_ENH_EQ_REGS]; +}; + struct wm8994_pdata { int gpio_base; @@ -129,6 +141,9 @@ struct wm8994_pdata { int num_vss_hpf_cfgs; struct wm8958_vss_hpf_cfg *vss_hpf_cfgs; + int num_enh_eq_cfgs; + struct wm8958_enh_eq_cfg *enh_eq_cfgs; + /* LINEOUT can be differential or single ended */ unsigned int lineout1_diff:1; unsigned int lineout2_diff:1; -- cgit v1.2.2 From 650c2a2145981696c414be1d540a32447d0e353e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 15 May 2011 22:53:56 +0200 Subject: mach-ux500: move the DB8500 PRCMU driver to MFD We have decided that this function arbiter fits better in the MFD subsystem. Since we need to concatenate the split header files we move it basically like this: mv mach-ux500/prcmu-db8500.c drivers/mfd/db8500-prcmu.c mv mach-ux500/include/mach/prcmu-defs.h include/linux/mfd/db8500-prcmu.h mv mach-ux500/include/mach/prcmu-regs.h drivers/mfd/db8500-prcmu-regs.h mach-ux500/include/mach/prcmu.h >> include/linux/mfd/db8500-prcmu.h rm arch/arm/mach-ux500/include/mach/prcmu.h Then we update different #include statements and Makefile orders etc to make the PRCMU driver compile, link and boot in the new place without really changing any code. Acked-by: Samuel Ortiz Signed-off-by: Linus Walleij --- include/linux/mfd/db8500-prcmu.h | 58 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 include/linux/mfd/db8500-prcmu.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h new file mode 100644 index 000000000000..d591d79aa6f0 --- /dev/null +++ b/include/linux/mfd/db8500-prcmu.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) STMicroelectronics 2009 + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Sundar Iyer + * Author: Martin Persson + * + * License Terms: GNU General Public License v2 + * + * PRCM Unit definitions + */ + +#ifndef __MACH_PRCMU_DEFS_H +#define __MACH_PRCMU_DEFS_H + +enum prcmu_cpu_opp { + CPU_OPP_INIT = 0x00, + CPU_OPP_NO_CHANGE = 0x01, + CPU_OPP_100 = 0x02, + CPU_OPP_50 = 0x03, + CPU_OPP_MAX = 0x04, + CPU_OPP_EXT_CLK = 0x07 +}; +enum prcmu_ape_opp { + APE_OPP_NO_CHANGE = 0x00, + APE_OPP_100 = 0x02, + APE_OPP_50 = 0x03, +}; + +#endif /* __MACH_PRCMU_DEFS_H */ + +/* + * Copyright (C) STMicroelectronics 2009 + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Kumar Sanghvi + * Author: Sundar Iyer + * Author: Mattias Nilsson + * + * License Terms: GNU General Public License v2 + * + * PRCM Unit f/w API + */ +#ifndef __MACH_PRCMU_H +#define __MACH_PRCMU_H + +void __init prcmu_early_init(void); +int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); +int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); +int prcmu_set_ape_opp(enum prcmu_ape_opp opp); +int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp); +int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp, + enum prcmu_cpu_opp cpu_opp); +enum prcmu_ape_opp prcmu_get_ape_opp(void); +int prcmu_get_cpu_opp(void); +bool prcmu_has_arm_maxopp(void); + +#endif /* __MACH_PRCMU_H */ -- cgit v1.2.2 From 3df57bcf5a6ba74572218a811bd0e311414f2aff Mon Sep 17 00:00:00 2001 From: Mattias Nilsson Date: Mon, 16 May 2011 00:15:05 +0200 Subject: mfd: update DB8500 PRCMU driver This updates the DB8500 PRCMU driver to the latest version available internally. Nominally we would update the dependent CPUfreq driver at the same time but since that is being moved around in this patch set we postpone that by simply deactivating it for the time being. This is a snapshot of the current PRCMU firmware API as it looks right now. The PRCMU firmware is still subject to change. This also updates the CPUfreq driver to a newer version that will utilize the new API. Acked-by: Samuel Ortiz Signed-off-by: Mattias Nilsson Signed-off-by: Martin Persson Signed-off-by: Per Fransson Signed-off-by: Jonas Aaberg Signed-off-by: Sebastien Rault Signed-off-by: Bengt Jonsson Signed-off-by: Rickard Andersson Signed-off-by: Linus Walleij --- include/linux/mfd/db8500-prcmu.h | 992 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 956 insertions(+), 36 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h index d591d79aa6f0..917dbcab701c 100644 --- a/include/linux/mfd/db8500-prcmu.h +++ b/include/linux/mfd/db8500-prcmu.h @@ -2,57 +2,977 @@ * Copyright (C) STMicroelectronics 2009 * Copyright (C) ST-Ericsson SA 2010 * - * Author: Sundar Iyer - * Author: Martin Persson - * * License Terms: GNU General Public License v2 + * Author: Kumar Sanghvi * - * PRCM Unit definitions + * PRCMU f/w APIs */ +#ifndef __MFD_DB8500_PRCMU_H +#define __MFD_DB8500_PRCMU_H + +#include +#include -#ifndef __MACH_PRCMU_DEFS_H -#define __MACH_PRCMU_DEFS_H +/* This portion previously known as */ -enum prcmu_cpu_opp { - CPU_OPP_INIT = 0x00, - CPU_OPP_NO_CHANGE = 0x01, - CPU_OPP_100 = 0x02, - CPU_OPP_50 = 0x03, - CPU_OPP_MAX = 0x04, - CPU_OPP_EXT_CLK = 0x07 +/** + * enum state - ON/OFF state definition + * @OFF: State is ON + * @ON: State is OFF + * + */ +enum state { + OFF = 0x0, + ON = 0x1, }; -enum prcmu_ape_opp { - APE_OPP_NO_CHANGE = 0x00, - APE_OPP_100 = 0x02, - APE_OPP_50 = 0x03, + +/** + * enum ret_state - general purpose On/Off/Retention states + * + */ +enum ret_state { + OFFST = 0, + ONST = 1, + RETST = 2 }; -#endif /* __MACH_PRCMU_DEFS_H */ +/** + * enum clk_arm - ARM Cortex A9 clock schemes + * @A9_OFF: + * @A9_BOOT: + * @A9_OPPT1: + * @A9_OPPT2: + * @A9_EXTCLK: + */ +enum clk_arm { + A9_OFF, + A9_BOOT, + A9_OPPT1, + A9_OPPT2, + A9_EXTCLK +}; -/* - * Copyright (C) STMicroelectronics 2009 - * Copyright (C) ST-Ericsson SA 2010 +/** + * enum clk_gen - GEN#0/GEN#1 clock schemes + * @GEN_OFF: + * @GEN_BOOT: + * @GEN_OPPT1: + */ +enum clk_gen { + GEN_OFF, + GEN_BOOT, + GEN_OPPT1, +}; + +/* some information between arm and xp70 */ + +/** + * enum romcode_write - Romcode message written by A9 AND read by XP70 + * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70 + * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the + * romcode. The xp70 will go into self-reset + */ +enum romcode_write { + RDY_2_DS = 0x09, + RDY_2_XP70_RST = 0x10 +}; + +/** + * enum romcode_read - Romcode message written by XP70 and read by A9 + * @INIT: Init value when romcode field is not used + * @FS_2_DS: Value set when power state is going from ApExecute to + * ApDeepSleep + * @END_DS: Value set when ApDeepSleep power state is reached coming from + * ApExecute state + * @DS_TO_FS: Value set when power state is going from ApDeepSleep to + * ApExecute + * @END_FS: Value set when ApExecute power state is reached coming from + * ApDeepSleep state + * @SWR: Value set when power state is going to ApReset + * @END_SWR: Value set when the xp70 finished executing ApReset actions and + * waits for romcode acknowledgment to go to self-reset + */ +enum romcode_read { + INIT = 0x00, + FS_2_DS = 0x0A, + END_DS = 0x0B, + DS_TO_FS = 0x0C, + END_FS = 0x0D, + SWR = 0x0E, + END_SWR = 0x0F +}; + +/** + * enum ap_pwrst - current power states defined in PRCMU firmware + * @NO_PWRST: Current power state init + * @AP_BOOT: Current power state is apBoot + * @AP_EXECUTE: Current power state is apExecute + * @AP_DEEP_SLEEP: Current power state is apDeepSleep + * @AP_SLEEP: Current power state is apSleep + * @AP_IDLE: Current power state is apIdle + * @AP_RESET: Current power state is apReset + */ +enum ap_pwrst { + NO_PWRST = 0x00, + AP_BOOT = 0x01, + AP_EXECUTE = 0x02, + AP_DEEP_SLEEP = 0x03, + AP_SLEEP = 0x04, + AP_IDLE = 0x05, + AP_RESET = 0x06 +}; + +/** + * enum ap_pwrst_trans - Transition states defined in PRCMU firmware + * @NO_TRANSITION: No power state transition + * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep + * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep + * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute + * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to + * ApDeepSleep + * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle + */ +enum ap_pwrst_trans { + NO_TRANSITION = 0x00, + APEXECUTE_TO_APSLEEP = 0x01, + APIDLE_TO_APSLEEP = 0x02, /* To be removed */ + PRCMU_AP_SLEEP = 0x01, + APBOOT_TO_APEXECUTE = 0x03, + APEXECUTE_TO_APDEEPSLEEP = 0x04, /* To be removed */ + PRCMU_AP_DEEP_SLEEP = 0x04, + APEXECUTE_TO_APIDLE = 0x05, /* To be removed */ + PRCMU_AP_IDLE = 0x05, + PRCMU_AP_DEEP_IDLE = 0x07, +}; + +/** + * enum ddr_pwrst - DDR power states definition + * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged + * @DDR_PWR_STATE_ON: + * @DDR_PWR_STATE_OFFLOWLAT: + * @DDR_PWR_STATE_OFFHIGHLAT: + */ +enum ddr_pwrst { + DDR_PWR_STATE_UNCHANGED = 0x00, + DDR_PWR_STATE_ON = 0x01, + DDR_PWR_STATE_OFFLOWLAT = 0x02, + DDR_PWR_STATE_OFFHIGHLAT = 0x03 +}; + +/** + * enum arm_opp - ARM OPP states definition + * @ARM_OPP_INIT: + * @ARM_NO_CHANGE: The ARM operating point is unchanged + * @ARM_100_OPP: The new ARM operating point is arm100opp + * @ARM_50_OPP: The new ARM operating point is arm50opp + * @ARM_MAX_OPP: Operating point is "max" (more than 100) + * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 + * @ARM_EXTCLK: The new ARM operating point is armExtClk + */ +enum arm_opp { + ARM_OPP_INIT = 0x00, + ARM_NO_CHANGE = 0x01, + ARM_100_OPP = 0x02, + ARM_50_OPP = 0x03, + ARM_MAX_OPP = 0x04, + ARM_MAX_FREQ100OPP = 0x05, + ARM_EXTCLK = 0x07 +}; + +/** + * enum ape_opp - APE OPP states definition + * @APE_OPP_INIT: + * @APE_NO_CHANGE: The APE operating point is unchanged + * @APE_100_OPP: The new APE operating point is ape100opp + * @APE_50_OPP: 50% + */ +enum ape_opp { + APE_OPP_INIT = 0x00, + APE_NO_CHANGE = 0x01, + APE_100_OPP = 0x02, + APE_50_OPP = 0x03 +}; + +/** + * enum hw_acc_state - State definition for hardware accelerator + * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged + * @HW_OFF: The hardware accelerator must be switched off + * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its + * internal RAM in retention + * @HW_ON: The hwa hardware accelerator hwa must be switched on * - * Author: Kumar Sanghvi - * Author: Sundar Iyer - * Author: Mattias Nilsson + * NOTE! Deprecated, to be removed when all users switched over to use the + * regulator API. + */ +enum hw_acc_state { + HW_NO_CHANGE = 0x00, + HW_OFF = 0x01, + HW_OFF_RAMRET = 0x02, + HW_ON = 0x04 +}; + +/** + * enum mbox_2_arm_stat - Status messages definition for mbox_arm + * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been + * completed + * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been + * completed + * @SLEEPOK: The apExecute to apSleep state transition has been completed + * @IDLEOK: The apExecute to apIdle state transition has been completed + * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed + * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going + * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going + * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on + * going + * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on + * going + * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has + * been completed + * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going + * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going + * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been + * completed + * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going + * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going + * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been + * completed + * @INIT_STATUS: Status init + */ +enum ap_pwrsttr_status { + BOOT_TO_EXECUTEOK = 0xFF, + DEEPSLEEPOK = 0xFE, + SLEEPOK = 0xFD, + IDLEOK = 0xFC, + SOFTRESETOK = 0xFB, + SOFTRESETGO = 0xFA, + BOOT_TO_EXECUTE = 0xF9, + EXECUTE_TO_DEEPSLEEP = 0xF8, + DEEPSLEEP_TO_EXECUTE = 0xF7, + DEEPSLEEP_TO_EXECUTEOK = 0xF6, + EXECUTE_TO_SLEEP = 0xF5, + SLEEP_TO_EXECUTE = 0xF4, + SLEEP_TO_EXECUTEOK = 0xF3, + EXECUTE_TO_IDLE = 0xF2, + IDLE_TO_EXECUTE = 0xF1, + IDLE_TO_EXECUTEOK = 0xF0, + RDYTODS_RETURNTOEXE = 0xEF, + NORDYTODS_RETURNTOEXE = 0xEE, + EXETOSLEEP_RETURNTOEXE = 0xED, + EXETOIDLE_RETURNTOEXE = 0xEC, + INIT_STATUS = 0xEB, + + /*error messages */ + INITERROR = 0x00, + PLLARMLOCKP_ER = 0x01, + PLLDDRLOCKP_ER = 0x02, + PLLSOCLOCKP_ER = 0x03, + PLLSOCK1LOCKP_ER = 0x04, + ARMWFI_ER = 0x05, + SYSCLKOK_ER = 0x06, + I2C_NACK_DATA_ER = 0x07, + BOOT_ER = 0x08, + I2C_STATUS_ALWAYS_1 = 0x0A, + I2C_NACK_REG_ADDR_ER = 0x0B, + I2C_NACK_DATA0123_ER = 0x1B, + I2C_NACK_ADDR_ER = 0x1F, + CURAPPWRSTISNOT_BOOT = 0x20, + CURAPPWRSTISNOT_EXECUTE = 0x21, + CURAPPWRSTISNOT_SLEEPMODE = 0x22, + CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23, + FIFO4500WUISNOT_WUPEVENT = 0x24, + PLL32KLOCKP_ER = 0x29, + DDRDEEPSLEEPOK_ER = 0x2A, + ROMCODEREADY_ER = 0x50, + WUPBEFOREDS = 0x51, + DDRCONFIG_ER = 0x52, + WUPBEFORESLEEP = 0x53, + WUPBEFOREIDLE = 0x54 +}; /* earlier called as mbox_2_arm_stat */ + +/** + * enum dvfs_stat - DVFS status messages definition + * @DVFS_GO: A state transition DVFS is on going + * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP + * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP + * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK + * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for + * NOCHGCLK + * @DVFS_INITSTATUS: Value init + */ +enum dvfs_stat { + DVFS_GO = 0xFF, + DVFS_ARM100OPPOK = 0xFE, + DVFS_ARM50OPPOK = 0xFD, + DVFS_ARMEXTCLKOK = 0xFC, + DVFS_NOCHGTCLKOK = 0xFB, + DVFS_INITSTATUS = 0x00 +}; + +/** + * enum sva_mmdsp_stat - SVA MMDSP status messages + * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened + * @SVA_MMDSP_INIT: Status init + */ +enum sva_mmdsp_stat { + SVA_MMDSP_GO = 0xFF, + SVA_MMDSP_INIT = 0x00 +}; + +/** + * enum sia_mmdsp_stat - SIA MMDSP status messages + * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened + * @SIA_MMDSP_INIT: Status init + */ +enum sia_mmdsp_stat { + SIA_MMDSP_GO = 0xFF, + SIA_MMDSP_INIT = 0x00 +}; + +/** + * enum mbox_to_arm_err - Error messages definition + * @INIT_ERR: Init value + * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time + * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time + * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time + * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time + * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time + * @SYSCLKOK_ERR: The SYSCLK is not available in the given time + * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time + * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context + * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered + * through I2C has not been correctly executed in the given time + * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered + * through I2C has not been correctly executed in the given time + * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through + * I2C has not been correctly executed in the given time + * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered + * through I2C has not been correctly executed in the given time + * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through + * I2C has not been correctly executed in the given time + * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered + * through I2C has not been correctly executed in the given time + * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through + * I2C has not been correctly executed in the given time + * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C + * has not been correctly executed in the given time + * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has + * not been correctly executed in the given time + * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has + * not been correctly executed in the given time + * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through + * I2C has not been correctly executed in the given time + * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through + * I2C has not been correctly executed in the given time + * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered + * through I2C has not been correctly executed in the given time + * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition + * ApBoot to ApExecute but the power current state is not Apboot + * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state + * transition from ApExecute to others power state but the + * power current state is not ApExecute + * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted + * but the power current state is not ApDeepSleep/ApSleep/ApIdle + * @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted + * but the power current state is not correct + * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not + * been correctly executed in the given time + * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not + * been correctly executed in the given time + * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not + * been correctly executed in the given time + * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not + * been correctly executed in the given time + * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not + * been correctly executed in the given time + */ +enum mbox_to_arm_err { + INIT_ERR = 0x00, + PLLARMLOCKP_ERR = 0x01, + PLLDDRLOCKP_ERR = 0x02, + PLLSOC0LOCKP_ERR = 0x03, + PLLSOC1LOCKP_ERR = 0x04, + ARMWFI_ERR = 0x05, + SYSCLKOK_ERR = 0x06, + BOOT_ERR = 0x07, + ROMCODESAVECONTEXT = 0x08, + VARMHIGHSPEEDVALTO_ERR = 0x10, + VARMHIGHSPEEDACCESS_ERR = 0x11, + VARMLOWSPEEDVALTO_ERR = 0x12, + VARMLOWSPEEDACCESS_ERR = 0x13, + VARMRETENTIONVALTO_ERR = 0x14, + VARMRETENTIONACCESS_ERR = 0x15, + VAPEHIGHSPEEDVALTO_ERR = 0x16, + VSAFEHPVALTO_ERR = 0x17, + VMODSEL1VALTO_ERR = 0x18, + VMODSEL2VALTO_ERR = 0x19, + VARMOFFACCESS_ERR = 0x1A, + VAPEOFFACCESS_ERR = 0x1B, + VARMRETACCES_ERR = 0x1C, + CURAPPWRSTISNOTBOOT = 0x20, + CURAPPWRSTISNOTEXECUTE = 0x21, + CURAPPWRSTISNOTSLEEPMODE = 0x22, + CURAPPWRSTISNOTCORRECTDBG = 0x23, + ARMREGU1VALTO_ERR = 0x24, + ARMREGU2VALTO_ERR = 0x25, + VAPEREGUVALTO_ERR = 0x26, + VSMPS3REGUVALTO_ERR = 0x27, + VMODREGUVALTO_ERR = 0x28 +}; + +enum hw_acc { + SVAMMDSP = 0, + SVAPIPE = 1, + SIAMMDSP = 2, + SIAPIPE = 3, + SGA = 4, + B2R2MCDE = 5, + ESRAM12 = 6, + ESRAM34 = 7, +}; + +enum cs_pwrmgt { + PWRDNCS0 = 0, + WKUPCS0 = 1, + PWRDNCS1 = 2, + WKUPCS1 = 3 +}; + +/* Defs related to autonomous power management */ + +/** + * enum sia_sva_pwr_policy - Power policy + * @NO_CHGT: No change + * @DSPOFF_HWPOFF: + * @DSPOFFRAMRET_HWPOFF: + * @DSPCLKOFF_HWPOFF: + * @DSPCLKOFF_HWPCLKOFF: * - * License Terms: GNU General Public License v2 + */ +enum sia_sva_pwr_policy { + NO_CHGT = 0x0, + DSPOFF_HWPOFF = 0x1, + DSPOFFRAMRET_HWPOFF = 0x2, + DSPCLKOFF_HWPOFF = 0x3, + DSPCLKOFF_HWPCLKOFF = 0x4, +}; + +/** + * enum auto_enable - Auto Power enable + * @AUTO_OFF: + * @AUTO_ON: + * + */ +enum auto_enable { + AUTO_OFF = 0x0, + AUTO_ON = 0x1, +}; + +/* End of file previously known as prcmu-fw-defs_v1.h */ + +/* PRCMU Wakeup defines */ +enum prcmu_wakeup_index { + PRCMU_WAKEUP_INDEX_RTC, + PRCMU_WAKEUP_INDEX_RTT0, + PRCMU_WAKEUP_INDEX_RTT1, + PRCMU_WAKEUP_INDEX_HSI0, + PRCMU_WAKEUP_INDEX_HSI1, + PRCMU_WAKEUP_INDEX_USB, + PRCMU_WAKEUP_INDEX_ABB, + PRCMU_WAKEUP_INDEX_ABB_FIFO, + PRCMU_WAKEUP_INDEX_ARM, + NUM_PRCMU_WAKEUP_INDICES +}; +#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) + +/* PRCMU QoS APE OPP class */ +#define PRCMU_QOS_APE_OPP 1 +#define PRCMU_QOS_DDR_OPP 2 +#define PRCMU_QOS_DEFAULT_VALUE -1 + +/** + * enum hw_acc_dev - enum for hw accelerators + * @HW_ACC_SVAMMDSP: for SVAMMDSP + * @HW_ACC_SVAPIPE: for SVAPIPE + * @HW_ACC_SIAMMDSP: for SIAMMDSP + * @HW_ACC_SIAPIPE: for SIAPIPE + * @HW_ACC_SGA: for SGA + * @HW_ACC_B2R2: for B2R2 + * @HW_ACC_MCDE: for MCDE + * @HW_ACC_ESRAM1: for ESRAM1 + * @HW_ACC_ESRAM2: for ESRAM2 + * @HW_ACC_ESRAM3: for ESRAM3 + * @HW_ACC_ESRAM4: for ESRAM4 + * @NUM_HW_ACC: number of hardware accelerators + * + * Different hw accelerators which can be turned ON/ + * OFF or put into retention (MMDSPs and ESRAMs). + * Used with EPOD API. * - * PRCM Unit f/w API + * NOTE! Deprecated, to be removed when all users switched over to use the + * regulator API. + */ +enum hw_acc_dev { + HW_ACC_SVAMMDSP, + HW_ACC_SVAPIPE, + HW_ACC_SIAMMDSP, + HW_ACC_SIAPIPE, + HW_ACC_SGA, + HW_ACC_B2R2, + HW_ACC_MCDE, + HW_ACC_ESRAM1, + HW_ACC_ESRAM2, + HW_ACC_ESRAM3, + HW_ACC_ESRAM4, + NUM_HW_ACC +}; + +/* + * Ids for all EPODs (power domains) + * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP + * - EPOD_ID_SVAPIPE: power domain for SVA pipe + * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP + * - EPOD_ID_SIAPIPE: power domain for SIA pipe + * - EPOD_ID_SGA: power domain for SGA + * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE + * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 + * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 + * - NUM_EPOD_ID: number of power domains + */ +#define EPOD_ID_SVAMMDSP 0 +#define EPOD_ID_SVAPIPE 1 +#define EPOD_ID_SIAMMDSP 2 +#define EPOD_ID_SIAPIPE 3 +#define EPOD_ID_SGA 4 +#define EPOD_ID_B2R2_MCDE 5 +#define EPOD_ID_ESRAM12 6 +#define EPOD_ID_ESRAM34 7 +#define NUM_EPOD_ID 8 + +/* + * state definition for EPOD (power domain) + * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged + * - EPOD_STATE_OFF: The EPOD is switched off + * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in + * retention + * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off + * - EPOD_STATE_ON: Same as above, but with clock enabled */ -#ifndef __MACH_PRCMU_H -#define __MACH_PRCMU_H +#define EPOD_STATE_NO_CHANGE 0x00 +#define EPOD_STATE_OFF 0x01 +#define EPOD_STATE_RAMRET 0x02 +#define EPOD_STATE_ON_CLK_OFF 0x03 +#define EPOD_STATE_ON 0x04 +/* + * CLKOUT sources + */ +#define PRCMU_CLKSRC_CLK38M 0x00 +#define PRCMU_CLKSRC_ACLK 0x01 +#define PRCMU_CLKSRC_SYSCLK 0x02 +#define PRCMU_CLKSRC_LCDCLK 0x03 +#define PRCMU_CLKSRC_SDMMCCLK 0x04 +#define PRCMU_CLKSRC_TVCLK 0x05 +#define PRCMU_CLKSRC_TIMCLK 0x06 +#define PRCMU_CLKSRC_CLK009 0x07 +/* These are only valid for CLKOUT1: */ +#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 +#define PRCMU_CLKSRC_I2CCLK 0x41 +#define PRCMU_CLKSRC_MSP02CLK 0x42 +#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 +#define PRCMU_CLKSRC_HSIRXCLK 0x44 +#define PRCMU_CLKSRC_HSITXCLK 0x45 +#define PRCMU_CLKSRC_ARMCLKFIX 0x46 +#define PRCMU_CLKSRC_HDMICLK 0x47 + +/* + * Definitions for autonomous power management configuration. + */ + +#define PRCMU_AUTO_PM_OFF 0 +#define PRCMU_AUTO_PM_ON 1 + +#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0) +#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1) + +enum prcmu_auto_pm_policy { + PRCMU_AUTO_PM_POLICY_NO_CHANGE, + PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF, + PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF, + PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF, + PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF, +}; + +/** + * struct prcmu_auto_pm_config - Autonomous power management configuration. + * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON}) + * @sia_power_on: SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask) + * @sia_policy: SIA power policy. (enum prcmu_auto_pm_policy) + * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON}) + * @sva_power_on: SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask) + * @sva_policy: SVA power policy. (enum prcmu_auto_pm_policy) + */ +struct prcmu_auto_pm_config { + u8 sia_auto_pm_enable; + u8 sia_power_on; + u8 sia_policy; + u8 sva_auto_pm_enable; + u8 sva_power_on; + u8 sva_policy; +}; + +/** + * enum ddr_opp - DDR OPP states definition + * @DDR_100_OPP: The new DDR operating point is ddr100opp + * @DDR_50_OPP: The new DDR operating point is ddr50opp + * @DDR_25_OPP: The new DDR operating point is ddr25opp + */ +enum ddr_opp { + DDR_100_OPP = 0x00, + DDR_50_OPP = 0x01, + DDR_25_OPP = 0x02, +}; + +/* + * Clock identifiers. + */ +enum prcmu_clock { + PRCMU_SGACLK, + PRCMU_UARTCLK, + PRCMU_MSP02CLK, + PRCMU_MSP1CLK, + PRCMU_I2CCLK, + PRCMU_SDMMCCLK, + PRCMU_SLIMCLK, + PRCMU_PER1CLK, + PRCMU_PER2CLK, + PRCMU_PER3CLK, + PRCMU_PER5CLK, + PRCMU_PER6CLK, + PRCMU_PER7CLK, + PRCMU_LCDCLK, + PRCMU_BMLCLK, + PRCMU_HSITXCLK, + PRCMU_HSIRXCLK, + PRCMU_HDMICLK, + PRCMU_APEATCLK, + PRCMU_APETRACECLK, + PRCMU_MCDECLK, + PRCMU_IPI2CCLK, + PRCMU_DSIALTCLK, + PRCMU_DMACLK, + PRCMU_B2R2CLK, + PRCMU_TVCLK, + PRCMU_SSPCLK, + PRCMU_RNGCLK, + PRCMU_UICCCLK, + PRCMU_NUM_REG_CLOCKS, + PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, + PRCMU_TIMCLK, +}; + +/* + * Definitions for controlling ESRAM0 in deep sleep. + */ +#define ESRAM0_DEEP_SLEEP_STATE_OFF 1 +#define ESRAM0_DEEP_SLEEP_STATE_RET 2 + +#ifdef CONFIG_MFD_DB8500_PRCMU void __init prcmu_early_init(void); +int prcmu_set_display_clocks(void); +int prcmu_disable_dsipll(void); +int prcmu_enable_dsipll(void); +#else +static inline void __init prcmu_early_init(void) {} +#endif + +#ifdef CONFIG_MFD_DB8500_PRCMU + +int prcmu_set_rc_a2p(enum romcode_write); +enum romcode_read prcmu_get_rc_p2a(void); +enum ap_pwrst prcmu_get_xp70_current_state(void); +int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); + +void prcmu_enable_wakeups(u32 wakeups); +static inline void prcmu_disable_wakeups(void) +{ + prcmu_enable_wakeups(0); +} + +void prcmu_config_abb_event_readout(u32 abb_events); +void prcmu_get_abb_event_buffer(void __iomem **buf); +int prcmu_set_arm_opp(u8 opp); +int prcmu_get_arm_opp(void); +bool prcmu_has_arm_maxopp(void); +bool prcmu_is_u8400(void); +int prcmu_set_ape_opp(u8 opp); +int prcmu_get_ape_opp(void); +int prcmu_request_ape_opp_100_voltage(bool enable); +int prcmu_release_usb_wakeup_state(void); +int prcmu_set_ddr_opp(u8 opp); +int prcmu_get_ddr_opp(void); +unsigned long prcmu_qos_get_cpufreq_opp_delay(void); +void prcmu_qos_set_cpufreq_opp_delay(unsigned long); +/* NOTE! Use regulator framework instead */ +int prcmu_set_hwacc(u16 hw_acc_dev, u8 state); +int prcmu_set_epod(u16 epod_id, u8 epod_state); +void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, + struct prcmu_auto_pm_config *idle); +bool prcmu_is_auto_pm_enabled(void); + +int prcmu_config_clkout(u8 clkout, u8 source, u8 div); +int prcmu_request_clock(u8 clock, bool enable); +int prcmu_set_clock_divider(u8 clock, u8 divider); +int prcmu_config_esram0_deep_sleep(u8 state); +int prcmu_config_hotdog(u8 threshold); +int prcmu_config_hotmon(u8 low, u8 high); +int prcmu_start_temp_sense(u16 cycles32k); +int prcmu_stop_temp_sense(void); int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); -int prcmu_set_ape_opp(enum prcmu_ape_opp opp); -int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp); -int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp, - enum prcmu_cpu_opp cpu_opp); -enum prcmu_ape_opp prcmu_get_ape_opp(void); -int prcmu_get_cpu_opp(void); -bool prcmu_has_arm_maxopp(void); -#endif /* __MACH_PRCMU_H */ +void prcmu_ac_wake_req(void); +void prcmu_ac_sleep_req(void); +void prcmu_system_reset(u16 reset_code); +void prcmu_modem_reset(void); +bool prcmu_is_ac_wake_requested(void); +void prcmu_enable_spi2(void); +void prcmu_disable_spi2(void); + +#else /* !CONFIG_MFD_DB8500_PRCMU */ + +static inline int prcmu_set_rc_a2p(enum romcode_write code) +{ + return 0; +} + +static inline enum romcode_read prcmu_get_rc_p2a(void) +{ + return INIT; +} + +static inline enum ap_pwrst prcmu_get_xp70_current_state(void) +{ + return AP_EXECUTE; +} + +static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll) +{ + return 0; +} + +static inline void prcmu_enable_wakeups(u32 wakeups) {} + +static inline void prcmu_disable_wakeups(void) {} + +static inline void prcmu_config_abb_event_readout(u32 abb_events) {} + +static inline int prcmu_set_arm_opp(u8 opp) +{ + return 0; +} + +static inline int prcmu_get_arm_opp(void) +{ + return ARM_100_OPP; +} + +static bool prcmu_has_arm_maxopp(void) +{ + return false; +} + +static bool prcmu_is_u8400(void) +{ + return false; +} + +static inline int prcmu_set_ape_opp(u8 opp) +{ + return 0; +} + +static inline int prcmu_get_ape_opp(void) +{ + return APE_100_OPP; +} + +static inline int prcmu_request_ape_opp_100_voltage(bool enable) +{ + return 0; +} + +static inline int prcmu_release_usb_wakeup_state(void) +{ + return 0; +} + +static inline int prcmu_set_ddr_opp(u8 opp) +{ + return 0; +} + +static inline int prcmu_get_ddr_opp(void) +{ + return DDR_100_OPP; +} + +static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void) +{ + return 0; +} + +static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {} + +static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state) +{ + return 0; +} + +static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, + struct prcmu_auto_pm_config *idle) +{ +} + +static inline bool prcmu_is_auto_pm_enabled(void) +{ + return false; +} + +static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) +{ + return 0; +} + +static inline int prcmu_request_clock(u8 clock, bool enable) +{ + return 0; +} + +static inline int prcmu_set_clock_divider(u8 clock, u8 divider) +{ + return 0; +} + +int prcmu_config_esram0_deep_sleep(u8 state) +{ + return 0; +} + +static inline int prcmu_config_hotdog(u8 threshold) +{ + return 0; +} + +static inline int prcmu_config_hotmon(u8 low, u8 high) +{ + return 0; +} + +static inline int prcmu_start_temp_sense(u16 cycles32k) +{ + return 0; +} + +static inline int prcmu_stop_temp_sense(void) +{ + return 0; +} + +static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) +{ + return -ENOSYS; +} + +static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) +{ + return -ENOSYS; +} + +static inline void prcmu_ac_wake_req(void) {} + +static inline void prcmu_ac_sleep_req(void) {} + +static inline void prcmu_system_reset(u16 reset_code) {} + +static inline void prcmu_modem_reset(void) {} + +static inline bool prcmu_is_ac_wake_requested(void) +{ + return false; +} + +#ifndef CONFIG_UX500_SOC_DB5500 +static inline int prcmu_set_display_clocks(void) +{ + return 0; +} + +static inline int prcmu_disable_dsipll(void) +{ + return 0; +} + +static inline int prcmu_enable_dsipll(void) +{ + return 0; +} +#endif + +static inline int prcmu_enable_spi2(void) +{ + return 0; +} + +static inline int prcmu_disable_spi2(void) +{ + return 0; +} + +#endif /* !CONFIG_MFD_DB8500_PRCMU */ + +#ifdef CONFIG_UX500_PRCMU_QOS_POWER +int prcmu_qos_requirement(int pm_qos_class); +int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); +int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value); +void prcmu_qos_remove_requirement(int pm_qos_class, char *name); +int prcmu_qos_add_notifier(int prcmu_qos_class, + struct notifier_block *notifier); +int prcmu_qos_remove_notifier(int prcmu_qos_class, + struct notifier_block *notifier); +#else +static inline int prcmu_qos_requirement(int prcmu_qos_class) +{ + return 0; +} + +static inline int prcmu_qos_add_requirement(int prcmu_qos_class, + char *name, s32 value) +{ + return 0; +} + +static inline int prcmu_qos_update_requirement(int prcmu_qos_class, + char *name, s32 new_value) +{ + return 0; +} + +static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) +{ +} + +static inline int prcmu_qos_add_notifier(int prcmu_qos_class, + struct notifier_block *notifier) +{ + return 0; +} +static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, + struct notifier_block *notifier) +{ + return 0; +} + +#endif + +#endif /* __MFD_DB8500_PRCMU_H */ -- cgit v1.2.2 From 8317797ca657081ed81312ea3501f3a3d59d52e9 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 3 May 2011 18:14:48 +0200 Subject: mfd: add DB5500 PRCMU driver This adds the DB5500 PRCMU driver. Right now this one is pretty restricted in functionality, exposing a simple interface to send I2C messages. Acked-by: Samuel Ortiz Signed-off-by: Linus Walleij --- include/linux/mfd/db5500-prcmu.h | 45 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 include/linux/mfd/db5500-prcmu.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h new file mode 100644 index 000000000000..f0977986402c --- /dev/null +++ b/include/linux/mfd/db5500-prcmu.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * + * U5500 PRCMU API. + */ +#ifndef __MACH_PRCMU_U5500_H +#define __MACH_PRCMU_U5500_H + +#ifdef CONFIG_UX500_SOC_DB5500 + +void db5500_prcmu_early_init(void); + +int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); +int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); + +#else /* !CONFIG_UX500_SOC_DB5500 */ + +static inline void db5500_prcmu_early_init(void) +{ +} + +static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) +{ + return -ENOSYS; +} + +static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) +{ + return -ENOSYS; +} + +#endif /* CONFIG_UX500_SOC_DB5500 */ + +static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events) +{ +#ifdef CONFIG_MACH_U5500_SIMULATOR + return 0; +#else + return -1; +#endif +} + +#endif /* __MACH_PRCMU_U5500_H */ -- cgit v1.2.2 From 7311bef0697bcfbbcb898c3c22e61e23f203ae9d Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 11 May 2011 16:51:11 +0000 Subject: mmc: tmio: runtime suspend the controller, where possible The TMIO MMC controller cannot be powered off to save power, when no card is plugged in, because then it will not be able to detect a new card-insertion event. On some implementations, however, it is possible to switch to using another source to detect card insertion. This patch adds support for such implementations. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Chris Ball --- include/linux/mfd/tmio.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h index 8e70310ee945..5a90266c3a5a 100644 --- a/include/linux/mfd/tmio.h +++ b/include/linux/mfd/tmio.h @@ -4,6 +4,7 @@ #include #include #include +#include #define tmio_ioread8(addr) readb(addr) #define tmio_ioread16(addr) readw(addr) @@ -61,6 +62,12 @@ * Some controllers can support SDIO IRQ signalling. */ #define TMIO_MMC_SDIO_IRQ (1 << 2) +/* + * Some platforms can detect card insertion events with controller powered + * down, in which case they have to call tmio_mmc_cd_wakeup() to power up the + * controller and report the event to the driver. + */ +#define TMIO_MMC_HAS_COLD_CD (1 << 3) int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); @@ -82,11 +89,21 @@ struct tmio_mmc_data { unsigned long flags; u32 ocr_mask; /* available voltages */ struct tmio_mmc_dma *dma; + struct device *dev; + bool power; void (*set_pwr)(struct platform_device *host, int state); void (*set_clk_div)(struct platform_device *host, int state); int (*get_cd)(struct platform_device *host); }; +static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata) +{ + if (pdata && !pdata->power) { + pdata->power = true; + pm_runtime_get(pdata->dev); + } +} + /* * data for the NAND controller */ -- cgit v1.2.2 From eb8956074e7652e802be5f078080c704c2c87104 Mon Sep 17 00:00:00 2001 From: Samuel Ortiz Date: Wed, 6 Apr 2011 16:52:52 +0200 Subject: mfd: Add platform data pointer back Now that we have a way to pass MFD cells down to the sub drivers, we can gradually get rid of mfd_data by putting the platform pointer back in place. Signed-off-by: Samuel Ortiz --- include/linux/mfd/core.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h index aef23309a742..68c13e52a50c 100644 --- a/include/linux/mfd/core.h +++ b/include/linux/mfd/core.h @@ -36,6 +36,10 @@ struct mfd_cell { /* mfd_data can be used to pass data to client drivers */ void *mfd_data; + /* platform data passed to the sub devices drivers */ + void *platform_data; + size_t pdata_size; + /* * These resources can be specified relative to the parent device. * For accessing hardware you should use resources from the platform dev -- cgit v1.2.2 From 1f235a3785dbcfb324ff228048b859a3bd1e1a59 Mon Sep 17 00:00:00 2001 From: Samuel Ortiz Date: Wed, 6 Apr 2011 00:20:24 +0200 Subject: mfd: Use mfd cell platform_data for ab3550 cells platform bits With the addition of a platform device mfd_cell pointer, MFD drivers can go back to passing platform data back to their sub drivers. This allows for an mfd_cell->mfd_data removal and thus keep the sub drivers MFD agnostic. This is mostly needed for non MFD aware sub drivers. Acked-by: Linus Walleij Signed-off-by: Samuel Ortiz --- include/linux/mfd/abx500.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h index 7d9b6ae1c203..67bd6f7ecf32 100644 --- a/include/linux/mfd/abx500.h +++ b/include/linux/mfd/abx500.h @@ -186,6 +186,7 @@ struct abx500_init_settings { struct ab3550_platform_data { struct {unsigned int base; unsigned int count; } irq; void *dev_data[AB3550_NUM_DEVICES]; + size_t dev_data_sz[AB3550_NUM_DEVICES]; struct abx500_init_settings *init_settings; unsigned int init_settings_sz; }; -- cgit v1.2.2 From ba279f58c6148c1dc76265da98eb292e76c15a32 Mon Sep 17 00:00:00 2001 From: Samuel Ortiz Date: Fri, 8 Apr 2011 02:04:50 +0200 Subject: mfd: Remove mfd_data Cell pointers are passed through device->mfd_cell and platform data is passed through the MFD cell platform_data pointer. Signed-off-by: Samuel Ortiz --- include/linux/mfd/core.h | 21 --------------------- 1 file changed, 21 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h index 68c13e52a50c..4e76163dd862 100644 --- a/include/linux/mfd/core.h +++ b/include/linux/mfd/core.h @@ -33,9 +33,6 @@ struct mfd_cell { int (*suspend)(struct platform_device *dev); int (*resume)(struct platform_device *dev); - /* mfd_data can be used to pass data to client drivers */ - void *mfd_data; - /* platform data passed to the sub devices drivers */ void *platform_data; size_t pdata_size; @@ -93,24 +90,6 @@ static inline const struct mfd_cell *mfd_get_cell(struct platform_device *pdev) return pdev->mfd_cell; } -/* - * Given a platform device that's been created by mfd_add_devices(), fetch - * the .mfd_data entry from the mfd_cell that created it. - * Otherwise just return the platform_data pointer. - * This maintains compatibility with platform drivers whose devices aren't - * created by the mfd layer, and expect platform_data to contain what would've - * otherwise been in mfd_data. - */ -static inline void *mfd_get_data(struct platform_device *pdev) -{ - const struct mfd_cell *cell = mfd_get_cell(pdev); - - if (cell) - return cell->mfd_data; - else - return pdev->dev.platform_data; -} - extern int mfd_add_devices(struct device *parent, int id, struct mfd_cell *cells, int n_devs, struct resource *mem_base, -- cgit v1.2.2 From 8997619a045bef5d138f0f45141a398557f809e6 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Apr 2011 11:04:12 +0900 Subject: mfd: Remove compatibility interface for WM831x specific IRQ API The last user was removed in the merge window. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm831x/core.h | 26 -------------------------- 1 file changed, 26 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h index 903280d21866..0d515ee1c247 100644 --- a/include/linux/mfd/wm831x/core.h +++ b/include/linux/mfd/wm831x/core.h @@ -301,30 +301,4 @@ int wm831x_device_suspend(struct wm831x *wm831x); int wm831x_irq_init(struct wm831x *wm831x, int irq); void wm831x_irq_exit(struct wm831x *wm831x); -static inline int __must_check wm831x_request_irq(struct wm831x *wm831x, - unsigned int irq, - irq_handler_t handler, - unsigned long flags, - const char *name, - void *dev) -{ - return request_threaded_irq(irq, NULL, handler, flags, name, dev); -} - -static inline void wm831x_free_irq(struct wm831x *wm831x, - unsigned int irq, void *dev) -{ - free_irq(irq, dev); -} - -static inline void wm831x_disable_irq(struct wm831x *wm831x, int irq) -{ - disable_irq(irq); -} - -static inline void wm831x_enable_irq(struct wm831x *wm831x, int irq) -{ - enable_irq(irq); -} - #endif -- cgit v1.2.2 From 0b14c22ea1e0226d894df76176971d06e8886aa7 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 4 Apr 2011 11:04:42 +0900 Subject: mfd: Provide platform data for WM831x GPIO configuration Allow the GPIO mode of WM831x devices to be configured using platform data. Users may provide a table of GPIO register values in gpio_defaults[]. In order to allow 0 to be set explicitly out of range values are accepted and masked off, with a WM831X_GPIO_CONFIGURE define provided to set an out of range value. This can be used to configure higher numbered GPIOs or override values set in OTP for GPIOs configured using OTP. Signed-off-by: Mark Brown Signed-off-by: Samuel Ortiz --- include/linux/mfd/wm831x/pdata.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h index 632d1567a1b6..ff42d700293f 100644 --- a/include/linux/mfd/wm831x/pdata.h +++ b/include/linux/mfd/wm831x/pdata.h @@ -105,6 +105,9 @@ struct wm831x_watchdog_pdata { #define WM831X_MAX_LDO 11 #define WM831X_MAX_ISINK 2 +#define WM831X_GPIO_CONFIGURE 0x10000 +#define WM831X_GPIO_NUM 16 + struct wm831x_pdata { /** Used to distinguish multiple WM831x chips */ int wm831x_num; @@ -119,6 +122,7 @@ struct wm831x_pdata { int irq_base; int gpio_base; + int gpio_defaults[WM831X_GPIO_NUM]; struct wm831x_backlight_pdata *backlight; struct wm831x_backup_pdata *backup; struct wm831x_battery_pdata *battery; -- cgit v1.2.2 From cbdb53e1f33baf60ded045dc79cd0dd4e9705fa5 Mon Sep 17 00:00:00 2001 From: Abhijeet Dharmapurikar Date: Tue, 5 Apr 2011 14:40:52 -0700 Subject: mfd: Add Qualcomm PMIC 8921 core driver Add support for the Qualcomm PM8921 PMIC chip. The core driver will communicate with the PMIC chip via the MSM SSBI bus. Signed-off-by: Abhijeet Dharmapurikar Signed-off-by: Samuel Ortiz --- include/linux/mfd/pm8xxx/core.h | 71 +++++++++++++++++++++++++++++++++++++++ include/linux/mfd/pm8xxx/pm8921.h | 27 +++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 include/linux/mfd/pm8xxx/core.h create mode 100644 include/linux/mfd/pm8xxx/pm8921.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h new file mode 100644 index 000000000000..36ccb33332ed --- /dev/null +++ b/include/linux/mfd/pm8xxx/core.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * Qualcomm PMIC 8xxx driver header file + * + */ + +#ifndef __MFD_PM8XXX_CORE_H +#define __MFD_PM8XXX_CORE_H + +#include + +struct pm8xxx_drvdata { + int (*pmic_readb) (const struct device *dev, u16 addr, u8 *val); + int (*pmic_writeb) (const struct device *dev, u16 addr, u8 val); + int (*pmic_read_buf) (const struct device *dev, u16 addr, u8 *buf, + int n); + int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf, + int n); + void *pm_chip_data; +}; + +static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val) +{ + struct pm8xxx_drvdata *dd = dev_get_drvdata(dev); + + if (!dd) + return -EINVAL; + return dd->pmic_readb(dev, addr, val); +} + +static inline int pm8xxx_writeb(const struct device *dev, u16 addr, u8 val) +{ + struct pm8xxx_drvdata *dd = dev_get_drvdata(dev); + + if (!dd) + return -EINVAL; + return dd->pmic_writeb(dev, addr, val); +} + +static inline int pm8xxx_read_buf(const struct device *dev, u16 addr, u8 *buf, + int n) +{ + struct pm8xxx_drvdata *dd = dev_get_drvdata(dev); + + if (!dd) + return -EINVAL; + return dd->pmic_read_buf(dev, addr, buf, n); +} + +static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf, + int n) +{ + struct pm8xxx_drvdata *dd = dev_get_drvdata(dev); + + if (!dd) + return -EINVAL; + return dd->pmic_write_buf(dev, addr, buf, n); +} + +#endif diff --git a/include/linux/mfd/pm8xxx/pm8921.h b/include/linux/mfd/pm8xxx/pm8921.h new file mode 100644 index 000000000000..33fbe9c960a3 --- /dev/null +++ b/include/linux/mfd/pm8xxx/pm8921.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * Qualcomm PMIC 8921 driver header file + * + */ + +#ifndef __MFD_PM8921_H +#define __MFD_PM8921_H + +#include + +struct pm8921_platform_data { + int irq_base; +}; + +#endif -- cgit v1.2.2 From c013f0a56c56b88ac63c4037f2dfaaf2422fa863 Mon Sep 17 00:00:00 2001 From: Abhijeet Dharmapurikar Date: Tue, 5 Apr 2011 14:40:53 -0700 Subject: mfd: Add pm8xxx irq support Add support for the irq controller in Qualcomm 8xxx pmic. The 8xxx interrupt controller provides control for gpio and mpp configured as interrupts in addition to other subdevice interrupts. The interrupt controller also provides a way to read the real time status of an interrupt. This real time status is the only way one can get the input values of gpio and mpp lines. Signed-off-by: Abhijeet Dharmapurikar Signed-off-by: Samuel Ortiz --- include/linux/mfd/pm8xxx/core.h | 10 +++++++ include/linux/mfd/pm8xxx/irq.h | 59 +++++++++++++++++++++++++++++++++++++++ include/linux/mfd/pm8xxx/pm8921.h | 4 +++ 3 files changed, 73 insertions(+) create mode 100644 include/linux/mfd/pm8xxx/irq.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h index 36ccb33332ed..bd2f4f64e931 100644 --- a/include/linux/mfd/pm8xxx/core.h +++ b/include/linux/mfd/pm8xxx/core.h @@ -27,6 +27,7 @@ struct pm8xxx_drvdata { int n); int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf, int n); + int (*pmic_read_irq_stat) (const struct device *dev, int irq); void *pm_chip_data; }; @@ -68,4 +69,13 @@ static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf, return dd->pmic_write_buf(dev, addr, buf, n); } +static inline int pm8xxx_read_irq_stat(const struct device *dev, int irq) +{ + struct pm8xxx_drvdata *dd = dev_get_drvdata(dev); + + if (!dd) + return -EINVAL; + return dd->pmic_read_irq_stat(dev, irq); +} + #endif diff --git a/include/linux/mfd/pm8xxx/irq.h b/include/linux/mfd/pm8xxx/irq.h new file mode 100644 index 000000000000..4b21769f4483 --- /dev/null +++ b/include/linux/mfd/pm8xxx/irq.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * Qualcomm PMIC irq 8xxx driver header file + * + */ + +#ifndef __MFD_PM8XXX_IRQ_H +#define __MFD_PM8XXX_IRQ_H + +#include +#include + +struct pm8xxx_irq_core_data { + u32 rev; + int nirqs; +}; + +struct pm8xxx_irq_platform_data { + int irq_base; + struct pm8xxx_irq_core_data irq_cdata; + int devirq; + int irq_trigger_flag; +}; + +struct pm_irq_chip; + +#ifdef CONFIG_MFD_PM8XXX_IRQ +int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq); +struct pm_irq_chip * __devinit pm8xxx_irq_init(struct device *dev, + const struct pm8xxx_irq_platform_data *pdata); +int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip); +#else +static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq) +{ + return -ENXIO; +} +static inline struct pm_irq_chip * __devinit pm8xxx_irq_init( + const struct device *dev, + const struct pm8xxx_irq_platform_data *pdata) +{ + return ERR_PTR(-ENXIO); +} +static inline int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip) +{ + return -ENXIO; +} +#endif /* CONFIG_MFD_PM8XXX_IRQ */ +#endif /* __MFD_PM8XXX_IRQ_H */ diff --git a/include/linux/mfd/pm8xxx/pm8921.h b/include/linux/mfd/pm8xxx/pm8921.h index 33fbe9c960a3..d5517fd32d1b 100644 --- a/include/linux/mfd/pm8xxx/pm8921.h +++ b/include/linux/mfd/pm8xxx/pm8921.h @@ -19,9 +19,13 @@ #define __MFD_PM8921_H #include +#include + +#define PM8921_NR_IRQS 256 struct pm8921_platform_data { int irq_base; + struct pm8xxx_irq_platform_data *irq_pdata; }; #endif -- cgit v1.2.2 From 008b30408c40ede5985397e7daac45d30b375a01 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 6 May 2011 17:21:20 +0800 Subject: mfd: Add rtc support to 88pm860x Enable rtc function in 88pm860x PMIC. Signed-off-by: Haojian Zhuang Cc: Alessandro Zummo Signed-off-by: Samuel Ortiz --- include/linux/mfd/88pm860x.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h index 8fba7972ff5f..63b4fb8e3b6f 100644 --- a/include/linux/mfd/88pm860x.h +++ b/include/linux/mfd/88pm860x.h @@ -330,6 +330,11 @@ struct pm860x_led_pdata { unsigned long flags; }; +struct pm860x_rtc_pdata { + int (*sync)(unsigned int ticks); + int vrtc; +}; + struct pm860x_touch_pdata { int gpadc_prebias; int slot_cycle; @@ -349,6 +354,7 @@ struct pm860x_power_pdata { struct pm860x_platform_data { struct pm860x_backlight_pdata *backlight; struct pm860x_led_pdata *led; + struct pm860x_rtc_pdata *rtc; struct pm860x_touch_pdata *touch; struct pm860x_power_pdata *power; struct regulator_init_data *regulator; -- cgit v1.2.2 From 863dde5bfa3c48f459c6302daf64f94a11c7c1e5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 8 May 2011 00:54:45 +0200 Subject: mfd: Provide ab8500-core enumerators for chip cuts Since functionality in MFD cells may need to be adjusted according to chip revision, let's enumerate them and keep track of them. Signed-off-by: Linus Walleij Signed-off-by: Samuel Ortiz --- include/linux/mfd/abx500.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h index 67bd6f7ecf32..896b5e47f16e 100644 --- a/include/linux/mfd/abx500.h +++ b/include/linux/mfd/abx500.h @@ -34,6 +34,13 @@ #define AB5500_2_0 0x21 #define AB5500_2_1 0x22 +/* AB8500 CIDs*/ +#define AB8500_CUTEARLY 0x00 +#define AB8500_CUT1P0 0x10 +#define AB8500_CUT1P1 0x11 +#define AB8500_CUT2P0 0x20 +#define AB8500_CUT3P0 0x30 + /* * AB3100, EVENTA1, A2 and A3 event register flags * these are catenated into a single 32-bit flag in the code -- cgit v1.2.2 From 4a7c00cd94d4ca7061c481fe823a256e37436044 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 10 May 2011 08:59:23 +0300 Subject: mfd: Update twl4030-code maintainer e-mail address Signed-off-by: Peter Ujfalusi Signed-off-by: Samuel Ortiz --- include/linux/mfd/twl4030-codec.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/twl4030-codec.h b/include/linux/mfd/twl4030-codec.h index 2ec317c68e59..5cc16bbd1da1 100644 --- a/include/linux/mfd/twl4030-codec.h +++ b/include/linux/mfd/twl4030-codec.h @@ -1,7 +1,7 @@ /* * MFD driver for twl4030 codec submodule * - * Author: Peter Ujfalusi + * Author: Peter Ujfalusi * * Copyright: (C) 2009 Nokia Corporation * -- cgit v1.2.2 From 7d9e7e9fbd3041a0596394579d800788bbf94939 Mon Sep 17 00:00:00 2001 From: Paul Parsons Date: Fri, 13 May 2011 18:52:56 +0000 Subject: leds: Add ASIC3 LED support Add LED support for the HTC ASIC3. Underlying support is provided by the mfd/asic3 and leds/leds-asic3 drivers. An example configuration is provided by the pxa/hx4700 platform. Signed-off-by: Paul Parsons Signed-off-by: Samuel Ortiz --- include/linux/mfd/asic3.h | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h index de3c4ad19afb..d0dd3ebd8488 100644 --- a/include/linux/mfd/asic3.h +++ b/include/linux/mfd/asic3.h @@ -16,6 +16,13 @@ #include +struct led_classdev; +struct asic3_led { + const char *name; + const char *default_trigger; + struct led_classdev *cdev; +}; + struct asic3_platform_data { u16 *gpio_config; unsigned int gpio_config_num; @@ -23,6 +30,8 @@ struct asic3_platform_data { unsigned int irq_base; unsigned int gpio_base; + + struct asic3_led *leds; }; #define ASIC3_NUM_GPIO_BANKS 4 @@ -111,9 +120,9 @@ struct asic3_platform_data { #define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0) #define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0) #define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0) -#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 1, 0) -#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 1, 0) -#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 1, 0) +#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 0, 0) +#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 0, 0) +#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 0, 0) #define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0) #define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0) #define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0) @@ -152,6 +161,7 @@ struct asic3_platform_data { #define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */ #define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */ +#define ASIC3_NUM_LEDS 3 #define ASIC3_LED_0_Base 0x0700 #define ASIC3_LED_1_Base 0x0800 #define ASIC3_LED_2_Base 0x0900 @@ -293,4 +303,10 @@ struct asic3_platform_data { #define ASIC3_MAP_SIZE_32BIT 0x2000 #define ASIC3_MAP_SIZE_16BIT 0x1000 +/* Functions needed by leds-asic3 */ + +struct asic3; +extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val); +extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg); + #endif /* __ASIC3_H__ */ -- cgit v1.2.2 From 74e32d1b68f177f9c998041d789253df9c7f3575 Mon Sep 17 00:00:00 2001 From: Paul Parsons Date: Sun, 15 May 2011 14:13:11 +0000 Subject: mfd: Fix ASIC3 SD Host Controller Configuration size The size of the TC6380AF SD Host Controller Configuration area is 0x200 bytes (assuming registers are aligned on 32-bit boundaries), not 0x400 bytes. Source: Toshiba TC6380AF Specification sections 4.2 and 4.3.1 Signed-off-by: Paul Parsons Signed-off-by: Samuel Ortiz --- include/linux/mfd/asic3.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h index d0dd3ebd8488..ed793b77a1c5 100644 --- a/include/linux/mfd/asic3.h +++ b/include/linux/mfd/asic3.h @@ -297,6 +297,7 @@ struct asic3_platform_data { * *****************************************************************************/ #define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */ +#define ASIC3_SD_CONFIG_SIZE 0x0200 /* Assumes 32 bit addressing */ #define ASIC3_SD_CTRL_BASE 0x1000 #define ASIC3_SDIO_CTRL_BASE 0x1200 -- cgit v1.2.2 From 27c6750ec56fd3b22c670d9333d519a322996eb2 Mon Sep 17 00:00:00 2001 From: Graeme Gregory Date: Mon, 2 May 2011 16:19:46 -0500 Subject: MFD: TPS65910: Add new mfd device for TPS65910 The TPS65910 chip is a power management IC for multimedia and handheld devices. It contains the following components: - Regulators - GPIO controller - RTC The tps65910 core driver is registered as a platform driver and provides communication through I2C with the host device for the different components. Signed-off-by: Graeme Gregory Signed-off-by: Jorge Eduardo Candelaria Acked-by: Samuel Ortiz Signed-off-by: Liam Girdwood --- include/linux/mfd/tps65910.h | 753 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 753 insertions(+) create mode 100644 include/linux/mfd/tps65910.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h new file mode 100644 index 000000000000..fa1b029e5499 --- /dev/null +++ b/include/linux/mfd/tps65910.h @@ -0,0 +1,753 @@ +/* + * tps65910.h -- TI TPS6591x + * + * Copyright 2010-2011 Texas Instruments Inc. + * + * Author: Graeme Gregory + * Author: Jorge Eduardo Candelaria + * Author: Arnaud Deconinck + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __LINUX_MFD_TPS65910_H +#define __LINUX_MFD_TPS65910_H + +/* + * List of registers for component TPS65910 + * + */ + +#define TPS65910_SECONDS 0x0 +#define TPS65910_MINUTES 0x1 +#define TPS65910_HOURS 0x2 +#define TPS65910_DAYS 0x3 +#define TPS65910_MONTHS 0x4 +#define TPS65910_YEARS 0x5 +#define TPS65910_WEEKS 0x6 +#define TPS65910_ALARM_SECONDS 0x8 +#define TPS65910_ALARM_MINUTES 0x9 +#define TPS65910_ALARM_HOURS 0xA +#define TPS65910_ALARM_DAYS 0xB +#define TPS65910_ALARM_MONTHS 0xC +#define TPS65910_ALARM_YEARS 0xD +#define TPS65910_RTC_CTRL 0x10 +#define TPS65910_RTC_STATUS 0x11 +#define TPS65910_RTC_INTERRUPTS 0x12 +#define TPS65910_RTC_COMP_LSB 0x13 +#define TPS65910_RTC_COMP_MSB 0x14 +#define TPS65910_RTC_RES_PROG 0x15 +#define TPS65910_RTC_RESET_STATUS 0x16 +#define TPS65910_BCK1 0x17 +#define TPS65910_BCK2 0x18 +#define TPS65910_BCK3 0x19 +#define TPS65910_BCK4 0x1A +#define TPS65910_BCK5 0x1B +#define TPS65910_PUADEN 0x1C +#define TPS65910_REF 0x1D +#define TPS65910_VRTC 0x1E +#define TPS65910_VIO 0x20 +#define TPS65910_VDD1 0x21 +#define TPS65910_VDD1_OP 0x22 +#define TPS65910_VDD1_SR 0x23 +#define TPS65910_VDD2 0x24 +#define TPS65910_VDD2_OP 0x25 +#define TPS65910_VDD2_SR 0x26 +#define TPS65910_VDD3 0x27 +#define TPS65910_VDIG1 0x30 +#define TPS65910_VDIG2 0x31 +#define TPS65910_VAUX1 0x32 +#define TPS65910_VAUX2 0x33 +#define TPS65910_VAUX33 0x34 +#define TPS65910_VMMC 0x35 +#define TPS65910_VPLL 0x36 +#define TPS65910_VDAC 0x37 +#define TPS65910_THERM 0x38 +#define TPS65910_BBCH 0x39 +#define TPS65910_DCDCCTRL 0x3E +#define TPS65910_DEVCTRL 0x3F +#define TPS65910_DEVCTRL2 0x40 +#define TPS65910_SLEEP_KEEP_LDO_ON 0x41 +#define TPS65910_SLEEP_KEEP_RES_ON 0x42 +#define TPS65910_SLEEP_SET_LDO_OFF 0x43 +#define TPS65910_SLEEP_SET_RES_OFF 0x44 +#define TPS65910_EN1_LDO_ASS 0x45 +#define TPS65910_EN1_SMPS_ASS 0x46 +#define TPS65910_EN2_LDO_ASS 0x47 +#define TPS65910_EN2_SMPS_ASS 0x48 +#define TPS65910_EN3_LDO_ASS 0x49 +#define TPS65910_SPARE 0x4A +#define TPS65910_INT_STS 0x50 +#define TPS65910_INT_MSK 0x51 +#define TPS65910_INT_STS2 0x52 +#define TPS65910_INT_MSK2 0x53 +#define TPS65910_INT_STS3 0x54 +#define TPS65910_INT_MSK3 0x55 +#define TPS65910_GPIO0 0x60 +#define TPS65910_GPIO1 0x61 +#define TPS65910_GPIO2 0x62 +#define TPS65910_GPIO3 0x63 +#define TPS65910_GPIO4 0x64 +#define TPS65910_GPIO5 0x65 +#define TPS65910_JTAGVERNUM 0x80 +#define TPS65910_MAX_REGISTER 0x80 + +/* + * List of register bitfields for component TPS65910 + * + */ + + +/*Register BCK1 (0x80) register.RegisterDescription */ +#define BCK1_BCKUP_MASK 0xFF +#define BCK1_BCKUP_SHIFT 0 + + +/*Register BCK2 (0x80) register.RegisterDescription */ +#define BCK2_BCKUP_MASK 0xFF +#define BCK2_BCKUP_SHIFT 0 + + +/*Register BCK3 (0x80) register.RegisterDescription */ +#define BCK3_BCKUP_MASK 0xFF +#define BCK3_BCKUP_SHIFT 0 + + +/*Register BCK4 (0x80) register.RegisterDescription */ +#define BCK4_BCKUP_MASK 0xFF +#define BCK4_BCKUP_SHIFT 0 + + +/*Register BCK5 (0x80) register.RegisterDescription */ +#define BCK5_BCKUP_MASK 0xFF +#define BCK5_BCKUP_SHIFT 0 + + +/*Register PUADEN (0x80) register.RegisterDescription */ +#define PUADEN_EN3P_MASK 0x80 +#define PUADEN_EN3P_SHIFT 7 +#define PUADEN_I2CCTLP_MASK 0x40 +#define PUADEN_I2CCTLP_SHIFT 6 +#define PUADEN_I2CSRP_MASK 0x20 +#define PUADEN_I2CSRP_SHIFT 5 +#define PUADEN_PWRONP_MASK 0x10 +#define PUADEN_PWRONP_SHIFT 4 +#define PUADEN_SLEEPP_MASK 0x08 +#define PUADEN_SLEEPP_SHIFT 3 +#define PUADEN_PWRHOLDP_MASK 0x04 +#define PUADEN_PWRHOLDP_SHIFT 2 +#define PUADEN_BOOT1P_MASK 0x02 +#define PUADEN_BOOT1P_SHIFT 1 +#define PUADEN_BOOT0P_MASK 0x01 +#define PUADEN_BOOT0P_SHIFT 0 + + +/*Register REF (0x80) register.RegisterDescription */ +#define REF_VMBCH_SEL_MASK 0x0C +#define REF_VMBCH_SEL_SHIFT 2 +#define REF_ST_MASK 0x03 +#define REF_ST_SHIFT 0 + + +/*Register VRTC (0x80) register.RegisterDescription */ +#define VRTC_VRTC_OFFMASK_MASK 0x08 +#define VRTC_VRTC_OFFMASK_SHIFT 3 +#define VRTC_ST_MASK 0x03 +#define VRTC_ST_SHIFT 0 + + +/*Register VIO (0x80) register.RegisterDescription */ +#define VIO_ILMAX_MASK 0xC0 +#define VIO_ILMAX_SHIFT 6 +#define VIO_SEL_MASK 0x0C +#define VIO_SEL_SHIFT 2 +#define VIO_ST_MASK 0x03 +#define VIO_ST_SHIFT 0 + + +/*Register VDD1 (0x80) register.RegisterDescription */ +#define VDD1_VGAIN_SEL_MASK 0xC0 +#define VDD1_VGAIN_SEL_SHIFT 6 +#define VDD1_ILMAX_MASK 0x20 +#define VDD1_ILMAX_SHIFT 5 +#define VDD1_TSTEP_MASK 0x1C +#define VDD1_TSTEP_SHIFT 2 +#define VDD1_ST_MASK 0x03 +#define VDD1_ST_SHIFT 0 + + +/*Register VDD1_OP (0x80) register.RegisterDescription */ +#define VDD1_OP_CMD_MASK 0x80 +#define VDD1_OP_CMD_SHIFT 7 +#define VDD1_OP_SEL_MASK 0x7F +#define VDD1_OP_SEL_SHIFT 0 + + +/*Register VDD1_SR (0x80) register.RegisterDescription */ +#define VDD1_SR_SEL_MASK 0x7F +#define VDD1_SR_SEL_SHIFT 0 + + +/*Register VDD2 (0x80) register.RegisterDescription */ +#define VDD2_VGAIN_SEL_MASK 0xC0 +#define VDD2_VGAIN_SEL_SHIFT 6 +#define VDD2_ILMAX_MASK 0x20 +#define VDD2_ILMAX_SHIFT 5 +#define VDD2_TSTEP_MASK 0x1C +#define VDD2_TSTEP_SHIFT 2 +#define VDD2_ST_MASK 0x03 +#define VDD2_ST_SHIFT 0 + + +/*Register VDD2_OP (0x80) register.RegisterDescription */ +#define VDD2_OP_CMD_MASK 0x80 +#define VDD2_OP_CMD_SHIFT 7 +#define VDD2_OP_SEL_MASK 0x7F +#define VDD2_OP_SEL_SHIFT 0 + + +/*Register VDD2_SR (0x80) register.RegisterDescription */ +#define VDD2_SR_SEL_MASK 0x7F +#define VDD2_SR_SEL_SHIFT 0 + + +/*Register VDD3 (0x80) register.RegisterDescription */ +#define VDD3_CKINEN_MASK 0x04 +#define VDD3_CKINEN_SHIFT 2 +#define VDD3_ST_MASK 0x03 +#define VDD3_ST_SHIFT 0 + + +/*Register VDIG1 (0x80) register.RegisterDescription */ +#define VDIG1_SEL_MASK 0x0C +#define VDIG1_SEL_SHIFT 2 +#define VDIG1_ST_MASK 0x03 +#define VDIG1_ST_SHIFT 0 + + +/*Register VDIG2 (0x80) register.RegisterDescription */ +#define VDIG2_SEL_MASK 0x0C +#define VDIG2_SEL_SHIFT 2 +#define VDIG2_ST_MASK 0x03 +#define VDIG2_ST_SHIFT 0 + + +/*Register VAUX1 (0x80) register.RegisterDescription */ +#define VAUX1_SEL_MASK 0x0C +#define VAUX1_SEL_SHIFT 2 +#define VAUX1_ST_MASK 0x03 +#define VAUX1_ST_SHIFT 0 + + +/*Register VAUX2 (0x80) register.RegisterDescription */ +#define VAUX2_SEL_MASK 0x0C +#define VAUX2_SEL_SHIFT 2 +#define VAUX2_ST_MASK 0x03 +#define VAUX2_ST_SHIFT 0 + + +/*Register VAUX33 (0x80) register.RegisterDescription */ +#define VAUX33_SEL_MASK 0x0C +#define VAUX33_SEL_SHIFT 2 +#define VAUX33_ST_MASK 0x03 +#define VAUX33_ST_SHIFT 0 + + +/*Register VMMC (0x80) register.RegisterDescription */ +#define VMMC_SEL_MASK 0x0C +#define VMMC_SEL_SHIFT 2 +#define VMMC_ST_MASK 0x03 +#define VMMC_ST_SHIFT 0 + + +/*Register VPLL (0x80) register.RegisterDescription */ +#define VPLL_SEL_MASK 0x0C +#define VPLL_SEL_SHIFT 2 +#define VPLL_ST_MASK 0x03 +#define VPLL_ST_SHIFT 0 + + +/*Register VDAC (0x80) register.RegisterDescription */ +#define VDAC_SEL_MASK 0x0C +#define VDAC_SEL_SHIFT 2 +#define VDAC_ST_MASK 0x03 +#define VDAC_ST_SHIFT 0 + + +/*Register THERM (0x80) register.RegisterDescription */ +#define THERM_THERM_HD_MASK 0x20 +#define THERM_THERM_HD_SHIFT 5 +#define THERM_THERM_TS_MASK 0x10 +#define THERM_THERM_TS_SHIFT 4 +#define THERM_THERM_HDSEL_MASK 0x0C +#define THERM_THERM_HDSEL_SHIFT 2 +#define THERM_RSVD1_MASK 0x02 +#define THERM_RSVD1_SHIFT 1 +#define THERM_THERM_STATE_MASK 0x01 +#define THERM_THERM_STATE_SHIFT 0 + + +/*Register BBCH (0x80) register.RegisterDescription */ +#define BBCH_BBSEL_MASK 0x06 +#define BBCH_BBSEL_SHIFT 1 +#define BBCH_BBCHEN_MASK 0x01 +#define BBCH_BBCHEN_SHIFT 0 + + +/*Register DCDCCTRL (0x80) register.RegisterDescription */ +#define DCDCCTRL_VDD2_PSKIP_MASK 0x20 +#define DCDCCTRL_VDD2_PSKIP_SHIFT 5 +#define DCDCCTRL_VDD1_PSKIP_MASK 0x10 +#define DCDCCTRL_VDD1_PSKIP_SHIFT 4 +#define DCDCCTRL_VIO_PSKIP_MASK 0x08 +#define DCDCCTRL_VIO_PSKIP_SHIFT 3 +#define DCDCCTRL_DCDCCKEXT_MASK 0x04 +#define DCDCCTRL_DCDCCKEXT_SHIFT 2 +#define DCDCCTRL_DCDCCKSYNC_MASK 0x03 +#define DCDCCTRL_DCDCCKSYNC_SHIFT 0 + + +/*Register DEVCTRL (0x80) register.RegisterDescription */ +#define DEVCTRL_RTC_PWDN_MASK 0x40 +#define DEVCTRL_RTC_PWDN_SHIFT 6 +#define DEVCTRL_CK32K_CTRL_MASK 0x20 +#define DEVCTRL_CK32K_CTRL_SHIFT 5 +#define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10 +#define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4 +#define DEVCTRL_DEV_OFF_RST_MASK 0x08 +#define DEVCTRL_DEV_OFF_RST_SHIFT 3 +#define DEVCTRL_DEV_ON_MASK 0x04 +#define DEVCTRL_DEV_ON_SHIFT 2 +#define DEVCTRL_DEV_SLP_MASK 0x02 +#define DEVCTRL_DEV_SLP_SHIFT 1 +#define DEVCTRL_DEV_OFF_MASK 0x01 +#define DEVCTRL_DEV_OFF_SHIFT 0 + + +/*Register DEVCTRL2 (0x80) register.RegisterDescription */ +#define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 +#define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 +#define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 +#define DEVCTRL2_SLEEPSIG_POL_SHIFT 3 +#define DEVCTRL2_PWON_LP_OFF_MASK 0x04 +#define DEVCTRL2_PWON_LP_OFF_SHIFT 2 +#define DEVCTRL2_PWON_LP_RST_MASK 0x02 +#define DEVCTRL2_PWON_LP_RST_SHIFT 1 +#define DEVCTRL2_IT_POL_MASK 0x01 +#define DEVCTRL2_IT_POL_SHIFT 0 + + +/*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ +#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80 +#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7 +#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40 +#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6 +#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20 +#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5 +#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10 +#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4 +#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08 +#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3 +#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04 +#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2 +#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02 +#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1 +#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01 +#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0 + + +/*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ +#define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80 +#define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7 +#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40 +#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6 +#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20 +#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5 +#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10 +#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4 +#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08 +#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3 +#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04 +#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2 +#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02 +#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1 +#define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01 +#define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0 + + +/*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ +#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80 +#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7 +#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40 +#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6 +#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20 +#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5 +#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10 +#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4 +#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08 +#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3 +#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04 +#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2 +#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02 +#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1 +#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01 +#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0 + + +/*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ +#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80 +#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7 +#define SLEEP_SET_RES_OFF_RSVD_MASK 0x60 +#define SLEEP_SET_RES_OFF_RSVD_SHIFT 5 +#define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10 +#define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4 +#define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08 +#define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3 +#define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04 +#define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2 +#define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02 +#define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1 +#define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01 +#define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0 + + +/*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ +#define EN1_LDO_ASS_VDAC_EN1_MASK 0x80 +#define EN1_LDO_ASS_VDAC_EN1_SHIFT 7 +#define EN1_LDO_ASS_VPLL_EN1_MASK 0x40 +#define EN1_LDO_ASS_VPLL_EN1_SHIFT 6 +#define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20 +#define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5 +#define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10 +#define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4 +#define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08 +#define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3 +#define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04 +#define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2 +#define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02 +#define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1 +#define EN1_LDO_ASS_VMMC_EN1_MASK 0x01 +#define EN1_LDO_ASS_VMMC_EN1_SHIFT 0 + + +/*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ +#define EN1_SMPS_ASS_RSVD_MASK 0xE0 +#define EN1_SMPS_ASS_RSVD_SHIFT 5 +#define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10 +#define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4 +#define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08 +#define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3 +#define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04 +#define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2 +#define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02 +#define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1 +#define EN1_SMPS_ASS_VIO_EN1_MASK 0x01 +#define EN1_SMPS_ASS_VIO_EN1_SHIFT 0 + + +/*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ +#define EN2_LDO_ASS_VDAC_EN2_MASK 0x80 +#define EN2_LDO_ASS_VDAC_EN2_SHIFT 7 +#define EN2_LDO_ASS_VPLL_EN2_MASK 0x40 +#define EN2_LDO_ASS_VPLL_EN2_SHIFT 6 +#define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20 +#define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5 +#define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10 +#define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4 +#define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08 +#define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3 +#define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04 +#define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2 +#define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02 +#define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1 +#define EN2_LDO_ASS_VMMC_EN2_MASK 0x01 +#define EN2_LDO_ASS_VMMC_EN2_SHIFT 0 + + +/*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ +#define EN2_SMPS_ASS_RSVD_MASK 0xE0 +#define EN2_SMPS_ASS_RSVD_SHIFT 5 +#define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10 +#define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4 +#define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08 +#define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3 +#define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04 +#define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2 +#define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02 +#define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1 +#define EN2_SMPS_ASS_VIO_EN2_MASK 0x01 +#define EN2_SMPS_ASS_VIO_EN2_SHIFT 0 + + +/*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ +#define EN3_LDO_ASS_VDAC_EN3_MASK 0x80 +#define EN3_LDO_ASS_VDAC_EN3_SHIFT 7 +#define EN3_LDO_ASS_VPLL_EN3_MASK 0x40 +#define EN3_LDO_ASS_VPLL_EN3_SHIFT 6 +#define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20 +#define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5 +#define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10 +#define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4 +#define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08 +#define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3 +#define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04 +#define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2 +#define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02 +#define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1 +#define EN3_LDO_ASS_VMMC_EN3_MASK 0x01 +#define EN3_LDO_ASS_VMMC_EN3_SHIFT 0 + + +/*Register SPARE (0x80) register.RegisterDescription */ +#define SPARE_SPARE_MASK 0xFF +#define SPARE_SPARE_SHIFT 0 + + +/*Register INT_STS (0x80) register.RegisterDescription */ +#define INT_STS_RTC_PERIOD_IT_MASK 0x80 +#define INT_STS_RTC_PERIOD_IT_SHIFT 7 +#define INT_STS_RTC_ALARM_IT_MASK 0x40 +#define INT_STS_RTC_ALARM_IT_SHIFT 6 +#define INT_STS_HOTDIE_IT_MASK 0x20 +#define INT_STS_HOTDIE_IT_SHIFT 5 +#define INT_STS_PWRHOLD_IT_MASK 0x10 +#define INT_STS_PWRHOLD_IT_SHIFT 4 +#define INT_STS_PWRON_LP_IT_MASK 0x08 +#define INT_STS_PWRON_LP_IT_SHIFT 3 +#define INT_STS_PWRON_IT_MASK 0x04 +#define INT_STS_PWRON_IT_SHIFT 2 +#define INT_STS_VMBHI_IT_MASK 0x02 +#define INT_STS_VMBHI_IT_SHIFT 1 +#define INT_STS_VMBDCH_IT_MASK 0x01 +#define INT_STS_VMBDCH_IT_SHIFT 0 + + +/*Register INT_MSK (0x80) register.RegisterDescription */ +#define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 +#define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 +#define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 +#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 +#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 +#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 +#define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 +#define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 +#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 +#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 +#define INT_MSK_PWRON_IT_MSK_MASK 0x04 +#define INT_MSK_PWRON_IT_MSK_SHIFT 2 +#define INT_MSK_VMBHI_IT_MSK_MASK 0x02 +#define INT_MSK_VMBHI_IT_MSK_SHIFT 1 +#define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 +#define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 + + +/*Register INT_STS2 (0x80) register.RegisterDescription */ +#define INT_STS2_GPIO3_F_IT_MASK 0x80 +#define INT_STS2_GPIO3_F_IT_SHIFT 7 +#define INT_STS2_GPIO3_R_IT_MASK 0x40 +#define INT_STS2_GPIO3_R_IT_SHIFT 6 +#define INT_STS2_GPIO2_F_IT_MASK 0x20 +#define INT_STS2_GPIO2_F_IT_SHIFT 5 +#define INT_STS2_GPIO2_R_IT_MASK 0x10 +#define INT_STS2_GPIO2_R_IT_SHIFT 4 +#define INT_STS2_GPIO1_F_IT_MASK 0x08 +#define INT_STS2_GPIO1_F_IT_SHIFT 3 +#define INT_STS2_GPIO1_R_IT_MASK 0x04 +#define INT_STS2_GPIO1_R_IT_SHIFT 2 +#define INT_STS2_GPIO0_F_IT_MASK 0x02 +#define INT_STS2_GPIO0_F_IT_SHIFT 1 +#define INT_STS2_GPIO0_R_IT_MASK 0x01 +#define INT_STS2_GPIO0_R_IT_SHIFT 0 + + +/*Register INT_MSK2 (0x80) register.RegisterDescription */ +#define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80 +#define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7 +#define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40 +#define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6 +#define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20 +#define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5 +#define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10 +#define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4 +#define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08 +#define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3 +#define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04 +#define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2 +#define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 +#define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1 +#define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 +#define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0 + + +/*Register INT_STS3 (0x80) register.RegisterDescription */ +#define INT_STS3_GPIO5_F_IT_MASK 0x08 +#define INT_STS3_GPIO5_F_IT_SHIFT 3 +#define INT_STS3_GPIO5_R_IT_MASK 0x04 +#define INT_STS3_GPIO5_R_IT_SHIFT 2 +#define INT_STS3_GPIO4_F_IT_MASK 0x02 +#define INT_STS3_GPIO4_F_IT_SHIFT 1 +#define INT_STS3_GPIO4_R_IT_MASK 0x01 +#define INT_STS3_GPIO4_R_IT_SHIFT 0 + + +/*Register INT_MSK3 (0x80) register.RegisterDescription */ +#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 +#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 +#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 +#define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2 +#define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02 +#define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1 +#define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01 +#define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 + + +/*Register GPIO0 (0x80) register.RegisterDescription */ +#define GPIO0_GPIO_DEB_MASK 0x10 +#define GPIO0_GPIO_DEB_SHIFT 4 +#define GPIO0_GPIO_PUEN_MASK 0x08 +#define GPIO0_GPIO_PUEN_SHIFT 3 +#define GPIO0_GPIO_CFG_MASK 0x04 +#define GPIO0_GPIO_CFG_SHIFT 2 +#define GPIO0_GPIO_STS_MASK 0x02 +#define GPIO0_GPIO_STS_SHIFT 1 +#define GPIO0_GPIO_SET_MASK 0x01 +#define GPIO0_GPIO_SET_SHIFT 0 + + +/*Register GPIO1 (0x80) register.RegisterDescription */ +#define GPIO1_GPIO_DEB_MASK 0x10 +#define GPIO1_GPIO_DEB_SHIFT 4 +#define GPIO1_GPIO_PUEN_MASK 0x08 +#define GPIO1_GPIO_PUEN_SHIFT 3 +#define GPIO1_GPIO_CFG_MASK 0x04 +#define GPIO1_GPIO_CFG_SHIFT 2 +#define GPIO1_GPIO_STS_MASK 0x02 +#define GPIO1_GPIO_STS_SHIFT 1 +#define GPIO1_GPIO_SET_MASK 0x01 +#define GPIO1_GPIO_SET_SHIFT 0 + + +/*Register GPIO2 (0x80) register.RegisterDescription */ +#define GPIO2_GPIO_DEB_MASK 0x10 +#define GPIO2_GPIO_DEB_SHIFT 4 +#define GPIO2_GPIO_PUEN_MASK 0x08 +#define GPIO2_GPIO_PUEN_SHIFT 3 +#define GPIO2_GPIO_CFG_MASK 0x04 +#define GPIO2_GPIO_CFG_SHIFT 2 +#define GPIO2_GPIO_STS_MASK 0x02 +#define GPIO2_GPIO_STS_SHIFT 1 +#define GPIO2_GPIO_SET_MASK 0x01 +#define GPIO2_GPIO_SET_SHIFT 0 + + +/*Register GPIO3 (0x80) register.RegisterDescription */ +#define GPIO3_GPIO_DEB_MASK 0x10 +#define GPIO3_GPIO_DEB_SHIFT 4 +#define GPIO3_GPIO_PUEN_MASK 0x08 +#define GPIO3_GPIO_PUEN_SHIFT 3 +#define GPIO3_GPIO_CFG_MASK 0x04 +#define GPIO3_GPIO_CFG_SHIFT 2 +#define GPIO3_GPIO_STS_MASK 0x02 +#define GPIO3_GPIO_STS_SHIFT 1 +#define GPIO3_GPIO_SET_MASK 0x01 +#define GPIO3_GPIO_SET_SHIFT 0 + + +/*Register GPIO4 (0x80) register.RegisterDescription */ +#define GPIO4_GPIO_DEB_MASK 0x10 +#define GPIO4_GPIO_DEB_SHIFT 4 +#define GPIO4_GPIO_PUEN_MASK 0x08 +#define GPIO4_GPIO_PUEN_SHIFT 3 +#define GPIO4_GPIO_CFG_MASK 0x04 +#define GPIO4_GPIO_CFG_SHIFT 2 +#define GPIO4_GPIO_STS_MASK 0x02 +#define GPIO4_GPIO_STS_SHIFT 1 +#define GPIO4_GPIO_SET_MASK 0x01 +#define GPIO4_GPIO_SET_SHIFT 0 + + +/*Register GPIO5 (0x80) register.RegisterDescription */ +#define GPIO5_GPIO_DEB_MASK 0x10 +#define GPIO5_GPIO_DEB_SHIFT 4 +#define GPIO5_GPIO_PUEN_MASK 0x08 +#define GPIO5_GPIO_PUEN_SHIFT 3 +#define GPIO5_GPIO_CFG_MASK 0x04 +#define GPIO5_GPIO_CFG_SHIFT 2 +#define GPIO5_GPIO_STS_MASK 0x02 +#define GPIO5_GPIO_STS_SHIFT 1 +#define GPIO5_GPIO_SET_MASK 0x01 +#define GPIO5_GPIO_SET_SHIFT 0 + + +/*Register JTAGVERNUM (0x80) register.RegisterDescription */ +#define JTAGVERNUM_VERNUM_MASK 0x0F +#define JTAGVERNUM_VERNUM_SHIFT 0 + + +/* IRQ Definitions */ +#define TPS65910_IRQ_VBAT_VMBDCH 0 +#define TPS65910_IRQ_VBAT_VMHI 1 +#define TPS65910_IRQ_PWRON 2 +#define TPS65910_IRQ_PWRON_LP 3 +#define TPS65910_IRQ_PWRHOLD 4 +#define TPS65910_IRQ_HOTDIE 5 +#define TPS65910_IRQ_RTC_ALARM 6 +#define TPS65910_IRQ_RTC_PERIOD 7 +#define TPS65910_IRQ_GPIO_R 8 +#define TPS65910_IRQ_GPIO_F 9 +#define TPS65910_NUM_IRQ 10 + +/* GPIO Register Definitions */ +#define TPS65910_GPIO_DEB BIT(2) +#define TPS65910_GPIO_PUEN BIT(3) +#define TPS65910_GPIO_CFG BIT(2) +#define TPS65910_GPIO_STS BIT(1) +#define TPS65910_GPIO_SET BIT(0) + +/** + * struct tps65910_board + * Board platform data may be used to initialize regulators. + */ + +struct tps65910_board { + struct regulator_init_data *tps65910_pmic_init_data; +}; + +/** + * struct tps65910 - tps65910 sub-driver chip access routines + */ + +struct tps65910 { + struct device *dev; + struct i2c_client *i2c_client; + struct mutex io_mutex; + int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest); + int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src); + + /* Client devices */ + struct tps65910_pmic *pmic; + struct tps65910_rtc *rtc; + struct tps65910_power *power; + + /* GPIO Handling */ + struct gpio_chip gpio; + + /* IRQ Handling */ + struct mutex irq_lock; + int chip_irq; + int irq_base; + u16 irq_mask; +}; + +struct tps65910_platform_data { + int irq_base; +}; + +int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask); +int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask); + +#endif /* __LINUX_MFD_TPS65910_H */ -- cgit v1.2.2 From 2537df722d338ab687d7ed91dc589265c0d14aec Mon Sep 17 00:00:00 2001 From: Graeme Gregory Date: Mon, 2 May 2011 16:19:52 -0500 Subject: TPS65910: GPIO: Add GPIO driver TPS65910 has one configurable GPIO that can be used for several purposes. Subsequent versions of the TPS chip support more than one GPIO. Signed-off-by: Graeme Gregory Signed-off-by: Jorge Eduardo Candelaria Acked-by: Grant Likely Signed-off-by: Liam Girdwood --- include/linux/mfd/tps65910.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index fa1b029e5499..0e01d504ab58 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -714,6 +714,7 @@ */ struct tps65910_board { + int gpio_base; struct regulator_init_data *tps65910_pmic_init_data; }; @@ -749,5 +750,6 @@ struct tps65910_platform_data { int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask); int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask); +void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); #endif /* __LINUX_MFD_TPS65910_H */ -- cgit v1.2.2 From e3471bdc2784ee20a0d636c5904200c2d1148ef9 Mon Sep 17 00:00:00 2001 From: Graeme Gregory Date: Mon, 2 May 2011 16:20:04 -0500 Subject: TPS65910: IRQ: Add interrupt controller This module controls the interrupt handling for the tps chip. The interrupt sources are the following: - GPIO falling/rising edge detection - Battery voltage below/above threshold - PWRON signal - PWRHOLD signal - Temperature detection - RTC alarm and periodic event Signed-off-by: Graeme Gregory Signed-off-by: Jorge Eduardo Candelaria Reviewed-by: Mark Brown Acked-by: Samuel Ortiz Signed-off-by: Liam Girdwood --- include/linux/mfd/tps65910.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 0e01d504ab58..8afe91c85587 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -715,6 +715,8 @@ struct tps65910_board { int gpio_base; + int irq; + int irq_base; struct regulator_init_data *tps65910_pmic_init_data; }; @@ -745,11 +747,14 @@ struct tps65910 { }; struct tps65910_platform_data { + int irq; int irq_base; }; int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask); int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask); void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); +int tps65910_irq_init(struct tps65910 *tps65910, int irq, + struct tps65910_platform_data *pdata); #endif /* __LINUX_MFD_TPS65910_H */ -- cgit v1.2.2 From 518fb721de3685c8326e72746151b534a241feda Mon Sep 17 00:00:00 2001 From: Graeme Gregory Date: Mon, 2 May 2011 16:20:08 -0500 Subject: TPS65910: Add tps65910 regulator driver The regulator module consists of 3 DCDCs and 8 LDOs. The output voltages are configurable and are meant to supply power to the main processor and other components Signed-off-by: Graeme Gregory Signed-off-by: Jorge Eduardo Candelaria Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- include/linux/mfd/tps65910.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 8afe91c85587..be08a0c7e7de 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -215,12 +215,26 @@ #define VDD2_SR_SEL_SHIFT 0 +/*Registers VDD1, VDD2 voltage values definitions */ +#define VDD1_2_NUM_VOLTS 73 +#define VDD1_2_MIN_VOLT 6000 +#define VDD1_2_OFFSET 125 + + /*Register VDD3 (0x80) register.RegisterDescription */ #define VDD3_CKINEN_MASK 0x04 #define VDD3_CKINEN_SHIFT 2 #define VDD3_ST_MASK 0x03 #define VDD3_ST_SHIFT 0 +/*Registers VDIG (0x80) to VDAC register.RegisterDescription */ +#define LDO_SEL_MASK 0x0C +#define LDO_SEL_SHIFT 2 +#define LDO_ST_MASK 0x03 +#define LDO_ST_SHIFT 0 +#define LDO_ST_ON_BIT 0x01 +#define LDO_ST_MODE_BIT 0x02 + /*Register VDIG1 (0x80) register.RegisterDescription */ #define VDIG1_SEL_MASK 0x0C -- cgit v1.2.2 From ecb9c4f5956afa2ca0a20a1f99932b9ff81de854 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Mon, 16 May 2011 18:20:34 +0800 Subject: regulator: Remove MAX8997_REG_BUCK1DVS/MAX8997_REG_BUCK2DVS/MAX8997_REG_BUCK5DVS macros In current implementation, the original macro implementation assumes the caller pass the parameter starting from 1 (to match the register names in datasheet). Thus we have unneeded plus one then minus one operations when using MAX8997_REG_BUCK1DVS/MAX8997_REG_BUCK2DVS/MAX8997_REG_BUCK5DVS macros. This patch removes these macros to avoid unneeded plus one then minus one operations without reducing readability. Signed-off-by: Axel Lin Acked-by: Kyungmin Park Acked-by: MyungJoo Ham Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- include/linux/mfd/max8997-private.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h index 69d1010e2e51..5ff2400ad46c 100644 --- a/include/linux/mfd/max8997-private.h +++ b/include/linux/mfd/max8997-private.h @@ -311,10 +311,6 @@ enum max8997_irq { MAX8997_IRQ_NR, }; -#define MAX8997_REG_BUCK1DVS(x) (MAX8997_REG_BUCK1DVS1 + (x) - 1) -#define MAX8997_REG_BUCK2DVS(x) (MAX8997_REG_BUCK2DVS1 + (x) - 1) -#define MAX8997_REG_BUCK5DVS(x) (MAX8997_REG_BUCK5DVS1 + (x) - 1) - #define MAX8997_NUM_GPIO 12 struct max8997_dev { struct device *dev; -- cgit v1.2.2 From 795570561cc9c8dc7f7582ed6c4d07121b1c4831 Mon Sep 17 00:00:00 2001 From: Jorge Eduardo Candelaria Date: Mon, 16 May 2011 18:34:59 -0500 Subject: MFD: TPS65910: Add support for TPS65911 device The TPS65911 is the next generation of the TPS65910 family of PMIC chips. It adds a few features: - Watchdog Timer - PWM & LED generators - Comparators for system control status It also adds a set of Interrupts and GPIOs, among other things. The driver exports a function to identify between different versions of the tps65910 family, allowing other modules to identify the capabilities of the current chip. Signed-off-by: Jorge Eduardo Candelaria Acked-by: Samuel Ortiz Signed-off-by: Liam Girdwood --- include/linux/mfd/tps65910.h | 46 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index be08a0c7e7de..6ceea0dab8d7 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -17,6 +17,14 @@ #ifndef __LINUX_MFD_TPS65910_H #define __LINUX_MFD_TPS65910_H +/* TPS chip id list */ +#define TPS65910 0 +#define TPS65911 1 + +/* TPS regulator type list */ +#define REGULATOR_LDO 0 +#define REGULATOR_DCDC 1 + /* * List of registers for component TPS65910 * @@ -96,6 +104,21 @@ #define TPS65910_JTAGVERNUM 0x80 #define TPS65910_MAX_REGISTER 0x80 +/* + * List of registers specific to TPS65911 + */ +#define TPS65911_VDDCTRL 0x27 +#define TPS65911_VDDCTRL_OP 0x28 +#define TPS65911_VDDCTRL_SR 0x29 +#define TPS65911_LDO1 0x30 +#define TPS65911_LDO2 0x31 +#define TPS65911_LDO5 0x32 +#define TPS65911_LDO8 0x33 +#define TPS65911_LDO7 0x34 +#define TPS65911_LDO6 0x35 +#define TPS65911_LDO4 0x36 +#define TPS65911_LDO3 0x37 + /* * List of register bitfields for component TPS65910 * @@ -702,6 +725,23 @@ #define JTAGVERNUM_VERNUM_SHIFT 0 +/* Register VDDCTRL (0x27) bit definitions */ +#define VDDCTRL_ST_MASK 0x03 +#define VDDCTRL_ST_SHIFT 0 + + +/*Register VDDCTRL_OP (0x28) bit definitios */ +#define VDDCTRL_OP_CMD_MASK 0x80 +#define VDDCTRL_OP_CMD_SHIFT 7 +#define VDDCTRL_OP_SEL_MASK 0x7F +#define VDDCTRL_OP_SEL_SHIFT 0 + + +/*Register VDDCTRL_SR (0x29) bit definitions */ +#define VDDCTRL_SR_SEL_MASK 0x7F +#define VDDCTRL_SR_SEL_SHIFT 0 + + /* IRQ Definitions */ #define TPS65910_IRQ_VBAT_VMBDCH 0 #define TPS65910_IRQ_VBAT_VMHI 1 @@ -742,6 +782,7 @@ struct tps65910 { struct device *dev; struct i2c_client *i2c_client; struct mutex io_mutex; + unsigned int id; int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest); int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src); @@ -771,4 +812,9 @@ void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); int tps65910_irq_init(struct tps65910 *tps65910, int irq, struct tps65910_platform_data *pdata); +static inline int tps65910_chip_id(struct tps65910 *tps65910) +{ + return tps65910->id; +} + #endif /* __LINUX_MFD_TPS65910_H */ -- cgit v1.2.2 From a320e3c3d6351814afa5182159df88d2637e0f6f Mon Sep 17 00:00:00 2001 From: Jorge Eduardo Candelaria Date: Mon, 16 May 2011 18:35:03 -0500 Subject: regulator: tps65911: Add new chip version The tps65911 chip introduces new features, including changes in the regulator module. - VDD1 and VDD2 remain unchanged. - VDD3 is now named VDDCTRL and has a wider voltage range. - LDOs are now named LDO1...8 and voltage ranges are sequential, making LDOs easier to handle. Signed-off-by: Jorge Eduardo Candelaria Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- include/linux/mfd/tps65910.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 6ceea0dab8d7..20359e669ae7 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -232,7 +232,6 @@ #define VDD2_OP_SEL_MASK 0x7F #define VDD2_OP_SEL_SHIFT 0 - /*Register VDD2_SR (0x80) register.RegisterDescription */ #define VDD2_SR_SEL_MASK 0x7F #define VDD2_SR_SEL_SHIFT 0 @@ -249,6 +248,8 @@ #define VDD3_CKINEN_SHIFT 2 #define VDD3_ST_MASK 0x03 #define VDD3_ST_SHIFT 0 +#define VDDCTRL_MIN_VOLT 6000 +#define VDDCTRL_OFFSET 125 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */ #define LDO_SEL_MASK 0x0C @@ -259,6 +260,13 @@ #define LDO_ST_MODE_BIT 0x02 +/* Registers LDO1 to LDO8 in tps65910 */ +#define LDO1_SEL_MASK 0xFC +#define LDO3_SEL_MASK 0x7C +#define LDO_MIN_VOLT 1000 +#define LDO_MAX_VOLT 3300; + + /*Register VDIG1 (0x80) register.RegisterDescription */ #define VDIG1_SEL_MASK 0x0C #define VDIG1_SEL_SHIFT 2 -- cgit v1.2.2 From a2974732ca7614aaf0baf9d6dd3ad893d50ce1c5 Mon Sep 17 00:00:00 2001 From: Jorge Eduardo Candelaria Date: Mon, 16 May 2011 18:35:07 -0500 Subject: TPS65911: Add new irq definitions TPS65911 adds new interrupt sources, as well as two new registers to handle them, one for interrupt status and one for interrupt masking. The added irqs are: -VMBCH2 - Low and High threshold -GPIO1-8 - Rising and falling edge detection -WTCHDG - Watchdog interrupt -PWRDN - PWRDN reset interrupt The code should handle these new registers only when the chip version is TPS65911. Signed-off-by: Jorge Eduardo Candelaria Acked-by: Samuel Ortiz Signed-off-by: Liam Girdwood --- include/linux/mfd/tps65910.h | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 20359e669ae7..32bb7b81f713 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -763,6 +763,35 @@ #define TPS65910_IRQ_GPIO_F 9 #define TPS65910_NUM_IRQ 10 +#define TPS65911_IRQ_VBAT_VMBDCH 0 +#define TPS65911_IRQ_VBAT_VMBDCH2L 1 +#define TPS65911_IRQ_VBAT_VMBDCH2H 2 +#define TPS65911_IRQ_VBAT_VMHI 3 +#define TPS65911_IRQ_PWRON 4 +#define TPS65911_IRQ_PWRON_LP 5 +#define TPS65911_IRQ_PWRHOLD_F 6 +#define TPS65911_IRQ_PWRHOLD_R 7 +#define TPS65911_IRQ_HOTDIE 8 +#define TPS65911_IRQ_RTC_ALARM 9 +#define TPS65911_IRQ_RTC_PERIOD 10 +#define TPS65911_IRQ_GPIO0_R 11 +#define TPS65911_IRQ_GPIO0_F 12 +#define TPS65911_IRQ_GPIO1_R 13 +#define TPS65911_IRQ_GPIO1_F 14 +#define TPS65911_IRQ_GPIO2_R 15 +#define TPS65911_IRQ_GPIO2_F 16 +#define TPS65911_IRQ_GPIO3_R 17 +#define TPS65911_IRQ_GPIO3_F 18 +#define TPS65911_IRQ_GPIO4_R 19 +#define TPS65911_IRQ_GPIO4_F 20 +#define TPS65911_IRQ_GPIO5_R 21 +#define TPS65911_IRQ_GPIO5_F 22 +#define TPS65911_IRQ_WTCHDG 23 +#define TPS65911_IRQ_PWRDN 24 + +#define TPS65911_NUM_IRQ 25 + + /* GPIO Register Definitions */ #define TPS65910_GPIO_DEB BIT(2) #define TPS65910_GPIO_PUEN BIT(3) @@ -806,7 +835,8 @@ struct tps65910 { struct mutex irq_lock; int chip_irq; int irq_base; - u16 irq_mask; + int irq_num; + u32 irq_mask; }; struct tps65910_platform_data { -- cgit v1.2.2 From 11ad14f86a7847b084d3e3f114180be39b1c7322 Mon Sep 17 00:00:00 2001 From: Jorge Eduardo Candelaria Date: Mon, 16 May 2011 18:35:42 -0500 Subject: TPS65911: Add support for added GPIO lines GPIO 1 to 8 are added for TPS65911 chip version. The gpio driver now handles more than one gpio lines. Subsequent versions of the chip family can add new GPIO lines with minimal driver changes. Signed-off-by: Jorge Eduardo Candelaria Acked-by: Grant Likely Signed-off-by: Liam Girdwood --- include/linux/mfd/tps65910.h | 90 +++++++------------------------------------- 1 file changed, 14 insertions(+), 76 deletions(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 32bb7b81f713..5f770064e0c5 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -101,6 +101,9 @@ #define TPS65910_GPIO3 0x63 #define TPS65910_GPIO4 0x64 #define TPS65910_GPIO5 0x65 +#define TPS65910_GPIO6 0x66 +#define TPS65910_GPIO7 0x67 +#define TPS65910_GPIO8 0x68 #define TPS65910_JTAGVERNUM 0x80 #define TPS65910_MAX_REGISTER 0x80 @@ -650,82 +653,17 @@ #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 -/*Register GPIO0 (0x80) register.RegisterDescription */ -#define GPIO0_GPIO_DEB_MASK 0x10 -#define GPIO0_GPIO_DEB_SHIFT 4 -#define GPIO0_GPIO_PUEN_MASK 0x08 -#define GPIO0_GPIO_PUEN_SHIFT 3 -#define GPIO0_GPIO_CFG_MASK 0x04 -#define GPIO0_GPIO_CFG_SHIFT 2 -#define GPIO0_GPIO_STS_MASK 0x02 -#define GPIO0_GPIO_STS_SHIFT 1 -#define GPIO0_GPIO_SET_MASK 0x01 -#define GPIO0_GPIO_SET_SHIFT 0 - - -/*Register GPIO1 (0x80) register.RegisterDescription */ -#define GPIO1_GPIO_DEB_MASK 0x10 -#define GPIO1_GPIO_DEB_SHIFT 4 -#define GPIO1_GPIO_PUEN_MASK 0x08 -#define GPIO1_GPIO_PUEN_SHIFT 3 -#define GPIO1_GPIO_CFG_MASK 0x04 -#define GPIO1_GPIO_CFG_SHIFT 2 -#define GPIO1_GPIO_STS_MASK 0x02 -#define GPIO1_GPIO_STS_SHIFT 1 -#define GPIO1_GPIO_SET_MASK 0x01 -#define GPIO1_GPIO_SET_SHIFT 0 - - -/*Register GPIO2 (0x80) register.RegisterDescription */ -#define GPIO2_GPIO_DEB_MASK 0x10 -#define GPIO2_GPIO_DEB_SHIFT 4 -#define GPIO2_GPIO_PUEN_MASK 0x08 -#define GPIO2_GPIO_PUEN_SHIFT 3 -#define GPIO2_GPIO_CFG_MASK 0x04 -#define GPIO2_GPIO_CFG_SHIFT 2 -#define GPIO2_GPIO_STS_MASK 0x02 -#define GPIO2_GPIO_STS_SHIFT 1 -#define GPIO2_GPIO_SET_MASK 0x01 -#define GPIO2_GPIO_SET_SHIFT 0 - - -/*Register GPIO3 (0x80) register.RegisterDescription */ -#define GPIO3_GPIO_DEB_MASK 0x10 -#define GPIO3_GPIO_DEB_SHIFT 4 -#define GPIO3_GPIO_PUEN_MASK 0x08 -#define GPIO3_GPIO_PUEN_SHIFT 3 -#define GPIO3_GPIO_CFG_MASK 0x04 -#define GPIO3_GPIO_CFG_SHIFT 2 -#define GPIO3_GPIO_STS_MASK 0x02 -#define GPIO3_GPIO_STS_SHIFT 1 -#define GPIO3_GPIO_SET_MASK 0x01 -#define GPIO3_GPIO_SET_SHIFT 0 - - -/*Register GPIO4 (0x80) register.RegisterDescription */ -#define GPIO4_GPIO_DEB_MASK 0x10 -#define GPIO4_GPIO_DEB_SHIFT 4 -#define GPIO4_GPIO_PUEN_MASK 0x08 -#define GPIO4_GPIO_PUEN_SHIFT 3 -#define GPIO4_GPIO_CFG_MASK 0x04 -#define GPIO4_GPIO_CFG_SHIFT 2 -#define GPIO4_GPIO_STS_MASK 0x02 -#define GPIO4_GPIO_STS_SHIFT 1 -#define GPIO4_GPIO_SET_MASK 0x01 -#define GPIO4_GPIO_SET_SHIFT 0 - - -/*Register GPIO5 (0x80) register.RegisterDescription */ -#define GPIO5_GPIO_DEB_MASK 0x10 -#define GPIO5_GPIO_DEB_SHIFT 4 -#define GPIO5_GPIO_PUEN_MASK 0x08 -#define GPIO5_GPIO_PUEN_SHIFT 3 -#define GPIO5_GPIO_CFG_MASK 0x04 -#define GPIO5_GPIO_CFG_SHIFT 2 -#define GPIO5_GPIO_STS_MASK 0x02 -#define GPIO5_GPIO_STS_SHIFT 1 -#define GPIO5_GPIO_SET_MASK 0x01 -#define GPIO5_GPIO_SET_SHIFT 0 +/*Register GPIO (0x80) register.RegisterDescription */ +#define GPIO_DEB_MASK 0x10 +#define GPIO_DEB_SHIFT 4 +#define GPIO_PUEN_MASK 0x08 +#define GPIO_PUEN_SHIFT 3 +#define GPIO_CFG_MASK 0x04 +#define GPIO_CFG_SHIFT 2 +#define GPIO_STS_MASK 0x02 +#define GPIO_STS_SHIFT 1 +#define GPIO_SET_MASK 0x01 +#define GPIO_SET_SHIFT 0 /*Register JTAGVERNUM (0x80) register.RegisterDescription */ -- cgit v1.2.2 From 6851ad3ab3461966adfffe8789372fe8256da792 Mon Sep 17 00:00:00 2001 From: Jorge Eduardo Candelaria Date: Mon, 16 May 2011 18:35:48 -0500 Subject: TPS65911: Comparator: Add comparator driver This driver adds functionality to the tps65911 chip driver. Two of the comparators are configurable by software and measures VCCS voltage to detect high or low voltage scenarios. Signed-off-by: Jorge Eduardo Candelaria Acked-by: Samuel Ortiz Signed-off-by: Liam Girdwood --- include/linux/mfd/tps65910.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 5f770064e0c5..8bb85b930c07 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -121,6 +121,8 @@ #define TPS65911_LDO6 0x35 #define TPS65911_LDO4 0x36 #define TPS65911_LDO3 0x37 +#define TPS65911_VMBCH 0x6A +#define TPS65911_VMBCH2 0x6B /* * List of register bitfields for component TPS65910 @@ -746,6 +748,8 @@ struct tps65910_board { int gpio_base; int irq; int irq_base; + int vmbch_threshold; + int vmbch2_threshold; struct regulator_init_data *tps65910_pmic_init_data; }; -- cgit v1.2.2