Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

6 files changed, 379 insertions, 35 deletions

diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h
index b0c174012436..fcbbe71a3cc1 100644
--- a/include/linux/amba/bus.h
+++ b/include/linux/amba/bus.h
@@ -18,8 +18,10 @@
 #include <linux/device.h>
 #include <linux/err.h>
 #include <linux/resource.h>
+#include <linux/regulator/consumer.h>
 
 #define AMBA_NR_IRQS    2
+#define AMBA_CID        0xb105f00d
 
 struct clk;
 
@@ -27,6 +29,7 @@ struct amba_device {
         struct device           dev;
         struct resource         res;
         struct clk              *pclk;
+        struct regulator        *vcore;
         u64                     dma_mask;
         unsigned int            periphid;
         unsigned int            irq[AMBA_NR_IRQS];
@@ -40,12 +43,12 @@ struct amba_id {
 
 struct amba_driver {
         struct device_driver    drv;
-        int                     (*probe)(struct amba_device *, struct amba_id *);
+        int                     (*probe)(struct amba_device *, const struct amba_id *);
         int                     (*remove)(struct amba_device *);
         void                    (*shutdown)(struct amba_device *);
         int                     (*suspend)(struct amba_device *, pm_message_t);
         int                     (*resume)(struct amba_device *);
-        struct amba_id          *id_table;
+        const struct amba_id    *id_table;
 };
 
 enum amba_vendor {
@@ -53,6 +56,10 @@ enum amba_vendor {
         AMBA_VENDOR_ST = 0x80,
 };
 
+extern struct bus_type amba_bustype;
+
+#define to_amba_device(d)       container_of(d, struct amba_device, dev)
+
 #define amba_get_drvdata(d)     dev_get_drvdata(&d->dev)
 #define amba_set_drvdata(d,p)   dev_set_drvdata(&d->dev, p)
 
@@ -70,9 +77,21 @@ void amba_release_regions(struct amba_device *);
 #define amba_pclk_disable(d)    \
         do { if (!IS_ERR((d)->pclk)) clk_disable((d)->pclk); } while (0)
 
-#define amba_config(d)  (((d)->periphid >> 24) & 0xff)
-#define amba_rev(d)     (((d)->periphid >> 20) & 0x0f)
-#define amba_manf(d)    (((d)->periphid >> 12) & 0xff)
-#define amba_part(d)    ((d)->periphid & 0xfff)
+#define amba_vcore_enable(d)    \
+        (IS_ERR((d)->vcore) ? 0 : regulator_enable((d)->vcore))
+
+#define amba_vcore_disable(d)   \
+        do { if (!IS_ERR((d)->vcore)) regulator_disable((d)->vcore); } while (0)
+
+/* Some drivers don't use the struct amba_device */
+#define AMBA_CONFIG_BITS(a) (((a) >> 24) & 0xff)
+#define AMBA_REV_BITS(a) (((a) >> 20) & 0x0f)
+#define AMBA_MANF_BITS(a) (((a) >> 12) & 0xff)
+#define AMBA_PART_BITS(a) ((a) & 0xfff)
+
+#define amba_config(d)  AMBA_CONFIG_BITS((d)->periphid)
+#define amba_rev(d)     AMBA_REV_BITS((d)->periphid)
+#define amba_manf(d)    AMBA_MANF_BITS((d)->periphid)
+#define amba_part(d)    AMBA_PART_BITS((d)->periphid)
 
 #endif
diff --git a/include/linux/amba/clcd.h b/include/linux/amba/clcd.h
index be33b3affc8a..e82e3ee2c54a 100644
--- a/include/linux/amba/clcd.h
+++ b/include/linux/amba/clcd.h
@@ -53,6 +53,7 @@
 #define CNTL_LCDBPP8            (3 << 1)
 #define CNTL_LCDBPP16           (4 << 1)
 #define CNTL_LCDBPP16_565       (6 << 1)
+#define CNTL_LCDBPP16_444       (7 << 1)
 #define CNTL_LCDBPP24           (5 << 1)
 #define CNTL_LCDBW              (1 << 4)
 #define CNTL_LCDTFT             (1 << 5)
@@ -66,6 +67,32 @@
 #define CNTL_LDMAFIFOTIME       (1 << 15)
 #define CNTL_WATERMARK          (1 << 16)
 
+enum {
+        /* individual formats */
+        CLCD_CAP_RGB444         = (1 << 0),
+        CLCD_CAP_RGB5551        = (1 << 1),
+        CLCD_CAP_RGB565         = (1 << 2),
+        CLCD_CAP_RGB888         = (1 << 3),
+        CLCD_CAP_BGR444         = (1 << 4),
+        CLCD_CAP_BGR5551        = (1 << 5),
+        CLCD_CAP_BGR565         = (1 << 6),
+        CLCD_CAP_BGR888         = (1 << 7),
+
+        /* connection layouts */
+        CLCD_CAP_444            = CLCD_CAP_RGB444 | CLCD_CAP_BGR444,
+        CLCD_CAP_5551           = CLCD_CAP_RGB5551 | CLCD_CAP_BGR5551,
+        CLCD_CAP_565            = CLCD_CAP_RGB565 | CLCD_CAP_BGR565,
+        CLCD_CAP_888            = CLCD_CAP_RGB888 | CLCD_CAP_BGR888,
+
+        /* red/blue ordering */
+        CLCD_CAP_RGB            = CLCD_CAP_RGB444 | CLCD_CAP_RGB5551 |
+                                  CLCD_CAP_RGB565 | CLCD_CAP_RGB888,
+        CLCD_CAP_BGR            = CLCD_CAP_BGR444 | CLCD_CAP_BGR5551 |
+                                  CLCD_CAP_BGR565 | CLCD_CAP_BGR888,
+
+        CLCD_CAP_ALL            = CLCD_CAP_BGR | CLCD_CAP_RGB,
+};
+
 struct clcd_panel {
         struct fb_videomode     mode;
         signed short            width;  /* width in mm */
@@ -73,6 +100,7 @@ struct clcd_panel {
         u32                     tim2;
         u32                     tim3;
         u32                     cntl;
+        u32                     caps;
         unsigned int            bpp:8,
                                 fixedtimings:1,
                                 grayscale:1;
@@ -97,13 +125,18 @@ struct clcd_board {
         const char *name;
 
         /*
+         * Optional.  Hardware capability flags.
+         */
+        u32     caps;
+
+        /*
          * Optional.  Check whether the var structure is acceptable
          * for this display.
          */
         int     (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
 
         /*
-         * Compulsary.  Decode fb->fb.var into regs->*.  In the case of
+         * Compulsory.  Decode fb->fb.var into regs->*.  In the case of
          * fixed timing, set regs->* to the register values required.
          */
         void    (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
@@ -155,34 +188,35 @@ struct clcd_fb {
 
 static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
 {
+        struct fb_var_screeninfo *var = &fb->fb.var;
         u32 val, cpl;
 
         /*
          * Program the CLCD controller registers and start the CLCD
          */
-        val = ((fb->fb.var.xres / 16) - 1) << 2;
-        val |= (fb->fb.var.hsync_len - 1) << 8;
-        val |= (fb->fb.var.right_margin - 1) << 16;
-        val |= (fb->fb.var.left_margin - 1) << 24;
+        val = ((var->xres / 16) - 1) << 2;
+        val |= (var->hsync_len - 1) << 8;
+        val |= (var->right_margin - 1) << 16;
+        val |= (var->left_margin - 1) << 24;
         regs->tim0 = val;
 
-        val = fb->fb.var.yres;
+        val = var->yres;
         if (fb->panel->cntl & CNTL_LCDDUAL)
                 val /= 2;
         val -= 1;
-        val |= (fb->fb.var.vsync_len - 1) << 10;
-        val |= fb->fb.var.lower_margin << 16;
-        val |= fb->fb.var.upper_margin << 24;
+        val |= (var->vsync_len - 1) << 10;
+        val |= var->lower_margin << 16;
+        val |= var->upper_margin << 24;
         regs->tim1 = val;
 
         val = fb->panel->tim2;
-        val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT  ? 0 : TIM2_IHS;
-        val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
+        val |= var->sync & FB_SYNC_HOR_HIGH_ACT  ? 0 : TIM2_IHS;
+        val |= var->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
 
-        cpl = fb->fb.var.xres_virtual;
+        cpl = var->xres_virtual;
         if (fb->panel->cntl & CNTL_LCDTFT)        /* TFT */
                 /* / 1 */;
-        else if (!fb->fb.var.grayscale)           /* STN color */
+        else if (!var->grayscale)                 /* STN color */
                 cpl = cpl * 8 / 3;
         else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
                 cpl /= 8;
@@ -194,10 +228,22 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
         regs->tim3 = fb->panel->tim3;
 
         val = fb->panel->cntl;
-        if (fb->fb.var.grayscale)
+        if (var->grayscale)
                 val |= CNTL_LCDBW;
 
-        switch (fb->fb.var.bits_per_pixel) {
+        if (fb->panel->caps && fb->board->caps &&
+            var->bits_per_pixel >= 16) {
+                /*
+                 * if board and panel supply capabilities, we can support
+                 * changing BGR/RGB depending on supplied parameters
+                 */
+                if (var->red.offset == 0)
+                        val &= ~CNTL_BGR;
+                else
+                        val |= CNTL_BGR;
+        }
+
+        switch (var->bits_per_pixel) {
         case 1:
                 val |= CNTL_LCDBPP1;
                 break;
@@ -212,15 +258,17 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
                 break;
         case 16:
                 /*
-                 * PL110 cannot choose between 5551 and 565 modes in
-                 * its control register
+                 * PL110 cannot choose between 5551 and 565 modes in its
+                 * control register.  It is possible to use 565 with
+                 * custom external wiring.
                  */
-                if ((fb->dev->periphid & 0x000fffff) == 0x00041110)
+                if (amba_part(fb->dev) == 0x110 ||
+                    var->green.length == 5)
                         val |= CNTL_LCDBPP16;
-                else if (fb->fb.var.green.length == 5)
-                        val |= CNTL_LCDBPP16;
-                else
+                else if (var->green.length == 6)
                         val |= CNTL_LCDBPP16_565;
+                else
+                        val |= CNTL_LCDBPP16_444;
                 break;
         case 32:
                 val |= CNTL_LCDBPP24;
@@ -228,7 +276,7 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
         }
 
         regs->cntl = val;
-        regs->pixclock = fb->fb.var.pixclock;
+        regs->pixclock = var->pixclock;
 }
 
 static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h
index ca84ce70d5d5..21114810c7c0 100644
--- a/include/linux/amba/mmci.h
+++ b/include/linux/amba/mmci.h
@@ -6,6 +6,9 @@
 
 #include <linux/mmc/host.h>
 
+/* Just some dummy forwarding */
+struct dma_chan;
+
 /**
  * struct mmci_platform_data - platform configuration for the MMCI
  * (also known as PL180) block.
@@ -24,8 +27,20 @@
  * whether a card is present in the MMC slot or not
  * @gpio_wp: read this GPIO pin to see if the card is write protected
  * @gpio_cd: read this GPIO pin to detect card insertion
+ * @cd_invert: true if the gpio_cd pin value is active low
  * @capabilities: the capabilities of the block as implemented in
  * this platform, signify anything MMC_CAP_* from mmc/host.h
+ * @dma_filter: function used to select an appropriate RX and TX
+ * DMA channel to be used for DMA, if and only if you're deploying the
+ * generic DMA engine
+ * @dma_rx_param: parameter passed to the DMA allocation
+ * filter in order to select an appropriate RX channel. If
+ * there is a bidirectional RX+TX channel, then just specify
+ * this and leave dma_tx_param set to NULL
+ * @dma_tx_param: parameter passed to the DMA allocation
+ * filter in order to select an appropriate TX channel. If this
+ * is NULL the driver will attempt to use the RX channel as a
+ * bidirectional channel
  */
 struct mmci_platform_data {
         unsigned int f_max;
@@ -35,7 +50,11 @@ struct mmci_platform_data {
         unsigned int (*status)(struct device *);
         int     gpio_wp;
         int     gpio_cd;
+        bool    cd_invert;
         unsigned long capabilities;
+        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+        void *dma_rx_param;
+        void *dma_tx_param;
 };
 
 #endif
diff --git a/include/linux/amba/pl022.h b/include/linux/amba/pl022.h
index abf26cc47a2b..4ce98f54186b 100644
--- a/include/linux/amba/pl022.h
+++ b/include/linux/amba/pl022.h
@@ -228,6 +228,7 @@ enum ssp_chip_select {
 };
 
 
+struct dma_chan;
 /**
  * struct pl022_ssp_master - device.platform_data for SPI controller devices.
  * @num_chipselect: chipselects are used to distinguish individual
@@ -235,11 +236,16 @@ enum ssp_chip_select {
  *     each slave has a chipselect signal, but it's common that not
  *     every chipselect is connected to a slave.
  * @enable_dma: if true enables DMA driven transfers.
+ * @dma_rx_param: parameter to locate an RX DMA channel.
+ * @dma_tx_param: parameter to locate a TX DMA channel.
  */
 struct pl022_ssp_controller {
         u16 bus_id;
         u8 num_chipselect;
         u8 enable_dma:1;
+        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+        void *dma_rx_param;
+        void *dma_tx_param;
 };
 
 /**
@@ -270,20 +276,13 @@ struct pl022_ssp_controller {
  * @dma_config: DMA configuration for SSP controller and peripheral
  */
 struct pl022_config_chip {
-        struct device *dev;
-        enum ssp_loopback lbm;
         enum ssp_interface iface;
         enum ssp_hierarchy hierarchy;
         bool slave_tx_disable;
         struct ssp_clock_params clk_freq;
-        enum ssp_rx_endian endian_rx;
-        enum ssp_tx_endian endian_tx;
-        enum ssp_data_size data_size;
         enum ssp_mode com_mode;
         enum ssp_rx_level_trig rx_lev_trig;
         enum ssp_tx_level_trig tx_lev_trig;
-        enum ssp_spi_clk_phase clk_phase;
-        enum ssp_spi_clk_pol clk_pol;
         enum ssp_microwire_ctrl_len ctrl_len;
         enum ssp_microwire_wait_state wait_state;
         enum ssp_duplex duplex;
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
new file mode 100644
index 000000000000..3111385b8ca7
--- /dev/null
+++ b/include/linux/amba/pl08x.h
@@ -0,0 +1,223 @@
+/*
+ * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
+ *
+ * Copyright (C) 2005 ARM Ltd
+ * Copyright (C) 2010 ST-Ericsson SA
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * pl08x information required by platform code
+ *
+ * Please credit ARM.com
+ * Documentation: ARM DDI 0196D
+ */
+
+#ifndef AMBA_PL08X_H
+#define AMBA_PL08X_H
+
+/* We need sizes of structs from this header */
+#include <linux/dmaengine.h>
+#include <linux/interrupt.h>
+
+struct pl08x_lli;
+struct pl08x_driver_data;
+
+/* Bitmasks for selecting AHB ports for DMA transfers */
+enum {
+        PL08X_AHB1 = (1 << 0),
+        PL08X_AHB2 = (1 << 1)
+};
+
+/**
+ * struct pl08x_channel_data - data structure to pass info between
+ * platform and PL08x driver regarding channel configuration
+ * @bus_id: name of this device channel, not just a device name since
+ * devices may have more than one channel e.g. "foo_tx"
+ * @min_signal: the minimum DMA signal number to be muxed in for this
+ * channel (for platforms supporting muxed signals). If you have
+ * static assignments, make sure this is set to the assigned signal
+ * number, PL08x have 16 possible signals in number 0 thru 15 so
+ * when these are not enough they often get muxed (in hardware)
+ * disabling simultaneous use of the same channel for two devices.
+ * @max_signal: the maximum DMA signal number to be muxed in for
+ * the channel. Set to the same as min_signal for
+ * devices with static assignments
+ * @muxval: a number usually used to poke into some mux regiser to
+ * mux in the signal to this channel
+ * @cctl_opt: default options for the channel control register
+ * @addr: source/target address in physical memory for this DMA channel,
+ * can be the address of a FIFO register for burst requests for example.
+ * This can be left undefined if the PrimeCell API is used for configuring
+ * this.
+ * @circular_buffer: whether the buffer passed in is circular and
+ * shall simply be looped round round (like a record baby round
+ * round round round)
+ * @single: the device connected to this channel will request single DMA
+ * transfers, not bursts. (Bursts are default.)
+ * @periph_buses: the device connected to this channel is accessible via
+ * these buses (use PL08X_AHB1 | PL08X_AHB2).
+ */
+struct pl08x_channel_data {
+        char *bus_id;
+        int min_signal;
+        int max_signal;
+        u32 muxval;
+        u32 cctl;
+        dma_addr_t addr;
+        bool circular_buffer;
+        bool single;
+        u8 periph_buses;
+};
+
+/**
+ * Struct pl08x_bus_data - information of source or destination
+ * busses for a transfer
+ * @addr: current address
+ * @maxwidth: the maximum width of a transfer on this bus
+ * @buswidth: the width of this bus in bytes: 1, 2 or 4
+ * @fill_bytes: bytes required to fill to the next bus memory boundary
+ */
+struct pl08x_bus_data {
+        dma_addr_t addr;
+        u8 maxwidth;
+        u8 buswidth;
+        size_t fill_bytes;
+};
+
+/**
+ * struct pl08x_phy_chan - holder for the physical channels
+ * @id: physical index to this channel
+ * @lock: a lock to use when altering an instance of this struct
+ * @signal: the physical signal (aka channel) serving this physical channel
+ * right now
+ * @serving: the virtual channel currently being served by this physical
+ * channel
+ */
+struct pl08x_phy_chan {
+        unsigned int id;
+        void __iomem *base;
+        spinlock_t lock;
+        int signal;
+        struct pl08x_dma_chan *serving;
+};
+
+/**
+ * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
+ * @llis_bus: DMA memory address (physical) start for the LLIs
+ * @llis_va: virtual memory address start for the LLIs
+ */
+struct pl08x_txd {
+        struct dma_async_tx_descriptor tx;
+        struct list_head node;
+        enum dma_data_direction direction;
+        dma_addr_t src_addr;
+        dma_addr_t dst_addr;
+        size_t len;
+        dma_addr_t llis_bus;
+        struct pl08x_lli *llis_va;
+        /* Default cctl value for LLIs */
+        u32 cctl;
+        /*
+         * Settings to be put into the physical channel when we
+         * trigger this txd.  Other registers are in llis_va[0].
+         */
+        u32 ccfg;
+};
+
+/**
+ * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
+ * states
+ * @PL08X_CHAN_IDLE: the channel is idle
+ * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
+ * channel and is running a transfer on it
+ * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
+ * channel, but the transfer is currently paused
+ * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
+ * channel to become available (only pertains to memcpy channels)
+ */
+enum pl08x_dma_chan_state {
+        PL08X_CHAN_IDLE,
+        PL08X_CHAN_RUNNING,
+        PL08X_CHAN_PAUSED,
+        PL08X_CHAN_WAITING,
+};
+
+/**
+ * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
+ * @chan: wrappped abstract channel
+ * @phychan: the physical channel utilized by this channel, if there is one
+ * @phychan_hold: if non-zero, hold on to the physical channel even if we
+ * have no pending entries
+ * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
+ * @name: name of channel
+ * @cd: channel platform data
+ * @runtime_addr: address for RX/TX according to the runtime config
+ * @runtime_direction: current direction of this channel according to
+ * runtime config
+ * @lc: last completed transaction on this channel
+ * @pend_list: queued transactions pending on this channel
+ * @at: active transaction on this channel
+ * @lock: a lock for this channel data
+ * @host: a pointer to the host (internal use)
+ * @state: whether the channel is idle, paused, running etc
+ * @slave: whether this channel is a device (slave) or for memcpy
+ * @waiting: a TX descriptor on this channel which is waiting for a physical
+ * channel to become available
+ */
+struct pl08x_dma_chan {
+        struct dma_chan chan;
+        struct pl08x_phy_chan *phychan;
+        int phychan_hold;
+        struct tasklet_struct tasklet;
+        char *name;
+        struct pl08x_channel_data *cd;
+        dma_addr_t runtime_addr;
+        enum dma_data_direction runtime_direction;
+        dma_cookie_t lc;
+        struct list_head pend_list;
+        struct pl08x_txd *at;
+        spinlock_t lock;
+        struct pl08x_driver_data *host;
+        enum pl08x_dma_chan_state state;
+        bool slave;
+        struct pl08x_txd *waiting;
+};
+
+/**
+ * struct pl08x_platform_data - the platform configuration for the PL08x
+ * PrimeCells.
+ * @slave_channels: the channels defined for the different devices on the
+ * platform, all inclusive, including multiplexed channels. The available
+ * physical channels will be multiplexed around these signals as they are
+ * requested, just enumerate all possible channels.
+ * @get_signal: request a physical signal to be used for a DMA transfer
+ * immediately: if there is some multiplexing or similar blocking the use
+ * of the channel the transfer can be denied by returning less than zero,
+ * else it returns the allocated signal number
+ * @put_signal: indicate to the platform that this physical signal is not
+ * running any DMA transfer and multiplexing can be recycled
+ * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
+ * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
+ */
+struct pl08x_platform_data {
+        struct pl08x_channel_data *slave_channels;
+        unsigned int num_slave_channels;
+        struct pl08x_channel_data memcpy_channel;
+        int (*get_signal)(struct pl08x_dma_chan *);
+        void (*put_signal)(struct pl08x_dma_chan *);
+        u8 lli_buses;
+        u8 mem_buses;
+};
+
+#ifdef CONFIG_AMBA_PL08X
+bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
+#else
+static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
+{
+        return false;
+}
+#endif
+
+#endif  /* AMBA_PL08X_H */
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index e1b634b635f2..514ed45c462e 100644
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -32,7 +32,9 @@
 #define UART01x_RSR             0x04    /* Receive status register (Read). */
 #define UART01x_ECR             0x04    /* Error clear register (Write). */
 #define UART010_LCRH            0x08    /* Line control register, high byte. */
+#define ST_UART011_DMAWM        0x08    /* DMA watermark configure register. */
 #define UART010_LCRM            0x0C    /* Line control register, middle byte. */
+#define ST_UART011_TIMEOUT      0x0C    /* Timeout period register. */
 #define UART010_LCRL            0x10    /* Line control register, low byte. */
 #define UART010_CR              0x14    /* Control register. */
 #define UART01x_FR              0x18    /* Flag register (Read only). */
@@ -51,6 +53,15 @@
 #define UART011_MIS             0x40    /* Masked interrupt status. */
 #define UART011_ICR             0x44    /* Interrupt clear register. */
 #define UART011_DMACR           0x48    /* DMA control register. */
+#define ST_UART011_XFCR         0x50    /* XON/XOFF control register. */
+#define ST_UART011_XON1         0x54    /* XON1 register. */
+#define ST_UART011_XON2         0x58    /* XON2 register. */
+#define ST_UART011_XOFF1        0x5C    /* XON1 register. */
+#define ST_UART011_XOFF2        0x60    /* XON2 register. */
+#define ST_UART011_ITCR         0x80    /* Integration test control register. */
+#define ST_UART011_ITIP         0x84    /* Integration test input register. */
+#define ST_UART011_ABCR         0x100   /* Autobaud control register. */
+#define ST_UART011_ABIMSC       0x15C   /* Autobaud interrupt mask/clear register. */
 
 #define UART011_DR_OE           (1 << 11)
 #define UART011_DR_BE           (1 << 10)
@@ -102,6 +113,21 @@
 #define UART01x_LCRH_PEN        0x02
 #define UART01x_LCRH_BRK        0x01
 
+#define ST_UART011_DMAWM_RX_1   (0 << 3)
+#define ST_UART011_DMAWM_RX_2   (1 << 3)
+#define ST_UART011_DMAWM_RX_4   (2 << 3)
+#define ST_UART011_DMAWM_RX_8   (3 << 3)
+#define ST_UART011_DMAWM_RX_16  (4 << 3)
+#define ST_UART011_DMAWM_RX_32  (5 << 3)
+#define ST_UART011_DMAWM_RX_48  (6 << 3)
+#define ST_UART011_DMAWM_TX_1   0
+#define ST_UART011_DMAWM_TX_2   1
+#define ST_UART011_DMAWM_TX_4   2
+#define ST_UART011_DMAWM_TX_8   3
+#define ST_UART011_DMAWM_TX_16  4
+#define ST_UART011_DMAWM_TX_32  5
+#define ST_UART011_DMAWM_TX_48  6
+
 #define UART010_IIR_RTIS        0x08
 #define UART010_IIR_TIS         0x04
 #define UART010_IIR_RIS         0x02
@@ -169,6 +195,16 @@ struct amba_device; /* in uncompress this is included but amba/bus.h is not */
 struct amba_pl010_data {
         void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
 };
+
+struct dma_chan;
+struct amba_pl011_data {
+        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+        void *dma_rx_param;
+        void *dma_tx_param;
+        void (*init) (void);
+        void (*exit) (void);
+        void (*reset) (void);
+};
 #endif
 
 #endif