diff options
Diffstat (limited to 'include/linux/amba/pl08x.h')
-rw-r--r-- | include/linux/amba/pl08x.h | 223 |
1 files changed, 223 insertions, 0 deletions
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h new file mode 100644 index 000000000000..3111385b8ca7 --- /dev/null +++ b/include/linux/amba/pl08x.h | |||
@@ -0,0 +1,223 @@ | |||
1 | /* | ||
2 | * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver | ||
3 | * | ||
4 | * Copyright (C) 2005 ARM Ltd | ||
5 | * Copyright (C) 2010 ST-Ericsson SA | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * pl08x information required by platform code | ||
12 | * | ||
13 | * Please credit ARM.com | ||
14 | * Documentation: ARM DDI 0196D | ||
15 | */ | ||
16 | |||
17 | #ifndef AMBA_PL08X_H | ||
18 | #define AMBA_PL08X_H | ||
19 | |||
20 | /* We need sizes of structs from this header */ | ||
21 | #include <linux/dmaengine.h> | ||
22 | #include <linux/interrupt.h> | ||
23 | |||
24 | struct pl08x_lli; | ||
25 | struct pl08x_driver_data; | ||
26 | |||
27 | /* Bitmasks for selecting AHB ports for DMA transfers */ | ||
28 | enum { | ||
29 | PL08X_AHB1 = (1 << 0), | ||
30 | PL08X_AHB2 = (1 << 1) | ||
31 | }; | ||
32 | |||
33 | /** | ||
34 | * struct pl08x_channel_data - data structure to pass info between | ||
35 | * platform and PL08x driver regarding channel configuration | ||
36 | * @bus_id: name of this device channel, not just a device name since | ||
37 | * devices may have more than one channel e.g. "foo_tx" | ||
38 | * @min_signal: the minimum DMA signal number to be muxed in for this | ||
39 | * channel (for platforms supporting muxed signals). If you have | ||
40 | * static assignments, make sure this is set to the assigned signal | ||
41 | * number, PL08x have 16 possible signals in number 0 thru 15 so | ||
42 | * when these are not enough they often get muxed (in hardware) | ||
43 | * disabling simultaneous use of the same channel for two devices. | ||
44 | * @max_signal: the maximum DMA signal number to be muxed in for | ||
45 | * the channel. Set to the same as min_signal for | ||
46 | * devices with static assignments | ||
47 | * @muxval: a number usually used to poke into some mux regiser to | ||
48 | * mux in the signal to this channel | ||
49 | * @cctl_opt: default options for the channel control register | ||
50 | * @addr: source/target address in physical memory for this DMA channel, | ||
51 | * can be the address of a FIFO register for burst requests for example. | ||
52 | * This can be left undefined if the PrimeCell API is used for configuring | ||
53 | * this. | ||
54 | * @circular_buffer: whether the buffer passed in is circular and | ||
55 | * shall simply be looped round round (like a record baby round | ||
56 | * round round round) | ||
57 | * @single: the device connected to this channel will request single DMA | ||
58 | * transfers, not bursts. (Bursts are default.) | ||
59 | * @periph_buses: the device connected to this channel is accessible via | ||
60 | * these buses (use PL08X_AHB1 | PL08X_AHB2). | ||
61 | */ | ||
62 | struct pl08x_channel_data { | ||
63 | char *bus_id; | ||
64 | int min_signal; | ||
65 | int max_signal; | ||
66 | u32 muxval; | ||
67 | u32 cctl; | ||
68 | dma_addr_t addr; | ||
69 | bool circular_buffer; | ||
70 | bool single; | ||
71 | u8 periph_buses; | ||
72 | }; | ||
73 | |||
74 | /** | ||
75 | * Struct pl08x_bus_data - information of source or destination | ||
76 | * busses for a transfer | ||
77 | * @addr: current address | ||
78 | * @maxwidth: the maximum width of a transfer on this bus | ||
79 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | ||
80 | * @fill_bytes: bytes required to fill to the next bus memory boundary | ||
81 | */ | ||
82 | struct pl08x_bus_data { | ||
83 | dma_addr_t addr; | ||
84 | u8 maxwidth; | ||
85 | u8 buswidth; | ||
86 | size_t fill_bytes; | ||
87 | }; | ||
88 | |||
89 | /** | ||
90 | * struct pl08x_phy_chan - holder for the physical channels | ||
91 | * @id: physical index to this channel | ||
92 | * @lock: a lock to use when altering an instance of this struct | ||
93 | * @signal: the physical signal (aka channel) serving this physical channel | ||
94 | * right now | ||
95 | * @serving: the virtual channel currently being served by this physical | ||
96 | * channel | ||
97 | */ | ||
98 | struct pl08x_phy_chan { | ||
99 | unsigned int id; | ||
100 | void __iomem *base; | ||
101 | spinlock_t lock; | ||
102 | int signal; | ||
103 | struct pl08x_dma_chan *serving; | ||
104 | }; | ||
105 | |||
106 | /** | ||
107 | * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor | ||
108 | * @llis_bus: DMA memory address (physical) start for the LLIs | ||
109 | * @llis_va: virtual memory address start for the LLIs | ||
110 | */ | ||
111 | struct pl08x_txd { | ||
112 | struct dma_async_tx_descriptor tx; | ||
113 | struct list_head node; | ||
114 | enum dma_data_direction direction; | ||
115 | dma_addr_t src_addr; | ||
116 | dma_addr_t dst_addr; | ||
117 | size_t len; | ||
118 | dma_addr_t llis_bus; | ||
119 | struct pl08x_lli *llis_va; | ||
120 | /* Default cctl value for LLIs */ | ||
121 | u32 cctl; | ||
122 | /* | ||
123 | * Settings to be put into the physical channel when we | ||
124 | * trigger this txd. Other registers are in llis_va[0]. | ||
125 | */ | ||
126 | u32 ccfg; | ||
127 | }; | ||
128 | |||
129 | /** | ||
130 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel | ||
131 | * states | ||
132 | * @PL08X_CHAN_IDLE: the channel is idle | ||
133 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | ||
134 | * channel and is running a transfer on it | ||
135 | * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport | ||
136 | * channel, but the transfer is currently paused | ||
137 | * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport | ||
138 | * channel to become available (only pertains to memcpy channels) | ||
139 | */ | ||
140 | enum pl08x_dma_chan_state { | ||
141 | PL08X_CHAN_IDLE, | ||
142 | PL08X_CHAN_RUNNING, | ||
143 | PL08X_CHAN_PAUSED, | ||
144 | PL08X_CHAN_WAITING, | ||
145 | }; | ||
146 | |||
147 | /** | ||
148 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | ||
149 | * @chan: wrappped abstract channel | ||
150 | * @phychan: the physical channel utilized by this channel, if there is one | ||
151 | * @phychan_hold: if non-zero, hold on to the physical channel even if we | ||
152 | * have no pending entries | ||
153 | * @tasklet: tasklet scheduled by the IRQ to handle actual work etc | ||
154 | * @name: name of channel | ||
155 | * @cd: channel platform data | ||
156 | * @runtime_addr: address for RX/TX according to the runtime config | ||
157 | * @runtime_direction: current direction of this channel according to | ||
158 | * runtime config | ||
159 | * @lc: last completed transaction on this channel | ||
160 | * @pend_list: queued transactions pending on this channel | ||
161 | * @at: active transaction on this channel | ||
162 | * @lock: a lock for this channel data | ||
163 | * @host: a pointer to the host (internal use) | ||
164 | * @state: whether the channel is idle, paused, running etc | ||
165 | * @slave: whether this channel is a device (slave) or for memcpy | ||
166 | * @waiting: a TX descriptor on this channel which is waiting for a physical | ||
167 | * channel to become available | ||
168 | */ | ||
169 | struct pl08x_dma_chan { | ||
170 | struct dma_chan chan; | ||
171 | struct pl08x_phy_chan *phychan; | ||
172 | int phychan_hold; | ||
173 | struct tasklet_struct tasklet; | ||
174 | char *name; | ||
175 | struct pl08x_channel_data *cd; | ||
176 | dma_addr_t runtime_addr; | ||
177 | enum dma_data_direction runtime_direction; | ||
178 | dma_cookie_t lc; | ||
179 | struct list_head pend_list; | ||
180 | struct pl08x_txd *at; | ||
181 | spinlock_t lock; | ||
182 | struct pl08x_driver_data *host; | ||
183 | enum pl08x_dma_chan_state state; | ||
184 | bool slave; | ||
185 | struct pl08x_txd *waiting; | ||
186 | }; | ||
187 | |||
188 | /** | ||
189 | * struct pl08x_platform_data - the platform configuration for the PL08x | ||
190 | * PrimeCells. | ||
191 | * @slave_channels: the channels defined for the different devices on the | ||
192 | * platform, all inclusive, including multiplexed channels. The available | ||
193 | * physical channels will be multiplexed around these signals as they are | ||
194 | * requested, just enumerate all possible channels. | ||
195 | * @get_signal: request a physical signal to be used for a DMA transfer | ||
196 | * immediately: if there is some multiplexing or similar blocking the use | ||
197 | * of the channel the transfer can be denied by returning less than zero, | ||
198 | * else it returns the allocated signal number | ||
199 | * @put_signal: indicate to the platform that this physical signal is not | ||
200 | * running any DMA transfer and multiplexing can be recycled | ||
201 | * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2 | ||
202 | * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2 | ||
203 | */ | ||
204 | struct pl08x_platform_data { | ||
205 | struct pl08x_channel_data *slave_channels; | ||
206 | unsigned int num_slave_channels; | ||
207 | struct pl08x_channel_data memcpy_channel; | ||
208 | int (*get_signal)(struct pl08x_dma_chan *); | ||
209 | void (*put_signal)(struct pl08x_dma_chan *); | ||
210 | u8 lli_buses; | ||
211 | u8 mem_buses; | ||
212 | }; | ||
213 | |||
214 | #ifdef CONFIG_AMBA_PL08X | ||
215 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id); | ||
216 | #else | ||
217 | static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | ||
218 | { | ||
219 | return false; | ||
220 | } | ||
221 | #endif | ||
222 | |||
223 | #endif /* AMBA_PL08X_H */ | ||