clk: samsung: exynos5433: Add clocks for CMU_MSCL domain

This patch adds the mux/divider/gate clocks for CMU_MSCL domain which
generates the clocks for M2M (Memory to Memory) scaler, JPEG IPs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 40 insertions, 1 deletions

diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index cdc91f7e6ec8..9898390710e6 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -114,6 +114,8 @@
 #define CLK_DIV_SCLK_USBHOST30          141
 #define CLK_DIV_SCLK_UFSUNIPRO          142
 #define CLK_DIV_SCLK_USBDRD30           143
+#define CLK_DIV_SCLK_JPEG               144
+#define CLK_DIV_ACLK_MSCL_400           145
 
 #define CLK_ACLK_PERIC_66               200
 #define CLK_ACLK_PERIS_66               201
@@ -149,8 +151,10 @@
 #define CLK_SCLK_USBDRD30_FSYS          231
 #define CLK_ACLK_GSCL_111               232
 #define CLK_ACLK_GSCL_333               233
+#define CLK_SCLK_JPEG_MSCL              234
+#define CLK_ACLK_MSCL_400               235
 
-#define TOP_NR_CLK                      234
+#define TOP_NR_CLK                      236
 
 /* CMU_CPIF */
 #define CLK_FOUT_MPHY_PLL               1
@@ -937,4 +941,39 @@
 
 #define ATLAS_NR_CLK                                    40
 
+/* CMU_MSCL */
+#define CLK_MOUT_SCLK_JPEG_USER                         1
+#define CLK_MOUT_ACLK_MSCL_400_USER                     2
+#define CLK_MOUT_SCLK_JPEG                              3
+
+#define CLK_DIV_PCLK_MSCL                               4
+
+#define CLK_ACLK_BTS_JPEG                               5
+#define CLK_ACLK_BTS_M2MSCALER1                         6
+#define CLK_ACLK_BTS_M2MSCALER0                         7
+#define CLK_ACLK_AHB2APB_MSCL0P                         8
+#define CLK_ACLK_XIU_MSCLX                              9
+#define CLK_ACLK_MSCLNP_100                             10
+#define CLK_ACLK_MSCLND_400                             11
+#define CLK_ACLK_JPEG                                   12
+#define CLK_ACLK_M2MSCALER1                             13
+#define CLK_ACLK_M2MSCALER0                             14
+#define CLK_ACLK_SMMU_M2MSCALER0                        15
+#define CLK_ACLK_SMMU_M2MSCALER1                        16
+#define CLK_ACLK_SMMU_JPEG                              17
+#define CLK_PCLK_BTS_JPEG                               18
+#define CLK_PCLK_BTS_M2MSCALER1                         19
+#define CLK_PCLK_BTS_M2MSCALER0                         20
+#define CLK_PCLK_PMU_MSCL                               21
+#define CLK_PCLK_SYSREG_MSCL                            22
+#define CLK_PCLK_JPEG                                   23
+#define CLK_PCLK_M2MSCALER1                             24
+#define CLK_PCLK_M2MSCALER0                             25
+#define CLK_PCLK_SMMU_M2MSCALER0                        26
+#define CLK_PCLK_SMMU_M2MSCALER1                        27
+#define CLK_PCLK_SMMU_JPEG                              28
+#define CLK_SCLK_JPEG                                   29
+
+#define MSCL_NR_CLK                                     30
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */