clk: samsung: exynos5433: Add clocks for CMU_ATLAS domain

This patch adds the mux/divider/gate clocks for CMU_ATLAS domain which
generates the clocks for Cortex-A57 Quad-core processsor, L2 cache
controller and CoreSight.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 46 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 90184e3a42d5..cdc91f7e6ec8 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -891,4 +891,50 @@
 
 #define APOLLO_NR_CLK                                   31
 
+/* CMU_ATLAS */
+#define CLK_FOUT_ATLAS_PLL                              1
+
+#define CLK_MOUT_ATLAS_PLL                              2
+#define CLK_MOUT_BUS_PLL_ATLAS_USER                     3
+#define CLK_MOUT_ATLAS                                  4
+
+#define CLK_DIV_CNTCLK_ATLAS                            5
+#define CLK_DIV_PCLK_DBG_ATLAS                          6
+#define CLK_DIV_ATCLK_ATLASO                            7
+#define CLK_DIV_PCLK_ATLAS                              8
+#define CLK_DIV_ACLK_ATLAS                              9
+#define CLK_DIV_ATLAS2                                  10
+#define CLK_DIV_ATLAS1                                  11
+#define CLK_DIV_SCLK_HPM_ATLAS                          12
+#define CLK_DIV_ATLAS_PLL                               13
+
+#define CLK_ACLK_ATB_AUD_CSSYS                          14
+#define CLK_ACLK_ATB_APOLLO3_CSSYS                      15
+#define CLK_ACLK_ATB_APOLLO2_CSSYS                      16
+#define CLK_ACLK_ATB_APOLLO1_CSSYS                      17
+#define CLK_ACLK_ATB_APOLLO0_CSSYS                      18
+#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS                    19
+#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX                   20
+#define CLK_ACLK_ASYNCACES_ATLAS_CCI                    21
+#define CLK_ACLK_AHB2APB_ATLASP                         22
+#define CLK_ACLK_ATLASNP_200                            23
+#define CLK_PCLK_ASYNCAPB_AUD_CSSYS                     24
+#define CLK_PCLK_ASYNCAPB_ISP_CSSYS                     25
+#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS                  26
+#define CLK_PCLK_PMU_ATLAS                              27
+#define CLK_PCLK_SYSREG_ATLAS                           28
+#define CLK_PCLK_SECJTAG                                29
+#define CLK_CNTCLK_ATLAS                                30
+#define CLK_SCLK_FREQ_DET_ATLAS_PLL                     31
+#define CLK_SCLK_HPM_ATLAS                              32
+#define CLK_TRACECLK                                    33
+#define CLK_CTMCLK                                      34
+#define CLK_HCLK_CSSYS                                  35
+#define CLK_PCLK_DBG_CSSYS                              36
+#define CLK_PCLK_DBG                                    37
+#define CLK_ATCLK                                       38
+#define CLK_SCLK_ATLAS                                  39
+
+#define ATLAS_NR_CLK                                    40
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */