clk: samsung: exynos5433: Add clocks for CMU_PERIS domain

This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use oscclk source clock directly.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 32 insertions, 1 deletions

diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index b5c66f7b83be..5b3397d9843a 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -227,8 +227,39 @@
 #define CLK_PCLK_WDT_ATLAS              8
 #define CLK_PCLK_MCT                    9
 #define CLK_PCLK_HDMI_CEC               10
+#define CLK_ACLK_AHB2APB_PERIS1P        11
+#define CLK_ACLK_AHB2APB_PERIS0P        12
+#define CLK_ACLK_PERISNP_66             13
+#define CLK_PCLK_TZPC12                 14
+#define CLK_PCLK_TZPC11                 15
+#define CLK_PCLK_TZPC10                 16
+#define CLK_PCLK_TZPC9                  17
+#define CLK_PCLK_TZPC8                  18
+#define CLK_PCLK_TZPC7                  19
+#define CLK_PCLK_TZPC6                  20
+#define CLK_PCLK_TZPC5                  21
+#define CLK_PCLK_TZPC4                  22
+#define CLK_PCLK_TZPC3                  23
+#define CLK_PCLK_TZPC2                  24
+#define CLK_PCLK_TZPC1                  25
+#define CLK_PCLK_TZPC0                  26
+#define CLK_PCLK_SECKEY_APBIF           27
+#define CLK_PCLK_CHIPID_APBIF           28
+#define CLK_PCLK_TOPRTC                 29
+#define CLK_PCLK_CUSTOM_EFUSE_APBIF     30
+#define CLK_PCLK_ANTIRBK_CNT_APBIF      31
+#define CLK_PCLK_OTP_CON_APBIF          32
+#define CLK_SCLK_ASV_TB                 33
+#define CLK_SCLK_TMU1                   34
+#define CLK_SCLK_TMU0                   35
+#define CLK_SCLK_SECKEY                 36
+#define CLK_SCLK_CHIPID                 37
+#define CLK_SCLK_TOPRTC                 38
+#define CLK_SCLK_CUSTOM_EFUSE           39
+#define CLK_SCLK_ANTIRBK_CNT            40
+#define CLK_SCLK_OTP_CON                41
 
-#define PERIS_NR_CLK                    11
+#define PERIS_NR_CLK                    42
 
 /* CMU_FSYS */
 #define CLK_MOUT_ACLK_FSYS_200_USER     1