clk: samsung: exynos5433: Add clocks for CMU_PERIC domain

This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on]
Signed-off-by: Inha Song <ideal.song@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 33 insertions, 1 deletions

diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 8f0ee5a13db4..b5c66f7b83be 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -181,8 +181,40 @@
 #define CLK_SCLK_UART2                  34
 #define CLK_SCLK_UART1                  35
 #define CLK_SCLK_UART0                  36
+#define CLK_ACLK_AHB2APB_PERIC2P        37
+#define CLK_ACLK_AHB2APB_PERIC1P        38
+#define CLK_ACLK_AHB2APB_PERIC0P        39
+#define CLK_ACLK_PERICNP_66             40
+#define CLK_PCLK_SCI                    41
+#define CLK_PCLK_GPIO_FINGER            42
+#define CLK_PCLK_GPIO_ESE               43
+#define CLK_PCLK_PWM                    44
+#define CLK_PCLK_SPDIF                  45
+#define CLK_PCLK_PCM1                   46
+#define CLK_PCLK_I2S1                   47
+#define CLK_PCLK_ADCIF                  48
+#define CLK_PCLK_GPIO_TOUCH             49
+#define CLK_PCLK_GPIO_NFC               50
+#define CLK_PCLK_GPIO_PERIC             51
+#define CLK_PCLK_PMU_PERIC              52
+#define CLK_PCLK_SYSREG_PERIC           53
+#define CLK_SCLK_IOCLK_SPI4             54
+#define CLK_SCLK_IOCLK_SPI3             55
+#define CLK_SCLK_SCI                    56
+#define CLK_SCLK_SC_IN                  57
+#define CLK_SCLK_PWM                    58
+#define CLK_SCLK_IOCLK_SPI2             59
+#define CLK_SCLK_IOCLK_SPI1             60
+#define CLK_SCLK_IOCLK_SPI0             61
+#define CLK_SCLK_IOCLK_I2S1_BCLK        62
+#define CLK_SCLK_SPDIF                  63
+#define CLK_SCLK_PCM1                   64
+#define CLK_SCLK_I2S1                   65
 
-#define PERIC_NR_CLK                    37
+#define CLK_DIV_SCLK_SCI                70
+#define CLK_DIV_SCLK_SC_IN              71
+
+#define PERIC_NR_CLK                    72
 
 /* CMU_PERIS */
 #define CLK_PCLK_HPM_APBIF              1