clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support

Add support for the multimedia clock controller found on the APQ8084
based platforms. This will allow the multimedia device drivers to
control their clocks.

Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
[sboyd: Rework parent mapping to avoid conflicts]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

1 files changed, 64 insertions, 0 deletions

diff --git a/include/dt-bindings/reset/qcom,mmcc-apq8084.h b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
new file mode 100644
index 000000000000..c1671396531d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H
+#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H
+
+#define MMSS_SPDM_RESET                 0
+#define MMSS_SPDM_RM_RESET              1
+#define VENUS0_RESET                    2
+#define VPU_RESET                       3
+#define MDSS_RESET                      4
+#define AVSYNC_RESET                    5
+#define CAMSS_PHY0_RESET                6
+#define CAMSS_PHY1_RESET                7
+#define CAMSS_PHY2_RESET                8
+#define CAMSS_CSI0_RESET                9
+#define CAMSS_CSI0PHY_RESET             10
+#define CAMSS_CSI0RDI_RESET             11
+#define CAMSS_CSI0PIX_RESET             12
+#define CAMSS_CSI1_RESET                13
+#define CAMSS_CSI1PHY_RESET             14
+#define CAMSS_CSI1RDI_RESET             15
+#define CAMSS_CSI1PIX_RESET             16
+#define CAMSS_CSI2_RESET                17
+#define CAMSS_CSI2PHY_RESET             18
+#define CAMSS_CSI2RDI_RESET             19
+#define CAMSS_CSI2PIX_RESET             20
+#define CAMSS_CSI3_RESET                21
+#define CAMSS_CSI3PHY_RESET             22
+#define CAMSS_CSI3RDI_RESET             23
+#define CAMSS_CSI3PIX_RESET             24
+#define CAMSS_ISPIF_RESET               25
+#define CAMSS_CCI_RESET                 26
+#define CAMSS_MCLK0_RESET               27
+#define CAMSS_MCLK1_RESET               28
+#define CAMSS_MCLK2_RESET               29
+#define CAMSS_MCLK3_RESET               30
+#define CAMSS_GP0_RESET                 31
+#define CAMSS_GP1_RESET                 32
+#define CAMSS_TOP_RESET                 33
+#define CAMSS_AHB_RESET                 34
+#define CAMSS_MICRO_RESET               35
+#define CAMSS_JPEG_RESET                36
+#define CAMSS_VFE_RESET                 37
+#define CAMSS_CSI_VFE0_RESET            38
+#define CAMSS_CSI_VFE1_RESET            39
+#define OXILI_RESET                     40
+#define OXILICX_RESET                   41
+#define OCMEMCX_RESET                   42
+#define MMSS_RBCRP_RESET                43
+#define MMSSNOCAHB_RESET                44
+#define MMSSNOCAXI_RESET                45
+
+#endif