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authorGeorgi Djakov <gdjakov@mm-sol.com>2014-06-12 12:41:42 -0400
committerStephen Boyd <sboyd@codeaurora.org>2014-07-15 19:38:57 -0400
commit2b46cd23a5a2cf0b8d3583338b63409f5e78e7cd (patch)
tree9c68c3247a0e196252bcceabbe13f4d2f38d362b
parent5424e102815762f835b998536170e791681f6411 (diff)
clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support
Add support for the multimedia clock controller found on the APQ8084 based platforms. This will allow the multimedia device drivers to control their clocks. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> [sboyd: Rework parent mapping to avoid conflicts] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,mmcc.txt1
-rw-r--r--drivers/clk/qcom/Kconfig9
-rw-r--r--drivers/clk/qcom/Makefile1
-rw-r--r--drivers/clk/qcom/mmcc-apq8084.c3352
-rw-r--r--include/dt-bindings/clock/qcom,mmcc-apq8084.h183
-rw-r--r--include/dt-bindings/reset/qcom,mmcc-apq8084.h64
6 files changed, 3610 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
index d572e9964c54..4f1f6be9e66d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
@@ -4,6 +4,7 @@ Qualcomm Multimedia Clock & Reset Controller Binding
4Required properties : 4Required properties :
5- compatible : shall contain only one of the following: 5- compatible : shall contain only one of the following:
6 6
7 "qcom,mmcc-apq8084"
7 "qcom,mmcc-msm8660" 8 "qcom,mmcc-msm8660"
8 "qcom,mmcc-msm8960" 9 "qcom,mmcc-msm8960"
9 "qcom,mmcc-msm8974" 10 "qcom,mmcc-msm8974"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e7516c2a2502..e5f95161d747 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -12,6 +12,15 @@ config APQ_GCC_8084
12 Say Y if you want to use peripheral devices such as UART, SPI, 12 Say Y if you want to use peripheral devices such as UART, SPI,
13 i2c, USB, SD/eMMC, SATA, PCIe, etc. 13 i2c, USB, SD/eMMC, SATA, PCIe, etc.
14 14
15config APQ_MMCC_8084
16 tristate "APQ8084 Multimedia Clock Controller"
17 select APQ_GCC_8084
18 depends on COMMON_CLK_QCOM
19 help
20 Support for the multimedia clock controller on apq8084 devices.
21 Say Y if you want to support multimedia devices such as display,
22 graphics, video encode/decode, camera, etc.
23
15config MSM_GCC_8660 24config MSM_GCC_8660
16 tristate "MSM8660 Global Clock Controller" 25 tristate "MSM8660 Global Clock Controller"
17 depends on COMMON_CLK_QCOM 26 depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 196a5df9125a..f9366261f836 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -9,6 +9,7 @@ clk-qcom-y += clk-branch.o
9clk-qcom-y += reset.o 9clk-qcom-y += reset.o
10 10
11obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o 11obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
12obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
12obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o 13obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
13obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o 14obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
14obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o 15obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
new file mode 100644
index 000000000000..751eea376a2b
--- /dev/null
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -0,0 +1,3352 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/module.h>
17#include <linux/regmap.h>
18#include <linux/reset-controller.h>
19
20#include <dt-bindings/clock/qcom,mmcc-apq8084.h>
21#include <dt-bindings/reset/qcom,mmcc-apq8084.h>
22
23#include "common.h"
24#include "clk-regmap.h"
25#include "clk-pll.h"
26#include "clk-rcg.h"
27#include "clk-branch.h"
28#include "reset.h"
29
30#define P_XO 0
31#define P_MMPLL0 1
32#define P_EDPLINK 1
33#define P_MMPLL1 2
34#define P_HDMIPLL 2
35#define P_GPLL0 3
36#define P_EDPVCO 3
37#define P_MMPLL4 4
38#define P_DSI0PLL 4
39#define P_DSI0PLL_BYTE 4
40#define P_MMPLL2 4
41#define P_MMPLL3 4
42#define P_GPLL1 5
43#define P_DSI1PLL 5
44#define P_DSI1PLL_BYTE 5
45#define P_MMSLEEP 6
46
47static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
48 [P_XO] = 0,
49 [P_MMPLL0] = 1,
50 [P_MMPLL1] = 2,
51 [P_GPLL0] = 5,
52};
53
54static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
55 "xo",
56 "mmpll0_vote",
57 "mmpll1_vote",
58 "mmss_gpll0_vote",
59};
60
61static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
62 [P_XO] = 0,
63 [P_MMPLL0] = 1,
64 [P_HDMIPLL] = 4,
65 [P_GPLL0] = 5,
66 [P_DSI0PLL] = 2,
67 [P_DSI1PLL] = 3,
68};
69
70static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
71 "xo",
72 "mmpll0_vote",
73 "hdmipll",
74 "mmss_gpll0_vote",
75 "dsi0pll",
76 "dsi1pll",
77};
78
79static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
80 [P_XO] = 0,
81 [P_MMPLL0] = 1,
82 [P_MMPLL1] = 2,
83 [P_GPLL0] = 5,
84 [P_MMPLL2] = 3,
85};
86
87static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
88 "xo",
89 "mmpll0_vote",
90 "mmpll1_vote",
91 "mmss_gpll0_vote",
92 "mmpll2",
93};
94
95static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
96 [P_XO] = 0,
97 [P_MMPLL0] = 1,
98 [P_MMPLL1] = 2,
99 [P_GPLL0] = 5,
100 [P_MMPLL3] = 3,
101};
102
103static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
104 "xo",
105 "mmpll0_vote",
106 "mmpll1_vote",
107 "mmss_gpll0_vote",
108 "mmpll3",
109};
110
111static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
112 [P_XO] = 0,
113 [P_EDPLINK] = 4,
114 [P_HDMIPLL] = 3,
115 [P_EDPVCO] = 5,
116 [P_DSI0PLL] = 1,
117 [P_DSI1PLL] = 2,
118};
119
120static const char *mmcc_xo_dsi_hdmi_edp[] = {
121 "xo",
122 "edp_link_clk",
123 "hdmipll",
124 "edp_vco_div",
125 "dsi0pll",
126 "dsi1pll",
127};
128
129static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
130 [P_XO] = 0,
131 [P_EDPLINK] = 4,
132 [P_HDMIPLL] = 3,
133 [P_GPLL0] = 5,
134 [P_DSI0PLL] = 1,
135 [P_DSI1PLL] = 2,
136};
137
138static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
139 "xo",
140 "edp_link_clk",
141 "hdmipll",
142 "gpll0_vote",
143 "dsi0pll",
144 "dsi1pll",
145};
146
147static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
148 [P_XO] = 0,
149 [P_EDPLINK] = 4,
150 [P_HDMIPLL] = 3,
151 [P_GPLL0] = 5,
152 [P_DSI0PLL_BYTE] = 1,
153 [P_DSI1PLL_BYTE] = 2,
154};
155
156static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
157 "xo",
158 "edp_link_clk",
159 "hdmipll",
160 "gpll0_vote",
161 "dsi0pllbyte",
162 "dsi1pllbyte",
163};
164
165static const u8 mmcc_xo_mmpll0_1_4_gpll0_map[] = {
166 [P_XO] = 0,
167 [P_MMPLL0] = 1,
168 [P_MMPLL1] = 2,
169 [P_GPLL0] = 5,
170 [P_MMPLL4] = 3,
171};
172
173static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
174 "xo",
175 "mmpll0",
176 "mmpll1",
177 "mmpll4",
178 "gpll0",
179};
180
181static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
182 [P_XO] = 0,
183 [P_MMPLL0] = 1,
184 [P_MMPLL1] = 2,
185 [P_MMPLL4] = 3,
186 [P_GPLL0] = 5,
187 [P_GPLL1] = 4,
188};
189
190static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
191 "xo",
192 "mmpll0",
193 "mmpll1",
194 "mmpll4",
195 "gpll1",
196 "gpll0",
197};
198
199static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
200 [P_XO] = 0,
201 [P_MMPLL0] = 1,
202 [P_MMPLL1] = 2,
203 [P_MMPLL4] = 3,
204 [P_GPLL0] = 5,
205 [P_GPLL1] = 4,
206 [P_MMSLEEP] = 6,
207};
208
209static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
210 "xo",
211 "mmpll0",
212 "mmpll1",
213 "mmpll4",
214 "gpll1",
215 "gpll0",
216 "sleep_clk_src",
217};
218
219#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
220
221static struct clk_pll mmpll0 = {
222 .l_reg = 0x0004,
223 .m_reg = 0x0008,
224 .n_reg = 0x000c,
225 .config_reg = 0x0014,
226 .mode_reg = 0x0000,
227 .status_reg = 0x001c,
228 .status_bit = 17,
229 .clkr.hw.init = &(struct clk_init_data){
230 .name = "mmpll0",
231 .parent_names = (const char *[]){ "xo" },
232 .num_parents = 1,
233 .ops = &clk_pll_ops,
234 },
235};
236
237static struct clk_regmap mmpll0_vote = {
238 .enable_reg = 0x0100,
239 .enable_mask = BIT(0),
240 .hw.init = &(struct clk_init_data){
241 .name = "mmpll0_vote",
242 .parent_names = (const char *[]){ "mmpll0" },
243 .num_parents = 1,
244 .ops = &clk_pll_vote_ops,
245 },
246};
247
248static struct clk_pll mmpll1 = {
249 .l_reg = 0x0044,
250 .m_reg = 0x0048,
251 .n_reg = 0x004c,
252 .config_reg = 0x0050,
253 .mode_reg = 0x0040,
254 .status_reg = 0x005c,
255 .status_bit = 17,
256 .clkr.hw.init = &(struct clk_init_data){
257 .name = "mmpll1",
258 .parent_names = (const char *[]){ "xo" },
259 .num_parents = 1,
260 .ops = &clk_pll_ops,
261 },
262};
263
264static struct clk_regmap mmpll1_vote = {
265 .enable_reg = 0x0100,
266 .enable_mask = BIT(1),
267 .hw.init = &(struct clk_init_data){
268 .name = "mmpll1_vote",
269 .parent_names = (const char *[]){ "mmpll1" },
270 .num_parents = 1,
271 .ops = &clk_pll_vote_ops,
272 },
273};
274
275static struct clk_pll mmpll2 = {
276 .l_reg = 0x4104,
277 .m_reg = 0x4108,
278 .n_reg = 0x410c,
279 .config_reg = 0x4110,
280 .mode_reg = 0x4100,
281 .status_reg = 0x411c,
282 .clkr.hw.init = &(struct clk_init_data){
283 .name = "mmpll2",
284 .parent_names = (const char *[]){ "xo" },
285 .num_parents = 1,
286 .ops = &clk_pll_ops,
287 },
288};
289
290static struct clk_pll mmpll3 = {
291 .l_reg = 0x0084,
292 .m_reg = 0x0088,
293 .n_reg = 0x008c,
294 .config_reg = 0x0090,
295 .mode_reg = 0x0080,
296 .status_reg = 0x009c,
297 .status_bit = 17,
298 .clkr.hw.init = &(struct clk_init_data){
299 .name = "mmpll3",
300 .parent_names = (const char *[]){ "xo" },
301 .num_parents = 1,
302 .ops = &clk_pll_ops,
303 },
304};
305
306static struct clk_pll mmpll4 = {
307 .l_reg = 0x00a4,
308 .m_reg = 0x00a8,
309 .n_reg = 0x00ac,
310 .config_reg = 0x00b0,
311 .mode_reg = 0x0080,
312 .status_reg = 0x00bc,
313 .clkr.hw.init = &(struct clk_init_data){
314 .name = "mmpll4",
315 .parent_names = (const char *[]){ "xo" },
316 .num_parents = 1,
317 .ops = &clk_pll_ops,
318 },
319};
320
321static struct clk_rcg2 mmss_ahb_clk_src = {
322 .cmd_rcgr = 0x5000,
323 .hid_width = 5,
324 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
325 .clkr.hw.init = &(struct clk_init_data){
326 .name = "mmss_ahb_clk_src",
327 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
328 .num_parents = 4,
329 .ops = &clk_rcg2_ops,
330 },
331};
332
333static struct freq_tbl ftbl_mmss_axi_clk[] = {
334 F(19200000, P_XO, 1, 0, 0),
335 F(37500000, P_GPLL0, 16, 0, 0),
336 F(50000000, P_GPLL0, 12, 0, 0),
337 F(75000000, P_GPLL0, 8, 0, 0),
338 F(100000000, P_GPLL0, 6, 0, 0),
339 F(150000000, P_GPLL0, 4, 0, 0),
340 F(333430000, P_MMPLL1, 3.5, 0, 0),
341 F(400000000, P_MMPLL0, 2, 0, 0),
342 F(466800000, P_MMPLL1, 2.5, 0, 0),
343};
344
345static struct clk_rcg2 mmss_axi_clk_src = {
346 .cmd_rcgr = 0x5040,
347 .hid_width = 5,
348 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
349 .freq_tbl = ftbl_mmss_axi_clk,
350 .clkr.hw.init = &(struct clk_init_data){
351 .name = "mmss_axi_clk_src",
352 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
353 .num_parents = 4,
354 .ops = &clk_rcg2_ops,
355 },
356};
357
358static struct freq_tbl ftbl_ocmemnoc_clk[] = {
359 F(19200000, P_XO, 1, 0, 0),
360 F(37500000, P_GPLL0, 16, 0, 0),
361 F(50000000, P_GPLL0, 12, 0, 0),
362 F(75000000, P_GPLL0, 8, 0, 0),
363 F(109090000, P_GPLL0, 5.5, 0, 0),
364 F(150000000, P_GPLL0, 4, 0, 0),
365 F(228570000, P_MMPLL0, 3.5, 0, 0),
366 F(320000000, P_MMPLL0, 2.5, 0, 0),
367};
368
369static struct clk_rcg2 ocmemnoc_clk_src = {
370 .cmd_rcgr = 0x5090,
371 .hid_width = 5,
372 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
373 .freq_tbl = ftbl_ocmemnoc_clk,
374 .clkr.hw.init = &(struct clk_init_data){
375 .name = "ocmemnoc_clk_src",
376 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
377 .num_parents = 4,
378 .ops = &clk_rcg2_ops,
379 },
380};
381
382static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
383 F(100000000, P_GPLL0, 6, 0, 0),
384 F(200000000, P_MMPLL0, 4, 0, 0),
385 { }
386};
387
388static struct clk_rcg2 csi0_clk_src = {
389 .cmd_rcgr = 0x3090,
390 .hid_width = 5,
391 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
392 .freq_tbl = ftbl_camss_csi0_3_clk,
393 .clkr.hw.init = &(struct clk_init_data){
394 .name = "csi0_clk_src",
395 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
396 .num_parents = 5,
397 .ops = &clk_rcg2_ops,
398 },
399};
400
401static struct clk_rcg2 csi1_clk_src = {
402 .cmd_rcgr = 0x3100,
403 .hid_width = 5,
404 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
405 .freq_tbl = ftbl_camss_csi0_3_clk,
406 .clkr.hw.init = &(struct clk_init_data){
407 .name = "csi1_clk_src",
408 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
409 .num_parents = 5,
410 .ops = &clk_rcg2_ops,
411 },
412};
413
414static struct clk_rcg2 csi2_clk_src = {
415 .cmd_rcgr = 0x3160,
416 .hid_width = 5,
417 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
418 .freq_tbl = ftbl_camss_csi0_3_clk,
419 .clkr.hw.init = &(struct clk_init_data){
420 .name = "csi2_clk_src",
421 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
422 .num_parents = 5,
423 .ops = &clk_rcg2_ops,
424 },
425};
426
427static struct clk_rcg2 csi3_clk_src = {
428 .cmd_rcgr = 0x31c0,
429 .hid_width = 5,
430 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
431 .freq_tbl = ftbl_camss_csi0_3_clk,
432 .clkr.hw.init = &(struct clk_init_data){
433 .name = "csi3_clk_src",
434 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
435 .num_parents = 5,
436 .ops = &clk_rcg2_ops,
437 },
438};
439
440static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
441 F(37500000, P_GPLL0, 16, 0, 0),
442 F(50000000, P_GPLL0, 12, 0, 0),
443 F(60000000, P_GPLL0, 10, 0, 0),
444 F(80000000, P_GPLL0, 7.5, 0, 0),
445 F(100000000, P_GPLL0, 6, 0, 0),
446 F(109090000, P_GPLL0, 5.5, 0, 0),
447 F(133330000, P_GPLL0, 4.5, 0, 0),
448 F(200000000, P_GPLL0, 3, 0, 0),
449 F(228570000, P_MMPLL0, 3.5, 0, 0),
450 F(266670000, P_MMPLL0, 3, 0, 0),
451 F(320000000, P_MMPLL0, 2.5, 0, 0),
452 F(465000000, P_MMPLL4, 2, 0, 0),
453 F(600000000, P_GPLL0, 1, 0, 0),
454 { }
455};
456
457static struct clk_rcg2 vfe0_clk_src = {
458 .cmd_rcgr = 0x3600,
459 .hid_width = 5,
460 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
461 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
462 .clkr.hw.init = &(struct clk_init_data){
463 .name = "vfe0_clk_src",
464 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
465 .num_parents = 5,
466 .ops = &clk_rcg2_ops,
467 },
468};
469
470static struct clk_rcg2 vfe1_clk_src = {
471 .cmd_rcgr = 0x3620,
472 .hid_width = 5,
473 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
474 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
475 .clkr.hw.init = &(struct clk_init_data){
476 .name = "vfe1_clk_src",
477 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
478 .num_parents = 5,
479 .ops = &clk_rcg2_ops,
480 },
481};
482
483static struct freq_tbl ftbl_mdss_mdp_clk[] = {
484 F(37500000, P_GPLL0, 16, 0, 0),
485 F(60000000, P_GPLL0, 10, 0, 0),
486 F(75000000, P_GPLL0, 8, 0, 0),
487 F(85710000, P_GPLL0, 7, 0, 0),
488 F(100000000, P_GPLL0, 6, 0, 0),
489 F(150000000, P_GPLL0, 4, 0, 0),
490 F(160000000, P_MMPLL0, 5, 0, 0),
491 F(200000000, P_MMPLL0, 4, 0, 0),
492 F(228570000, P_MMPLL0, 3.5, 0, 0),
493 F(300000000, P_GPLL0, 2, 0, 0),
494 F(320000000, P_MMPLL0, 2.5, 0, 0),
495 { }
496};
497
498static struct clk_rcg2 mdp_clk_src = {
499 .cmd_rcgr = 0x2040,
500 .hid_width = 5,
501 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
502 .freq_tbl = ftbl_mdss_mdp_clk,
503 .clkr.hw.init = &(struct clk_init_data){
504 .name = "mdp_clk_src",
505 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
506 .num_parents = 6,
507 .ops = &clk_rcg2_ops,
508 },
509};
510
511static struct clk_rcg2 gfx3d_clk_src = {
512 .cmd_rcgr = 0x4000,
513 .hid_width = 5,
514 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
515 .clkr.hw.init = &(struct clk_init_data){
516 .name = "gfx3d_clk_src",
517 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
518 .num_parents = 5,
519 .ops = &clk_rcg2_ops,
520 },
521};
522
523static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
524 F(75000000, P_GPLL0, 8, 0, 0),
525 F(133330000, P_GPLL0, 4.5, 0, 0),
526 F(200000000, P_GPLL0, 3, 0, 0),
527 F(228570000, P_MMPLL0, 3.5, 0, 0),
528 F(266670000, P_MMPLL0, 3, 0, 0),
529 F(320000000, P_MMPLL0, 2.5, 0, 0),
530 { }
531};
532
533static struct clk_rcg2 jpeg0_clk_src = {
534 .cmd_rcgr = 0x3500,
535 .hid_width = 5,
536 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
537 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
538 .clkr.hw.init = &(struct clk_init_data){
539 .name = "jpeg0_clk_src",
540 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
541 .num_parents = 5,
542 .ops = &clk_rcg2_ops,
543 },
544};
545
546static struct clk_rcg2 jpeg1_clk_src = {
547 .cmd_rcgr = 0x3520,
548 .hid_width = 5,
549 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
550 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
551 .clkr.hw.init = &(struct clk_init_data){
552 .name = "jpeg1_clk_src",
553 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
554 .num_parents = 5,
555 .ops = &clk_rcg2_ops,
556 },
557};
558
559static struct clk_rcg2 jpeg2_clk_src = {
560 .cmd_rcgr = 0x3540,
561 .hid_width = 5,
562 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
563 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
564 .clkr.hw.init = &(struct clk_init_data){
565 .name = "jpeg2_clk_src",
566 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
567 .num_parents = 5,
568 .ops = &clk_rcg2_ops,
569 },
570};
571
572static struct freq_tbl pixel_freq_tbl[] = {
573 { .src = P_DSI0PLL },
574 { }
575};
576
577static struct clk_rcg2 pclk0_clk_src = {
578 .cmd_rcgr = 0x2000,
579 .mnd_width = 8,
580 .hid_width = 5,
581 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
582 .freq_tbl = pixel_freq_tbl,
583 .clkr.hw.init = &(struct clk_init_data){
584 .name = "pclk0_clk_src",
585 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
586 .num_parents = 6,
587 .ops = &clk_pixel_ops,
588 .flags = CLK_SET_RATE_PARENT,
589 },
590};
591
592static struct clk_rcg2 pclk1_clk_src = {
593 .cmd_rcgr = 0x2020,
594 .mnd_width = 8,
595 .hid_width = 5,
596 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
597 .freq_tbl = pixel_freq_tbl,
598 .clkr.hw.init = &(struct clk_init_data){
599 .name = "pclk1_clk_src",
600 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
601 .num_parents = 6,
602 .ops = &clk_pixel_ops,
603 .flags = CLK_SET_RATE_PARENT,
604 },
605};
606
607static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
608 F(50000000, P_GPLL0, 12, 0, 0),
609 F(100000000, P_GPLL0, 6, 0, 0),
610 F(133330000, P_GPLL0, 4.5, 0, 0),
611 F(200000000, P_MMPLL0, 4, 0, 0),
612 F(266670000, P_MMPLL0, 3, 0, 0),
613 F(465000000, P_MMPLL3, 2, 0, 0),
614 { }
615};
616
617static struct clk_rcg2 vcodec0_clk_src = {
618 .cmd_rcgr = 0x1000,
619 .mnd_width = 8,
620 .hid_width = 5,
621 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
622 .freq_tbl = ftbl_venus0_vcodec0_clk,
623 .clkr.hw.init = &(struct clk_init_data){
624 .name = "vcodec0_clk_src",
625 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
626 .num_parents = 5,
627 .ops = &clk_rcg2_ops,
628 },
629};
630
631static struct freq_tbl ftbl_avsync_vp_clk[] = {
632 F(150000000, P_GPLL0, 4, 0, 0),
633 F(320000000, P_MMPLL0, 2.5, 0, 0),
634 { }
635};
636
637static struct clk_rcg2 vp_clk_src = {
638 .cmd_rcgr = 0x2430,
639 .hid_width = 5,
640 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
641 .freq_tbl = ftbl_avsync_vp_clk,
642 .clkr.hw.init = &(struct clk_init_data){
643 .name = "vp_clk_src",
644 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
645 .num_parents = 4,
646 .ops = &clk_rcg2_ops,
647 },
648};
649
650static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
651 F(19200000, P_XO, 1, 0, 0),
652 { }
653};
654
655static struct clk_rcg2 cci_clk_src = {
656 .cmd_rcgr = 0x3300,
657 .mnd_width = 8,
658 .hid_width = 5,
659 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
660 .freq_tbl = ftbl_camss_cci_cci_clk,
661 .clkr.hw.init = &(struct clk_init_data){
662 .name = "cci_clk_src",
663 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
664 .num_parents = 6,
665 .ops = &clk_rcg2_ops,
666 },
667};
668
669static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
670 F(10000, P_XO, 16, 1, 120),
671 F(24000, P_XO, 16, 1, 50),
672 F(6000000, P_GPLL0, 10, 1, 10),
673 F(12000000, P_GPLL0, 10, 1, 5),
674 F(13000000, P_GPLL0, 4, 13, 150),
675 F(24000000, P_GPLL0, 5, 1, 5),
676 { }
677};
678
679static struct clk_rcg2 camss_gp0_clk_src = {
680 .cmd_rcgr = 0x3420,
681 .mnd_width = 8,
682 .hid_width = 5,
683 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
684 .freq_tbl = ftbl_camss_gp0_1_clk,
685 .clkr.hw.init = &(struct clk_init_data){
686 .name = "camss_gp0_clk_src",
687 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
688 .num_parents = 7,
689 .ops = &clk_rcg2_ops,
690 },
691};
692
693static struct clk_rcg2 camss_gp1_clk_src = {
694 .cmd_rcgr = 0x3450,
695 .mnd_width = 8,
696 .hid_width = 5,
697 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
698 .freq_tbl = ftbl_camss_gp0_1_clk,
699 .clkr.hw.init = &(struct clk_init_data){
700 .name = "camss_gp1_clk_src",
701 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
702 .num_parents = 7,
703 .ops = &clk_rcg2_ops,
704 },
705};
706
707static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
708 F(4800000, P_XO, 4, 0, 0),
709 F(6000000, P_GPLL0, 10, 1, 10),
710 F(8000000, P_GPLL0, 15, 1, 5),
711 F(9600000, P_XO, 2, 0, 0),
712 F(16000000, P_MMPLL0, 10, 1, 5),
713 F(19200000, P_XO, 1, 0, 0),
714 F(24000000, P_GPLL0, 5, 1, 5),
715 F(32000000, P_MMPLL0, 5, 1, 5),
716 F(48000000, P_GPLL0, 12.5, 0, 0),
717 F(64000000, P_MMPLL0, 12.5, 0, 0),
718 { }
719};
720
721static struct clk_rcg2 mclk0_clk_src = {
722 .cmd_rcgr = 0x3360,
723 .mnd_width = 8,
724 .hid_width = 5,
725 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
726 .freq_tbl = ftbl_camss_mclk0_3_clk,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "mclk0_clk_src",
729 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
730 .num_parents = 6,
731 .ops = &clk_rcg2_ops,
732 },
733};
734
735static struct clk_rcg2 mclk1_clk_src = {
736 .cmd_rcgr = 0x3390,
737 .mnd_width = 8,
738 .hid_width = 5,
739 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
740 .freq_tbl = ftbl_camss_mclk0_3_clk,
741 .clkr.hw.init = &(struct clk_init_data){
742 .name = "mclk1_clk_src",
743 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
744 .num_parents = 6,
745 .ops = &clk_rcg2_ops,
746 },
747};
748
749static struct clk_rcg2 mclk2_clk_src = {
750 .cmd_rcgr = 0x33c0,
751 .mnd_width = 8,
752 .hid_width = 5,
753 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
754 .freq_tbl = ftbl_camss_mclk0_3_clk,
755 .clkr.hw.init = &(struct clk_init_data){
756 .name = "mclk2_clk_src",
757 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
758 .num_parents = 6,
759 .ops = &clk_rcg2_ops,
760 },
761};
762
763static struct clk_rcg2 mclk3_clk_src = {
764 .cmd_rcgr = 0x33f0,
765 .mnd_width = 8,
766 .hid_width = 5,
767 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
768 .freq_tbl = ftbl_camss_mclk0_3_clk,
769 .clkr.hw.init = &(struct clk_init_data){
770 .name = "mclk3_clk_src",
771 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
772 .num_parents = 6,
773 .ops = &clk_rcg2_ops,
774 },
775};
776
777static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
778 F(100000000, P_GPLL0, 6, 0, 0),
779 F(200000000, P_MMPLL0, 4, 0, 0),
780 { }
781};
782
783static struct clk_rcg2 csi0phytimer_clk_src = {
784 .cmd_rcgr = 0x3000,
785 .hid_width = 5,
786 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
787 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "csi0phytimer_clk_src",
790 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
791 .num_parents = 5,
792 .ops = &clk_rcg2_ops,
793 },
794};
795
796static struct clk_rcg2 csi1phytimer_clk_src = {
797 .cmd_rcgr = 0x3030,
798 .hid_width = 5,
799 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
800 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "csi1phytimer_clk_src",
803 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
804 .num_parents = 5,
805 .ops = &clk_rcg2_ops,
806 },
807};
808
809static struct clk_rcg2 csi2phytimer_clk_src = {
810 .cmd_rcgr = 0x3060,
811 .hid_width = 5,
812 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
813 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
814 .clkr.hw.init = &(struct clk_init_data){
815 .name = "csi2phytimer_clk_src",
816 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
817 .num_parents = 5,
818 .ops = &clk_rcg2_ops,
819 },
820};
821
822static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
823 F(133330000, P_GPLL0, 4.5, 0, 0),
824 F(266670000, P_MMPLL0, 3, 0, 0),
825 F(320000000, P_MMPLL0, 2.5, 0, 0),
826 F(372000000, P_MMPLL4, 2.5, 0, 0),
827 F(465000000, P_MMPLL4, 2, 0, 0),
828 F(600000000, P_GPLL0, 1, 0, 0),
829 { }
830};
831
832static struct clk_rcg2 cpp_clk_src = {
833 .cmd_rcgr = 0x3640,
834 .hid_width = 5,
835 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
836 .freq_tbl = ftbl_camss_vfe_cpp_clk,
837 .clkr.hw.init = &(struct clk_init_data){
838 .name = "cpp_clk_src",
839 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
840 .num_parents = 5,
841 .ops = &clk_rcg2_ops,
842 },
843};
844
845static struct freq_tbl byte_freq_tbl[] = {
846 { .src = P_DSI0PLL_BYTE },
847 { }
848};
849
850static struct clk_rcg2 byte0_clk_src = {
851 .cmd_rcgr = 0x2120,
852 .hid_width = 5,
853 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
854 .freq_tbl = byte_freq_tbl,
855 .clkr.hw.init = &(struct clk_init_data){
856 .name = "byte0_clk_src",
857 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
858 .num_parents = 6,
859 .ops = &clk_byte_ops,
860 .flags = CLK_SET_RATE_PARENT,
861 },
862};
863
864static struct clk_rcg2 byte1_clk_src = {
865 .cmd_rcgr = 0x2140,
866 .hid_width = 5,
867 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
868 .freq_tbl = byte_freq_tbl,
869 .clkr.hw.init = &(struct clk_init_data){
870 .name = "byte1_clk_src",
871 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
872 .num_parents = 6,
873 .ops = &clk_byte_ops,
874 .flags = CLK_SET_RATE_PARENT,
875 },
876};
877
878static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
879 F(19200000, P_XO, 1, 0, 0),
880 { }
881};
882
883static struct clk_rcg2 edpaux_clk_src = {
884 .cmd_rcgr = 0x20e0,
885 .hid_width = 5,
886 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
887 .freq_tbl = ftbl_mdss_edpaux_clk,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "edpaux_clk_src",
890 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
891 .num_parents = 4,
892 .ops = &clk_rcg2_ops,
893 },
894};
895
896static struct freq_tbl ftbl_mdss_edplink_clk[] = {
897 F(135000000, P_EDPLINK, 2, 0, 0),
898 F(270000000, P_EDPLINK, 11, 0, 0),
899 { }
900};
901
902static struct clk_rcg2 edplink_clk_src = {
903 .cmd_rcgr = 0x20c0,
904 .hid_width = 5,
905 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
906 .freq_tbl = ftbl_mdss_edplink_clk,
907 .clkr.hw.init = &(struct clk_init_data){
908 .name = "edplink_clk_src",
909 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
910 .num_parents = 6,
911 .ops = &clk_rcg2_ops,
912 .flags = CLK_SET_RATE_PARENT,
913 },
914};
915
916static struct freq_tbl edp_pixel_freq_tbl[] = {
917 { .src = P_EDPVCO },
918 { }
919};
920
921static struct clk_rcg2 edppixel_clk_src = {
922 .cmd_rcgr = 0x20a0,
923 .mnd_width = 8,
924 .hid_width = 5,
925 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
926 .freq_tbl = edp_pixel_freq_tbl,
927 .clkr.hw.init = &(struct clk_init_data){
928 .name = "edppixel_clk_src",
929 .parent_names = mmcc_xo_dsi_hdmi_edp,
930 .num_parents = 6,
931 .ops = &clk_edp_pixel_ops,
932 },
933};
934
935static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
936 F(19200000, P_XO, 1, 0, 0),
937 { }
938};
939
940static struct clk_rcg2 esc0_clk_src = {
941 .cmd_rcgr = 0x2160,
942 .hid_width = 5,
943 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
944 .freq_tbl = ftbl_mdss_esc0_1_clk,
945 .clkr.hw.init = &(struct clk_init_data){
946 .name = "esc0_clk_src",
947 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
948 .num_parents = 6,
949 .ops = &clk_rcg2_ops,
950 },
951};
952
953static struct clk_rcg2 esc1_clk_src = {
954 .cmd_rcgr = 0x2180,
955 .hid_width = 5,
956 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
957 .freq_tbl = ftbl_mdss_esc0_1_clk,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "esc1_clk_src",
960 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
961 .num_parents = 6,
962 .ops = &clk_rcg2_ops,
963 },
964};
965
966static struct freq_tbl extpclk_freq_tbl[] = {
967 { .src = P_HDMIPLL },
968 { }
969};
970
971static struct clk_rcg2 extpclk_clk_src = {
972 .cmd_rcgr = 0x2060,
973 .hid_width = 5,
974 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
975 .freq_tbl = extpclk_freq_tbl,
976 .clkr.hw.init = &(struct clk_init_data){
977 .name = "extpclk_clk_src",
978 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
979 .num_parents = 6,
980 .ops = &clk_byte_ops,
981 .flags = CLK_SET_RATE_PARENT,
982 },
983};
984
985static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
986 F(19200000, P_XO, 1, 0, 0),
987 { }
988};
989
990static struct clk_rcg2 hdmi_clk_src = {
991 .cmd_rcgr = 0x2100,
992 .hid_width = 5,
993 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
994 .freq_tbl = ftbl_mdss_hdmi_clk,
995 .clkr.hw.init = &(struct clk_init_data){
996 .name = "hdmi_clk_src",
997 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
998 .num_parents = 4,
999 .ops = &clk_rcg2_ops,
1000 },
1001};
1002
1003static struct freq_tbl ftbl_mdss_vsync_clk[] = {
1004 F(19200000, P_XO, 1, 0, 0),
1005 { }
1006};
1007
1008static struct clk_rcg2 vsync_clk_src = {
1009 .cmd_rcgr = 0x2080,
1010 .hid_width = 5,
1011 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1012 .freq_tbl = ftbl_mdss_vsync_clk,
1013 .clkr.hw.init = &(struct clk_init_data){
1014 .name = "vsync_clk_src",
1015 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1016 .num_parents = 4,
1017 .ops = &clk_rcg2_ops,
1018 },
1019};
1020
1021static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1022 F(50000000, P_GPLL0, 12, 0, 0),
1023 { }
1024};
1025
1026static struct clk_rcg2 rbcpr_clk_src = {
1027 .cmd_rcgr = 0x4060,
1028 .hid_width = 5,
1029 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1030 .freq_tbl = ftbl_mmss_rbcpr_clk,
1031 .clkr.hw.init = &(struct clk_init_data){
1032 .name = "rbcpr_clk_src",
1033 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1034 .num_parents = 4,
1035 .ops = &clk_rcg2_ops,
1036 },
1037};
1038
1039static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1040 F(19200000, P_XO, 1, 0, 0),
1041 { }
1042};
1043
1044static struct clk_rcg2 rbbmtimer_clk_src = {
1045 .cmd_rcgr = 0x4090,
1046 .hid_width = 5,
1047 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1048 .freq_tbl = ftbl_oxili_rbbmtimer_clk,
1049 .clkr.hw.init = &(struct clk_init_data){
1050 .name = "rbbmtimer_clk_src",
1051 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1052 .num_parents = 4,
1053 .ops = &clk_rcg2_ops,
1054 },
1055};
1056
1057static struct freq_tbl ftbl_vpu_maple_clk[] = {
1058 F(50000000, P_GPLL0, 12, 0, 0),
1059 F(100000000, P_GPLL0, 6, 0, 0),
1060 F(133330000, P_GPLL0, 4.5, 0, 0),
1061 F(200000000, P_MMPLL0, 4, 0, 0),
1062 F(266670000, P_MMPLL0, 3, 0, 0),
1063 F(465000000, P_MMPLL3, 2, 0, 0),
1064 { }
1065};
1066
1067static struct clk_rcg2 maple_clk_src = {
1068 .cmd_rcgr = 0x1320,
1069 .hid_width = 5,
1070 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1071 .freq_tbl = ftbl_vpu_maple_clk,
1072 .clkr.hw.init = &(struct clk_init_data){
1073 .name = "maple_clk_src",
1074 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1075 .num_parents = 4,
1076 .ops = &clk_rcg2_ops,
1077 },
1078};
1079
1080static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1081 F(50000000, P_GPLL0, 12, 0, 0),
1082 F(100000000, P_GPLL0, 6, 0, 0),
1083 F(200000000, P_MMPLL0, 4, 0, 0),
1084 F(320000000, P_MMPLL0, 2.5, 0, 0),
1085 F(400000000, P_MMPLL0, 2, 0, 0),
1086 { }
1087};
1088
1089static struct clk_rcg2 vdp_clk_src = {
1090 .cmd_rcgr = 0x1300,
1091 .hid_width = 5,
1092 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1093 .freq_tbl = ftbl_vpu_vdp_clk,
1094 .clkr.hw.init = &(struct clk_init_data){
1095 .name = "vdp_clk_src",
1096 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1097 .num_parents = 4,
1098 .ops = &clk_rcg2_ops,
1099 },
1100};
1101
1102static struct freq_tbl ftbl_vpu_bus_clk[] = {
1103 F(40000000, P_GPLL0, 15, 0, 0),
1104 F(80000000, P_MMPLL0, 10, 0, 0),
1105 { }
1106};
1107
1108static struct clk_rcg2 vpu_bus_clk_src = {
1109 .cmd_rcgr = 0x1340,
1110 .hid_width = 5,
1111 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1112 .freq_tbl = ftbl_vpu_bus_clk,
1113 .clkr.hw.init = &(struct clk_init_data){
1114 .name = "vpu_bus_clk_src",
1115 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1116 .num_parents = 4,
1117 .ops = &clk_rcg2_ops,
1118 },
1119};
1120
1121static struct clk_branch mmss_cxo_clk = {
1122 .halt_reg = 0x5104,
1123 .clkr = {
1124 .enable_reg = 0x5104,
1125 .enable_mask = BIT(0),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "mmss_cxo_clk",
1128 .parent_names = (const char *[]){ "xo" },
1129 .num_parents = 1,
1130 .flags = CLK_SET_RATE_PARENT,
1131 .ops = &clk_branch2_ops,
1132 },
1133 },
1134};
1135
1136static struct clk_branch mmss_sleepclk_clk = {
1137 .halt_reg = 0x5100,
1138 .clkr = {
1139 .enable_reg = 0x5100,
1140 .enable_mask = BIT(0),
1141 .hw.init = &(struct clk_init_data){
1142 .name = "mmss_sleepclk_clk",
1143 .parent_names = (const char *[]){
1144 "sleep_clk_src",
1145 },
1146 .num_parents = 1,
1147 .flags = CLK_SET_RATE_PARENT,
1148 .ops = &clk_branch2_ops,
1149 },
1150 },
1151};
1152
1153static struct clk_branch avsync_ahb_clk = {
1154 .halt_reg = 0x2414,
1155 .clkr = {
1156 .enable_reg = 0x2414,
1157 .enable_mask = BIT(0),
1158 .hw.init = &(struct clk_init_data){
1159 .name = "avsync_ahb_clk",
1160 .parent_names = (const char *[]){
1161 "mmss_ahb_clk_src",
1162 },
1163 .num_parents = 1,
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_branch2_ops,
1166 },
1167 },
1168};
1169
1170static struct clk_branch avsync_edppixel_clk = {
1171 .halt_reg = 0x2418,
1172 .clkr = {
1173 .enable_reg = 0x2418,
1174 .enable_mask = BIT(0),
1175 .hw.init = &(struct clk_init_data){
1176 .name = "avsync_edppixel_clk",
1177 .parent_names = (const char *[]){
1178 "edppixel_clk_src",
1179 },
1180 .num_parents = 1,
1181 .flags = CLK_SET_RATE_PARENT,
1182 .ops = &clk_branch2_ops,
1183 },
1184 },
1185};
1186
1187static struct clk_branch avsync_extpclk_clk = {
1188 .halt_reg = 0x2410,
1189 .clkr = {
1190 .enable_reg = 0x2410,
1191 .enable_mask = BIT(0),
1192 .hw.init = &(struct clk_init_data){
1193 .name = "avsync_extpclk_clk",
1194 .parent_names = (const char *[]){
1195 "extpclk_clk_src",
1196 },
1197 .num_parents = 1,
1198 .flags = CLK_SET_RATE_PARENT,
1199 .ops = &clk_branch2_ops,
1200 },
1201 },
1202};
1203
1204static struct clk_branch avsync_pclk0_clk = {
1205 .halt_reg = 0x241c,
1206 .clkr = {
1207 .enable_reg = 0x241c,
1208 .enable_mask = BIT(0),
1209 .hw.init = &(struct clk_init_data){
1210 .name = "avsync_pclk0_clk",
1211 .parent_names = (const char *[]){
1212 "pclk0_clk_src",
1213 },
1214 .num_parents = 1,
1215 .flags = CLK_SET_RATE_PARENT,
1216 .ops = &clk_branch2_ops,
1217 },
1218 },
1219};
1220
1221static struct clk_branch avsync_pclk1_clk = {
1222 .halt_reg = 0x2420,
1223 .clkr = {
1224 .enable_reg = 0x2420,
1225 .enable_mask = BIT(0),
1226 .hw.init = &(struct clk_init_data){
1227 .name = "avsync_pclk1_clk",
1228 .parent_names = (const char *[]){
1229 "pclk1_clk_src",
1230 },
1231 .num_parents = 1,
1232 .flags = CLK_SET_RATE_PARENT,
1233 .ops = &clk_branch2_ops,
1234 },
1235 },
1236};
1237
1238static struct clk_branch avsync_vp_clk = {
1239 .halt_reg = 0x2404,
1240 .clkr = {
1241 .enable_reg = 0x2404,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "avsync_vp_clk",
1245 .parent_names = (const char *[]){
1246 "vp_clk_src",
1247 },
1248 .num_parents = 1,
1249 .flags = CLK_SET_RATE_PARENT,
1250 .ops = &clk_branch2_ops,
1251 },
1252 },
1253};
1254
1255static struct clk_branch camss_ahb_clk = {
1256 .halt_reg = 0x348c,
1257 .clkr = {
1258 .enable_reg = 0x348c,
1259 .enable_mask = BIT(0),
1260 .hw.init = &(struct clk_init_data){
1261 .name = "camss_ahb_clk",
1262 .parent_names = (const char *[]){
1263 "mmss_ahb_clk_src",
1264 },
1265 .num_parents = 1,
1266 .flags = CLK_SET_RATE_PARENT,
1267 .ops = &clk_branch2_ops,
1268 },
1269 },
1270};
1271
1272static struct clk_branch camss_cci_cci_ahb_clk = {
1273 .halt_reg = 0x3348,
1274 .clkr = {
1275 .enable_reg = 0x3348,
1276 .enable_mask = BIT(0),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "camss_cci_cci_ahb_clk",
1279 .parent_names = (const char *[]){
1280 "mmss_ahb_clk_src",
1281 },
1282 .num_parents = 1,
1283 .ops = &clk_branch2_ops,
1284 },
1285 },
1286};
1287
1288static struct clk_branch camss_cci_cci_clk = {
1289 .halt_reg = 0x3344,
1290 .clkr = {
1291 .enable_reg = 0x3344,
1292 .enable_mask = BIT(0),
1293 .hw.init = &(struct clk_init_data){
1294 .name = "camss_cci_cci_clk",
1295 .parent_names = (const char *[]){
1296 "cci_clk_src",
1297 },
1298 .num_parents = 1,
1299 .flags = CLK_SET_RATE_PARENT,
1300 .ops = &clk_branch2_ops,
1301 },
1302 },
1303};
1304
1305static struct clk_branch camss_csi0_ahb_clk = {
1306 .halt_reg = 0x30bc,
1307 .clkr = {
1308 .enable_reg = 0x30bc,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "camss_csi0_ahb_clk",
1312 .parent_names = (const char *[]){
1313 "mmss_ahb_clk_src",
1314 },
1315 .num_parents = 1,
1316 .ops = &clk_branch2_ops,
1317 },
1318 },
1319};
1320
1321static struct clk_branch camss_csi0_clk = {
1322 .halt_reg = 0x30b4,
1323 .clkr = {
1324 .enable_reg = 0x30b4,
1325 .enable_mask = BIT(0),
1326 .hw.init = &(struct clk_init_data){
1327 .name = "camss_csi0_clk",
1328 .parent_names = (const char *[]){
1329 "csi0_clk_src",
1330 },
1331 .num_parents = 1,
1332 .flags = CLK_SET_RATE_PARENT,
1333 .ops = &clk_branch2_ops,
1334 },
1335 },
1336};
1337
1338static struct clk_branch camss_csi0phy_clk = {
1339 .halt_reg = 0x30c4,
1340 .clkr = {
1341 .enable_reg = 0x30c4,
1342 .enable_mask = BIT(0),
1343 .hw.init = &(struct clk_init_data){
1344 .name = "camss_csi0phy_clk",
1345 .parent_names = (const char *[]){
1346 "csi0_clk_src",
1347 },
1348 .num_parents = 1,
1349 .flags = CLK_SET_RATE_PARENT,
1350 .ops = &clk_branch2_ops,
1351 },
1352 },
1353};
1354
1355static struct clk_branch camss_csi0pix_clk = {
1356 .halt_reg = 0x30e4,
1357 .clkr = {
1358 .enable_reg = 0x30e4,
1359 .enable_mask = BIT(0),
1360 .hw.init = &(struct clk_init_data){
1361 .name = "camss_csi0pix_clk",
1362 .parent_names = (const char *[]){
1363 "csi0_clk_src",
1364 },
1365 .num_parents = 1,
1366 .flags = CLK_SET_RATE_PARENT,
1367 .ops = &clk_branch2_ops,
1368 },
1369 },
1370};
1371
1372static struct clk_branch camss_csi0rdi_clk = {
1373 .halt_reg = 0x30d4,
1374 .clkr = {
1375 .enable_reg = 0x30d4,
1376 .enable_mask = BIT(0),
1377 .hw.init = &(struct clk_init_data){
1378 .name = "camss_csi0rdi_clk",
1379 .parent_names = (const char *[]){
1380 "csi0_clk_src",
1381 },
1382 .num_parents = 1,
1383 .flags = CLK_SET_RATE_PARENT,
1384 .ops = &clk_branch2_ops,
1385 },
1386 },
1387};
1388
1389static struct clk_branch camss_csi1_ahb_clk = {
1390 .halt_reg = 0x3128,
1391 .clkr = {
1392 .enable_reg = 0x3128,
1393 .enable_mask = BIT(0),
1394 .hw.init = &(struct clk_init_data){
1395 .name = "camss_csi1_ahb_clk",
1396 .parent_names = (const char *[]){
1397 "mmss_ahb_clk_src",
1398 },
1399 .num_parents = 1,
1400 .flags = CLK_SET_RATE_PARENT,
1401 .ops = &clk_branch2_ops,
1402 },
1403 },
1404};
1405
1406static struct clk_branch camss_csi1_clk = {
1407 .halt_reg = 0x3124,
1408 .clkr = {
1409 .enable_reg = 0x3124,
1410 .enable_mask = BIT(0),
1411 .hw.init = &(struct clk_init_data){
1412 .name = "camss_csi1_clk",
1413 .parent_names = (const char *[]){
1414 "csi1_clk_src",
1415 },
1416 .num_parents = 1,
1417 .flags = CLK_SET_RATE_PARENT,
1418 .ops = &clk_branch2_ops,
1419 },
1420 },
1421};
1422
1423static struct clk_branch camss_csi1phy_clk = {
1424 .halt_reg = 0x3134,
1425 .clkr = {
1426 .enable_reg = 0x3134,
1427 .enable_mask = BIT(0),
1428 .hw.init = &(struct clk_init_data){
1429 .name = "camss_csi1phy_clk",
1430 .parent_names = (const char *[]){
1431 "csi1_clk_src",
1432 },
1433 .num_parents = 1,
1434 .flags = CLK_SET_RATE_PARENT,
1435 .ops = &clk_branch2_ops,
1436 },
1437 },
1438};
1439
1440static struct clk_branch camss_csi1pix_clk = {
1441 .halt_reg = 0x3154,
1442 .clkr = {
1443 .enable_reg = 0x3154,
1444 .enable_mask = BIT(0),
1445 .hw.init = &(struct clk_init_data){
1446 .name = "camss_csi1pix_clk",
1447 .parent_names = (const char *[]){
1448 "csi1_clk_src",
1449 },
1450 .num_parents = 1,
1451 .flags = CLK_SET_RATE_PARENT,
1452 .ops = &clk_branch2_ops,
1453 },
1454 },
1455};
1456
1457static struct clk_branch camss_csi1rdi_clk = {
1458 .halt_reg = 0x3144,
1459 .clkr = {
1460 .enable_reg = 0x3144,
1461 .enable_mask = BIT(0),
1462 .hw.init = &(struct clk_init_data){
1463 .name = "camss_csi1rdi_clk",
1464 .parent_names = (const char *[]){
1465 "csi1_clk_src",
1466 },
1467 .num_parents = 1,
1468 .flags = CLK_SET_RATE_PARENT,
1469 .ops = &clk_branch2_ops,
1470 },
1471 },
1472};
1473
1474static struct clk_branch camss_csi2_ahb_clk = {
1475 .halt_reg = 0x3188,
1476 .clkr = {
1477 .enable_reg = 0x3188,
1478 .enable_mask = BIT(0),
1479 .hw.init = &(struct clk_init_data){
1480 .name = "camss_csi2_ahb_clk",
1481 .parent_names = (const char *[]){
1482 "mmss_ahb_clk_src",
1483 },
1484 .num_parents = 1,
1485 .ops = &clk_branch2_ops,
1486 },
1487 },
1488};
1489
1490static struct clk_branch camss_csi2_clk = {
1491 .halt_reg = 0x3184,
1492 .clkr = {
1493 .enable_reg = 0x3184,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "camss_csi2_clk",
1497 .parent_names = (const char *[]){
1498 "csi2_clk_src",
1499 },
1500 .num_parents = 1,
1501 .flags = CLK_SET_RATE_PARENT,
1502 .ops = &clk_branch2_ops,
1503 },
1504 },
1505};
1506
1507static struct clk_branch camss_csi2phy_clk = {
1508 .halt_reg = 0x3194,
1509 .clkr = {
1510 .enable_reg = 0x3194,
1511 .enable_mask = BIT(0),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "camss_csi2phy_clk",
1514 .parent_names = (const char *[]){
1515 "csi2_clk_src",
1516 },
1517 .num_parents = 1,
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1520 },
1521 },
1522};
1523
1524static struct clk_branch camss_csi2pix_clk = {
1525 .halt_reg = 0x31b4,
1526 .clkr = {
1527 .enable_reg = 0x31b4,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "camss_csi2pix_clk",
1531 .parent_names = (const char *[]){
1532 "csi2_clk_src",
1533 },
1534 .num_parents = 1,
1535 .flags = CLK_SET_RATE_PARENT,
1536 .ops = &clk_branch2_ops,
1537 },
1538 },
1539};
1540
1541static struct clk_branch camss_csi2rdi_clk = {
1542 .halt_reg = 0x31a4,
1543 .clkr = {
1544 .enable_reg = 0x31a4,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(struct clk_init_data){
1547 .name = "camss_csi2rdi_clk",
1548 .parent_names = (const char *[]){
1549 "csi2_clk_src",
1550 },
1551 .num_parents = 1,
1552 .flags = CLK_SET_RATE_PARENT,
1553 .ops = &clk_branch2_ops,
1554 },
1555 },
1556};
1557
1558static struct clk_branch camss_csi3_ahb_clk = {
1559 .halt_reg = 0x31e8,
1560 .clkr = {
1561 .enable_reg = 0x31e8,
1562 .enable_mask = BIT(0),
1563 .hw.init = &(struct clk_init_data){
1564 .name = "camss_csi3_ahb_clk",
1565 .parent_names = (const char *[]){
1566 "mmss_ahb_clk_src",
1567 },
1568 .num_parents = 1,
1569 .ops = &clk_branch2_ops,
1570 },
1571 },
1572};
1573
1574static struct clk_branch camss_csi3_clk = {
1575 .halt_reg = 0x31e4,
1576 .clkr = {
1577 .enable_reg = 0x31e4,
1578 .enable_mask = BIT(0),
1579 .hw.init = &(struct clk_init_data){
1580 .name = "camss_csi3_clk",
1581 .parent_names = (const char *[]){
1582 "csi3_clk_src",
1583 },
1584 .num_parents = 1,
1585 .flags = CLK_SET_RATE_PARENT,
1586 .ops = &clk_branch2_ops,
1587 },
1588 },
1589};
1590
1591static struct clk_branch camss_csi3phy_clk = {
1592 .halt_reg = 0x31f4,
1593 .clkr = {
1594 .enable_reg = 0x31f4,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "camss_csi3phy_clk",
1598 .parent_names = (const char *[]){
1599 "csi3_clk_src",
1600 },
1601 .num_parents = 1,
1602 .flags = CLK_SET_RATE_PARENT,
1603 .ops = &clk_branch2_ops,
1604 },
1605 },
1606};
1607
1608static struct clk_branch camss_csi3pix_clk = {
1609 .halt_reg = 0x3214,
1610 .clkr = {
1611 .enable_reg = 0x3214,
1612 .enable_mask = BIT(0),
1613 .hw.init = &(struct clk_init_data){
1614 .name = "camss_csi3pix_clk",
1615 .parent_names = (const char *[]){
1616 "csi3_clk_src",
1617 },
1618 .num_parents = 1,
1619 .flags = CLK_SET_RATE_PARENT,
1620 .ops = &clk_branch2_ops,
1621 },
1622 },
1623};
1624
1625static struct clk_branch camss_csi3rdi_clk = {
1626 .halt_reg = 0x3204,
1627 .clkr = {
1628 .enable_reg = 0x3204,
1629 .enable_mask = BIT(0),
1630 .hw.init = &(struct clk_init_data){
1631 .name = "camss_csi3rdi_clk",
1632 .parent_names = (const char *[]){
1633 "csi3_clk_src",
1634 },
1635 .num_parents = 1,
1636 .flags = CLK_SET_RATE_PARENT,
1637 .ops = &clk_branch2_ops,
1638 },
1639 },
1640};
1641
1642static struct clk_branch camss_csi_vfe0_clk = {
1643 .halt_reg = 0x3704,
1644 .clkr = {
1645 .enable_reg = 0x3704,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "camss_csi_vfe0_clk",
1649 .parent_names = (const char *[]){
1650 "vfe0_clk_src",
1651 },
1652 .num_parents = 1,
1653 .flags = CLK_SET_RATE_PARENT,
1654 .ops = &clk_branch2_ops,
1655 },
1656 },
1657};
1658
1659static struct clk_branch camss_csi_vfe1_clk = {
1660 .halt_reg = 0x3714,
1661 .clkr = {
1662 .enable_reg = 0x3714,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "camss_csi_vfe1_clk",
1666 .parent_names = (const char *[]){
1667 "vfe1_clk_src",
1668 },
1669 .num_parents = 1,
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1672 },
1673 },
1674};
1675
1676static struct clk_branch camss_gp0_clk = {
1677 .halt_reg = 0x3444,
1678 .clkr = {
1679 .enable_reg = 0x3444,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "camss_gp0_clk",
1683 .parent_names = (const char *[]){
1684 "camss_gp0_clk_src",
1685 },
1686 .num_parents = 1,
1687 .flags = CLK_SET_RATE_PARENT,
1688 .ops = &clk_branch2_ops,
1689 },
1690 },
1691};
1692
1693static struct clk_branch camss_gp1_clk = {
1694 .halt_reg = 0x3474,
1695 .clkr = {
1696 .enable_reg = 0x3474,
1697 .enable_mask = BIT(0),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "camss_gp1_clk",
1700 .parent_names = (const char *[]){
1701 "camss_gp1_clk_src",
1702 },
1703 .num_parents = 1,
1704 .flags = CLK_SET_RATE_PARENT,
1705 .ops = &clk_branch2_ops,
1706 },
1707 },
1708};
1709
1710static struct clk_branch camss_ispif_ahb_clk = {
1711 .halt_reg = 0x3224,
1712 .clkr = {
1713 .enable_reg = 0x3224,
1714 .enable_mask = BIT(0),
1715 .hw.init = &(struct clk_init_data){
1716 .name = "camss_ispif_ahb_clk",
1717 .parent_names = (const char *[]){
1718 "mmss_ahb_clk_src",
1719 },
1720 .num_parents = 1,
1721 .flags = CLK_SET_RATE_PARENT,
1722 .ops = &clk_branch2_ops,
1723 },
1724 },
1725};
1726
1727static struct clk_branch camss_jpeg_jpeg0_clk = {
1728 .halt_reg = 0x35a8,
1729 .clkr = {
1730 .enable_reg = 0x35a8,
1731 .enable_mask = BIT(0),
1732 .hw.init = &(struct clk_init_data){
1733 .name = "camss_jpeg_jpeg0_clk",
1734 .parent_names = (const char *[]){
1735 "jpeg0_clk_src",
1736 },
1737 .num_parents = 1,
1738 .flags = CLK_SET_RATE_PARENT,
1739 .ops = &clk_branch2_ops,
1740 },
1741 },
1742};
1743
1744static struct clk_branch camss_jpeg_jpeg1_clk = {
1745 .halt_reg = 0x35ac,
1746 .clkr = {
1747 .enable_reg = 0x35ac,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "camss_jpeg_jpeg1_clk",
1751 .parent_names = (const char *[]){
1752 "jpeg1_clk_src",
1753 },
1754 .num_parents = 1,
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1757 },
1758 },
1759};
1760
1761static struct clk_branch camss_jpeg_jpeg2_clk = {
1762 .halt_reg = 0x35b0,
1763 .clkr = {
1764 .enable_reg = 0x35b0,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "camss_jpeg_jpeg2_clk",
1768 .parent_names = (const char *[]){
1769 "jpeg2_clk_src",
1770 },
1771 .num_parents = 1,
1772 .flags = CLK_SET_RATE_PARENT,
1773 .ops = &clk_branch2_ops,
1774 },
1775 },
1776};
1777
1778static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1779 .halt_reg = 0x35b4,
1780 .clkr = {
1781 .enable_reg = 0x35b4,
1782 .enable_mask = BIT(0),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "camss_jpeg_jpeg_ahb_clk",
1785 .parent_names = (const char *[]){
1786 "mmss_ahb_clk_src",
1787 },
1788 .num_parents = 1,
1789 .ops = &clk_branch2_ops,
1790 },
1791 },
1792};
1793
1794static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1795 .halt_reg = 0x35b8,
1796 .clkr = {
1797 .enable_reg = 0x35b8,
1798 .enable_mask = BIT(0),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "camss_jpeg_jpeg_axi_clk",
1801 .parent_names = (const char *[]){
1802 "mmss_axi_clk_src",
1803 },
1804 .num_parents = 1,
1805 .ops = &clk_branch2_ops,
1806 },
1807 },
1808};
1809
1810static struct clk_branch camss_mclk0_clk = {
1811 .halt_reg = 0x3384,
1812 .clkr = {
1813 .enable_reg = 0x3384,
1814 .enable_mask = BIT(0),
1815 .hw.init = &(struct clk_init_data){
1816 .name = "camss_mclk0_clk",
1817 .parent_names = (const char *[]){
1818 "mclk0_clk_src",
1819 },
1820 .num_parents = 1,
1821 .flags = CLK_SET_RATE_PARENT,
1822 .ops = &clk_branch2_ops,
1823 },
1824 },
1825};
1826
1827static struct clk_branch camss_mclk1_clk = {
1828 .halt_reg = 0x33b4,
1829 .clkr = {
1830 .enable_reg = 0x33b4,
1831 .enable_mask = BIT(0),
1832 .hw.init = &(struct clk_init_data){
1833 .name = "camss_mclk1_clk",
1834 .parent_names = (const char *[]){
1835 "mclk1_clk_src",
1836 },
1837 .num_parents = 1,
1838 .flags = CLK_SET_RATE_PARENT,
1839 .ops = &clk_branch2_ops,
1840 },
1841 },
1842};
1843
1844static struct clk_branch camss_mclk2_clk = {
1845 .halt_reg = 0x33e4,
1846 .clkr = {
1847 .enable_reg = 0x33e4,
1848 .enable_mask = BIT(0),
1849 .hw.init = &(struct clk_init_data){
1850 .name = "camss_mclk2_clk",
1851 .parent_names = (const char *[]){
1852 "mclk2_clk_src",
1853 },
1854 .num_parents = 1,
1855 .flags = CLK_SET_RATE_PARENT,
1856 .ops = &clk_branch2_ops,
1857 },
1858 },
1859};
1860
1861static struct clk_branch camss_mclk3_clk = {
1862 .halt_reg = 0x3414,
1863 .clkr = {
1864 .enable_reg = 0x3414,
1865 .enable_mask = BIT(0),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "camss_mclk3_clk",
1868 .parent_names = (const char *[]){
1869 "mclk3_clk_src",
1870 },
1871 .num_parents = 1,
1872 .flags = CLK_SET_RATE_PARENT,
1873 .ops = &clk_branch2_ops,
1874 },
1875 },
1876};
1877
1878static struct clk_branch camss_micro_ahb_clk = {
1879 .halt_reg = 0x3494,
1880 .clkr = {
1881 .enable_reg = 0x3494,
1882 .enable_mask = BIT(0),
1883 .hw.init = &(struct clk_init_data){
1884 .name = "camss_micro_ahb_clk",
1885 .parent_names = (const char *[]){
1886 "mmss_ahb_clk_src",
1887 },
1888 .num_parents = 1,
1889 .ops = &clk_branch2_ops,
1890 },
1891 },
1892};
1893
1894static struct clk_branch camss_phy0_csi0phytimer_clk = {
1895 .halt_reg = 0x3024,
1896 .clkr = {
1897 .enable_reg = 0x3024,
1898 .enable_mask = BIT(0),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "camss_phy0_csi0phytimer_clk",
1901 .parent_names = (const char *[]){
1902 "csi0phytimer_clk_src",
1903 },
1904 .num_parents = 1,
1905 .flags = CLK_SET_RATE_PARENT,
1906 .ops = &clk_branch2_ops,
1907 },
1908 },
1909};
1910
1911static struct clk_branch camss_phy1_csi1phytimer_clk = {
1912 .halt_reg = 0x3054,
1913 .clkr = {
1914 .enable_reg = 0x3054,
1915 .enable_mask = BIT(0),
1916 .hw.init = &(struct clk_init_data){
1917 .name = "camss_phy1_csi1phytimer_clk",
1918 .parent_names = (const char *[]){
1919 "csi1phytimer_clk_src",
1920 },
1921 .num_parents = 1,
1922 .flags = CLK_SET_RATE_PARENT,
1923 .ops = &clk_branch2_ops,
1924 },
1925 },
1926};
1927
1928static struct clk_branch camss_phy2_csi2phytimer_clk = {
1929 .halt_reg = 0x3084,
1930 .clkr = {
1931 .enable_reg = 0x3084,
1932 .enable_mask = BIT(0),
1933 .hw.init = &(struct clk_init_data){
1934 .name = "camss_phy2_csi2phytimer_clk",
1935 .parent_names = (const char *[]){
1936 "csi2phytimer_clk_src",
1937 },
1938 .num_parents = 1,
1939 .flags = CLK_SET_RATE_PARENT,
1940 .ops = &clk_branch2_ops,
1941 },
1942 },
1943};
1944
1945static struct clk_branch camss_top_ahb_clk = {
1946 .halt_reg = 0x3484,
1947 .clkr = {
1948 .enable_reg = 0x3484,
1949 .enable_mask = BIT(0),
1950 .hw.init = &(struct clk_init_data){
1951 .name = "camss_top_ahb_clk",
1952 .parent_names = (const char *[]){
1953 "mmss_ahb_clk_src",
1954 },
1955 .num_parents = 1,
1956 .flags = CLK_SET_RATE_PARENT,
1957 .ops = &clk_branch2_ops,
1958 },
1959 },
1960};
1961
1962static struct clk_branch camss_vfe_cpp_ahb_clk = {
1963 .halt_reg = 0x36b4,
1964 .clkr = {
1965 .enable_reg = 0x36b4,
1966 .enable_mask = BIT(0),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "camss_vfe_cpp_ahb_clk",
1969 .parent_names = (const char *[]){
1970 "mmss_ahb_clk_src",
1971 },
1972 .num_parents = 1,
1973 .flags = CLK_SET_RATE_PARENT,
1974 .ops = &clk_branch2_ops,
1975 },
1976 },
1977};
1978
1979static struct clk_branch camss_vfe_cpp_clk = {
1980 .halt_reg = 0x36b0,
1981 .clkr = {
1982 .enable_reg = 0x36b0,
1983 .enable_mask = BIT(0),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "camss_vfe_cpp_clk",
1986 .parent_names = (const char *[]){
1987 "cpp_clk_src",
1988 },
1989 .num_parents = 1,
1990 .flags = CLK_SET_RATE_PARENT,
1991 .ops = &clk_branch2_ops,
1992 },
1993 },
1994};
1995
1996static struct clk_branch camss_vfe_vfe0_clk = {
1997 .halt_reg = 0x36a8,
1998 .clkr = {
1999 .enable_reg = 0x36a8,
2000 .enable_mask = BIT(0),
2001 .hw.init = &(struct clk_init_data){
2002 .name = "camss_vfe_vfe0_clk",
2003 .parent_names = (const char *[]){
2004 "vfe0_clk_src",
2005 },
2006 .num_parents = 1,
2007 .flags = CLK_SET_RATE_PARENT,
2008 .ops = &clk_branch2_ops,
2009 },
2010 },
2011};
2012
2013static struct clk_branch camss_vfe_vfe1_clk = {
2014 .halt_reg = 0x36ac,
2015 .clkr = {
2016 .enable_reg = 0x36ac,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "camss_vfe_vfe1_clk",
2020 .parent_names = (const char *[]){
2021 "vfe1_clk_src",
2022 },
2023 .num_parents = 1,
2024 .flags = CLK_SET_RATE_PARENT,
2025 .ops = &clk_branch2_ops,
2026 },
2027 },
2028};
2029
2030static struct clk_branch camss_vfe_vfe_ahb_clk = {
2031 .halt_reg = 0x36b8,
2032 .clkr = {
2033 .enable_reg = 0x36b8,
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "camss_vfe_vfe_ahb_clk",
2037 .parent_names = (const char *[]){
2038 "mmss_ahb_clk_src",
2039 },
2040 .num_parents = 1,
2041 .flags = CLK_SET_RATE_PARENT,
2042 .ops = &clk_branch2_ops,
2043 },
2044 },
2045};
2046
2047static struct clk_branch camss_vfe_vfe_axi_clk = {
2048 .halt_reg = 0x36bc,
2049 .clkr = {
2050 .enable_reg = 0x36bc,
2051 .enable_mask = BIT(0),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "camss_vfe_vfe_axi_clk",
2054 .parent_names = (const char *[]){
2055 "mmss_axi_clk_src",
2056 },
2057 .num_parents = 1,
2058 .flags = CLK_SET_RATE_PARENT,
2059 .ops = &clk_branch2_ops,
2060 },
2061 },
2062};
2063
2064static struct clk_branch mdss_ahb_clk = {
2065 .halt_reg = 0x2308,
2066 .clkr = {
2067 .enable_reg = 0x2308,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "mdss_ahb_clk",
2071 .parent_names = (const char *[]){
2072 "mmss_ahb_clk_src",
2073 },
2074 .num_parents = 1,
2075 .flags = CLK_SET_RATE_PARENT,
2076 .ops = &clk_branch2_ops,
2077 },
2078 },
2079};
2080
2081static struct clk_branch mdss_axi_clk = {
2082 .halt_reg = 0x2310,
2083 .clkr = {
2084 .enable_reg = 0x2310,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "mdss_axi_clk",
2088 .parent_names = (const char *[]){
2089 "mmss_axi_clk_src",
2090 },
2091 .num_parents = 1,
2092 .flags = CLK_SET_RATE_PARENT,
2093 .ops = &clk_branch2_ops,
2094 },
2095 },
2096};
2097
2098static struct clk_branch mdss_byte0_clk = {
2099 .halt_reg = 0x233c,
2100 .clkr = {
2101 .enable_reg = 0x233c,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "mdss_byte0_clk",
2105 .parent_names = (const char *[]){
2106 "byte0_clk_src",
2107 },
2108 .num_parents = 1,
2109 .flags = CLK_SET_RATE_PARENT,
2110 .ops = &clk_branch2_ops,
2111 },
2112 },
2113};
2114
2115static struct clk_branch mdss_byte1_clk = {
2116 .halt_reg = 0x2340,
2117 .clkr = {
2118 .enable_reg = 0x2340,
2119 .enable_mask = BIT(0),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "mdss_byte1_clk",
2122 .parent_names = (const char *[]){
2123 "byte1_clk_src",
2124 },
2125 .num_parents = 1,
2126 .flags = CLK_SET_RATE_PARENT,
2127 .ops = &clk_branch2_ops,
2128 },
2129 },
2130};
2131
2132static struct clk_branch mdss_edpaux_clk = {
2133 .halt_reg = 0x2334,
2134 .clkr = {
2135 .enable_reg = 0x2334,
2136 .enable_mask = BIT(0),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "mdss_edpaux_clk",
2139 .parent_names = (const char *[]){
2140 "edpaux_clk_src",
2141 },
2142 .num_parents = 1,
2143 .flags = CLK_SET_RATE_PARENT,
2144 .ops = &clk_branch2_ops,
2145 },
2146 },
2147};
2148
2149static struct clk_branch mdss_edplink_clk = {
2150 .halt_reg = 0x2330,
2151 .clkr = {
2152 .enable_reg = 0x2330,
2153 .enable_mask = BIT(0),
2154 .hw.init = &(struct clk_init_data){
2155 .name = "mdss_edplink_clk",
2156 .parent_names = (const char *[]){
2157 "edplink_clk_src",
2158 },
2159 .num_parents = 1,
2160 .flags = CLK_SET_RATE_PARENT,
2161 .ops = &clk_branch2_ops,
2162 },
2163 },
2164};
2165
2166static struct clk_branch mdss_edppixel_clk = {
2167 .halt_reg = 0x232c,
2168 .clkr = {
2169 .enable_reg = 0x232c,
2170 .enable_mask = BIT(0),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "mdss_edppixel_clk",
2173 .parent_names = (const char *[]){
2174 "edppixel_clk_src",
2175 },
2176 .num_parents = 1,
2177 .flags = CLK_SET_RATE_PARENT,
2178 .ops = &clk_branch2_ops,
2179 },
2180 },
2181};
2182
2183static struct clk_branch mdss_esc0_clk = {
2184 .halt_reg = 0x2344,
2185 .clkr = {
2186 .enable_reg = 0x2344,
2187 .enable_mask = BIT(0),
2188 .hw.init = &(struct clk_init_data){
2189 .name = "mdss_esc0_clk",
2190 .parent_names = (const char *[]){
2191 "esc0_clk_src",
2192 },
2193 .num_parents = 1,
2194 .flags = CLK_SET_RATE_PARENT,
2195 .ops = &clk_branch2_ops,
2196 },
2197 },
2198};
2199
2200static struct clk_branch mdss_esc1_clk = {
2201 .halt_reg = 0x2348,
2202 .clkr = {
2203 .enable_reg = 0x2348,
2204 .enable_mask = BIT(0),
2205 .hw.init = &(struct clk_init_data){
2206 .name = "mdss_esc1_clk",
2207 .parent_names = (const char *[]){
2208 "esc1_clk_src",
2209 },
2210 .num_parents = 1,
2211 .flags = CLK_SET_RATE_PARENT,
2212 .ops = &clk_branch2_ops,
2213 },
2214 },
2215};
2216
2217static struct clk_branch mdss_extpclk_clk = {
2218 .halt_reg = 0x2324,
2219 .clkr = {
2220 .enable_reg = 0x2324,
2221 .enable_mask = BIT(0),
2222 .hw.init = &(struct clk_init_data){
2223 .name = "mdss_extpclk_clk",
2224 .parent_names = (const char *[]){
2225 "extpclk_clk_src",
2226 },
2227 .num_parents = 1,
2228 .flags = CLK_SET_RATE_PARENT,
2229 .ops = &clk_branch2_ops,
2230 },
2231 },
2232};
2233
2234static struct clk_branch mdss_hdmi_ahb_clk = {
2235 .halt_reg = 0x230c,
2236 .clkr = {
2237 .enable_reg = 0x230c,
2238 .enable_mask = BIT(0),
2239 .hw.init = &(struct clk_init_data){
2240 .name = "mdss_hdmi_ahb_clk",
2241 .parent_names = (const char *[]){
2242 "mmss_ahb_clk_src",
2243 },
2244 .num_parents = 1,
2245 .flags = CLK_SET_RATE_PARENT,
2246 .ops = &clk_branch2_ops,
2247 },
2248 },
2249};
2250
2251static struct clk_branch mdss_hdmi_clk = {
2252 .halt_reg = 0x2338,
2253 .clkr = {
2254 .enable_reg = 0x2338,
2255 .enable_mask = BIT(0),
2256 .hw.init = &(struct clk_init_data){
2257 .name = "mdss_hdmi_clk",
2258 .parent_names = (const char *[]){
2259 "hdmi_clk_src",
2260 },
2261 .num_parents = 1,
2262 .flags = CLK_SET_RATE_PARENT,
2263 .ops = &clk_branch2_ops,
2264 },
2265 },
2266};
2267
2268static struct clk_branch mdss_mdp_clk = {
2269 .halt_reg = 0x231c,
2270 .clkr = {
2271 .enable_reg = 0x231c,
2272 .enable_mask = BIT(0),
2273 .hw.init = &(struct clk_init_data){
2274 .name = "mdss_mdp_clk",
2275 .parent_names = (const char *[]){
2276 "mdp_clk_src",
2277 },
2278 .num_parents = 1,
2279 .flags = CLK_SET_RATE_PARENT,
2280 .ops = &clk_branch2_ops,
2281 },
2282 },
2283};
2284
2285static struct clk_branch mdss_mdp_lut_clk = {
2286 .halt_reg = 0x2320,
2287 .clkr = {
2288 .enable_reg = 0x2320,
2289 .enable_mask = BIT(0),
2290 .hw.init = &(struct clk_init_data){
2291 .name = "mdss_mdp_lut_clk",
2292 .parent_names = (const char *[]){
2293 "mdp_clk_src",
2294 },
2295 .num_parents = 1,
2296 .flags = CLK_SET_RATE_PARENT,
2297 .ops = &clk_branch2_ops,
2298 },
2299 },
2300};
2301
2302static struct clk_branch mdss_pclk0_clk = {
2303 .halt_reg = 0x2314,
2304 .clkr = {
2305 .enable_reg = 0x2314,
2306 .enable_mask = BIT(0),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "mdss_pclk0_clk",
2309 .parent_names = (const char *[]){
2310 "pclk0_clk_src",
2311 },
2312 .num_parents = 1,
2313 .flags = CLK_SET_RATE_PARENT,
2314 .ops = &clk_branch2_ops,
2315 },
2316 },
2317};
2318
2319static struct clk_branch mdss_pclk1_clk = {
2320 .halt_reg = 0x2318,
2321 .clkr = {
2322 .enable_reg = 0x2318,
2323 .enable_mask = BIT(0),
2324 .hw.init = &(struct clk_init_data){
2325 .name = "mdss_pclk1_clk",
2326 .parent_names = (const char *[]){
2327 "pclk1_clk_src",
2328 },
2329 .num_parents = 1,
2330 .flags = CLK_SET_RATE_PARENT,
2331 .ops = &clk_branch2_ops,
2332 },
2333 },
2334};
2335
2336static struct clk_branch mdss_vsync_clk = {
2337 .halt_reg = 0x2328,
2338 .clkr = {
2339 .enable_reg = 0x2328,
2340 .enable_mask = BIT(0),
2341 .hw.init = &(struct clk_init_data){
2342 .name = "mdss_vsync_clk",
2343 .parent_names = (const char *[]){
2344 "vsync_clk_src",
2345 },
2346 .num_parents = 1,
2347 .flags = CLK_SET_RATE_PARENT,
2348 .ops = &clk_branch2_ops,
2349 },
2350 },
2351};
2352
2353static struct clk_branch mmss_rbcpr_ahb_clk = {
2354 .halt_reg = 0x4088,
2355 .clkr = {
2356 .enable_reg = 0x4088,
2357 .enable_mask = BIT(0),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "mmss_rbcpr_ahb_clk",
2360 .parent_names = (const char *[]){
2361 "mmss_ahb_clk_src",
2362 },
2363 .num_parents = 1,
2364 .flags = CLK_SET_RATE_PARENT,
2365 .ops = &clk_branch2_ops,
2366 },
2367 },
2368};
2369
2370static struct clk_branch mmss_rbcpr_clk = {
2371 .halt_reg = 0x4084,
2372 .clkr = {
2373 .enable_reg = 0x4084,
2374 .enable_mask = BIT(0),
2375 .hw.init = &(struct clk_init_data){
2376 .name = "mmss_rbcpr_clk",
2377 .parent_names = (const char *[]){
2378 "rbcpr_clk_src",
2379 },
2380 .num_parents = 1,
2381 .flags = CLK_SET_RATE_PARENT,
2382 .ops = &clk_branch2_ops,
2383 },
2384 },
2385};
2386
2387static struct clk_branch mmss_spdm_ahb_clk = {
2388 .halt_reg = 0x0230,
2389 .clkr = {
2390 .enable_reg = 0x0230,
2391 .enable_mask = BIT(0),
2392 .hw.init = &(struct clk_init_data){
2393 .name = "mmss_spdm_ahb_clk",
2394 .parent_names = (const char *[]){
2395 "mmss_spdm_ahb_div_clk",
2396 },
2397 .num_parents = 1,
2398 .flags = CLK_SET_RATE_PARENT,
2399 .ops = &clk_branch2_ops,
2400 },
2401 },
2402};
2403
2404static struct clk_branch mmss_spdm_axi_clk = {
2405 .halt_reg = 0x0210,
2406 .clkr = {
2407 .enable_reg = 0x0210,
2408 .enable_mask = BIT(0),
2409 .hw.init = &(struct clk_init_data){
2410 .name = "mmss_spdm_axi_clk",
2411 .parent_names = (const char *[]){
2412 "mmss_spdm_axi_div_clk",
2413 },
2414 .num_parents = 1,
2415 .flags = CLK_SET_RATE_PARENT,
2416 .ops = &clk_branch2_ops,
2417 },
2418 },
2419};
2420
2421static struct clk_branch mmss_spdm_csi0_clk = {
2422 .halt_reg = 0x023c,
2423 .clkr = {
2424 .enable_reg = 0x023c,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "mmss_spdm_csi0_clk",
2428 .parent_names = (const char *[]){
2429 "mmss_spdm_csi0_div_clk",
2430 },
2431 .num_parents = 1,
2432 .flags = CLK_SET_RATE_PARENT,
2433 .ops = &clk_branch2_ops,
2434 },
2435 },
2436};
2437
2438static struct clk_branch mmss_spdm_gfx3d_clk = {
2439 .halt_reg = 0x022c,
2440 .clkr = {
2441 .enable_reg = 0x022c,
2442 .enable_mask = BIT(0),
2443 .hw.init = &(struct clk_init_data){
2444 .name = "mmss_spdm_gfx3d_clk",
2445 .parent_names = (const char *[]){
2446 "mmss_spdm_gfx3d_div_clk",
2447 },
2448 .num_parents = 1,
2449 .flags = CLK_SET_RATE_PARENT,
2450 .ops = &clk_branch2_ops,
2451 },
2452 },
2453};
2454
2455static struct clk_branch mmss_spdm_jpeg0_clk = {
2456 .halt_reg = 0x0204,
2457 .clkr = {
2458 .enable_reg = 0x0204,
2459 .enable_mask = BIT(0),
2460 .hw.init = &(struct clk_init_data){
2461 .name = "mmss_spdm_jpeg0_clk",
2462 .parent_names = (const char *[]){
2463 "mmss_spdm_jpeg0_div_clk",
2464 },
2465 .num_parents = 1,
2466 .flags = CLK_SET_RATE_PARENT,
2467 .ops = &clk_branch2_ops,
2468 },
2469 },
2470};
2471
2472static struct clk_branch mmss_spdm_jpeg1_clk = {
2473 .halt_reg = 0x0208,
2474 .clkr = {
2475 .enable_reg = 0x0208,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "mmss_spdm_jpeg1_clk",
2479 .parent_names = (const char *[]){
2480 "mmss_spdm_jpeg1_div_clk",
2481 },
2482 .num_parents = 1,
2483 .flags = CLK_SET_RATE_PARENT,
2484 .ops = &clk_branch2_ops,
2485 },
2486 },
2487};
2488
2489static struct clk_branch mmss_spdm_jpeg2_clk = {
2490 .halt_reg = 0x0224,
2491 .clkr = {
2492 .enable_reg = 0x0224,
2493 .enable_mask = BIT(0),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "mmss_spdm_jpeg2_clk",
2496 .parent_names = (const char *[]){
2497 "mmss_spdm_jpeg2_div_clk",
2498 },
2499 .num_parents = 1,
2500 .flags = CLK_SET_RATE_PARENT,
2501 .ops = &clk_branch2_ops,
2502 },
2503 },
2504};
2505
2506static struct clk_branch mmss_spdm_mdp_clk = {
2507 .halt_reg = 0x020c,
2508 .clkr = {
2509 .enable_reg = 0x020c,
2510 .enable_mask = BIT(0),
2511 .hw.init = &(struct clk_init_data){
2512 .name = "mmss_spdm_mdp_clk",
2513 .parent_names = (const char *[]){
2514 "mmss_spdm_mdp_div_clk",
2515 },
2516 .num_parents = 1,
2517 .flags = CLK_SET_RATE_PARENT,
2518 .ops = &clk_branch2_ops,
2519 },
2520 },
2521};
2522
2523static struct clk_branch mmss_spdm_pclk0_clk = {
2524 .halt_reg = 0x0234,
2525 .clkr = {
2526 .enable_reg = 0x0234,
2527 .enable_mask = BIT(0),
2528 .hw.init = &(struct clk_init_data){
2529 .name = "mmss_spdm_pclk0_clk",
2530 .parent_names = (const char *[]){
2531 "mmss_spdm_pclk0_div_clk",
2532 },
2533 .num_parents = 1,
2534 .flags = CLK_SET_RATE_PARENT,
2535 .ops = &clk_branch2_ops,
2536 },
2537 },
2538};
2539
2540static struct clk_branch mmss_spdm_pclk1_clk = {
2541 .halt_reg = 0x0228,
2542 .clkr = {
2543 .enable_reg = 0x0228,
2544 .enable_mask = BIT(0),
2545 .hw.init = &(struct clk_init_data){
2546 .name = "mmss_spdm_pclk1_clk",
2547 .parent_names = (const char *[]){
2548 "mmss_spdm_pclk1_div_clk",
2549 },
2550 .num_parents = 1,
2551 .flags = CLK_SET_RATE_PARENT,
2552 .ops = &clk_branch2_ops,
2553 },
2554 },
2555};
2556
2557static struct clk_branch mmss_spdm_vcodec0_clk = {
2558 .halt_reg = 0x0214,
2559 .clkr = {
2560 .enable_reg = 0x0214,
2561 .enable_mask = BIT(0),
2562 .hw.init = &(struct clk_init_data){
2563 .name = "mmss_spdm_vcodec0_clk",
2564 .parent_names = (const char *[]){
2565 "mmss_spdm_vcodec0_div_clk",
2566 },
2567 .num_parents = 1,
2568 .flags = CLK_SET_RATE_PARENT,
2569 .ops = &clk_branch2_ops,
2570 },
2571 },
2572};
2573
2574static struct clk_branch mmss_spdm_vfe0_clk = {
2575 .halt_reg = 0x0218,
2576 .clkr = {
2577 .enable_reg = 0x0218,
2578 .enable_mask = BIT(0),
2579 .hw.init = &(struct clk_init_data){
2580 .name = "mmss_spdm_vfe0_clk",
2581 .parent_names = (const char *[]){
2582 "mmss_spdm_vfe0_div_clk",
2583 },
2584 .num_parents = 1,
2585 .flags = CLK_SET_RATE_PARENT,
2586 .ops = &clk_branch2_ops,
2587 },
2588 },
2589};
2590
2591static struct clk_branch mmss_spdm_vfe1_clk = {
2592 .halt_reg = 0x021c,
2593 .clkr = {
2594 .enable_reg = 0x021c,
2595 .enable_mask = BIT(0),
2596 .hw.init = &(struct clk_init_data){
2597 .name = "mmss_spdm_vfe1_clk",
2598 .parent_names = (const char *[]){
2599 "mmss_spdm_vfe1_div_clk",
2600 },
2601 .num_parents = 1,
2602 .flags = CLK_SET_RATE_PARENT,
2603 .ops = &clk_branch2_ops,
2604 },
2605 },
2606};
2607
2608static struct clk_branch mmss_spdm_rm_axi_clk = {
2609 .halt_reg = 0x0304,
2610 .clkr = {
2611 .enable_reg = 0x0304,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(struct clk_init_data){
2614 .name = "mmss_spdm_rm_axi_clk",
2615 .parent_names = (const char *[]){
2616 "mmss_axi_clk_src",
2617 },
2618 .num_parents = 1,
2619 .flags = CLK_SET_RATE_PARENT,
2620 .ops = &clk_branch2_ops,
2621 },
2622 },
2623};
2624
2625static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
2626 .halt_reg = 0x0308,
2627 .clkr = {
2628 .enable_reg = 0x0308,
2629 .enable_mask = BIT(0),
2630 .hw.init = &(struct clk_init_data){
2631 .name = "mmss_spdm_rm_ocmemnoc_clk",
2632 .parent_names = (const char *[]){
2633 "ocmemnoc_clk_src",
2634 },
2635 .num_parents = 1,
2636 .flags = CLK_SET_RATE_PARENT,
2637 .ops = &clk_branch2_ops,
2638 },
2639 },
2640};
2641
2642
2643static struct clk_branch mmss_misc_ahb_clk = {
2644 .halt_reg = 0x502c,
2645 .clkr = {
2646 .enable_reg = 0x502c,
2647 .enable_mask = BIT(0),
2648 .hw.init = &(struct clk_init_data){
2649 .name = "mmss_misc_ahb_clk",
2650 .parent_names = (const char *[]){
2651 "mmss_ahb_clk_src",
2652 },
2653 .num_parents = 1,
2654 .flags = CLK_SET_RATE_PARENT,
2655 .ops = &clk_branch2_ops,
2656 },
2657 },
2658};
2659
2660static struct clk_branch mmss_mmssnoc_ahb_clk = {
2661 .halt_reg = 0x5024,
2662 .clkr = {
2663 .enable_reg = 0x5024,
2664 .enable_mask = BIT(0),
2665 .hw.init = &(struct clk_init_data){
2666 .name = "mmss_mmssnoc_ahb_clk",
2667 .parent_names = (const char *[]){
2668 "mmss_ahb_clk_src",
2669 },
2670 .num_parents = 1,
2671 .ops = &clk_branch2_ops,
2672 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2673 },
2674 },
2675};
2676
2677static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2678 .halt_reg = 0x5028,
2679 .clkr = {
2680 .enable_reg = 0x5028,
2681 .enable_mask = BIT(0),
2682 .hw.init = &(struct clk_init_data){
2683 .name = "mmss_mmssnoc_bto_ahb_clk",
2684 .parent_names = (const char *[]){
2685 "mmss_ahb_clk_src",
2686 },
2687 .num_parents = 1,
2688 .ops = &clk_branch2_ops,
2689 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2690 },
2691 },
2692};
2693
2694static struct clk_branch mmss_mmssnoc_axi_clk = {
2695 .halt_reg = 0x506c,
2696 .clkr = {
2697 .enable_reg = 0x506c,
2698 .enable_mask = BIT(0),
2699 .hw.init = &(struct clk_init_data){
2700 .name = "mmss_mmssnoc_axi_clk",
2701 .parent_names = (const char *[]){
2702 "mmss_axi_clk_src",
2703 },
2704 .num_parents = 1,
2705 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2706 .ops = &clk_branch2_ops,
2707 },
2708 },
2709};
2710
2711static struct clk_branch mmss_s0_axi_clk = {
2712 .halt_reg = 0x5064,
2713 .clkr = {
2714 .enable_reg = 0x5064,
2715 .enable_mask = BIT(0),
2716 .hw.init = &(struct clk_init_data){
2717 .name = "mmss_s0_axi_clk",
2718 .parent_names = (const char *[]){
2719 "mmss_axi_clk_src",
2720 },
2721 .num_parents = 1,
2722 .ops = &clk_branch2_ops,
2723 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2724 },
2725 },
2726};
2727
2728static struct clk_branch ocmemcx_ahb_clk = {
2729 .halt_reg = 0x405c,
2730 .clkr = {
2731 .enable_reg = 0x405c,
2732 .enable_mask = BIT(0),
2733 .hw.init = &(struct clk_init_data){
2734 .name = "ocmemcx_ahb_clk",
2735 .parent_names = (const char *[]){
2736 "mmss_ahb_clk_src",
2737 },
2738 .num_parents = 1,
2739 .flags = CLK_SET_RATE_PARENT,
2740 .ops = &clk_branch2_ops,
2741 },
2742 },
2743};
2744
2745static struct clk_branch ocmemcx_ocmemnoc_clk = {
2746 .halt_reg = 0x4058,
2747 .clkr = {
2748 .enable_reg = 0x4058,
2749 .enable_mask = BIT(0),
2750 .hw.init = &(struct clk_init_data){
2751 .name = "ocmemcx_ocmemnoc_clk",
2752 .parent_names = (const char *[]){
2753 "ocmemnoc_clk_src",
2754 },
2755 .num_parents = 1,
2756 .flags = CLK_SET_RATE_PARENT,
2757 .ops = &clk_branch2_ops,
2758 },
2759 },
2760};
2761
2762static struct clk_branch oxili_ocmemgx_clk = {
2763 .halt_reg = 0x402c,
2764 .clkr = {
2765 .enable_reg = 0x402c,
2766 .enable_mask = BIT(0),
2767 .hw.init = &(struct clk_init_data){
2768 .name = "oxili_ocmemgx_clk",
2769 .parent_names = (const char *[]){
2770 "gfx3d_clk_src",
2771 },
2772 .num_parents = 1,
2773 .flags = CLK_SET_RATE_PARENT,
2774 .ops = &clk_branch2_ops,
2775 },
2776 },
2777};
2778
2779static struct clk_branch oxili_gfx3d_clk = {
2780 .halt_reg = 0x4028,
2781 .clkr = {
2782 .enable_reg = 0x4028,
2783 .enable_mask = BIT(0),
2784 .hw.init = &(struct clk_init_data){
2785 .name = "oxili_gfx3d_clk",
2786 .parent_names = (const char *[]){
2787 "gfx3d_clk_src",
2788 },
2789 .num_parents = 1,
2790 .flags = CLK_SET_RATE_PARENT,
2791 .ops = &clk_branch2_ops,
2792 },
2793 },
2794};
2795
2796static struct clk_branch oxili_rbbmtimer_clk = {
2797 .halt_reg = 0x40b0,
2798 .clkr = {
2799 .enable_reg = 0x40b0,
2800 .enable_mask = BIT(0),
2801 .hw.init = &(struct clk_init_data){
2802 .name = "oxili_rbbmtimer_clk",
2803 .parent_names = (const char *[]){
2804 "rbbmtimer_clk_src",
2805 },
2806 .num_parents = 1,
2807 .flags = CLK_SET_RATE_PARENT,
2808 .ops = &clk_branch2_ops,
2809 },
2810 },
2811};
2812
2813static struct clk_branch oxilicx_ahb_clk = {
2814 .halt_reg = 0x403c,
2815 .clkr = {
2816 .enable_reg = 0x403c,
2817 .enable_mask = BIT(0),
2818 .hw.init = &(struct clk_init_data){
2819 .name = "oxilicx_ahb_clk",
2820 .parent_names = (const char *[]){
2821 "mmss_ahb_clk_src",
2822 },
2823 .num_parents = 1,
2824 .flags = CLK_SET_RATE_PARENT,
2825 .ops = &clk_branch2_ops,
2826 },
2827 },
2828};
2829
2830static struct clk_branch venus0_ahb_clk = {
2831 .halt_reg = 0x1030,
2832 .clkr = {
2833 .enable_reg = 0x1030,
2834 .enable_mask = BIT(0),
2835 .hw.init = &(struct clk_init_data){
2836 .name = "venus0_ahb_clk",
2837 .parent_names = (const char *[]){
2838 "mmss_ahb_clk_src",
2839 },
2840 .num_parents = 1,
2841 .flags = CLK_SET_RATE_PARENT,
2842 .ops = &clk_branch2_ops,
2843 },
2844 },
2845};
2846
2847static struct clk_branch venus0_axi_clk = {
2848 .halt_reg = 0x1034,
2849 .clkr = {
2850 .enable_reg = 0x1034,
2851 .enable_mask = BIT(0),
2852 .hw.init = &(struct clk_init_data){
2853 .name = "venus0_axi_clk",
2854 .parent_names = (const char *[]){
2855 "mmss_axi_clk_src",
2856 },
2857 .num_parents = 1,
2858 .flags = CLK_SET_RATE_PARENT,
2859 .ops = &clk_branch2_ops,
2860 },
2861 },
2862};
2863
2864static struct clk_branch venus0_core0_vcodec_clk = {
2865 .halt_reg = 0x1048,
2866 .clkr = {
2867 .enable_reg = 0x1048,
2868 .enable_mask = BIT(0),
2869 .hw.init = &(struct clk_init_data){
2870 .name = "venus0_core0_vcodec_clk",
2871 .parent_names = (const char *[]){
2872 "vcodec0_clk_src",
2873 },
2874 .num_parents = 1,
2875 .flags = CLK_SET_RATE_PARENT,
2876 .ops = &clk_branch2_ops,
2877 },
2878 },
2879};
2880
2881static struct clk_branch venus0_core1_vcodec_clk = {
2882 .halt_reg = 0x104c,
2883 .clkr = {
2884 .enable_reg = 0x104c,
2885 .enable_mask = BIT(0),
2886 .hw.init = &(struct clk_init_data){
2887 .name = "venus0_core1_vcodec_clk",
2888 .parent_names = (const char *[]){
2889 "vcodec0_clk_src",
2890 },
2891 .num_parents = 1,
2892 .flags = CLK_SET_RATE_PARENT,
2893 .ops = &clk_branch2_ops,
2894 },
2895 },
2896};
2897
2898static struct clk_branch venus0_ocmemnoc_clk = {
2899 .halt_reg = 0x1038,
2900 .clkr = {
2901 .enable_reg = 0x1038,
2902 .enable_mask = BIT(0),
2903 .hw.init = &(struct clk_init_data){
2904 .name = "venus0_ocmemnoc_clk",
2905 .parent_names = (const char *[]){
2906 "ocmemnoc_clk_src",
2907 },
2908 .num_parents = 1,
2909 .flags = CLK_SET_RATE_PARENT,
2910 .ops = &clk_branch2_ops,
2911 },
2912 },
2913};
2914
2915static struct clk_branch venus0_vcodec0_clk = {
2916 .halt_reg = 0x1028,
2917 .clkr = {
2918 .enable_reg = 0x1028,
2919 .enable_mask = BIT(0),
2920 .hw.init = &(struct clk_init_data){
2921 .name = "venus0_vcodec0_clk",
2922 .parent_names = (const char *[]){
2923 "vcodec0_clk_src",
2924 },
2925 .num_parents = 1,
2926 .flags = CLK_SET_RATE_PARENT,
2927 .ops = &clk_branch2_ops,
2928 },
2929 },
2930};
2931
2932static struct clk_branch vpu_ahb_clk = {
2933 .halt_reg = 0x1430,
2934 .clkr = {
2935 .enable_reg = 0x1430,
2936 .enable_mask = BIT(0),
2937 .hw.init = &(struct clk_init_data){
2938 .name = "vpu_ahb_clk",
2939 .parent_names = (const char *[]){
2940 "mmss_ahb_clk_src",
2941 },
2942 .num_parents = 1,
2943 .flags = CLK_SET_RATE_PARENT,
2944 .ops = &clk_branch2_ops,
2945 },
2946 },
2947};
2948
2949static struct clk_branch vpu_axi_clk = {
2950 .halt_reg = 0x143c,
2951 .clkr = {
2952 .enable_reg = 0x143c,
2953 .enable_mask = BIT(0),
2954 .hw.init = &(struct clk_init_data){
2955 .name = "vpu_axi_clk",
2956 .parent_names = (const char *[]){
2957 "mmss_axi_clk_src",
2958 },
2959 .num_parents = 1,
2960 .flags = CLK_SET_RATE_PARENT,
2961 .ops = &clk_branch2_ops,
2962 },
2963 },
2964};
2965
2966static struct clk_branch vpu_bus_clk = {
2967 .halt_reg = 0x1440,
2968 .clkr = {
2969 .enable_reg = 0x1440,
2970 .enable_mask = BIT(0),
2971 .hw.init = &(struct clk_init_data){
2972 .name = "vpu_bus_clk",
2973 .parent_names = (const char *[]){
2974 "vpu_bus_clk_src",
2975 },
2976 .num_parents = 1,
2977 .flags = CLK_SET_RATE_PARENT,
2978 .ops = &clk_branch2_ops,
2979 },
2980 },
2981};
2982
2983static struct clk_branch vpu_cxo_clk = {
2984 .halt_reg = 0x1434,
2985 .clkr = {
2986 .enable_reg = 0x1434,
2987 .enable_mask = BIT(0),
2988 .hw.init = &(struct clk_init_data){
2989 .name = "vpu_cxo_clk",
2990 .parent_names = (const char *[]){ "xo" },
2991 .num_parents = 1,
2992 .flags = CLK_SET_RATE_PARENT,
2993 .ops = &clk_branch2_ops,
2994 },
2995 },
2996};
2997
2998static struct clk_branch vpu_maple_clk = {
2999 .halt_reg = 0x142c,
3000 .clkr = {
3001 .enable_reg = 0x142c,
3002 .enable_mask = BIT(0),
3003 .hw.init = &(struct clk_init_data){
3004 .name = "vpu_maple_clk",
3005 .parent_names = (const char *[]){
3006 "maple_clk_src",
3007 },
3008 .num_parents = 1,
3009 .flags = CLK_SET_RATE_PARENT,
3010 .ops = &clk_branch2_ops,
3011 },
3012 },
3013};
3014
3015static struct clk_branch vpu_sleep_clk = {
3016 .halt_reg = 0x1438,
3017 .clkr = {
3018 .enable_reg = 0x1438,
3019 .enable_mask = BIT(0),
3020 .hw.init = &(struct clk_init_data){
3021 .name = "vpu_sleep_clk",
3022 .parent_names = (const char *[]){
3023 "sleep_clk_src",
3024 },
3025 .num_parents = 1,
3026 .flags = CLK_SET_RATE_PARENT,
3027 .ops = &clk_branch2_ops,
3028 },
3029 },
3030};
3031
3032static struct clk_branch vpu_vdp_clk = {
3033 .halt_reg = 0x1428,
3034 .clkr = {
3035 .enable_reg = 0x1428,
3036 .enable_mask = BIT(0),
3037 .hw.init = &(struct clk_init_data){
3038 .name = "vpu_vdp_clk",
3039 .parent_names = (const char *[]){
3040 "vdp_clk_src",
3041 },
3042 .num_parents = 1,
3043 .flags = CLK_SET_RATE_PARENT,
3044 .ops = &clk_branch2_ops,
3045 },
3046 },
3047};
3048
3049static const struct pll_config mmpll1_config = {
3050 .l = 60,
3051 .m = 25,
3052 .n = 32,
3053 .vco_val = 0x0,
3054 .vco_mask = 0x3 << 20,
3055 .pre_div_val = 0x0,
3056 .pre_div_mask = 0x7 << 12,
3057 .post_div_val = 0x0,
3058 .post_div_mask = 0x3 << 8,
3059 .mn_ena_mask = BIT(24),
3060 .main_output_mask = BIT(0),
3061};
3062
3063static const struct pll_config mmpll3_config = {
3064 .l = 48,
3065 .m = 7,
3066 .n = 16,
3067 .vco_val = 0x0,
3068 .vco_mask = 0x3 << 20,
3069 .pre_div_val = 0x0,
3070 .pre_div_mask = 0x7 << 12,
3071 .post_div_val = 0x0,
3072 .post_div_mask = 0x3 << 8,
3073 .mn_ena_mask = BIT(24),
3074 .main_output_mask = BIT(0),
3075 .aux_output_mask = BIT(1),
3076};
3077
3078static struct clk_regmap *mmcc_apq8084_clocks[] = {
3079 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
3080 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
3081 [MMPLL0] = &mmpll0.clkr,
3082 [MMPLL0_VOTE] = &mmpll0_vote,
3083 [MMPLL1] = &mmpll1.clkr,
3084 [MMPLL1_VOTE] = &mmpll1_vote,
3085 [MMPLL2] = &mmpll2.clkr,
3086 [MMPLL3] = &mmpll3.clkr,
3087 [MMPLL4] = &mmpll4.clkr,
3088 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3089 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3090 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3091 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3092 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3093 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3094 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3095 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3096 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3097 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3098 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
3099 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3100 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3101 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
3102 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3103 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
3104 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3105 [VP_CLK_SRC] = &vp_clk_src.clkr,
3106 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3107 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3108 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3109 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3110 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3111 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3112 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3113 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3114 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3115 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3116 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3117 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3118 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3119 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
3120 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
3121 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3122 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3123 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3124 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3125 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3126 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3127 [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
3128 [VDP_CLK_SRC] = &vdp_clk_src.clkr,
3129 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
3130 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
3131 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
3132 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
3133 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
3134 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
3135 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
3136 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
3137 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
3138 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3139 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
3140 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
3141 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3142 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3143 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3144 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3145 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3146 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3147 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3148 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3149 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3150 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3151 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3152 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3153 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3154 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3155 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3156 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3157 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3158 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3159 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3160 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3161 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3162 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3163 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3164 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3165 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3166 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
3167 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
3168 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
3169 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
3170 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
3171 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3172 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3173 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3174 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3175 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3176 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
3177 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
3178 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
3179 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3180 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
3181 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
3182 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
3183 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
3184 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
3185 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
3186 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3187 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3188 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3189 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3190 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3191 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3192 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3193 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3194 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3195 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3196 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3197 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3198 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3199 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3200 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3201 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3202 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3203 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3204 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3205 [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
3206 [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
3207 [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
3208 [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
3209 [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
3210 [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
3211 [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
3212 [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
3213 [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
3214 [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
3215 [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
3216 [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
3217 [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
3218 [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
3219 [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
3220 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3221 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3222 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3223 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3224 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3225 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3226 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3227 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3228 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3229 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3230 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3231 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3232 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3233 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3234 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3235 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3236 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3237 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3238 [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3239 [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3240 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3241 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3242 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3243 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3244};
3245
3246static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3247 [MMSS_SPDM_RESET] = { 0x0200 },
3248 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3249 [VENUS0_RESET] = { 0x1020 },
3250 [VPU_RESET] = { 0x1400 },
3251 [MDSS_RESET] = { 0x2300 },
3252 [AVSYNC_RESET] = { 0x2400 },
3253 [CAMSS_PHY0_RESET] = { 0x3020 },
3254 [CAMSS_PHY1_RESET] = { 0x3050 },
3255 [CAMSS_PHY2_RESET] = { 0x3080 },
3256 [CAMSS_CSI0_RESET] = { 0x30b0 },
3257 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3258 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3259 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3260 [CAMSS_CSI1_RESET] = { 0x3120 },
3261 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3262 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3263 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3264 [CAMSS_CSI2_RESET] = { 0x3180 },
3265 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3266 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3267 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3268 [CAMSS_CSI3_RESET] = { 0x31e0 },
3269 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3270 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3271 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3272 [CAMSS_ISPIF_RESET] = { 0x3220 },
3273 [CAMSS_CCI_RESET] = { 0x3340 },
3274 [CAMSS_MCLK0_RESET] = { 0x3380 },
3275 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3276 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3277 [CAMSS_MCLK3_RESET] = { 0x3410 },
3278 [CAMSS_GP0_RESET] = { 0x3440 },
3279 [CAMSS_GP1_RESET] = { 0x3470 },
3280 [CAMSS_TOP_RESET] = { 0x3480 },
3281 [CAMSS_AHB_RESET] = { 0x3488 },
3282 [CAMSS_MICRO_RESET] = { 0x3490 },
3283 [CAMSS_JPEG_RESET] = { 0x35a0 },
3284 [CAMSS_VFE_RESET] = { 0x36a0 },
3285 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3286 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3287 [OXILI_RESET] = { 0x4020 },
3288 [OXILICX_RESET] = { 0x4030 },
3289 [OCMEMCX_RESET] = { 0x4050 },
3290 [MMSS_RBCRP_RESET] = { 0x4080 },
3291 [MMSSNOCAHB_RESET] = { 0x5020 },
3292 [MMSSNOCAXI_RESET] = { 0x5060 },
3293};
3294
3295static const struct regmap_config mmcc_apq8084_regmap_config = {
3296 .reg_bits = 32,
3297 .reg_stride = 4,
3298 .val_bits = 32,
3299 .max_register = 0x5104,
3300 .fast_io = true,
3301};
3302
3303static const struct qcom_cc_desc mmcc_apq8084_desc = {
3304 .config = &mmcc_apq8084_regmap_config,
3305 .clks = mmcc_apq8084_clocks,
3306 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3307 .resets = mmcc_apq8084_resets,
3308 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
3309};
3310
3311static const struct of_device_id mmcc_apq8084_match_table[] = {
3312 { .compatible = "qcom,mmcc-apq8084" },
3313 { }
3314};
3315MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3316
3317static int mmcc_apq8084_probe(struct platform_device *pdev)
3318{
3319 int ret;
3320 struct regmap *regmap;
3321
3322 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
3323 if (ret)
3324 return ret;
3325
3326 regmap = dev_get_regmap(&pdev->dev, NULL);
3327 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
3328 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
3329
3330 return 0;
3331}
3332
3333static int mmcc_apq8084_remove(struct platform_device *pdev)
3334{
3335 qcom_cc_remove(pdev);
3336 return 0;
3337}
3338
3339static struct platform_driver mmcc_apq8084_driver = {
3340 .probe = mmcc_apq8084_probe,
3341 .remove = mmcc_apq8084_remove,
3342 .driver = {
3343 .name = "mmcc-apq8084",
3344 .owner = THIS_MODULE,
3345 .of_match_table = mmcc_apq8084_match_table,
3346 },
3347};
3348module_platform_driver(mmcc_apq8084_driver);
3349
3350MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3351MODULE_LICENSE("GPL v2");
3352MODULE_ALIAS("platform:mmcc-apq8084");
diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
new file mode 100644
index 000000000000..a929f86d0ddd
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
@@ -0,0 +1,183 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H
15#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H
16
17#define MMSS_AHB_CLK_SRC 0
18#define MMSS_AXI_CLK_SRC 1
19#define MMPLL0 2
20#define MMPLL0_VOTE 3
21#define MMPLL1 4
22#define MMPLL1_VOTE 5
23#define MMPLL2 6
24#define MMPLL3 7
25#define MMPLL4 8
26#define CSI0_CLK_SRC 9
27#define CSI1_CLK_SRC 10
28#define CSI2_CLK_SRC 11
29#define CSI3_CLK_SRC 12
30#define VCODEC0_CLK_SRC 13
31#define VFE0_CLK_SRC 14
32#define VFE1_CLK_SRC 15
33#define MDP_CLK_SRC 16
34#define PCLK0_CLK_SRC 17
35#define PCLK1_CLK_SRC 18
36#define OCMEMNOC_CLK_SRC 19
37#define GFX3D_CLK_SRC 20
38#define JPEG0_CLK_SRC 21
39#define JPEG1_CLK_SRC 22
40#define JPEG2_CLK_SRC 23
41#define EDPPIXEL_CLK_SRC 24
42#define EXTPCLK_CLK_SRC 25
43#define VP_CLK_SRC 26
44#define CCI_CLK_SRC 27
45#define CAMSS_GP0_CLK_SRC 28
46#define CAMSS_GP1_CLK_SRC 29
47#define MCLK0_CLK_SRC 30
48#define MCLK1_CLK_SRC 31
49#define MCLK2_CLK_SRC 32
50#define MCLK3_CLK_SRC 33
51#define CSI0PHYTIMER_CLK_SRC 34
52#define CSI1PHYTIMER_CLK_SRC 35
53#define CSI2PHYTIMER_CLK_SRC 36
54#define CPP_CLK_SRC 37
55#define BYTE0_CLK_SRC 38
56#define BYTE1_CLK_SRC 39
57#define EDPAUX_CLK_SRC 40
58#define EDPLINK_CLK_SRC 41
59#define ESC0_CLK_SRC 42
60#define ESC1_CLK_SRC 43
61#define HDMI_CLK_SRC 44
62#define VSYNC_CLK_SRC 45
63#define RBCPR_CLK_SRC 46
64#define RBBMTIMER_CLK_SRC 47
65#define MAPLE_CLK_SRC 48
66#define VDP_CLK_SRC 49
67#define VPU_BUS_CLK_SRC 50
68#define MMSS_CXO_CLK 51
69#define MMSS_SLEEPCLK_CLK 52
70#define AVSYNC_AHB_CLK 53
71#define AVSYNC_EDPPIXEL_CLK 54
72#define AVSYNC_EXTPCLK_CLK 55
73#define AVSYNC_PCLK0_CLK 56
74#define AVSYNC_PCLK1_CLK 57
75#define AVSYNC_VP_CLK 58
76#define CAMSS_AHB_CLK 59
77#define CAMSS_CCI_CCI_AHB_CLK 60
78#define CAMSS_CCI_CCI_CLK 61
79#define CAMSS_CSI0_AHB_CLK 62
80#define CAMSS_CSI0_CLK 63
81#define CAMSS_CSI0PHY_CLK 64
82#define CAMSS_CSI0PIX_CLK 65
83#define CAMSS_CSI0RDI_CLK 66
84#define CAMSS_CSI1_AHB_CLK 67
85#define CAMSS_CSI1_CLK 68
86#define CAMSS_CSI1PHY_CLK 69
87#define CAMSS_CSI1PIX_CLK 70
88#define CAMSS_CSI1RDI_CLK 71
89#define CAMSS_CSI2_AHB_CLK 72
90#define CAMSS_CSI2_CLK 73
91#define CAMSS_CSI2PHY_CLK 74
92#define CAMSS_CSI2PIX_CLK 75
93#define CAMSS_CSI2RDI_CLK 76
94#define CAMSS_CSI3_AHB_CLK 77
95#define CAMSS_CSI3_CLK 78
96#define CAMSS_CSI3PHY_CLK 79
97#define CAMSS_CSI3PIX_CLK 80
98#define CAMSS_CSI3RDI_CLK 81
99#define CAMSS_CSI_VFE0_CLK 82
100#define CAMSS_CSI_VFE1_CLK 83
101#define CAMSS_GP0_CLK 84
102#define CAMSS_GP1_CLK 85
103#define CAMSS_ISPIF_AHB_CLK 86
104#define CAMSS_JPEG_JPEG0_CLK 87
105#define CAMSS_JPEG_JPEG1_CLK 88
106#define CAMSS_JPEG_JPEG2_CLK 89
107#define CAMSS_JPEG_JPEG_AHB_CLK 90
108#define CAMSS_JPEG_JPEG_AXI_CLK 91
109#define CAMSS_MCLK0_CLK 92
110#define CAMSS_MCLK1_CLK 93
111#define CAMSS_MCLK2_CLK 94
112#define CAMSS_MCLK3_CLK 95
113#define CAMSS_MICRO_AHB_CLK 96
114#define CAMSS_PHY0_CSI0PHYTIMER_CLK 97
115#define CAMSS_PHY1_CSI1PHYTIMER_CLK 98
116#define CAMSS_PHY2_CSI2PHYTIMER_CLK 99
117#define CAMSS_TOP_AHB_CLK 100
118#define CAMSS_VFE_CPP_AHB_CLK 101
119#define CAMSS_VFE_CPP_CLK 102
120#define CAMSS_VFE_VFE0_CLK 103
121#define CAMSS_VFE_VFE1_CLK 104
122#define CAMSS_VFE_VFE_AHB_CLK 105
123#define CAMSS_VFE_VFE_AXI_CLK 106
124#define MDSS_AHB_CLK 107
125#define MDSS_AXI_CLK 108
126#define MDSS_BYTE0_CLK 109
127#define MDSS_BYTE1_CLK 110
128#define MDSS_EDPAUX_CLK 111
129#define MDSS_EDPLINK_CLK 112
130#define MDSS_EDPPIXEL_CLK 113
131#define MDSS_ESC0_CLK 114
132#define MDSS_ESC1_CLK 115
133#define MDSS_EXTPCLK_CLK 116
134#define MDSS_HDMI_AHB_CLK 117
135#define MDSS_HDMI_CLK 118
136#define MDSS_MDP_CLK 119
137#define MDSS_MDP_LUT_CLK 120
138#define MDSS_PCLK0_CLK 121
139#define MDSS_PCLK1_CLK 122
140#define MDSS_VSYNC_CLK 123
141#define MMSS_RBCPR_AHB_CLK 124
142#define MMSS_RBCPR_CLK 125
143#define MMSS_SPDM_AHB_CLK 126
144#define MMSS_SPDM_AXI_CLK 127
145#define MMSS_SPDM_CSI0_CLK 128
146#define MMSS_SPDM_GFX3D_CLK 129
147#define MMSS_SPDM_JPEG0_CLK 130
148#define MMSS_SPDM_JPEG1_CLK 131
149#define MMSS_SPDM_JPEG2_CLK 132
150#define MMSS_SPDM_MDP_CLK 133
151#define MMSS_SPDM_PCLK0_CLK 134
152#define MMSS_SPDM_PCLK1_CLK 135
153#define MMSS_SPDM_VCODEC0_CLK 136
154#define MMSS_SPDM_VFE0_CLK 137
155#define MMSS_SPDM_VFE1_CLK 138
156#define MMSS_SPDM_RM_AXI_CLK 139
157#define MMSS_SPDM_RM_OCMEMNOC_CLK 140
158#define MMSS_MISC_AHB_CLK 141
159#define MMSS_MMSSNOC_AHB_CLK 142
160#define MMSS_MMSSNOC_BTO_AHB_CLK 143
161#define MMSS_MMSSNOC_AXI_CLK 144
162#define MMSS_S0_AXI_CLK 145
163#define OCMEMCX_AHB_CLK 146
164#define OCMEMCX_OCMEMNOC_CLK 147
165#define OXILI_OCMEMGX_CLK 148
166#define OXILI_GFX3D_CLK 149
167#define OXILI_RBBMTIMER_CLK 150
168#define OXILICX_AHB_CLK 151
169#define VENUS0_AHB_CLK 152
170#define VENUS0_AXI_CLK 153
171#define VENUS0_CORE0_VCODEC_CLK 154
172#define VENUS0_CORE1_VCODEC_CLK 155
173#define VENUS0_OCMEMNOC_CLK 156
174#define VENUS0_VCODEC0_CLK 157
175#define VPU_AHB_CLK 158
176#define VPU_AXI_CLK 159
177#define VPU_BUS_CLK 160
178#define VPU_CXO_CLK 161
179#define VPU_MAPLE_CLK 162
180#define VPU_SLEEP_CLK 163
181#define VPU_VDP_CLK 164
182
183#endif
diff --git a/include/dt-bindings/reset/qcom,mmcc-apq8084.h b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
new file mode 100644
index 000000000000..c1671396531d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H
15#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H
16
17#define MMSS_SPDM_RESET 0
18#define MMSS_SPDM_RM_RESET 1
19#define VENUS0_RESET 2
20#define VPU_RESET 3
21#define MDSS_RESET 4
22#define AVSYNC_RESET 5
23#define CAMSS_PHY0_RESET 6
24#define CAMSS_PHY1_RESET 7
25#define CAMSS_PHY2_RESET 8
26#define CAMSS_CSI0_RESET 9
27#define CAMSS_CSI0PHY_RESET 10
28#define CAMSS_CSI0RDI_RESET 11
29#define CAMSS_CSI0PIX_RESET 12
30#define CAMSS_CSI1_RESET 13
31#define CAMSS_CSI1PHY_RESET 14
32#define CAMSS_CSI1RDI_RESET 15
33#define CAMSS_CSI1PIX_RESET 16
34#define CAMSS_CSI2_RESET 17
35#define CAMSS_CSI2PHY_RESET 18
36#define CAMSS_CSI2RDI_RESET 19
37#define CAMSS_CSI2PIX_RESET 20
38#define CAMSS_CSI3_RESET 21
39#define CAMSS_CSI3PHY_RESET 22
40#define CAMSS_CSI3RDI_RESET 23
41#define CAMSS_CSI3PIX_RESET 24
42#define CAMSS_ISPIF_RESET 25
43#define CAMSS_CCI_RESET 26
44#define CAMSS_MCLK0_RESET 27
45#define CAMSS_MCLK1_RESET 28
46#define CAMSS_MCLK2_RESET 29
47#define CAMSS_MCLK3_RESET 30
48#define CAMSS_GP0_RESET 31
49#define CAMSS_GP1_RESET 32
50#define CAMSS_TOP_RESET 33
51#define CAMSS_AHB_RESET 34
52#define CAMSS_MICRO_RESET 35
53#define CAMSS_JPEG_RESET 36
54#define CAMSS_VFE_RESET 37
55#define CAMSS_CSI_VFE0_RESET 38
56#define CAMSS_CSI_VFE1_RESET 39
57#define OXILI_RESET 40
58#define OXILICX_RESET 41
59#define OCMEMCX_RESET 42
60#define MMSS_RBCRP_RESET 43
61#define MMSSNOCAHB_RESET 44
62#define MMSSNOCAXI_RESET 45
63
64#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-17 10:05:05 -0400