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authorJani Nikula <jani.nikula@intel.com>2013-09-27 12:01:01 -0400
committerDave Airlie <airlied@redhat.com>2013-10-01 01:28:57 -0400
commit0aec288130713cf7bcf97c929ac5fab6a8e00e44 (patch)
tree3fb1b235e3bb502a7dcd6cf9351d12725697c436 /include/drm
parent4ddc773b60497dcefbd9824f8931ae297659e6cc (diff)
drm/dp: constify DP DPCD helpers
None of the DP DPCD helpers need to modify the DPCD. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/drm_dp_helper.h16
1 files changed, 8 insertions, 8 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 83da4eb1575b..110f4f1f51d7 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -333,20 +333,20 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
333 333
334 334
335#define DP_LINK_STATUS_SIZE 6 335#define DP_LINK_STATUS_SIZE 6
336bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], 336bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
337 int lane_count); 337 int lane_count);
338bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], 338bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
339 int lane_count); 339 int lane_count);
340u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], 340u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
341 int lane); 341 int lane);
342u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], 342u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
343 int lane); 343 int lane);
344 344
345#define DP_RECEIVER_CAP_SIZE 0xf 345#define DP_RECEIVER_CAP_SIZE 0xf
346#define EDP_PSR_RECEIVER_CAP_SIZE 2 346#define EDP_PSR_RECEIVER_CAP_SIZE 2
347 347
348void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); 348void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
349void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); 349void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
350 350
351u8 drm_dp_link_rate_to_bw_code(int link_rate); 351u8 drm_dp_link_rate_to_bw_code(int link_rate);
352int drm_dp_bw_code_to_link_rate(u8 link_bw); 352int drm_dp_bw_code_to_link_rate(u8 link_bw);
@@ -379,13 +379,13 @@ struct edp_vsc_psr {
379#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) 379#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
380 380
381static inline int 381static inline int
382drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) 382drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
383{ 383{
384 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 384 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
385} 385}
386 386
387static inline u8 387static inline u8
388drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE]) 388drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
389{ 389{
390 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 390 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
391} 391}