aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips
diff options
context:
space:
mode:
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-04-15 13:00:45 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-15 13:44:32 -0400
commitb29eee4935d9e5952a7ea8543ea499f06fb86808 (patch)
tree713846fdbd856500602a06df0b20ef1233dced01 /include/asm-mips
parentaf3e69cfc9644c742a22647a5091779b9dfb9653 (diff)
[MIPS] rbtx4927: misc cleanups
* Merge tx4927_pci.h into tx4927.h * Kill (broken) external PCI clock frequency reporting * Kill unnecessary wbflush() * Kill unnecessary includes * Kill debug garbages Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/tx4927/toshiba_rbtx4927.h4
-rw-r--r--include/asm-mips/tx4927/tx4927.h240
-rw-r--r--include/asm-mips/tx4927/tx4927_pci.h268
3 files changed, 237 insertions, 275 deletions
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
index b188a659ce02..d6b32acd6b7b 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h
@@ -28,9 +28,6 @@
28#define __ASM_TX4927_TOSHIBA_RBTX4927_H 28#define __ASM_TX4927_TOSHIBA_RBTX4927_H
29 29
30#include <asm/tx4927/tx4927.h> 30#include <asm/tx4927/tx4927.h>
31#ifdef CONFIG_PCI
32#include <asm/tx4927/tx4927_pci.h>
33#endif
34 31
35#ifdef CONFIG_PCI 32#ifdef CONFIG_PCI
36#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO 33#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO
@@ -44,7 +41,6 @@
44#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL 41#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
45#define RBTX4927_SW_RESET_ENABLE_SET 0x01 42#define RBTX4927_SW_RESET_ENABLE_SET 0x01
46 43
47
48#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) 44#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
49#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) 45#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5)
50 46
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index 193e80a17c12..1d4816f3266f 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -36,11 +36,245 @@
36#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) 36#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
37 37
38 38
39#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) 39#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
40#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) 40#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1)
41#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) 41#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2)
42#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) 42#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7)
43 43
44#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) 44#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3)
45 45
46#define TX4927_CCFG_TOE 0x00004000
47#define TX4927_CCFG_WR 0x00008000
48#define TX4927_CCFG_TINTDIS 0x01000000
49
50#define TX4927_PCIMEM 0x08000000
51#define TX4927_PCIMEM_SIZE 0x08000000
52#define TX4927_PCIIO 0x16000000
53#define TX4927_PCIIO_SIZE 0x01000000
54
55#define TX4927_SDRAMC_REG 0xff1f8000
56#define TX4927_EBUSC_REG 0xff1f9000
57#define TX4927_PCIC_REG 0xff1fd000
58#define TX4927_CCFG_REG 0xff1fe000
59#define TX4927_IRC_REG 0xff1ff600
60#define TX4927_NR_TMR 3
61#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
62
63/* bits for ISTAT3/IMASK3/IMSTAT3 */
64#define TX4927_INT3B_PCID 0
65#define TX4927_INT3B_PCIC 1
66#define TX4927_INT3B_PCIB 2
67#define TX4927_INT3B_PCIA 3
68#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
69#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
70#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
71#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
72
73#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
74#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
75
76#define TX4927_IR_PCIC 16
77#define TX4927_IR_PCIERR 22
78#define TX4927_IR_PCIPMA 23
79#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
80#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
81#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
82#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
83#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
84#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
85#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
86
87#ifdef _LANGUAGE_ASSEMBLY
88#define _CONST64(c) c
89#else
90#define _CONST64(c) c##ull
91
92#include <asm/byteorder.h>
93
94struct tx4927_sdramc_reg {
95 volatile unsigned long long cr[4];
96 volatile unsigned long long unused0[4];
97 volatile unsigned long long tr;
98 volatile unsigned long long unused1[2];
99 volatile unsigned long long cmd;
100};
101
102struct tx4927_ebusc_reg {
103 volatile unsigned long long cr[8];
104};
105
106struct tx4927_ccfg_reg {
107 volatile unsigned long long ccfg;
108 volatile unsigned long long crir;
109 volatile unsigned long long pcfg;
110 volatile unsigned long long tear;
111 volatile unsigned long long clkctr;
112 volatile unsigned long long unused0;
113 volatile unsigned long long garbc;
114 volatile unsigned long long unused1;
115 volatile unsigned long long unused2;
116 volatile unsigned long long ramp;
117};
118
119struct tx4927_pcic_reg {
120 volatile unsigned long pciid;
121 volatile unsigned long pcistatus;
122 volatile unsigned long pciccrev;
123 volatile unsigned long pcicfg1;
124 volatile unsigned long p2gm0plbase; /* +10 */
125 volatile unsigned long p2gm0pubase;
126 volatile unsigned long p2gm1plbase;
127 volatile unsigned long p2gm1pubase;
128 volatile unsigned long p2gm2pbase; /* +20 */
129 volatile unsigned long p2giopbase;
130 volatile unsigned long unused0;
131 volatile unsigned long pcisid;
132 volatile unsigned long unused1; /* +30 */
133 volatile unsigned long pcicapptr;
134 volatile unsigned long unused2;
135 volatile unsigned long pcicfg2;
136 volatile unsigned long g2ptocnt; /* +40 */
137 volatile unsigned long unused3[15];
138 volatile unsigned long g2pstatus; /* +80 */
139 volatile unsigned long g2pmask;
140 volatile unsigned long pcisstatus;
141 volatile unsigned long pcimask;
142 volatile unsigned long p2gcfg; /* +90 */
143 volatile unsigned long p2gstatus;
144 volatile unsigned long p2gmask;
145 volatile unsigned long p2gccmd;
146 volatile unsigned long unused4[24]; /* +a0 */
147 volatile unsigned long pbareqport; /* +100 */
148 volatile unsigned long pbacfg;
149 volatile unsigned long pbastatus;
150 volatile unsigned long pbamask;
151 volatile unsigned long pbabm; /* +110 */
152 volatile unsigned long pbacreq;
153 volatile unsigned long pbacgnt;
154 volatile unsigned long pbacstate;
155 volatile unsigned long long g2pmgbase[3]; /* +120 */
156 volatile unsigned long long g2piogbase;
157 volatile unsigned long g2pmmask[3]; /* +140 */
158 volatile unsigned long g2piomask;
159 volatile unsigned long long g2pmpbase[3]; /* +150 */
160 volatile unsigned long long g2piopbase;
161 volatile unsigned long pciccfg; /* +170 */
162 volatile unsigned long pcicstatus;
163 volatile unsigned long pcicmask;
164 volatile unsigned long unused5;
165 volatile unsigned long long p2gmgbase[3]; /* +180 */
166 volatile unsigned long long p2giogbase;
167 volatile unsigned long g2pcfgadrs; /* +1a0 */
168 volatile unsigned long g2pcfgdata;
169 volatile unsigned long unused6[8];
170 volatile unsigned long g2pintack;
171 volatile unsigned long g2pspc;
172 volatile unsigned long unused7[12]; /* +1d0 */
173 volatile unsigned long long pdmca; /* +200 */
174 volatile unsigned long long pdmga;
175 volatile unsigned long long pdmpa;
176 volatile unsigned long long pdmcut;
177 volatile unsigned long long pdmcnt; /* +220 */
178 volatile unsigned long long pdmsts;
179 volatile unsigned long long unused8[2];
180 volatile unsigned long long pdmdb[4]; /* +240 */
181 volatile unsigned long long pdmtdh; /* +260 */
182 volatile unsigned long long pdmdms;
183};
184
185#endif /* _LANGUAGE_ASSEMBLY */
186
187/*
188 * PCIC
189 */
190
191/* bits for G2PSTATUS/G2PMASK */
192#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
193#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
194#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
195
196/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
197#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
198
199/* bits for PBACFG */
200#define TX4927_PCIC_PBACFG_RPBA 0x00000004
201#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
202#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
203
204/* bits for G2PMnGBASE */
205#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
206#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
207
208/* bits for G2PIOGBASE */
209#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
210#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
211
212/* bits for PCICSTATUS/PCICMASK */
213#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
214
215/* bits for PCICCFG */
216#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
217#define TX4927_PCIC_PCICCFG_HRST 0x00000800
218#define TX4927_PCIC_PCICCFG_SRST 0x00000400
219#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
220#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
221#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
222#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
223#define TX4927_PCIC_PCICCFG_IISE 0x00000020
224#define TX4927_PCIC_PCICCFG_ATR 0x00000010
225#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
226
227/* bits for P2GMnGBASE */
228#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
229#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
230#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
231
232/* bits for P2GIOGBASE */
233#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
234#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
235#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
236
237#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
238#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
239
240/*
241 * CCFG
242 */
243/* CCFG : Chip Configuration */
244#define TX4927_CCFG_PCI66 0x00800000
245#define TX4927_CCFG_PCIMIDE 0x00400000
246#define TX4927_CCFG_PCIXARB 0x00002000
247#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
248#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
249#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
250#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
251#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
252
253#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
254#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
255#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
256#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
257#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
258#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
259#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
260#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
261#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
262
263/* PCFG : Pin Configuration */
264#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
265#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
266
267/* CLKCTR : Clock Control */
268#define TX4927_CLKCTR_PCICKD 0x00400000
269#define TX4927_CLKCTR_PCIRST 0x00000040
270
271#ifndef _LANGUAGE_ASSEMBLY
272
273#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
274#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
275#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
276#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
277
278#endif /* _LANGUAGE_ASSEMBLY */
279
46#endif /* __ASM_TX4927_TX4927_H */ 280#endif /* __ASM_TX4927_TX4927_H */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
deleted file mode 100644
index 0be77df70f2b..000000000000
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ /dev/null
@@ -1,268 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000-2001 Toshiba Corporation
7 */
8#ifndef __ASM_TX4927_TX4927_PCI_H
9#define __ASM_TX4927_TX4927_PCI_H
10
11#define TX4927_CCFG_TOE 0x00004000
12#define TX4927_CCFG_WR 0x00008000
13#define TX4927_CCFG_TINTDIS 0x01000000
14
15#define TX4927_PCIMEM 0x08000000
16#define TX4927_PCIMEM_SIZE 0x08000000
17#define TX4927_PCIIO 0x16000000
18#define TX4927_PCIIO_SIZE 0x01000000
19
20#define TX4927_SDRAMC_REG 0xff1f8000
21#define TX4927_EBUSC_REG 0xff1f9000
22#define TX4927_PCIC_REG 0xff1fd000
23#define TX4927_CCFG_REG 0xff1fe000
24#define TX4927_IRC_REG 0xff1ff600
25#define TX4927_NR_TMR 3
26#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
27#define TX4927_CE3 0x17f00000 /* 1M */
28#define TX4927_PCIRESET_ADDR 0xbc00f006
29#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
30
31#define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n))
32#define tx4927_imstat_ptr(n) \
33 ((volatile unsigned char *)TX4927_IMSTAT_ADDR(n))
34
35/* bits for ISTAT3/IMASK3/IMSTAT3 */
36#define TX4927_INT3B_PCID 0
37#define TX4927_INT3B_PCIC 1
38#define TX4927_INT3B_PCIB 2
39#define TX4927_INT3B_PCIA 3
40#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
41#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
42#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
43#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
44
45/* bits for PCI_CLK (S6) */
46#define TX4927_PCI_CLK_HOST 0x80
47#define TX4927_PCI_CLK_MASK (0x0f << 3)
48#define TX4927_PCI_CLK_33 (0x01 << 3)
49#define TX4927_PCI_CLK_25 (0x04 << 3)
50#define TX4927_PCI_CLK_66 (0x09 << 3)
51#define TX4927_PCI_CLK_50 (0x0c << 3)
52#define TX4927_PCI_CLK_ACK 0x04
53#define TX4927_PCI_CLK_ACE 0x02
54#define TX4927_PCI_CLK_ENDIAN 0x01
55#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
56#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
57
58#define TX4927_IR_PCIC 16
59#define TX4927_IR_PCIERR 22
60#define TX4927_IR_PCIPMA 23
61#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
62#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
63#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
64#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
65#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
66#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
67#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
68
69#ifdef _LANGUAGE_ASSEMBLY
70#define _CONST64(c) c
71#else
72#define _CONST64(c) c##ull
73
74#include <asm/byteorder.h>
75
76#define tx4927_pcireset_ptr \
77 ((volatile unsigned char *)TX4927_PCIRESET_ADDR)
78#define tx4927_pci_clk_ptr \
79 ((volatile unsigned char *)TX4927_PCI_CLK_ADDR)
80
81struct tx4927_sdramc_reg {
82 volatile unsigned long long cr[4];
83 volatile unsigned long long unused0[4];
84 volatile unsigned long long tr;
85 volatile unsigned long long unused1[2];
86 volatile unsigned long long cmd;
87};
88
89struct tx4927_ebusc_reg {
90 volatile unsigned long long cr[8];
91};
92
93struct tx4927_ccfg_reg {
94 volatile unsigned long long ccfg;
95 volatile unsigned long long crir;
96 volatile unsigned long long pcfg;
97 volatile unsigned long long tear;
98 volatile unsigned long long clkctr;
99 volatile unsigned long long unused0;
100 volatile unsigned long long garbc;
101 volatile unsigned long long unused1;
102 volatile unsigned long long unused2;
103 volatile unsigned long long ramp;
104};
105
106struct tx4927_pcic_reg {
107 volatile unsigned long pciid;
108 volatile unsigned long pcistatus;
109 volatile unsigned long pciccrev;
110 volatile unsigned long pcicfg1;
111 volatile unsigned long p2gm0plbase; /* +10 */
112 volatile unsigned long p2gm0pubase;
113 volatile unsigned long p2gm1plbase;
114 volatile unsigned long p2gm1pubase;
115 volatile unsigned long p2gm2pbase; /* +20 */
116 volatile unsigned long p2giopbase;
117 volatile unsigned long unused0;
118 volatile unsigned long pcisid;
119 volatile unsigned long unused1; /* +30 */
120 volatile unsigned long pcicapptr;
121 volatile unsigned long unused2;
122 volatile unsigned long pcicfg2;
123 volatile unsigned long g2ptocnt; /* +40 */
124 volatile unsigned long unused3[15];
125 volatile unsigned long g2pstatus; /* +80 */
126 volatile unsigned long g2pmask;
127 volatile unsigned long pcisstatus;
128 volatile unsigned long pcimask;
129 volatile unsigned long p2gcfg; /* +90 */
130 volatile unsigned long p2gstatus;
131 volatile unsigned long p2gmask;
132 volatile unsigned long p2gccmd;
133 volatile unsigned long unused4[24]; /* +a0 */
134 volatile unsigned long pbareqport; /* +100 */
135 volatile unsigned long pbacfg;
136 volatile unsigned long pbastatus;
137 volatile unsigned long pbamask;
138 volatile unsigned long pbabm; /* +110 */
139 volatile unsigned long pbacreq;
140 volatile unsigned long pbacgnt;
141 volatile unsigned long pbacstate;
142 volatile unsigned long long g2pmgbase[3]; /* +120 */
143 volatile unsigned long long g2piogbase;
144 volatile unsigned long g2pmmask[3]; /* +140 */
145 volatile unsigned long g2piomask;
146 volatile unsigned long long g2pmpbase[3]; /* +150 */
147 volatile unsigned long long g2piopbase;
148 volatile unsigned long pciccfg; /* +170 */
149 volatile unsigned long pcicstatus;
150 volatile unsigned long pcicmask;
151 volatile unsigned long unused5;
152 volatile unsigned long long p2gmgbase[3]; /* +180 */
153 volatile unsigned long long p2giogbase;
154 volatile unsigned long g2pcfgadrs; /* +1a0 */
155 volatile unsigned long g2pcfgdata;
156 volatile unsigned long unused6[8];
157 volatile unsigned long g2pintack;
158 volatile unsigned long g2pspc;
159 volatile unsigned long unused7[12]; /* +1d0 */
160 volatile unsigned long long pdmca; /* +200 */
161 volatile unsigned long long pdmga;
162 volatile unsigned long long pdmpa;
163 volatile unsigned long long pdmcut;
164 volatile unsigned long long pdmcnt; /* +220 */
165 volatile unsigned long long pdmsts;
166 volatile unsigned long long unused8[2];
167 volatile unsigned long long pdmdb[4]; /* +240 */
168 volatile unsigned long long pdmtdh; /* +260 */
169 volatile unsigned long long pdmdms;
170};
171
172#endif /* _LANGUAGE_ASSEMBLY */
173
174/*
175 * PCIC
176 */
177
178/* bits for G2PSTATUS/G2PMASK */
179#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
180#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
181#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
182
183/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
184#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
185
186/* bits for PBACFG */
187#define TX4927_PCIC_PBACFG_RPBA 0x00000004
188#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
189#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
190
191/* bits for G2PMnGBASE */
192#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
193#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
194
195/* bits for G2PIOGBASE */
196#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
197#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
198
199/* bits for PCICSTATUS/PCICMASK */
200#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
201
202/* bits for PCICCFG */
203#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
204#define TX4927_PCIC_PCICCFG_HRST 0x00000800
205#define TX4927_PCIC_PCICCFG_SRST 0x00000400
206#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
207#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
208#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
209#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
210#define TX4927_PCIC_PCICCFG_IISE 0x00000020
211#define TX4927_PCIC_PCICCFG_ATR 0x00000010
212#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
213
214/* bits for P2GMnGBASE */
215#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
216#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
217#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
218
219/* bits for P2GIOGBASE */
220#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
221#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
222#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
223
224#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
225#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
226
227/*
228 * CCFG
229 */
230/* CCFG : Chip Configuration */
231#define TX4927_CCFG_PCI66 0x00800000
232#define TX4927_CCFG_PCIMIDE 0x00400000
233#define TX4927_CCFG_PCIXARB 0x00002000
234#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
235#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
236#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
237#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
238#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
239
240#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
241#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
242#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
243#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
244#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
245#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
246#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
247#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
248#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
249
250/* PCFG : Pin Configuration */
251#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
252#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
253
254/* CLKCTR : Clock Control */
255#define TX4927_CLKCTR_PCICKD 0x00400000
256#define TX4927_CLKCTR_PCIRST 0x00000040
257
258
259#ifndef _LANGUAGE_ASSEMBLY
260
261#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
262#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
263#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
264#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
265
266#endif /* _LANGUAGE_ASSEMBLY */
267
268#endif /* __ASM_TX4927_TX4927_PCI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 05:05:11 -0500