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-rw-r--r--arch/mips/pci/fixup-rbtx4927.c1
-rw-r--r--arch/mips/pci/ops-tx4927.c5
-rw-r--r--arch/mips/tx4927/common/tx4927_dbgio.c5
-rw-r--r--arch/mips/tx4927/common/tx4927_prom.c8
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c234
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c7
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c322
-rw-r--r--include/asm-mips/tx4927/toshiba_rbtx4927.h4
-rw-r--r--include/asm-mips/tx4927/tx4927.h240
-rw-r--r--include/asm-mips/tx4927/tx4927_pci.h268
10 files changed, 266 insertions, 828 deletions
diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c
index 7450c335b387..2d234ca017db 100644
--- a/arch/mips/pci/fixup-rbtx4927.c
+++ b/arch/mips/pci/fixup-rbtx4927.c
@@ -38,7 +38,6 @@
38#include <linux/init.h> 38#include <linux/init.h>
39 39
40#include <asm/tx4927/tx4927.h> 40#include <asm/tx4927/tx4927.h>
41#include <asm/tx4927/tx4927_pci.h>
42 41
43#undef DEBUG 42#undef DEBUG
44#ifdef DEBUG 43#ifdef DEBUG
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index 150419c8b414..1bbafeb4a774 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -40,10 +40,7 @@
40#include <linux/pci.h> 40#include <linux/pci.h>
41#include <linux/kernel.h> 41#include <linux/kernel.h>
42#include <linux/init.h> 42#include <linux/init.h>
43 43#include <asm/tx4927/tx4927.h>
44#include <asm/addrspace.h>
45#include <asm/byteorder.h>
46#include <asm/tx4927/tx4927_pci.h>
47 44
48/* initialize in setup */ 45/* initialize in setup */
49struct resource pci_io_resource = { 46struct resource pci_io_resource = {
diff --git a/arch/mips/tx4927/common/tx4927_dbgio.c b/arch/mips/tx4927/common/tx4927_dbgio.c
index d8423e001b2d..ea1ff23f4b72 100644
--- a/arch/mips/tx4927/common/tx4927_dbgio.c
+++ b/arch/mips/tx4927/common/tx4927_dbgio.c
@@ -28,9 +28,7 @@
28 * with this program; if not, write to the Free Software Foundation, Inc., 28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */ 30 */
31 31#include <linux/types.h>
32#include <asm/mipsregs.h>
33#include <asm/system.h>
34 32
35u8 getDebugChar(void) 33u8 getDebugChar(void)
36{ 34{
@@ -38,7 +36,6 @@ u8 getDebugChar(void)
38 return (txx9_sio_kdbg_rd()); 36 return (txx9_sio_kdbg_rd());
39} 37}
40 38
41
42int putDebugChar(u8 byte) 39int putDebugChar(u8 byte)
43{ 40{
44 extern int txx9_sio_kdbg_wr( u8 ch ); 41 extern int txx9_sio_kdbg_wr( u8 ch );
diff --git a/arch/mips/tx4927/common/tx4927_prom.c b/arch/mips/tx4927/common/tx4927_prom.c
index 6eed53d8f386..cc2aa9d63e82 100644
--- a/arch/mips/tx4927/common/tx4927_prom.c
+++ b/arch/mips/tx4927/common/tx4927_prom.c
@@ -30,12 +30,8 @@
30 */ 30 */
31 31
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/mm.h> 33#include <linux/types.h>
34#include <linux/sched.h> 34#include <linux/io.h>
35#include <linux/bootmem.h>
36
37#include <asm/addrspace.h>
38#include <asm/bootinfo.h>
39#include <asm/tx4927/tx4927.h> 35#include <asm/tx4927/tx4927.h>
40 36
41static unsigned int __init tx4927_process_sdccr(unsigned long addr) 37static unsigned int __init tx4927_process_sdccr(unsigned long addr)
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index 6d31f2a98abf..c18901a75cc4 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -28,8 +28,6 @@
28 * with this program; if not, write to the Free Software Foundation, Inc., 28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */ 30 */
31
32
33/* 31/*
34IRQ Device 32IRQ Device
3500 RBTX4927-ISA/00 3300 RBTX4927-ISA/00
@@ -112,76 +110,14 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
112*/ 110*/
113 111
114#include <linux/init.h> 112#include <linux/init.h>
115#include <linux/kernel.h>
116#include <linux/types.h> 113#include <linux/types.h>
117#include <linux/mm.h>
118#include <linux/swap.h>
119#include <linux/ioport.h>
120#include <linux/sched.h>
121#include <linux/interrupt.h> 114#include <linux/interrupt.h>
122#include <linux/pci.h>
123#include <linux/timex.h>
124#include <asm/bootinfo.h>
125#include <asm/page.h>
126#include <asm/io.h> 115#include <asm/io.h>
127#include <asm/irq.h>
128#include <asm/pci.h>
129#include <asm/processor.h>
130#include <asm/reboot.h>
131#include <asm/time.h>
132#include <asm/wbflush.h>
133#include <linux/bootmem.h>
134#include <linux/blkdev.h>
135#ifdef CONFIG_TOSHIBA_FPCIB0 116#ifdef CONFIG_TOSHIBA_FPCIB0
136#include <asm/i8259.h> 117#include <asm/i8259.h>
137#include <asm/tx4927/smsc_fdc37m81x.h>
138#endif 118#endif
139#include <asm/tx4927/toshiba_rbtx4927.h> 119#include <asm/tx4927/toshiba_rbtx4927.h>
140 120
141
142#undef TOSHIBA_RBTX4927_IRQ_DEBUG
143
144#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
145#define TOSHIBA_RBTX4927_IRQ_NONE 0x00000000
146
147#define TOSHIBA_RBTX4927_IRQ_INFO ( 1 << 0 )
148#define TOSHIBA_RBTX4927_IRQ_WARN ( 1 << 1 )
149#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 )
150
151#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
152#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
153#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
154
155#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
156#endif
157
158
159#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
160static const u32 toshiba_rbtx4927_irq_debug_flag =
161 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
162 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
163// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
164// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
165// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
166 );
167#endif
168
169
170#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
171#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \
172 if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \
173 { \
174 char tmp[100]; \
175 sprintf( tmp, str ); \
176 printk( "%s(%s:%u)::%s", __func__, __FILE__, __LINE__, tmp ); \
177 }
178#else
179#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag, str...)
180#endif
181
182
183
184
185#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 121#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0
186#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 122#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7
187 123
@@ -207,39 +143,22 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
207#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL 143#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL
208#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL 144#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL
209 145
210
211u32 bit2num(u32 num)
212{
213 u32 i;
214
215 for (i = 0; i < (sizeof(num) * 8); i++) {
216 if (num & (1 << i)) {
217 return (i);
218 }
219 }
220 return (0);
221}
222
223int toshiba_rbtx4927_irq_nested(int sw_irq) 146int toshiba_rbtx4927_irq_nested(int sw_irq)
224{ 147{
225 u32 level3; 148 u8 level3;
226 149
227 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 150 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
228 if (level3) { 151 if (level3) {
229 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3); 152 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1;
230 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
231 goto RETURN;
232 }
233 }
234#ifdef CONFIG_TOSHIBA_FPCIB0 153#ifdef CONFIG_TOSHIBA_FPCIB0
235 if (tx4927_using_backplane) { 154 if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC &&
236 int irq = i8259_irq(); 155 tx4927_using_backplane) {
237 if (irq >= 0) 156 int irq = i8259_irq();
238 sw_irq = irq; 157 if (irq >= 0)
239 } 158 sw_irq = irq;
159 }
240#endif 160#endif
241 161 }
242 RETURN:
243 return (sw_irq); 162 return (sw_irq);
244} 163}
245 164
@@ -250,21 +169,10 @@ static struct irqaction toshiba_rbtx4927_irq_ioc_action = {
250 .name = TOSHIBA_RBTX4927_IOC_NAME 169 .name = TOSHIBA_RBTX4927_IOC_NAME
251}; 170};
252 171
253
254/**********************************************************************************/
255/* Functions for ioc */
256/**********************************************************************************/
257
258
259static void __init toshiba_rbtx4927_irq_ioc_init(void) 172static void __init toshiba_rbtx4927_irq_ioc_init(void)
260{ 173{
261 int i; 174 int i;
262 175
263 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT,
264 "beg=%d end=%d\n",
265 TOSHIBA_RBTX4927_IRQ_IOC_BEG,
266 TOSHIBA_RBTX4927_IRQ_IOC_END);
267
268 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; 176 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
269 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) 177 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
270 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, 178 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
@@ -276,37 +184,16 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void)
276 184
277static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) 185static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
278{ 186{
279 volatile unsigned char v; 187 unsigned char v;
280
281 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
282 "irq=%d\n", irq);
283
284 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
285 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
286 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
287 "bad irq=%d\n", irq);
288 panic("\n");
289 }
290 188
291 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 189 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
292 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 190 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
293 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); 191 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
294} 192}
295 193
296
297static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) 194static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
298{ 195{
299 volatile unsigned char v; 196 unsigned char v;
300
301 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
302 "irq=%d\n", irq);
303
304 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
305 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
306 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
307 "bad irq=%d\n", irq);
308 panic("\n");
309 }
310 197
311 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 198 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
312 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 199 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
@@ -314,7 +201,6 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
314 mmiowb(); 201 mmiowb();
315} 202}
316 203
317
318void __init arch_init_irq(void) 204void __init arch_init_irq(void)
319{ 205{
320 extern void tx4927_irq_init(void); 206 extern void tx4927_irq_init(void);
@@ -327,102 +213,4 @@ void __init arch_init_irq(void)
327#endif 213#endif
328 /* Onboard 10M Ether: High Active */ 214 /* Onboard 10M Ether: High Active */
329 set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); 215 set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
330
331 wbflush();
332}
333
334void toshiba_rbtx4927_irq_dump(char *key)
335{
336#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
337 {
338 u32 i, j = 0;
339 for (i = 0; i < NR_IRQS; i++) {
340 if (strcmp(irq_desc[i].chip->name, "none")
341 == 0)
342 continue;
343
344 if ((i >= 1)
345 && (irq_desc[i - 1].chip->name ==
346 irq_desc[i].chip->name)) {
347 j++;
348 } else {
349 j = 0;
350 }
351 TOSHIBA_RBTX4927_IRQ_DPRINTK
352 (TOSHIBA_RBTX4927_IRQ_INFO,
353 "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
354 key, i, i, irq_desc[i].status,
355 (u32) irq_desc[i].chip,
356 (u32) irq_desc[i].action,
357 (u32) (irq_desc[i].action ? irq_desc[i].
358 action->handler : 0),
359 irq_desc[i].depth,
360 irq_desc[i].chip->name, j);
361 }
362 }
363#endif
364}
365
366void toshiba_rbtx4927_irq_dump_pics(char *s)
367{
368 u32 level0_m;
369 u32 level0_s;
370 u32 level1_m;
371 u32 level1_s;
372 u32 level2;
373 u32 level2_p;
374 u32 level2_s;
375 u32 level3_m;
376 u32 level3_s;
377 u32 level4_m;
378 u32 level4_s;
379 u32 level5_m;
380 u32 level5_s;
381
382 if (s == NULL)
383 s = "null";
384
385 level0_m = (read_c0_status() & 0x0000ff00) >> 8;
386 level0_s = (read_c0_cause() & 0x0000ff00) >> 8;
387
388 level1_m = level0_m;
389 level1_s = level0_s & 0x87;
390
391 level2 = __raw_readl((void __iomem *)0xff1ff6a0UL);
392 level2_p = (((level2 & 0x10000)) ? 0 : 1);
393 level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
394
395 level3_m = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
396 level3_s = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
397
398 level4_m = inb(0x21);
399 outb(0x0A, 0x20);
400 level4_s = inb(0x20);
401
402 level5_m = inb(0xa1);
403 outb(0x0A, 0xa0);
404 level5_s = inb(0xa0);
405
406 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
407 "dump_raw_pic() ");
408 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
409 "cp0:m=0x%02x/s=0x%02x ", level0_m,
410 level0_s);
411 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
412 "cp0:m=0x%02x/s=0x%02x ", level1_m,
413 level1_s);
414 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
415 "pic:e=0x%02x/s=0x%02x ", level2_p,
416 level2_s);
417 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
418 "ioc:m=0x%02x/s=0x%02x ", level3_m,
419 level3_s);
420 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
421 "sbm:m=0x%02x/s=0x%02x ", level4_m,
422 level4_s);
423 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
424 "sbs:m=0x%02x/s=0x%02x ", level5_m,
425 level5_s);
426 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
427 s);
428} 216}
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
index f3f86857beae..fdbad4bc6021 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
@@ -30,13 +30,10 @@
30 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */ 31 */
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/mm.h> 33#include <linux/string.h>
34#include <linux/sched.h>
35#include <linux/bootmem.h>
36
37#include <asm/addrspace.h>
38#include <asm/bootinfo.h> 34#include <asm/bootinfo.h>
39#include <asm/cpu.h> 35#include <asm/cpu.h>
36#include <asm/mipsregs.h>
40#include <asm/tx4927/tx4927.h> 37#include <asm/tx4927/tx4927.h>
41 38
42void __init prom_init_cmdline(void) 39void __init prom_init_cmdline(void)
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index 2203c77b2ce2..185f303c0e2a 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -62,43 +62,10 @@
62#include <asm/tx4927/smsc_fdc37m81x.h> 62#include <asm/tx4927/smsc_fdc37m81x.h>
63#endif 63#endif
64#include <asm/tx4927/toshiba_rbtx4927.h> 64#include <asm/tx4927/toshiba_rbtx4927.h>
65#ifdef CONFIG_PCI
66#include <asm/tx4927/tx4927_pci.h>
67#endif
68#ifdef CONFIG_SERIAL_TXX9 65#ifdef CONFIG_SERIAL_TXX9
69#include <linux/serial_core.h> 66#include <linux/serial_core.h>
70#endif 67#endif
71 68
72#undef TOSHIBA_RBTX4927_SETUP_DEBUG
73
74#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
75#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
76#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
77#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
78#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
79
80#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
81#endif
82
83#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
84static const u32 toshiba_rbtx4927_setup_debug_flag =
85 (TOSHIBA_RBTX4927_SETUP_SETUP |
86 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
87 TOSHIBA_RBTX4927_SETUP_PCI2);
88#endif
89
90#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
91#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
92 if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
93 { \
94 char tmp[100]; \
95 sprintf( tmp, str ); \
96 printk( "%s(%s:%u)::%s", __func__, __FILE__, __LINE__, tmp ); \
97 }
98#else
99#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...)
100#endif
101
102/* These functions are used for rebooting or halting the machine*/ 69/* These functions are used for rebooting or halting the machine*/
103extern void toshiba_rbtx4927_restart(char *command); 70extern void toshiba_rbtx4927_restart(char *command);
104extern void toshiba_rbtx4927_halt(void); 71extern void toshiba_rbtx4927_halt(void);
@@ -124,7 +91,6 @@ unsigned long mips_memory_upper;
124static int tx4927_ccfg_toeon = 1; 91static int tx4927_ccfg_toeon = 1;
125static int tx4927_pcic_trdyto = 0; /* default: disabled */ 92static int tx4927_pcic_trdyto = 0; /* default: disabled */
126unsigned long tx4927_ce_base[8]; 93unsigned long tx4927_ce_base[8];
127void tx4927_reset_pci_pcic(void);
128int tx4927_pci66 = 0; /* 0:auto */ 94int tx4927_pci66 = 0; /* 0:auto */
129#endif 95#endif
130 96
@@ -172,9 +138,6 @@ static int __init tx4927_pcibios_init(void)
172 int busno = 0; /* One bus on the Toshiba */ 138 int busno = 0; /* One bus on the Toshiba */
173 struct pci_controller *hose = &tx4927_controller; 139 struct pci_controller *hose = &tx4927_controller;
174 140
175 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
176 "-\n");
177
178 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { 141 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
179 early_read_config_dword(hose, busno, busno, pci_devfn, 142 early_read_config_dword(hose, busno, busno, pci_devfn,
180 PCI_VENDOR_ID, &id); 143 PCI_VENDOR_ID, &id);
@@ -187,13 +150,6 @@ static int __init tx4927_pcibios_init(void)
187 u8 v08_64; 150 u8 v08_64;
188 u32 v32_b0; 151 u32 v32_b0;
189 u8 v08_e1; 152 u8 v08_e1;
190#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
191 char *s = " sb/isa --";
192#endif
193
194 TOSHIBA_RBTX4927_SETUP_DPRINTK
195 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
196 s);
197 153
198 early_read_config_byte(hose, busno, busno, 154 early_read_config_byte(hose, busno, busno,
199 pci_devfn, 0x64, &v08_64); 155 pci_devfn, 0x64, &v08_64);
@@ -202,16 +158,6 @@ static int __init tx4927_pcibios_init(void)
202 early_read_config_byte(hose, busno, busno, 158 early_read_config_byte(hose, busno, busno,
203 pci_devfn, 0xe1, &v08_e1); 159 pci_devfn, 0xe1, &v08_e1);
204 160
205 TOSHIBA_RBTX4927_SETUP_DPRINTK
206 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
207 ":%s beg 0x64 = 0x%02x\n", s, v08_64);
208 TOSHIBA_RBTX4927_SETUP_DPRINTK
209 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
210 ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
211 TOSHIBA_RBTX4927_SETUP_DPRINTK
212 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
213 ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
214
215 /* serial irq control */ 161 /* serial irq control */
216 v08_64 = 0xd0; 162 v08_64 = 0xd0;
217 163
@@ -222,50 +168,12 @@ static int __init tx4927_pcibios_init(void)
222 v08_e1 &= 0xf0; 168 v08_e1 &= 0xf0;
223 v08_e1 |= 0x0d; 169 v08_e1 |= 0x0d;
224 170
225 TOSHIBA_RBTX4927_SETUP_DPRINTK
226 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
227 ":%s mid 0x64 = 0x%02x\n", s, v08_64);
228 TOSHIBA_RBTX4927_SETUP_DPRINTK
229 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
230 ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
231 TOSHIBA_RBTX4927_SETUP_DPRINTK
232 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
233 ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
234
235 early_write_config_byte(hose, busno, busno, 171 early_write_config_byte(hose, busno, busno,
236 pci_devfn, 0x64, v08_64); 172 pci_devfn, 0x64, v08_64);
237 early_write_config_dword(hose, busno, busno, 173 early_write_config_dword(hose, busno, busno,
238 pci_devfn, 0xb0, v32_b0); 174 pci_devfn, 0xb0, v32_b0);
239 early_write_config_byte(hose, busno, busno, 175 early_write_config_byte(hose, busno, busno,
240 pci_devfn, 0xe1, v08_e1); 176 pci_devfn, 0xe1, v08_e1);
241
242#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
243 {
244 early_read_config_byte(hose, busno, busno,
245 pci_devfn, 0x64,
246 &v08_64);
247 early_read_config_dword(hose, busno, busno,
248 pci_devfn, 0xb0,
249 &v32_b0);
250 early_read_config_byte(hose, busno, busno,
251 pci_devfn, 0xe1,
252 &v08_e1);
253
254 TOSHIBA_RBTX4927_SETUP_DPRINTK
255 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
256 ":%s end 0x64 = 0x%02x\n", s, v08_64);
257 TOSHIBA_RBTX4927_SETUP_DPRINTK
258 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
259 ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
260 TOSHIBA_RBTX4927_SETUP_DPRINTK
261 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
262 ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
263 }
264#endif
265
266 TOSHIBA_RBTX4927_SETUP_DPRINTK
267 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
268 s);
269 } 177 }
270 178
271 if (id == 0x91301055) { 179 if (id == 0x91301055) {
@@ -274,13 +182,6 @@ static int __init tx4927_pcibios_init(void)
274 u8 v08_41; 182 u8 v08_41;
275 u8 v08_43; 183 u8 v08_43;
276 u8 v08_5c; 184 u8 v08_5c;
277#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
278 char *s = " sb/ide --";
279#endif
280
281 TOSHIBA_RBTX4927_SETUP_DPRINTK
282 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
283 s);
284 185
285 early_read_config_byte(hose, busno, busno, 186 early_read_config_byte(hose, busno, busno,
286 pci_devfn, 0x04, &v08_04); 187 pci_devfn, 0x04, &v08_04);
@@ -293,22 +194,6 @@ static int __init tx4927_pcibios_init(void)
293 early_read_config_byte(hose, busno, busno, 194 early_read_config_byte(hose, busno, busno,
294 pci_devfn, 0x5c, &v08_5c); 195 pci_devfn, 0x5c, &v08_5c);
295 196
296 TOSHIBA_RBTX4927_SETUP_DPRINTK
297 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
298 ":%s beg 0x04 = 0x%02x\n", s, v08_04);
299 TOSHIBA_RBTX4927_SETUP_DPRINTK
300 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
301 ":%s beg 0x09 = 0x%02x\n", s, v08_09);
302 TOSHIBA_RBTX4927_SETUP_DPRINTK
303 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
304 ":%s beg 0x41 = 0x%02x\n", s, v08_41);
305 TOSHIBA_RBTX4927_SETUP_DPRINTK
306 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
307 ":%s beg 0x43 = 0x%02x\n", s, v08_43);
308 TOSHIBA_RBTX4927_SETUP_DPRINTK
309 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
310 ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
311
312 /* enable ide master/io */ 197 /* enable ide master/io */
313 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); 198 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
314 199
@@ -332,22 +217,6 @@ static int __init tx4927_pcibios_init(void)
332 */ 217 */
333 v08_5c |= 0x01; 218 v08_5c |= 0x01;
334 219
335 TOSHIBA_RBTX4927_SETUP_DPRINTK
336 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
337 ":%s mid 0x04 = 0x%02x\n", s, v08_04);
338 TOSHIBA_RBTX4927_SETUP_DPRINTK
339 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
340 ":%s mid 0x09 = 0x%02x\n", s, v08_09);
341 TOSHIBA_RBTX4927_SETUP_DPRINTK
342 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
343 ":%s mid 0x41 = 0x%02x\n", s, v08_41);
344 TOSHIBA_RBTX4927_SETUP_DPRINTK
345 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
346 ":%s mid 0x43 = 0x%02x\n", s, v08_43);
347 TOSHIBA_RBTX4927_SETUP_DPRINTK
348 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
349 ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
350
351 early_write_config_byte(hose, busno, busno, 220 early_write_config_byte(hose, busno, busno,
352 pci_devfn, 0x5c, v08_5c); 221 pci_devfn, 0x5c, v08_5c);
353 early_write_config_byte(hose, busno, busno, 222 early_write_config_byte(hose, busno, busno,
@@ -358,54 +227,11 @@ static int __init tx4927_pcibios_init(void)
358 pci_devfn, 0x41, v08_41); 227 pci_devfn, 0x41, v08_41);
359 early_write_config_byte(hose, busno, busno, 228 early_write_config_byte(hose, busno, busno,
360 pci_devfn, 0x43, v08_43); 229 pci_devfn, 0x43, v08_43);
361
362#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
363 {
364 early_read_config_byte(hose, busno, busno,
365 pci_devfn, 0x04,
366 &v08_04);
367 early_read_config_byte(hose, busno, busno,
368 pci_devfn, 0x09,
369 &v08_09);
370 early_read_config_byte(hose, busno, busno,
371 pci_devfn, 0x41,
372 &v08_41);
373 early_read_config_byte(hose, busno, busno,
374 pci_devfn, 0x43,
375 &v08_43);
376 early_read_config_byte(hose, busno, busno,
377 pci_devfn, 0x5c,
378 &v08_5c);
379
380 TOSHIBA_RBTX4927_SETUP_DPRINTK
381 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
382 ":%s end 0x04 = 0x%02x\n", s, v08_04);
383 TOSHIBA_RBTX4927_SETUP_DPRINTK
384 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
385 ":%s end 0x09 = 0x%02x\n", s, v08_09);
386 TOSHIBA_RBTX4927_SETUP_DPRINTK
387 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
388 ":%s end 0x41 = 0x%02x\n", s, v08_41);
389 TOSHIBA_RBTX4927_SETUP_DPRINTK
390 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
391 ":%s end 0x43 = 0x%02x\n", s, v08_43);
392 TOSHIBA_RBTX4927_SETUP_DPRINTK
393 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
394 ":%s end 0x5c = 0x%02x\n", s, v08_5c);
395 }
396#endif
397
398 TOSHIBA_RBTX4927_SETUP_DPRINTK
399 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
400 s);
401 } 230 }
402 231
403 } 232 }
404 233
405 register_pci_controller(&tx4927_controller); 234 register_pci_controller(&tx4927_controller);
406 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
407 "+\n");
408
409 return 0; 235 return 0;
410} 236}
411 237
@@ -419,45 +245,13 @@ void __init tx4927_pci_setup(void)
419 static int called = 0; 245 static int called = 0;
420 extern unsigned int tx4927_get_mem_size(void); 246 extern unsigned int tx4927_get_mem_size(void);
421 247
422 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
423
424 mips_memory_upper = tx4927_get_mem_size() << 20; 248 mips_memory_upper = tx4927_get_mem_size() << 20;
425 mips_memory_upper += KSEG0; 249 mips_memory_upper += KSEG0;
426 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
427 "0x%08lx=mips_memory_upper\n",
428 mips_memory_upper);
429 mips_pci_io_base = TX4927_PCIIO; 250 mips_pci_io_base = TX4927_PCIIO;
430 mips_pci_io_size = TX4927_PCIIO_SIZE; 251 mips_pci_io_size = TX4927_PCIIO_SIZE;
431 mips_pci_mem_base = TX4927_PCIMEM; 252 mips_pci_mem_base = TX4927_PCIMEM;
432 mips_pci_mem_size = TX4927_PCIMEM_SIZE; 253 mips_pci_mem_size = TX4927_PCIMEM_SIZE;
433 254
434 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
435 "0x%08lx=mips_pci_io_base\n",
436 mips_pci_io_base);
437 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
438 "0x%08lx=mips_pci_io_size\n",
439 mips_pci_io_size);
440 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
441 "0x%08lx=mips_pci_mem_base\n",
442 mips_pci_mem_base);
443 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
444 "0x%08lx=mips_pci_mem_size\n",
445 mips_pci_mem_size);
446 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
447 "0x%08lx=pci_io_resource.start\n",
448 pci_io_resource.start);
449 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
450 "0x%08lx=pci_io_resource.end\n",
451 pci_io_resource.end);
452 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
453 "0x%08lx=pci_mem_resource.start\n",
454 pci_mem_resource.start);
455 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
456 "0x%08lx=pci_mem_resource.end\n",
457 pci_mem_resource.end);
458 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
459 "0x%08lx=mips_io_port_base",
460 mips_io_port_base);
461 if (!called) { 255 if (!called) {
462 printk 256 printk
463 ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", 257 ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
@@ -521,29 +315,10 @@ void __init tx4927_pci_setup(void)
521 } 315 }
522 316
523 printk("Internal(%dMHz)", pciclk / 1000000); 317 printk("Internal(%dMHz)", pciclk / 1000000);
524 } else { 318 } else
525 int pciclk = 0; 319 printk("External");
526 int pciclk_setting = *tx4927_pci_clk_ptr;
527 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
528 case TX4927_PCI_CLK_33:
529 pciclk = 33333333;
530 break;
531 case TX4927_PCI_CLK_25:
532 pciclk = 25000000;
533 break;
534 case TX4927_PCI_CLK_66:
535 pciclk = 66666666;
536 break;
537 case TX4927_PCI_CLK_50:
538 pciclk = 50000000;
539 break;
540 }
541 printk("External(%dMHz)", pciclk / 1000000);
542 }
543 printk("\n"); 320 printk("\n");
544 321
545
546
547 /* GB->PCI mappings */ 322 /* GB->PCI mappings */
548 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; 323 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
549 tx4927_pcicptr->g2piogbase = mips_pci_io_base | 324 tx4927_pcicptr->g2piogbase = mips_pci_io_base |
@@ -644,12 +419,7 @@ void __init tx4927_pci_setup(void)
644 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | 419 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
645 PCI_COMMAND_MEMORY | 420 PCI_COMMAND_MEMORY |
646 PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 421 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
647
648 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
649 ":pci setup complete:\n");
650 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
651} 422}
652
653#endif /* CONFIG_PCI */ 423#endif /* CONFIG_PCI */
654 424
655static void __noreturn wait_forever(void) 425static void __noreturn wait_forever(void)
@@ -679,7 +449,6 @@ void toshiba_rbtx4927_restart(char *command)
679 /* no return */ 449 /* no return */
680} 450}
681 451
682
683void toshiba_rbtx4927_halt(void) 452void toshiba_rbtx4927_halt(void)
684{ 453{
685 printk(KERN_NOTICE "System Halted\n"); 454 printk(KERN_NOTICE "System Halted\n");
@@ -702,33 +471,19 @@ void __init plat_mem_setup(void)
702 471
703 printk("CPU is %s\n", toshiba_name); 472 printk("CPU is %s\n", toshiba_name);
704 473
705 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
706 "-\n");
707
708 /* f/w leaves this on at startup */ 474 /* f/w leaves this on at startup */
709 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
710 ":Clearing STO_ERL.\n");
711 clear_c0_status(ST0_ERL); 475 clear_c0_status(ST0_ERL);
712 476
713 /* enable caches -- HCP5 does this, pmon does not */ 477 /* enable caches -- HCP5 does this, pmon does not */
714 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
715 ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
716 cp0_config = read_c0_config(); 478 cp0_config = read_c0_config();
717 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); 479 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
718 write_c0_config(cp0_config); 480 write_c0_config(cp0_config);
719 481
720 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); 482 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
721 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
722 ":mips_io_port_base=0x%08lx\n",
723 mips_io_port_base);
724 483
725 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
726 ":Resource\n");
727 ioport_resource.end = 0xffffffff; 484 ioport_resource.end = 0xffffffff;
728 iomem_resource.end = 0xffffffff; 485 iomem_resource.end = 0xffffffff;
729 486
730 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
731 ":ResetRoutines\n");
732 _machine_restart = toshiba_rbtx4927_restart; 487 _machine_restart = toshiba_rbtx4927_restart;
733 _machine_halt = toshiba_rbtx4927_halt; 488 _machine_halt = toshiba_rbtx4927_halt;
734 pm_power_off = toshiba_rbtx4927_power_off; 489 pm_power_off = toshiba_rbtx4927_power_off;
@@ -761,23 +516,6 @@ void __init plat_mem_setup(void)
761 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) 516 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
762 * 517 *
763 */ 518 */
764 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
765 "ccfg is %lx, PCIDIVMODE is %x\n",
766 (unsigned long) tx4927_ccfgptr->ccfg,
767 (unsigned long) tx4927_ccfgptr->ccfg &
768 (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
769 TX4937_CCFG_PCIDIVMODE_MASK :
770 TX4927_CCFG_PCIDIVMODE_MASK));
771
772 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
773 "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
774 (unsigned long) tx4927_ccfgptr->
775 ccfg & TX4927_CCFG_PCI66,
776 (unsigned long) tx4927_ccfgptr->
777 ccfg & TX4927_CCFG_PCIMIDE,
778 (unsigned long) tx4927_ccfgptr->
779 ccfg & TX4927_CCFG_PCIXARB);
780
781 if (mips_machtype == MACH_TOSHIBA_RBTX4937) 519 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
782 switch ((unsigned long)tx4927_ccfgptr-> 520 switch ((unsigned long)tx4927_ccfgptr->
783 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { 521 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
@@ -818,49 +556,18 @@ void __init plat_mem_setup(void)
818 556
819 /* this is on ISA bus behind PCI bus, so need PCI up first */ 557 /* this is on ISA bus behind PCI bus, so need PCI up first */
820#ifdef CONFIG_TOSHIBA_FPCIB0 558#ifdef CONFIG_TOSHIBA_FPCIB0
821 { 559 if (tx4927_using_backplane) {
822 if (tx4927_using_backplane) { 560 smsc_fdc37m81x_init(0x3f0);
823 TOSHIBA_RBTX4927_SETUP_DPRINTK 561 smsc_fdc37m81x_config_beg();
824 (TOSHIBA_RBTX4927_SETUP_SETUP, 562 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
825 ":fpcibo=yes\n"); 563 SMSC_FDC37M81X_KBD);
826 564 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
827 TOSHIBA_RBTX4927_SETUP_DPRINTK 565 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
828 (TOSHIBA_RBTX4927_SETUP_SETUP, 566 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
829 ":smsc_fdc37m81x_init()\n"); 567 1);
830 smsc_fdc37m81x_init(0x3f0); 568 smsc_fdc37m81x_config_end();
831
832 TOSHIBA_RBTX4927_SETUP_DPRINTK
833 (TOSHIBA_RBTX4927_SETUP_SETUP,
834 ":smsc_fdc37m81x_config_beg()\n");
835 smsc_fdc37m81x_config_beg();
836
837 TOSHIBA_RBTX4927_SETUP_DPRINTK
838 (TOSHIBA_RBTX4927_SETUP_SETUP,
839 ":smsc_fdc37m81x_config_set(KBD)\n");
840 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
841 SMSC_FDC37M81X_KBD);
842 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
843 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
844 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
845 1);
846
847 smsc_fdc37m81x_config_end();
848 TOSHIBA_RBTX4927_SETUP_DPRINTK
849 (TOSHIBA_RBTX4927_SETUP_SETUP,
850 ":smsc_fdc37m81x_config_end()\n");
851 } else {
852 TOSHIBA_RBTX4927_SETUP_DPRINTK
853 (TOSHIBA_RBTX4927_SETUP_SETUP,
854 ":fpcibo=not_found\n");
855 }
856 }
857#else
858 {
859 TOSHIBA_RBTX4927_SETUP_DPRINTK
860 (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
861 } 569 }
862#endif 570#endif
863
864#endif /* CONFIG_PCI */ 571#endif /* CONFIG_PCI */
865 572
866#ifdef CONFIG_SERIAL_TXX9 573#ifdef CONFIG_SERIAL_TXX9
@@ -894,17 +601,12 @@ void __init plat_mem_setup(void)
894 } 601 }
895#endif 602#endif
896 603
897
898#ifdef CONFIG_IP_PNP 604#ifdef CONFIG_IP_PNP
899 argptr = prom_getcmdline(); 605 argptr = prom_getcmdline();
900 if (strstr(argptr, "ip=") == NULL) { 606 if (strstr(argptr, "ip=") == NULL) {
901 strcat(argptr, " ip=any"); 607 strcat(argptr, " ip=any");
902 } 608 }
903#endif 609#endif
904
905
906 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
907 "+\n");
908} 610}
909 611
910void __init plat_time_init(void) 612void __init plat_time_init(void)
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
index b188a659ce02..d6b32acd6b7b 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h
@@ -28,9 +28,6 @@
28#define __ASM_TX4927_TOSHIBA_RBTX4927_H 28#define __ASM_TX4927_TOSHIBA_RBTX4927_H
29 29
30#include <asm/tx4927/tx4927.h> 30#include <asm/tx4927/tx4927.h>
31#ifdef CONFIG_PCI
32#include <asm/tx4927/tx4927_pci.h>
33#endif
34 31
35#ifdef CONFIG_PCI 32#ifdef CONFIG_PCI
36#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO 33#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO
@@ -44,7 +41,6 @@
44#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL 41#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
45#define RBTX4927_SW_RESET_ENABLE_SET 0x01 42#define RBTX4927_SW_RESET_ENABLE_SET 0x01
46 43
47
48#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) 44#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
49#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) 45#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5)
50 46
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index 193e80a17c12..1d4816f3266f 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -36,11 +36,245 @@
36#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) 36#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
37 37
38 38
39#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) 39#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
40#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) 40#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1)
41#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) 41#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2)
42#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) 42#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7)
43 43
44#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) 44#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3)
45 45
46#define TX4927_CCFG_TOE 0x00004000
47#define TX4927_CCFG_WR 0x00008000
48#define TX4927_CCFG_TINTDIS 0x01000000
49
50#define TX4927_PCIMEM 0x08000000
51#define TX4927_PCIMEM_SIZE 0x08000000
52#define TX4927_PCIIO 0x16000000
53#define TX4927_PCIIO_SIZE 0x01000000
54
55#define TX4927_SDRAMC_REG 0xff1f8000
56#define TX4927_EBUSC_REG 0xff1f9000
57#define TX4927_PCIC_REG 0xff1fd000
58#define TX4927_CCFG_REG 0xff1fe000
59#define TX4927_IRC_REG 0xff1ff600
60#define TX4927_NR_TMR 3
61#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
62
63/* bits for ISTAT3/IMASK3/IMSTAT3 */
64#define TX4927_INT3B_PCID 0
65#define TX4927_INT3B_PCIC 1
66#define TX4927_INT3B_PCIB 2
67#define TX4927_INT3B_PCIA 3
68#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
69#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
70#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
71#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
72
73#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
74#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
75
76#define TX4927_IR_PCIC 16
77#define TX4927_IR_PCIERR 22
78#define TX4927_IR_PCIPMA 23
79#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
80#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
81#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
82#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
83#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
84#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
85#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
86
87#ifdef _LANGUAGE_ASSEMBLY
88#define _CONST64(c) c
89#else
90#define _CONST64(c) c##ull
91
92#include <asm/byteorder.h>
93
94struct tx4927_sdramc_reg {
95 volatile unsigned long long cr[4];
96 volatile unsigned long long unused0[4];
97 volatile unsigned long long tr;
98 volatile unsigned long long unused1[2];
99 volatile unsigned long long cmd;
100};
101
102struct tx4927_ebusc_reg {
103 volatile unsigned long long cr[8];
104};
105
106struct tx4927_ccfg_reg {
107 volatile unsigned long long ccfg;
108 volatile unsigned long long crir;
109 volatile unsigned long long pcfg;
110 volatile unsigned long long tear;
111 volatile unsigned long long clkctr;
112 volatile unsigned long long unused0;
113 volatile unsigned long long garbc;
114 volatile unsigned long long unused1;
115 volatile unsigned long long unused2;
116 volatile unsigned long long ramp;
117};
118
119struct tx4927_pcic_reg {
120 volatile unsigned long pciid;
121 volatile unsigned long pcistatus;
122 volatile unsigned long pciccrev;
123 volatile unsigned long pcicfg1;
124 volatile unsigned long p2gm0plbase; /* +10 */
125 volatile unsigned long p2gm0pubase;
126 volatile unsigned long p2gm1plbase;
127 volatile unsigned long p2gm1pubase;
128 volatile unsigned long p2gm2pbase; /* +20 */
129 volatile unsigned long p2giopbase;
130 volatile unsigned long unused0;
131 volatile unsigned long pcisid;
132 volatile unsigned long unused1; /* +30 */
133 volatile unsigned long pcicapptr;
134 volatile unsigned long unused2;
135 volatile unsigned long pcicfg2;
136 volatile unsigned long g2ptocnt; /* +40 */
137 volatile unsigned long unused3[15];
138 volatile unsigned long g2pstatus; /* +80 */
139 volatile unsigned long g2pmask;
140 volatile unsigned long pcisstatus;
141 volatile unsigned long pcimask;
142 volatile unsigned long p2gcfg; /* +90 */
143 volatile unsigned long p2gstatus;
144 volatile unsigned long p2gmask;
145 volatile unsigned long p2gccmd;
146 volatile unsigned long unused4[24]; /* +a0 */
147 volatile unsigned long pbareqport; /* +100 */
148 volatile unsigned long pbacfg;
149 volatile unsigned long pbastatus;
150 volatile unsigned long pbamask;
151 volatile unsigned long pbabm; /* +110 */
152 volatile unsigned long pbacreq;
153 volatile unsigned long pbacgnt;
154 volatile unsigned long pbacstate;
155 volatile unsigned long long g2pmgbase[3]; /* +120 */
156 volatile unsigned long long g2piogbase;
157 volatile unsigned long g2pmmask[3]; /* +140 */
158 volatile unsigned long g2piomask;
159 volatile unsigned long long g2pmpbase[3]; /* +150 */
160 volatile unsigned long long g2piopbase;
161 volatile unsigned long pciccfg; /* +170 */
162 volatile unsigned long pcicstatus;
163 volatile unsigned long pcicmask;
164 volatile unsigned long unused5;
165 volatile unsigned long long p2gmgbase[3]; /* +180 */
166 volatile unsigned long long p2giogbase;
167 volatile unsigned long g2pcfgadrs; /* +1a0 */
168 volatile unsigned long g2pcfgdata;
169 volatile unsigned long unused6[8];
170 volatile unsigned long g2pintack;
171 volatile unsigned long g2pspc;
172 volatile unsigned long unused7[12]; /* +1d0 */
173 volatile unsigned long long pdmca; /* +200 */
174 volatile unsigned long long pdmga;
175 volatile unsigned long long pdmpa;
176 volatile unsigned long long pdmcut;
177 volatile unsigned long long pdmcnt; /* +220 */
178 volatile unsigned long long pdmsts;
179 volatile unsigned long long unused8[2];
180 volatile unsigned long long pdmdb[4]; /* +240 */
181 volatile unsigned long long pdmtdh; /* +260 */
182 volatile unsigned long long pdmdms;
183};
184
185#endif /* _LANGUAGE_ASSEMBLY */
186
187/*
188 * PCIC
189 */
190
191/* bits for G2PSTATUS/G2PMASK */
192#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
193#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
194#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
195
196/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
197#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
198
199/* bits for PBACFG */
200#define TX4927_PCIC_PBACFG_RPBA 0x00000004
201#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
202#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
203
204/* bits for G2PMnGBASE */
205#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
206#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
207
208/* bits for G2PIOGBASE */
209#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
210#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
211
212/* bits for PCICSTATUS/PCICMASK */
213#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
214
215/* bits for PCICCFG */
216#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
217#define TX4927_PCIC_PCICCFG_HRST 0x00000800
218#define TX4927_PCIC_PCICCFG_SRST 0x00000400
219#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
220#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
221#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
222#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
223#define TX4927_PCIC_PCICCFG_IISE 0x00000020
224#define TX4927_PCIC_PCICCFG_ATR 0x00000010
225#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
226
227/* bits for P2GMnGBASE */
228#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
229#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
230#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
231
232/* bits for P2GIOGBASE */
233#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
234#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
235#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
236
237#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
238#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
239
240/*
241 * CCFG
242 */
243/* CCFG : Chip Configuration */
244#define TX4927_CCFG_PCI66 0x00800000
245#define TX4927_CCFG_PCIMIDE 0x00400000
246#define TX4927_CCFG_PCIXARB 0x00002000
247#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
248#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
249#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
250#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
251#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
252
253#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
254#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
255#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
256#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
257#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
258#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
259#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
260#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
261#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
262
263/* PCFG : Pin Configuration */
264#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
265#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
266
267/* CLKCTR : Clock Control */
268#define TX4927_CLKCTR_PCICKD 0x00400000
269#define TX4927_CLKCTR_PCIRST 0x00000040
270
271#ifndef _LANGUAGE_ASSEMBLY
272
273#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
274#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
275#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
276#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
277
278#endif /* _LANGUAGE_ASSEMBLY */
279
46#endif /* __ASM_TX4927_TX4927_H */ 280#endif /* __ASM_TX4927_TX4927_H */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
deleted file mode 100644
index 0be77df70f2b..000000000000
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ /dev/null
@@ -1,268 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000-2001 Toshiba Corporation
7 */
8#ifndef __ASM_TX4927_TX4927_PCI_H
9#define __ASM_TX4927_TX4927_PCI_H
10
11#define TX4927_CCFG_TOE 0x00004000
12#define TX4927_CCFG_WR 0x00008000
13#define TX4927_CCFG_TINTDIS 0x01000000
14
15#define TX4927_PCIMEM 0x08000000
16#define TX4927_PCIMEM_SIZE 0x08000000
17#define TX4927_PCIIO 0x16000000
18#define TX4927_PCIIO_SIZE 0x01000000
19
20#define TX4927_SDRAMC_REG 0xff1f8000
21#define TX4927_EBUSC_REG 0xff1f9000
22#define TX4927_PCIC_REG 0xff1fd000
23#define TX4927_CCFG_REG 0xff1fe000
24#define TX4927_IRC_REG 0xff1ff600
25#define TX4927_NR_TMR 3
26#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
27#define TX4927_CE3 0x17f00000 /* 1M */
28#define TX4927_PCIRESET_ADDR 0xbc00f006
29#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
30
31#define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n))
32#define tx4927_imstat_ptr(n) \
33 ((volatile unsigned char *)TX4927_IMSTAT_ADDR(n))
34
35/* bits for ISTAT3/IMASK3/IMSTAT3 */
36#define TX4927_INT3B_PCID 0
37#define TX4927_INT3B_PCIC 1
38#define TX4927_INT3B_PCIB 2
39#define TX4927_INT3B_PCIA 3
40#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
41#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
42#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
43#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
44
45/* bits for PCI_CLK (S6) */
46#define TX4927_PCI_CLK_HOST 0x80
47#define TX4927_PCI_CLK_MASK (0x0f << 3)
48#define TX4927_PCI_CLK_33 (0x01 << 3)
49#define TX4927_PCI_CLK_25 (0x04 << 3)
50#define TX4927_PCI_CLK_66 (0x09 << 3)
51#define TX4927_PCI_CLK_50 (0x0c << 3)
52#define TX4927_PCI_CLK_ACK 0x04
53#define TX4927_PCI_CLK_ACE 0x02
54#define TX4927_PCI_CLK_ENDIAN 0x01
55#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
56#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
57
58#define TX4927_IR_PCIC 16
59#define TX4927_IR_PCIERR 22
60#define TX4927_IR_PCIPMA 23
61#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
62#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
63#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
64#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
65#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
66#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
67#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
68
69#ifdef _LANGUAGE_ASSEMBLY
70#define _CONST64(c) c
71#else
72#define _CONST64(c) c##ull
73
74#include <asm/byteorder.h>
75
76#define tx4927_pcireset_ptr \
77 ((volatile unsigned char *)TX4927_PCIRESET_ADDR)
78#define tx4927_pci_clk_ptr \
79 ((volatile unsigned char *)TX4927_PCI_CLK_ADDR)
80
81struct tx4927_sdramc_reg {
82 volatile unsigned long long cr[4];
83 volatile unsigned long long unused0[4];
84 volatile unsigned long long tr;
85 volatile unsigned long long unused1[2];
86 volatile unsigned long long cmd;
87};
88
89struct tx4927_ebusc_reg {
90 volatile unsigned long long cr[8];
91};
92
93struct tx4927_ccfg_reg {
94 volatile unsigned long long ccfg;
95 volatile unsigned long long crir;
96 volatile unsigned long long pcfg;
97 volatile unsigned long long tear;
98 volatile unsigned long long clkctr;
99 volatile unsigned long long unused0;
100 volatile unsigned long long garbc;
101 volatile unsigned long long unused1;
102 volatile unsigned long long unused2;
103 volatile unsigned long long ramp;
104};
105
106struct tx4927_pcic_reg {
107 volatile unsigned long pciid;
108 volatile unsigned long pcistatus;
109 volatile unsigned long pciccrev;
110 volatile unsigned long pcicfg1;
111 volatile unsigned long p2gm0plbase; /* +10 */
112 volatile unsigned long p2gm0pubase;
113 volatile unsigned long p2gm1plbase;
114 volatile unsigned long p2gm1pubase;
115 volatile unsigned long p2gm2pbase; /* +20 */
116 volatile unsigned long p2giopbase;
117 volatile unsigned long unused0;
118 volatile unsigned long pcisid;
119 volatile unsigned long unused1; /* +30 */
120 volatile unsigned long pcicapptr;
121 volatile unsigned long unused2;
122 volatile unsigned long pcicfg2;
123 volatile unsigned long g2ptocnt; /* +40 */
124 volatile unsigned long unused3[15];
125 volatile unsigned long g2pstatus; /* +80 */
126 volatile unsigned long g2pmask;
127 volatile unsigned long pcisstatus;
128 volatile unsigned long pcimask;
129 volatile unsigned long p2gcfg; /* +90 */
130 volatile unsigned long p2gstatus;
131 volatile unsigned long p2gmask;
132 volatile unsigned long p2gccmd;
133 volatile unsigned long unused4[24]; /* +a0 */
134 volatile unsigned long pbareqport; /* +100 */
135 volatile unsigned long pbacfg;
136 volatile unsigned long pbastatus;
137 volatile unsigned long pbamask;
138 volatile unsigned long pbabm; /* +110 */
139 volatile unsigned long pbacreq;
140 volatile unsigned long pbacgnt;
141 volatile unsigned long pbacstate;
142 volatile unsigned long long g2pmgbase[3]; /* +120 */
143 volatile unsigned long long g2piogbase;
144 volatile unsigned long g2pmmask[3]; /* +140 */
145 volatile unsigned long g2piomask;
146 volatile unsigned long long g2pmpbase[3]; /* +150 */
147 volatile unsigned long long g2piopbase;
148 volatile unsigned long pciccfg; /* +170 */
149 volatile unsigned long pcicstatus;
150 volatile unsigned long pcicmask;
151 volatile unsigned long unused5;
152 volatile unsigned long long p2gmgbase[3]; /* +180 */
153 volatile unsigned long long p2giogbase;
154 volatile unsigned long g2pcfgadrs; /* +1a0 */
155 volatile unsigned long g2pcfgdata;
156 volatile unsigned long unused6[8];
157 volatile unsigned long g2pintack;
158 volatile unsigned long g2pspc;
159 volatile unsigned long unused7[12]; /* +1d0 */
160 volatile unsigned long long pdmca; /* +200 */
161 volatile unsigned long long pdmga;
162 volatile unsigned long long pdmpa;
163 volatile unsigned long long pdmcut;
164 volatile unsigned long long pdmcnt; /* +220 */
165 volatile unsigned long long pdmsts;
166 volatile unsigned long long unused8[2];
167 volatile unsigned long long pdmdb[4]; /* +240 */
168 volatile unsigned long long pdmtdh; /* +260 */
169 volatile unsigned long long pdmdms;
170};
171
172#endif /* _LANGUAGE_ASSEMBLY */
173
174/*
175 * PCIC
176 */
177
178/* bits for G2PSTATUS/G2PMASK */
179#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
180#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
181#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
182
183/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
184#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
185
186/* bits for PBACFG */
187#define TX4927_PCIC_PBACFG_RPBA 0x00000004
188#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
189#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
190
191/* bits for G2PMnGBASE */
192#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
193#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
194
195/* bits for G2PIOGBASE */
196#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
197#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
198
199/* bits for PCICSTATUS/PCICMASK */
200#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
201
202/* bits for PCICCFG */
203#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
204#define TX4927_PCIC_PCICCFG_HRST 0x00000800
205#define TX4927_PCIC_PCICCFG_SRST 0x00000400
206#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
207#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
208#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
209#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
210#define TX4927_PCIC_PCICCFG_IISE 0x00000020
211#define TX4927_PCIC_PCICCFG_ATR 0x00000010
212#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
213
214/* bits for P2GMnGBASE */
215#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
216#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
217#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
218
219/* bits for P2GIOGBASE */
220#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
221#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
222#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
223
224#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
225#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
226
227/*
228 * CCFG
229 */
230/* CCFG : Chip Configuration */
231#define TX4927_CCFG_PCI66 0x00800000
232#define TX4927_CCFG_PCIMIDE 0x00400000
233#define TX4927_CCFG_PCIXARB 0x00002000
234#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
235#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
236#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
237#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
238#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
239
240#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
241#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
242#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
243#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
244#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
245#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
246#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
247#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
248#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
249
250/* PCFG : Pin Configuration */
251#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
252#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
253
254/* CLKCTR : Clock Control */
255#define TX4927_CLKCTR_PCICKD 0x00400000
256#define TX4927_CLKCTR_PCIRST 0x00000040
257
258
259#ifndef _LANGUAGE_ASSEMBLY
260
261#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
262#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
263#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
264#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
265
266#endif /* _LANGUAGE_ASSEMBLY */
267
268#endif /* __ASM_TX4927_TX4927_PCI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 07:44:57 -0500