diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
| commit | 49a89efbbbcc178a39555c43bd59a7593c429664 (patch) | |
| tree | 93ab78ec340d3f2fe23f9f853edd0bd62dcc64bb /include/asm-mips/mach-pb1x00 | |
| parent | 10cc3529072d5415fb040018a8a99aa7a60190b6 (diff) | |
[MIPS] Fix "no space between function name and open parenthesis" warnings.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-pb1x00')
| -rw-r--r-- | include/asm-mips/mach-pb1x00/pb1000.h | 56 | ||||
| -rw-r--r-- | include/asm-mips/mach-pb1x00/pb1100.h | 60 |
2 files changed, 58 insertions, 58 deletions
diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h index 50c1e413a688..b52e0e7ee3fb 100644 --- a/include/asm-mips/mach-pb1x00/pb1000.h +++ b/include/asm-mips/mach-pb1x00/pb1000.h | |||
| @@ -32,38 +32,38 @@ | |||
| 32 | #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) | 32 | #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) |
| 33 | 33 | ||
| 34 | #define PB1000_PCR 0xBE000000 | 34 | #define PB1000_PCR 0xBE000000 |
| 35 | #define PCR_SLOT_0_VPP0 (1<<0) | 35 | # define PCR_SLOT_0_VPP0 (1<<0) |
| 36 | #define PCR_SLOT_0_VPP1 (1<<1) | 36 | # define PCR_SLOT_0_VPP1 (1<<1) |
| 37 | #define PCR_SLOT_0_VCC0 (1<<2) | 37 | # define PCR_SLOT_0_VCC0 (1<<2) |
| 38 | #define PCR_SLOT_0_VCC1 (1<<3) | 38 | # define PCR_SLOT_0_VCC1 (1<<3) |
| 39 | #define PCR_SLOT_0_RST (1<<4) | 39 | # define PCR_SLOT_0_RST (1<<4) |
| 40 | 40 | ||
| 41 | #define PCR_SLOT_1_VPP0 (1<<8) | 41 | # define PCR_SLOT_1_VPP0 (1<<8) |
| 42 | #define PCR_SLOT_1_VPP1 (1<<9) | 42 | # define PCR_SLOT_1_VPP1 (1<<9) |
| 43 | #define PCR_SLOT_1_VCC0 (1<<10) | 43 | # define PCR_SLOT_1_VCC0 (1<<10) |
| 44 | #define PCR_SLOT_1_VCC1 (1<<11) | 44 | # define PCR_SLOT_1_VCC1 (1<<11) |
| 45 | #define PCR_SLOT_1_RST (1<<12) | 45 | # define PCR_SLOT_1_RST (1<<12) |
| 46 | 46 | ||
| 47 | #define PB1000_MDR 0xBE000004 | 47 | #define PB1000_MDR 0xBE000004 |
| 48 | #define MDR_PI (1<<5) /* pcmcia int latch */ | 48 | # define MDR_PI (1<<5) /* pcmcia int latch */ |
| 49 | #define MDR_EPI (1<<14) /* enable pcmcia int */ | 49 | # define MDR_EPI (1<<14) /* enable pcmcia int */ |
| 50 | #define MDR_CPI (1<<15) /* clear pcmcia int */ | 50 | # define MDR_CPI (1<<15) /* clear pcmcia int */ |
| 51 | 51 | ||
| 52 | #define PB1000_ACR1 0xBE000008 | 52 | #define PB1000_ACR1 0xBE000008 |
| 53 | #define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ | 53 | # define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ |
| 54 | #define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ | 54 | # define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ |
| 55 | #define ACR1_SLOT_0_READY (1<<2) /* ready */ | 55 | # define ACR1_SLOT_0_READY (1<<2) /* ready */ |
| 56 | #define ACR1_SLOT_0_STATUS (1<<3) /* status change */ | 56 | # define ACR1_SLOT_0_STATUS (1<<3) /* status change */ |
| 57 | #define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ | 57 | # define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ |
| 58 | #define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ | 58 | # define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ |
| 59 | #define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ | 59 | # define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ |
| 60 | #define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ | 60 | # define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ |
| 61 | #define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ | 61 | # define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ |
| 62 | #define ACR1_SLOT_1_READY (1<<10) /* ready */ | 62 | # define ACR1_SLOT_1_READY (1<<10) /* ready */ |
| 63 | #define ACR1_SLOT_1_STATUS (1<<11) /* status change */ | 63 | # define ACR1_SLOT_1_STATUS (1<<11) /* status change */ |
| 64 | #define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ | 64 | # define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ |
| 65 | #define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ | 65 | # define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ |
| 66 | #define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ | 66 | # define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ |
| 67 | 67 | ||
| 68 | #define CPLD_AUX0 0xBE00000C | 68 | #define CPLD_AUX0 0xBE00000C |
| 69 | #define CPLD_AUX1 0xBE000010 | 69 | #define CPLD_AUX1 0xBE000010 |
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h index 4c5a1cd01841..63aa3926b297 100644 --- a/include/asm-mips/mach-pb1x00/pb1100.h +++ b/include/asm-mips/mach-pb1x00/pb1100.h | |||
| @@ -29,44 +29,44 @@ | |||
| 29 | 29 | ||
| 30 | #define PB1100_IDENT 0xAE000000 | 30 | #define PB1100_IDENT 0xAE000000 |
| 31 | #define BOARD_STATUS_REG 0xAE000004 | 31 | #define BOARD_STATUS_REG 0xAE000004 |
| 32 | #define PB1100_ROM_SEL (1<<15) | 32 | # define PB1100_ROM_SEL (1<<15) |
| 33 | #define PB1100_ROM_SIZ (1<<14) | 33 | # define PB1100_ROM_SIZ (1<<14) |
| 34 | #define PB1100_SWAP_BOOT (1<<13) | 34 | # define PB1100_SWAP_BOOT (1<<13) |
| 35 | #define PB1100_FLASH_WP (1<<12) | 35 | # define PB1100_FLASH_WP (1<<12) |
| 36 | #define PB1100_ROM_H_STS (1<<11) | 36 | # define PB1100_ROM_H_STS (1<<11) |
| 37 | #define PB1100_ROM_L_STS (1<<10) | 37 | # define PB1100_ROM_L_STS (1<<10) |
| 38 | #define PB1100_FLASH_H_STS (1<<9) | 38 | # define PB1100_FLASH_H_STS (1<<9) |
| 39 | #define PB1100_FLASH_L_STS (1<<8) | 39 | # define PB1100_FLASH_L_STS (1<<8) |
| 40 | #define PB1100_SRAM_SIZ (1<<7) | 40 | # define PB1100_SRAM_SIZ (1<<7) |
| 41 | #define PB1100_TSC_BUSY (1<<6) | 41 | # define PB1100_TSC_BUSY (1<<6) |
| 42 | #define PB1100_PCMCIA_VS_MASK (3<<4) | 42 | # define PB1100_PCMCIA_VS_MASK (3<<4) |
| 43 | #define PB1100_RS232_CD (1<<3) | 43 | # define PB1100_RS232_CD (1<<3) |
| 44 | #define PB1100_RS232_CTS (1<<2) | 44 | # define PB1100_RS232_CTS (1<<2) |
| 45 | #define PB1100_RS232_DSR (1<<1) | 45 | # define PB1100_RS232_DSR (1<<1) |
| 46 | #define PB1100_RS232_RI (1<<0) | 46 | # define PB1100_RS232_RI (1<<0) |
| 47 | 47 | ||
| 48 | #define PB1100_IRDA_RS232 0xAE00000C | 48 | #define PB1100_IRDA_RS232 0xAE00000C |
| 49 | #define PB1100_IRDA_FULL (0<<14) /* full power */ | 49 | # define PB1100_IRDA_FULL (0<<14) /* full power */ |
| 50 | #define PB1100_IRDA_SHUTDOWN (1<<14) | 50 | # define PB1100_IRDA_SHUTDOWN (1<<14) |
| 51 | #define PB1100_IRDA_TT (2<<14) /* 2/3 power */ | 51 | # define PB1100_IRDA_TT (2<<14) /* 2/3 power */ |
| 52 | #define PB1100_IRDA_OT (3<<14) /* 1/3 power */ | 52 | # define PB1100_IRDA_OT (3<<14) /* 1/3 power */ |
| 53 | #define PB1100_IRDA_FIR (1<<13) | 53 | # define PB1100_IRDA_FIR (1<<13) |
| 54 | 54 | ||
| 55 | #define PCMCIA_BOARD_REG 0xAE000010 | 55 | #define PCMCIA_BOARD_REG 0xAE000010 |
| 56 | #define PB1100_SD_WP1_RO (1<<15) /* read only */ | 56 | # define PB1100_SD_WP1_RO (1<<15) /* read only */ |
| 57 | #define PB1100_SD_WP0_RO (1<<14) /* read only */ | 57 | # define PB1100_SD_WP0_RO (1<<14) /* read only */ |
| 58 | #define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ | 58 | # define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ |
| 59 | #define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ | 59 | # define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ |
| 60 | #define PB1100_SEL_SD_CONN1 (1<<9) | 60 | # define PB1100_SEL_SD_CONN1 (1<<9) |
| 61 | #define PB1100_SEL_SD_CONN0 (1<<8) | 61 | # define PB1100_SEL_SD_CONN0 (1<<8) |
| 62 | #define PC_DEASSERT_RST (1<<7) | 62 | # define PC_DEASSERT_RST (1<<7) |
| 63 | #define PC_DRV_EN (1<<4) | 63 | # define PC_DRV_EN (1<<4) |
| 64 | 64 | ||
| 65 | #define PB1100_G_CONTROL 0xAE000014 /* graphics control */ | 65 | #define PB1100_G_CONTROL 0xAE000014 /* graphics control */ |
| 66 | 66 | ||
| 67 | #define PB1100_RST_VDDI 0xAE00001C | 67 | #define PB1100_RST_VDDI 0xAE00001C |
| 68 | #define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ | 68 | # define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ |
| 69 | #define PB1100_VDDI_MASK (0x1F) | 69 | # define PB1100_VDDI_MASK (0x1F) |
| 70 | 70 | ||
| 71 | #define PB1100_LEDS 0xAE000018 | 71 | #define PB1100_LEDS 0xAE000018 |
| 72 | 72 | ||