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authorGraf Yang <graf.yang@analog.com>2008-04-24 15:09:15 -0400
committerBryan Wu <cooloney@kernel.org>2008-04-24 15:09:15 -0400
commit5be36d22b28f01e5074f78b29aa6128da0a53641 (patch)
tree1fda8bcb0680eda6a826fc3753ee8c9f52a2c75b /include/asm-blackfin
parent37b6972ad8fb08d438fd600888aff212b1b193b0 (diff)
[Blackfin] arch: add Blackfin on-chip SIR IrDA driver support
- add platform device resources in board files - add new bfin_sir.h to each machines Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin')
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_serial_5xx.h48
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_sir.h133
-rw-r--r--include/asm-blackfin/mach-bf527/blackfin.h15
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_serial_5xx.h50
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_sir.h120
-rw-r--r--include/asm-blackfin/mach-bf533/blackfin.h15
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_serial_5xx.h48
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_sir.h133
-rw-r--r--include/asm-blackfin/mach-bf537/blackfin.h15
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h48
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_sir.h149
-rw-r--r--include/asm-blackfin/mach-bf548/blackfin.h15
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_serial_5xx.h50
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_sir.h120
-rw-r--r--include/asm-blackfin/mach-bf561/blackfin.h14
15 files changed, 891 insertions, 82 deletions
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index c0694ecd2ecd..f0ab2736a680 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
1#include <linux/serial.h> 32#include <linux/serial.h>
2#include <asm/dma.h> 33#include <asm/dma.h>
3#include <asm/portmux.h> 34#include <asm/portmux.h>
4 35
5#define NR_PORTS 2
6
7#define OFFSET_THR 0x00 /* Transmit Holding register */
8#define OFFSET_RBR 0x00 /* Receive Buffer register */
9#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
10#define OFFSET_IER 0x04 /* Interrupt Enable Register */
11#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
12#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
13#define OFFSET_LCR 0x0C /* Line Control Register */
14#define OFFSET_MCR 0x10 /* Modem Control Register */
15#define OFFSET_LSR 0x14 /* Line Status Register */
16#define OFFSET_MSR 0x18 /* Modem Status Register */
17#define OFFSET_SCR 0x1C /* SCR Scratch Register */
18#define OFFSET_GCTL 0x24 /* Global Control Register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) 38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -92,7 +108,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
92 bfin_write16(uart->port.membase + OFFSET_LSR, -1); 108 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
93} 109}
94 110
95struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 111struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
96struct bfin_serial_res { 112struct bfin_serial_res {
97 unsigned long uart_base_addr; 113 unsigned long uart_base_addr;
98 int uart_irq; 114 int uart_irq;
diff --git a/include/asm-blackfin/mach-bf527/bfin_sir.h b/include/asm-blackfin/mach-bf527/bfin_sir.h
new file mode 100644
index 000000000000..0612d0c9501c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/bfin_sir.h
@@ -0,0 +1,133 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART0_RX,
69 CH_UART0_RX,
70 CH_UART0_TX,
71 },
72#endif
73#ifdef CONFIG_BFIN_SIR1
74 {
75 0xFFC02000,
76 IRQ_UART1_RX,
77 CH_UART1_RX,
78 CH_UART1_TX,
79 },
80#endif
81};
82
83int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
84
85struct bfin_sir_self {
86 struct bfin_sir_port *sir_port;
87 spinlock_t lock;
88 unsigned int open;
89 int speed;
90 int newspeed;
91
92 struct sk_buff *txskb;
93 struct sk_buff *rxskb;
94 struct net_device_stats stats;
95 struct device *dev;
96 struct irlap_cb *irlap;
97 struct qos_info qos;
98
99 iobuff_t tx_buff;
100 iobuff_t rx_buff;
101
102 struct work_struct work;
103 int mtt;
104};
105
106static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
107{
108 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
109 port->lsr |= (lsr & (BI|FE|PE|OE));
110 return lsr | port->lsr;
111}
112
113static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
114{
115 port->lsr = 0;
116 bfin_read16(port->membase + OFFSET_LSR);
117}
118
119#define DRIVER_NAME "bfin_sir"
120
121static void bfin_sir_hw_init(void)
122{
123#ifdef CONFIG_BFIN_SIR0
124 peripheral_request(P_UART0_TX, DRIVER_NAME);
125 peripheral_request(P_UART0_RX, DRIVER_NAME);
126#endif
127
128#ifdef CONFIG_BFIN_SIR1
129 peripheral_request(P_UART1_TX, DRIVER_NAME);
130 peripheral_request(P_UART1_RX, DRIVER_NAME);
131#endif
132 SSYNC();
133}
diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h
index 1bd07e30781c..2891727b6176 100644
--- a/include/asm-blackfin/mach-bf527/blackfin.h
+++ b/include/asm-blackfin/mach-bf527/blackfin.h
@@ -64,6 +64,21 @@
64#define STATUS_P1 0x02 64#define STATUS_P1 0x02
65#define STATUS_P0 0x01 65#define STATUS_P0 0x01
66 66
67#define BFIN_UART_NR_PORTS 2
68
69#define OFFSET_THR 0x00 /* Transmit Holding register */
70#define OFFSET_RBR 0x00 /* Receive Buffer register */
71#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
72#define OFFSET_IER 0x04 /* Interrupt Enable Register */
73#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
74#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
75#define OFFSET_LCR 0x0C /* Line Control Register */
76#define OFFSET_MCR 0x10 /* Modem Control Register */
77#define OFFSET_LSR 0x14 /* Line Status Register */
78#define OFFSET_MSR 0x18 /* Modem Status Register */
79#define OFFSET_SCR 0x1C /* SCR Scratch Register */
80#define OFFSET_GCTL 0x24 /* Global Control Register */
81
67/* DPMC*/ 82/* DPMC*/
68#define bfin_read_STOPCK_OFF() bfin_read_STOPCK() 83#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
69#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) 84#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index b6f513bee56e..fbe88dee3e2d 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
1/*
2 * file: include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
1#include <linux/serial.h> 32#include <linux/serial.h>
2#include <asm/dma.h> 33#include <asm/dma.h>
3#include <asm/portmux.h> 34#include <asm/portmux.h>
4 35
5#define NR_PORTS 1
6
7#define OFFSET_THR 0x00 /* Transmit Holding register */
8#define OFFSET_RBR 0x00 /* Receive Buffer register */
9#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
10#define OFFSET_IER 0x04 /* Interrupt Enable Register */
11#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
12#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
13#define OFFSET_LCR 0x0C /* Line Control Register */
14#define OFFSET_MCR 0x10 /* Modem Control Register */
15#define OFFSET_LSR 0x14 /* Line Status Register */
16#define OFFSET_MSR 0x18 /* Modem Status Register */
17#define OFFSET_SCR 0x1C /* SCR Scratch Register */
18#define OFFSET_GCTL 0x24 /* Global Control Register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) 38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -84,7 +100,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
84 bfin_write16(uart->port.membase + OFFSET_LSR, -1); 100 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
85} 101}
86 102
87struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 103struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
88struct bfin_serial_res { 104struct bfin_serial_res {
89 unsigned long uart_base_addr; 105 unsigned long uart_base_addr;
90 int uart_irq; 106 int uart_irq;
@@ -115,7 +131,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
115 131
116#define DRIVER_NAME "bfin-uart" 132#define DRIVER_NAME "bfin-uart"
117 133
118int nr_ports = NR_PORTS; 134int nr_ports = BFIN_UART_NR_PORTS;
119static void bfin_serial_hw_init(struct bfin_serial_port *uart) 135static void bfin_serial_hw_init(struct bfin_serial_port *uart)
120{ 136{
121 137
diff --git a/include/asm-blackfin/mach-bf533/bfin_sir.h b/include/asm-blackfin/mach-bf533/bfin_sir.h
new file mode 100644
index 000000000000..cefcf8bb505b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/bfin_sir.h
@@ -0,0 +1,120 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART_RX,
69 CH_UART_RX,
70 CH_UART_TX,
71 },
72#endif
73};
74
75int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
76
77struct bfin_sir_self {
78 struct bfin_sir_port *sir_port;
79 spinlock_t lock;
80 unsigned int open;
81 int speed;
82 int newspeed;
83
84 struct sk_buff *txskb;
85 struct sk_buff *rxskb;
86 struct net_device_stats stats;
87 struct device *dev;
88 struct irlap_cb *irlap;
89 struct qos_info qos;
90
91 iobuff_t tx_buff;
92 iobuff_t rx_buff;
93
94 struct work_struct work;
95 int mtt;
96};
97
98static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
99{
100 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
101 port->lsr |= (lsr & (BI|FE|PE|OE));
102 return lsr | port->lsr;
103}
104
105static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
106{
107 port->lsr = 0;
108 bfin_read16(port->membase + OFFSET_LSR);
109}
110
111#define DRIVER_NAME "bfin_sir"
112
113static void bfin_sir_hw_init(void)
114{
115#ifdef CONFIG_BFIN_SIR0
116 peripheral_request(P_UART0_TX, DRIVER_NAME);
117 peripheral_request(P_UART0_RX, DRIVER_NAME);
118#endif
119 SSYNC();
120}
diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h
index f3b240abf170..d80971b4e3aa 100644
--- a/include/asm-blackfin/mach-bf533/blackfin.h
+++ b/include/asm-blackfin/mach-bf533/blackfin.h
@@ -42,4 +42,19 @@
42#include "cdefBF532.h" 42#include "cdefBF532.h"
43#endif 43#endif
44 44
45#define BFIN_UART_NR_PORTS 1
46
47#define OFFSET_THR 0x00 /* Transmit Holding register */
48#define OFFSET_RBR 0x00 /* Receive Buffer register */
49#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
50#define OFFSET_IER 0x04 /* Interrupt Enable Register */
51#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
52#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
53#define OFFSET_LCR 0x0C /* Line Control Register */
54#define OFFSET_MCR 0x10 /* Modem Control Register */
55#define OFFSET_LSR 0x14 /* Line Status Register */
56#define OFFSET_MSR 0x18 /* Modem Status Register */
57#define OFFSET_SCR 0x1C /* SCR Scratch Register */
58#define OFFSET_GCTL 0x24 /* Global Control Register */
59
45#endif /* _MACH_BLACKFIN_H_ */ 60#endif /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index 8fc672d31057..fd100a415b98 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver header files
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
1#include <linux/serial.h> 32#include <linux/serial.h>
2#include <asm/dma.h> 33#include <asm/dma.h>
3#include <asm/portmux.h> 34#include <asm/portmux.h>
4 35
5#define NR_PORTS 2
6
7#define OFFSET_THR 0x00 /* Transmit Holding register */
8#define OFFSET_RBR 0x00 /* Receive Buffer register */
9#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
10#define OFFSET_IER 0x04 /* Interrupt Enable Register */
11#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
12#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
13#define OFFSET_LCR 0x0C /* Line Control Register */
14#define OFFSET_MCR 0x10 /* Modem Control Register */
15#define OFFSET_LSR 0x14 /* Line Status Register */
16#define OFFSET_MSR 0x18 /* Modem Status Register */
17#define OFFSET_SCR 0x1C /* SCR Scratch Register */
18#define OFFSET_GCTL 0x24 /* Global Control Register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) 38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -92,7 +108,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
92 bfin_write16(uart->port.membase + OFFSET_LSR, -1); 108 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
93} 109}
94 110
95struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 111struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
96struct bfin_serial_res { 112struct bfin_serial_res {
97 unsigned long uart_base_addr; 113 unsigned long uart_base_addr;
98 int uart_irq; 114 int uart_irq;
diff --git a/include/asm-blackfin/mach-bf537/bfin_sir.h b/include/asm-blackfin/mach-bf537/bfin_sir.h
new file mode 100644
index 000000000000..0612d0c9501c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/bfin_sir.h
@@ -0,0 +1,133 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART0_RX,
69 CH_UART0_RX,
70 CH_UART0_TX,
71 },
72#endif
73#ifdef CONFIG_BFIN_SIR1
74 {
75 0xFFC02000,
76 IRQ_UART1_RX,
77 CH_UART1_RX,
78 CH_UART1_TX,
79 },
80#endif
81};
82
83int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
84
85struct bfin_sir_self {
86 struct bfin_sir_port *sir_port;
87 spinlock_t lock;
88 unsigned int open;
89 int speed;
90 int newspeed;
91
92 struct sk_buff *txskb;
93 struct sk_buff *rxskb;
94 struct net_device_stats stats;
95 struct device *dev;
96 struct irlap_cb *irlap;
97 struct qos_info qos;
98
99 iobuff_t tx_buff;
100 iobuff_t rx_buff;
101
102 struct work_struct work;
103 int mtt;
104};
105
106static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
107{
108 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
109 port->lsr |= (lsr & (BI|FE|PE|OE));
110 return lsr | port->lsr;
111}
112
113static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
114{
115 port->lsr = 0;
116 bfin_read16(port->membase + OFFSET_LSR);
117}
118
119#define DRIVER_NAME "bfin_sir"
120
121static void bfin_sir_hw_init(void)
122{
123#ifdef CONFIG_BFIN_SIR0
124 peripheral_request(P_UART0_TX, DRIVER_NAME);
125 peripheral_request(P_UART0_RX, DRIVER_NAME);
126#endif
127
128#ifdef CONFIG_BFIN_SIR1
129 peripheral_request(P_UART1_TX, DRIVER_NAME);
130 peripheral_request(P_UART1_RX, DRIVER_NAME);
131#endif
132 SSYNC();
133}
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h
index 4f10ee0ae10d..cffc786b2a2b 100644
--- a/include/asm-blackfin/mach-bf537/blackfin.h
+++ b/include/asm-blackfin/mach-bf537/blackfin.h
@@ -136,6 +136,21 @@
136#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) 136#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
137#define BFIN_UART_GCTL UART0_GCTL 137#define BFIN_UART_GCTL UART0_GCTL
138 138
139#define BFIN_UART_NR_PORTS 2
140
141#define OFFSET_THR 0x00 /* Transmit Holding register */
142#define OFFSET_RBR 0x00 /* Receive Buffer register */
143#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
144#define OFFSET_IER 0x04 /* Interrupt Enable Register */
145#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
146#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
147#define OFFSET_LCR 0x0C /* Line Control Register */
148#define OFFSET_MCR 0x10 /* Modem Control Register */
149#define OFFSET_LSR 0x14 /* Line Status Register */
150#define OFFSET_MSR 0x18 /* Modem Status Register */
151#define OFFSET_SCR 0x1C /* SCR Scratch Register */
152#define OFFSET_GCTL 0x24 /* Global Control Register */
153
139/* DPMC*/ 154/* DPMC*/
140#define bfin_read_STOPCK_OFF() bfin_read_STOPCK() 155#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
141#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) 156#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index 7e6339f62a50..6547027cd3e6 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
1#include <linux/serial.h> 32#include <linux/serial.h>
2#include <asm/dma.h> 33#include <asm/dma.h>
3#include <asm/portmux.h> 34#include <asm/portmux.h>
4 35
5#define NR_PORTS 4
6
7#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
8#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
9#define OFFSET_GCTL 0x08 /* Global Control Register */
10#define OFFSET_LCR 0x0C /* Line Control Register */
11#define OFFSET_MCR 0x10 /* Modem Control Register */
12#define OFFSET_LSR 0x14 /* Line Status Register */
13#define OFFSET_MSR 0x18 /* Modem Status Register */
14#define OFFSET_SCR 0x1C /* SCR Scratch Register */
15#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
16#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
17#define OFFSET_THR 0x28 /* Transmit Holding register */
18#define OFFSET_RBR 0x2C /* Receive Buffer register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) 38#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
@@ -80,7 +96,7 @@ struct bfin_serial_port {
80#endif 96#endif
81}; 97};
82 98
83struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 99struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
84struct bfin_serial_res { 100struct bfin_serial_res {
85 unsigned long uart_base_addr; 101 unsigned long uart_base_addr;
86 int uart_irq; 102 int uart_irq;
diff --git a/include/asm-blackfin/mach-bf548/bfin_sir.h b/include/asm-blackfin/mach-bf548/bfin_sir.h
new file mode 100644
index 000000000000..5e94271c7e3b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/bfin_sir.h
@@ -0,0 +1,149 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
21#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
27#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
28#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
29#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
30#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
31#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
32#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
33
34#ifdef CONFIG_SIR_BFIN_DMA
35struct dma_rx_buf {
36 char *buf;
37 int head;
38 int tail;
39 };
40#endif /* CONFIG_SIR_BFIN_DMA */
41
42struct bfin_sir_port {
43 unsigned char __iomem *membase;
44 unsigned int irq;
45 unsigned int lsr;
46 unsigned long clk;
47 struct net_device *dev;
48#ifdef CONFIG_SIR_BFIN_DMA
49 int tx_done;
50 struct dma_rx_buf rx_dma_buf;
51 struct timer_list rx_dma_timer;
52 int rx_dma_nrows;
53#endif /* CONFIG_SIR_BFIN_DMA */
54 unsigned int tx_dma_channel;
55 unsigned int rx_dma_channel;
56};
57
58struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
59
60struct bfin_sir_port_res {
61 unsigned long base_addr;
62 int irq;
63 unsigned int rx_dma_channel;
64 unsigned int tx_dma_channel;
65};
66
67struct bfin_sir_port_res bfin_sir_port_resource[] = {
68#ifdef CONFIG_BFIN_SIR0
69 {
70 0xFFC00400,
71 IRQ_UART0_RX,
72 CH_UART0_RX,
73 CH_UART0_TX,
74 },
75#endif
76#ifdef CONFIG_BFIN_SIR1
77 {
78 0xFFC02000,
79 IRQ_UART1_RX,
80 CH_UART1_RX,
81 CH_UART1_TX,
82 },
83#endif
84#ifdef CONFIG_BFIN_SIR2
85 {
86 0xFFC02100,
87 IRQ_UART2_RX,
88 CH_UART2_RX,
89 CH_UART2_TX,
90 },
91#endif
92#ifdef CONFIG_BFIN_SIR3
93 {
94 0xFFC03100,
95 IRQ_UART3_RX,
96 CH_UART3_RX,
97 CH_UART3_TX,
98 },
99#endif
100};
101
102int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
103
104struct bfin_sir_self {
105 struct bfin_sir_port *sir_port;
106 spinlock_t lock;
107 unsigned int open;
108 int speed;
109 int newspeed;
110
111 struct sk_buff *txskb;
112 struct sk_buff *rxskb;
113 struct net_device_stats stats;
114 struct device *dev;
115 struct irlap_cb *irlap;
116 struct qos_info qos;
117
118 iobuff_t tx_buff;
119 iobuff_t rx_buff;
120
121 struct work_struct work;
122 int mtt;
123};
124
125#define DRIVER_NAME "bfin_sir"
126
127static void bfin_sir_hw_init(void)
128{
129#ifdef CONFIG_BFIN_SIR0
130 peripheral_request(P_UART0_TX, DRIVER_NAME);
131 peripheral_request(P_UART0_RX, DRIVER_NAME);
132#endif
133
134#ifdef CONFIG_BFIN_SIR1
135 peripheral_request(P_UART1_TX, DRIVER_NAME);
136 peripheral_request(P_UART1_RX, DRIVER_NAME);
137#endif
138
139#ifdef CONFIG_BFIN_SIR2
140 peripheral_request(P_UART2_TX, DRIVER_NAME);
141 peripheral_request(P_UART2_RX, DRIVER_NAME);
142#endif
143
144#ifdef CONFIG_BFIN_SIR3
145 peripheral_request(P_UART3_TX, DRIVER_NAME);
146 peripheral_request(P_UART3_RX, DRIVER_NAME);
147#endif
148 SSYNC();
149}
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
index b8509c16ecd4..d6ee74ac0460 100644
--- a/include/asm-blackfin/mach-bf548/blackfin.h
+++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -166,6 +166,21 @@
166#define BFIN_UART_SCR UART1_SCR 166#define BFIN_UART_SCR UART1_SCR
167#define BFIN_UART_GCTL UART1_GCTL 167#define BFIN_UART_GCTL UART1_GCTL
168 168
169#define BFIN_UART_NR_PORTS 4
170
171#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
172#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
173#define OFFSET_GCTL 0x08 /* Global Control Register */
174#define OFFSET_LCR 0x0C /* Line Control Register */
175#define OFFSET_MCR 0x10 /* Modem Control Register */
176#define OFFSET_LSR 0x14 /* Line Status Register */
177#define OFFSET_MSR 0x18 /* Modem Status Register */
178#define OFFSET_SCR 0x1C /* SCR Scratch Register */
179#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
180#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
181#define OFFSET_THR 0x28 /* Transmit Holding register */
182#define OFFSET_RBR 0x2C /* Receive Buffer register */
183
169/* PLL_DIV Masks */ 184/* PLL_DIV Masks */
170#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ 185#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
171#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ 186#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index b6f513bee56e..8a4e66d1db37 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
1/*
2 * file: include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
1#include <linux/serial.h> 32#include <linux/serial.h>
2#include <asm/dma.h> 33#include <asm/dma.h>
3#include <asm/portmux.h> 34#include <asm/portmux.h>
4 35
5#define NR_PORTS 1
6
7#define OFFSET_THR 0x00 /* Transmit Holding register */
8#define OFFSET_RBR 0x00 /* Receive Buffer register */
9#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
10#define OFFSET_IER 0x04 /* Interrupt Enable Register */
11#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
12#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
13#define OFFSET_LCR 0x0C /* Line Control Register */
14#define OFFSET_MCR 0x10 /* Modem Control Register */
15#define OFFSET_LSR 0x14 /* Line Status Register */
16#define OFFSET_MSR 0x18 /* Modem Status Register */
17#define OFFSET_SCR 0x1C /* SCR Scratch Register */
18#define OFFSET_GCTL 0x24 /* Global Control Register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) 38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -84,7 +100,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
84 bfin_write16(uart->port.membase + OFFSET_LSR, -1); 100 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
85} 101}
86 102
87struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 103struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
88struct bfin_serial_res { 104struct bfin_serial_res {
89 unsigned long uart_base_addr; 105 unsigned long uart_base_addr;
90 int uart_irq; 106 int uart_irq;
@@ -115,7 +131,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
115 131
116#define DRIVER_NAME "bfin-uart" 132#define DRIVER_NAME "bfin-uart"
117 133
118int nr_ports = NR_PORTS; 134int nr_ports = BFIN_UART_NR_PORTS;
119static void bfin_serial_hw_init(struct bfin_serial_port *uart) 135static void bfin_serial_hw_init(struct bfin_serial_port *uart)
120{ 136{
121 137
diff --git a/include/asm-blackfin/mach-bf561/bfin_sir.h b/include/asm-blackfin/mach-bf561/bfin_sir.h
new file mode 100644
index 000000000000..cefcf8bb505b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/bfin_sir.h
@@ -0,0 +1,120 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART_RX,
69 CH_UART_RX,
70 CH_UART_TX,
71 },
72#endif
73};
74
75int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
76
77struct bfin_sir_self {
78 struct bfin_sir_port *sir_port;
79 spinlock_t lock;
80 unsigned int open;
81 int speed;
82 int newspeed;
83
84 struct sk_buff *txskb;
85 struct sk_buff *rxskb;
86 struct net_device_stats stats;
87 struct device *dev;
88 struct irlap_cb *irlap;
89 struct qos_info qos;
90
91 iobuff_t tx_buff;
92 iobuff_t rx_buff;
93
94 struct work_struct work;
95 int mtt;
96};
97
98static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
99{
100 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
101 port->lsr |= (lsr & (BI|FE|PE|OE));
102 return lsr | port->lsr;
103}
104
105static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
106{
107 port->lsr = 0;
108 bfin_read16(port->membase + OFFSET_LSR);
109}
110
111#define DRIVER_NAME "bfin_sir"
112
113static void bfin_sir_hw_init(void)
114{
115#ifdef CONFIG_BFIN_SIR0
116 peripheral_request(P_UART0_TX, DRIVER_NAME);
117 peripheral_request(P_UART0_RX, DRIVER_NAME);
118#endif
119 SSYNC();
120}
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
index 3a16df2c86d8..0ea8666e6764 100644
--- a/include/asm-blackfin/mach-bf561/blackfin.h
+++ b/include/asm-blackfin/mach-bf561/blackfin.h
@@ -69,5 +69,19 @@
69#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) 69#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
70#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) 70#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
71 71
72#define BFIN_UART_NR_PORTS 1
73
74#define OFFSET_THR 0x00 /* Transmit Holding register */
75#define OFFSET_RBR 0x00 /* Receive Buffer register */
76#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
77#define OFFSET_IER 0x04 /* Interrupt Enable Register */
78#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
79#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
80#define OFFSET_LCR 0x0C /* Line Control Register */
81#define OFFSET_MCR 0x10 /* Modem Control Register */
82#define OFFSET_LSR 0x14 /* Line Status Register */
83#define OFFSET_MSR 0x18 /* Modem Status Register */
84#define OFFSET_SCR 0x1C /* SCR Scratch Register */
85#define OFFSET_GCTL 0x24 /* Global Control Register */
72 86
73#endif /* _MACH_BLACKFIN_H_ */ 87#endif /* _MACH_BLACKFIN_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 08:17:00 -0400