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authorAndrew Victor <andrew@sanpeople.com>2007-02-08 03:00:39 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-08 09:55:22 -0500
commitd0760b3bc8ff9b34e3e2e166e2102548a24751b4 (patch)
tree1ff9a9acf479b75e2d8dc23f1b894e5ac12c8d1d /include/asm-arm/arch-at91/entry-macro.S
parent9d0412680e6c7b685ee466842047bcfb924d6dc5 (diff)
[ARM] 4143/1: AT91: Prepare for AT91SAM9263 support
The Atmel AT91SAM9263 processor includes many more integrated peripherals than Atmel's previous ARM9-based AT91 processors, so this has necessitated a few changes to the core AT91 support. These changes are: * The system peripheral I/O region we remap has increased from 0xFFFA0000..0xFFFFFFFF to 0xFFF78000..0xFFFFFFFF. * The increased I/O region forces changes to entry-macro.S and debug-macro.S due to ARM's limited immediate offset addressing modes. * Maximum number of GPIO banks increases to 5. * 2 MMC controllers so the board-setup code needs to specify which controller it wishes to use when calling at91_add_device_mmc(). Original patch from Nicolas Ferre. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-at91/entry-macro.S')
-rw-r--r--include/asm-arm/arch-at91/entry-macro.S10
1 files changed, 5 insertions, 5 deletions
diff --git a/include/asm-arm/arch-at91/entry-macro.S b/include/asm-arm/arch-at91/entry-macro.S
index a6f33832a178..76c8cccf73aa 100644
--- a/include/asm-arm/arch-at91/entry-macro.S
+++ b/include/asm-arm/arch-at91/entry-macro.S
@@ -17,10 +17,10 @@
17 .endm 17 .endm
18 18
19 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 19 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
20 ldr \base, =(AT91_VA_BASE_SYS) @ base virtual address of SYS peripherals 20 ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
21 ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) 21 ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
22 ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number 22 ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number
23 teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt 23 teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
24 streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now. 24 streq \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)] @ not going to be handled further, then ACK it now.
25 .endm 25 .endm
26 26