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authorMike Turquette <mturquette@linaro.org>2014-07-31 12:32:18 -0400
committerMike Turquette <mturquette@linaro.org>2014-07-31 12:32:18 -0400
commitd7d3d26fa5446fc74e2c52504d827bda89b7b03e (patch)
tree209f3a0fe71af5a97ece45cee40c7e1a4f5495f3 /drivers
parentabeab450bfe823079c8a3abf5123f41a0da62392 (diff)
parentf65d518942325d4bfa74b5c9d42ea5a89e4f6943 (diff)
Merge tag 'for_3.17/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung
Samsung clock patches for 3.17 1) non-critical fixes (without need to push to stable): d5e136a clk: samsung: Register clk provider only after registering its all clocks 305cfab clk: samsung: Make of_device_id array const e9d5295 clk: samsung: exynos5420: Setup clocks before system suspend f65d518 clk: samsung: trivial: Correct typo in author's name 2) Exynos CLKOUT driver: 800c979 clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy 01f7ec2 clk: samsung: exynos4: Add CLKOUT clock hierarchy 1e832e5 clk: samsung: Add driver to control CLKOUT line on Exynos SoCs d19bb39 ARM: dts: exynos: Update PMU node with CLKOUT related data 3) Clock hierarchy extensions: 17d3f1d clk: exynos4: Add PPMU IP block source clocks. ca5b402 clk: samsung: register exynos5420 apll/kpll configuration data 4) ARM CLKDOWN functionality enablement for Exynos4 and 3250: 42773b2 clk: samsung: exynos4: Enable ARMCLK down feature 45c5b0a clk: samsung: exynos3250: Enable ARMCLK down feature
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/samsung/Makefile1
-rw-r--r--drivers/clk/samsung/clk-exynos-clkout.c153
-rw-r--r--drivers/clk/samsung/clk-exynos3250.c43
-rw-r--r--drivers/clk/samsung/clk-exynos4.c231
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c4
-rw-r--r--drivers/clk/samsung/clk-exynos5260.c2
-rw-r--r--drivers/clk/samsung/clk-exynos5410.c2
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c61
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c4
-rw-r--r--drivers/clk/samsung/clk-s3c2410.c2
-rw-r--r--drivers/clk/samsung/clk-s3c2412.c2
-rw-r--r--drivers/clk/samsung/clk-s3c2443.c2
-rw-r--r--drivers/clk/samsung/clk-s3c64xx.c2
-rw-r--r--drivers/clk/samsung/clk.c21
-rw-r--r--drivers/clk/samsung/clk.h4
15 files changed, 519 insertions, 15 deletions
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 69e81773164e..2949a556af8f 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
11obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o 11obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
12obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o 12obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
13obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o 13obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
14obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
14obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o 15obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
15obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o 16obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
16obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o 17obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c
new file mode 100644
index 000000000000..3a7cb2506731
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-clkout.c
@@ -0,0 +1,153 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Tomasz Figa <t.figa@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Clock driver for Exynos clock output
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/syscore_ops.h>
18
19#define EXYNOS_CLKOUT_NR_CLKS 1
20#define EXYNOS_CLKOUT_PARENTS 32
21
22#define EXYNOS_PMU_DEBUG_REG 0xa00
23#define EXYNOS_CLKOUT_DISABLE_SHIFT 0
24#define EXYNOS_CLKOUT_MUX_SHIFT 8
25#define EXYNOS4_CLKOUT_MUX_MASK 0xf
26#define EXYNOS5_CLKOUT_MUX_MASK 0x1f
27
28struct exynos_clkout {
29 struct clk_gate gate;
30 struct clk_mux mux;
31 spinlock_t slock;
32 struct clk_onecell_data data;
33 struct clk *clk_table[EXYNOS_CLKOUT_NR_CLKS];
34 void __iomem *reg;
35 u32 pmu_debug_save;
36};
37
38static struct exynos_clkout *clkout;
39
40static int exynos_clkout_suspend(void)
41{
42 clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
43
44 return 0;
45}
46
47static void exynos_clkout_resume(void)
48{
49 writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
50}
51
52static struct syscore_ops exynos_clkout_syscore_ops = {
53 .suspend = exynos_clkout_suspend,
54 .resume = exynos_clkout_resume,
55};
56
57static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
58{
59 const char *parent_names[EXYNOS_CLKOUT_PARENTS];
60 struct clk *parents[EXYNOS_CLKOUT_PARENTS];
61 int parent_count;
62 int ret;
63 int i;
64
65 clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
66 if (!clkout)
67 return;
68
69 spin_lock_init(&clkout->slock);
70
71 parent_count = 0;
72 for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
73 char name[] = "clkoutXX";
74
75 snprintf(name, sizeof(name), "clkout%d", i);
76 parents[i] = of_clk_get_by_name(node, name);
77 if (IS_ERR(parents[i])) {
78 parent_names[i] = "none";
79 continue;
80 }
81
82 parent_names[i] = __clk_get_name(parents[i]);
83 parent_count = i + 1;
84 }
85
86 if (!parent_count)
87 goto free_clkout;
88
89 clkout->reg = of_iomap(node, 0);
90 if (!clkout->reg)
91 goto clks_put;
92
93 clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
94 clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
95 clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
96 clkout->gate.lock = &clkout->slock;
97
98 clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
99 clkout->mux.mask = mux_mask;
100 clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
101 clkout->mux.lock = &clkout->slock;
102
103 clkout->clk_table[0] = clk_register_composite(NULL, "clkout",
104 parent_names, parent_count, &clkout->mux.hw,
105 &clk_mux_ops, NULL, NULL, &clkout->gate.hw,
106 &clk_gate_ops, CLK_SET_RATE_PARENT
107 | CLK_SET_RATE_NO_REPARENT);
108 if (IS_ERR(clkout->clk_table[0]))
109 goto err_unmap;
110
111 clkout->data.clks = clkout->clk_table;
112 clkout->data.clk_num = EXYNOS_CLKOUT_NR_CLKS;
113 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &clkout->data);
114 if (ret)
115 goto err_clk_unreg;
116
117 register_syscore_ops(&exynos_clkout_syscore_ops);
118
119 return;
120
121err_clk_unreg:
122 clk_unregister(clkout->clk_table[0]);
123err_unmap:
124 iounmap(clkout->reg);
125clks_put:
126 for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
127 if (!IS_ERR(parents[i]))
128 clk_put(parents[i]);
129free_clkout:
130 kfree(clkout);
131
132 pr_err("%s: failed to register clkout clock\n", __func__);
133}
134
135static void __init exynos4_clkout_init(struct device_node *node)
136{
137 exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK);
138}
139CLK_OF_DECLARE(exynos4210_clkout, "samsung,exynos4210-pmu",
140 exynos4_clkout_init);
141CLK_OF_DECLARE(exynos4212_clkout, "samsung,exynos4212-pmu",
142 exynos4_clkout_init);
143CLK_OF_DECLARE(exynos4412_clkout, "samsung,exynos4412-pmu",
144 exynos4_clkout_init);
145
146static void __init exynos5_clkout_init(struct device_node *node)
147{
148 exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK);
149}
150CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu",
151 exynos5_clkout_init);
152CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu",
153 exynos5_clkout_init);
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 7a17bd40d1dd..dc85f8e7a2d7 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -87,6 +87,22 @@
87#define SRC_CPU 0x14200 87#define SRC_CPU 0x14200
88#define DIV_CPU0 0x14500 88#define DIV_CPU0 0x14500
89#define DIV_CPU1 0x14504 89#define DIV_CPU1 0x14504
90#define PWR_CTRL1 0x15020
91#define PWR_CTRL2 0x15024
92
93/* Below definitions are used for PWR_CTRL settings */
94#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
95#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
96#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
97#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
98#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
99#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
100#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
101#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
102#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
103#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
104#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
105#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
90 106
91/* list of PLLs to be registered */ 107/* list of PLLs to be registered */
92enum exynos3250_plls { 108enum exynos3250_plls {
@@ -168,6 +184,8 @@ static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
168 SRC_CPU, 184 SRC_CPU,
169 DIV_CPU0, 185 DIV_CPU0,
170 DIV_CPU1, 186 DIV_CPU1,
187 PWR_CTRL1,
188 PWR_CTRL2,
171}; 189};
172 190
173static int exynos3250_clk_suspend(void) 191static int exynos3250_clk_suspend(void)
@@ -748,6 +766,27 @@ static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = {
748 UPLL_LOCK, UPLL_CON0, NULL), 766 UPLL_LOCK, UPLL_CON0, NULL),
749}; 767};
750 768
769static void __init exynos3_core_down_clock(void)
770{
771 unsigned int tmp;
772
773 /*
774 * Enable arm clock down (in idle) and set arm divider
775 * ratios in WFI/WFE state.
776 */
777 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
778 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
779 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
780 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
781 __raw_writel(tmp, reg_base + PWR_CTRL1);
782
783 /*
784 * Disable the clock up feature on Exynos4x12, in case it was
785 * enabled by bootloader.
786 */
787 __raw_writel(0x0, reg_base + PWR_CTRL2);
788}
789
751static void __init exynos3250_cmu_init(struct device_node *np) 790static void __init exynos3250_cmu_init(struct device_node *np)
752{ 791{
753 struct samsung_clk_provider *ctx; 792 struct samsung_clk_provider *ctx;
@@ -775,6 +814,10 @@ static void __init exynos3250_cmu_init(struct device_node *np)
775 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks)); 814 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
776 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks)); 815 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
777 816
817 exynos3_core_down_clock();
818
778 exynos3250_clk_sleep_init(); 819 exynos3250_clk_sleep_init();
820
821 samsung_clk_of_add_provider(np, ctx);
779} 822}
780CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); 823CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 7f4a473a7ad7..ac163d7f5bc3 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -25,10 +25,12 @@
25#define DIV_LEFTBUS 0x4500 25#define DIV_LEFTBUS 0x4500
26#define GATE_IP_LEFTBUS 0x4800 26#define GATE_IP_LEFTBUS 0x4800
27#define E4X12_GATE_IP_IMAGE 0x4930 27#define E4X12_GATE_IP_IMAGE 0x4930
28#define CLKOUT_CMU_LEFTBUS 0x4a00
28#define SRC_RIGHTBUS 0x8200 29#define SRC_RIGHTBUS 0x8200
29#define DIV_RIGHTBUS 0x8500 30#define DIV_RIGHTBUS 0x8500
30#define GATE_IP_RIGHTBUS 0x8800 31#define GATE_IP_RIGHTBUS 0x8800
31#define E4X12_GATE_IP_PERIR 0x8960 32#define E4X12_GATE_IP_PERIR 0x8960
33#define CLKOUT_CMU_RIGHTBUS 0x8a00
32#define EPLL_LOCK 0xc010 34#define EPLL_LOCK 0xc010
33#define VPLL_LOCK 0xc020 35#define VPLL_LOCK 0xc020
34#define EPLL_CON0 0xc110 36#define EPLL_CON0 0xc110
@@ -98,6 +100,7 @@
98#define GATE_IP_PERIL 0xc950 100#define GATE_IP_PERIL 0xc950
99#define E4210_GATE_IP_PERIR 0xc960 101#define E4210_GATE_IP_PERIR 0xc960
100#define GATE_BLOCK 0xc970 102#define GATE_BLOCK 0xc970
103#define CLKOUT_CMU_TOP 0xca00
101#define E4X12_MPLL_LOCK 0x10008 104#define E4X12_MPLL_LOCK 0x10008
102#define E4X12_MPLL_CON0 0x10108 105#define E4X12_MPLL_CON0 0x10108
103#define SRC_DMC 0x10200 106#define SRC_DMC 0x10200
@@ -105,6 +108,7 @@
105#define DIV_DMC0 0x10500 108#define DIV_DMC0 0x10500
106#define DIV_DMC1 0x10504 109#define DIV_DMC1 0x10504
107#define GATE_IP_DMC 0x10900 110#define GATE_IP_DMC 0x10900
111#define CLKOUT_CMU_DMC 0x10a00
108#define APLL_LOCK 0x14000 112#define APLL_LOCK 0x14000
109#define E4210_MPLL_LOCK 0x14008 113#define E4210_MPLL_LOCK 0x14008
110#define APLL_CON0 0x14100 114#define APLL_CON0 0x14100
@@ -114,11 +118,28 @@
114#define DIV_CPU1 0x14504 118#define DIV_CPU1 0x14504
115#define GATE_SCLK_CPU 0x14800 119#define GATE_SCLK_CPU 0x14800
116#define GATE_IP_CPU 0x14900 120#define GATE_IP_CPU 0x14900
121#define CLKOUT_CMU_CPU 0x14a00
122#define PWR_CTRL1 0x15020
123#define E4X12_PWR_CTRL2 0x15024
117#define E4X12_DIV_ISP0 0x18300 124#define E4X12_DIV_ISP0 0x18300
118#define E4X12_DIV_ISP1 0x18304 125#define E4X12_DIV_ISP1 0x18304
119#define E4X12_GATE_ISP0 0x18800 126#define E4X12_GATE_ISP0 0x18800
120#define E4X12_GATE_ISP1 0x18804 127#define E4X12_GATE_ISP1 0x18804
121 128
129/* Below definitions are used for PWR_CTRL settings */
130#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
131#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
132#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
133#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
134#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
135#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
136#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
137#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
138#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
139#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
140#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
141#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
142
122/* the exynos4 soc type */ 143/* the exynos4 soc type */
123enum exynos4_soc { 144enum exynos4_soc {
124 EXYNOS4210, 145 EXYNOS4210,
@@ -155,6 +176,7 @@ static unsigned long exynos4210_clk_save[] __initdata = {
155 E4210_GATE_IP_LCD1, 176 E4210_GATE_IP_LCD1,
156 E4210_GATE_IP_PERIR, 177 E4210_GATE_IP_PERIR,
157 E4210_MPLL_CON0, 178 E4210_MPLL_CON0,
179 PWR_CTRL1,
158}; 180};
159 181
160static unsigned long exynos4x12_clk_save[] __initdata = { 182static unsigned long exynos4x12_clk_save[] __initdata = {
@@ -164,6 +186,8 @@ static unsigned long exynos4x12_clk_save[] __initdata = {
164 E4X12_DIV_ISP, 186 E4X12_DIV_ISP,
165 E4X12_DIV_CAM1, 187 E4X12_DIV_CAM1,
166 E4X12_MPLL_CON0, 188 E4X12_MPLL_CON0,
189 PWR_CTRL1,
190 E4X12_PWR_CTRL2,
167}; 191};
168 192
169static unsigned long exynos4_clk_pll_regs[] __initdata = { 193static unsigned long exynos4_clk_pll_regs[] __initdata = {
@@ -242,6 +266,11 @@ static unsigned long exynos4_clk_regs[] __initdata = {
242 DIV_CPU1, 266 DIV_CPU1,
243 GATE_SCLK_CPU, 267 GATE_SCLK_CPU,
244 GATE_IP_CPU, 268 GATE_IP_CPU,
269 CLKOUT_CMU_LEFTBUS,
270 CLKOUT_CMU_RIGHTBUS,
271 CLKOUT_CMU_TOP,
272 CLKOUT_CMU_DMC,
273 CLKOUT_CMU_CPU,
245}; 274};
246 275
247static const struct samsung_clk_reg_dump src_mask_suspend[] = { 276static const struct samsung_clk_reg_dump src_mask_suspend[] = {
@@ -397,10 +426,32 @@ PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
397 "sclk_epll", "sclk_vpll", }; 426 "sclk_epll", "sclk_vpll", };
398PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", }; 427PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
399PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", }; 428PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
429PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
430 "sclk_usbphy1", "sclk_hdmiphy", "none",
431 "sclk_epll", "sclk_vpll" };
432PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
433 "div_gdl", "div_gpl" };
434PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
435 "div_gdr", "div_gpr" };
436PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
437 "sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
438 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
439 "aclk160", "aclk133", "aclk200", "aclk100",
440 "sclk_mfc", "sclk_g3d", "sclk_g2d",
441 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
442 "s_rxbyteclkhs0_4l" };
443PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
444 "div_dphy", "none", "div_pwi" };
445PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
446 "none", "arm_clk_div_2", "div_corem0",
447 "div_corem1", "div_corem0", "div_atb",
448 "div_periph", "div_pclk_dbg", "div_hpm" };
400 449
401/* Exynos 4x12-specific parent groups */ 450/* Exynos 4x12-specific parent groups */
402PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", }; 451PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
403PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", }; 452PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
453PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", };
454PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", };
404PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", }; 455PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
405PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", 456PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
406 "none", "sclk_hdmiphy", "mout_mpll_user_t", 457 "none", "sclk_hdmiphy", "mout_mpll_user_t",
@@ -418,6 +469,32 @@ PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
418PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; 469PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
419PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; 470PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
420PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; 471PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
472PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
473 "none", "sclk_hdmiphy", "sclk_mpll",
474 "sclk_epll", "sclk_vpll" };
475PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
476 "div_gdl", "div_gpl" };
477PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
478 "div_gdr", "div_gpr" };
479PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
480 "sclk_usbphy0", "none", "sclk_hdmiphy",
481 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
482 "aclk160", "aclk133", "aclk200", "aclk100",
483 "sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
484 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
485 "s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
486 "rx_half_byte_clk_csis1", "div_jpeg",
487 "sclk_pwm_isp", "sclk_spi0_isp",
488 "sclk_spi1_isp", "sclk_uart_isp",
489 "sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
490 "sclk_pcm0" };
491PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
492 "div_dmc", "div_dphy", "fout_mpll_div_2",
493 "div_pwi", "none", "div_c2c", "div_c2c_aclk" };
494PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
495 "arm_clk_div_2", "div_corem0", "div_corem1",
496 "div_cores", "div_atb", "div_periph",
497 "div_pclk_dbg", "div_hpm" };
421 498
422/* fixed rate clocks generated outside the soc */ 499/* fixed rate clocks generated outside the soc */
423static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 500static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
@@ -436,6 +513,24 @@ static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata =
436 FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 513 FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
437}; 514};
438 515
516static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata = {
517 FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
518 FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
519 FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
520 FFACTOR(0, "arm_clk_div_2", "arm_clk", 1, 2, 0),
521};
522
523static struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initdata = {
524 FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
525};
526
527static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initdata = {
528 FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
529 FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
530 FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
531 FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
532};
533
439/* list of mux clocks supported in all exynos4 soc's */ 534/* list of mux clocks supported in all exynos4 soc's */
440static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 535static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
441 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 536 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
@@ -451,6 +546,9 @@ static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
451 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), 546 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
452 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1), 547 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
453 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), 548 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
549
550 MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
551 MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
454}; 552};
455 553
456/* list of mux clocks supported in exynos4210 soc */ 554/* list of mux clocks supported in exynos4210 soc */
@@ -459,6 +557,14 @@ static struct samsung_mux_clock exynos4210_mux_early[] __initdata = {
459}; 557};
460 558
461static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 559static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
560 MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
561 MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
562 CLKOUT_CMU_LEFTBUS, 0, 5),
563
564 MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
565 MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
566 CLKOUT_CMU_RIGHTBUS, 0, 5),
567
462 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), 568 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
463 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), 569 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
464 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), 570 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
@@ -472,6 +578,7 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
472 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), 578 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
473 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), 579 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
474 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), 580 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
581 MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
475 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), 582 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
476 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), 583 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
477 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), 584 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
@@ -503,12 +610,30 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
503 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), 610 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
504 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), 611 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
505 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), 612 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
613 MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
614
615 MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
616 MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
617
618 MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
506}; 619};
507 620
508/* list of mux clocks supported in exynos4x12 soc */ 621/* list of mux clocks supported in exynos4x12 soc */
509static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 622static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
623 MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
624 MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
625 MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
626 CLKOUT_CMU_LEFTBUS, 0, 5),
627
628 MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
629 MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
630 MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
631 CLKOUT_CMU_RIGHTBUS, 0, 5),
632
510 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12, 633 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
511 SRC_CPU, 24, 1), 634 SRC_CPU, 24, 1),
635 MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
636
512 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), 637 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
513 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), 638 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
514 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12, 639 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
@@ -531,6 +656,7 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
531 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), 656 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
532 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 657 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
533 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), 658 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
659 MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
534 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), 660 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
535 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), 661 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
536 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), 662 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
@@ -565,15 +691,39 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
565 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), 691 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
566 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), 692 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
567 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), 693 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
694 MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
695
696 MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
697 MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
568 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), 698 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
569 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), 699 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
570 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), 700 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
701 MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
571}; 702};
572 703
573/* list of divider clocks supported in all exynos4 soc's */ 704/* list of divider clocks supported in all exynos4 soc's */
574static struct samsung_div_clock exynos4_div_clks[] __initdata = { 705static struct samsung_div_clock exynos4_div_clks[] __initdata = {
706 DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
707 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
708 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
709 CLKOUT_CMU_LEFTBUS, 8, 6),
710
711 DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
712 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
713 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
714 CLKOUT_CMU_RIGHTBUS, 8, 6),
715
575 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), 716 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
717 DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
718 DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
719 DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
720 DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
721 DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
576 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3), 722 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
723 DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
724 DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
725 DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
726
577 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), 727 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
578 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), 728 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
579 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), 729 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
@@ -631,6 +781,16 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
631 CLK_SET_RATE_PARENT, 0), 781 CLK_SET_RATE_PARENT, 0),
632 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, 782 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
633 CLK_SET_RATE_PARENT, 0), 783 CLK_SET_RATE_PARENT, 0),
784 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
785
786 DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
787 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
788 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
789 DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
790 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
791 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
792 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
793 DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
634}; 794};
635 795
636/* list of divider clocks supported in exynos4210 soc */ 796/* list of divider clocks supported in exynos4210 soc */
@@ -671,6 +831,8 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
671 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 831 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
672 8, 3, CLK_GET_RATE_NOCACHE, 0), 832 8, 3, CLK_GET_RATE_NOCACHE, 0),
673 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 833 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
834 DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
835 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
674}; 836};
675 837
676/* list of gate clocks supported in all exynos4 soc's */ 838/* list of gate clocks supported in all exynos4 soc's */
@@ -680,6 +842,8 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
680 * the device name and clock alias names specified below for some 842 * the device name and clock alias names specified below for some
681 * of the clocks can be removed. 843 * of the clocks can be removed.
682 */ 844 */
845 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
846 GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
683 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 847 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
684 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 848 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
685 0), 849 0),
@@ -695,11 +859,13 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
695 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), 859 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
696 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, 860 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
697 CLK_SET_RATE_PARENT, 0), 861 CLK_SET_RATE_PARENT, 0),
862 GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
698 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), 863 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
699 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), 864 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
700 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), 865 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
701 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), 866 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
702 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), 867 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
868 GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
703 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), 869 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
704 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, 870 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
705 CLK_SET_RATE_PARENT, 0), 871 CLK_SET_RATE_PARENT, 0),
@@ -781,19 +947,24 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
781 0, 0), 947 0, 0),
782 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 948 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
783 0, 0), 949 0, 0),
950 GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
784 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), 951 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
785 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), 952 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
786 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4, 953 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
787 0, 0), 954 0, 0),
955 GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
788 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0), 956 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
789 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, 957 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
790 0, 0), 958 0, 0),
791 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, 959 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
792 0, 0), 960 0, 0),
961 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
962 GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
793 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0, 963 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
794 0, 0), 964 0, 0),
795 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, 965 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
796 0, 0), 966 0, 0),
967 GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
797 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0, 968 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
798 0, 0), 969 0, 0),
799 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1, 970 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
@@ -806,6 +977,7 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
806 0, 0), 977 0, 0),
807 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8, 978 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
808 0, 0), 979 0, 0),
980 GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
809 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0, 981 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
810 0, 0), 982 0, 0),
811 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1, 983 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
@@ -852,6 +1024,21 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
852 0, 0), 1024 0, 0),
853 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27, 1025 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
854 0, 0), 1026 0, 0),
1027 GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
1028 GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
1029 GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
1030 GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
1031
1032 GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
1033 CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
1034 GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
1035 CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
1036 GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
1037 CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
1038 GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
1039 CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
1040 GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
1041 CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
855}; 1042};
856 1043
857/* list of gate clocks supported in exynos4210 soc */ 1044/* list of gate clocks supported in exynos4210 soc */
@@ -863,6 +1050,9 @@ static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
863 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), 1050 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
864 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 1051 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
865 0), 1052 0),
1053 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
1054 0),
1055 GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
866 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), 1056 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
867 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), 1057 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
868 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), 1058 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
@@ -906,6 +1096,8 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
906 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 1096 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
907 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 1097 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
908 0), 1098 0),
1099 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
1100 0),
909 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 1101 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
910 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 1102 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
911 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 1103 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
@@ -1062,7 +1254,7 @@ static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
1062 1254
1063} 1255}
1064 1256
1065static struct of_device_id ext_clk_match[] __initdata = { 1257static const struct of_device_id ext_clk_match[] __initconst = {
1066 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 1258 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
1067 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, 1259 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
1068 {}, 1260 {},
@@ -1164,6 +1356,32 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1164 VPLL_LOCK, VPLL_CON0, NULL), 1356 VPLL_LOCK, VPLL_CON0, NULL),
1165}; 1357};
1166 1358
1359static void __init exynos4_core_down_clock(enum exynos4_soc soc)
1360{
1361 unsigned int tmp;
1362
1363 /*
1364 * Enable arm clock down (in idle) and set arm divider
1365 * ratios in WFI/WFE state.
1366 */
1367 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
1368 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
1369 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
1370 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
1371 /* On Exynos4412 enable it also on core 2 and 3 */
1372 if (num_possible_cpus() == 4)
1373 tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
1374 PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
1375 __raw_writel(tmp, reg_base + PWR_CTRL1);
1376
1377 /*
1378 * Disable the clock up feature on Exynos4x12, in case it was
1379 * enabled by bootloader.
1380 */
1381 if (exynos4_soc == EXYNOS4X12)
1382 __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
1383}
1384
1167/* register exynos4 clocks */ 1385/* register exynos4 clocks */
1168static void __init exynos4_clk_init(struct device_node *np, 1386static void __init exynos4_clk_init(struct device_node *np,
1169 enum exynos4_soc soc) 1387 enum exynos4_soc soc)
@@ -1224,6 +1442,8 @@ static void __init exynos4_clk_init(struct device_node *np,
1224 ARRAY_SIZE(exynos4_div_clks)); 1442 ARRAY_SIZE(exynos4_div_clks));
1225 samsung_clk_register_gate(ctx, exynos4_gate_clks, 1443 samsung_clk_register_gate(ctx, exynos4_gate_clks,
1226 ARRAY_SIZE(exynos4_gate_clks)); 1444 ARRAY_SIZE(exynos4_gate_clks));
1445 samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
1446 ARRAY_SIZE(exynos4_fixed_factor_clks));
1227 1447
1228 if (exynos4_soc == EXYNOS4210) { 1448 if (exynos4_soc == EXYNOS4210) {
1229 samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks, 1449 samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
@@ -1236,6 +1456,9 @@ static void __init exynos4_clk_init(struct device_node *np,
1236 ARRAY_SIZE(exynos4210_gate_clks)); 1456 ARRAY_SIZE(exynos4210_gate_clks));
1237 samsung_clk_register_alias(ctx, exynos4210_aliases, 1457 samsung_clk_register_alias(ctx, exynos4210_aliases,
1238 ARRAY_SIZE(exynos4210_aliases)); 1458 ARRAY_SIZE(exynos4210_aliases));
1459 samsung_clk_register_fixed_factor(ctx,
1460 exynos4210_fixed_factor_clks,
1461 ARRAY_SIZE(exynos4210_fixed_factor_clks));
1239 } else { 1462 } else {
1240 samsung_clk_register_mux(ctx, exynos4x12_mux_clks, 1463 samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1241 ARRAY_SIZE(exynos4x12_mux_clks)); 1464 ARRAY_SIZE(exynos4x12_mux_clks));
@@ -1245,13 +1468,19 @@ static void __init exynos4_clk_init(struct device_node *np,
1245 ARRAY_SIZE(exynos4x12_gate_clks)); 1468 ARRAY_SIZE(exynos4x12_gate_clks));
1246 samsung_clk_register_alias(ctx, exynos4x12_aliases, 1469 samsung_clk_register_alias(ctx, exynos4x12_aliases,
1247 ARRAY_SIZE(exynos4x12_aliases)); 1470 ARRAY_SIZE(exynos4x12_aliases));
1471 samsung_clk_register_fixed_factor(ctx,
1472 exynos4x12_fixed_factor_clks,
1473 ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1248 } 1474 }
1249 1475
1250 samsung_clk_register_alias(ctx, exynos4_aliases, 1476 samsung_clk_register_alias(ctx, exynos4_aliases,
1251 ARRAY_SIZE(exynos4_aliases)); 1477 ARRAY_SIZE(exynos4_aliases));
1252 1478
1479 exynos4_core_down_clock(soc);
1253 exynos4_clk_sleep_init(); 1480 exynos4_clk_sleep_init();
1254 1481
1482 samsung_clk_of_add_provider(np, ctx);
1483
1255 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" 1484 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1256 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", 1485 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
1257 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", 1486 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 184f64293b26..70ec3d2608a1 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -748,7 +748,7 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
748 VPLL_LOCK, VPLL_CON0, NULL), 748 VPLL_LOCK, VPLL_CON0, NULL),
749}; 749};
750 750
751static struct of_device_id ext_clk_match[] __initdata = { 751static const struct of_device_id ext_clk_match[] __initconst = {
752 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 752 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
753 { }, 753 { },
754}; 754};
@@ -820,6 +820,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
820 820
821 exynos5250_clk_sleep_init(); 821 exynos5250_clk_sleep_init();
822 822
823 samsung_clk_of_add_provider(np, ctx);
824
823 pr_info("Exynos5250: clock setup completed, armclk=%ld\n", 825 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
824 _get_rate("div_arm2")); 826 _get_rate("div_arm2"));
825} 827}
diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
index 64596ba58df1..ce3de97e5f11 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -206,6 +206,8 @@ void __init exynos5260_cmu_register_one(struct device_node *np,
206 if (cmu->clk_regs) 206 if (cmu->clk_regs)
207 exynos5260_clk_sleep_init(reg_base, cmu->clk_regs, 207 exynos5260_clk_sleep_init(reg_base, cmu->clk_regs,
208 cmu->nr_clk_regs); 208 cmu->nr_clk_regs);
209
210 samsung_clk_of_add_provider(np, ctx);
209} 211}
210 212
211 213
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index c9505ab9ee70..231475bc2b99 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -204,6 +204,8 @@ static void __init exynos5410_clk_init(struct device_node *np)
204 samsung_clk_register_gate(ctx, exynos5410_gate_clks, 204 samsung_clk_register_gate(ctx, exynos5410_gate_clks,
205 ARRAY_SIZE(exynos5410_gate_clks)); 205 ARRAY_SIZE(exynos5410_gate_clks));
206 206
207 samsung_clk_of_add_provider(np, ctx);
208
207 pr_debug("Exynos5410: clock setup completed.\n"); 209 pr_debug("Exynos5410: clock setup completed.\n");
208} 210}
209CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init); 211CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 61eccf0dd72f..bc772f8585d6 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -28,6 +28,7 @@
28#define GATE_BUS_CPU 0x700 28#define GATE_BUS_CPU 0x700
29#define GATE_SCLK_CPU 0x800 29#define GATE_SCLK_CPU 0x800
30#define CLKOUT_CMU_CPU 0xa00 30#define CLKOUT_CMU_CPU 0xa00
31#define SRC_MASK_CPERI 0x4300
31#define GATE_IP_G2D 0x8800 32#define GATE_IP_G2D 0x8800
32#define CPLL_LOCK 0x10020 33#define CPLL_LOCK 0x10020
33#define DPLL_LOCK 0x10030 34#define DPLL_LOCK 0x10030
@@ -70,6 +71,8 @@
70#define SRC_TOP11 0x10284 71#define SRC_TOP11 0x10284
71#define SRC_TOP12 0x10288 72#define SRC_TOP12 0x10288
72#define SRC_TOP13 0x1028c /* 5800 specific */ 73#define SRC_TOP13 0x1028c /* 5800 specific */
74#define SRC_MASK_TOP0 0x10300
75#define SRC_MASK_TOP1 0x10304
73#define SRC_MASK_TOP2 0x10308 76#define SRC_MASK_TOP2 0x10308
74#define SRC_MASK_TOP7 0x1031c 77#define SRC_MASK_TOP7 0x1031c
75#define SRC_MASK_DISP10 0x1032c 78#define SRC_MASK_DISP10 0x1032c
@@ -77,6 +80,7 @@
77#define SRC_MASK_FSYS 0x10340 80#define SRC_MASK_FSYS 0x10340
78#define SRC_MASK_PERIC0 0x10350 81#define SRC_MASK_PERIC0 0x10350
79#define SRC_MASK_PERIC1 0x10354 82#define SRC_MASK_PERIC1 0x10354
83#define SRC_MASK_ISP 0x10370
80#define DIV_TOP0 0x10500 84#define DIV_TOP0 0x10500
81#define DIV_TOP1 0x10504 85#define DIV_TOP1 0x10504
82#define DIV_TOP2 0x10508 86#define DIV_TOP2 0x10508
@@ -98,6 +102,7 @@
98#define DIV2_RATIO0 0x10590 102#define DIV2_RATIO0 0x10590
99#define DIV4_RATIO 0x105a0 103#define DIV4_RATIO 0x105a0
100#define GATE_BUS_TOP 0x10700 104#define GATE_BUS_TOP 0x10700
105#define GATE_BUS_DISP1 0x10728
101#define GATE_BUS_GEN 0x1073c 106#define GATE_BUS_GEN 0x1073c
102#define GATE_BUS_FSYS0 0x10740 107#define GATE_BUS_FSYS0 0x10740
103#define GATE_BUS_FSYS2 0x10748 108#define GATE_BUS_FSYS2 0x10748
@@ -190,6 +195,10 @@ static unsigned long exynos5x_clk_regs[] __initdata = {
190 SRC_MASK_FSYS, 195 SRC_MASK_FSYS,
191 SRC_MASK_PERIC0, 196 SRC_MASK_PERIC0,
192 SRC_MASK_PERIC1, 197 SRC_MASK_PERIC1,
198 SRC_MASK_TOP0,
199 SRC_MASK_TOP1,
200 SRC_MASK_MAU,
201 SRC_MASK_ISP,
193 SRC_ISP, 202 SRC_ISP,
194 DIV_TOP0, 203 DIV_TOP0,
195 DIV_TOP1, 204 DIV_TOP1,
@@ -208,6 +217,7 @@ static unsigned long exynos5x_clk_regs[] __initdata = {
208 SCLK_DIV_ISP1, 217 SCLK_DIV_ISP1,
209 DIV2_RATIO0, 218 DIV2_RATIO0,
210 DIV4_RATIO, 219 DIV4_RATIO,
220 GATE_BUS_DISP1,
211 GATE_BUS_TOP, 221 GATE_BUS_TOP,
212 GATE_BUS_GEN, 222 GATE_BUS_GEN,
213 GATE_BUS_FSYS0, 223 GATE_BUS_FSYS0,
@@ -249,6 +259,22 @@ static unsigned long exynos5800_clk_regs[] __initdata = {
249 GATE_IP_CAM, 259 GATE_IP_CAM,
250}; 260};
251 261
262static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
263 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
264 { .offset = SRC_MASK_TOP0, .value = 0x11111111, },
265 { .offset = SRC_MASK_TOP1, .value = 0x11101111, },
266 { .offset = SRC_MASK_TOP2, .value = 0x11111110, },
267 { .offset = SRC_MASK_TOP7, .value = 0x00111100, },
268 { .offset = SRC_MASK_DISP10, .value = 0x11111110, },
269 { .offset = SRC_MASK_MAU, .value = 0x10000000, },
270 { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
271 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
272 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
273 { .offset = SRC_MASK_ISP, .value = 0x11111000, },
274 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
275 { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
276};
277
252static int exynos5420_clk_suspend(void) 278static int exynos5420_clk_suspend(void)
253{ 279{
254 samsung_clk_save(reg_base, exynos5x_save, 280 samsung_clk_save(reg_base, exynos5x_save,
@@ -258,6 +284,9 @@ static int exynos5420_clk_suspend(void)
258 samsung_clk_save(reg_base, exynos5800_save, 284 samsung_clk_save(reg_base, exynos5800_save,
259 ARRAY_SIZE(exynos5800_clk_regs)); 285 ARRAY_SIZE(exynos5800_clk_regs));
260 286
287 samsung_clk_restore(reg_base, exynos5420_set_clksrc,
288 ARRAY_SIZE(exynos5420_set_clksrc));
289
261 return 0; 290 return 0;
262} 291}
263 292
@@ -1167,6 +1196,28 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
1167 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1196 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1168}; 1197};
1169 1198
1199static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = {
1200 PLL_35XX_RATE(2000000000, 250, 3, 0),
1201 PLL_35XX_RATE(1900000000, 475, 6, 0),
1202 PLL_35XX_RATE(1800000000, 225, 3, 0),
1203 PLL_35XX_RATE(1700000000, 425, 6, 0),
1204 PLL_35XX_RATE(1600000000, 200, 3, 0),
1205 PLL_35XX_RATE(1500000000, 250, 4, 0),
1206 PLL_35XX_RATE(1400000000, 175, 3, 0),
1207 PLL_35XX_RATE(1300000000, 325, 6, 0),
1208 PLL_35XX_RATE(1200000000, 200, 2, 1),
1209 PLL_35XX_RATE(1100000000, 275, 3, 1),
1210 PLL_35XX_RATE(1000000000, 250, 3, 1),
1211 PLL_35XX_RATE(900000000, 150, 2, 1),
1212 PLL_35XX_RATE(800000000, 200, 3, 1),
1213 PLL_35XX_RATE(700000000, 175, 3, 1),
1214 PLL_35XX_RATE(600000000, 200, 2, 2),
1215 PLL_35XX_RATE(500000000, 250, 3, 2),
1216 PLL_35XX_RATE(400000000, 200, 3, 2),
1217 PLL_35XX_RATE(300000000, 200, 2, 3),
1218 PLL_35XX_RATE(200000000, 200, 3, 3),
1219};
1220
1170static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1221static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1171 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1222 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1172 APLL_CON0, NULL), 1223 APLL_CON0, NULL),
@@ -1192,7 +1243,7 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1192 KPLL_CON0, NULL), 1243 KPLL_CON0, NULL),
1193}; 1244};
1194 1245
1195static struct of_device_id ext_clk_match[] __initdata = { 1246static const struct of_device_id ext_clk_match[] __initconst = {
1196 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 1247 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1197 { }, 1248 { },
1198}; 1249};
@@ -1220,6 +1271,12 @@ static void __init exynos5x_clk_init(struct device_node *np,
1220 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 1271 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1221 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 1272 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1222 ext_clk_match); 1273 ext_clk_match);
1274
1275 if (_get_rate("fin_pll") == 24 * MHZ) {
1276 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1277 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1278 }
1279
1223 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1280 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1224 reg_base); 1281 reg_base);
1225 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 1282 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
@@ -1251,6 +1308,8 @@ static void __init exynos5x_clk_init(struct device_node *np,
1251 } 1308 }
1252 1309
1253 exynos5420_clk_sleep_init(); 1310 exynos5420_clk_sleep_init();
1311
1312 samsung_clk_of_add_provider(np, ctx);
1254} 1313}
1255 1314
1256static void __init exynos5420_clk_init(struct device_node *np) 1315static void __init exynos5420_clk_init(struct device_node *np)
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index 647f1440aa6a..00d1d00a41de 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -84,7 +84,7 @@ static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
84 GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0), 84 GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
85}; 85};
86 86
87static struct of_device_id ext_clk_match[] __initdata = { 87static const struct of_device_id ext_clk_match[] __initconst = {
88 { .compatible = "samsung,clock-xtal", .data = (void *)0, }, 88 { .compatible = "samsung,clock-xtal", .data = (void *)0, },
89 {}, 89 {},
90}; 90};
@@ -123,6 +123,8 @@ static void __init exynos5440_clk_init(struct device_node *np)
123 samsung_clk_register_gate(ctx, exynos5440_gate_clks, 123 samsung_clk_register_gate(ctx, exynos5440_gate_clks,
124 ARRAY_SIZE(exynos5440_gate_clks)); 124 ARRAY_SIZE(exynos5440_gate_clks));
125 125
126 samsung_clk_of_add_provider(np, ctx);
127
126 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk")); 128 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
127 pr_info("exynos5440 clock initialization complete\n"); 129 pr_info("exynos5440 clock initialization complete\n");
128} 130}
diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c
index 140f4733c02e..5d2f03461bc5 100644
--- a/drivers/clk/samsung/clk-s3c2410.c
+++ b/drivers/clk/samsung/clk-s3c2410.c
@@ -466,6 +466,8 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
466 } 466 }
467 467
468 s3c2410_clk_sleep_init(); 468 s3c2410_clk_sleep_init();
469
470 samsung_clk_of_add_provider(np, ctx);
469} 471}
470 472
471static void __init s3c2410_clk_init(struct device_node *np) 473static void __init s3c2410_clk_init(struct device_node *np)
diff --git a/drivers/clk/samsung/clk-s3c2412.c b/drivers/clk/samsung/clk-s3c2412.c
index 23e4313f625e..34af09f6a155 100644
--- a/drivers/clk/samsung/clk-s3c2412.c
+++ b/drivers/clk/samsung/clk-s3c2412.c
@@ -265,6 +265,8 @@ void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
265 ARRAY_SIZE(s3c2412_aliases)); 265 ARRAY_SIZE(s3c2412_aliases));
266 266
267 s3c2412_clk_sleep_init(); 267 s3c2412_clk_sleep_init();
268
269 samsung_clk_of_add_provider(np, ctx);
268} 270}
269 271
270static void __init s3c2412_clk_init(struct device_node *np) 272static void __init s3c2412_clk_init(struct device_node *np)
diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
index c4bbdabebaa4..c92f853fca9f 100644
--- a/drivers/clk/samsung/clk-s3c2443.c
+++ b/drivers/clk/samsung/clk-s3c2443.c
@@ -445,6 +445,8 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
445 } 445 }
446 446
447 s3c2443_clk_sleep_init(); 447 s3c2443_clk_sleep_init();
448
449 samsung_clk_of_add_provider(np, ctx);
448} 450}
449 451
450static void __init s3c2416_clk_init(struct device_node *np) 452static void __init s3c2416_clk_init(struct device_node *np)
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
index 8889ff1c10fc..0f590e5550cb 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -518,6 +518,8 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
518 ARRAY_SIZE(s3c64xx_clock_aliases)); 518 ARRAY_SIZE(s3c64xx_clock_aliases));
519 s3c64xx_clk_sleep_init(); 519 s3c64xx_clk_sleep_init();
520 520
521 samsung_clk_of_add_provider(np, ctx);
522
521 pr_info("%s clocks: apll = %lu, mpll = %lu\n" 523 pr_info("%s clocks: apll = %lu, mpll = %lu\n"
522 "\tepll = %lu, arm_clk = %lu\n", 524 "\tepll = %lu, arm_clk = %lu\n",
523 is_s3c6400 ? "S3C6400" : "S3C6410", 525 is_s3c6400 ? "S3C6400" : "S3C6410",
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 49629c71c9e7..deab84d9f37d 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -53,7 +53,6 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
53{ 53{
54 struct samsung_clk_provider *ctx; 54 struct samsung_clk_provider *ctx;
55 struct clk **clk_table; 55 struct clk **clk_table;
56 int ret;
57 int i; 56 int i;
58 57
59 ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); 58 ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
@@ -72,17 +71,19 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
72 ctx->clk_data.clk_num = nr_clks; 71 ctx->clk_data.clk_num = nr_clks;
73 spin_lock_init(&ctx->lock); 72 spin_lock_init(&ctx->lock);
74 73
75 if (!np)
76 return ctx;
77
78 ret = of_clk_add_provider(np, of_clk_src_onecell_get,
79 &ctx->clk_data);
80 if (ret)
81 panic("could not register clock provide\n");
82
83 return ctx; 74 return ctx;
84} 75}
85 76
77void __init samsung_clk_of_add_provider(struct device_node *np,
78 struct samsung_clk_provider *ctx)
79{
80 if (np) {
81 if (of_clk_add_provider(np, of_clk_src_onecell_get,
82 &ctx->clk_data))
83 panic("could not register clk provider\n");
84 }
85}
86
86/* add a clock instance to the clock lookup table used for dt based lookup */ 87/* add a clock instance to the clock lookup table used for dt based lookup */
87void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, 88void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
88 unsigned int id) 89 unsigned int id)
@@ -284,7 +285,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
284void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, 285void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
285 struct samsung_fixed_rate_clock *fixed_rate_clk, 286 struct samsung_fixed_rate_clock *fixed_rate_clk,
286 unsigned int nr_fixed_rate_clk, 287 unsigned int nr_fixed_rate_clk,
287 struct of_device_id *clk_matches) 288 const struct of_device_id *clk_matches)
288{ 289{
289 const struct of_device_id *match; 290 const struct of_device_id *match;
290 struct device_node *clk_np; 291 struct device_node *clk_np;
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 9693b80d924f..66ab36b5cef1 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -327,11 +327,13 @@ struct samsung_pll_clock {
327extern struct samsung_clk_provider *__init samsung_clk_init( 327extern struct samsung_clk_provider *__init samsung_clk_init(
328 struct device_node *np, void __iomem *base, 328 struct device_node *np, void __iomem *base,
329 unsigned long nr_clks); 329 unsigned long nr_clks);
330extern void __init samsung_clk_of_add_provider(struct device_node *np,
331 struct samsung_clk_provider *ctx);
330extern void __init samsung_clk_of_register_fixed_ext( 332extern void __init samsung_clk_of_register_fixed_ext(
331 struct samsung_clk_provider *ctx, 333 struct samsung_clk_provider *ctx,
332 struct samsung_fixed_rate_clock *fixed_rate_clk, 334 struct samsung_fixed_rate_clock *fixed_rate_clk,
333 unsigned int nr_fixed_rate_clk, 335 unsigned int nr_fixed_rate_clk,
334 struct of_device_id *clk_matches); 336 const struct of_device_id *clk_matches);
335 337
336extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, 338extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
337 struct clk *clk, unsigned int id); 339 struct clk *clk, unsigned int id);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 22:27:58 -0400