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path: root/drivers/clk/samsung/clk-exynos5440.c
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Diffstat (limited to 'drivers/clk/samsung/clk-exynos5440.c')
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index 647f1440aa6a..00d1d00a41de 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -84,7 +84,7 @@ static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
84 GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0), 84 GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
85}; 85};
86 86
87static struct of_device_id ext_clk_match[] __initdata = { 87static const struct of_device_id ext_clk_match[] __initconst = {
88 { .compatible = "samsung,clock-xtal", .data = (void *)0, }, 88 { .compatible = "samsung,clock-xtal", .data = (void *)0, },
89 {}, 89 {},
90}; 90};
@@ -123,6 +123,8 @@ static void __init exynos5440_clk_init(struct device_node *np)
123 samsung_clk_register_gate(ctx, exynos5440_gate_clks, 123 samsung_clk_register_gate(ctx, exynos5440_gate_clks,
124 ARRAY_SIZE(exynos5440_gate_clks)); 124 ARRAY_SIZE(exynos5440_gate_clks));
125 125
126 samsung_clk_of_add_provider(np, ctx);
127
126 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk")); 128 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
127 pr_info("exynos5440 clock initialization complete\n"); 129 pr_info("exynos5440 clock initialization complete\n");
128} 130}