aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2014-06-10 21:54:22 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-06-10 21:54:22 -0400
commitc5aec4c76af1a2d89ee2f2d4d5463b2ad2d85de5 (patch)
tree628ae2d9370a6739fd98d8d2f055b46c87ab9316 /drivers
parent2937f5efa5754754daf46de745f67350f7f06ec2 (diff)
parent0c0a3e5a100bbc4aaedd140e82b429227a76701b (diff)
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc updates from Ben Herrenschmidt: "Here is the bulk of the powerpc changes for this merge window. It got a bit delayed in part because I wasn't paying attention, and in part because I discovered I had a core PCI change without a PCI maintainer ack in it. Bjorn eventually agreed it was ok to merge it though we'll probably improve it later and I didn't want to rebase to add his ack. There is going to be a bit more next week, essentially fixes that I still want to sort through and test. The biggest item this time is the support to build the ppc64 LE kernel with our new v2 ABI. We previously supported v2 userspace but the kernel itself was a tougher nut to crack. This is now sorted mostly thanks to Anton and Rusty. We also have a fairly big series from Cedric that add support for 64-bit LE zImage boot wrapper. This was made harder by the fact that traditionally our zImage wrapper was always 32-bit, but our new LE toolchains don't really support 32-bit anymore (it's somewhat there but not really "supported") so we didn't want to rely on it. This meant more churn that just endian fixes. This brings some more LE bits as well, such as the ability to run in LE mode without a hypervisor (ie. under OPAL firmware) by doing the right OPAL call to reinitialize the CPU to take HV interrupts in the right mode and the usual pile of endian fixes. There's another series from Gavin adding EEH improvements (one day we *will* have a release with less than 20 EEH patches, I promise!). Another highlight is the support for the "Split core" functionality on P8 by Michael. This allows a P8 core to be split into "sub cores" of 4 threads which allows the subcores to run different guests under KVM (the HW still doesn't support a partition per thread). And then the usual misc bits and fixes ..." [ Further delayed by gmail deciding that BenH is a dirty spammer. Google knows. ] * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (155 commits) powerpc/powernv: Add missing include to LPC code selftests/powerpc: Test the THP bug we fixed in the previous commit powerpc/mm: Check paca psize is up to date for huge mappings powerpc/powernv: Pass buffer size to OPAL validate flash call powerpc/pseries: hcall functions are exported to modules, need _GLOBAL_TOC() powerpc: Exported functions __clear_user and copy_page use r2 so need _GLOBAL_TOC() powerpc/powernv: Set memory_block_size_bytes to 256MB powerpc: Allow ppc_md platform hook to override memory_block_size_bytes powerpc/powernv: Fix endian issues in memory error handling code powerpc/eeh: Skip eeh sysfs when eeh is disabled powerpc: 64bit sendfile is capped at 2GB powerpc/powernv: Provide debugfs access to the LPC bus via OPAL powerpc/serial: Use saner flags when creating legacy ports powerpc: Add cpu family documentation powerpc/xmon: Fix up xmon format strings powerpc/powernv: Add calls to support little endian host powerpc: Document sysfs DSCR interface powerpc: Fix regression of per-CPU DSCR setting powerpc: Split __SYSFS_SPRSETUP macro arch: powerpc/fadump: Cleaning up inconsistent NULL checks ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/macintosh/windfarm_pm121.c16
-rw-r--r--drivers/pci/pci.c21
2 files changed, 26 insertions, 11 deletions
diff --git a/drivers/macintosh/windfarm_pm121.c b/drivers/macintosh/windfarm_pm121.c
index 7fe58b0ae8b4..b350fb86ff08 100644
--- a/drivers/macintosh/windfarm_pm121.c
+++ b/drivers/macintosh/windfarm_pm121.c
@@ -555,8 +555,18 @@ static void pm121_create_sys_fans(int loop_id)
555 pid_param.interval = PM121_SYS_INTERVAL; 555 pid_param.interval = PM121_SYS_INTERVAL;
556 pid_param.history_len = PM121_SYS_HISTORY_SIZE; 556 pid_param.history_len = PM121_SYS_HISTORY_SIZE;
557 pid_param.itarget = param->itarget; 557 pid_param.itarget = param->itarget;
558 pid_param.min = control->ops->get_min(control); 558 if(control)
559 pid_param.max = control->ops->get_max(control); 559 {
560 pid_param.min = control->ops->get_min(control);
561 pid_param.max = control->ops->get_max(control);
562 } else {
563 /*
564 * This is probably not the right!?
565 * Perhaps goto fail if control == NULL above?
566 */
567 pid_param.min = 0;
568 pid_param.max = 0;
569 }
560 570
561 wf_pid_init(&pm121_sys_state[loop_id]->pid, &pid_param); 571 wf_pid_init(&pm121_sys_state[loop_id]->pid, &pid_param);
562 572
@@ -571,7 +581,7 @@ static void pm121_create_sys_fans(int loop_id)
571 control the same control */ 581 control the same control */
572 printk(KERN_WARNING "pm121: failed to set up %s loop " 582 printk(KERN_WARNING "pm121: failed to set up %s loop "
573 "setting \"%s\" to max speed.\n", 583 "setting \"%s\" to max speed.\n",
574 loop_names[loop_id], control->name); 584 loop_names[loop_id], control ? control->name : "uninitialized value");
575 585
576 if (control) 586 if (control)
577 wf_control_set_max(control); 587 wf_control_set_max(control);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 436a76ab4bb1..212c63d780e7 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3179,14 +3179,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
3179 return 0; 3179 return 0;
3180} 3180}
3181 3181
3182/** 3182void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3183 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3184 * @dev: Bridge device
3185 *
3186 * Use the bridge control register to assert reset on the secondary bus.
3187 * Devices on the secondary bus are left in power-on state.
3188 */
3189void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3190{ 3183{
3191 u16 ctrl; 3184 u16 ctrl;
3192 3185
@@ -3211,6 +3204,18 @@ void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3211 */ 3204 */
3212 ssleep(1); 3205 ssleep(1);
3213} 3206}
3207
3208/**
3209 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3210 * @dev: Bridge device
3211 *
3212 * Use the bridge control register to assert reset on the secondary bus.
3213 * Devices on the secondary bus are left in power-on state.
3214 */
3215void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3216{
3217 pcibios_reset_secondary_bus(dev);
3218}
3214EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); 3219EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3215 3220
3216static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 3221static int pci_parent_bus_reset(struct pci_dev *dev, int probe)