205 files changed, 6897 insertions, 1772 deletions
diff --git a/Documentation/ABI/stable/sysfs-devices-system-cpu b/Documentation/ABI/stable/sysfs-devices-system-cpu
new file mode 100644
index 000000000000..33c133e2a631
--- /dev/null
+++ b/Documentation/ABI/stable/sysfs-devices-system-cpu
@@ -0,0 +1,25 @@
+What:           /sys/devices/system/cpu/dscr_default
+Date:           13-May-2014
+KernelVersion:  v3.15.0
+Contact:
+Description:    Writes are equivalent to writing to
+                /sys/devices/system/cpu/cpuN/dscr on all CPUs.
+                Reads return the last written value or 0.
+                This value is not a global default: it is a way to set
+                all per-CPU defaults at the same time.
+Values:         64 bit unsigned integer (bit field)
+What:           /sys/devices/system/cpu/cpu[0-9]+/dscr
+Date:           13-May-2014
+KernelVersion:  v3.15.0
+Contact:
+Description:    Default value for the Data Stream Control Register (DSCR) on
+                a CPU.
+                This default value is used when the kernel is executing and
+                for any process that has not set the DSCR itself.
+                If a process ever sets the DSCR (via direct access to the
+                SPR) that value will be persisted for that process and used
+                on any CPU where it executes (overriding the value described
+                here).
+                If set by a process it will be inherited by child processes.
+Values:         64 bit unsigned integer (bit field)
diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 24711af48e30..5666812fc42b 100644
--- a/Documentation/devicetree/bindings/clock/corenet-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -7,6 +7,14 @@ which can then be passed to a variety of internal logic, including
 cores and peripheral IP blocks.
 Please refer to the Reference Manual for details.
+All references to "1.0" and "2.0" refer to the QorIQ chassis version to
+which the chip complies.
+Chassis Version         Example Chips
+---------------         -------------
+1.0                     p4080, p5020, p5040
+2.0                     t4240, b4860, t1040
 1. Clock Block Binding
 Required properties:
@@ -85,7 +93,7 @@ Example for clock block and clock provider:
                        #clock-cells = <0>;
                        compatible = "fsl,qoriq-sysclk-1.0";
                        clock-output-names = "sysclk";
-                }
+                };
                pll0: pll0@800 {
                        #clock-cells = <1>;
diff --git a/Documentation/devicetree/bindings/mfd/bfticu.txt b/Documentation/devicetree/bindings/mfd/bfticu.txt
new file mode 100644
index 000000000000..65c90776c620
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/bfticu.txt
@@ -0,0 +1,25 @@
+KEYMILE bfticu Chassis Management FPGA
+The bfticu is a multifunction device that manages the whole chassis.
+Its main functionality is to collect IRQs from the whole chassis and signals
+them to a single controller.
+Required properties:
+- compatible: "keymile,bfticu"
+- interrupt-controller: the bfticu FPGA is an interrupt controller
+- interrupts: the main IRQ line to signal the collected IRQs
+- #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant
+  of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+- interrupt-parent: the parent IRQ ctrl the main IRQ is connected to
+- reg: access on the parent local bus (chip select, offset in chip select, size)
+Example:
+        chassis-mgmt@3,0 {
+                compatible = "keymile,bfticu";
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                reg = <3 0 0x100>;
+                interrupt-parent = <&mpic>;
+                interrupts = <6 1 0 0>;
+        };
diff --git a/Documentation/devicetree/bindings/mfd/qriox.txt b/Documentation/devicetree/bindings/mfd/qriox.txt
new file mode 100644
index 000000000000..f301e2d4ce76
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qriox.txt
@@ -0,0 +1,17 @@
+KEYMILE qrio Board Control CPLD
+The qrio is a multifunction device that controls the KEYMILE boards based on
+the kmp204x design.
+It is consists of a reset controller, watchdog timer, LEDs, and 2 IRQ capable
+GPIO blocks.
+Required properties:
+- compatible: "keymile,qriox"
+- reg: access on the parent local bus (chip select, offset in chip select, size)
+Example:
+        board-control@1,0 {
+                compatible = "keymile,qriox";
+                reg = <1 0 0x80>;
+        };
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/akebono.txt b/Documentation/devicetree/bindings/powerpc/4xx/akebono.txt
new file mode 100644
index 000000000000..db939210e29d
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/4xx/akebono.txt
@@ -0,0 +1,54 @@
+IBM Akebono board device tree
+=============================
+The IBM Akebono board is a development board for the PPC476GTR SoC.
+0) The root node
+   Required properties:
+   - model : "ibm,akebono".
+   - compatible : "ibm,akebono" , "ibm,476gtr".
+1.a) The Secure Digital Host Controller Interface (SDHCI) node
+  Represent the Secure Digital Host Controller Interfaces.
+  Required properties:
+   - compatible : should be "ibm,476gtr-sdhci","generic-sdhci".
+   - reg : should contain the SDHCI registers location and length.
+   - interrupt-parent : a phandle for the interrupt controller.
+   - interrupts : should contain the SDHCI interrupt.
+1.b) The Advanced Host Controller Interface (AHCI) SATA node
+  Represents the advanced host controller SATA interface.
+  Required properties:
+   - compatible : should be "ibm,476gtr-ahci".
+   - reg : should contain the AHCI registers location and length.
+   - interrupt-parent : a phandle for the interrupt controller.
+   - interrupts : should contain the AHCI interrupt.
+1.c) The FPGA node
+  The Akebono board stores some board information such as the revision
+  number in an FPGA which is represented by this node.
+  Required properties:
+   - compatible : should be "ibm,akebono-fpga".
+   - reg : should contain the FPGA registers location and length.
+1.d) The AVR node
+  The Akebono board has an Atmel AVR microprocessor attached to the I2C
+  bus as a power controller for the board.
+  Required properties:
+   - compatible : should be "ibm,akebono-avr".
+   - reg : should contain the I2C bus address for the AVR.
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/hsta.txt b/Documentation/devicetree/bindings/powerpc/4xx/hsta.txt
new file mode 100644
index 000000000000..c737c8338705
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/4xx/hsta.txt
@@ -0,0 +1,19 @@
+ppc476gtr High Speed Serial Assist (HSTA) node
+==============================================
+The 476gtr SoC contains a high speed serial assist module attached
+between the plb4 and plb6 system buses to provide high speed data
+transfer between memory and system peripherals as well as support for
+PCI message signalled interrupts.
+Currently only the MSI support is used by Linux using the following
+device tree entries:
+Require properties:
+- compatible            : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
+- reg                   : register mapping for the HSTA MSI space
+- interrupt-parent      : parent controller for mapping interrupts
+- interrupts            : ordered interrupt mapping for each MSI in the register
+                          space. The first interrupt should be associated with a
+                          register offset of 0x00, the second to 0x10, etc.
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
index 380914e965e0..700dec4774fa 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/board.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
@@ -67,3 +67,20 @@ Example:
                        gpio-controller;
                };
        };
+* Freescale on-board FPGA connected on I2C bus
+Some Freescale boards like BSC9132QDS have on board FPGA connected on
+the i2c bus.
+Required properties:
+- compatible: Should be a board-specific string followed by a string
+  indicating the type of FPGA.  Example:
+        "fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
+- reg: Should contain the address of the FPGA
+Example:
+        fpga: fpga@66 {
+                compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
+                reg = <0x66>;
+        };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
new file mode 100644
index 000000000000..454da7e08acd
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
@@ -0,0 +1,46 @@
+Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
+DESCRIPTION
+The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
+that enables the implementation of coherent, multicore systems.
+Required properties:
+- compatible: <string list>
+                fsl,corenet1-cf - CoreNet coherency fabric version 1.
+                Example chips: T4240, B4860
+                fsl,corenet2-cf - CoreNet coherency fabric version 2.
+                Example chips: P5040, P5020, P4080, P3041, P2041
+                fsl,corenet-cf - Used to represent the common registers
+                between CCF version 1 and CCF version 2.  This compatible
+                is retained for compatibility reasons, as it was already
+                used for both CCF version 1 chips and CCF version 2
+                chips.  It should be specified after either
+                "fsl,corenet1-cf" or "fsl,corenet2-cf".
+- reg: <prop-encoded-array>
+                A standard property. Represents the CCF registers.
+- interrupts: <prop-encoded-array>
+                Interrupt mapping for CCF error interrupt.
+- fsl,ccf-num-csdids: <u32>
+                Specifies the number of Coherency Subdomain ID Port Mapping
+                Registers that are supported by the CCF.
+- fsl,ccf-num-snoopids: <u32>
+                Specifies the number of Snoop ID Port Mapping Registers that
+                are supported by CCF.
+Example:
+        corenet-cf@18000 {
+                compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
+                reg = <0x18000 0x1000>;
+                interrupts = <16 2 1 31>;
+                fsl,ccf-num-csdids = <32>;
+                fsl,ccf-num-snoopids = <32>;
+        };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
index 922c30ad90d1..f8cd2397aa04 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
@@ -20,3 +20,14 @@ PROPERTIES
        a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
        name with all uppercase letters converted to lowercase, indicates that
        the category is supported by the implementation.
+    - fsl,portid-mapping
+        Usage: optional
+        Value type: <u32>
+        Definition: The Coherency Subdomain ID Port Mapping Registers and
+        Snoop ID Port Mapping registers, which are part of the CoreNet
+        Coherency fabric (CCF), provide a CoreNet Coherency Subdomain
+        ID/CoreNet Snoop ID to cpu mapping functions.  Certain bits from
+        these registers should be set if the coresponding CPU should be
+        snooped.  This property defines a bitmask which selects the bit
+        that should be set if this cpu should be snooped.
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt b/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt
index 1f5e329f756c..c2b2899885f2 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/pamu.txt
@@ -34,6 +34,15 @@ Optional properties:
                  for legacy drivers.
 - interrupt-parent : <phandle>
                  Phandle to interrupt controller
+- fsl,portid-mapping : <u32>
+                  The Coherency Subdomain ID Port Mapping Registers and
+                  Snoop ID Port Mapping registers, which are part of the
+                  CoreNet Coherency fabric (CCF), provide a CoreNet
+                  Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping
+                  functions.  Certain bits from these registers should be
+                  set if PAMUs should be snooped.  This property defines
+                  a bitmask which selects the bits that should be set if
+                  PAMUs should be snooped.
 Child nodes:
@@ -88,6 +97,7 @@ Example:
                compatible = "fsl,pamu-v1.0", "fsl,pamu";
                reg = <0x20000 0x5000>;
                ranges = <0 0x20000 0x5000>;
+                fsl,portid-mapping = <0xf80000>;
                #address-cells = <1>;
                #size-cells = <1>;
                interrupts = <
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 5261271046ce..4d7f3758d1b4 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -142,3 +142,4 @@ wm	Wondermedia Technologies, Inc.
 xes     Extreme Engineering Solutions (X-ES)
 xlnx    Xilinx
 zyxel   ZyXEL Communications Corp.
+zarlink Zarlink Semiconductor
diff --git a/Documentation/powerpc/cpu_families.txt b/Documentation/powerpc/cpu_families.txt
new file mode 100644
index 000000000000..fc08e22feb1a
--- /dev/null
+++ b/Documentation/powerpc/cpu_families.txt
@@ -0,0 +1,221 @@
+CPU Families
+============
+This document tries to summarise some of the different cpu families that exist
+and are supported by arch/powerpc.
+Book3S (aka sPAPR)
+------------------
+ - Hash MMU
+ - Mix of 32 & 64 bit
+   +--------------+                 +----------------+
+   |  Old POWER   | --------------> | RS64 (threads) |
+   +--------------+                 +----------------+
+          |
+          |
+          v
+   +--------------+                 +----------------+      +------+
+   |     601      | --------------> |      603       | ---> | e300 |
+   +--------------+                 +----------------+      +------+
+          |                                 |
+          |                                 |
+          v                                 v
+   +--------------+                 +----------------+      +-------+
+   |     604      |                 |    750 (G3)    | ---> | 750CX |
+   +--------------+                 +----------------+      +-------+
+          |                                 |                   |
+          |                                 |                   |
+          v                                 v                   v
+   +--------------+                 +----------------+      +-------+
+   | 620 (64 bit) |                 |      7400      |      | 750CL |
+   +--------------+                 +----------------+      +-------+
+          |                                 |                   |
+          |                                 |                   |
+          v                                 v                   v
+   +--------------+                 +----------------+      +-------+
+   |  POWER3/630  |                 |      7410      |      | 750FX |
+   +--------------+                 +----------------+      +-------+
+          |                                 |
+          |                                 |
+          v                                 v
+   +--------------+                 +----------------+
+   |   POWER3+    |                 |      7450      |
+   +--------------+                 +----------------+
+          |                                 |
+          |                                 |
+          v                                 v
+   +--------------+                 +----------------+
+   |    POWER4    |                 |      7455      |
+   +--------------+                 +----------------+
+          |                                 |
+          |                                 |
+          v                                 v
+   +--------------+     +-------+   +----------------+
+   |   POWER4+    | --> |  970  |   |      7447      |
+   +--------------+     +-------+   +----------------+
+          |                 |               |
+          |                 |               |
+          v                 v               v
+   +--------------+     +-------+   +----------------+
+   |    POWER5    |     | 970FX |   |      7448      |
+   +--------------+     +-------+   +----------------+
+          |                 |               |
+          |                 |               |
+          v                 v               v
+   +--------------+     +-------+   +----------------+
+   |   POWER5+    |     | 970MP |   |      e600      |
+   +--------------+     +-------+   +----------------+
+          |
+          |
+          v
+   +--------------+
+   |   POWER5++   |
+   +--------------+
+          |
+          |
+          v
+   +--------------+       +-------+
+   |    POWER6    | <-?-> | Cell  |
+   +--------------+       +-------+
+          |
+          |
+          v
+   +--------------+
+   |    POWER7    |
+   +--------------+
+          |
+          |
+          v
+   +--------------+
+   |   POWER7+    |
+   +--------------+
+          |
+          |
+          v
+   +--------------+
+   |    POWER8    |
+   +--------------+
+   +---------------+
+   | PA6T (64 bit) |
+   +---------------+
+IBM BookE
+---------
+ - Software loaded TLB.
+ - All 32 bit
+   +--------------+
+   |     401      |
+   +--------------+
+          |
+          |
+          v
+   +--------------+
+   |     403      |
+   +--------------+
+          |
+          |
+          v
+   +--------------+
+   |     405      |
+   +--------------+
+          |
+          |
+          v
+   +--------------+
+   |     440      |
+   +--------------+
+          |
+          |
+          v
+   +--------------+     +----------------+
+   |     450      | --> |      BG/P      |
+   +--------------+     +----------------+
+          |
+          |
+          v
+   +--------------+
+   |     460      |
+   +--------------+
+          |
+          |
+          v
+   +--------------+
+   |     476      |
+   +--------------+
+Motorola/Freescale 8xx
+----------------------
+ - Software loaded with hardware assist.
+ - All 32 bit
+   +-------------+
+   | MPC8xx Core |
+   +-------------+
+Freescale BookE
+---------------
+ - Software loaded TLB.
+ - e6500 adds HW loaded indirect TLB entries.
+ - Mix of 32 & 64 bit
+   +--------------+
+   |     e200     |
+   +--------------+
+   +--------------------------------+
+   |              e500              |
+   +--------------------------------+
+                   |
+                   |
+                   v
+   +--------------------------------+
+   |             e500v2             |
+   +--------------------------------+
+                   |
+                   |
+                   v
+   +--------------------------------+
+   |        e500mc (Book3e)         |
+   +--------------------------------+
+                   |
+                   |
+                   v
+   +--------------------------------+
+   |          e5500 (64 bit)        |
+   +--------------------------------+
+                   |
+                   |
+                   v
+   +--------------------------------+
+   | e6500 (HW TLB) (Multithreaded) |
+   +--------------------------------+
+IBM A2 core
+-----------
+ - Book3E, software loaded TLB + HW loaded indirect TLB entries.
+ - 64 bit
+   +--------------+     +----------------+
+   |   A2 core    | --> |      WSP       |
+   +--------------+     +----------------+
+           |
+           |
+           v
+   +--------------+
+   |     BG/Q     |
+   +--------------+
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index e0998997943b..bd6dd6ed3a9f 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -453,6 +453,14 @@ config NODES_SHIFT
        default "4"
        depends on NEED_MULTIPLE_NODES
+config USE_PERCPU_NUMA_NODE_ID
+        def_bool y
+        depends on NUMA
+config HAVE_MEMORYLESS_NODES
+        def_bool y
+        depends on NUMA
 config ARCH_SELECT_MEMORY_MODEL
        def_bool y
        depends on PPC64
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index ce4c68a4a823..5687e299d0a5 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -113,8 +113,13 @@ else
 endif
 endif
-CFLAGS-$(CONFIG_PPC64)  := -mtraceback=no -mcall-aixdesc
+CFLAGS-$(CONFIG_PPC64)  := -mtraceback=no
-CFLAGS-$(CONFIG_PPC64)  += $(call cc-option,-mabi=elfv1)
+ifeq ($(CONFIG_CPU_LITTLE_ENDIAN),y)
+CFLAGS-$(CONFIG_PPC64)  += $(call cc-option,-mabi=elfv2,-mcall-aixdesc)
+AFLAGS-$(CONFIG_PPC64)  += $(call cc-option,-mabi=elfv2)
+else
+CFLAGS-$(CONFIG_PPC64)  += -mcall-aixdesc
+endif
 CFLAGS-$(CONFIG_PPC64)  += $(call cc-option,-mcmodel=medium,-mminimal-toc)
 CFLAGS-$(CONFIG_PPC64)  += $(call cc-option,-mno-pointers-to-nested-functions)
 CFLAGS-$(CONFIG_PPC32)  := -ffixed-r2 $(MULTIPLEWORD)
@@ -153,7 +158,7 @@ CFLAGS-$(CONFIG_TUNE_CELL) += $(call cc-option,-mtune=cell)
 asinstr := $(call as-instr,lis 9$(comma)foo@high,-DHAVE_AS_ATHIGH=1)
 KBUILD_CPPFLAGS += -Iarch/$(ARCH) $(asinstr)
-KBUILD_AFLAGS   += -Iarch/$(ARCH)
+KBUILD_AFLAGS   += -Iarch/$(ARCH) $(AFLAGS-y)
 KBUILD_CFLAGS   += -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y)
 CPP             = $(CC) -E $(KBUILD_CFLAGS)
@@ -161,6 +166,11 @@ CHECKFLAGS	+= -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)
 KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
+ifeq ($(CONFIG_476FPE_ERR46),y)
+        KBUILD_LDFLAGS_MODULE += --ppc476-workaround \
+                -T $(srctree)/arch/powerpc/platforms/44x/ppc476_modules.lds
+endif
 # No AltiVec or VSX instructions when building kernel
 KBUILD_CFLAGS += $(call cc-option,-mno-altivec)
 KBUILD_CFLAGS += $(call cc-option,-mno-vsx)
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index a1f8c7f1ec60..426dce7ae7c4 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -22,8 +22,14 @@ all: $(obj)/zImage
 BOOTCFLAGS    := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
                 -fno-strict-aliasing -Os -msoft-float -pipe \
                 -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
-                 -isystem $(shell $(CROSS32CC) -print-file-name=include) \
+                 -isystem $(shell $(CROSS32CC) -print-file-name=include)
-                 -mbig-endian
+ifdef CONFIG_PPC64_BOOT_WRAPPER
+BOOTCFLAGS      += -m64
+endif
+ifdef CONFIG_CPU_BIG_ENDIAN
+BOOTCFLAGS      += -mbig-endian
+endif
 BOOTAFLAGS      := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
 ifdef CONFIG_DEBUG_INFO
@@ -47,6 +53,7 @@ $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
+$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu=405
 $(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
@@ -86,6 +93,7 @@ src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
                                cuboot-taishan.c cuboot-katmai.c \
                                cuboot-warp.c cuboot-yosemite.c \
                                treeboot-iss4xx.c treeboot-currituck.c \
+                                treeboot-akebono.c \
                                simpleboot.c fixed-head.S virtex.c
 src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
 src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
@@ -99,6 +107,11 @@ src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
 src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
 src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
 src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
+src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
+src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+src-plat-$(CONFIG_PPC_CELLEB) += pseries-head.S
+src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S
 src-wlib := $(sort $(src-wlib-y))
 src-plat := $(sort $(src-plat-y))
@@ -137,7 +150,11 @@ $(addprefix $(obj)/,$(libfdt) $(libfdtheader)): $(obj)/%: $(srctree)/scripts/dtc
 $(obj)/empty.c:
        @touch $@
-$(obj)/zImage.lds $(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds: $(obj)/%: $(srctree)/$(src)/%.S
+$(obj)/zImage.lds: $(obj)/%: $(srctree)/$(src)/%.S
+        $(CROSS32CC) $(cpp_flags) -E -Wp,-MD,$(depfile) -P -Upowerpc \
+                -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
+$(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds : $(obj)/%: $(srctree)/$(src)/%.S
        @cp $< $@
 clean-files := $(zlib) $(zlibheader) $(zliblinuxheader) \
@@ -235,6 +252,7 @@ image-$(CONFIG_YOSEMITE)		+= cuImage.yosemite
 image-$(CONFIG_ISS4xx)                  += treeImage.iss4xx \
                                           treeImage.iss4xx-mpic
 image-$(CONFIG_CURRITUCK)                       += treeImage.currituck
+image-$(CONFIG_AKEBONO)                 += treeImage.akebono
 # Board ports in arch/powerpc/platform/8xx/Kconfig
 image-$(CONFIG_MPC86XADS)               += cuImage.mpc866ads
diff --git a/arch/powerpc/boot/addnote.c b/arch/powerpc/boot/addnote.c
index 349b5530d2c4..9d9f6f334d3c 100644
--- a/arch/powerpc/boot/addnote.c
+++ b/arch/powerpc/boot/addnote.c
@@ -6,6 +6,8 @@
 *
 * Copyright 2000 Paul Mackerras.
 *
+ * Adapted for 64 bit little endian images by Andrew Tauferner.
+ *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
@@ -55,36 +57,61 @@ unsigned int rpanote[N_RPA_DESCR] = {
 #define ROUNDUP(len)    (((len) + 3) & ~3)
-unsigned char buf[512];
+unsigned char buf[1024];
+#define ELFDATA2LSB     1
+#define ELFDATA2MSB     2
+static int e_data = ELFDATA2MSB;
+#define ELFCLASS32      1
+#define ELFCLASS64      2
+static int e_class = ELFCLASS32;
 #define GET_16BE(off)   ((buf[off] << 8) + (buf[(off)+1]))
-#define GET_32BE(off)   ((GET_16BE(off) << 16) + GET_16BE((off)+2))
+#define GET_32BE(off)   ((GET_16BE(off) << 16U) + GET_16BE((off)+2U))
+#define GET_64BE(off)   ((((unsigned long long)GET_32BE(off)) << 32ULL) + \
-#define PUT_16BE(off, v)        (buf[off] = ((v) >> 8) & 0xff, \
+                        ((unsigned long long)GET_32BE((off)+4ULL)))
-                                 buf[(off) + 1] = (v) & 0xff)
+#define PUT_16BE(off, v)(buf[off] = ((v) >> 8) & 0xff, \
-#define PUT_32BE(off, v)        (PUT_16BE((off), (v) >> 16), \
+                         buf[(off) + 1] = (v) & 0xff)
-                                 PUT_16BE((off) + 2, (v)))
+#define PUT_32BE(off, v)(PUT_16BE((off), (v) >> 16L), PUT_16BE((off) + 2, (v)))
+#define PUT_64BE(off, v)((PUT_32BE((off), (v) >> 32L), \
+                          PUT_32BE((off) + 4, (v))))
+#define GET_16LE(off)   ((buf[off]) + (buf[(off)+1] << 8))
+#define GET_32LE(off)   (GET_16LE(off) + (GET_16LE((off)+2U) << 16U))
+#define GET_64LE(off)   ((unsigned long long)GET_32LE(off) + \
+                        (((unsigned long long)GET_32LE((off)+4ULL)) << 32ULL))
+#define PUT_16LE(off, v) (buf[off] = (v) & 0xff, \
+                          buf[(off) + 1] = ((v) >> 8) & 0xff)
+#define PUT_32LE(off, v) (PUT_16LE((off), (v)), PUT_16LE((off) + 2, (v) >> 16L))
+#define PUT_64LE(off, v) (PUT_32LE((off), (v)), PUT_32LE((off) + 4, (v) >> 32L))
+#define GET_16(off)     (e_data == ELFDATA2MSB ? GET_16BE(off) : GET_16LE(off))
+#define GET_32(off)     (e_data == ELFDATA2MSB ? GET_32BE(off) : GET_32LE(off))
+#define GET_64(off)     (e_data == ELFDATA2MSB ? GET_64BE(off) : GET_64LE(off))
+#define PUT_16(off, v)  (e_data == ELFDATA2MSB ? PUT_16BE(off, v) : \
+                         PUT_16LE(off, v))
+#define PUT_32(off, v)  (e_data == ELFDATA2MSB ? PUT_32BE(off, v) : \
+                         PUT_32LE(off, v))
+#define PUT_64(off, v)  (e_data == ELFDATA2MSB ? PUT_64BE(off, v) : \
+                         PUT_64LE(off, v))
 /* Structure of an ELF file */
 #define E_IDENT         0       /* ELF header */
-#define E_PHOFF         28
+#define E_PHOFF         (e_class == ELFCLASS32 ? 28 : 32)
-#define E_PHENTSIZE     42
+#define E_PHENTSIZE     (e_class == ELFCLASS32 ? 42 : 54)
-#define E_PHNUM         44
+#define E_PHNUM         (e_class == ELFCLASS32 ? 44 : 56)
-#define E_HSIZE         52      /* size of ELF header */
+#define E_HSIZE         (e_class == ELFCLASS32 ? 52 : 64)
 #define EI_MAGIC        0       /* offsets in E_IDENT area */
 #define EI_CLASS        4
 #define EI_DATA         5
 #define PH_TYPE         0       /* ELF program header */
-#define PH_OFFSET       4
+#define PH_OFFSET       (e_class == ELFCLASS32 ? 4 : 8)
-#define PH_FILESZ       16
+#define PH_FILESZ       (e_class == ELFCLASS32 ? 16 : 32)
-#define PH_HSIZE        32      /* size of program header */
+#define PH_HSIZE        (e_class == ELFCLASS32 ? 32 : 56)
 #define PT_NOTE         4       /* Program header type = note */
-#define ELFCLASS32      1
-#define ELFDATA2MSB     2
 unsigned char elf_magic[4] = { 0x7f, 'E', 'L', 'F' };
@@ -92,8 +119,8 @@ int
 main(int ac, char **av)
 {
        int fd, n, i;
-        int ph, ps, np;
+        unsigned long ph, ps, np;
-        int nnote, nnote2, ns;
+        long nnote, nnote2, ns;
        if (ac != 2) {
                fprintf(stderr, "Usage: %s elf-file\n", av[0]);
@@ -114,26 +141,27 @@ main(int ac, char **av)
                exit(1);
        }
-        if (n < E_HSIZE || memcmp(&buf[E_IDENT+EI_MAGIC], elf_magic, 4) != 0)
+        if (memcmp(&buf[E_IDENT+EI_MAGIC], elf_magic, 4) != 0)
+                goto notelf;
+        e_class = buf[E_IDENT+EI_CLASS];
+        if (e_class != ELFCLASS32 && e_class != ELFCLASS64)
+                goto notelf;
+        e_data = buf[E_IDENT+EI_DATA];
+        if (e_data != ELFDATA2MSB && e_data != ELFDATA2LSB)
+                goto notelf;
+        if (n < E_HSIZE)
                goto notelf;
-        if (buf[E_IDENT+EI_CLASS] != ELFCLASS32
+        ph = (e_class == ELFCLASS32 ? GET_32(E_PHOFF) : GET_64(E_PHOFF));
-            || buf[E_IDENT+EI_DATA] != ELFDATA2MSB) {
+        ps = GET_16(E_PHENTSIZE);
-                fprintf(stderr, "%s is not a big-endian 32-bit ELF image\n",
+        np = GET_16(E_PHNUM);
-                        av[1]);
-                exit(1);
-        }
-        ph = GET_32BE(E_PHOFF);
-        ps = GET_16BE(E_PHENTSIZE);
-        np = GET_16BE(E_PHNUM);
        if (ph < E_HSIZE || ps < PH_HSIZE || np < 1)
                goto notelf;
        if (ph + (np + 2) * ps + nnote + nnote2 > n)
                goto nospace;
        for (i = 0; i < np; ++i) {
-                if (GET_32BE(ph + PH_TYPE) == PT_NOTE) {
+                if (GET_32(ph + PH_TYPE) == PT_NOTE) {
                        fprintf(stderr, "%s already has a note entry\n",
                                av[1]);
                        exit(0);
@@ -148,15 +176,22 @@ main(int ac, char **av)
        /* fill in the program header entry */
        ns = ph + 2 * ps;
-        PUT_32BE(ph + PH_TYPE, PT_NOTE);
+        PUT_32(ph + PH_TYPE, PT_NOTE);
-        PUT_32BE(ph + PH_OFFSET, ns);
+        if (e_class == ELFCLASS32)
-        PUT_32BE(ph + PH_FILESZ, nnote);
+                PUT_32(ph + PH_OFFSET, ns);
+        else
+                PUT_64(ph + PH_OFFSET, ns);
+        if (e_class == ELFCLASS32)
+                PUT_32(ph + PH_FILESZ, nnote);
+        else
+                PUT_64(ph + PH_FILESZ, nnote);
        /* fill in the note area we point to */
        /* XXX we should probably make this a proper section */
-        PUT_32BE(ns, strlen(arch) + 1);
+        PUT_32(ns, strlen(arch) + 1);
-        PUT_32BE(ns + 4, N_DESCR * 4);
+        PUT_32(ns + 4, N_DESCR * 4);
-        PUT_32BE(ns + 8, 0x1275);
+        PUT_32(ns + 8, 0x1275);
        strcpy((char *) &buf[ns + 12], arch);
        ns += 12 + strlen(arch) + 1;
        for (i = 0; i < N_DESCR; ++i, ns += 4)
@@ -164,21 +199,28 @@ main(int ac, char **av)
        /* fill in the second program header entry and the RPA note area */
        ph += ps;
-        PUT_32BE(ph + PH_TYPE, PT_NOTE);
+        PUT_32(ph + PH_TYPE, PT_NOTE);
-        PUT_32BE(ph + PH_OFFSET, ns);
+        if (e_class == ELFCLASS32)
-        PUT_32BE(ph + PH_FILESZ, nnote2);
+                PUT_32(ph + PH_OFFSET, ns);
+        else
+                PUT_64(ph + PH_OFFSET, ns);
+        if (e_class == ELFCLASS32)
+                PUT_32(ph + PH_FILESZ, nnote);
+        else
+                PUT_64(ph + PH_FILESZ, nnote2);
        /* fill in the note area we point to */
-        PUT_32BE(ns, strlen(rpaname) + 1);
+        PUT_32(ns, strlen(rpaname) + 1);
-        PUT_32BE(ns + 4, sizeof(rpanote));
+        PUT_32(ns + 4, sizeof(rpanote));
-        PUT_32BE(ns + 8, 0x12759999);
+        PUT_32(ns + 8, 0x12759999);
        strcpy((char *) &buf[ns + 12], rpaname);
        ns += 12 + ROUNDUP(strlen(rpaname) + 1);
        for (i = 0; i < N_RPA_DESCR; ++i, ns += 4)
                PUT_32BE(ns, rpanote[i]);
        /* Update the number of program headers */
-        PUT_16BE(E_PHNUM, np + 2);
+        PUT_16(E_PHNUM, np + 2);
        /* write back */
        lseek(fd, (long) 0, SEEK_SET);
diff --git a/arch/powerpc/boot/crt0.S b/arch/powerpc/boot/crt0.S
index 0f7428a37efb..14de4f8778a7 100644
--- a/arch/powerpc/boot/crt0.S
+++ b/arch/powerpc/boot/crt0.S
@@ -1,17 +1,20 @@
 /*
 * Copyright (C) Paul Mackerras 1997.
 *
+ * Adapted for 64 bit LE PowerPC by Andrew Tauferner
+ *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
- * NOTE: this code runs in 32 bit mode, is position-independent,
- * and is packaged as ELF32.
 */
 #include "ppc_asm.h"
+RELA = 7
+RELACOUNT = 0x6ffffff9
        .text
        /* A procedure descriptor used when booting this as a COFF file.
         * When making COFF, this comes first in the link and we're
@@ -21,6 +24,20 @@
 _zimage_start_opd:
        .long   0x500000, 0, 0, 0
+#ifdef __powerpc64__
+.balign 8
+p_start:        .llong  _start
+p_etext:        .llong  _etext
+p_bss_start:    .llong  __bss_start
+p_end:          .llong  _end
+p_toc:          .llong  __toc_start + 0x8000 - p_base
+p_dyn:          .llong  __dynamic_start - p_base
+p_rela:         .llong  __rela_dyn_start - p_base
+p_prom:         .llong  0
+        .weak   _platform_stack_top
+p_pstack:       .llong  _platform_stack_top
+#else
 p_start:        .long   _start
 p_etext:        .long   _etext
 p_bss_start:    .long   __bss_start
@@ -28,6 +45,7 @@ p_end:		.long	_end
        .weak   _platform_stack_top
 p_pstack:       .long   _platform_stack_top
+#endif
        .weak   _zimage_start
        .globl  _zimage_start
@@ -38,6 +56,7 @@ _zimage_start_lib:
           and the address where we're running. */
        bl      .+4
 p_base: mflr    r10             /* r10 now points to runtime addr of p_base */
+#ifndef __powerpc64__
        /* grab the link address of the dynamic section in r11 */
        addis   r11,r10,(_GLOBAL_OFFSET_TABLE_-p_base)@ha
        lwz     r11,(_GLOBAL_OFFSET_TABLE_-p_base)@l(r11)
@@ -51,8 +70,6 @@ p_base:	mflr	r10		/* r10 now points to runtime addr of p_base */
        /* The dynamic section contains a series of tagged entries.
         * We need the RELA and RELACOUNT entries. */
-RELA = 7
-RELACOUNT = 0x6ffffff9
        li      r9,0
        li      r0,0
 9:      lwz     r8,0(r12)       /* get tag */
@@ -120,9 +137,164 @@ RELACOUNT = 0x6ffffff9
        li      r0,0
        stwu    r0,-16(r1)      /* establish a stack frame */
 6:
+#else /* __powerpc64__ */
+        /* Save the prom pointer at p_prom. */
+        std     r5,(p_prom-p_base)(r10)
+        /* Set r2 to the TOC. */
+        ld      r2,(p_toc-p_base)(r10)
+        add     r2,r2,r10
+        /* Grab the link address of the dynamic section in r11. */
+        ld      r11,-32768(r2)
+        cmpwi   r11,0
+        beq     3f              /* if not linked -pie then no dynamic section */
+        ld      r11,(p_dyn-p_base)(r10)
+        add     r11,r11,r10
+        ld      r9,(p_rela-p_base)(r10)
+        add     r9,r9,r10
+        li      r7,0
+        li      r8,0
+9:      ld      r6,0(r11)       /* get tag */
+        cmpdi   r6,0
+        beq     12f              /* end of list */
+        cmpdi   r6,RELA
+        bne     10f
+        ld      r7,8(r11)       /* get RELA pointer in r7 */
+        b       11f
+10:     addis   r6,r6,(-RELACOUNT)@ha
+        cmpdi   r6,RELACOUNT@l
+        bne     11f
+        ld      r8,8(r11)       /* get RELACOUNT value in r8 */
+11:     addi    r11,r11,16
+        b       9b
+12:
+        cmpdi   r7,0            /* check we have both RELA and RELACOUNT */
+        cmpdi   cr1,r8,0
+        beq     3f
+        beq     cr1,3f
+        /* Calcuate the runtime offset. */
+        subf    r7,r7,r9
+        /* Run through the list of relocations and process the
+         * R_PPC64_RELATIVE ones. */
+        mtctr   r8
+13:     ld      r0,8(r9)        /* ELF64_R_TYPE(reloc->r_info) */
+        cmpdi   r0,22           /* R_PPC64_RELATIVE */
+        bne     3f
+        ld      r6,0(r9)        /* reloc->r_offset */
+        ld      r0,16(r9)       /* reloc->r_addend */
+        add     r0,r0,r7
+        stdx    r0,r7,r6
+        addi    r9,r9,24
+        bdnz    13b
+        /* Do a cache flush for our text, in case the loader didn't */
+3:      ld      r9,p_start-p_base(r10)  /* note: these are relocated now */
+        ld      r8,p_etext-p_base(r10)
+4:      dcbf    r0,r9
+        icbi    r0,r9
+        addi    r9,r9,0x20
+        cmpld   cr0,r9,r8
+        blt     4b
+        sync
+        isync
+        /* Clear the BSS */
+        ld      r9,p_bss_start-p_base(r10)
+        ld      r8,p_end-p_base(r10)
+        li      r0,0
+5:      std     r0,0(r9)
+        addi    r9,r9,8
+        cmpld   cr0,r9,r8
+        blt     5b
+        /* Possibly set up a custom stack */
+        ld      r8,p_pstack-p_base(r10)
+        cmpdi   r8,0
+        beq     6f
+        ld      r1,0(r8)
+        li      r0,0
+        stdu    r0,-16(r1)      /* establish a stack frame */
+6:
+#endif  /* __powerpc64__ */
        /* Call platform_init() */
        bl      platform_init
        /* Call start */
        b       start
+#ifdef __powerpc64__
+#define PROM_FRAME_SIZE 512
+#define SAVE_GPR(n, base)       std     n,8*(n)(base)
+#define REST_GPR(n, base)       ld      n,8*(n)(base)
+#define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
+#define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
+#define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
+#define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
+#define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
+#define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
+#define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
+#define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
+/* prom handles the jump into and return from firmware.  The prom args pointer
+   is loaded in r3. */
+.globl prom
+prom:
+        mflr    r0
+        std     r0,16(r1)
+        stdu    r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
+        SAVE_GPR(2, r1)
+        SAVE_GPR(13, r1)
+        SAVE_8GPRS(14, r1)
+        SAVE_10GPRS(22, r1)
+        mfcr    r10
+        std     r10,8*32(r1)
+        mfmsr   r10
+        std     r10,8*33(r1)
+        /* remove MSR_LE from msr but keep MSR_SF */
+        mfmsr   r10
+        rldicr  r10,r10,0,62
+        mtsrr1  r10
+        /* Load FW address, set LR to label 1, and jump to FW */
+        bl      0f
+0:      mflr    r10
+        addi    r11,r10,(1f-0b)
+        mtlr    r11
+        ld      r10,(p_prom-0b)(r10)
+        mtsrr0  r10
+        rfid
+1:      /* Return from OF */
+        FIXUP_ENDIAN
+        /* Restore registers and return. */
+        rldicl  r1,r1,0,32
+        /* Restore the MSR (back to 64 bits) */
+        ld      r10,8*(33)(r1)
+        mtmsr   r10
+        isync
+        /* Restore other registers */
+        REST_GPR(2, r1)
+        REST_GPR(13, r1)
+        REST_8GPRS(14, r1)
+        REST_10GPRS(22, r1)
+        ld      r10,8*32(r1)
+        mtcr    r10
+        addi    r1,r1,PROM_FRAME_SIZE
+        ld      r0,16(r1)
+        mtlr    r0
+        blr
+#endif
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index cc73f7a95e26..bf8f4ede1928 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -15,6 +15,10 @@
                asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
                rval; \
        })
+#define mtdcrx(rn, val) \
+        ({      \
+                asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
+        })
 /* 440GP/440GX SDRAM controller DCRs */
 #define DCRN_SDRAM0_CFGADDR                             0x010
diff --git a/arch/powerpc/boot/dts/akebono.dts b/arch/powerpc/boot/dts/akebono.dts
new file mode 100644
index 000000000000..f92ecfed3d2f
--- /dev/null
+++ b/arch/powerpc/boot/dts/akebono.dts
@@ -0,0 +1,415 @@
+/*
+ * Device Tree Source for IBM Embedded PPC 476 Platform
+ *
+ * Copyright © 2013 Tony Breeds IBM Corporation
+ * Copyright © 2013 Alistair Popple IBM Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+/memreserve/ 0x01f00000 0x00100000;     // spin table
+/ {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        model = "ibm,akebono";
+        compatible = "ibm,akebono", "ibm,476gtr";
+        dcr-parent = <&{/cpus/cpu@0}>;
+        aliases {
+                serial0 = &UART0;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        model = "PowerPC,476";
+                        reg = <0>;
+                        clock-frequency = <1600000000>; // 1.6 GHz
+                        timebase-frequency = <100000000>; // 100Mhz
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                        status = "ok";
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        model = "PowerPC,476";
+                        reg = <1>;
+                        clock-frequency = <1600000000>; // 1.6 GHz
+                        timebase-frequency = <100000000>; // 100Mhz
+                        i-cache-line-size = <32>;
+                        d-cache-line-size = <32>;
+                        i-cache-size = <32768>;
+                        d-cache-size = <32768>;
+                        dcr-controller;
+                        dcr-access-method = "native";
+                        status = "disabled";
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x01f00000>;
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
+        };
+        MPIC: interrupt-controller {
+                compatible = "chrp,open-pic";
+                interrupt-controller;
+                dcr-reg = <0xffc00000 0x00040000>;
+                #address-cells = <0>;
+                #size-cells = <0>;
+                #interrupt-cells = <2>;
+                single-cpu-affinity;
+        };
+        plb {
+                compatible = "ibm,plb6";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                clock-frequency = <200000000>; // 200Mhz
+                HSTA0: hsta@310000e0000 {
+                        compatible = "ibm,476gtr-hsta-msi", "ibm,hsta-msi";
+                        reg = <0x310 0x000e0000 0x0 0xf0>;
+                        interrupt-parent = <&MPIC>;
+                        interrupts = <108 0
+                                      109 0
+                                      110 0
+                                      111 0
+                                      112 0
+                                      113 0
+                                      114 0
+                                      115 0
+                                      116 0
+                                      117 0
+                                      118 0
+                                      119 0
+                                      120 0
+                                      121 0
+                                      122 0
+                                      123 0>;
+                };
+                MAL0: mcmal {
+                        compatible = "ibm,mcmal-476gtr", "ibm,mcmal2";
+                        dcr-reg = <0xc0000000 0x062>;
+                        num-tx-chans = <1>;
+                        num-rx-chans = <1>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&MPIC>;
+                        interrupts = <  /*TXEOB*/ 77 0x4
+                                        /*RXEOB*/ 78 0x4
+                                        /*SERR*/  76 0x4
+                                        /*TXDE*/  79 0x4
+                                        /*RXDE*/  80 0x4>;
+                };
+                SATA0: sata@30000010000 {
+                        compatible = "ibm,476gtr-ahci";
+                        reg = <0x300 0x00010000 0x0 0x10000>;
+                        interrupt-parent = <&MPIC>;
+                        interrupts = <93 2>;
+                };
+                EHCI0: ehci@30010000000 {
+                        compatible = "ibm,476gtr-ehci", "generic-ehci";
+                        reg = <0x300 0x10000000 0x0 0x10000>;
+                        interrupt-parent = <&MPIC>;
+                        interrupts = <85 2>;
+                };
+                SD0: sd@30000000000 {
+                        compatible = "ibm,476gtr-sdhci", "generic-sdhci";
+                        reg = <0x300 0x00000000 0x0 0x10000>;
+                        interrupts = <91 2>;
+                        interrupt-parent = <&MPIC>;
+                };
+                OHCI0: ohci@30010010000 {
+                        compatible = "ibm,476gtr-ohci", "generic-ohci";
+                        reg = <0x300 0x10010000 0x0 0x10000>;
+                        interrupt-parent = <&MPIC>;
+                        interrupts = <89 1>;
+                        };
+                OHCI1: ohci@30010020000 {
+                        compatible = "ibm,476gtr-ohci", "generic-ohci";
+                        reg = <0x300 0x10020000 0x0 0x10000>;
+                        interrupt-parent = <&MPIC>;
+                        interrupts = <88 1>;
+                        };
+                POB0: opb {
+                        compatible = "ibm,opb-4xx", "ibm,opb";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        /* Wish there was a nicer way of specifying a full
+                         * 32-bit range
+                         */
+                        ranges = <0x00000000 0x0000033f 0x00000000 0x80000000
+                                  0x80000000 0x0000033f 0x80000000 0x80000000>;
+                        clock-frequency = <100000000>;
+                        RGMII0: emac-rgmii-wol@50004 {
+                                compatible = "ibm,rgmii-wol-476gtr", "ibm,rgmii-wol";
+                                reg = <0x50004 0x00000008>;
+                                has-mdio;
+                        };
+                        EMAC0: ethernet@30000 {
+                                device_type = "network";
+                                compatible = "ibm,emac-476gtr", "ibm,emac4sync";
+                                interrupt-parent = <&EMAC0>;
+                                interrupts = <0x0 0x1>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = </*Status*/ 0x0 &MPIC 81 0x4
+                                                 /*Wake*/   0x1 &MPIC 82 0x4>;
+                                reg = <0x30000 0x78>;
+                                /* local-mac-address will normally be added by
+                                 * the wrapper. If your device doesn't support
+                                 * passing data to the wrapper (in the form
+                                 * local-mac-addr=<hwaddr>) then you will need
+                                 * to set it manually here. */
+                                //local-mac-address = [000000000000];
+                                mal-device = <&MAL0>;
+                                mal-tx-channel = <0>;
+                                mal-rx-channel = <0>;
+                                cell-index = <0>;
+                                max-frame-size = <9000>;
+                                rx-fifo-size = <4096>;
+                                tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                phy-mode = "rgmii";
+                                phy-map = <0x00000000>;
+                                rgmii-wol-device = <&RGMII0>;
+                                has-inverted-stacr-oc;
+                                has-new-stacr-staopc;
+                        };
+                        UART0: serial@10000 {
+                                device_type = "serial";
+                                compatible = "ns16750", "ns16550";
+                                reg = <0x10000 0x00000008>;
+                                virtual-reg = <0xe8010000>;
+                                clock-frequency = <1851851>;
+                                current-speed = <38400>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <39 2>;
+                        };
+                        IIC0: i2c@00000000 {
+                                compatible = "ibm,iic-476gtr", "ibm,iic";
+                                reg = <0x0 0x00000020>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <37 2>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rtc@68 {
+                                        compatible = "stm,m41t80", "m41st85";
+                                        reg = <0x68>;
+                                };
+                        };
+                        IIC1: i2c@00000100 {
+                                compatible = "ibm,iic-476gtr", "ibm,iic";
+                                reg = <0x100 0x00000020>;
+                                interrupt-parent = <&MPIC>;
+                                interrupts = <38 2>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                avr@58 {
+                                        compatible = "ibm,akebono-avr";
+                                        reg = <0x58>;
+                                };
+                        };
+                        FPGA0: fpga@ebc00000 {
+                                compatible = "ibm,akebono-fpga";
+                                reg = <0xebc00000 0x8>;
+                        };
+                };
+                PCIE0: pciex@10100000000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
+                        primary;
+                        port = <0x0>; /* port number */
+                        reg = <0x00000101 0x00000000 0x0 0x10000000            /* Config space access */
+                               0x00000100 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
+                        dcr-reg = <0xc0 0x20>;
+//                                pci_space  < pci_addr          > < cpu_addr          > < size       >
+                        ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
+                                  0x01000000 0x0        0x0        0x00000140 0x0        0x0 0x00010000>;
+                        /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
+                         * PCI devices must be able to write to the HSTA module.
+                         */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
+                        /* This drives busses 0 to 0xf */
+                        bus-range = <0x0 0xf>;
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
+                                0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
+                                0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
+                                0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
+                };
+                PCIE1: pciex@20100000000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
+                        primary;
+                        port = <0x1>; /* port number */
+                        reg = <0x00000201 0x00000000 0x0 0x10000000            /* Config space access */
+                               0x00000200 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
+                        dcr-reg = <0x100 0x20>;
+//                                pci_space  < pci_addr          > < cpu_addr          > < size       >
+                        ranges = <0x02000000 0x00000000 0x80000000 0x00000210 0x80000000 0x0 0x80000000
+                                  0x01000000 0x0        0x0        0x00000240 0x0        0x0 0x00010000>;
+                        /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
+                         * PCI devices must be able to write to the HSTA module.
+                         */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
+                        /* This drives busses 0 to 0xf */
+                        bus-range = <0x0 0xf>;
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
+                                0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
+                                0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
+                                0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
+                };
+                PCIE2: pciex@18100000000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
+                        primary;
+                        port = <0x2>; /* port number */
+                        reg = <0x00000181 0x00000000 0x0 0x10000000            /* Config space access */
+                               0x00000180 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
+                        dcr-reg = <0xe0 0x20>;
+//                                pci_space  < pci_addr          > < cpu_addr          > < size       >
+                        ranges = <0x02000000 0x00000000 0x80000000 0x00000190 0x80000000 0x0 0x80000000
+                                  0x01000000 0x0        0x0        0x000001c0 0x0        0x0 0x00010000>;
+                        /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
+                         * PCI devices must be able to write to the HSTA module.
+                         */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
+                        /* This drives busses 0 to 0xf */
+                        bus-range = <0x0 0xf>;
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
+                                0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
+                                0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
+                                0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
+                };
+                PCIE3: pciex@28100000000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
+                        primary;
+                        port = <0x3>; /* port number */
+                        reg = <0x00000281 0x00000000 0x0 0x10000000            /* Config space access */
+                               0x00000280 0x00000000 0x0 0x00001000>;   /* UTL Registers space access */
+                        dcr-reg = <0x120 0x20>;
+//                                pci_space  < pci_addr          > < cpu_addr          > < size       >
+                        ranges = <0x02000000 0x00000000 0x80000000 0x00000290 0x80000000 0x0 0x80000000
+                                  0x01000000 0x0        0x0        0x000002c0 0x0        0x0 0x00010000>;
+                        /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
+                         * PCI devices must be able to write to the HSTA module.
+                         */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
+                        /* This drives busses 0 to 0xf */
+                        bus-range = <0x0 0xf>;
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x0 0x0 0x0 0x1 &MPIC 69 0x2 /* int A */
+                                0x0 0x0 0x0 0x2 &MPIC 70 0x2 /* int B */
+                                0x0 0x0 0x0 0x3 &MPIC 71 0x2 /* int C */
+                                0x0 0x0 0x0 0x4 &MPIC 72 0x2 /* int D */>;
+                };
+        };
+        chosen {
+                linux,stdout-path = &UART0;
+        };
+};
diff --git a/arch/powerpc/boot/dts/b4860emu.dts b/arch/powerpc/boot/dts/b4860emu.dts
index 7290021f2dfc..85646b4f96e1 100644
--- a/arch/powerpc/boot/dts/b4860emu.dts
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -61,21 +61,25 @@
                        device_type = "cpu";
                        reg = <0 1>;
                        next-level-cache = <&L2>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu1: PowerPC,e6500@2 {
                        device_type = "cpu";
                        reg = <2 3>;
                        next-level-cache = <&L2>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu2: PowerPC,e6500@4 {
                        device_type = "cpu";
                        reg = <4 5>;
                        next-level-cache = <&L2>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu3: PowerPC,e6500@6 {
                        device_type = "cpu";
                        reg = <6 7>;
                        next-level-cache = <&L2>;
+                        fsl,portid-mapping = <0x80000000>;
                };
        };
 };
@@ -157,7 +161,7 @@
        };
        corenet-cf@18000 {
-                compatible = "fsl,b4-corenet-cf";
+                compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
                reg = <0x18000 0x1000>;
                interrupts = <16 2 1 0>;
                fsl,ccf-num-csdids = <32>;
@@ -167,6 +171,7 @@
        iommu@20000 {
                compatible = "fsl,pamu-v1.0", "fsl,pamu";
                reg = <0x20000 0x4000>;
+                fsl,portid-mapping = <0x8000>;
                #address-cells = <1>;
                #size-cells = <1>;
                interrupts = <
diff --git a/arch/powerpc/boot/dts/bsc9132qds.dts b/arch/powerpc/boot/dts/bsc9132qds.dts
new file mode 100644
index 000000000000..6cab1062bc74
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9132qds.dts
@@ -0,0 +1,35 @@
+/*
+ * BSC9132 QDS Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/include/ "fsl/bsc9132si-pre.dtsi"
+/ {
+        model = "fsl,bsc9132qds";
+        compatible = "fsl,bsc9132qds";
+        memory {
+                device_type = "memory";
+        };
+        ifc: ifc@ff71e000 {
+                /* NOR, NAND Flash on board */
+                ranges = <0x0 0x0 0x0 0x88000000 0x08000000
+                          0x1 0x0 0x0 0xff800000 0x00010000>;
+                reg = <0x0 0xff71e000 0x0 0x2000>;
+        };
+        soc: soc@ff700000 {
+                ranges = <0x0 0x0 0xff700000 0x100000>;
+        };
+};
+/include/ "bsc9132qds.dtsi"
+/include/ "fsl/bsc9132si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/bsc9132qds.dtsi b/arch/powerpc/boot/dts/bsc9132qds.dtsi
new file mode 100644
index 000000000000..af8e88830221
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9132qds.dtsi
@@ -0,0 +1,101 @@
+/*
+ * BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&ifc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x8000000>;
+                bank-width = <2>;
+                device-width = <1>;
+        };
+        nand@1,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,ifc-nand";
+                reg = <0x1 0x0 0x4000>;
+        };
+};
+&soc {
+        spi@7000 {
+                flash@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "spansion,s25sl12801";
+                        reg = <0>;
+                        spi-max-frequency = <30000000>;
+                };
+        };
+        i2c@3000 {
+                fpga: fpga@66 {
+                        compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
+                        reg = <0x66>;
+                };
+        };
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+        mdio@24000 {
+                phy0: ethernet-phy@0 {
+                        reg = <0x0>;
+                };
+                phy1: ethernet-phy@1 {
+                        reg = <0x1>;
+                };
+                tbi0: tbi-phy@11 {
+                        reg = <0x1f>;
+                        device_type = "tbi-phy";
+                };
+        };
+        enet0: ethernet@b0000 {
+                phy-handle = <&phy0>;
+                tbi-handle = <&tbi0>;
+                phy-connection-type = "sgmii";
+        };
+        enet1: ethernet@b1000 {
+                phy-handle = <&phy1>;
+                tbi-handle = <&tbi0>;
+                phy-connection-type = "sgmii";
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 60566f9927be..d67894459ac8 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -76,10 +76,6 @@
                compatible = "fsl,b4420-l3-cache-controller", "cache";
        };
-        corenet-cf@18000 {
-                compatible = "fsl,b4420-corenet-cf";
-        };
        guts: global-utilities@e0000 {
                compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
        };
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 2419731c2c54..338af7e39dd9 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -66,12 +66,14 @@
                        reg = <0 1>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu1: PowerPC,e6500@2 {
                        device_type = "cpu";
                        reg = <2 3>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
+                        fsl,portid-mapping = <0x80000000>;
                };
        };
 };
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index cbc354b05117..582381dba1d7 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -120,10 +120,6 @@
                compatible = "fsl,b4860-l3-cache-controller", "cache";
        };
-        corenet-cf@18000 {
-                compatible = "fsl,b4860-corenet-cf";
-        };
        guts: global-utilities@e0000 {
                compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
        };
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 142ac862cacf..1948f73fd26b 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -66,24 +66,28 @@
                        reg = <0 1>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu1: PowerPC,e6500@2 {
                        device_type = "cpu";
                        reg = <2 3>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu2: PowerPC,e6500@4 {
                        device_type = "cpu";
                        reg = <4 5>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu3: PowerPC,e6500@6 {
                        device_type = "cpu";
                        reg = <6 7>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
+                        fsl,portid-mapping = <0x80000000>;
                };
        };
 };
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 4f6e48277c46..1a54ba71f685 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -158,7 +158,7 @@
        };
        corenet-cf@18000 {
-                compatible = "fsl,b4-corenet-cf";
+                compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
                reg = <0x18000 0x1000>;
                interrupts = <16 2 1 0>;
                fsl,ccf-num-csdids = <32>;
@@ -168,6 +168,7 @@
        iommu@20000 {
                compatible =  "fsl,pamu-v1.0", "fsl,pamu";
                reg = <0x20000 0x4000>;
+                fsl,portid-mapping = <0x8000>;
                #address-cells = <1>;
                #size-cells = <1>;
                interrupts = <
diff --git a/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi b/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi
new file mode 100644
index 000000000000..c72307198140
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi
@@ -0,0 +1,185 @@
+/*
+ * BSC9132 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&ifc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,ifc", "simple-bus";
+        /* FIXME: Test whether interrupts are split */
+        interrupts = <16 2 0 0 20 2 0 0>;
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,bsc9132-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <12>;
+        };
+        ecm@1000 {
+                compatible = "fsl,bsc9132-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+        memory-controller@2000 {
+                compatible = "fsl,bsc9132-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <16 2 1 8>;
+        };
+/include/ "pq3-i2c-0.dtsi"
+        i2c@3000 {
+                interrupts = <17 2 0 0>;
+        };
+/include/ "pq3-i2c-1.dtsi"
+        i2c@3100 {
+                interrupts = <17 2 0 0>;
+        };
+/include/ "pq3-duart-0.dtsi"
+        serial0: serial@4500 {
+                interrupts = <18 2 0 0>;
+        };
+        serial1: serial@4600 {
+                interrupts = <18 2 0 0 >;
+        };
+/include/ "pq3-espi-0.dtsi"
+        spi0: spi@7000 {
+                fsl,espi-num-chipselects = <1>;
+                interrupts = <22 0x2 0 0>;
+        };
+/include/ "pq3-gpio-0.dtsi"
+        gpio-controller@f000 {
+                interrupts = <19 0x2 0 0>;
+                };
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,bsc9132-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x40000>; // L2,256K
+                interrupts = <16 2 1 0>;
+        };
+/include/ "pq3-dma-0.dtsi"
+dma@21300 {
+        dma-channel@0 {
+                interrupts = <62 2 0 0>;
+        };
+        dma-channel@80 {
+                interrupts = <63 2 0 0>;
+        };
+        dma-channel@100 {
+                interrupts = <64 2 0 0>;
+        };
+        dma-channel@180 {
+                interrupts = <65 2 0 0>;
+        };
+};
+/include/ "pq3-usb2-dr-0.dtsi"
+usb@22000 {
+        compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
+        interrupts = <40 0x2 0 0>;
+};
+/include/ "pq3-esdhc-0.dtsi"
+        sdhc@2e000 {
+                fsl,sdhci-auto-cmd12;
+                interrupts = <41 0x2 0 0>;
+        };
+/include/ "pq3-sec4.4-0.dtsi"
+crypto@30000 {
+        interrupts       = <57 2 0 0>;
+        sec_jr0: jr@1000 {
+                interrupts       = <58 2 0 0>;
+        };
+        sec_jr1: jr@2000 {
+                interrupts       = <59 2 0 0>;
+        };
+        sec_jr2: jr@3000 {
+                interrupts       = <60 2 0 0>;
+        };
+        sec_jr3: jr@4000 {
+                interrupts       = <61 2 0 0>;
+        };
+};
+/include/ "pq3-mpic.dtsi"
+/include/ "pq3-mpic-timer-B.dtsi"
+/include/ "pq3-etsec2-0.dtsi"
+enet0: ethernet@b0000 {
+        queue-group@b0000 {
+                fsl,rx-bit-map = <0xff>;
+                fsl,tx-bit-map = <0xff>;
+                interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
+        };
+};
+/include/ "pq3-etsec2-1.dtsi"
+enet1: ethernet@b1000 {
+        queue-group@b1000 {
+                fsl,rx-bit-map = <0xff>;
+                fsl,tx-bit-map = <0xff>;
+                interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
+        };
+};
+global-utilities@e0000 {
+                compatible = "fsl,bsc9132-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi b/arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi
new file mode 100644
index 000000000000..301a9dba5790
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi
@@ -0,0 +1,66 @@
+/*
+ * BSC9132 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/include/ "e500v2_power_isa.dtsi"
+/ {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                serial0 = &serial0;
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: PowerPC,e500v2@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+                cpu1: PowerPC,e500v2@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index e2987a33083c..5290df83ff30 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -246,7 +246,7 @@
        };
        corenet-cf@18000 {
-                compatible = "fsl,corenet-cf";
+                compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
                reg = <0x18000 0x1000>;
                interrupts = <16 2 1 31>;
                fsl,ccf-num-csdids = <32>;
@@ -262,6 +262,7 @@
                interrupts = <
                        24 2 0 0
                        16 2 1 30>;
+                fsl,portid-mapping = <0x0f000000>;
                pamu0: pamu@0 {
                        reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 22f3b14517de..b1ea147f2995 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -83,6 +83,7 @@
                        reg = <0>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
+                        fsl,portid-mapping = <0x80000000>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -92,6 +93,7 @@
                        reg = <1>;
                        clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x40000000>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -101,6 +103,7 @@
                        reg = <2>;
                        clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x20000000>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -110,6 +113,7 @@
                        reg = <3>;
                        clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x10000000>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;
                        };
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 7af6d45fd998..cd63cb1b1042 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -273,7 +273,7 @@
        };
        corenet-cf@18000 {
-                compatible = "fsl,corenet-cf";
+                compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
                reg = <0x18000 0x1000>;
                interrupts = <16 2 1 31>;
                fsl,ccf-num-csdids = <32>;
@@ -289,6 +289,7 @@
                interrupts = <
                        24 2 0 0
                        16 2 1 30>;
+                fsl,portid-mapping = <0x0f000000>;
                pamu0: pamu@0 {
                        reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index 468e8be8ac6f..dc5f4b362c24 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -84,6 +84,7 @@
                        reg = <0>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
+                        fsl,portid-mapping = <0x80000000>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -93,6 +94,7 @@
                        reg = <1>;
                        clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x40000000>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -102,6 +104,7 @@
                        reg = <2>;
                        clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x20000000>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -111,6 +114,7 @@
                        reg = <3>;
                        clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x10000000>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;
                        };
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 2415e1f1d3fa..12947ccddf25 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -281,7 +281,7 @@
        };
        corenet-cf@18000 {
-                compatible = "fsl,corenet-cf";
+                compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
                reg = <0x18000 0x1000>;
                interrupts = <16 2 1 31>;
                fsl,ccf-num-csdids = <32>;
@@ -297,6 +297,7 @@
                interrupts = <
                        24 2 0 0
                        16 2 1 30>;
+                fsl,portid-mapping = <0x00f80000>;
                pamu0: pamu@0 {
                        reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index 0040b5a5379e..38bde0958672 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -83,6 +83,7 @@
                        reg = <0>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
+                        fsl,portid-mapping = <0x80000000>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -92,6 +93,7 @@
                        reg = <1>;
                        clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x40000000>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -101,6 +103,7 @@
                        reg = <2>;
                        clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x20000000>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -110,6 +113,7 @@
                        reg = <3>;
                        clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x10000000>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -119,6 +123,7 @@
                        reg = <4>;
                        clocks = <&mux4>;
                        next-level-cache = <&L2_4>;
+                        fsl,portid-mapping = <0x08000000>;
                        L2_4: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -128,6 +133,7 @@
                        reg = <5>;
                        clocks = <&mux5>;
                        next-level-cache = <&L2_5>;
+                        fsl,portid-mapping = <0x04000000>;
                        L2_5: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -137,6 +143,7 @@
                        reg = <6>;
                        clocks = <&mux6>;
                        next-level-cache = <&L2_6>;
+                        fsl,portid-mapping = <0x02000000>;
                        L2_6: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -146,6 +153,7 @@
                        reg = <7>;
                        clocks = <&mux7>;
                        next-level-cache = <&L2_7>;
+                        fsl,portid-mapping = <0x01000000>;
                        L2_7: l2-cache {
                                next-level-cache = <&cpc>;
                        };
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 2985de4ad6be..4c4a2b0436b2 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -278,7 +278,7 @@
        };
        corenet-cf@18000 {
-                compatible = "fsl,corenet-cf";
+                compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
                reg = <0x18000 0x1000>;
                interrupts = <16 2 1 31>;
                fsl,ccf-num-csdids = <32>;
@@ -294,6 +294,7 @@
                interrupts = <
                        24 2 0 0
                        16 2 1 30>;
+                fsl,portid-mapping = <0x3c000000>;
                pamu0: pamu@0 {
                        reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index fe1a2e6613b4..1cc61e126e4c 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -90,6 +90,7 @@
                        reg = <0>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
+                        fsl,portid-mapping = <0x80000000>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -99,6 +100,7 @@
                        reg = <1>;
                        clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x40000000>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
                        };
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index 546a899efe20..67296fdd9698 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -233,7 +233,7 @@
        };
        corenet-cf@18000 {
-                compatible = "fsl,corenet-cf";
+                compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
                reg = <0x18000 0x1000>;
                interrupts = <16 2 1 31>;
                fsl,ccf-num-csdids = <32>;
@@ -248,6 +248,7 @@
                #size-cells = <1>;
                interrupts = <24 2 0 0
                              16 2 1 30>;
+                fsl,portid-mapping = <0x0f800000>;
                pamu0: pamu@0 {
                        reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
index 3674686687cb..b048a2be05a8 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -83,6 +83,7 @@
                        reg = <0>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
+                        fsl,portid-mapping = <0x80000000>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -92,6 +93,7 @@
                        reg = <1>;
                        clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x40000000>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -101,6 +103,7 @@
                        reg = <2>;
                        clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x20000000>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -110,6 +113,7 @@
                        reg = <3>;
                        clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x10000000>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;
                        };
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
new file mode 100644
index 000000000000..12e597eea3c8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -0,0 +1,430 @@
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&ifc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,ifc", "simple-bus";
+        interrupts = <25 2 0 0>;
+};
+&pci0 {
+        compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        interrupts = <20 2 0 0>;
+        fsl,iommu-parent = <&pamu0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <20 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 40 1 0 0
+                        0000 0 0 2 &mpic 1 1 0 0
+                        0000 0 0 3 &mpic 2 1 0 0
+                        0000 0 0 4 &mpic 3 1 0 0
+                        >;
+        };
+};
+&pci1 {
+        compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 0xff>;
+        interrupts = <21 2 0 0>;
+        fsl,iommu-parent = <&pamu0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <21 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 41 1 0 0
+                        0000 0 0 2 &mpic 5 1 0 0
+                        0000 0 0 3 &mpic 6 1 0 0
+                        0000 0 0 4 &mpic 7 1 0 0
+                        >;
+        };
+};
+&pci2 {
+        compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        interrupts = <22 2 0 0>;
+        fsl,iommu-parent = <&pamu0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <22 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 42 1 0 0
+                        0000 0 0 2 &mpic 9 1 0 0
+                        0000 0 0 3 &mpic 10 1 0 0
+                        0000 0 0 4 &mpic 11 1 0 0
+                        >;
+        };
+};
+&pci3 {
+        compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        interrupts = <23 2 0 0>;
+        fsl,iommu-parent = <&pamu0>;
+        pcie@0 {
+                reg = <0 0 0 0 0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                interrupts = <23 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 43 1 0 0
+                        0000 0 0 2 &mpic 0 1 0 0
+                        0000 0 0 3 &mpic 4 1 0 0
+                        0000 0 0 4 &mpic 8 1 0 0
+                        >;
+        };
+};
+&dcsr {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,dcsr", "simple-bus";
+        dcsr-epu@0 {
+                compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu";
+                interrupts = <52 2 0 0
+                              84 2 0 0
+                              85 2 0 0>;
+                reg = <0x0 0x1000>;
+        };
+        dcsr-npc {
+                compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc";
+                reg = <0x1000 0x1000 0x1002000 0x10000>;
+        };
+        dcsr-nxc@2000 {
+                compatible = "fsl,dcsr-nxc";
+                reg = <0x2000 0x1000>;
+        };
+        dcsr-corenet {
+                compatible = "fsl,dcsr-corenet";
+                reg = <0x8000 0x1000 0x1A000 0x1000>;
+        };
+        dcsr-dpaa@9000 {
+                compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa";
+                reg = <0x9000 0x1000>;
+        };
+        dcsr-ocn@11000 {
+                compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn";
+                reg = <0x11000 0x1000>;
+        };
+        dcsr-ddr@12000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr1>;
+                reg = <0x12000 0x1000>;
+        };
+        dcsr-nal@18000 {
+                compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal";
+                reg = <0x18000 0x1000>;
+        };
+        dcsr-rcpm@22000 {
+                compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm";
+                reg = <0x22000 0x1000>;
+        };
+        dcsr-snpc@30000 {
+                compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
+                reg = <0x30000 0x1000 0x1022000 0x10000>;
+        };
+        dcsr-snpc@31000 {
+                compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
+                reg = <0x31000 0x1000 0x1042000 0x10000>;
+        };
+        dcsr-cpu-sb-proxy@100000 {
+                compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu0>;
+                reg = <0x100000 0x1000 0x101000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@108000 {
+                compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu1>;
+                reg = <0x108000 0x1000 0x109000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@110000 {
+                compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu2>;
+                reg = <0x110000 0x1000 0x111000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@118000 {
+                compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu3>;
+                reg = <0x118000 0x1000 0x119000 0x1000>;
+        };
+};
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "simple-bus";
+        soc-sram-error {
+                compatible = "fsl,soc-sram-error";
+                interrupts = <16 2 1 29>;
+        };
+        corenet-law@0 {
+                compatible = "fsl,corenet-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <16>;
+        };
+        ddr1: memory-controller@8000 {
+                compatible = "fsl,qoriq-memory-controller-v5.0",
+                                "fsl,qoriq-memory-controller";
+                reg = <0x8000 0x1000>;
+                interrupts = <16 2 1 23>;
+        };
+        cpc: l3-cache-controller@10000 {
+                compatible = "fsl,t1040-l3-cache-controller", "cache";
+                reg = <0x10000 0x1000>;
+                interrupts = <16 2 1 27>;
+        };
+        corenet-cf@18000 {
+                compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
+                reg = <0x18000 0x1000>;
+                interrupts = <16 2 1 31>;
+                fsl,ccf-num-csdids = <32>;
+                fsl,ccf-num-snoopids = <32>;
+        };
+        iommu@20000 {
+                compatible = "fsl,pamu-v1.0", "fsl,pamu";
+                reg = <0x20000 0x1000>;
+                ranges = <0 0x20000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupts = <
+                        24 2 0 0
+                        16 2 1 30>;
+                pamu0: pamu@0 {
+                        reg = <0 0x1000>;
+                        fsl,primary-cache-geometry = <128 1>;
+                        fsl,secondary-cache-geometry = <16 2>;
+                };
+        };
+/include/ "qoriq-mpic.dtsi"
+        guts: global-utilities@e0000 {
+                compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0";
+                reg = <0xe0000 0xe00>;
+                fsl,has-rstcr;
+                fsl,liodn-bits = <12>;
+        };
+        clockgen: global-utilities@e1000 {
+                compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
+                ranges = <0x0 0xe1000 0x1000>;
+                reg = <0xe1000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                sysclk: sysclk {
+                        #clock-cells = <0>;
+                        compatible = "fsl,qoriq-sysclk-2.0";
+                        clock-output-names = "sysclk", "fixed-clock";
+                };
+                pll0: pll0@800 {
+                        #clock-cells = <1>;
+                        reg = <0x800 4>;
+                        compatible = "fsl,qoriq-core-pll-2.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+                };
+                pll1: pll1@820 {
+                        #clock-cells = <1>;
+                        reg = <0x820 4>;
+                        compatible = "fsl,qoriq-core-pll-2.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+                };
+                mux0: mux0@0 {
+                        #clock-cells = <0>;
+                        reg = <0x0 4>;
+                        compatible = "fsl,qoriq-core-mux-2.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                                 <&pll1 0>, <&pll1 1>, <&pll1 2>;
+                        clock-names = "pll0", "pll0-div2", "pll1-div4",
+                                "pll1", "pll1-div2", "pll1-div4";
+                        clock-output-names = "cmux0";
+                };
+                mux1: mux1@20 {
+                        #clock-cells = <0>;
+                        reg = <0x20 4>;
+                        compatible = "fsl,qoriq-core-mux-2.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                                 <&pll1 0>, <&pll1 1>, <&pll1 2>;
+                        clock-names = "pll0", "pll0-div2", "pll1-div4",
+                                "pll1", "pll1-div2", "pll1-div4";
+                        clock-output-names = "cmux1";
+                };
+                mux2: mux2@40 {
+                        #clock-cells = <0>;
+                        reg = <0x40 4>;
+                        compatible = "fsl,qoriq-core-mux-2.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                                 <&pll1 0>, <&pll1 1>, <&pll1 2>;
+                        clock-names = "pll0", "pll0-div2", "pll1-div4",
+                                "pll1", "pll1-div2", "pll1-div4";
+                        clock-output-names = "cmux2";
+                };
+                mux3: mux3@60 {
+                        #clock-cells = <0>;
+                        reg = <0x60 4>;
+                        compatible = "fsl,qoriq-core-mux-2.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                                 <&pll1 0>, <&pll1 1>, <&pll1 2>;
+                        clock-names = "pll0_0", "pll0_1", "pll0_2",
+                                "pll1_0", "pll1_1", "pll1_2";
+                        clock-output-names = "cmux3";
+                };
+        };
+        rcpm: global-utilities@e2000 {
+                compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.0";
+                reg = <0xe2000 0x1000>;
+        };
+        sfp: sfp@e8000 {
+                compatible = "fsl,t1040-sfp";
+                reg        = <0xe8000 0x1000>;
+        };
+        serdes: serdes@ea000 {
+                compatible = "fsl,t1040-serdes";
+                reg        = <0xea000 0x4000>;
+        };
+/include/ "elo3-dma-0.dtsi"
+/include/ "elo3-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+        spi@110000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+/include/ "qoriq-esdhc-0.dtsi"
+        sdhc@114000 {
+                compatible = "fsl,t1040-esdhc", "fsl,esdhc";
+                fsl,iommu-parent = <&pamu0>;
+                fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
+                sdhci,auto-cmd12;
+        };
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+                usb0: usb@210000 {
+                        compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph";
+                        fsl,iommu-parent = <&pamu0>;
+                        fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
+                        phy_type = "utmi";
+                        port0;
+                };
+/include/ "qoriq-usb2-dr-0.dtsi"
+                usb1: usb@211000 {
+                        compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
+                        fsl,iommu-parent = <&pamu0>;
+                        fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
+                        dr_mode = "host";
+                        phy_type = "utmi";
+                };
+        display@180000 {
+                compatible = "fsl,t1040-diu", "fsl,diu";
+                reg = <0x180000 1000>;
+                interrupts = <74 2 0 0>;
+        };
+/include/ "qoriq-sata2-0.dtsi"
+        sata@220000 {
+                fsl,iommu-parent = <&pamu0>;
+                fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
+        };
+/include/ "qoriq-sata2-1.dtsi"
+        sata@221000 {
+                fsl,iommu-parent = <&pamu0>;
+                fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
+        };
+/include/ "qoriq-sec5.0-0.dtsi"
+};
diff --git a/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
new file mode 100644
index 000000000000..319b74f29724
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
@@ -0,0 +1,37 @@
+/*
+ * T1042 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/include/ "t1040si-post.dtsi"
+/* Place holder for ethernet related device tree nodes */
diff --git a/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
new file mode 100644
index 000000000000..bbb7025ca9c2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
@@ -0,0 +1,104 @@
+/*
+ * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/dts-v1/;
+/include/ "e5500_power_isa.dtsi"
+/ {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                pci3 = &pci3;
+                usb0 = &usb0;
+                usb1 = &usb1;
+                sdhc = &sdhc;
+                crypto = &crypto;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: PowerPC,e5500@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        clocks = <&mux0>;
+                        next-level-cache = <&L2_1>;
+                        L2_1: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu1: PowerPC,e5500@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        clocks = <&mux1>;
+                        next-level-cache = <&L2_2>;
+                        L2_2: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu2: PowerPC,e5500@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        clocks = <&mux2>;
+                        next-level-cache = <&L2_3>;
+                        L2_3: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+                cpu3: PowerPC,e5500@3 {
+                        device_type = "cpu";
+                        reg = <3>;
+                        clocks = <&mux3>;
+                        next-level-cache = <&L2_4>;
+                        L2_4: l2-cache {
+                                next-level-cache = <&cpc>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index f99d74ff11b4..793669baa13e 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -343,7 +343,7 @@
        };
        corenet-cf@18000 {
-                compatible = "fsl,corenet-cf";
+                compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
                reg = <0x18000 0x1000>;
                interrupts = <16 2 1 31>;
                fsl,ccf-num-csdids = <32>;
@@ -353,6 +353,7 @@
        iommu@20000 {
                compatible = "fsl,pamu-v1.0", "fsl,pamu";
                reg = <0x20000 0x6000>;
+                fsl,portid-mapping = <0x8000>;
                interrupts = <
                        24 2 0 0
                        16 2 1 30>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index 0b8ccc5b4a46..d2f157edbe81 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -69,72 +69,84 @@
                        reg = <0 1>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu1: PowerPC,e6500@2 {
                        device_type = "cpu";
                        reg = <2 3>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu2: PowerPC,e6500@4 {
                        device_type = "cpu";
                        reg = <4 5>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu3: PowerPC,e6500@6 {
                        device_type = "cpu";
                        reg = <6 7>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu4: PowerPC,e6500@8 {
                        device_type = "cpu";
                        reg = <8 9>;
                        clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x40000000>;
                };
                cpu5: PowerPC,e6500@10 {
                        device_type = "cpu";
                        reg = <10 11>;
                        clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x40000000>;
                };
                cpu6: PowerPC,e6500@12 {
                        device_type = "cpu";
                        reg = <12 13>;
                        clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x40000000>;
                };
                cpu7: PowerPC,e6500@14 {
                        device_type = "cpu";
                        reg = <14 15>;
                        clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x40000000>;
                };
                cpu8: PowerPC,e6500@16 {
                        device_type = "cpu";
                        reg = <16 17>;
                        clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x20000000>;
                };
                cpu9: PowerPC,e6500@18 {
                        device_type = "cpu";
                        reg = <18 19>;
                        clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x20000000>;
                };
                cpu10: PowerPC,e6500@20 {
                        device_type = "cpu";
                        reg = <20 21>;
                        clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x20000000>;
                };
                cpu11: PowerPC,e6500@22 {
                        device_type = "cpu";
                        reg = <22 23>;
                        clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x20000000>;
                };
        };
 };
diff --git a/arch/powerpc/boot/dts/kmcoge4.dts b/arch/powerpc/boot/dts/kmcoge4.dts
new file mode 100644
index 000000000000..89b4119f3b19
--- /dev/null
+++ b/arch/powerpc/boot/dts/kmcoge4.dts
@@ -0,0 +1,152 @@
+/*
+ * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
+ *
+ * (C) Copyright 2014
+ * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/include/ "fsl/p2041si-pre.dtsi"
+/ {
+        model = "keymile,kmcoge4";
+        compatible = "keymile,kmcoge4", "keymile,kmp204x";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        memory {
+                device_type = "memory";
+        };
+        dcsr: dcsr@f00000000 {
+                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
+        };
+        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
+                spi@110000 {
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "spansion,s25fl256s1";
+                                reg = <0>;
+                                spi-max-frequency = <20000000>; /* input clock */
+                        };
+                        network_clock@1 {
+                                compatible = "zarlink,zl30343";
+                                reg = <1>;
+                                spi-max-frequency = <8000000>;
+                        };
+                        flash@2 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "micron,m25p32";
+                                reg = <2>;
+                                spi-max-frequency = <15000000>;
+                        };
+                };
+                i2c@119000 {
+                        status = "disabled";
+                };
+                i2c@119100 {
+                        status = "disabled";
+                };
+                usb0: usb@210000 {
+                        status = "disabled";
+                };
+                usb1: usb@211000 {
+                        status = "disabled";
+                };
+                sata@220000 {
+                        status = "disabled";
+                };
+                sata@221000 {
+                        status = "disabled";
+                };
+        };
+        rio: rapidio@ffe0c0000 {
+                status = "disabled";
+        };
+        lbc: localbus@ffe124000 {
+                reg = <0xf 0xfe124000 0 0x1000>;
+                ranges = <0 0 0xf 0xffa00000 0x00040000         /* LB 0 */
+                          1 0 0xf 0xfb000000 0x00010000         /* LB 1 */
+                          2 0 0xf 0xd0000000 0x10000000         /* LB 2 */
+                          3 0 0xf 0xe0000000 0x10000000>;       /* LB 3 */
+                nand@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0 0 0x40000>;
+                };
+                board-control@1,0 {
+                        compatible = "keymile,qriox";
+                        reg = <1 0 0x80>;
+                };
+                chassis-mgmt@3,0 {
+                        compatible = "keymile,bfticu";
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        reg = <3 0 0x100>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <6 1 0 0>;
+                };
+        };
+        pci0: pcie@ffe200000 {
+                reg = <0xf 0xfe200000 0 0x1000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+        pci1: pcie@ffe201000 {
+                status = "disabled";
+        };
+        pci2: pcie@ffe202000 {
+                reg = <0xf 0xfe202000 0 0x1000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+};
+/include/ "fsl/p2041si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/oca4080.dts b/arch/powerpc/boot/dts/oca4080.dts
new file mode 100644
index 000000000000..3d4c751d1608
--- /dev/null
+++ b/arch/powerpc/boot/dts/oca4080.dts
@@ -0,0 +1,118 @@
+/*
+ * OCA4080 Device Tree Source
+ *
+ * Copyright 2014 Prodrive Technologies B.V.
+ *
+ * Based on:
+ * P4080DS Device Tree Source
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/include/ "fsl/p4080si-pre.dtsi"
+/ {
+        model = "fsl,OCA4080";
+        compatible = "fsl,OCA4080";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        memory {
+                device_type = "memory";
+        };
+        dcsr: dcsr@f00000000 {
+                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
+        };
+        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
+                i2c@118000 {
+                        status = "disabled";
+                };
+                i2c@118100 {
+                        status = "disabled";
+                };
+                i2c@119000 {
+                        status = "disabled";
+                };
+                i2c@119100 {
+                        status = "disabled";
+                };
+                usb0: usb@210000 {
+                        status = "disabled";
+                };
+                usb1: usb@211000 {
+                        status = "disabled";
+                };
+        };
+        rio: rapidio@ffe0c0000 {
+                reg = <0xf 0xfe0c0000 0 0x11000>;
+                port1 {
+                        ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+                };
+        };
+        lbc: localbus@ffe124000 {
+                reg = <0xf 0xfe124000 0 0x1000>;
+                ranges = <0 0 0xf 0xef800000 0x800000>;
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x00800000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                };
+        };
+        pci0: pcie@ffe200000 {
+                status = "disabled";
+        };
+        pci1: pcie@ffe201000 {
+                status = "disabled";
+        };
+        pci2: pcie@ffe202000 {
+                status = "disabled";
+        };
+};
+/include/ "fsl/p4080si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
deleted file mode 100644
index beb6cb12e59d..000000000000
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * P1023 RDS Device Tree Source
- *
- * Copyright 2010-2011 Freescale Semiconductor Inc.
- *
- * Author: Roy Zang <tie-fei.zang@freescale.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/include/ "fsl/p1023si-pre.dtsi"
-/ {
-        model = "fsl,P1023";
-        compatible = "fsl,P1023RDS";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        interrupt-parent = <&mpic>;
-        memory {
-                device_type = "memory";
-        };
-        soc: soc@ff600000 {
-                ranges = <0x0 0x0 0xff600000 0x200000>;
-                i2c@3000 {
-                        rtc@68 {
-                                compatible = "dallas,ds1374";
-                                reg = <0x68>;
-                        };
-                };
-                spi@7000 {
-                        fsl_dataflash@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                compatible = "atmel,at45db081d";
-                                reg = <0>;
-                                spi-max-frequency = <40000000>; /* input clock */
-                                partition@u-boot {
-                                        /* 512KB for u-boot Bootloader Image */
-                                        label = "u-boot-spi";
-                                        reg = <0x00000000 0x00080000>;
-                                        read-only;
-                                };
-                                partition@dtb {
-                                        /* 512KB for DTB Image */
-                                        label = "dtb-spi";
-                                        reg = <0x00080000 0x00080000>;
-                                        read-only;
-                                };
-                        };
-                };
-                usb@22000 {
-                        dr_mode = "host";
-                        phy_type = "ulpi";
-                };
-        };
-        lbc: localbus@ff605000 {
-                reg = <0 0xff605000 0 0x1000>;
-                /* NOR Flash, BCSR */
-                ranges = <0x0 0x0 0x0 0xee000000 0x02000000
-                          0x1 0x0 0x0 0xe0000000 0x00008000>;
-                nor@0,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "cfi-flash";
-                        reg = <0x0 0x0 0x02000000>;
-                        bank-width = <2>;
-                        device-width = <1>;
-                        partition@0 {
-                                label = "ramdisk";
-                                reg = <0x00000000 0x01c00000>;
-                        };
-                        partition@1c00000 {
-                                label = "kernel";
-                                reg = <0x01c00000 0x002e0000>;
-                        };
-                        partiton@1ee0000 {
-                                label = "dtb";
-                                reg = <0x01ee0000 0x00020000>;
-                        };
-                        partition@1f00000 {
-                                label = "firmware";
-                                reg = <0x01f00000 0x00080000>;
-                                read-only;
-                        };
-                        partition@1f80000 {
-                                label = "u-boot";
-                                reg = <0x01f80000 0x00080000>;
-                                read-only;
-                        };
-                };
-                fpga@1,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,p1023rds-fpga";
-                        reg = <1 0 0x8000>;
-                        ranges = <0 1 0 0x8000>;
-                        bcsr@20 {
-                                compatible = "fsl,p1023rds-bcsr";
-                                reg = <0x20 0x20>;
-                        };
-                };
-        };
-        pci0: pcie@ff60a000 {
-                reg = <0 0xff60a000 0 0x1000>;
-                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
-                pcie@0 {
-                        /* IRQ[0:3] are pulled up on board, set to active-low */
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 0 1 0 0
-                                0000 0 0 2 &mpic 1 1 0 0
-                                0000 0 0 3 &mpic 2 1 0 0
-                                0000 0 0 4 &mpic 3 1 0 0
-                                >;
-                        ranges = <0x2000000 0x0 0xc0000000
-                                  0x2000000 0x0 0xc0000000
-                                  0x0 0x20000000
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
-        board_pci1: pci1: pcie@ff609000 {
-                reg = <0 0xff609000 0 0x1000>;
-                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
-                pcie@0 {
-                        /*
-                         * IRQ[4:6] only for PCIe, set to active-high,
-                         * IRQ[7] is pulled up on board, set to active-low
-                         */
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 4 2 0 0
-                                0000 0 0 2 &mpic 5 2 0 0
-                                0000 0 0 3 &mpic 6 2 0 0
-                                0000 0 0 4 &mpic 7 1 0 0
-                                >;
-                        ranges = <0x2000000 0x0 0xa0000000
-                                  0x2000000 0x0 0xa0000000
-                                  0x0 0x20000000
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
-        pci2: pcie@ff60b000 {
-                reg = <0 0xff60b000 0 0x1000>;
-                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
-                pcie@0 {
-                        /*
-                         * IRQ[8:10] are pulled up on board, set to active-low
-                         * IRQ[11] only for PCIe, set to active-high,
-                         */
-                        interrupt-map-mask = <0xf800 0 0 7>;
-                        interrupt-map = <
-                                /* IDSEL 0x0 */
-                                0000 0 0 1 &mpic 8 1 0 0
-                                0000 0 0 2 &mpic 9 1 0 0
-                                0000 0 0 3 &mpic 10 1 0 0
-                                0000 0 0 4 &mpic 11 2 0 0
-                                >;
-                        ranges = <0x2000000 0x0 0x80000000
-                                  0x2000000 0x0 0x80000000
-                                  0x0 0x20000000
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
-};
-/include/ "fsl/p1023si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t1040qds.dts b/arch/powerpc/boot/dts/t1040qds.dts
new file mode 100644
index 000000000000..973c29c2f56e
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T1040QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/include/ "fsl/t104xsi-pre.dtsi"
+/include/ "t104xqds.dtsi"
+/ {
+        model = "fsl,T1040QDS";
+        compatible = "fsl,T1040QDS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+};
+/include/ "fsl/t1040si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t1042qds.dts b/arch/powerpc/boot/dts/t1042qds.dts
new file mode 100644
index 000000000000..45bd03752154
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1042qds.dts
@@ -0,0 +1,46 @@
+/*
+ * T1042QDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/include/ "fsl/t104xsi-pre.dtsi"
+/include/ "t104xqds.dtsi"
+/ {
+        model = "fsl,T1042QDS";
+        compatible = "fsl,T1042QDS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+};
+/include/ "fsl/t1042si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t104xqds.dtsi b/arch/powerpc/boot/dts/t104xqds.dtsi
new file mode 100644
index 000000000000..234f4b596c5b
--- /dev/null
+++ b/arch/powerpc/boot/dts/t104xqds.dtsi
@@ -0,0 +1,166 @@
+/*
+ * T104xQDS Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/ {
+        model = "fsl,T1040QDS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        ifc: localbus@ffe124000 {
+                reg = <0xf 0xfe124000 0 0x2000>;
+                ranges = <0 0 0xf 0xe8000000 0x08000000
+                          2 0 0xf 0xff800000 0x00010000
+                          3 0 0xf 0xffdf0000 0x00008000>;
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x8000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+                };
+                nand@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,ifc-nand";
+                        reg = <0x2 0x0 0x10000>;
+                };
+                board-control@3,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,fpga-qixis";
+                        reg = <3 0 0x300>;
+                };
+        };
+        memory {
+                device_type = "memory";
+        };
+        dcsr: dcsr@f00000000 {
+                ranges = <0x00000000 0xf 0x00000000 0x01072000>;
+        };
+        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
+                spi@110000 {
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "micron,n25q128a11";
+                                reg = <0>;
+                                spi-max-frequency = <10000000>; /* input clock */
+                        };
+                };
+                i2c@118000 {
+                        pca9547@77 {
+                                compatible = "philips,pca9547";
+                                reg = <0x77>;
+                        };
+                        rtc@68 {
+                                compatible = "dallas,ds3232";
+                                reg = <0x68>;
+                                interrupts = <0x1 0x1 0 0>;
+                        };
+                };
+        };
+        pci0: pcie@ffe240000 {
+                reg = <0xf 0xfe240000 0 0x10000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
+                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+        pci1: pcie@ffe250000 {
+                reg = <0xf 0xfe250000 0 0x10000>;
+                ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
+                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+        pci2: pcie@ffe260000 {
+                reg = <0xf 0xfe260000 0 0x10000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+        pci3: pcie@ffe270000 {
+                reg = <0xf 0xfe270000 0 0x10000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/t4240emu.dts b/arch/powerpc/boot/dts/t4240emu.dts
index ee24ab335598..bc12127a03fb 100644
--- a/arch/powerpc/boot/dts/t4240emu.dts
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -60,63 +60,75 @@
                        device_type = "cpu";
                        reg = <0 1>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu1: PowerPC,e6500@2 {
                        device_type = "cpu";
                        reg = <2 3>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu2: PowerPC,e6500@4 {
                        device_type = "cpu";
                        reg = <4 5>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu3: PowerPC,e6500@6 {
                        device_type = "cpu";
                        reg = <6 7>;
                        next-level-cache = <&L2_1>;
+                        fsl,portid-mapping = <0x80000000>;
                };
                cpu4: PowerPC,e6500@8 {
                        device_type = "cpu";
                        reg = <8 9>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x40000000>;
                };
                cpu5: PowerPC,e6500@10 {
                        device_type = "cpu";
                        reg = <10 11>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x40000000>;
                };
                cpu6: PowerPC,e6500@12 {
                        device_type = "cpu";
                        reg = <12 13>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x40000000>;
                };
                cpu7: PowerPC,e6500@14 {
                        device_type = "cpu";
                        reg = <14 15>;
                        next-level-cache = <&L2_2>;
+                        fsl,portid-mapping = <0x40000000>;
                };
                cpu8: PowerPC,e6500@16 {
                        device_type = "cpu";
                        reg = <16 17>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x20000000>;
                };
                cpu9: PowerPC,e6500@18 {
                        device_type = "cpu";
                        reg = <18 19>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x20000000>;
                };
                cpu10: PowerPC,e6500@20 {
                        device_type = "cpu";
                        reg = <20 21>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x20000000>;
                };
                cpu11: PowerPC,e6500@22 {
                        device_type = "cpu";
                        reg = <22 23>;
                        next-level-cache = <&L2_3>;
+                        fsl,portid-mapping = <0x20000000>;
                };
        };
 };
@@ -213,7 +225,7 @@
        };
        corenet-cf@18000 {
-                compatible = "fsl,corenet-cf";
+                compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
                reg = <0x18000 0x1000>;
                interrupts = <16 2 1 31>;
                fsl,ccf-num-csdids = <32>;
@@ -223,6 +235,7 @@
        iommu@20000 {
                compatible = "fsl,pamu-v1.0", "fsl,pamu";
                reg = <0x20000 0x6000>;
+                fsl,portid-mapping = <0x8000>;
                interrupts = <
                        24 2 0 0
                        16 2 1 30>;
diff --git a/arch/powerpc/boot/elf_util.c b/arch/powerpc/boot/elf_util.c
index 1567a0c0f05c..316552dea4d8 100644
--- a/arch/powerpc/boot/elf_util.c
+++ b/arch/powerpc/boot/elf_util.c
@@ -26,7 +26,11 @@ int parse_elf64(void *hdr, struct elf_info *info)
              elf64->e_ident[EI_MAG2]  == ELFMAG2       &&
              elf64->e_ident[EI_MAG3]  == ELFMAG3       &&
              elf64->e_ident[EI_CLASS] == ELFCLASS64    &&
+#ifdef __LITTLE_ENDIAN__
+              elf64->e_ident[EI_DATA]  == ELFDATA2LSB   &&
+#else
              elf64->e_ident[EI_DATA]  == ELFDATA2MSB   &&
+#endif
              (elf64->e_type            == ET_EXEC ||
               elf64->e_type            == ET_DYN)      &&
              elf64->e_machine         == EM_PPC64))
diff --git a/arch/powerpc/boot/of.c b/arch/powerpc/boot/of.c
index 62e2f43ec1df..7ca910cb2fc6 100644
--- a/arch/powerpc/boot/of.c
+++ b/arch/powerpc/boot/of.c
@@ -40,8 +40,8 @@ static void *of_try_claim(unsigned long size)
 #ifdef DEBUG
                printf("    trying: 0x%08lx\n\r", claim_base);
 #endif
-                addr = (unsigned long)of_claim(claim_base, size, 0);
+                addr = (unsigned long) of_claim(claim_base, size, 0);
-                if ((void *)addr != (void *)-1)
+                if (addr != PROM_ERROR)
                        break;
        }
        if (addr == 0)
diff --git a/arch/powerpc/boot/of.h b/arch/powerpc/boot/of.h
index e4c68f7391c5..c8c1750aba0c 100644
--- a/arch/powerpc/boot/of.h
+++ b/arch/powerpc/boot/of.h
@@ -1,12 +1,15 @@
 #ifndef _PPC_BOOT_OF_H_
 #define _PPC_BOOT_OF_H_
+#include "swab.h"
 typedef void *phandle;
-typedef void *ihandle;
+typedef u32 ihandle;
 void of_init(void *promptr);
 int of_call_prom(const char *service, int nargs, int nret, ...);
-void *of_claim(unsigned long virt, unsigned long size, unsigned long align);
+unsigned int of_claim(unsigned long virt, unsigned long size,
+        unsigned long align);
 void *of_vmlinux_alloc(unsigned long size);
 void of_exit(void);
 void *of_finddevice(const char *name);
@@ -18,4 +21,16 @@ int of_setprop(const void *phandle, const char *name, const void *buf,
 /* Console functions */
 void of_console_init(void);
+typedef u32                     __be32;
+#ifdef __LITTLE_ENDIAN__
+#define cpu_to_be32(x) swab32(x)
+#define be32_to_cpu(x) swab32(x)
+#else
+#define cpu_to_be32(x) (x)
+#define be32_to_cpu(x) (x)
+#endif
+#define PROM_ERROR (-1u)
 #endif /* _PPC_BOOT_OF_H_ */
diff --git a/arch/powerpc/boot/ofconsole.c b/arch/powerpc/boot/ofconsole.c
index ce0e02424453..8b754702460a 100644
--- a/arch/powerpc/boot/ofconsole.c
+++ b/arch/powerpc/boot/ofconsole.c
@@ -18,7 +18,7 @@
 #include "of.h"
-static void *of_stdout_handle;
+static unsigned int of_stdout_handle;
 static int of_console_open(void)
 {
@@ -27,8 +27,10 @@ static int of_console_open(void)
        if (((devp = of_finddevice("/chosen")) != NULL)
            && (of_getprop(devp, "stdout", &of_stdout_handle,
                           sizeof(of_stdout_handle))
-                == sizeof(of_stdout_handle)))
+                == sizeof(of_stdout_handle))) {
+                of_stdout_handle = be32_to_cpu(of_stdout_handle);
                return 0;
+        }
        return -1;
 }
diff --git a/arch/powerpc/boot/oflib.c b/arch/powerpc/boot/oflib.c
index b0ec9cf3eaaf..46c98a47d949 100644
--- a/arch/powerpc/boot/oflib.c
+++ b/arch/powerpc/boot/oflib.c
@@ -16,74 +16,83 @@
 #include "of.h"
+typedef u32 prom_arg_t;
+/* The following structure is used to communicate with open firmware.
+ * All arguments in and out are in big endian format. */
+struct prom_args {
+        __be32 service; /* Address of service name string. */
+        __be32 nargs;   /* Number of input arguments. */
+        __be32 nret;    /* Number of output arguments. */
+        __be32 args[10];        /* Input/output arguments. */
+};
+#ifdef __powerpc64__
+extern int prom(void *);
+#else
 static int (*prom) (void *);
+#endif
 void of_init(void *promptr)
 {
+#ifndef __powerpc64__
        prom = (int (*)(void *))promptr;
+#endif
 }
+#define ADDR(x)         (u32)(unsigned long)(x)
 int of_call_prom(const char *service, int nargs, int nret, ...)
 {
        int i;
-        struct prom_args {
+        struct prom_args args;
-                const char *service;
-                int nargs;
-                int nret;
-                unsigned int args[12];
-        } args;
        va_list list;
-        args.service = service;
+        args.service = cpu_to_be32(ADDR(service));
-        args.nargs = nargs;
+        args.nargs = cpu_to_be32(nargs);
-        args.nret = nret;
+        args.nret = cpu_to_be32(nret);
        va_start(list, nret);
        for (i = 0; i < nargs; i++)
-                args.args[i] = va_arg(list, unsigned int);
+                args.args[i] = cpu_to_be32(va_arg(list, prom_arg_t));
        va_end(list);
        for (i = 0; i < nret; i++)
                args.args[nargs+i] = 0;
        if (prom(&args) < 0)
-                return -1;
+                return PROM_ERROR;
-        return (nret > 0)? args.args[nargs]: 0;
+        return (nret > 0) ? be32_to_cpu(args.args[nargs]) : 0;
 }
 static int of_call_prom_ret(const char *service, int nargs, int nret,
-                            unsigned int *rets, ...)
+                            prom_arg_t *rets, ...)
 {
        int i;
-        struct prom_args {
+        struct prom_args args;
-                const char *service;
-                int nargs;
-                int nret;
-                unsigned int args[12];
-        } args;
        va_list list;
-        args.service = service;
+        args.service = cpu_to_be32(ADDR(service));
-        args.nargs = nargs;
+        args.nargs = cpu_to_be32(nargs);
-        args.nret = nret;
+        args.nret = cpu_to_be32(nret);
        va_start(list, rets);
        for (i = 0; i < nargs; i++)
-                args.args[i] = va_arg(list, unsigned int);
+                args.args[i] = cpu_to_be32(va_arg(list, prom_arg_t));
        va_end(list);
        for (i = 0; i < nret; i++)
                args.args[nargs+i] = 0;
        if (prom(&args) < 0)
-                return -1;
+                return PROM_ERROR;
-        if (rets != (void *) 0)
+        if (rets != NULL)
                for (i = 1; i < nret; ++i)
-                        rets[i-1] = args.args[nargs+i];
+                        rets[i-1] = be32_to_cpu(args.args[nargs+i]);
-        return (nret > 0)? args.args[nargs]: 0;
+        return (nret > 0) ? be32_to_cpu(args.args[nargs]) : 0;
 }
 /* returns true if s2 is a prefix of s1 */
@@ -103,7 +112,7 @@ static int string_match(const char *s1, const char *s2)
 */
 static int need_map = -1;
 static ihandle chosen_mmu;
-static phandle memory;
+static ihandle memory;
 static int check_of_version(void)
 {
@@ -132,10 +141,10 @@ static int check_of_version(void)
                printf("no mmu\n");
                return 0;
        }
-        memory = (ihandle) of_call_prom("open", 1, 1, "/memory");
+        memory = of_call_prom("open", 1, 1, "/memory");
-        if (memory == (ihandle) -1) {
+        if (memory == PROM_ERROR) {
-                memory = (ihandle) of_call_prom("open", 1, 1, "/memory@0");
+                memory = of_call_prom("open", 1, 1, "/memory@0");
-                if (memory == (ihandle) -1) {
+                if (memory == PROM_ERROR) {
                        printf("no memory node\n");
                        return 0;
                }
@@ -144,40 +153,41 @@ static int check_of_version(void)
        return 1;
 }
-void *of_claim(unsigned long virt, unsigned long size, unsigned long align)
+unsigned int of_claim(unsigned long virt, unsigned long size,
+                      unsigned long align)
 {
        int ret;
-        unsigned int result;
+        prom_arg_t result;
        if (need_map < 0)
                need_map = check_of_version();
        if (align || !need_map)
-                return (void *) of_call_prom("claim", 3, 1, virt, size, align);
+                return of_call_prom("claim", 3, 1, virt, size, align);
        ret = of_call_prom_ret("call-method", 5, 2, &result, "claim", memory,
                               align, size, virt);
        if (ret != 0 || result == -1)
-                return (void *) -1;
+                return  -1;
        ret = of_call_prom_ret("call-method", 5, 2, &result, "claim", chosen_mmu,
                               align, size, virt);
        /* 0x12 == coherent + read/write */
        ret = of_call_prom("call-method", 6, 1, "map", chosen_mmu,
                           0x12, size, virt, virt);
-        return (void *) virt;
+        return virt;
 }
 void *of_vmlinux_alloc(unsigned long size)
 {
        unsigned long start = (unsigned long)_start, end = (unsigned long)_end;
-        void *addr;
+        unsigned long addr;
        void *p;
        /* With some older POWER4 firmware we need to claim the area the kernel
         * will reside in.  Newer firmwares don't need this so we just ignore
         * the return value.
         */
-        addr = of_claim(start, end - start, 0);
+        addr = (unsigned long) of_claim(start, end - start, 0);
-        printf("Trying to claim from 0x%lx to 0x%lx (0x%lx) got %p\r\n",
+        printf("Trying to claim from 0x%lx to 0x%lx (0x%lx) got %lx\r\n",
               start, end, end - start, addr);
        p = malloc(size);
@@ -197,7 +207,7 @@ void of_exit(void)
 */
 void *of_finddevice(const char *name)
 {
-        return (phandle) of_call_prom("finddevice", 1, 1, name);
+        return (void *) (unsigned long) of_call_prom("finddevice", 1, 1, name);
 }
 int of_getprop(const void *phandle, const char *name, void *buf,
diff --git a/arch/powerpc/boot/ppc_asm.h b/arch/powerpc/boot/ppc_asm.h
index eb0e98be69e0..35ea60c1f070 100644
--- a/arch/powerpc/boot/ppc_asm.h
+++ b/arch/powerpc/boot/ppc_asm.h
@@ -62,4 +62,16 @@
 #define SPRN_TBRL       268
 #define SPRN_TBRU       269
+#define FIXUP_ENDIAN                                               \
+        tdi   0, 0, 0x48; /* Reverse endian of b . + 8          */ \
+        b     $+36;       /* Skip trampoline if endian is good  */ \
+        .long 0x05009f42; /* bcl 20,31,$+4                      */ \
+        .long 0xa602487d; /* mflr r10                           */ \
+        .long 0x1c004a39; /* addi r10,r10,28                    */ \
+        .long 0xa600607d; /* mfmsr r11                          */ \
+        .long 0x01006b69; /* xori r11,r11,1                     */ \
+        .long 0xa6035a7d; /* mtsrr0 r10                         */ \
+        .long 0xa6037b7d; /* mtsrr1 r11                         */ \
+        .long 0x2400004c  /* rfid                               */
 #endif /* _PPC64_PPC_ASM_H */
diff --git a/arch/powerpc/boot/pseries-head.S b/arch/powerpc/boot/pseries-head.S
new file mode 100644
index 000000000000..6ef6e02e80f9
--- /dev/null
+++ b/arch/powerpc/boot/pseries-head.S
@@ -0,0 +1,8 @@
+#include "ppc_asm.h"
+        .text
+        .globl _zimage_start
+_zimage_start:
+        FIXUP_ENDIAN
+        b _zimage_start_lib
diff --git a/arch/powerpc/boot/stdio.c b/arch/powerpc/boot/stdio.c
index 5b57800bbc67..a701261b1781 100644
--- a/arch/powerpc/boot/stdio.c
+++ b/arch/powerpc/boot/stdio.c
@@ -21,6 +21,18 @@ size_t strnlen(const char * s, size_t count)
        return sc - s;
 }
+#ifdef __powerpc64__
+# define do_div(n, base) ({                                             \
+        unsigned int __base = (base);                                   \
+        unsigned int __rem;                                             \
+        __rem = ((unsigned long long)(n)) % __base;                     \
+        (n) = ((unsigned long long)(n)) / __base;                       \
+        __rem;                                                          \
+})
+#else
 extern unsigned int __div64_32(unsigned long long *dividend,
                               unsigned int divisor);
@@ -39,6 +51,8 @@ extern unsigned int __div64_32(unsigned long long *dividend,
        __rem;                                                          \
 })
+#endif /* __powerpc64__ */
 static int skip_atoi(const char **s)
 {
        int i, c;
diff --git a/arch/powerpc/boot/swab.h b/arch/powerpc/boot/swab.h
new file mode 100644
index 000000000000..d0e1431084ca
--- /dev/null
+++ b/arch/powerpc/boot/swab.h
@@ -0,0 +1,29 @@
+#ifndef _PPC_BOOT_SWAB_H_
+#define _PPC_BOOT_SWAB_H_
+static inline u16 swab16(u16 x)
+{
+        return  ((x & (u16)0x00ffU) << 8) |
+                ((x & (u16)0xff00U) >> 8);
+}
+static inline u32 swab32(u32 x)
+{
+        return  ((x & (u32)0x000000ffUL) << 24) |
+                ((x & (u32)0x0000ff00UL) <<  8) |
+                ((x & (u32)0x00ff0000UL) >>  8) |
+                ((x & (u32)0xff000000UL) >> 24);
+}
+static inline u64 swab64(u64 x)
+{
+        return  (u64)((x & (u64)0x00000000000000ffULL) << 56) |
+                (u64)((x & (u64)0x000000000000ff00ULL) << 40) |
+                (u64)((x & (u64)0x0000000000ff0000ULL) << 24) |
+                (u64)((x & (u64)0x00000000ff000000ULL) <<  8) |
+                (u64)((x & (u64)0x000000ff00000000ULL) >>  8) |
+                (u64)((x & (u64)0x0000ff0000000000ULL) >> 24) |
+                (u64)((x & (u64)0x00ff000000000000ULL) >> 40) |
+                (u64)((x & (u64)0xff00000000000000ULL) >> 56);
+}
+#endif /* _PPC_BOOT_SWAB_H_ */
diff --git a/arch/powerpc/boot/treeboot-akebono.c b/arch/powerpc/boot/treeboot-akebono.c
new file mode 100644
index 000000000000..b73174c34fe4
--- /dev/null
+++ b/arch/powerpc/boot/treeboot-akebono.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright © 2013 Tony Breeds IBM Corporation
+ * Copyright © 2013 Alistair Popple IBM Corporation
+ *
+ * Based on earlier code:
+ *   Copyright (C) Paul Mackerras 1997.
+ *
+ *   Matt Porter <mporter@kernel.crashing.org>
+ *   Copyright 2002-2005 MontaVista Software Inc.
+ *
+ *   Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ *   Copyright (c) 2003, 2004 Zultys Technologies
+ *
+ *    Copyright 2007 David Gibson, IBM Corporation.
+ *    Copyright 2010 Ben. Herrenschmidt, IBM Corporation.
+ *    Copyright © 2011 David Kleikamp IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "string.h"
+#include "stdlib.h"
+#include "stdio.h"
+#include "page.h"
+#include "ops.h"
+#include "reg.h"
+#include "io.h"
+#include "dcr.h"
+#include "4xx.h"
+#include "44x.h"
+#include "libfdt.h"
+BSS_STACK(4096);
+#define SPRN_PIR        0x11E   /* Processor Indentification Register */
+#define USERDATA_LEN    256     /* Length of userdata passed in by PIBS */
+#define MAX_RANKS       0x4
+#define DDR3_MR0CF      0x80010011U
+#define CCTL0_MCO2      0x8000080FU
+#define CCTL0_MCO3      0x80000810U
+#define CCTL0_MCO4      0x80000811U
+#define CCTL0_MCO5      0x80000812U
+#define CCTL0_MCO6      0x80000813U
+static unsigned long long ibm_akebono_memsize;
+static long long unsigned mac_addr;
+static unsigned long long ibm_akebono_detect_memsize(void)
+{
+        u32 reg;
+        unsigned i;
+        unsigned long long memsize = 0;
+        for (i = 0; i < MAX_RANKS; i++) {
+                reg = mfdcrx(DDR3_MR0CF + i);
+                if (!(reg & 1))
+                        continue;
+                reg &= 0x0000f000;
+                reg >>= 12;
+                memsize += (0x800000ULL << reg);
+        }
+        return memsize;
+}
+static void ibm_akebono_fixups(void)
+{
+        void *emac;
+        u32 reg;
+        dt_fixup_memory(0x0ULL,  ibm_akebono_memsize);
+        /* Fixup the SD timeout frequency */
+        mtdcrx(CCTL0_MCO4, 0x1);
+        /* Disable SD high-speed mode (which seems to be broken) */
+        reg = mfdcrx(CCTL0_MCO2) & ~0x2;
+        mtdcrx(CCTL0_MCO2, reg);
+        /* Set the MAC address */
+        emac = finddevice("/plb/opb/ethernet");
+        if (emac > 0) {
+                if (mac_addr)
+                        setprop(emac, "local-mac-address",
+                                ((u8 *) &mac_addr) + 2 , 6);
+        }
+}
+void platform_init(char *userdata)
+{
+        unsigned long end_of_ram, avail_ram;
+        u32 pir_reg;
+        int node, size;
+        const u32 *timebase;
+        int len, i, userdata_len;
+        char *end;
+        userdata[USERDATA_LEN - 1] = '\0';
+        userdata_len = strlen(userdata);
+        for (i = 0; i < userdata_len - 15; i++) {
+                if (strncmp(&userdata[i], "local-mac-addr=", 15) == 0) {
+                        if (i > 0 && userdata[i - 1] != ' ') {
+                                /* We've only found a substring ending
+                                 * with local-mac-addr so this isn't
+                                 * our mac address. */
+                                continue;
+                        }
+                        mac_addr = strtoull(&userdata[i + 15], &end, 16);
+                        /* Remove the "local-mac-addr=<...>" from the kernel
+                         * command line, including the tailing space if
+                         * present. */
+                        if (*end == ' ')
+                                end++;
+                        len = ((int) end) - ((int) &userdata[i]);
+                        memmove(&userdata[i], end,
+                                userdata_len - (len + i) + 1);
+                        break;
+                }
+        }
+        loader_info.cmdline = userdata;
+        loader_info.cmdline_len = 256;
+        ibm_akebono_memsize = ibm_akebono_detect_memsize();
+        if (ibm_akebono_memsize >> 32)
+                end_of_ram = ~0UL;
+        else
+                end_of_ram = ibm_akebono_memsize;
+        avail_ram = end_of_ram - (unsigned long)_end;
+        simple_alloc_init(_end, avail_ram, 128, 64);
+        platform_ops.fixups = ibm_akebono_fixups;
+        platform_ops.exit = ibm44x_dbcr_reset;
+        pir_reg = mfspr(SPRN_PIR);
+        /* Make sure FDT blob is sane */
+        if (fdt_check_header(_dtb_start) != 0)
+                fatal("Invalid device tree blob\n");
+        node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
+                                             "cpu", sizeof("cpu"));
+        if (!node)
+                fatal("Cannot find cpu node\n");
+        timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
+        if (timebase && (size == 4))
+                timebase_period_ns = 1000000000 / *timebase;
+        fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
+        fdt_init(_dtb_start);
+        serial_console_init();
+}
diff --git a/arch/powerpc/boot/util.S b/arch/powerpc/boot/util.S
index 6636b1d7821b..243b8497d58b 100644
--- a/arch/powerpc/boot/util.S
+++ b/arch/powerpc/boot/util.S
@@ -45,7 +45,7 @@ udelay:
        mfspr   r4,SPRN_PVR
        srwi    r4,r4,16
        cmpwi   0,r4,1          /* 601 ? */
-        bne     .udelay_not_601
+        bne     .Ludelay_not_601
 00:     li      r0,86   /* Instructions / microsecond? */
        mtctr   r0
 10:     addi    r0,r0,0 /* NOP */
@@ -54,7 +54,7 @@ udelay:
        bne     00b
        blr
-.udelay_not_601:
+.Ludelay_not_601:
        mulli   r4,r3,1000      /* nanoseconds */
        /*  Change r4 to be the number of ticks using:
         *      (nanoseconds + (timebase_period_ns - 1 )) / timebase_period_ns
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index d27a25518b01..ae0f88ec4a32 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -40,6 +40,7 @@ cacheit=
 binary=
 gzip=.gz
 pie=
+format=
 # cross-compilation prefix
 CROSS=
@@ -136,6 +137,14 @@ if [ -z "$kernel" ]; then
    kernel=vmlinux
 fi
+elfformat="`${CROSS}objdump -p "$kernel" | grep 'file format' | awk '{print $4}'`"
+case "$elfformat" in
+    elf64-powerpcle)    format=elf64lppc        ;;
+    elf64-powerpc)      format=elf32ppc ;;
+    elf32-powerpc)      format=elf32ppc ;;
+esac
 platformo=$object/"$platform".o
 lds=$object/zImage.lds
 ext=strip
@@ -152,8 +161,12 @@ of)
    make_space=n
    ;;
 pseries)
-    platformo="$object/of.o $object/epapr.o"
+    platformo="$object/pseries-head.o $object/of.o $object/epapr.o"
    link_address='0x4000000'
+    if [ "$format" != "elf32ppc" ]; then
+        link_address=
+        pie=-pie
+    fi
    make_space=n
    ;;
 maple)
@@ -257,6 +270,9 @@ gamecube|wii)
 treeboot-currituck)
    link_address='0x1000000'
    ;;
+treeboot-akebono)
+    link_address='0x1000000'
+    ;;
 treeboot-iss4xx-mpic)
    platformo="$object/treeboot-iss4xx.o"
    ;;
@@ -379,7 +395,7 @@ if [ "$platform" != "miboot" ]; then
    if [ -n "$link_address" ] ; then
        text_start="-Ttext $link_address"
    fi
-    ${CROSS}ld -m elf32ppc -T $lds $text_start $pie -o "$ofile" \
+    ${CROSS}ld -m $format -T $lds $text_start $pie -o "$ofile" \
        $platformo $tmp $object/wrapper.a
    rm $tmp
 fi
diff --git a/arch/powerpc/boot/zImage.lds.S b/arch/powerpc/boot/zImage.lds.S
index 2bd8731f1365..861e72109df2 100644
--- a/arch/powerpc/boot/zImage.lds.S
+++ b/arch/powerpc/boot/zImage.lds.S
@@ -1,4 +1,10 @@
+#include <asm-generic/vmlinux.lds.h>
+#ifdef CONFIG_PPC64_BOOT_WRAPPER
+OUTPUT_ARCH(powerpc:common64)
+#else
 OUTPUT_ARCH(powerpc:common)
+#endif
 ENTRY(_zimage_start)
 EXTERN(_zimage_start)
 SECTIONS
@@ -16,7 +22,9 @@ SECTIONS
    *(.rodata*)
    *(.data*)
    *(.sdata*)
+#ifndef CONFIG_PPC64_BOOT_WRAPPER
    *(.got2)
+#endif
  }
  .dynsym : { *(.dynsym) }
  .dynstr : { *(.dynstr) }
@@ -27,7 +35,13 @@ SECTIONS
  }
  .hash : { *(.hash) }
  .interp : { *(.interp) }
-  .rela.dyn : { *(.rela*) }
+  .rela.dyn :
+  {
+#ifdef CONFIG_PPC64_BOOT_WRAPPER
+    __rela_dyn_start = .;
+#endif
+    *(.rela*)
+  }
  . = ALIGN(8);
  .kernel:dtb :
@@ -53,6 +67,15 @@ SECTIONS
    _initrd_end =  .;
  }
+#ifdef CONFIG_PPC64_BOOT_WRAPPER
+  .got :
+  {
+    __toc_start = .;
+    *(.got)
+    *(.toc)
+  }
+#endif
  . = ALIGN(4096);
  .bss       :
  {
diff --git a/arch/powerpc/configs/44x/akebono_defconfig b/arch/powerpc/configs/44x/akebono_defconfig
new file mode 100644
index 000000000000..7e2530cd9d30
--- /dev/null
+++ b/arch/powerpc/configs/44x/akebono_defconfig
@@ -0,0 +1,148 @@
+CONFIG_44x=y
+CONFIG_SMP=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_EXPERT=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_SLUB_CPU_PARTIAL is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_POWERNV_MSI is not set
+CONFIG_PPC_47x=y
+# CONFIG_EBONY is not set
+CONFIG_AKEBONO=y
+CONFIG_HIGHMEM=y
+CONFIG_HZ_100=y
+CONFIG_IRQ_ALL_CPUS=y
+# CONFIG_COMPACTION is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+# CONFIG_SUSPEND is not set
+CONFIG_PCI_MSI=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=35000
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SATA_PMP is not set
+# CONFIG_ATA_SFF is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+CONFIG_IBM_EMAC=y
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+# CONFIG_USB_DEFAULT_PERSIST is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_HCD_PCI is not set
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_M41T80=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_CRAMFS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_DEFAULT="n"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_XMON=y
+CONFIG_XMON_DEFAULT=y
+CONFIG_PPC_EARLY_DEBUG=y
+CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0x00010000
+CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x33f
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1_PPC=y
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/powerpc/configs/85xx/kmp204x_defconfig b/arch/powerpc/configs/85xx/kmp204x_defconfig
new file mode 100644
index 000000000000..e9a81e5ba273
--- /dev/null
+++ b/arch/powerpc/configs/85xx/kmp204x_defconfig
@@ -0,0 +1,225 @@
+CONFIG_PPC_85xx=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=8
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MAC_PARTITION=y
+CONFIG_CORENET_GENERIC=y
+CONFIG_MPIC_MSGR=y
+CONFIG_HIGHMEM=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_MISC=m
+CONFIG_KEXEC=y
+CONFIG_FORCE_MAX_ZONEORDER=13
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIEASPM is not set
+CONFIG_PCI_MSI=y
+CONFIG_ADVANCED_OPTIONS=y
+CONFIG_LOWMEM_SIZE_BOOL=y
+CONFIG_LOWMEM_SIZE=0x20000000
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6=y
+CONFIG_IP_SCTP=m
+CONFIG_TIPC=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_MULTIQ=y
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_CLS_BASIC=y
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_U32=y
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=y
+CONFIG_NET_CLS_CGROUP=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/mdev"
+CONFIG_DEVTMPFS=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_PHRAM=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC_BCH=y
+CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=2048
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+CONFIG_FSL_PQ_MDIO=y
+CONFIG_FSL_XGMAC_MDIO=y
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_FIXED_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_PPC_EPAPR_HV_BYTECHAN=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_NVRAM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_MPC=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_SPI=y
+CONFIG_SPI_FSL_ESPI=y
+CONFIG_SPI_SPIDEV=m
+CONFIG_PTP_1588_CLOCK=y
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_MPC85XX=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_CMOS=y
+CONFIG_UIO=y
+CONFIG_STAGING=y
+# CONFIG_NET_VENDOR_SILICOM is not set
+CONFIG_CLK_PPC_CORENET=y
+CONFIG_EXT2_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_CRAMFS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=m
+CONFIG_CRC_ITU_T=m
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_SCHEDSTATS=y
+CONFIG_RCU_TRACE=y
+CONFIG_UPROBE_EVENT=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index bbd794deb6eb..c19ff057d0f9 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -72,6 +72,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_M25P80=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 19f0fbe5ba4b..55765c8cb08f 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -32,7 +32,6 @@ CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1022_RDK=y
 CONFIG_P1023_RDB=y
-CONFIG_P1023_RDS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
 CONFIG_XES_MPC85xx=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 062312e1fe1a..5c6ecdc0f70e 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -35,7 +35,6 @@ CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
 CONFIG_P1022_RDK=y
 CONFIG_P1023_RDB=y
-CONFIG_P1023_RDS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
 CONFIG_XES_MPC85xx=y
diff --git a/arch/powerpc/include/asm/code-patching.h b/arch/powerpc/include/asm/code-patching.h
index 97e02f985df8..37991e154ef8 100644
--- a/arch/powerpc/include/asm/code-patching.h
+++ b/arch/powerpc/include/asm/code-patching.h
@@ -42,15 +42,47 @@ void __patch_exception(int exc, unsigned long addr);
 } while (0)
 #endif
+#define OP_RT_RA_MASK   0xffff0000UL
+#define LIS_R2          0x3c020000UL
+#define ADDIS_R2_R12    0x3c4c0000UL
+#define ADDI_R2_R2      0x38420000UL
 static inline unsigned long ppc_function_entry(void *func)
 {
-#ifdef CONFIG_PPC64
+#if defined(CONFIG_PPC64)
+#if defined(_CALL_ELF) && _CALL_ELF == 2
+        u32 *insn = func;
+        /*
+         * A PPC64 ABIv2 function may have a local and a global entry
+         * point. We need to use the local entry point when patching
+         * functions, so identify and step over the global entry point
+         * sequence.
+         *
+         * The global entry point sequence is always of the form:
+         *
+         * addis r2,r12,XXXX
+         * addi  r2,r2,XXXX
+         *
+         * A linker optimisation may convert the addis to lis:
+         *
+         * lis   r2,XXXX
+         * addi  r2,r2,XXXX
+         */
+        if ((((*insn & OP_RT_RA_MASK) == ADDIS_R2_R12) ||
+             ((*insn & OP_RT_RA_MASK) == LIS_R2)) &&
+            ((*(insn+1) & OP_RT_RA_MASK) == ADDI_R2_R2))
+                return (unsigned long)(insn + 2);
+        else
+                return (unsigned long)func;
+#else
        /*
-         * On PPC64 the function pointer actually points to the function's
+         * On PPC64 ABIv1 the function pointer actually points to the
-         * descriptor. The first entry in the descriptor is the address
+         * function's descriptor. The first entry in the descriptor is the
-         * of the function text.
+         * address of the function text.
         */
        return ((func_descr_t *)func)->entry;
+#endif
 #else
        return (unsigned long)func;
 #endif
diff --git a/arch/powerpc/include/asm/context_tracking.h b/arch/powerpc/include/asm/context_tracking.h
index b6f5a33b8ee2..40014921ffff 100644
--- a/arch/powerpc/include/asm/context_tracking.h
+++ b/arch/powerpc/include/asm/context_tracking.h
@@ -2,9 +2,9 @@
 #define _ASM_POWERPC_CONTEXT_TRACKING_H
 #ifdef CONFIG_CONTEXT_TRACKING
-#define SCHEDULE_USER bl        .schedule_user
+#define SCHEDULE_USER bl        schedule_user
 #else
-#define SCHEDULE_USER bl        .schedule
+#define SCHEDULE_USER bl        schedule
 #endif
 #endif
diff --git a/arch/powerpc/include/asm/cputhreads.h b/arch/powerpc/include/asm/cputhreads.h
index ac3eedb9b74a..2bf8e9307be9 100644
--- a/arch/powerpc/include/asm/cputhreads.h
+++ b/arch/powerpc/include/asm/cputhreads.h
@@ -18,10 +18,12 @@
 #ifdef CONFIG_SMP
 extern int threads_per_core;
+extern int threads_per_subcore;
 extern int threads_shift;
 extern cpumask_t threads_core_mask;
 #else
 #define threads_per_core        1
+#define threads_per_subcore     1
 #define threads_shift           0
 #define threads_core_mask       (CPU_MASK_CPU0)
 #endif
@@ -74,6 +76,11 @@ static inline int cpu_thread_in_core(int cpu)
        return cpu & (threads_per_core - 1);
 }
+static inline int cpu_thread_in_subcore(int cpu)
+{
+        return cpu & (threads_per_subcore - 1);
+}
 static inline int cpu_first_thread_sibling(int cpu)
 {
        return cpu & ~(threads_per_core - 1);
diff --git a/arch/powerpc/include/asm/debug.h b/arch/powerpc/include/asm/debug.h
index d2516308ed1e..a954e4975049 100644
--- a/arch/powerpc/include/asm/debug.h
+++ b/arch/powerpc/include/asm/debug.h
@@ -46,7 +46,8 @@ static inline int debugger_break_match(struct pt_regs *regs) { return 0; }
 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 #endif
-int set_breakpoint(struct arch_hw_breakpoint *brk);
+void set_breakpoint(struct arch_hw_breakpoint *brk);
+void __set_breakpoint(struct arch_hw_breakpoint *brk);
 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 extern void do_send_trap(struct pt_regs *regs, unsigned long address,
                         unsigned long error_code, int signal_code, int brkpt);
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index d4dd41fb951b..b76f58c124ca 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -32,6 +32,22 @@ struct device_node;
 #ifdef CONFIG_EEH
+/* EEH subsystem flags */
+#define EEH_ENABLED             0x1     /* EEH enabled          */
+#define EEH_FORCE_DISABLED      0x2     /* EEH disabled         */
+#define EEH_PROBE_MODE_DEV      0x4     /* From PCI device      */
+#define EEH_PROBE_MODE_DEVTREE  0x8     /* From device tree     */
+/*
+ * Delay for PE reset, all in ms
+ *
+ * PCI specification has reset hold time of 100 milliseconds.
+ * We have 250 milliseconds here. The PCI bus settlement time
+ * is specified as 1.5 seconds and we have 1.8 seconds.
+ */
+#define EEH_PE_RST_HOLD_TIME            250
+#define EEH_PE_RST_SETTLE_TIME          1800
 /*
 * The struct is used to trace PE related EEH functionality.
 * In theory, there will have one instance of the struct to
@@ -53,7 +69,7 @@ struct device_node;
 #define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
 #define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
-#define EEH_PE_PHB_DEAD         (1 << 2)        /* Dead PHB             */
+#define EEH_PE_RESET            (1 << 2)        /* PE reset in progress */
 #define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
@@ -92,6 +108,7 @@ struct eeh_pe {
 #define EEH_DEV_NO_HANDLER      (1 << 8)        /* No error handler     */
 #define EEH_DEV_SYSFS           (1 << 9)        /* Sysfs created        */
+#define EEH_DEV_REMOVED         (1 << 10)       /* Removed permanently  */
 struct eeh_dev {
        int mode;                       /* EEH mode                     */
@@ -99,7 +116,9 @@ struct eeh_dev {
        int config_addr;                /* Config address               */
        int pe_config_addr;             /* PE config address            */
        u32 config_space[16];           /* Saved PCI config space       */
-        u8 pcie_cap;                    /* Saved PCIe capability        */
+        int pcix_cap;                   /* Saved PCIx capability        */
+        int pcie_cap;                   /* Saved PCIe capability        */
+        int aer_cap;                    /* Saved AER capability         */
        struct eeh_pe *pe;              /* Associated PE                */
        struct list_head list;          /* Form link list in the PE     */
        struct pci_controller *phb;     /* Associated PHB               */
@@ -171,37 +190,40 @@ struct eeh_ops {
        int (*restore_config)(struct device_node *dn);
 };
+extern int eeh_subsystem_flags;
 extern struct eeh_ops *eeh_ops;
-extern bool eeh_subsystem_enabled;
 extern raw_spinlock_t confirm_error_lock;
-extern int eeh_probe_mode;
 static inline bool eeh_enabled(void)
 {
-        return eeh_subsystem_enabled;
+        if ((eeh_subsystem_flags & EEH_FORCE_DISABLED) ||
+            !(eeh_subsystem_flags & EEH_ENABLED))
+                return false;
+        return true;
 }
 static inline void eeh_set_enable(bool mode)
 {
-        eeh_subsystem_enabled = mode;
+        if (mode)
+                eeh_subsystem_flags |= EEH_ENABLED;
+        else
+                eeh_subsystem_flags &= ~EEH_ENABLED;
 }
-#define EEH_PROBE_MODE_DEV      (1<<0)  /* From PCI device      */
-#define EEH_PROBE_MODE_DEVTREE  (1<<1)  /* From device tree     */
 static inline void eeh_probe_mode_set(int flag)
 {
-        eeh_probe_mode = flag;
+        eeh_subsystem_flags |= flag;
 }
 static inline int eeh_probe_mode_devtree(void)
 {
-        return (eeh_probe_mode == EEH_PROBE_MODE_DEVTREE);
+        return (eeh_subsystem_flags & EEH_PROBE_MODE_DEVTREE);
 }
 static inline int eeh_probe_mode_dev(void)
 {
-        return (eeh_probe_mode == EEH_PROBE_MODE_DEV);
+        return (eeh_subsystem_flags & EEH_PROBE_MODE_DEV);
 }
 static inline void eeh_serialize_lock(unsigned long *flags)
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
index 935b5e7a1436..888d8f3f2524 100644
--- a/arch/powerpc/include/asm/elf.h
+++ b/arch/powerpc/include/asm/elf.h
@@ -90,6 +90,8 @@ typedef elf_vrregset_t elf_fpxregset_t;
 do {                                                            \
        if (((ex).e_flags & 0x3) == 2)                          \
                set_thread_flag(TIF_ELF2ABI);                   \
+        else                                                    \
+                clear_thread_flag(TIF_ELF2ABI);                 \
        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)               \
                set_thread_flag(TIF_32BIT);                     \
        else                                                    \
diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
index a563d9afd179..a8b52b61043f 100644
--- a/arch/powerpc/include/asm/exception-64e.h
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -174,10 +174,10 @@ exc_##label##_book3e:
        mtlr    r16;
 #define TLB_MISS_STATS_D(name)                                              \
        addi    r9,r13,MMSTAT_DSTATS+name;                                  \
-        bl      .tlb_stat_inc;
+        bl      tlb_stat_inc;
 #define TLB_MISS_STATS_I(name)                                              \
        addi    r9,r13,MMSTAT_ISTATS+name;                                  \
-        bl      .tlb_stat_inc;
+        bl      tlb_stat_inc;
 #define TLB_MISS_STATS_X(name)                                              \
        ld      r8,PACA_EXTLB+EX_TLB_ESR(r13);                              \
        cmpdi   cr2,r8,-1;                                                  \
@@ -185,7 +185,7 @@ exc_##label##_book3e:
        addi    r9,r13,MMSTAT_DSTATS+name;                                  \
        b       62f;                                                        \
 61:     addi    r9,r13,MMSTAT_ISTATS+name;                                  \
-62:     bl      .tlb_stat_inc;
+62:     bl      tlb_stat_inc;
 #define TLB_MISS_STATS_SAVE_INFO                                            \
        std     r14,EX_TLB_ESR(r12);    /* save ESR */
 #define TLB_MISS_STATS_SAVE_INFO_BOLTED                                     \
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index aeaa56cd9b54..8f35cd7d59cc 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -517,7 +517,7 @@ label##_relon_hv:							\
 #define DISABLE_INTS    RECONCILE_IRQ_STATE(r10,r11)
 #define ADD_NVGPRS                              \
-        bl      .save_nvgprs
+        bl      save_nvgprs
 #define RUNLATCH_ON                             \
 BEGIN_FTR_SECTION                               \
diff --git a/arch/powerpc/include/asm/ftrace.h b/arch/powerpc/include/asm/ftrace.h
index 169d039ed402..e3661872fbea 100644
--- a/arch/powerpc/include/asm/ftrace.h
+++ b/arch/powerpc/include/asm/ftrace.h
@@ -61,6 +61,7 @@ struct dyn_arch_ftrace {
 #endif
 #if defined(CONFIG_FTRACE_SYSCALLS) && defined(CONFIG_PPC64) && !defined(__ASSEMBLY__)
+#if !defined(_CALL_ELF) || _CALL_ELF != 2
 #define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
 static inline bool arch_syscall_match_sym_name(const char *sym, const char *name)
 {
@@ -72,6 +73,7 @@ static inline bool arch_syscall_match_sym_name(const char *sym, const char *name
         */
        return !strcmp(sym + 4, name + 3);
 }
+#endif
 #endif /* CONFIG_FTRACE_SYSCALLS && CONFIG_PPC64 && !__ASSEMBLY__ */
 #endif /* _ASM_POWERPC_FTRACE */
diff --git a/arch/powerpc/include/asm/hw_breakpoint.h b/arch/powerpc/include/asm/hw_breakpoint.h
index eb0f4ac75c4c..ac6432d9be46 100644
--- a/arch/powerpc/include/asm/hw_breakpoint.h
+++ b/arch/powerpc/include/asm/hw_breakpoint.h
@@ -79,7 +79,7 @@ static inline void hw_breakpoint_disable(void)
        brk.address = 0;
        brk.type = 0;
        brk.len = 0;
-        set_breakpoint(&brk);
+        __set_breakpoint(&brk);
 }
 extern void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs);
diff --git a/arch/powerpc/include/asm/irqflags.h b/arch/powerpc/include/asm/irqflags.h
index f51a5580bfd0..e20eb95429a8 100644
--- a/arch/powerpc/include/asm/irqflags.h
+++ b/arch/powerpc/include/asm/irqflags.h
@@ -20,9 +20,9 @@
 */
 #define TRACE_WITH_FRAME_BUFFER(func)           \
        mflr    r0;                             \
-        stdu    r1, -32(r1);                    \
+        stdu    r1, -STACK_FRAME_OVERHEAD(r1);  \
        std     r0, 16(r1);                     \
-        stdu    r1, -32(r1);                    \
+        stdu    r1, -STACK_FRAME_OVERHEAD(r1);  \
        bl func;                                \
        ld      r1, 0(r1);                      \
        ld      r1, 0(r1);
@@ -36,8 +36,8 @@
 * have to call a C function so call a wrapper that saves all the
 * C-clobbered registers.
 */
-#define TRACE_ENABLE_INTS       TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_on)
+#define TRACE_ENABLE_INTS       TRACE_WITH_FRAME_BUFFER(trace_hardirqs_on)
-#define TRACE_DISABLE_INTS      TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_off)
+#define TRACE_DISABLE_INTS      TRACE_WITH_FRAME_BUFFER(trace_hardirqs_off)
 /*
 * This is used by assembly code to soft-disable interrupts first and
diff --git a/arch/powerpc/include/asm/kprobes.h b/arch/powerpc/include/asm/kprobes.h
index 7b6feab6fd26..af15d4d8d604 100644
--- a/arch/powerpc/include/asm/kprobes.h
+++ b/arch/powerpc/include/asm/kprobes.h
@@ -30,6 +30,7 @@
 #include <linux/ptrace.h>
 #include <linux/percpu.h>
 #include <asm/probes.h>
+#include <asm/code-patching.h>
 #define  __ARCH_WANT_KPROBES_INSN_SLOT
@@ -56,9 +57,9 @@ typedef ppc_opcode_t kprobe_opcode_t;
                if ((colon = strchr(name, ':')) != NULL) {              \
                        colon++;                                        \
                        if (*colon != '\0' && *colon != '.')            \
-                                addr = *(kprobe_opcode_t **)addr;       \
+                                addr = (kprobe_opcode_t *)ppc_function_entry(addr); \
                } else if (name[0] != '.')                              \
-                        addr = *(kprobe_opcode_t **)addr;               \
+                        addr = (kprobe_opcode_t *)ppc_function_entry(addr); \
        } else {                                                        \
                char dot_name[KSYM_NAME_LEN];                           \
                dot_name[0] = '.';                                      \
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index 4a7cc453be0b..9c89cdd067a6 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -337,6 +337,10 @@ static inline void kvmppc_fast_vcpu_kick(struct kvm_vcpu *vcpu)
        vcpu->kvm->arch.kvm_ops->fast_vcpu_kick(vcpu);
 }
+extern void kvm_hv_vm_activated(void);
+extern void kvm_hv_vm_deactivated(void);
+extern bool kvm_hv_mode_active(void);
 #else
 static inline void __init kvm_cma_reserve(void)
 {}
@@ -356,6 +360,9 @@ static inline void kvmppc_fast_vcpu_kick(struct kvm_vcpu *vcpu)
 {
        kvm_vcpu_kick(vcpu);
 }
+static inline bool kvm_hv_mode_active(void)             { return false; }
 #endif
 #ifdef CONFIG_KVM_XICS
diff --git a/arch/powerpc/include/asm/linkage.h b/arch/powerpc/include/asm/linkage.h
index b36f650a13ff..e3ad5c72724a 100644
--- a/arch/powerpc/include/asm/linkage.h
+++ b/arch/powerpc/include/asm/linkage.h
@@ -2,6 +2,7 @@
 #define _ASM_POWERPC_LINKAGE_H
 #ifdef CONFIG_PPC64
+#if !defined(_CALL_ELF) || _CALL_ELF != 2
 #define cond_syscall(x) \
        asm ("\t.weak " #x "\n\t.set " #x ", sys_ni_syscall\n"          \
             "\t.weak ." #x "\n\t.set ." #x ", .sys_ni_syscall\n")
@@ -9,5 +10,6 @@
        asm ("\t.globl " #alias "\n\t.set " #alias ", " #name "\n"      \
             "\t.globl ." #alias "\n\t.set ." #alias ", ." #name)
 #endif
+#endif
 #endif  /* _ASM_POWERPC_LINKAGE_H */
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 5b6c03f1058f..f92b0b54e921 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -98,6 +98,9 @@ struct machdep_calls {
        void            (*iommu_save)(void);
        void            (*iommu_restore)(void);
 #endif
+#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
+        unsigned long   (*memory_block_size)(void);
+#endif
 #endif /* CONFIG_PPC64 */
        void            (*pci_dma_dev_setup)(struct pci_dev *dev);
@@ -113,6 +116,8 @@ struct machdep_calls {
        /* Optional, may be NULL. */
        void            (*show_cpuinfo)(struct seq_file *m);
        void            (*show_percpuinfo)(struct seq_file *m, int i);
+        /* Returns the current operating frequency of "cpu" in Hz */
+        unsigned long   (*get_proc_freq)(unsigned int cpu);
        void            (*init_IRQ)(void);
@@ -241,6 +246,9 @@ struct machdep_calls {
        /* Called during PCI resource reassignment */
        resource_size_t (*pcibios_window_alignment)(struct pci_bus *, unsigned long type);
+        /* Reset the secondary bus of bridge */
+        void  (*pcibios_reset_secondary_bus)(struct pci_dev *dev);
        /* Called to shutdown machine specific hardware not already controlled
         * by other drivers.
         */
diff --git a/arch/powerpc/include/asm/module.h b/arch/powerpc/include/asm/module.h
index 49fa55bfbac4..dcfcad139bcc 100644
--- a/arch/powerpc/include/asm/module.h
+++ b/arch/powerpc/include/asm/module.h
@@ -35,6 +35,7 @@ struct mod_arch_specific {
 #ifdef __powerpc64__
        unsigned int stubs_section;     /* Index of stubs section in module */
        unsigned int toc_section;       /* What section is the TOC? */
+        bool toc_fixed;                 /* Have we fixed up .TOC.? */
 #ifdef CONFIG_DYNAMIC_FTRACE
        unsigned long toc;
        unsigned long tramp;
@@ -77,6 +78,9 @@ struct mod_arch_specific {
 #    endif      /* MODULE */
 #endif
+bool is_module_trampoline(u32 *insns);
+int module_trampoline_target(struct module *mod, u32 *trampoline,
+                             unsigned long *target);
 struct exception_table_entry;
 void sort_ex_table(struct exception_table_entry *start,
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 66ad7a74116f..cb15cbb51600 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -154,6 +154,7 @@ extern int opal_enter_rtas(struct rtas_args *args,
 #define OPAL_LPC_READ                           67
 #define OPAL_LPC_WRITE                          68
 #define OPAL_RETURN_CPU                         69
+#define OPAL_REINIT_CPUS                        70
 #define OPAL_ELOG_READ                          71
 #define OPAL_ELOG_WRITE                         72
 #define OPAL_ELOG_ACK                           73
@@ -509,7 +510,7 @@ enum OpalMemErr_DynErrType {
 struct OpalMemoryErrorData {
        enum OpalMemErr_Version version:8;      /* 0x00 */
        enum OpalMemErrType     type:8;         /* 0x01 */
-        uint16_t                flags;          /* 0x02 */
+        __be16                  flags;          /* 0x02 */
        uint8_t                 reserved_1[4];  /* 0x04 */
        union {
@@ -517,15 +518,15 @@ struct OpalMemoryErrorData {
                struct {
                        enum OpalMemErr_ResilErrType resil_err_type:8;
                        uint8_t         reserved_1[7];
-                        uint64_t        physical_address_start;
+                        __be64          physical_address_start;
-                        uint64_t        physical_address_end;
+                        __be64          physical_address_end;
                } resilience;
                /* Dynamic memory deallocation error info */
                struct {
                        enum OpalMemErr_DynErrType dyn_err_type:8;
                        uint8_t         reserved_1[7];
-                        uint64_t        physical_address_start;
+                        __be64          physical_address_start;
-                        uint64_t        physical_address_end;
+                        __be64          physical_address_end;
                } dyn_dealloc;
        } u;
 };
@@ -725,6 +726,11 @@ struct OpalIoPhb3ErrorData {
        uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
 };
+enum {
+        OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
+        OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
+};
 typedef struct oppanel_line {
        const char *    line;
        uint64_t        line_len;
@@ -849,6 +855,7 @@ int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
                            uint16_t *pci_error_type, uint16_t *severity);
 int64_t opal_pci_poll(uint64_t phb_id);
 int64_t opal_return_cpu(void);
+int64_t opal_reinit_cpus(uint64_t flags);
 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
@@ -916,6 +923,7 @@ extern void opal_get_rtc_time(struct rtc_time *tm);
 extern unsigned long opal_get_boot_time(void);
 extern void opal_nvram_init(void);
 extern void opal_flash_init(void);
+extern void opal_flash_term_callback(void);
 extern int opal_elog_init(void);
 extern void opal_platform_dump_init(void);
 extern void opal_sys_param_init(void);
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 8e956a0b6e85..bb0bd25f20d0 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -92,7 +92,10 @@ struct paca_struct {
        struct slb_shadow *slb_shadow_ptr;
        struct dtl_entry *dispatch_log;
        struct dtl_entry *dispatch_log_end;
+#endif /* CONFIG_PPC_STD_MMU_64 */
+        u64 dscr_default;               /* per-CPU default DSCR */
+#ifdef CONFIG_PPC_STD_MMU_64
        /*
         * Now, starting in cacheline 2, the exception save areas
         */
diff --git a/arch/powerpc/include/asm/ppc-pci.h b/arch/powerpc/include/asm/ppc-pci.h
index ed57fa7920c8..db1e2b8eff3c 100644
--- a/arch/powerpc/include/asm/ppc-pci.h
+++ b/arch/powerpc/include/asm/ppc-pci.h
@@ -58,6 +58,7 @@ int rtas_write_config(struct pci_dn *, int where, int size, u32 val);
 int rtas_read_config(struct pci_dn *, int where, int size, u32 *val);
 void eeh_pe_state_mark(struct eeh_pe *pe, int state);
 void eeh_pe_state_clear(struct eeh_pe *pe, int state);
+void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode);
 void eeh_sysfs_add_device(struct pci_dev *pdev);
 void eeh_sysfs_remove_device(struct pci_dev *pdev);
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index cded7c1278ef..9ea266eae33e 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -57,7 +57,7 @@ BEGIN_FW_FTR_SECTION;							\
        LDX_BE  r10,0,r10;              /* get log write index */       \
        cmpd    cr1,r11,r10;                                            \
        beq+    cr1,33f;                                                \
-        bl      .accumulate_stolen_time;                                \
+        bl      accumulate_stolen_time;                         \
        ld      r12,_MSR(r1);                                           \
        andi.   r10,r12,MSR_PR;         /* Restore cr0 (coming from user) */ \
 33:                                                                     \
@@ -189,57 +189,53 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
 #define __STK_REG(i)   (112 + ((i)-14)*8)
 #define STK_REG(i)     __STK_REG(__REG_##i)
+#if defined(_CALL_ELF) && _CALL_ELF == 2
+#define STK_GOT         24
+#define __STK_PARAM(i)  (32 + ((i)-3)*8)
+#else
+#define STK_GOT         40
 #define __STK_PARAM(i)  (48 + ((i)-3)*8)
+#endif
 #define STK_PARAM(i)    __STK_PARAM(__REG_##i)
-#define XGLUE(a,b) a##b
+#if defined(_CALL_ELF) && _CALL_ELF == 2
-#define GLUE(a,b) XGLUE(a,b)
 #define _GLOBAL(name) \
        .section ".text"; \
        .align 2 ; \
+        .type name,@function; \
        .globl name; \
-        .globl GLUE(.,name); \
+name:
-        .section ".opd","aw"; \
-name: \
-        .quad GLUE(.,name); \
-        .quad .TOC.@tocbase; \
-        .quad 0; \
-        .previous; \
-        .type GLUE(.,name),@function; \
-GLUE(.,name):
-#define _INIT_GLOBAL(name) \
+#define _GLOBAL_TOC(name) \
-        __REF; \
+        .section ".text"; \
        .align 2 ; \
+        .type name,@function; \
        .globl name; \
-        .globl GLUE(.,name); \
-        .section ".opd","aw"; \
 name: \
-        .quad GLUE(.,name); \
+0:      addis r2,r12,(.TOC.-0b)@ha; \
-        .quad .TOC.@tocbase; \
+        addi r2,r2,(.TOC.-0b)@l; \
-        .quad 0; \
+        .localentry name,.-name
-        .previous; \
-        .type GLUE(.,name),@function; \
-GLUE(.,name):
 #define _KPROBE(name) \
        .section ".kprobes.text","a"; \
        .align 2 ; \
+        .type name,@function; \
        .globl name; \
-        .globl GLUE(.,name); \
+name:
-        .section ".opd","aw"; \
-name: \
+#define DOTSYM(a)       a
-        .quad GLUE(.,name); \
-        .quad .TOC.@tocbase; \
+#else
-        .quad 0; \
-        .previous; \
+#define XGLUE(a,b) a##b
-        .type GLUE(.,name),@function; \
+#define GLUE(a,b) XGLUE(a,b)
-GLUE(.,name):
-#define _STATIC(name) \
+#define _GLOBAL(name) \
        .section ".text"; \
        .align 2 ; \
+        .globl name; \
+        .globl GLUE(.,name); \
        .section ".opd","aw"; \
 name: \
        .quad GLUE(.,name); \
@@ -249,9 +245,13 @@ name: \
        .type GLUE(.,name),@function; \
 GLUE(.,name):
-#define _INIT_STATIC(name) \
+#define _GLOBAL_TOC(name) _GLOBAL(name)
-        __REF; \
+#define _KPROBE(name) \
+        .section ".kprobes.text","a"; \
        .align 2 ; \
+        .globl name; \
+        .globl GLUE(.,name); \
        .section ".opd","aw"; \
 name: \
        .quad GLUE(.,name); \
@@ -261,6 +261,10 @@ name: \
        .type GLUE(.,name),@function; \
 GLUE(.,name):
+#define DOTSYM(a)       GLUE(.,a)
+#endif
 #else /* 32-bit */
 #define _ENTRY(n)       \
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index d660dc36831a..6d59072e13a7 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -449,7 +449,7 @@ extern unsigned long cpuidle_disable;
 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
-extern void power7_nap(void);
+extern void power7_nap(int check_irq);
 extern void power7_sleep(void);
 extern void flush_instruction_cache(void);
 extern void hard_reset_now(void);
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 4852bcf270f3..bffd89d27301 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -215,6 +215,7 @@
 #define SPRN_TEXASR     0x82    /* Transaction EXception & Summary */
 #define   TEXASR_FS     __MASK(63-36)   /* Transaction Failure Summary */
 #define SPRN_TEXASRU    0x83    /* ''      ''      ''    Upper 32  */
+#define   TEXASR_FS     __MASK(63-36) /* TEXASR Failure Summary */
 #define SPRN_TFHAR      0x80    /* Transaction Failure Handler Addr */
 #define SPRN_CTRLF      0x088
 #define SPRN_CTRLT      0x098
@@ -224,6 +225,7 @@
 #define   CTRL_TE       0x00c00000      /* thread enable */
 #define   CTRL_RUNLATCH 0x1
 #define SPRN_DAWR       0xB4
+#define SPRN_RPR        0xBA    /* Relative Priority Register */
 #define SPRN_CIABR      0xBB
 #define   CIABR_PRIV            0x3
 #define   CIABR_PRIV_USER       1
@@ -272,8 +274,10 @@
 #define SPRN_HSRR1      0x13B   /* Hypervisor Save/Restore 1 */
 #define SPRN_IC         0x350   /* Virtual Instruction Count */
 #define SPRN_VTB        0x351   /* Virtual Time Base */
+#define SPRN_LDBAR      0x352   /* LD Base Address Register */
 #define SPRN_PMICR      0x354   /* Power Management Idle Control Reg */
 #define SPRN_PMSR       0x355   /* Power Management Status Reg */
+#define SPRN_PMMAR      0x356   /* Power Management Memory Activity Register */
 #define SPRN_PMCR       0x374   /* Power Management Control Register */
 /* HFSCR and FSCR bit numbers are the same */
@@ -433,6 +437,12 @@
 #define HID0_BTCD       (1<<1)          /* Branch target cache disable */
 #define HID0_NOPDST     (1<<1)          /* No-op dst, dstt, etc. instr. */
 #define HID0_NOPTI      (1<<0)          /* No-op dcbt and dcbst instr. */
+/* POWER8 HID0 bits */
+#define HID0_POWER8_4LPARMODE   __MASK(61)
+#define HID0_POWER8_2LPARMODE   __MASK(57)
+#define HID0_POWER8_1TO2LPAR    __MASK(52)
+#define HID0_POWER8_1TO4LPAR    __MASK(51)
+#define HID0_POWER8_DYNLPARDIS  __MASK(48)
 #define SPRN_HID1       0x3F1           /* Hardware Implementation Register 1 */
 #ifdef CONFIG_6xx
diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h
index 521790330672..a5e930aca804 100644
--- a/arch/powerpc/include/asm/sections.h
+++ b/arch/powerpc/include/asm/sections.h
@@ -50,6 +50,7 @@ static inline int overlaps_kvm_tmp(unsigned long start, unsigned long end)
 #endif
 }
+#if !defined(_CALL_ELF) || _CALL_ELF != 2
 #undef dereference_function_descriptor
 static inline void *dereference_function_descriptor(void *ptr)
 {
@@ -60,6 +61,7 @@ static inline void *dereference_function_descriptor(void *ptr)
                ptr = p;
        return ptr;
 }
+#endif
 #endif
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index ff51046b6466..5a6614a7f0b2 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -68,14 +68,6 @@ void generic_mach_cpu_die(void);
 void generic_set_cpu_dead(unsigned int cpu);
 void generic_set_cpu_up(unsigned int cpu);
 int generic_check_cpu_restart(unsigned int cpu);
-extern void inhibit_secondary_onlining(void);
-extern void uninhibit_secondary_onlining(void);
-#else /* HOTPLUG_CPU */
-static inline void inhibit_secondary_onlining(void) {}
-static inline void uninhibit_secondary_onlining(void) {}
 #endif
 #ifdef CONFIG_PPC64
diff --git a/arch/powerpc/include/asm/string.h b/arch/powerpc/include/asm/string.h
index 0dffad6bcc84..e40010abcaf1 100644
--- a/arch/powerpc/include/asm/string.h
+++ b/arch/powerpc/include/asm/string.h
@@ -10,9 +10,7 @@
 #define __HAVE_ARCH_STRNCMP
 #define __HAVE_ARCH_STRCAT
 #define __HAVE_ARCH_MEMSET
-#ifdef __BIG_ENDIAN__
 #define __HAVE_ARCH_MEMCPY
-#endif
 #define __HAVE_ARCH_MEMMOVE
 #define __HAVE_ARCH_MEMCMP
 #define __HAVE_ARCH_MEMCHR
@@ -24,9 +22,7 @@ extern int strcmp(const char *,const char *);
 extern int strncmp(const char *, const char *, __kernel_size_t);
 extern char * strcat(char *, const char *);
 extern void * memset(void *,int,__kernel_size_t);
-#ifdef __BIG_ENDIAN__
 extern void * memcpy(void *,const void *,__kernel_size_t);
-#endif
 extern void * memmove(void *,const void *,__kernel_size_t);
 extern int memcmp(const void *,const void *,__kernel_size_t);
 extern void * memchr(const void *,int,__kernel_size_t);
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index ea4dc3a89c1f..babbeca6850f 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -62,7 +62,7 @@ COMPAT_SYS_SPU(fcntl)
 SYSCALL(ni_syscall)
 SYSCALL_SPU(setpgid)
 SYSCALL(ni_syscall)
-SYSX(sys_ni_syscall,sys_olduname, sys_olduname)
+SYSX(sys_ni_syscall,sys_olduname,sys_olduname)
 SYSCALL_SPU(umask)
 SYSCALL_SPU(chroot)
 COMPAT_SYS(ustat)
@@ -190,7 +190,7 @@ SYSCALL_SPU(getcwd)
 SYSCALL_SPU(capget)
 SYSCALL_SPU(capset)
 COMPAT_SYS(sigaltstack)
-COMPAT_SYS_SPU(sendfile)
+SYSX_SPU(sys_sendfile64,compat_sys_sendfile,sys_sendfile)
 SYSCALL(ni_syscall)
 SYSCALL(ni_syscall)
 PPC_SYS(vfork)
@@ -258,7 +258,7 @@ SYSCALL_SPU(tgkill)
 COMPAT_SYS_SPU(utimes)
 COMPAT_SYS_SPU(statfs64)
 COMPAT_SYS_SPU(fstatfs64)
-SYSX(sys_ni_syscall, ppc_fadvise64_64, ppc_fadvise64_64)
+SYSX(sys_ni_syscall,ppc_fadvise64_64,ppc_fadvise64_64)
 PPC_SYS_SPU(rtas)
 OLDSYS(debug_setcontext)
 SYSCALL(ni_syscall)
@@ -295,7 +295,7 @@ SYSCALL_SPU(mkdirat)
 SYSCALL_SPU(mknodat)
 SYSCALL_SPU(fchownat)
 COMPAT_SYS_SPU(futimesat)
-SYSX_SPU(sys_newfstatat, sys_fstatat64, sys_fstatat64)
+SYSX_SPU(sys_newfstatat,sys_fstatat64,sys_fstatat64)
 SYSCALL_SPU(unlinkat)
 SYSCALL_SPU(renameat)
 SYSCALL_SPU(linkat)
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index 6c8a8c5a37a1..5f1048eaa5b6 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -16,19 +16,6 @@ struct device_node;
 #include <asm/mmzone.h>
-static inline int cpu_to_node(int cpu)
-{
-        int nid;
-        nid = numa_cpu_lookup_table[cpu];
-        /*
-         * During early boot, the numa-cpu lookup table might not have been
-         * setup for all CPUs yet. In such cases, default to node 0.
-         */
-        return (nid < 0) ? 0 : nid;
-}
 #define parent_node(node)       (node)
 #define cpumask_of_node(node) ((node) == -1 ?                           \
diff --git a/arch/powerpc/include/uapi/asm/Kbuild b/arch/powerpc/include/uapi/asm/Kbuild
index 48be855ef37b..7a3f795ac218 100644
--- a/arch/powerpc/include/uapi/asm/Kbuild
+++ b/arch/powerpc/include/uapi/asm/Kbuild
@@ -15,7 +15,6 @@ header-y += ioctls.h
 header-y += ipcbuf.h
 header-y += kvm.h
 header-y += kvm_para.h
-header-y += linkage.h
 header-y += mman.h
 header-y += msgbuf.h
 header-y += nvram.h
diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h
index 7e39c9146a71..59dad113897b 100644
--- a/arch/powerpc/include/uapi/asm/elf.h
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -291,9 +291,17 @@ do {									\
 #define R_PPC64_DTPREL16_HIGHERA 104 /* half16  (sym+add)@dtprel@highera */
 #define R_PPC64_DTPREL16_HIGHEST 105 /* half16  (sym+add)@dtprel@highest */
 #define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
+#define R_PPC64_TLSGD           107
+#define R_PPC64_TLSLD           108
+#define R_PPC64_TOCSAVE         109
+#define R_PPC64_REL16           249
+#define R_PPC64_REL16_LO        250
+#define R_PPC64_REL16_HI        251
+#define R_PPC64_REL16_HA        252
 /* Keep this the last entry.  */
-#define R_PPC64_NUM             107
+#define R_PPC64_NUM             253
 /* There's actually a third entry here, but it's unused */
 struct ppc64_opd_entry
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 93e1465c8496..f5995a912213 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -248,6 +248,7 @@ int main(void)
 #endif
        DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id));
        DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state));
+        DEFINE(PACA_DSCR, offsetof(struct paca_struct, dscr_default));
        DEFINE(PACA_STARTTIME, offsetof(struct paca_struct, starttime));
        DEFINE(PACA_STARTTIME_USER, offsetof(struct paca_struct, starttime_user));
        DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index cc2d8962e090..4f1393d20079 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -94,12 +94,12 @@ _GLOBAL(setup_altivec_idle)
 _GLOBAL(__setup_cpu_e6500)
        mflr    r6
 #ifdef CONFIG_PPC64
-        bl      .setup_altivec_ivors
+        bl      setup_altivec_ivors
        /* Touch IVOR42 only if the CPU supports E.HV category */
        mfspr   r10,SPRN_MMUCFG
        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
        beq     1f
-        bl      .setup_lrat_ivor
+        bl      setup_lrat_ivor
 1:
 #endif
        bl      setup_pw20_idle
@@ -164,15 +164,15 @@ _GLOBAL(__setup_cpu_e5500)
 #ifdef CONFIG_PPC_BOOK3E_64
 _GLOBAL(__restore_cpu_e6500)
        mflr    r5
-        bl      .setup_altivec_ivors
+        bl      setup_altivec_ivors
        /* Touch IVOR42 only if the CPU supports E.HV category */
        mfspr   r10,SPRN_MMUCFG
        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
        beq     1f
-        bl      .setup_lrat_ivor
+        bl      setup_lrat_ivor
 1:
-        bl      .setup_pw20_idle
+        bl      setup_pw20_idle
-        bl      .setup_altivec_idle
+        bl      setup_altivec_idle
        bl      __restore_cpu_e5500
        mtlr    r5
        blr
@@ -181,9 +181,9 @@ _GLOBAL(__restore_cpu_e5500)
        mflr    r4
        bl      __e500_icache_setup
        bl      __e500_dcache_setup
-        bl      .__setup_base_ivors
+        bl      __setup_base_ivors
-        bl      .setup_perfmon_ivor
+        bl      setup_perfmon_ivor
-        bl      .setup_doorbell_ivors
+        bl      setup_doorbell_ivors
        /*
         * We only want to touch IVOR38-41 if we're running on hardware
         * that supports category E.HV.  The architectural way to determine
@@ -192,7 +192,7 @@ _GLOBAL(__restore_cpu_e5500)
        mfspr   r10,SPRN_MMUCFG
        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
        beq     1f
-        bl      .setup_ehv_ivors
+        bl      setup_ehv_ivors
 1:
        mtlr    r4
        blr
@@ -201,9 +201,9 @@ _GLOBAL(__setup_cpu_e5500)
        mflr    r5
        bl      __e500_icache_setup
        bl      __e500_dcache_setup
-        bl      .__setup_base_ivors
+        bl      __setup_base_ivors
-        bl      .setup_perfmon_ivor
+        bl      setup_perfmon_ivor
-        bl      .setup_doorbell_ivors
+        bl      setup_doorbell_ivors
        /*
         * We only want to touch IVOR38-41 if we're running on hardware
         * that supports category E.HV.  The architectural way to determine
@@ -212,7 +212,7 @@ _GLOBAL(__setup_cpu_e5500)
        mfspr   r10,SPRN_MMUCFG
        rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
        beq     1f
-        bl      .setup_ehv_ivors
+        bl      setup_ehv_ivors
        b       2f
 1:
        ld      r10,CPU_SPEC_FEATURES(r4)
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index e7b76a6bf150..7051ea3101b9 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -22,6 +22,7 @@
 */
 #include <linux/delay.h>
+#include <linux/debugfs.h>
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/list.h>
@@ -35,6 +36,7 @@
 #include <linux/of.h>
 #include <linux/atomic.h>
+#include <asm/debug.h>
 #include <asm/eeh.h>
 #include <asm/eeh_event.h>
 #include <asm/io.h>
@@ -87,22 +89,21 @@
 /* Time to wait for a PCI slot to report status, in milliseconds */
 #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
-/* Platform dependent EEH operations */
-struct eeh_ops *eeh_ops = NULL;
-bool eeh_subsystem_enabled = false;
-EXPORT_SYMBOL(eeh_subsystem_enabled);
 /*
- * EEH probe mode support. The intention is to support multiple
+ * EEH probe mode support, which is part of the flags,
- * platforms for EEH. Some platforms like pSeries do PCI emunation
+ * is to support multiple platforms for EEH. Some platforms
- * based on device tree. However, other platforms like powernv probe
+ * like pSeries do PCI emunation based on device tree.
- * PCI devices from hardware. The flag is used to distinguish that.
+ * However, other platforms like powernv probe PCI devices
- * In addition, struct eeh_ops::probe would be invoked for particular
+ * from hardware. The flag is used to distinguish that.
- * OF node or PCI device so that the corresponding PE would be created
+ * In addition, struct eeh_ops::probe would be invoked for
- * there.
+ * particular OF node or PCI device so that the corresponding
+ * PE would be created there.
 */
-int eeh_probe_mode;
+int eeh_subsystem_flags;
+EXPORT_SYMBOL(eeh_subsystem_flags);
+/* Platform dependent EEH operations */
+struct eeh_ops *eeh_ops = NULL;
 /* Lock to avoid races due to multiple reports of an error */
 DEFINE_RAW_SPINLOCK(confirm_error_lock);
@@ -133,6 +134,15 @@ static struct eeh_stats eeh_stats;
 #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE)
+static int __init eeh_setup(char *str)
+{
+        if (!strcmp(str, "off"))
+                eeh_subsystem_flags |= EEH_FORCE_DISABLED;
+        return 1;
+}
+__setup("eeh=", eeh_setup);
 /**
 * eeh_gather_pci_data - Copy assorted PCI config space registers to buff
 * @edev: device to report data for
@@ -145,73 +155,67 @@ static struct eeh_stats eeh_stats;
 static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len)
 {
        struct device_node *dn = eeh_dev_to_of_node(edev);
-        struct pci_dev *dev = eeh_dev_to_pci_dev(edev);
        u32 cfg;
        int cap, i;
        int n = 0;
        n += scnprintf(buf+n, len-n, "%s\n", dn->full_name);
-        printk(KERN_WARNING "EEH: of node=%s\n", dn->full_name);
+        pr_warn("EEH: of node=%s\n", dn->full_name);
        eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg);
        n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
-        printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg);
+        pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
        eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg);
        n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
-        printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg);
+        pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
-        if (!dev) {
-                printk(KERN_WARNING "EEH: no PCI device for this of node\n");
-                return n;
-        }
        /* Gather bridge-specific registers */
-        if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
+        if (edev->mode & EEH_DEV_BRIDGE) {
                eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg);
                n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
-                printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg);
+                pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
                eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg);
                n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
-                printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg);
+                pr_warn("EEH: Bridge control: %04x\n", cfg);
        }
        /* Dump out the PCI-X command and status regs */
-        cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+        cap = edev->pcix_cap;
        if (cap) {
                eeh_ops->read_config(dn, cap, 4, &cfg);
                n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
-                printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg);
+                pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
                eeh_ops->read_config(dn, cap+4, 4, &cfg);
                n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
-                printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg);
+                pr_warn("EEH: PCI-X status: %08x\n", cfg);
        }
-        /* If PCI-E capable, dump PCI-E cap 10, and the AER */
+        /* If PCI-E capable, dump PCI-E cap 10 */
-        if (pci_is_pcie(dev)) {
+        cap = edev->pcie_cap;
+        if (cap) {
                n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
-                printk(KERN_WARNING
+                pr_warn("EEH: PCI-E capabilities and status follow:\n");
-                       "EEH: PCI-E capabilities and status follow:\n");
                for (i=0; i<=8; i++) {
-                        eeh_ops->read_config(dn, dev->pcie_cap+4*i, 4, &cfg);
+                        eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
                        n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
-                        printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg);
+                        pr_warn("EEH: PCI-E %02x: %08x\n", i, cfg);
                }
+        }
-                cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
+        /* If AER capable, dump it */
-                if (cap) {
+        cap = edev->aer_cap;
-                        n += scnprintf(buf+n, len-n, "pci-e AER:\n");
+        if (cap) {
-                        printk(KERN_WARNING
+                n += scnprintf(buf+n, len-n, "pci-e AER:\n");
-                               "EEH: PCI-E AER capability register set follows:\n");
+                pr_warn("EEH: PCI-E AER capability register set follows:\n");
-                        for (i=0; i<14; i++) {
+                for (i=0; i<14; i++) {
-                                eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
+                        eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
-                                n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
+                        n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
-                                printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg);
+                        pr_warn("EEH: PCI-E AER %02x: %08x\n", i, cfg);
-                        }
                }
        }
@@ -232,21 +236,19 @@ void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
 {
        size_t loglen = 0;
        struct eeh_dev *edev, *tmp;
-        bool valid_cfg_log = true;
        /*
         * When the PHB is fenced or dead, it's pointless to collect
         * the data from PCI config space because it should return
         * 0xFF's. For ER, we still retrieve the data from the PCI
         * config space.
+         *
+         * For pHyp, we have to enable IO for log retrieval. Otherwise,
+         * 0xFF's is always returned from PCI config space.
         */
-        if (eeh_probe_mode_dev() &&
+        if (!(pe->type & EEH_PE_PHB)) {
-            (pe->type & EEH_PE_PHB) &&
+                if (eeh_probe_mode_devtree())
-            (pe->state & (EEH_PE_ISOLATED | EEH_PE_PHB_DEAD)))
+                        eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
-                valid_cfg_log = false;
-        if (valid_cfg_log) {
-                eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
                eeh_ops->configure_bridge(pe);
                eeh_pe_restore_bars(pe);
@@ -309,7 +311,7 @@ static int eeh_phb_check_failure(struct eeh_pe *pe)
        /* If the PHB has been in problematic state */
        eeh_serialize_lock(&flags);
-        if (phb_pe->state & (EEH_PE_ISOLATED | EEH_PE_PHB_DEAD)) {
+        if (phb_pe->state & EEH_PE_ISOLATED) {
                ret = 0;
                goto out;
        }
@@ -515,16 +517,42 @@ EXPORT_SYMBOL(eeh_check_failure);
 */
 int eeh_pci_enable(struct eeh_pe *pe, int function)
 {
-        int rc;
+        int rc, flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
+        /*
+         * pHyp doesn't allow to enable IO or DMA on unfrozen PE.
+         * Also, it's pointless to enable them on unfrozen PE. So
+         * we have the check here.
+         */
+        if (function == EEH_OPT_THAW_MMIO ||
+            function == EEH_OPT_THAW_DMA) {
+                rc = eeh_ops->get_state(pe, NULL);
+                if (rc < 0)
+                        return rc;
+                /* Needn't to enable or already enabled */
+                if ((rc == EEH_STATE_NOT_SUPPORT) ||
+                    ((rc & flags) == flags))
+                        return 0;
+        }
        rc = eeh_ops->set_option(pe, function);
        if (rc)
-                pr_warning("%s: Unexpected state change %d on PHB#%d-PE#%x, err=%d\n",
+                pr_warn("%s: Unexpected state change %d on "
-                        __func__, function, pe->phb->global_number, pe->addr, rc);
+                        "PHB#%d-PE#%x, err=%d\n",
+                        __func__, function, pe->phb->global_number,
+                        pe->addr, rc);
        rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
-        if (rc > 0 && (rc & EEH_STATE_MMIO_ENABLED) &&
+        if (rc <= 0)
-           (function == EEH_OPT_THAW_MMIO))
+                return rc;
+        if ((function == EEH_OPT_THAW_MMIO) &&
+            (rc & EEH_STATE_MMIO_ENABLED))
+                return 0;
+        if ((function == EEH_OPT_THAW_DMA) &&
+            (rc & EEH_STATE_DMA_ENABLED))
                return 0;
        return rc;
@@ -612,26 +640,7 @@ static void eeh_reset_pe_once(struct eeh_pe *pe)
        else
                eeh_ops->reset(pe, EEH_RESET_HOT);
-        /* The PCI bus requires that the reset be held high for at least
-         * a 100 milliseconds. We wait a bit longer 'just in case'.
-         */
-#define PCI_BUS_RST_HOLD_TIME_MSEC 250
-        msleep(PCI_BUS_RST_HOLD_TIME_MSEC);
-        /* We might get hit with another EEH freeze as soon as the
-         * pci slot reset line is dropped. Make sure we don't miss
-         * these, and clear the flag now.
-         */
-        eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
        eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
-        /* After a PCI slot has been reset, the PCI Express spec requires
-         * a 1.5 second idle time for the bus to stabilize, before starting
-         * up traffic.
-         */
-#define PCI_BUS_SETTLE_TIME_MSEC 1800
-        msleep(PCI_BUS_SETTLE_TIME_MSEC);
 }
 /**
@@ -651,6 +660,10 @@ int eeh_reset_pe(struct eeh_pe *pe)
        for (i=0; i<3; i++) {
                eeh_reset_pe_once(pe);
+                /*
+                 * EEH_PE_ISOLATED is expected to be removed after
+                 * BAR restore.
+                 */
                rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
                if ((rc & flags) == flags)
                        return 0;
@@ -826,8 +839,8 @@ int eeh_init(void)
                        &hose_list, list_node)
                        pci_walk_bus(hose->bus, eeh_ops->dev_probe, NULL);
        } else {
-                pr_warning("%s: Invalid probe mode %d\n",
+                pr_warn("%s: Invalid probe mode %x",
-                           __func__, eeh_probe_mode);
+                        __func__, eeh_subsystem_flags);
                return -EINVAL;
        }
@@ -1102,10 +1115,45 @@ static const struct file_operations proc_eeh_operations = {
        .release   = single_release,
 };
+#ifdef CONFIG_DEBUG_FS
+static int eeh_enable_dbgfs_set(void *data, u64 val)
+{
+        if (val)
+                eeh_subsystem_flags &= ~EEH_FORCE_DISABLED;
+        else
+                eeh_subsystem_flags |= EEH_FORCE_DISABLED;
+        /* Notify the backend */
+        if (eeh_ops->post_init)
+                eeh_ops->post_init();
+        return 0;
+}
+static int eeh_enable_dbgfs_get(void *data, u64 *val)
+{
+        if (eeh_enabled())
+                *val = 0x1ul;
+        else
+                *val = 0x0ul;
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
+                        eeh_enable_dbgfs_set, "0x%llx\n");
+#endif
 static int __init eeh_init_proc(void)
 {
-        if (machine_is(pseries) || machine_is(powernv))
+        if (machine_is(pseries) || machine_is(powernv)) {
                proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations);
+#ifdef CONFIG_DEBUG_FS
+                debugfs_create_file("eeh_enable", 0600,
+                                    powerpc_debugfs_root, NULL,
+                                    &eeh_enable_dbgfs_ops);
+#endif
+        }
        return 0;
 }
 __initcall(eeh_init_proc);
diff --git a/arch/powerpc/kernel/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c
index bb61ca58ca6d..7100a5b96e70 100644
--- a/arch/powerpc/kernel/eeh_driver.c
+++ b/arch/powerpc/kernel/eeh_driver.c
@@ -171,6 +171,15 @@ static void eeh_enable_irq(struct pci_dev *dev)
        }
 }
+static bool eeh_dev_removed(struct eeh_dev *edev)
+{
+        /* EEH device removed ? */
+        if (!edev || (edev->mode & EEH_DEV_REMOVED))
+                return true;
+        return false;
+}
 /**
 * eeh_report_error - Report pci error to each device driver
 * @data: eeh device
@@ -187,10 +196,8 @@ static void *eeh_report_error(void *data, void *userdata)
        enum pci_ers_result rc, *res = userdata;
        struct pci_driver *driver;
-        /* We might not have the associated PCI device,
+        if (!dev || eeh_dev_removed(edev))
-         * then we should continue for next one.
+                return NULL;
-         */
-        if (!dev) return NULL;
        dev->error_state = pci_channel_io_frozen;
        driver = eeh_pcid_get(dev);
@@ -230,6 +237,9 @@ static void *eeh_report_mmio_enabled(void *data, void *userdata)
        enum pci_ers_result rc, *res = userdata;
        struct pci_driver *driver;
+        if (!dev || eeh_dev_removed(edev))
+                return NULL;
        driver = eeh_pcid_get(dev);
        if (!driver) return NULL;
@@ -267,7 +277,8 @@ static void *eeh_report_reset(void *data, void *userdata)
        enum pci_ers_result rc, *res = userdata;
        struct pci_driver *driver;
-        if (!dev) return NULL;
+        if (!dev || eeh_dev_removed(edev))
+                return NULL;
        dev->error_state = pci_channel_io_normal;
        driver = eeh_pcid_get(dev);
@@ -307,7 +318,8 @@ static void *eeh_report_resume(void *data, void *userdata)
        struct pci_dev *dev = eeh_dev_to_pci_dev(edev);
        struct pci_driver *driver;
-        if (!dev) return NULL;
+        if (!dev || eeh_dev_removed(edev))
+                return NULL;
        dev->error_state = pci_channel_io_normal;
        driver = eeh_pcid_get(dev);
@@ -343,7 +355,8 @@ static void *eeh_report_failure(void *data, void *userdata)
        struct pci_dev *dev = eeh_dev_to_pci_dev(edev);
        struct pci_driver *driver;
-        if (!dev) return NULL;
+        if (!dev || eeh_dev_removed(edev))
+                return NULL;
        dev->error_state = pci_channel_io_perm_failure;
        driver = eeh_pcid_get(dev);
@@ -380,6 +393,16 @@ static void *eeh_rmv_device(void *data, void *userdata)
        if (!dev || (dev->hdr_type & PCI_HEADER_TYPE_BRIDGE))
                return NULL;
+        /*
+         * We rely on count-based pcibios_release_device() to
+         * detach permanently offlined PEs. Unfortunately, that's
+         * not reliable enough. We might have the permanently
+         * offlined PEs attached, but we needn't take care of
+         * them and their child devices.
+         */
+        if (eeh_dev_removed(edev))
+                return NULL;
        driver = eeh_pcid_get(dev);
        if (driver) {
                eeh_pcid_put(dev);
@@ -417,6 +440,36 @@ static void *eeh_pe_detach_dev(void *data, void *userdata)
        return NULL;
 }
+/*
+ * Explicitly clear PE's frozen state for PowerNV where
+ * we have frozen PE until BAR restore is completed. It's
+ * harmless to clear it for pSeries. To be consistent with
+ * PE reset (for 3 times), we try to clear the frozen state
+ * for 3 times as well.
+ */
+static int eeh_clear_pe_frozen_state(struct eeh_pe *pe)
+{
+        int i, rc;
+        for (i = 0; i < 3; i++) {
+                rc = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
+                if (rc)
+                        continue;
+                rc = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
+                if (!rc)
+                        break;
+        }
+        /* The PE has been isolated, clear it */
+        if (rc)
+                pr_warn("%s: Can't clear frozen PHB#%x-PE#%x (%d)\n",
+                        __func__, pe->phb->global_number, pe->addr, rc);
+        else
+                eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
+        return rc;
+}
 /**
 * eeh_reset_device - Perform actual reset of a pci slot
 * @pe: EEH PE
@@ -451,19 +504,33 @@ static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
                eeh_pe_dev_traverse(pe, eeh_rmv_device, &removed);
        }
-        /* Reset the pci controller. (Asserts RST#; resets config space).
+        /*
+         * Reset the pci controller. (Asserts RST#; resets config space).
         * Reconfigure bridges and devices. Don't try to bring the system
         * up if the reset failed for some reason.
+         *
+         * During the reset, it's very dangerous to have uncontrolled PCI
+         * config accesses. So we prefer to block them. However, controlled
+         * PCI config accesses initiated from EEH itself are allowed.
         */
+        eeh_pe_state_mark(pe, EEH_PE_RESET);
        rc = eeh_reset_pe(pe);
-        if (rc)
+        if (rc) {
+                eeh_pe_state_clear(pe, EEH_PE_RESET);
                return rc;
+        }
        pci_lock_rescan_remove();
        /* Restore PE */
        eeh_ops->configure_bridge(pe);
        eeh_pe_restore_bars(pe);
+        eeh_pe_state_clear(pe, EEH_PE_RESET);
+        /* Clear frozen state */
+        rc = eeh_clear_pe_frozen_state(pe);
+        if (rc)
+                return rc;
        /* Give the system 5 seconds to finish running the user-space
         * hotplug shutdown scripts, e.g. ifdown for ethernet.  Yes,
@@ -573,7 +640,6 @@ static void eeh_handle_normal_event(struct eeh_pe *pe)
                        result = PCI_ERS_RESULT_NEED_RESET;
                } else {
                        pr_info("EEH: Notify device drivers to resume I/O\n");
-                        result = PCI_ERS_RESULT_NONE;
                        eeh_pe_dev_traverse(pe, eeh_report_mmio_enabled, &result);
                }
        }
@@ -585,10 +651,17 @@ static void eeh_handle_normal_event(struct eeh_pe *pe)
                if (rc < 0)
                        goto hard_fail;
-                if (rc)
+                if (rc) {
                        result = PCI_ERS_RESULT_NEED_RESET;
-                else
+                } else {
+                        /*
+                         * We didn't do PE reset for the case. The PE
+                         * is still in frozen state. Clear it before
+                         * resuming the PE.
+                         */
+                        eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
                        result = PCI_ERS_RESULT_RECOVERED;
+                }
        }
        /* If any device has a hard failure, then shut off everything. */
@@ -650,8 +723,17 @@ perm_error:
        /* Notify all devices that they're about to go down. */
        eeh_pe_dev_traverse(pe, eeh_report_failure, NULL);
-        /* Shut down the device drivers for good. */
+        /* Mark the PE to be removed permanently */
+        pe->freeze_count = EEH_MAX_ALLOWED_FREEZES + 1;
+        /*
+         * Shut down the device drivers for good. We mark
+         * all removed devices correctly to avoid access
+         * the their PCI config any more.
+         */
        if (frozen_bus) {
+                eeh_pe_dev_mode_mark(pe, EEH_DEV_REMOVED);
                pci_lock_rescan_remove();
                pcibios_remove_pci_devices(frozen_bus);
                pci_unlock_rescan_remove();
@@ -682,8 +764,7 @@ static void eeh_handle_special_event(void)
                                phb_pe = eeh_phb_pe_get(hose);
                                if (!phb_pe) continue;
-                                eeh_pe_state_mark(phb_pe,
+                                eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED);
-                                        EEH_PE_ISOLATED | EEH_PE_PHB_DEAD);
                        }
                        eeh_serialize_unlock(flags);
@@ -699,8 +780,7 @@ static void eeh_handle_special_event(void)
                        eeh_remove_event(pe);
                        if (rc == EEH_NEXT_ERR_DEAD_PHB)
-                                eeh_pe_state_mark(pe,
+                                eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
-                                        EEH_PE_ISOLATED | EEH_PE_PHB_DEAD);
                        else
                                eeh_pe_state_mark(pe,
                                        EEH_PE_ISOLATED | EEH_PE_RECOVERING);
@@ -724,12 +804,14 @@ static void eeh_handle_special_event(void)
                if (rc == EEH_NEXT_ERR_FROZEN_PE ||
                    rc == EEH_NEXT_ERR_FENCED_PHB) {
                        eeh_handle_normal_event(pe);
+                        eeh_pe_state_clear(pe, EEH_PE_RECOVERING);
                } else {
                        pci_lock_rescan_remove();
                        list_for_each_entry(hose, &hose_list, list_node) {
                                phb_pe = eeh_phb_pe_get(hose);
                                if (!phb_pe ||
-                                    !(phb_pe->state & EEH_PE_PHB_DEAD))
+                                    !(phb_pe->state & EEH_PE_ISOLATED) ||
+                                    (phb_pe->state & EEH_PE_RECOVERING))
                                        continue;
                                /* Notify all devices to be down */
diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index f0c353fa655a..995c2a284630 100644
--- a/arch/powerpc/kernel/eeh_pe.c
+++ b/arch/powerpc/kernel/eeh_pe.c
@@ -503,13 +503,17 @@ static void *__eeh_pe_state_mark(void *data, void *flag)
        struct eeh_dev *edev, *tmp;
        struct pci_dev *pdev;
-        /*
+        /* Keep the state of permanently removed PE intact */
-         * Mark the PE with the indicated state. Also,
+        if ((pe->freeze_count > EEH_MAX_ALLOWED_FREEZES) &&
-         * the associated PCI device will be put into
+            (state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))
-         * I/O frozen state to avoid I/O accesses from
+                return NULL;
-         * the PCI device driver.
-         */
        pe->state |= state;
+        /* Offline PCI devices if applicable */
+        if (state != EEH_PE_ISOLATED)
+                return NULL;
        eeh_pe_for_each_dev(pe, edev, tmp) {
                pdev = eeh_dev_to_pci_dev(edev);
                if (pdev)
@@ -532,6 +536,27 @@ void eeh_pe_state_mark(struct eeh_pe *pe, int state)
        eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
 }
+static void *__eeh_pe_dev_mode_mark(void *data, void *flag)
+{
+        struct eeh_dev *edev = data;
+        int mode = *((int *)flag);
+        edev->mode |= mode;
+        return NULL;
+}
+/**
+ * eeh_pe_dev_state_mark - Mark state for all device under the PE
+ * @pe: EEH PE
+ *
+ * Mark specific state for all child devices of the PE.
+ */
+void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
+{
+        eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
+}
 /**
 * __eeh_pe_state_clear - Clear state for the PE
 * @data: EEH PE
@@ -546,8 +571,16 @@ static void *__eeh_pe_state_clear(void *data, void *flag)
        struct eeh_pe *pe = (struct eeh_pe *)data;
        int state = *((int *)flag);
+        /* Keep the state of permanently removed PE intact */
+        if ((pe->freeze_count > EEH_MAX_ALLOWED_FREEZES) &&
+            (state & EEH_PE_ISOLATED))
+                return NULL;
        pe->state &= ~state;
-        pe->check_count = 0;
+        /* Clear check count since last isolation */
+        if (state & EEH_PE_ISOLATED)
+                pe->check_count = 0;
        return NULL;
 }
diff --git a/arch/powerpc/kernel/eeh_sysfs.c b/arch/powerpc/kernel/eeh_sysfs.c
index 5d753d4f2c75..e2595ba4b720 100644
--- a/arch/powerpc/kernel/eeh_sysfs.c
+++ b/arch/powerpc/kernel/eeh_sysfs.c
@@ -59,6 +59,9 @@ void eeh_sysfs_add_device(struct pci_dev *pdev)
        struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
        int rc=0;
+        if (!eeh_enabled())
+                return;
        if (edev && (edev->mode & EEH_DEV_SYSFS))
                return;
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 662c6dd98072..911d45366f59 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -39,8 +39,8 @@
 * System calls.
 */
        .section        ".toc","aw"
-.SYS_CALL_TABLE:
+SYS_CALL_TABLE:
-        .tc .sys_call_table[TC],.sys_call_table
+        .tc sys_call_table[TC],sys_call_table
 /* This value is used to mark exception frames on the stack. */
 exception_marker:
@@ -106,7 +106,7 @@ BEGIN_FW_FTR_SECTION
        LDX_BE  r10,0,r10               /* get log write index */
        cmpd    cr1,r11,r10
        beq+    cr1,33f
-        bl      .accumulate_stolen_time
+        bl      accumulate_stolen_time
        REST_GPR(0,r1)
        REST_4GPRS(3,r1)
        REST_2GPRS(7,r1)
@@ -143,7 +143,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
        std     r10,SOFTE(r1)
 #ifdef SHOW_SYSCALLS
-        bl      .do_show_syscall
+        bl      do_show_syscall
        REST_GPR(0,r1)
        REST_4GPRS(3,r1)
        REST_2GPRS(7,r1)
@@ -162,7 +162,7 @@ system_call:			/* label this so stack traces look sane */
 * Need to vector to 32 Bit or default sys_call_table here,
 * based on caller's run-mode / personality.
 */
-        ld      r11,.SYS_CALL_TABLE@toc(2)
+        ld      r11,SYS_CALL_TABLE@toc(2)
        andi.   r10,r10,_TIF_32BIT
        beq     15f
        addi    r11,r11,8       /* use 32-bit syscall entries */
@@ -174,14 +174,14 @@ system_call:			/* label this so stack traces look sane */
        clrldi  r8,r8,32
 15:
        slwi    r0,r0,4
-        ldx     r10,r11,r0      /* Fetch system call handler [ptr] */
+        ldx     r12,r11,r0      /* Fetch system call handler [ptr] */
-        mtctr   r10
+        mtctr   r12
        bctrl                   /* Call handler */
 syscall_exit:
        std     r3,RESULT(r1)
 #ifdef SHOW_SYSCALLS
-        bl      .do_show_syscall_exit
+        bl      do_show_syscall_exit
        ld      r3,RESULT(r1)
 #endif
        CURRENT_THREAD_INFO(r12, r1)
@@ -248,9 +248,9 @@ syscall_error:
        
 /* Traced system call support */
 syscall_dotrace:
-        bl      .save_nvgprs
+        bl      save_nvgprs
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .do_syscall_trace_enter
+        bl      do_syscall_trace_enter
        /*
         * Restore argument registers possibly just changed.
         * We use the return value of do_syscall_trace_enter
@@ -308,7 +308,7 @@ syscall_exit_work:
 4:      /* Anything else left to do? */
        SET_DEFAULT_THREAD_PPR(r3, r10)         /* Set thread.ppr = 3 */
        andi.   r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
-        beq     .ret_from_except_lite
+        beq     ret_from_except_lite
        /* Re-enable interrupts */
 #ifdef CONFIG_PPC_BOOK3E
@@ -319,10 +319,10 @@ syscall_exit_work:
        mtmsrd  r10,1
 #endif /* CONFIG_PPC_BOOK3E */
-        bl      .save_nvgprs
+        bl      save_nvgprs
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .do_syscall_trace_leave
+        bl      do_syscall_trace_leave
-        b       .ret_from_except
+        b       ret_from_except
 /* Save non-volatile GPRs, if not already saved. */
 _GLOBAL(save_nvgprs)
@@ -345,52 +345,48 @@ _GLOBAL(save_nvgprs)
 */
 _GLOBAL(ppc_fork)
-        bl      .save_nvgprs
+        bl      save_nvgprs
-        bl      .sys_fork
+        bl      sys_fork
        b       syscall_exit
 _GLOBAL(ppc_vfork)
-        bl      .save_nvgprs
+        bl      save_nvgprs
-        bl      .sys_vfork
+        bl      sys_vfork
        b       syscall_exit
 _GLOBAL(ppc_clone)
-        bl      .save_nvgprs
+        bl      save_nvgprs
-        bl      .sys_clone
+        bl      sys_clone
        b       syscall_exit
 _GLOBAL(ppc32_swapcontext)
-        bl      .save_nvgprs
+        bl      save_nvgprs
-        bl      .compat_sys_swapcontext
+        bl      compat_sys_swapcontext
        b       syscall_exit
 _GLOBAL(ppc64_swapcontext)
-        bl      .save_nvgprs
+        bl      save_nvgprs
-        bl      .sys_swapcontext
+        bl      sys_swapcontext
        b       syscall_exit
 _GLOBAL(ret_from_fork)
-        bl      .schedule_tail
+        bl      schedule_tail
        REST_NVGPRS(r1)
        li      r3,0
        b       syscall_exit
 _GLOBAL(ret_from_kernel_thread)
-        bl      .schedule_tail
+        bl      schedule_tail
        REST_NVGPRS(r1)
-        ld      r14, 0(r14)
        mtlr    r14
        mr      r3,r15
+#if defined(_CALL_ELF) && _CALL_ELF == 2
+        mr      r12,r14
+#endif
        blrl
        li      r3,0
        b       syscall_exit
-        .section        ".toc","aw"
-DSCR_DEFAULT:
-        .tc dscr_default[TC],dscr_default
-        .section        ".text"
 /*
 * This routine switches between two different tasks.  The process
 * state of one is saved on its kernel stack.  Then the state
@@ -575,11 +571,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 #ifdef CONFIG_PPC64
 BEGIN_FTR_SECTION
        lwz     r6,THREAD_DSCR_INHERIT(r4)
-        ld      r7,DSCR_DEFAULT@toc(2)
        ld      r0,THREAD_DSCR(r4)
        cmpwi   r6,0
        bne     1f
-        ld      r0,0(r7)
+        ld      r0,PACA_DSCR(r13)
 1:
 BEGIN_FTR_SECTION_NESTED(70)
        mfspr   r8, SPRN_FSCR
@@ -611,7 +606,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
 _GLOBAL(ret_from_except)
        ld      r11,_TRAP(r1)
        andi.   r0,r11,1
-        bne     .ret_from_except_lite
+        bne     ret_from_except_lite
        REST_NVGPRS(r1)
 _GLOBAL(ret_from_except_lite)
@@ -661,23 +656,23 @@ _GLOBAL(ret_from_except_lite)
 #endif
 1:      andi.   r0,r4,_TIF_NEED_RESCHED
        beq     2f
-        bl      .restore_interrupts
+        bl      restore_interrupts
        SCHEDULE_USER
-        b       .ret_from_except_lite
+        b       ret_from_except_lite
 2:
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
        andi.   r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
        bne     3f              /* only restore TM if nothing else to do */
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .restore_tm_state
+        bl      restore_tm_state
        b       restore
 3:
 #endif
-        bl      .save_nvgprs
+        bl      save_nvgprs
-        bl      .restore_interrupts
+        bl      restore_interrupts
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .do_notify_resume
+        bl      do_notify_resume
-        b       .ret_from_except
+        b       ret_from_except
 resume_kernel:
        /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
@@ -730,7 +725,7 @@ resume_kernel:
         * sure we are soft-disabled first and reconcile irq state.
         */
        RECONCILE_IRQ_STATE(r3,r4)
-1:      bl      .preempt_schedule_irq
+1:      bl      preempt_schedule_irq
        /* Re-test flags and eventually loop */
        CURRENT_THREAD_INFO(r9, r1)
@@ -792,7 +787,7 @@ restore_no_replay:
         */
 do_restore:
 #ifdef CONFIG_PPC_BOOK3E
-        b       .exception_return_book3e
+        b       exception_return_book3e
 #else
        /*
         * Clear the reservation. If we know the CPU tracks the address of
@@ -907,7 +902,7 @@ restore_check_irq_replay:
         *
         * Still, this might be useful for things like hash_page
         */
-        bl      .__check_irq_replay
+        bl      __check_irq_replay
        cmpwi   cr0,r3,0
        beq     restore_no_replay
 
@@ -928,13 +923,13 @@ restore_check_irq_replay:
        cmpwi   cr0,r3,0x500
        bne     1f
        addi    r3,r1,STACK_FRAME_OVERHEAD;
-        bl      .do_IRQ
+        bl      do_IRQ
-        b       .ret_from_except
+        b       ret_from_except
 1:      cmpwi   cr0,r3,0x900
        bne     1f
        addi    r3,r1,STACK_FRAME_OVERHEAD;
-        bl      .timer_interrupt
+        bl      timer_interrupt
-        b       .ret_from_except
+        b       ret_from_except
 #ifdef CONFIG_PPC_DOORBELL
 1:
 #ifdef CONFIG_PPC_BOOK3E
@@ -948,14 +943,14 @@ restore_check_irq_replay:
 #endif /* CONFIG_PPC_BOOK3E */
        bne     1f
        addi    r3,r1,STACK_FRAME_OVERHEAD;
-        bl      .doorbell_exception
+        bl      doorbell_exception
-        b       .ret_from_except
+        b       ret_from_except
 #endif /* CONFIG_PPC_DOORBELL */
-1:      b       .ret_from_except /* What else to do here ? */
+1:      b       ret_from_except /* What else to do here ? */
 
 unrecov_restore:
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unrecoverable_exception
+        bl      unrecoverable_exception
        b       unrecov_restore
 #ifdef CONFIG_PPC_RTAS
@@ -1021,7 +1016,7 @@ _GLOBAL(enter_rtas)
        std     r6,PACASAVEDMSR(r13)
        /* Setup our real return addr */        
-        LOAD_REG_ADDR(r4,.rtas_return_loc)
+        LOAD_REG_ADDR(r4,rtas_return_loc)
        clrldi  r4,r4,2                 /* convert to realmode address */
        mtlr    r4
@@ -1045,7 +1040,7 @@ _GLOBAL(enter_rtas)
        rfid
        b       .       /* prevent speculative execution */
-_STATIC(rtas_return_loc)
+rtas_return_loc:
        FIXUP_ENDIAN
        /* relocation is off at this point */
@@ -1054,7 +1049,7 @@ _STATIC(rtas_return_loc)
        bcl     20,31,$+4
 0:      mflr    r3
-        ld      r3,(1f-0b)(r3)          /* get &.rtas_restore_regs */
+        ld      r3,(1f-0b)(r3)          /* get &rtas_restore_regs */
        mfmsr   r6
        li      r0,MSR_RI
@@ -1071,9 +1066,9 @@ _STATIC(rtas_return_loc)
        b       .       /* prevent speculative execution */
        .align  3
-1:      .llong  .rtas_restore_regs
+1:      .llong  rtas_restore_regs
-_STATIC(rtas_restore_regs)
+rtas_restore_regs:
        /* relocation is on at this point */
        REST_GPR(2, r1)                 /* Restore the TOC */
        REST_GPR(13, r1)                /* Restore paca */
@@ -1173,7 +1168,7 @@ _GLOBAL(mcount)
 _GLOBAL(_mcount)
        blr
-_GLOBAL(ftrace_caller)
+_GLOBAL_TOC(ftrace_caller)
        /* Taken from output of objdump from lib64/glibc */
        mflr    r3
        ld      r11, 0(r1)
@@ -1197,10 +1192,7 @@ _GLOBAL(ftrace_graph_stub)
 _GLOBAL(ftrace_stub)
        blr
 #else
-_GLOBAL(mcount)
+_GLOBAL_TOC(_mcount)
-        blr
-_GLOBAL(_mcount)
        /* Taken from output of objdump from lib64/glibc */
        mflr    r3
        ld      r11, 0(r1)
@@ -1238,7 +1230,7 @@ _GLOBAL(ftrace_graph_caller)
        ld      r11, 112(r1)
        addi    r3, r11, 16
-        bl      .prepare_ftrace_return
+        bl      prepare_ftrace_return
        nop
        ld      r0, 128(r1)
@@ -1254,7 +1246,7 @@ _GLOBAL(return_to_handler)
        mr      r31, r1
        stdu    r1, -112(r1)
-        bl      .ftrace_return_to_handler
+        bl      ftrace_return_to_handler
        nop
        /* return value has real return address */
@@ -1284,7 +1276,7 @@ _GLOBAL(mod_return_to_handler)
         */
        ld      r2, PACATOC(r13)
-        bl      .ftrace_return_to_handler
+        bl      ftrace_return_to_handler
        nop
        /* return value has real return address */
diff --git a/arch/powerpc/kernel/epapr_paravirt.c b/arch/powerpc/kernel/epapr_paravirt.c
index 60d1a2259dbe..59e4ba74975d 100644
--- a/arch/powerpc/kernel/epapr_paravirt.c
+++ b/arch/powerpc/kernel/epapr_paravirt.c
@@ -30,6 +30,7 @@ extern u32 epapr_ev_idle_start[];
 #endif
 bool epapr_paravirt_enabled;
+static bool __maybe_unused epapr_has_idle;
 static int __init early_init_dt_scan_epapr(unsigned long node,
                                           const char *uname,
@@ -56,7 +57,7 @@ static int __init early_init_dt_scan_epapr(unsigned long node,
 #if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
        if (of_get_flat_dt_prop(node, "has-idle", NULL))
-                ppc_md.power_save = epapr_ev_idle;
+                epapr_has_idle = true;
 #endif
        epapr_paravirt_enabled = true;
@@ -71,3 +72,14 @@ int __init epapr_paravirt_early_init(void)
        return 0;
 }
+static int __init epapr_idle_init(void)
+{
+#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
+        if (epapr_has_idle)
+                ppc_md.power_save = epapr_ev_idle;
+#endif
+        return 0;
+}
+postcore_initcall(epapr_idle_init);
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index c1bee3ce9d1f..771b4e92e5d9 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -499,7 +499,7 @@ exc_##n##_bad_stack:							    \
        CHECK_NAPPING();                                                \
        addi    r3,r1,STACK_FRAME_OVERHEAD;                             \
        bl      hdlr;                                                   \
-        b       .ret_from_except_lite;
+        b       ret_from_except_lite;
 /* This value is used to mark exception frames on the stack. */
        .section        ".toc","aw"
@@ -550,11 +550,11 @@ interrupt_end_book3e:
        CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
                              PROLOG_ADDITION_NONE)
        EXCEPTION_COMMON_CRIT(0x100)
-        bl      .save_nvgprs
+        bl      save_nvgprs
        bl      special_reg_save
        CHECK_NAPPING();
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unknown_exception
+        bl      unknown_exception
        b       ret_from_crit_except
 /* Machine Check Interrupt */
@@ -562,11 +562,11 @@ interrupt_end_book3e:
        MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
                            PROLOG_ADDITION_NONE)
        EXCEPTION_COMMON_MC(0x000)
-        bl      .save_nvgprs
+        bl      save_nvgprs
        bl      special_reg_save
        CHECK_NAPPING();
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .machine_check_exception
+        bl      machine_check_exception
        b       ret_from_mc_except
 /* Data Storage Interrupt */
@@ -591,7 +591,7 @@ interrupt_end_book3e:
 /* External Input Interrupt */
        MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
-                           external_input, .do_IRQ, ACK_NONE)
+                           external_input, do_IRQ, ACK_NONE)
 /* Alignment */
        START_EXCEPTION(alignment);
@@ -612,9 +612,9 @@ interrupt_end_book3e:
        std     r14,_DSISR(r1)
        addi    r3,r1,STACK_FRAME_OVERHEAD
        ld      r14,PACA_EXGEN+EX_R14(r13)
-        bl      .save_nvgprs
+        bl      save_nvgprs
-        bl      .program_check_exception
+        bl      program_check_exception
-        b       .ret_from_except
+        b       ret_from_except
 /* Floating Point Unavailable Interrupt */
        START_EXCEPTION(fp_unavailable);
@@ -625,13 +625,13 @@ interrupt_end_book3e:
        ld      r12,_MSR(r1)
        andi.   r0,r12,MSR_PR;
        beq-    1f
-        bl      .load_up_fpu
+        bl      load_up_fpu
        b       fast_exception_return
 1:      INTS_DISABLE
-        bl      .save_nvgprs
+        bl      save_nvgprs
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .kernel_fp_unavailable_exception
+        bl      kernel_fp_unavailable_exception
-        b       .ret_from_except
+        b       ret_from_except
 /* Altivec Unavailable Interrupt */
        START_EXCEPTION(altivec_unavailable);
@@ -644,16 +644,16 @@ BEGIN_FTR_SECTION
        ld      r12,_MSR(r1)
        andi.   r0,r12,MSR_PR;
        beq-    1f
-        bl      .load_up_altivec
+        bl      load_up_altivec
        b       fast_exception_return
 1:
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 #endif
        INTS_DISABLE
-        bl      .save_nvgprs
+        bl      save_nvgprs
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .altivec_unavailable_exception
+        bl      altivec_unavailable_exception
-        b       .ret_from_except
+        b       ret_from_except
 /* AltiVec Assist */
        START_EXCEPTION(altivec_assist);
@@ -662,39 +662,39 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
                                PROLOG_ADDITION_NONE)
        EXCEPTION_COMMON(0x220)
        INTS_DISABLE
-        bl      .save_nvgprs
+        bl      save_nvgprs
        addi    r3,r1,STACK_FRAME_OVERHEAD
 #ifdef CONFIG_ALTIVEC
 BEGIN_FTR_SECTION
-        bl      .altivec_assist_exception
+        bl      altivec_assist_exception
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 #else
-        bl      .unknown_exception
+        bl      unknown_exception
 #endif
-        b       .ret_from_except
+        b       ret_from_except
 /* Decrementer Interrupt */
        MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
-                           decrementer, .timer_interrupt, ACK_DEC)
+                           decrementer, timer_interrupt, ACK_DEC)
 /* Fixed Interval Timer Interrupt */
        MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
-                           fixed_interval, .unknown_exception, ACK_FIT)
+                           fixed_interval, unknown_exception, ACK_FIT)
 /* Watchdog Timer Interrupt */
        START_EXCEPTION(watchdog);
        CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
                              PROLOG_ADDITION_NONE)
        EXCEPTION_COMMON_CRIT(0x9f0)
-        bl      .save_nvgprs
+        bl      save_nvgprs
        bl      special_reg_save
        CHECK_NAPPING();
        addi    r3,r1,STACK_FRAME_OVERHEAD
 #ifdef CONFIG_BOOKE_WDT
-        bl      .WatchdogException
+        bl      WatchdogException
 #else
-        bl      .unknown_exception
+        bl      unknown_exception
 #endif
        b       ret_from_crit_except
@@ -712,10 +712,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
                                PROLOG_ADDITION_NONE)
        EXCEPTION_COMMON(0xf20)
        INTS_DISABLE
-        bl      .save_nvgprs
+        bl      save_nvgprs
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unknown_exception
+        bl      unknown_exception
-        b       .ret_from_except
+        b       ret_from_except
 /* Debug exception as a critical interrupt*/
        START_EXCEPTION(debug_crit);
@@ -774,9 +774,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        mr      r4,r14
        ld      r14,PACA_EXCRIT+EX_R14(r13)
        ld      r15,PACA_EXCRIT+EX_R15(r13)
-        bl      .save_nvgprs
+        bl      save_nvgprs
-        bl      .DebugException
+        bl      DebugException
-        b       .ret_from_except
+        b       ret_from_except
 kernel_dbg_exc:
        b       .       /* NYI */
@@ -839,9 +839,9 @@ kernel_dbg_exc:
        mr      r4,r14
        ld      r14,PACA_EXDBG+EX_R14(r13)
        ld      r15,PACA_EXDBG+EX_R15(r13)
-        bl      .save_nvgprs
+        bl      save_nvgprs
-        bl      .DebugException
+        bl      DebugException
-        b       .ret_from_except
+        b       ret_from_except
        START_EXCEPTION(perfmon);
        NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
@@ -850,23 +850,23 @@ kernel_dbg_exc:
        INTS_DISABLE
        CHECK_NAPPING()
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .performance_monitor_exception
+        bl      performance_monitor_exception
-        b       .ret_from_except_lite
+        b       ret_from_except_lite
 /* Doorbell interrupt */
        MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
-                           doorbell, .doorbell_exception, ACK_NONE)
+                           doorbell, doorbell_exception, ACK_NONE)
 /* Doorbell critical Interrupt */
        START_EXCEPTION(doorbell_crit);
        CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
                              PROLOG_ADDITION_NONE)
        EXCEPTION_COMMON_CRIT(0x2a0)
-        bl      .save_nvgprs
+        bl      save_nvgprs
        bl      special_reg_save
        CHECK_NAPPING();
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unknown_exception
+        bl      unknown_exception
        b       ret_from_crit_except
 /*
@@ -878,21 +878,21 @@ kernel_dbg_exc:
                                PROLOG_ADDITION_NONE)
        EXCEPTION_COMMON(0x2c0)
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .save_nvgprs
+        bl      save_nvgprs
        INTS_RESTORE_HARD
-        bl      .unknown_exception
+        bl      unknown_exception
-        b       .ret_from_except
+        b       ret_from_except
 /* Guest Doorbell critical Interrupt */
        START_EXCEPTION(guest_doorbell_crit);
        CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
                              PROLOG_ADDITION_NONE)
        EXCEPTION_COMMON_CRIT(0x2e0)
-        bl      .save_nvgprs
+        bl      save_nvgprs
        bl      special_reg_save
        CHECK_NAPPING();
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unknown_exception
+        bl      unknown_exception
        b       ret_from_crit_except
 /* Hypervisor call */
@@ -901,10 +901,10 @@ kernel_dbg_exc:
                                PROLOG_ADDITION_NONE)
        EXCEPTION_COMMON(0x310)
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .save_nvgprs
+        bl      save_nvgprs
        INTS_RESTORE_HARD
-        bl      .unknown_exception
+        bl      unknown_exception
-        b       .ret_from_except
+        b       ret_from_except
 /* Embedded Hypervisor priviledged  */
        START_EXCEPTION(ehpriv);
@@ -912,10 +912,10 @@ kernel_dbg_exc:
                                PROLOG_ADDITION_NONE)
        EXCEPTION_COMMON(0x320)
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .save_nvgprs
+        bl      save_nvgprs
        INTS_RESTORE_HARD
-        bl      .unknown_exception
+        bl      unknown_exception
-        b       .ret_from_except
+        b       ret_from_except
 /* LRAT Error interrupt */
        START_EXCEPTION(lrat_error);
@@ -1014,16 +1014,16 @@ storage_fault_common:
        mr      r5,r15
        ld      r14,PACA_EXGEN+EX_R14(r13)
        ld      r15,PACA_EXGEN+EX_R15(r13)
-        bl      .do_page_fault
+        bl      do_page_fault
        cmpdi   r3,0
        bne-    1f
-        b       .ret_from_except_lite
+        b       ret_from_except_lite
-1:      bl      .save_nvgprs
+1:      bl      save_nvgprs
        mr      r5,r3
        addi    r3,r1,STACK_FRAME_OVERHEAD
        ld      r4,_DAR(r1)
-        bl      .bad_page_fault
+        bl      bad_page_fault
-        b       .ret_from_except
+        b       ret_from_except
 /*
 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
@@ -1035,10 +1035,10 @@ alignment_more:
        addi    r3,r1,STACK_FRAME_OVERHEAD
        ld      r14,PACA_EXGEN+EX_R14(r13)
        ld      r15,PACA_EXGEN+EX_R15(r13)
-        bl      .save_nvgprs
+        bl      save_nvgprs
        INTS_RESTORE_HARD
-        bl      .alignment_exception
+        bl      alignment_exception
-        b       .ret_from_except
+        b       ret_from_except
 /*
 * We branch here from entry_64.S for the last stage of the exception
@@ -1172,7 +1172,7 @@ bad_stack_book3e:
        std     r12,0(r11)
        ld      r2,PACATOC(r13)
 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .kernel_bad_stack
+        bl      kernel_bad_stack
        b       1b
 /*
@@ -1521,13 +1521,13 @@ _GLOBAL(start_initialization_book3e)
         * and always use AS 0, so we just set it up to match our link
         * address and never use 0 based addresses.
         */
-        bl      .initial_tlb_book3e
+        bl      initial_tlb_book3e
        /* Init global core bits */
-        bl      .init_core_book3e
+        bl      init_core_book3e
        /* Init per-thread bits */
-        bl      .init_thread_book3e
+        bl      init_thread_book3e
        /* Return to common init code */
        tovirt(r28,r28)
@@ -1548,7 +1548,7 @@ _GLOBAL(start_initialization_book3e)
 */
 _GLOBAL(book3e_secondary_core_init_tlb_set)
        li      r4,1
-        b       .generic_secondary_smp_init
+        b       generic_secondary_smp_init
 _GLOBAL(book3e_secondary_core_init)
        mflr    r28
@@ -1558,18 +1558,18 @@ _GLOBAL(book3e_secondary_core_init)
        bne     2f
        /* Setup TLB for this core */
-        bl      .initial_tlb_book3e
+        bl      initial_tlb_book3e
        /* We can return from the above running at a different
         * address, so recalculate r2 (TOC)
         */
-        bl      .relative_toc
+        bl      relative_toc
        /* Init global core bits */
-2:      bl      .init_core_book3e
+2:      bl      init_core_book3e
        /* Init per-thread bits */
-3:      bl      .init_thread_book3e
+3:      bl      init_thread_book3e
        /* Return to common init code at proper virtual address.
         *
@@ -1596,14 +1596,14 @@ _GLOBAL(book3e_secondary_thread_init)
        mflr    r28
        b       3b
-_STATIC(init_core_book3e)
+init_core_book3e:
        /* Establish the interrupt vector base */
        LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
        mtspr   SPRN_IVPR,r3
        sync
        blr
-_STATIC(init_thread_book3e)
+init_thread_book3e:
        lis     r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
        mtspr   SPRN_EPCR,r3
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 3afd3915921a..20f11eb4dff7 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -132,12 +132,12 @@ BEGIN_FTR_SECTION
 #endif
        beq     cr1,2f
-        b       .power7_wakeup_noloss
+        b       power7_wakeup_noloss
-2:      b       .power7_wakeup_loss
+2:      b       power7_wakeup_loss
        /* Fast Sleep wakeup on PowerNV */
 8:      GET_PACA(r13)
-        b       .power7_wakeup_tb_loss
+        b       power7_wakeup_tb_loss
 9:
 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
@@ -211,16 +211,16 @@ data_access_slb_pSeries:
 #endif /* __DISABLED__ */
        mfspr   r12,SPRN_SRR1
 #ifndef CONFIG_RELOCATABLE
-        b       .slb_miss_realmode
+        b       slb_miss_realmode
 #else
        /*
-         * We can't just use a direct branch to .slb_miss_realmode
+         * We can't just use a direct branch to slb_miss_realmode
         * because the distance from here to there depends on where
         * the kernel ends up being put.
         */
        mfctr   r11
        ld      r10,PACAKBASE(r13)
-        LOAD_HANDLER(r10, .slb_miss_realmode)
+        LOAD_HANDLER(r10, slb_miss_realmode)
        mtctr   r10
        bctr
 #endif
@@ -243,11 +243,11 @@ instruction_access_slb_pSeries:
 #endif /* __DISABLED__ */
        mfspr   r12,SPRN_SRR1
 #ifndef CONFIG_RELOCATABLE
-        b       .slb_miss_realmode
+        b       slb_miss_realmode
 #else
        mfctr   r11
        ld      r10,PACAKBASE(r13)
-        LOAD_HANDLER(r10, .slb_miss_realmode)
+        LOAD_HANDLER(r10, slb_miss_realmode)
        mtctr   r10
        bctr
 #endif
@@ -524,7 +524,7 @@ do_stab_bolted_pSeries:
        std     r12,PACA_EXSLB+EX_R12(r13)
        GET_SCRATCH0(r10)
        std     r10,PACA_EXSLB+EX_R13(r13)
-        EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD)
+        EXCEPTION_PROLOG_PSERIES_1(do_stab_bolted, EXC_STD)
        KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x300)
        KVM_HANDLER_SKIP(PACA_EXSLB, EXC_STD, 0x380)
@@ -769,38 +769,38 @@ kvmppc_skip_Hinterrupt:
 /*** Common interrupt handlers ***/
-        STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
+        STD_EXCEPTION_COMMON(0x100, system_reset, system_reset_exception)
        STD_EXCEPTION_COMMON_ASYNC(0x500, hardware_interrupt, do_IRQ)
-        STD_EXCEPTION_COMMON_ASYNC(0x900, decrementer, .timer_interrupt)
+        STD_EXCEPTION_COMMON_ASYNC(0x900, decrementer, timer_interrupt)
-        STD_EXCEPTION_COMMON(0x980, hdecrementer, .hdec_interrupt)
+        STD_EXCEPTION_COMMON(0x980, hdecrementer, hdec_interrupt)
 #ifdef CONFIG_PPC_DOORBELL
-        STD_EXCEPTION_COMMON_ASYNC(0xa00, doorbell_super, .doorbell_exception)
+        STD_EXCEPTION_COMMON_ASYNC(0xa00, doorbell_super, doorbell_exception)
 #else
-        STD_EXCEPTION_COMMON_ASYNC(0xa00, doorbell_super, .unknown_exception)
+        STD_EXCEPTION_COMMON_ASYNC(0xa00, doorbell_super, unknown_exception)
 #endif
-        STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
+        STD_EXCEPTION_COMMON(0xb00, trap_0b, unknown_exception)
-        STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
+        STD_EXCEPTION_COMMON(0xd00, single_step, single_step_exception)
-        STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
+        STD_EXCEPTION_COMMON(0xe00, trap_0e, unknown_exception)
-        STD_EXCEPTION_COMMON(0xe40, emulation_assist, .emulation_assist_interrupt)
+        STD_EXCEPTION_COMMON(0xe40, emulation_assist, emulation_assist_interrupt)
-        STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
+        STD_EXCEPTION_COMMON(0xe60, hmi_exception, unknown_exception)
 #ifdef CONFIG_PPC_DOORBELL
-        STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .doorbell_exception)
+        STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, doorbell_exception)
 #else
-        STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .unknown_exception)
+        STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, unknown_exception)
 #endif
-        STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, .performance_monitor_exception)
+        STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, performance_monitor_exception)
-        STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
+        STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, instruction_breakpoint_exception)
-        STD_EXCEPTION_COMMON(0x1502, denorm, .unknown_exception)
+        STD_EXCEPTION_COMMON(0x1502, denorm, unknown_exception)
 #ifdef CONFIG_ALTIVEC
-        STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
+        STD_EXCEPTION_COMMON(0x1700, altivec_assist, altivec_assist_exception)
 #else
-        STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
+        STD_EXCEPTION_COMMON(0x1700, altivec_assist, unknown_exception)
 #endif
 #ifdef CONFIG_CBE_RAS
-        STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
+        STD_EXCEPTION_COMMON(0x1200, cbe_system_error, cbe_system_error_exception)
-        STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
+        STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, cbe_maintenance_exception)
-        STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
+        STD_EXCEPTION_COMMON(0x1800, cbe_thermal, cbe_thermal_exception)
 #endif /* CONFIG_CBE_RAS */
        /*
@@ -829,16 +829,16 @@ data_access_slb_relon_pSeries:
        mfspr   r3,SPRN_DAR
        mfspr   r12,SPRN_SRR1
 #ifndef CONFIG_RELOCATABLE
-        b       .slb_miss_realmode
+        b       slb_miss_realmode
 #else
        /*
-         * We can't just use a direct branch to .slb_miss_realmode
+         * We can't just use a direct branch to slb_miss_realmode
         * because the distance from here to there depends on where
         * the kernel ends up being put.
         */
        mfctr   r11
        ld      r10,PACAKBASE(r13)
-        LOAD_HANDLER(r10, .slb_miss_realmode)
+        LOAD_HANDLER(r10, slb_miss_realmode)
        mtctr   r10
        bctr
 #endif
@@ -854,11 +854,11 @@ instruction_access_slb_relon_pSeries:
        mfspr   r3,SPRN_SRR0            /* SRR0 is faulting address */
        mfspr   r12,SPRN_SRR1
 #ifndef CONFIG_RELOCATABLE
-        b       .slb_miss_realmode
+        b       slb_miss_realmode
 #else
        mfctr   r11
        ld      r10,PACAKBASE(r13)
-        LOAD_HANDLER(r10, .slb_miss_realmode)
+        LOAD_HANDLER(r10, slb_miss_realmode)
        mtctr   r10
        bctr
 #endif
@@ -966,7 +966,7 @@ system_call_entry:
        b       system_call_common
 ppc64_runlatch_on_trampoline:
-        b       .__ppc64_runlatch_on
+        b       __ppc64_runlatch_on
 /*
 * Here we have detected that the kernel stack pointer is bad.
@@ -1025,7 +1025,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
        std     r12,RESULT(r1)
        std     r11,STACK_FRAME_OVERHEAD-16(r1)
 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .kernel_bad_stack
+        bl      kernel_bad_stack
        b       1b
 /*
@@ -1046,7 +1046,7 @@ data_access_common:
        ld      r3,PACA_EXGEN+EX_DAR(r13)
        lwz     r4,PACA_EXGEN+EX_DSISR(r13)
        li      r5,0x300
-        b       .do_hash_page           /* Try to handle as hpte fault */
+        b       do_hash_page            /* Try to handle as hpte fault */
        .align  7
        .globl  h_data_storage_common
@@ -1056,11 +1056,11 @@ h_data_storage_common:
        mfspr   r10,SPRN_HDSISR
        stw     r10,PACA_EXGEN+EX_DSISR(r13)
        EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
-        bl      .save_nvgprs
+        bl      save_nvgprs
        DISABLE_INTS
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unknown_exception
+        bl      unknown_exception
-        b       .ret_from_except
+        b       ret_from_except
        .align  7
        .globl instruction_access_common
@@ -1071,9 +1071,9 @@ instruction_access_common:
        ld      r3,_NIP(r1)
        andis.  r4,r12,0x5820
        li      r5,0x400
-        b       .do_hash_page           /* Try to handle as hpte fault */
+        b       do_hash_page            /* Try to handle as hpte fault */
-        STD_EXCEPTION_COMMON(0xe20, h_instr_storage, .unknown_exception)
+        STD_EXCEPTION_COMMON(0xe20, h_instr_storage, unknown_exception)
 /*
 * Here is the common SLB miss user that is used when going to virtual
@@ -1088,7 +1088,7 @@ slb_miss_user_common:
        stw     r9,PACA_EXGEN+EX_CCR(r13)
        std     r10,PACA_EXGEN+EX_LR(r13)
        std     r11,PACA_EXGEN+EX_SRR0(r13)
-        bl      .slb_allocate_user
+        bl      slb_allocate_user
        ld      r10,PACA_EXGEN+EX_LR(r13)
        ld      r3,PACA_EXGEN+EX_R3(r13)
@@ -1131,9 +1131,9 @@ slb_miss_fault:
 unrecov_user_slb:
        EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
        DISABLE_INTS
-        bl      .save_nvgprs
+        bl      save_nvgprs
 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unrecoverable_exception
+        bl      unrecoverable_exception
        b       1b
 #endif /* __DISABLED__ */
@@ -1158,10 +1158,10 @@ machine_check_common:
        lwz     r4,PACA_EXGEN+EX_DSISR(r13)
        std     r3,_DAR(r1)
        std     r4,_DSISR(r1)
-        bl      .save_nvgprs
+        bl      save_nvgprs
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .machine_check_exception
+        bl      machine_check_exception
-        b       .ret_from_except
+        b       ret_from_except
        .align  7
        .globl alignment_common
@@ -1175,31 +1175,31 @@ alignment_common:
        lwz     r4,PACA_EXGEN+EX_DSISR(r13)
        std     r3,_DAR(r1)
        std     r4,_DSISR(r1)
-        bl      .save_nvgprs
+        bl      save_nvgprs
        DISABLE_INTS
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .alignment_exception
+        bl      alignment_exception
-        b       .ret_from_except
+        b       ret_from_except
        .align  7
        .globl program_check_common
 program_check_common:
        EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
-        bl      .save_nvgprs
+        bl      save_nvgprs
        DISABLE_INTS
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .program_check_exception
+        bl      program_check_exception
-        b       .ret_from_except
+        b       ret_from_except
        .align  7
        .globl fp_unavailable_common
 fp_unavailable_common:
        EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
        bne     1f                      /* if from user, just load it up */
-        bl      .save_nvgprs
+        bl      save_nvgprs
        DISABLE_INTS
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .kernel_fp_unavailable_exception
+        bl      kernel_fp_unavailable_exception
        BUG_OPCODE
 1:
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
@@ -1211,15 +1211,15 @@ BEGIN_FTR_SECTION
        bne-    2f
 END_FTR_SECTION_IFSET(CPU_FTR_TM)
 #endif
-        bl      .load_up_fpu
+        bl      load_up_fpu
        b       fast_exception_return
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 2:      /* User process was in a transaction */
-        bl      .save_nvgprs
+        bl      save_nvgprs
        DISABLE_INTS
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .fp_unavailable_tm
+        bl      fp_unavailable_tm
-        b       .ret_from_except
+        b       ret_from_except
 #endif
        .align  7
        .globl altivec_unavailable_common
@@ -1237,24 +1237,24 @@ BEGIN_FTR_SECTION
        bne-    2f
  END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
 #endif
-        bl      .load_up_altivec
+        bl      load_up_altivec
        b       fast_exception_return
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 2:      /* User process was in a transaction */
-        bl      .save_nvgprs
+        bl      save_nvgprs
        DISABLE_INTS
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .altivec_unavailable_tm
+        bl      altivec_unavailable_tm
-        b       .ret_from_except
+        b       ret_from_except
 #endif
 1:
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 #endif
-        bl      .save_nvgprs
+        bl      save_nvgprs
        DISABLE_INTS
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .altivec_unavailable_exception
+        bl      altivec_unavailable_exception
-        b       .ret_from_except
+        b       ret_from_except
        .align  7
        .globl vsx_unavailable_common
@@ -1272,26 +1272,26 @@ BEGIN_FTR_SECTION
        bne-    2f
  END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
 #endif
-        b       .load_up_vsx
+        b       load_up_vsx
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 2:      /* User process was in a transaction */
-        bl      .save_nvgprs
+        bl      save_nvgprs
        DISABLE_INTS
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .vsx_unavailable_tm
+        bl      vsx_unavailable_tm
-        b       .ret_from_except
+        b       ret_from_except
 #endif
 1:
 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 #endif
-        bl      .save_nvgprs
+        bl      save_nvgprs
        DISABLE_INTS
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .vsx_unavailable_exception
+        bl      vsx_unavailable_exception
-        b       .ret_from_except
+        b       ret_from_except
-        STD_EXCEPTION_COMMON(0xf60, facility_unavailable, .facility_unavailable_exception)
+        STD_EXCEPTION_COMMON(0xf60, facility_unavailable, facility_unavailable_exception)
-        STD_EXCEPTION_COMMON(0xf80, hv_facility_unavailable, .facility_unavailable_exception)
+        STD_EXCEPTION_COMMON(0xf80, hv_facility_unavailable, facility_unavailable_exception)
        .align  7
        .globl  __end_handlers
@@ -1386,9 +1386,9 @@ _GLOBAL(opal_mc_secondary_handler)
 machine_check_handle_early:
        std     r0,GPR0(r1)     /* Save r0 */
        EXCEPTION_PROLOG_COMMON_3(0x200)
-        bl      .save_nvgprs
+        bl      save_nvgprs
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .machine_check_early
+        bl      machine_check_early
        ld      r12,_MSR(r1)
 #ifdef  CONFIG_PPC_P7_NAP
        /*
@@ -1408,11 +1408,11 @@ machine_check_handle_early:
        /* Supervisor state loss */
        li      r0,1
        stb     r0,PACA_NAPSTATELOST(r13)
-3:      bl      .machine_check_queue_event
+3:      bl      machine_check_queue_event
        MACHINE_CHECK_HANDLER_WINDUP
        GET_PACA(r13)
        ld      r1,PACAR1(r13)
-        b       .power7_enter_nap_mode
+        b       power7_enter_nap_mode
 4:
 #endif
        /*
@@ -1444,7 +1444,7 @@ machine_check_handle_early:
        andi.   r11,r12,MSR_RI
        bne     2f
 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unrecoverable_exception
+        bl      unrecoverable_exception
        b       1b
 2:
        /*
@@ -1452,7 +1452,7 @@ machine_check_handle_early:
         * Queue up the MCE event so that we can log it later, while
         * returning from kernel or opal call.
         */
-        bl      .machine_check_queue_event
+        bl      machine_check_queue_event
        MACHINE_CHECK_HANDLER_WINDUP
        rfid
 9:
@@ -1468,7 +1468,7 @@ machine_check_handle_early:
 * r3 is saved in paca->slb_r3
 * We assume we aren't going to take any exceptions during this procedure.
 */
-_GLOBAL(slb_miss_realmode)
+slb_miss_realmode:
        mflr    r10
 #ifdef CONFIG_RELOCATABLE
        mtctr   r11
@@ -1477,7 +1477,7 @@ _GLOBAL(slb_miss_realmode)
        stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
        std     r10,PACA_EXSLB+EX_LR(r13)       /* save LR */
-        bl      .slb_allocate_realmode
+        bl      slb_allocate_realmode
        /* All done -- return from exception. */
@@ -1517,9 +1517,9 @@ _GLOBAL(slb_miss_realmode)
 unrecov_slb:
        EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
        DISABLE_INTS
-        bl      .save_nvgprs
+        bl      save_nvgprs
 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unrecoverable_exception
+        bl      unrecoverable_exception
        b       1b
@@ -1536,7 +1536,7 @@ power4_fixup_nap:
 * Hash table stuff
 */
        .align  7
-_STATIC(do_hash_page)
+do_hash_page:
        std     r3,_DAR(r1)
        std     r4,_DSISR(r1)
@@ -1573,7 +1573,7 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
         *
         * at return r3 = 0 for success, 1 for page fault, negative for error
         */
-        bl      .hash_page              /* build HPTE if possible */
+        bl      hash_page               /* build HPTE if possible */
        cmpdi   r3,0                    /* see if hash_page succeeded */
        /* Success */
@@ -1587,35 +1587,35 @@ handle_page_fault:
 11:     ld      r4,_DAR(r1)
        ld      r5,_DSISR(r1)
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .do_page_fault
+        bl      do_page_fault
        cmpdi   r3,0
        beq+    12f
-        bl      .save_nvgprs
+        bl      save_nvgprs
        mr      r5,r3
        addi    r3,r1,STACK_FRAME_OVERHEAD
        lwz     r4,_DAR(r1)
-        bl      .bad_page_fault
+        bl      bad_page_fault
-        b       .ret_from_except
+        b       ret_from_except
 /* We have a data breakpoint exception - handle it */
 handle_dabr_fault:
-        bl      .save_nvgprs
+        bl      save_nvgprs
        ld      r4,_DAR(r1)
        ld      r5,_DSISR(r1)
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .do_break
+        bl      do_break
-12:     b       .ret_from_except_lite
+12:     b       ret_from_except_lite
 /* We have a page fault that hash_page could handle but HV refused
 * the PTE insertion
 */
-13:     bl      .save_nvgprs
+13:     bl      save_nvgprs
        mr      r5,r3
        addi    r3,r1,STACK_FRAME_OVERHEAD
        ld      r4,_DAR(r1)
-        bl      .low_hash_fault
+        bl      low_hash_fault
-        b       .ret_from_except
+        b       ret_from_except
 /*
 * We come here as a result of a DSI at a point where we don't want
@@ -1624,16 +1624,16 @@ handle_dabr_fault:
 * were soft-disabled.  We want to invoke the exception handler for
 * the access, or panic if there isn't a handler.
 */
-77:     bl      .save_nvgprs
+77:     bl      save_nvgprs
        mr      r4,r3
        addi    r3,r1,STACK_FRAME_OVERHEAD
        li      r5,SIGSEGV
-        bl      .bad_page_fault
+        bl      bad_page_fault
-        b       .ret_from_except
+        b       ret_from_except
        /* here we have a segment miss */
 do_ste_alloc:
-        bl      .ste_allocate           /* try to insert stab entry */
+        bl      ste_allocate            /* try to insert stab entry */
        cmpdi   r3,0
        bne-    handle_page_fault
        b       fast_exception_return
@@ -1646,7 +1646,7 @@ do_ste_alloc:
 * We assume (DAR >> 60) == 0xc.
 */
        .align  7
-_GLOBAL(do_stab_bolted)
+do_stab_bolted:
        stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
        std     r11,PACA_EXSLB+EX_SRR0(r13)     /* save SRR0 in exc. frame */
        mfspr   r11,SPRN_DAR                    /* ea */
diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c
index 7213d930918d..742694c1d852 100644
--- a/arch/powerpc/kernel/fadump.c
+++ b/arch/powerpc/kernel/fadump.c
@@ -69,7 +69,7 @@ int __init early_init_dt_scan_fw_dump(unsigned long node,
         */
        token = of_get_flat_dt_prop(node, "ibm,configure-kernel-dump", NULL);
        if (!token)
-                return 0;
+                return 1;
        fw_dump.fadump_supported = 1;
        fw_dump.ibm_configure_kernel_dump = *token;
@@ -92,7 +92,7 @@ int __init early_init_dt_scan_fw_dump(unsigned long node,
                                        &size);
        if (!sections)
-                return 0;
+                return 1;
        num_sections = size / (3 * sizeof(u32));
@@ -110,6 +110,7 @@ int __init early_init_dt_scan_fw_dump(unsigned long node,
                        break;
                }
        }
        return 1;
 }
@@ -645,7 +646,7 @@ static int __init fadump_build_cpu_notes(const struct fadump_mem_struct *fdm)
                }
                /* Lower 4 bytes of reg_value contains logical cpu id */
                cpu = reg_entry->reg_value & FADUMP_CPU_ID_MASK;
-                if (!cpumask_test_cpu(cpu, &fdh->cpu_online_mask)) {
+                if (fdh && !cpumask_test_cpu(cpu, &fdh->cpu_online_mask)) {
                        SKIP_TO_NEXT_CPU(reg_entry);
                        continue;
                }
@@ -662,9 +663,11 @@ static int __init fadump_build_cpu_notes(const struct fadump_mem_struct *fdm)
        }
        fadump_final_note(note_buf);
-        pr_debug("Updating elfcore header (%llx) with cpu notes\n",
+        if (fdh) {
+                pr_debug("Updating elfcore header (%llx) with cpu notes\n",
                                                        fdh->elfcorehdr_addr);
-        fadump_update_elfcore_header((char *)__va(fdh->elfcorehdr_addr));
+                fadump_update_elfcore_header((char *)__va(fdh->elfcorehdr_addr));
+        }
        return 0;
 error_out:
diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c
index 6a014c763cc7..f202d0731b06 100644
--- a/arch/powerpc/kernel/ftrace.c
+++ b/arch/powerpc/kernel/ftrace.c
@@ -105,11 +105,9 @@ __ftrace_make_nop(struct module *mod,
                  struct dyn_ftrace *rec, unsigned long addr)
 {
        unsigned int op;
-        unsigned int jmp[5];
        unsigned long ptr;
        unsigned long ip = rec->ip;
-        unsigned long tramp;
+        void *tramp;
-        int offset;
        /* read where this goes */
        if (probe_kernel_read(&op, (void *)ip, sizeof(int)))
@@ -122,96 +120,41 @@ __ftrace_make_nop(struct module *mod,
        }
        /* lets find where the pointer goes */
-        tramp = find_bl_target(ip, op);
+        tramp = (void *)find_bl_target(ip, op);
-        /*
-         * On PPC64 the trampoline looks like:
-         * 0x3d, 0x82, 0x00, 0x00,    addis   r12,r2, <high>
-         * 0x39, 0x8c, 0x00, 0x00,    addi    r12,r12, <low>
-         *   Where the bytes 2,3,6 and 7 make up the 32bit offset
-         *   to the TOC that holds the pointer.
-         *   to jump to.
-         * 0xf8, 0x41, 0x00, 0x28,    std     r2,40(r1)
-         * 0xe9, 0x6c, 0x00, 0x20,    ld      r11,32(r12)
-         *   The actually address is 32 bytes from the offset
-         *   into the TOC.
-         * 0xe8, 0x4c, 0x00, 0x28,    ld      r2,40(r12)
-         */
-        pr_devel("ip:%lx jumps to %lx r2: %lx", ip, tramp, mod->arch.toc);
-        /* Find where the trampoline jumps to */
-        if (probe_kernel_read(jmp, (void *)tramp, sizeof(jmp))) {
-                printk(KERN_ERR "Failed to read %lx\n", tramp);
-                return -EFAULT;
-        }
-        pr_devel(" %08x %08x", jmp[0], jmp[1]);
+        pr_devel("ip:%lx jumps to %p", ip, tramp);
-        /* verify that this is what we expect it to be */
+        if (!is_module_trampoline(tramp)) {
-        if (((jmp[0] & 0xffff0000) != 0x3d820000) ||
-            ((jmp[1] & 0xffff0000) != 0x398c0000) ||
-            (jmp[2] != 0xf8410028) ||
-            (jmp[3] != 0xe96c0020) ||
-            (jmp[4] != 0xe84c0028)) {
                printk(KERN_ERR "Not a trampoline\n");
                return -EINVAL;
        }
-        /* The bottom half is signed extended */
+        if (module_trampoline_target(mod, tramp, &ptr)) {
-        offset = ((unsigned)((unsigned short)jmp[0]) << 16) +
+                printk(KERN_ERR "Failed to get trampoline target\n");
-                (int)((short)jmp[1]);
-        pr_devel(" %x ", offset);
-        /* get the address this jumps too */
-        tramp = mod->arch.toc + offset + 32;
-        pr_devel("toc: %lx", tramp);
-        if (probe_kernel_read(jmp, (void *)tramp, 8)) {
-                printk(KERN_ERR "Failed to read %lx\n", tramp);
                return -EFAULT;
        }
-        pr_devel(" %08x %08x\n", jmp[0], jmp[1]);
+        pr_devel("trampoline target %lx", ptr);
-#ifdef __LITTLE_ENDIAN__
-        ptr = ((unsigned long)jmp[1] << 32) + jmp[0];
-#else
-        ptr = ((unsigned long)jmp[0] << 32) + jmp[1];
-#endif
        /* This should match what was called */
        if (ptr != ppc_function_entry((void *)addr)) {
-                printk(KERN_ERR "addr does not match %lx\n", ptr);
+                printk(KERN_ERR "addr %lx does not match expected %lx\n",
+                        ptr, ppc_function_entry((void *)addr));
                return -EINVAL;
        }
        /*
-         * We want to nop the line, but the next line is
+         * Our original call site looks like:
-         *  0xe8, 0x41, 0x00, 0x28   ld r2,40(r1)
+         *
-         * This needs to be turned to a nop too.
+         * bl <tramp>
-         */
+         * ld r2,XX(r1)
-        if (probe_kernel_read(&op, (void *)(ip+4), MCOUNT_INSN_SIZE))
+         *
-                return -EFAULT;
+         * Milton Miller pointed out that we can not simply nop the branch.
+         * If a task was preempted when calling a trace function, the nops
-        if (op != 0xe8410028) {
+         * will remove the way to restore the TOC in r2 and the r2 TOC will
-                printk(KERN_ERR "Next line is not ld! (%08x)\n", op);
+         * get corrupted.
-                return -EINVAL;
+         *
-        }
+         * Use a b +8 to jump over the load.
-        /*
-         * Milton Miller pointed out that we can not blindly do nops.
-         * If a task was preempted when calling a trace function,
-         * the nops will remove the way to restore the TOC in r2
-         * and the r2 TOC will get corrupted.
-         */
-        /*
-         * Replace:
-         *   bl <tramp>  <==== will be replaced with "b 1f"
-         *   ld r2,40(r1)
-         *  1:
         */
        op = 0x48000008;        /* b +8 */
@@ -349,19 +292,24 @@ static int
 __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
 {
        unsigned int op[2];
-        unsigned long ip = rec->ip;
+        void *ip = (void *)rec->ip;
        /* read where this goes */
-        if (probe_kernel_read(op, (void *)ip, MCOUNT_INSN_SIZE * 2))
+        if (probe_kernel_read(op, ip, sizeof(op)))
                return -EFAULT;
        /*
-         * It should be pointing to two nops or
+         * We expect to see:
-         *  b +8; ld r2,40(r1)
+         *
+         * b +8
+         * ld r2,XX(r1)
+         *
+         * The load offset is different depending on the ABI. For simplicity
+         * just mask it out when doing the compare.
         */
-        if (((op[0] != 0x48000008) || (op[1] != 0xe8410028)) &&
+        if ((op[0] != 0x48000008) || ((op[1] & 0xffff00000) != 0xe8410000)) {
-            ((op[0] != PPC_INST_NOP) || (op[1] != PPC_INST_NOP))) {
+                printk(KERN_ERR "Unexpected call sequence: %x %x\n",
-                printk(KERN_ERR "Expected NOPs but have %x %x\n", op[0], op[1]);
+                        op[0], op[1]);
                return -EINVAL;
        }
@@ -371,23 +319,16 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
                return -EINVAL;
        }
-        /* create the branch to the trampoline */
+        /* Ensure branch is within 24 bits */
-        op[0] = create_branch((unsigned int *)ip,
+        if (create_branch(ip, rec->arch.mod->arch.tramp, BRANCH_SET_LINK)) {
-                              rec->arch.mod->arch.tramp, BRANCH_SET_LINK);
+                printk(KERN_ERR "Branch out of range");
-        if (!op[0]) {
-                printk(KERN_ERR "REL24 out of range!\n");
                return -EINVAL;
        }
-        /* ld r2,40(r1) */
+        if (patch_branch(ip, rec->arch.mod->arch.tramp, BRANCH_SET_LINK)) {
-        op[1] = 0xe8410028;
+                printk(KERN_ERR "REL24 out of range!\n");
+                return -EINVAL;
-        pr_devel("write to %lx\n", rec->ip);
+        }
-        if (probe_kernel_write((void *)ip, op, MCOUNT_INSN_SIZE * 2))
-                return -EPERM;
-        flush_icache_range(ip, ip + 8);
        return 0;
 }
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index b7363bd42452..a95145d7f61b 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -70,16 +70,15 @@ _GLOBAL(__start)
        /* NOP this out unconditionally */
 BEGIN_FTR_SECTION
        FIXUP_ENDIAN
-        b       .__start_initialization_multiplatform
+        b       __start_initialization_multiplatform
 END_FTR_SECTION(0, 1)
        /* Catch branch to 0 in real mode */
        trap
-        /* Secondary processors spin on this value until it becomes nonzero.
+        /* Secondary processors spin on this value until it becomes non-zero.
-         * When it does it contains the real address of the descriptor
+         * When non-zero, it contains the real address of the function the cpu
-         * of the function that the cpu should jump to to continue
+         * should jump to.
-         * initialization.
         */
        .balign 8
        .globl  __secondary_hold_spinloop
@@ -140,16 +139,15 @@ __secondary_hold:
        tovirt(r26,r26)
 #endif
        /* All secondary cpus wait here until told to start. */
-100:    ld      r4,__secondary_hold_spinloop-_stext(r26)
+100:    ld      r12,__secondary_hold_spinloop-_stext(r26)
-        cmpdi   0,r4,0
+        cmpdi   0,r12,0
        beq     100b
 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
 #ifdef CONFIG_PPC_BOOK3E
-        tovirt(r4,r4)
+        tovirt(r12,r12)
 #endif
-        ld      r4,0(r4)                /* deref function descriptor */
+        mtctr   r12
-        mtctr   r4
        mr      r3,r24
        /*
         * it may be the case that other platforms have r4 right to
@@ -186,16 +184,16 @@ _GLOBAL(generic_secondary_thread_init)
        mr      r24,r3
        /* turn on 64-bit mode */
-        bl      .enable_64b_mode
+        bl      enable_64b_mode
        /* get a valid TOC pointer, wherever we're mapped at */
-        bl      .relative_toc
+        bl      relative_toc
        tovirt(r2,r2)
 #ifdef CONFIG_PPC_BOOK3E
        /* Book3E initialization */
        mr      r3,r24
-        bl      .book3e_secondary_thread_init
+        bl      book3e_secondary_thread_init
 #endif
        b       generic_secondary_common_init
@@ -214,17 +212,17 @@ _GLOBAL(generic_secondary_smp_init)
        mr      r25,r4
        /* turn on 64-bit mode */
-        bl      .enable_64b_mode
+        bl      enable_64b_mode
        /* get a valid TOC pointer, wherever we're mapped at */
-        bl      .relative_toc
+        bl      relative_toc
        tovirt(r2,r2)
 #ifdef CONFIG_PPC_BOOK3E
        /* Book3E initialization */
        mr      r3,r24
        mr      r4,r25
-        bl      .book3e_secondary_core_init
+        bl      book3e_secondary_core_init
 #endif
 generic_secondary_common_init:
@@ -236,7 +234,7 @@ generic_secondary_common_init:
        ld      r13,0(r13)              /* Get base vaddr of paca array  */
 #ifndef CONFIG_SMP
        addi    r13,r13,PACA_SIZE       /* know r13 if used accidentally */
-        b       .kexec_wait             /* wait for next kernel if !SMP  */
+        b       kexec_wait              /* wait for next kernel if !SMP  */
 #else
        LOAD_REG_ADDR(r7, nr_cpu_ids)   /* Load nr_cpu_ids address       */
        lwz     r7,0(r7)                /* also the max paca allocated   */
@@ -250,7 +248,7 @@ generic_secondary_common_init:
        blt     1b
        mr      r3,r24                  /* not found, copy phys to r3    */
-        b       .kexec_wait             /* next kernel might do better   */
+        b       kexec_wait              /* next kernel might do better   */
 2:      SET_PACA(r13)
 #ifdef CONFIG_PPC_BOOK3E
@@ -264,11 +262,13 @@ generic_secondary_common_init:
        /* See if we need to call a cpu state restore handler */
        LOAD_REG_ADDR(r23, cur_cpu_spec)
        ld      r23,0(r23)
-        ld      r23,CPU_SPEC_RESTORE(r23)
+        ld      r12,CPU_SPEC_RESTORE(r23)
-        cmpdi   0,r23,0
+        cmpdi   0,r12,0
        beq     3f
-        ld      r23,0(r23)
+#if !defined(_CALL_ELF) || _CALL_ELF != 2
-        mtctr   r23
+        ld      r12,0(r12)
+#endif
+        mtctr   r12
        bctrl
 3:      LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
@@ -299,7 +299,7 @@ generic_secondary_common_init:
 * Assumes we're mapped EA == RA if the MMU is on.
 */
 #ifdef CONFIG_PPC_BOOK3S
-_STATIC(__mmu_off)
+__mmu_off:
        mfmsr   r3
        andi.   r0,r3,MSR_IR|MSR_DR
        beqlr
@@ -324,12 +324,12 @@ _STATIC(__mmu_off)
 *                 DT block, r4 is a physical pointer to the kernel itself
 *
 */
-_GLOBAL(__start_initialization_multiplatform)
+__start_initialization_multiplatform:
        /* Make sure we are running in 64 bits mode */
-        bl      .enable_64b_mode
+        bl      enable_64b_mode
        /* Get TOC pointer (current runtime address) */
-        bl      .relative_toc
+        bl      relative_toc
        /* find out where we are now */
        bcl     20,31,$+4
@@ -342,7 +342,7 @@ _GLOBAL(__start_initialization_multiplatform)
         */
        cmpldi  cr0,r5,0
        beq     1f
-        b       .__boot_from_prom               /* yes -> prom */
+        b       __boot_from_prom                /* yes -> prom */
 1:
        /* Save parameters */
        mr      r31,r3
@@ -354,8 +354,8 @@ _GLOBAL(__start_initialization_multiplatform)
 #endif
 #ifdef CONFIG_PPC_BOOK3E
-        bl      .start_initialization_book3e
+        bl      start_initialization_book3e
-        b       .__after_prom_start
+        b       __after_prom_start
 #else
        /* Setup some critical 970 SPRs before switching MMU off */
        mfspr   r0,SPRN_PVR
@@ -368,15 +368,15 @@ _GLOBAL(__start_initialization_multiplatform)
        beq     1f
        cmpwi   r0,0x45         /* 970GX */
        bne     2f
-1:      bl      .__cpu_preinit_ppc970
+1:      bl      __cpu_preinit_ppc970
 2:
        /* Switch off MMU if not already off */
-        bl      .__mmu_off
+        bl      __mmu_off
-        b       .__after_prom_start
+        b       __after_prom_start
 #endif /* CONFIG_PPC_BOOK3E */
-_INIT_STATIC(__boot_from_prom)
+__boot_from_prom:
 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
        /* Save parameters */
        mr      r31,r3
@@ -395,7 +395,7 @@ _INIT_STATIC(__boot_from_prom)
 #ifdef CONFIG_RELOCATABLE
        /* Relocate code for where we are now */
        mr      r3,r26
-        bl      .relocate
+        bl      relocate
 #endif
        /* Restore parameters */
@@ -407,14 +407,14 @@ _INIT_STATIC(__boot_from_prom)
        /* Do all of the interaction with OF client interface */
        mr      r8,r26
-        bl      .prom_init
+        bl      prom_init
 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
        /* We never return. We also hit that trap if trying to boot
         * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
        trap
-_STATIC(__after_prom_start)
+__after_prom_start:
 #ifdef CONFIG_RELOCATABLE
        /* process relocations for the final address of the kernel */
        lis     r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
@@ -424,7 +424,7 @@ _STATIC(__after_prom_start)
        bne     1f
        add     r25,r25,r26
 1:      mr      r3,r25
-        bl      .relocate
+        bl      relocate
 #endif
 /*
@@ -464,12 +464,12 @@ _STATIC(__after_prom_start)
        lis     r5,(copy_to_here - _stext)@ha
        addi    r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */
-        bl      .copy_and_flush         /* copy the first n bytes        */
+        bl      copy_and_flush          /* copy the first n bytes        */
                                        /* this includes the code being  */
                                        /* executed here.                */
        addis   r8,r3,(4f - _stext)@ha  /* Jump to the copy of this code */
-        addi    r8,r8,(4f - _stext)@l   /* that we just made */
+        addi    r12,r8,(4f - _stext)@l  /* that we just made */
-        mtctr   r8
+        mtctr   r12
        bctr
 .balign 8
@@ -478,9 +478,9 @@ p_end:	.llong	_end - _stext
 4:      /* Now copy the rest of the kernel up to _end */
        addis   r5,r26,(p_end - _stext)@ha
        ld      r5,(p_end - _stext)@l(r5)       /* get _end */
-5:      bl      .copy_and_flush         /* copy the rest */
+5:      bl      copy_and_flush          /* copy the rest */
-9:      b       .start_here_multiplatform
+9:      b       start_here_multiplatform
 /*
 * Copy routine used to copy the kernel to start at physical address 0
@@ -544,7 +544,7 @@ __secondary_start_pmac_0:
        
 _GLOBAL(pmac_secondary_start)
        /* turn on 64-bit mode */
-        bl      .enable_64b_mode
+        bl      enable_64b_mode
        li      r0,0
        mfspr   r3,SPRN_HID4
@@ -556,11 +556,11 @@ _GLOBAL(pmac_secondary_start)
        slbia
        /* get TOC pointer (real address) */
-        bl      .relative_toc
+        bl      relative_toc
        tovirt(r2,r2)
        /* Copy some CPU settings from CPU 0 */
-        bl      .__restore_cpu_ppc970
+        bl      __restore_cpu_ppc970
        /* pSeries do that early though I don't think we really need it */
        mfmsr   r3
@@ -619,7 +619,7 @@ __secondary_start:
        std     r14,PACAKSAVE(r13)
        /* Do early setup for that CPU (stab, slb, hash table pointer) */
-        bl      .early_setup_secondary
+        bl      early_setup_secondary
        /*
         * setup the new stack pointer, but *don't* use this until
@@ -639,7 +639,7 @@ __secondary_start:
        stb     r0,PACAIRQHAPPENED(r13)
        /* enable MMU and jump to start_secondary */
-        LOAD_REG_ADDR(r3, .start_secondary_prolog)
+        LOAD_REG_ADDR(r3, start_secondary_prolog)
        LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
        mtspr   SPRN_SRR0,r3
@@ -652,11 +652,11 @@ __secondary_start:
 * zero the stack back-chain pointer and get the TOC virtual address
 * before going into C code.
 */
-_GLOBAL(start_secondary_prolog)
+start_secondary_prolog:
        ld      r2,PACATOC(r13)
        li      r3,0
        std     r3,0(r1)                /* Zero the stack frame pointer */
-        bl      .start_secondary
+        bl      start_secondary
        b       .
 /*
 * Reset stack pointer and call start_secondary
@@ -667,14 +667,14 @@ _GLOBAL(start_secondary_resume)
        ld      r1,PACAKSAVE(r13)       /* Reload kernel stack pointer */
        li      r3,0
        std     r3,0(r1)                /* Zero the stack frame pointer */
-        bl      .start_secondary
+        bl      start_secondary
        b       .
 #endif
 /*
 * This subroutine clobbers r11 and r12
 */
-_GLOBAL(enable_64b_mode)
+enable_64b_mode:
        mfmsr   r11                     /* grab the current MSR */
 #ifdef CONFIG_PPC_BOOK3E
        oris    r11,r11,0x8000          /* CM bit set, we'll set ICM later */
@@ -715,9 +715,9 @@ p_toc:	.llong	__toc_start + 0x8000 - 0b
 /*
 * This is where the main kernel code starts.
 */
-_INIT_STATIC(start_here_multiplatform)
+start_here_multiplatform:
        /* set up the TOC */
-        bl      .relative_toc
+        bl      relative_toc
        tovirt(r2,r2)
        /* Clear out the BSS. It may have been done in prom_init,
@@ -776,9 +776,9 @@ _INIT_STATIC(start_here_multiplatform)
        /* Restore parameters passed from prom_init/kexec */
        mr      r3,r31
-        bl      .early_setup            /* also sets r13 and SPRG_PACA */
+        bl      early_setup             /* also sets r13 and SPRG_PACA */
-        LOAD_REG_ADDR(r3, .start_here_common)
+        LOAD_REG_ADDR(r3, start_here_common)
        ld      r4,PACAKMSR(r13)
        mtspr   SPRN_SRR0,r3
        mtspr   SPRN_SRR1,r4
@@ -786,7 +786,8 @@ _INIT_STATIC(start_here_multiplatform)
        b       .       /* prevent speculative execution */
        
        /* This is where all platforms converge execution */
-_INIT_GLOBAL(start_here_common)
+start_here_common:
        /* relocation is on at this point */
        std     r1,PACAKSAVE(r13)
@@ -794,7 +795,7 @@ _INIT_GLOBAL(start_here_common)
        ld      r2,PACATOC(r13)
        /* Do more system initializations in virtual mode */
-        bl      .setup_system
+        bl      setup_system
        /* Mark interrupts soft and hard disabled (they might be enabled
         * in the PACA when doing hotplug)
@@ -805,7 +806,7 @@ _INIT_GLOBAL(start_here_common)
        stb     r0,PACAIRQHAPPENED(r13)
        /* Generic kernel entry */
-        bl      .start_kernel
+        bl      start_kernel
        /* Not reached */
        BUG_OPCODE
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
index b0a1792279bb..0bb5918faaaf 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -72,7 +72,7 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
         * If so, DABR will be populated in single_step_dabr_instruction().
         */
        if (current->thread.last_hit_ubp != bp)
-                set_breakpoint(info);
+                __set_breakpoint(info);
        return 0;
 }
@@ -198,7 +198,7 @@ void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
        info = counter_arch_bp(tsk->thread.last_hit_ubp);
        regs->msr &= ~MSR_SE;
-        set_breakpoint(info);
+        __set_breakpoint(info);
        tsk->thread.last_hit_ubp = NULL;
 }
@@ -284,7 +284,7 @@ int __kprobes hw_breakpoint_handler(struct die_args *args)
        if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
                perf_bp_event(bp, regs);
-        set_breakpoint(info);
+        __set_breakpoint(info);
 out:
        rcu_read_unlock();
        return rc;
@@ -316,7 +316,7 @@ int __kprobes single_step_dabr_instruction(struct die_args *args)
        if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
                perf_bp_event(bp, regs);
-        set_breakpoint(info);
+        __set_breakpoint(info);
        current->thread.last_hit_ubp = NULL;
        /*
diff --git a/arch/powerpc/kernel/idle_book3e.S b/arch/powerpc/kernel/idle_book3e.S
index bfb73cc209ce..48c21acef915 100644
--- a/arch/powerpc/kernel/idle_book3e.S
+++ b/arch/powerpc/kernel/idle_book3e.S
@@ -43,7 +43,7 @@ _GLOBAL(\name)
         */
 #ifdef CONFIG_TRACE_IRQFLAGS
        stdu    r1,-128(r1)
-        bl      .trace_hardirqs_on
+        bl      trace_hardirqs_on
        addi    r1,r1,128
 #endif
        li      r0,1
diff --git a/arch/powerpc/kernel/idle_power4.S b/arch/powerpc/kernel/idle_power4.S
index e3edaa189911..f57a19348bdd 100644
--- a/arch/powerpc/kernel/idle_power4.S
+++ b/arch/powerpc/kernel/idle_power4.S
@@ -46,7 +46,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
        mflr    r0
        std     r0,16(r1)
        stdu    r1,-128(r1)
-        bl      .trace_hardirqs_on
+        bl      trace_hardirqs_on
        addi    r1,r1,128
        ld      r0,16(r1)
        mtlr    r0
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index c3ab86975614..2480256272d4 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -39,6 +39,10 @@
 * Pass requested state in r3:
 *      0 - nap
 *      1 - sleep
+ *
+ * To check IRQ_HAPPENED in r4
+ *      0 - don't check
+ *      1 - check
 */
 _GLOBAL(power7_powersave_common)
        /* Use r3 to pass state nap/sleep/winkle */
@@ -58,7 +62,7 @@ _GLOBAL(power7_powersave_common)
        /* Make sure FPU, VSX etc... are flushed as we may lose
         * state when going to nap mode
         */
-        bl      .discard_lazy_cpu_state
+        bl      discard_lazy_cpu_state
 #endif /* CONFIG_SMP */
        /* Hard disable interrupts */
@@ -71,6 +75,8 @@ _GLOBAL(power7_powersave_common)
        lbz     r0,PACAIRQHAPPENED(r13)
        cmpwi   cr0,r0,0
        beq     1f
+        cmpwi   cr0,r4,0
+        beq     1f
        addi    r1,r1,INT_FRAME_SIZE
        ld      r0,16(r1)
        mtlr    r0
@@ -114,15 +120,18 @@ _GLOBAL(power7_idle)
        lwz     r4,ADDROFF(powersave_nap)(r3)
        cmpwi   0,r4,0
        beqlr
+        li      r3, 1
        /* fall through */
 _GLOBAL(power7_nap)
+        mr      r4,r3
        li      r3,0
        b       power7_powersave_common
        /* No return */
 _GLOBAL(power7_sleep)
        li      r3,1
+        li      r4,0
        b       power7_powersave_common
        /* No return */
@@ -168,7 +177,7 @@ _GLOBAL(power7_wakeup_loss)
 _GLOBAL(power7_wakeup_noloss)
        lbz     r0,PACA_NAPSTATELOST(r13)
        cmpwi   r0,0
-        bne     .power7_wakeup_loss
+        bne     power7_wakeup_loss
        ld      r1,PACAR1(r13)
        ld      r4,_MSR(r1)
        ld      r5,_NIP(r1)
diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c
index 40bd7bd4e19a..936258881c98 100644
--- a/arch/powerpc/kernel/legacy_serial.c
+++ b/arch/powerpc/kernel/legacy_serial.c
@@ -48,6 +48,9 @@ static struct of_device_id legacy_serial_parents[] __initdata = {
 static unsigned int legacy_serial_count;
 static int legacy_serial_console = -1;
+static const upf_t legacy_port_flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+        UPF_SHARE_IRQ | UPF_FIXED_PORT;
 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
 {
        unsigned int tmp;
@@ -71,8 +74,9 @@ static int __init add_legacy_port(struct device_node *np, int want_index,
                                  phys_addr_t taddr, unsigned long irq,
                                  upf_t flags, int irq_check_parent)
 {
-        const __be32 *clk, *spd;
+        const __be32 *clk, *spd, *rs;
        u32 clock = BASE_BAUD * 16;
+        u32 shift = 0;
        int index;
        /* get clock freq. if present */
@@ -83,6 +87,11 @@ static int __init add_legacy_port(struct device_node *np, int want_index,
        /* get default speed if present */
        spd = of_get_property(np, "current-speed", NULL);
+        /* get register shift if present */
+        rs = of_get_property(np, "reg-shift", NULL);
+        if (rs && *rs)
+                shift = be32_to_cpup(rs);
        /* If we have a location index, then try to use it */
        if (want_index >= 0 && want_index < MAX_LEGACY_SERIAL_PORTS)
                index = want_index;
@@ -126,6 +135,7 @@ static int __init add_legacy_port(struct device_node *np, int want_index,
        legacy_serial_ports[index].uartclk = clock;
        legacy_serial_ports[index].irq = irq;
        legacy_serial_ports[index].flags = flags;
+        legacy_serial_ports[index].regshift = shift;
        legacy_serial_infos[index].taddr = taddr;
        legacy_serial_infos[index].np = of_node_get(np);
        legacy_serial_infos[index].clock = clock;
@@ -153,8 +163,6 @@ static int __init add_legacy_soc_port(struct device_node *np,
 {
        u64 addr;
        const __be32 *addrp;
-        upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ
-                | UPF_FIXED_PORT;
        struct device_node *tsi = of_get_parent(np);
        /* We only support ports that have a clock frequency properly
@@ -163,9 +171,8 @@ static int __init add_legacy_soc_port(struct device_node *np,
        if (of_get_property(np, "clock-frequency", NULL) == NULL)
                return -1;
-        /* if reg-shift or offset, don't try to use it */
+        /* if reg-offset don't try to use it */
-        if ((of_get_property(np, "reg-shift", NULL) != NULL) ||
+        if ((of_get_property(np, "reg-offset", NULL) != NULL))
-                (of_get_property(np, "reg-offset", NULL) != NULL))
                return -1;
        /* if rtas uses this device, don't try to use it as well */
@@ -185,9 +192,11 @@ static int __init add_legacy_soc_port(struct device_node *np,
         * IO port value. It will be fixed up later along with the irq
         */
        if (tsi && !strcmp(tsi->type, "tsi-bridge"))
-                return add_legacy_port(np, -1, UPIO_TSI, addr, addr, NO_IRQ, flags, 0);
+                return add_legacy_port(np, -1, UPIO_TSI, addr, addr,
+                                       NO_IRQ, legacy_port_flags, 0);
        else
-                return add_legacy_port(np, -1, UPIO_MEM, addr, addr, NO_IRQ, flags, 0);
+                return add_legacy_port(np, -1, UPIO_MEM, addr, addr,
+                                       NO_IRQ, legacy_port_flags, 0);
 }
 static int __init add_legacy_isa_port(struct device_node *np,
@@ -233,7 +242,7 @@ static int __init add_legacy_isa_port(struct device_node *np,
        /* Add port, irq will be dealt with later */
        return add_legacy_port(np, index, UPIO_PORT, be32_to_cpu(reg[1]),
-                               taddr, NO_IRQ, UPF_BOOT_AUTOCONF, 0);
+                               taddr, NO_IRQ, legacy_port_flags, 0);
 }
@@ -306,7 +315,7 @@ static int __init add_legacy_pci_port(struct device_node *np,
         * IO port value. It will be fixed up later along with the irq
         */
        return add_legacy_port(np, index, iotype, base, addr, NO_IRQ,
-                               UPF_BOOT_AUTOCONF, np != pci_dev);
+                               legacy_port_flags, np != pci_dev);
 }
 #endif
@@ -315,17 +324,20 @@ static void __init setup_legacy_serial_console(int console)
        struct legacy_serial_info *info = &legacy_serial_infos[console];
        struct plat_serial8250_port *port = &legacy_serial_ports[console];
        void __iomem *addr;
+        unsigned int stride;
+        stride = 1 << port->regshift;
        /* Check if a translated MMIO address has been found */
        if (info->taddr) {
                addr = ioremap(info->taddr, 0x1000);
                if (addr == NULL)
                        return;
-                udbg_uart_init_mmio(addr, 1);
+                udbg_uart_init_mmio(addr, stride);
        } else {
                /* Check if it's PIO and we support untranslated PIO */
                if (port->iotype == UPIO_PORT && isa_io_special)
-                        udbg_uart_init_pio(port->iobase, 1);
+                        udbg_uart_init_pio(port->iobase, stride);
                else
                        return;
        }
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 3d0249599d52..4e314b90c75d 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -34,7 +34,7 @@ _GLOBAL(call_do_softirq)
        std     r0,16(r1)
        stdu    r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
        mr      r1,r3
-        bl      .__do_softirq
+        bl      __do_softirq
        ld      r1,0(r1)
        ld      r0,16(r1)
        mtlr    r0
@@ -45,7 +45,7 @@ _GLOBAL(call_do_irq)
        std     r0,16(r1)
        stdu    r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
        mr      r1,r4
-        bl      .__do_irq
+        bl      __do_irq
        ld      r1,0(r1)
        ld      r0,16(r1)
        mtlr    r0
@@ -506,7 +506,7 @@ _GLOBAL(kexec_smp_wait)
        stb     r4,PACAKEXECSTATE(r13)
        SYNC
-        b       .kexec_wait
+        b       kexec_wait
 /*
 * switch to real mode (turn mmu off)
@@ -576,7 +576,7 @@ _GLOBAL(kexec_sequence)
        /* copy dest pages, flush whole dest image */
        mr      r3,r29
-        bl      .kexec_copy_flush       /* (image) */
+        bl      kexec_copy_flush        /* (image) */
        /* turn off mmu */
        bl      real_mode
@@ -586,7 +586,7 @@ _GLOBAL(kexec_sequence)
        mr      r4,r30          /* start, aka phys mem offset */
        li      r5,0x100
        li      r6,0
-        bl      .copy_and_flush /* (dest, src, copy limit, start offset) */
+        bl      copy_and_flush  /* (dest, src, copy limit, start offset) */
 1:      /* assume normal blr return */
        /* release other cpus to the new kernel secondary start at 0x60 */
@@ -595,8 +595,12 @@ _GLOBAL(kexec_sequence)
        stw     r6,kexec_flag-1b(5)
        /* clear out hardware hash page table and tlb */
-        ld      r5,0(r27)               /* deref function descriptor */
+#if !defined(_CALL_ELF) || _CALL_ELF != 2
-        mtctr   r5
+        ld      r12,0(r27)              /* deref function descriptor */
+#else
+        mr      r12,r27
+#endif
+        mtctr   r12
        bctrl                           /* ppc_md.hpte_clear_all(void); */
 /*
@@ -630,3 +634,31 @@ _GLOBAL(kexec_sequence)
        li      r5,0
        blr     /* image->start(physid, image->start, 0); */
 #endif /* CONFIG_KEXEC */
+#ifdef CONFIG_MODULES
+#if defined(_CALL_ELF) && _CALL_ELF == 2
+#ifdef CONFIG_MODVERSIONS
+.weak __crc_TOC.
+.section "___kcrctab+TOC.","a"
+.globl __kcrctab_TOC.
+__kcrctab_TOC.:
+        .llong  __crc_TOC.
+#endif
+/*
+ * Export a fake .TOC. since both modpost and depmod will complain otherwise.
+ * Both modpost and depmod strip the leading . so we do the same here.
+ */
+.section "__ksymtab_strings","a"
+__kstrtab_TOC.:
+        .asciz "TOC."
+.section "___ksymtab+TOC.","a"
+/* This symbol name is important: it's used by modpost to find exported syms */
+.globl __ksymtab_TOC.
+__ksymtab_TOC.:
+        .llong 0 /* .value */
+        .llong __kstrtab_TOC.
+#endif /* ELFv2 */
+#endif /* MODULES */
diff --git a/arch/powerpc/kernel/module_64.c b/arch/powerpc/kernel/module_64.c
index 12664c130d73..077d2ce6c5a7 100644
--- a/arch/powerpc/kernel/module_64.c
+++ b/arch/powerpc/kernel/module_64.c
@@ -22,6 +22,7 @@
 #include <linux/vmalloc.h>
 #include <linux/ftrace.h>
 #include <linux/bug.h>
+#include <linux/uaccess.h>
 #include <asm/module.h>
 #include <asm/firmware.h>
 #include <asm/code-patching.h>
@@ -41,46 +42,170 @@
 #define DEBUGP(fmt , ...)
 #endif
+#if defined(_CALL_ELF) && _CALL_ELF == 2
+#define R2_STACK_OFFSET 24
+/* An address is simply the address of the function. */
+typedef unsigned long func_desc_t;
+static func_desc_t func_desc(unsigned long addr)
+{
+        return addr;
+}
+static unsigned long func_addr(unsigned long addr)
+{
+        return addr;
+}
+static unsigned long stub_func_addr(func_desc_t func)
+{
+        return func;
+}
+/* PowerPC64 specific values for the Elf64_Sym st_other field.  */
+#define STO_PPC64_LOCAL_BIT     5
+#define STO_PPC64_LOCAL_MASK    (7 << STO_PPC64_LOCAL_BIT)
+#define PPC64_LOCAL_ENTRY_OFFSET(other)                                 \
+ (((1 << (((other) & STO_PPC64_LOCAL_MASK) >> STO_PPC64_LOCAL_BIT)) >> 2) << 2)
+static unsigned int local_entry_offset(const Elf64_Sym *sym)
+{
+        /* sym->st_other indicates offset to local entry point
+         * (otherwise it will assume r12 is the address of the start
+         * of function and try to derive r2 from it). */
+        return PPC64_LOCAL_ENTRY_OFFSET(sym->st_other);
+}
+#else
+#define R2_STACK_OFFSET 40
+/* An address is address of the OPD entry, which contains address of fn. */
+typedef struct ppc64_opd_entry func_desc_t;
+static func_desc_t func_desc(unsigned long addr)
+{
+        return *(struct ppc64_opd_entry *)addr;
+}
+static unsigned long func_addr(unsigned long addr)
+{
+        return func_desc(addr).funcaddr;
+}
+static unsigned long stub_func_addr(func_desc_t func)
+{
+        return func.funcaddr;
+}
+static unsigned int local_entry_offset(const Elf64_Sym *sym)
+{
+        return 0;
+}
+#endif
 /* Like PPC32, we need little trampolines to do > 24-bit jumps (into
   the kernel itself).  But on PPC64, these need to be used for every
   jump, actually, to reset r2 (TOC+0x8000). */
 struct ppc64_stub_entry
 {
-        /* 28 byte jump instruction sequence (7 instructions) */
+        /* 28 byte jump instruction sequence (7 instructions). We only
-        unsigned char jump[28];
+         * need 6 instructions on ABIv2 but we always allocate 7 so
-        unsigned char unused[4];
+         * so we don't have to modify the trampoline load instruction. */
+        u32 jump[7];
+        u32 unused;
        /* Data for the above code */
-        struct ppc64_opd_entry opd;
+        func_desc_t funcdata;
 };
-/* We use a stub to fix up r2 (TOC ptr) and to jump to the (external)
+/*
-   function which may be more than 24-bits away.  We could simply
+ * PPC64 uses 24 bit jumps, but we need to jump into other modules or
-   patch the new r2 value and function pointer into the stub, but it's
+ * the kernel which may be further.  So we jump to a stub.
-   significantly shorter to put these values at the end of the stub
+ *
-   code, and patch the stub address (32-bits relative to the TOC ptr,
+ * For ELFv1 we need to use this to set up the new r2 value (aka TOC
-   r2) into the stub. */
+ * pointer).  For ELFv2 it's the callee's responsibility to set up the
-static struct ppc64_stub_entry ppc64_stub =
+ * new r2, but for both we need to save the old r2.
-{ .jump = {
+ *
-#ifdef __LITTLE_ENDIAN__
+ * We could simply patch the new r2 value and function pointer into
-        0x00, 0x00, 0x82, 0x3d, /* addis   r12,r2, <high> */
+ * the stub, but it's significantly shorter to put these values at the
-        0x00, 0x00, 0x8c, 0x39, /* addi    r12,r12, <low> */
+ * end of the stub code, and patch the stub address (32-bits relative
-        /* Save current r2 value in magic place on the stack. */
+ * to the TOC ptr, r2) into the stub.
-        0x28, 0x00, 0x41, 0xf8, /* std     r2,40(r1) */
+ */
-        0x20, 0x00, 0x6c, 0xe9, /* ld      r11,32(r12) */
-        0x28, 0x00, 0x4c, 0xe8, /* ld      r2,40(r12) */
+static u32 ppc64_stub_insns[] = {
-        0xa6, 0x03, 0x69, 0x7d, /* mtctr   r11 */
+        0x3d620000,                     /* addis   r11,r2, <high> */
-        0x20, 0x04, 0x80, 0x4e  /* bctr */
+        0x396b0000,                     /* addi    r11,r11, <low> */
-#else
-        0x3d, 0x82, 0x00, 0x00, /* addis   r12,r2, <high> */
-        0x39, 0x8c, 0x00, 0x00, /* addi    r12,r12, <low> */
        /* Save current r2 value in magic place on the stack. */
-        0xf8, 0x41, 0x00, 0x28, /* std     r2,40(r1) */
+        0xf8410000|R2_STACK_OFFSET,     /* std     r2,R2_STACK_OFFSET(r1) */
-        0xe9, 0x6c, 0x00, 0x20, /* ld      r11,32(r12) */
+        0xe98b0020,                     /* ld      r12,32(r11) */
-        0xe8, 0x4c, 0x00, 0x28, /* ld      r2,40(r12) */
+#if !defined(_CALL_ELF) || _CALL_ELF != 2
-        0x7d, 0x69, 0x03, 0xa6, /* mtctr   r11 */
+        /* Set up new r2 from function descriptor */
-        0x4e, 0x80, 0x04, 0x20  /* bctr */
+        0xe84b0028,                     /* ld      r2,40(r11) */
+#endif
+        0x7d8903a6,                     /* mtctr   r12 */
+        0x4e800420                      /* bctr */
+};
+#ifdef CONFIG_DYNAMIC_FTRACE
+static u32 ppc64_stub_mask[] = {
+        0xffff0000,
+        0xffff0000,
+        0xffffffff,
+        0xffffffff,
+#if !defined(_CALL_ELF) || _CALL_ELF != 2
+        0xffffffff,
+#endif
+        0xffffffff,
+        0xffffffff
+};
+bool is_module_trampoline(u32 *p)
+{
+        unsigned int i;
+        u32 insns[ARRAY_SIZE(ppc64_stub_insns)];
+        BUILD_BUG_ON(sizeof(ppc64_stub_insns) != sizeof(ppc64_stub_mask));
+        if (probe_kernel_read(insns, p, sizeof(insns)))
+                return -EFAULT;
+        for (i = 0; i < ARRAY_SIZE(ppc64_stub_insns); i++) {
+                u32 insna = insns[i];
+                u32 insnb = ppc64_stub_insns[i];
+                u32 mask = ppc64_stub_mask[i];
+                if ((insna & mask) != (insnb & mask))
+                        return false;
+        }
+        return true;
+}
+int module_trampoline_target(struct module *mod, u32 *trampoline,
+                             unsigned long *target)
+{
+        u32 buf[2];
+        u16 upper, lower;
+        long offset;
+        void *toc_entry;
+        if (probe_kernel_read(buf, trampoline, sizeof(buf)))
+                return -EFAULT;
+        upper = buf[0] & 0xffff;
+        lower = buf[1] & 0xffff;
+        /* perform the addis/addi, both signed */
+        offset = ((short)upper << 16) + (short)lower;
+        /*
+         * Now get the address this trampoline jumps to. This
+         * is always 32 bytes into our trampoline stub.
+         */
+        toc_entry = (void *)mod->arch.toc + offset + 32;
+        if (probe_kernel_read(target, toc_entry, sizeof(*target)))
+                return -EFAULT;
+        return 0;
+}
 #endif
-} };
 /* Count how many different 24-bit relocations (different symbol,
   different addend) */
@@ -183,6 +308,7 @@ static unsigned long get_stubs_size(const Elf64_Ehdr *hdr,
        return relocs * sizeof(struct ppc64_stub_entry);
 }
+/* Still needed for ELFv2, for .TOC. */
 static void dedotify_versions(struct modversion_info *vers,
                              unsigned long size)
 {
@@ -193,7 +319,7 @@ static void dedotify_versions(struct modversion_info *vers,
                        memmove(vers->name, vers->name+1, strlen(vers->name));
 }
-/* Undefined symbols which refer to .funcname, hack to funcname */
+/* Undefined symbols which refer to .funcname, hack to funcname (or .TOC.) */
 static void dedotify(Elf64_Sym *syms, unsigned int numsyms, char *strtab)
 {
        unsigned int i;
@@ -207,6 +333,24 @@ static void dedotify(Elf64_Sym *syms, unsigned int numsyms, char *strtab)
        }
 }
+static Elf64_Sym *find_dot_toc(Elf64_Shdr *sechdrs,
+                               const char *strtab,
+                               unsigned int symindex)
+{
+        unsigned int i, numsyms;
+        Elf64_Sym *syms;
+        syms = (Elf64_Sym *)sechdrs[symindex].sh_addr;
+        numsyms = sechdrs[symindex].sh_size / sizeof(Elf64_Sym);
+        for (i = 1; i < numsyms; i++) {
+                if (syms[i].st_shndx == SHN_UNDEF
+                    && strcmp(strtab + syms[i].st_name, "TOC.") == 0)
+                        return &syms[i];
+        }
+        return NULL;
+}
 int module_frob_arch_sections(Elf64_Ehdr *hdr,
                              Elf64_Shdr *sechdrs,
                              char *secstrings,
@@ -271,21 +415,12 @@ static inline unsigned long my_r2(Elf64_Shdr *sechdrs, struct module *me)
 /* Patch stub to reference function and correct r2 value. */
 static inline int create_stub(Elf64_Shdr *sechdrs,
                              struct ppc64_stub_entry *entry,
-                              struct ppc64_opd_entry *opd,
+                              unsigned long addr,
                              struct module *me)
 {
-        Elf64_Half *loc1, *loc2;
        long reladdr;
-        *entry = ppc64_stub;
+        memcpy(entry->jump, ppc64_stub_insns, sizeof(ppc64_stub_insns));
-#ifdef __LITTLE_ENDIAN__
-        loc1 = (Elf64_Half *)&entry->jump[0];
-        loc2 = (Elf64_Half *)&entry->jump[4];
-#else
-        loc1 = (Elf64_Half *)&entry->jump[2];
-        loc2 = (Elf64_Half *)&entry->jump[6];
-#endif
        /* Stub uses address relative to r2. */
        reladdr = (unsigned long)entry - my_r2(sechdrs, me);
@@ -296,35 +431,33 @@ static inline int create_stub(Elf64_Shdr *sechdrs,
        }
        DEBUGP("Stub %p get data from reladdr %li\n", entry, reladdr);
-        *loc1 = PPC_HA(reladdr);
+        entry->jump[0] |= PPC_HA(reladdr);
-        *loc2 = PPC_LO(reladdr);
+        entry->jump[1] |= PPC_LO(reladdr);
-        entry->opd.funcaddr = opd->funcaddr;
+        entry->funcdata = func_desc(addr);
-        entry->opd.r2 = opd->r2;
        return 1;
 }
-/* Create stub to jump to function described in this OPD: we need the
+/* Create stub to jump to function described in this OPD/ptr: we need the
   stub to set up the TOC ptr (r2) for the function. */
 static unsigned long stub_for_addr(Elf64_Shdr *sechdrs,
-                                   unsigned long opdaddr,
+                                   unsigned long addr,
                                   struct module *me)
 {
        struct ppc64_stub_entry *stubs;
-        struct ppc64_opd_entry *opd = (void *)opdaddr;
        unsigned int i, num_stubs;
        num_stubs = sechdrs[me->arch.stubs_section].sh_size / sizeof(*stubs);
        /* Find this stub, or if that fails, the next avail. entry */
        stubs = (void *)sechdrs[me->arch.stubs_section].sh_addr;
-        for (i = 0; stubs[i].opd.funcaddr; i++) {
+        for (i = 0; stub_func_addr(stubs[i].funcdata); i++) {
                BUG_ON(i >= num_stubs);
-                if (stubs[i].opd.funcaddr == opd->funcaddr)
+                if (stub_func_addr(stubs[i].funcdata) == func_addr(addr))
                        return (unsigned long)&stubs[i];
        }
-        if (!create_stub(sechdrs, &stubs[i], opd, me))
+        if (!create_stub(sechdrs, &stubs[i], addr, me))
                return 0;
        return (unsigned long)&stubs[i];
@@ -339,7 +472,8 @@ static int restore_r2(u32 *instruction, struct module *me)
                       me->name, *instruction);
                return 0;
        }
-        *instruction = 0xe8410028;      /* ld r2,40(r1) */
+        /* ld r2,R2_STACK_OFFSET(r1) */
+        *instruction = 0xe8410000 | R2_STACK_OFFSET;
        return 1;
 }
@@ -357,6 +491,17 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
        DEBUGP("Applying ADD relocate section %u to %u\n", relsec,
               sechdrs[relsec].sh_info);
+        /* First time we're called, we can fix up .TOC. */
+        if (!me->arch.toc_fixed) {
+                sym = find_dot_toc(sechdrs, strtab, symindex);
+                /* It's theoretically possible that a module doesn't want a
+                 * .TOC. so don't fail it just for that. */
+                if (sym)
+                        sym->st_value = my_r2(sechdrs, me);
+                me->arch.toc_fixed = true;
+        }
        for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rela); i++) {
                /* This is where to make the change */
                location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
@@ -453,7 +598,8 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
                                        return -ENOENT;
                                if (!restore_r2((u32 *)location + 1, me))
                                        return -ENOEXEC;
-                        }
+                        } else
+                                value += local_entry_offset(sym);
                        /* Convert value to relative */
                        value -= (unsigned long)location;
@@ -474,6 +620,31 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
                        *location = value - (unsigned long)location;
                        break;
+                case R_PPC64_TOCSAVE:
+                        /*
+                         * Marker reloc indicates we don't have to save r2.
+                         * That would only save us one instruction, so ignore
+                         * it.
+                         */
+                        break;
+                case R_PPC64_REL16_HA:
+                        /* Subtract location pointer */
+                        value -= (unsigned long)location;
+                        value = ((value + 0x8000) >> 16);
+                        *((uint16_t *) location)
+                                = (*((uint16_t *) location) & ~0xffff)
+                                | (value & 0xffff);
+                        break;
+                case R_PPC64_REL16_LO:
+                        /* Subtract location pointer */
+                        value -= (unsigned long)location;
+                        *((uint16_t *) location)
+                                = (*((uint16_t *) location) & ~0xffff)
+                                | (value & 0xffff);
+                        break;
                default:
                        printk("%s: Unknown ADD relocation: %lu\n",
                               me->name,
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 24d342e91790..b49c72fd7f16 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -21,6 +21,7 @@
 #include <linux/string.h>
 #include <linux/init.h>
 #include <linux/bootmem.h>
+#include <linux/delay.h>
 #include <linux/export.h>
 #include <linux/of_address.h>
 #include <linux/of_pci.h>
@@ -120,6 +121,25 @@ resource_size_t pcibios_window_alignment(struct pci_bus *bus,
        return 1;
 }
+void pcibios_reset_secondary_bus(struct pci_dev *dev)
+{
+        u16 ctrl;
+        if (ppc_md.pcibios_reset_secondary_bus) {
+                ppc_md.pcibios_reset_secondary_bus(dev);
+                return;
+        }
+        pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
+        ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
+        pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
+        msleep(2);
+        ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
+        pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
+        ssleep(1);
+}
 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
 {
 #ifdef CONFIG_PPC64
@@ -646,60 +666,36 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar,
 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
                                  struct device_node *dev, int primary)
 {
-        const __be32 *ranges;
-        int rlen;
-        int pna = of_n_addr_cells(dev);
-        int np = pna + 5;
        int memno = 0;
-        u32 pci_space;
-        unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
        struct resource *res;
+        struct of_pci_range range;
+        struct of_pci_range_parser parser;
        printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
               dev->full_name, primary ? "(primary)" : "");
-        /* Get ranges property */
+        /* Check for ranges property */
-        ranges = of_get_property(dev, "ranges", &rlen);
+        if (of_pci_range_parser_init(&parser, dev))
-        if (ranges == NULL)
                return;
        /* Parse it */
-        while ((rlen -= np * 4) >= 0) {
+        for_each_of_pci_range(&parser, &range) {
-                /* Read next ranges element */
-                pci_space = of_read_number(ranges, 1);
-                pci_addr = of_read_number(ranges + 1, 2);
-                cpu_addr = of_translate_address(dev, ranges + 3);
-                size = of_read_number(ranges + pna + 3, 2);
-                ranges += np;
                /* If we failed translation or got a zero-sized region
                 * (some FW try to feed us with non sensical zero sized regions
                 * such as power3 which look like some kind of attempt at exposing
                 * the VGA memory hole)
                 */
-                if (cpu_addr == OF_BAD_ADDR || size == 0)
+                if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
                        continue;
-                /* Now consume following elements while they are contiguous */
-                for (; rlen >= np * sizeof(u32);
-                     ranges += np, rlen -= np * 4) {
-                        if (of_read_number(ranges, 1) != pci_space)
-                                break;
-                        pci_next = of_read_number(ranges + 1, 2);
-                        cpu_next = of_translate_address(dev, ranges + 3);
-                        if (pci_next != pci_addr + size ||
-                            cpu_next != cpu_addr + size)
-                                break;
-                        size += of_read_number(ranges + pna + 3, 2);
-                }
                /* Act based on address space type */
                res = NULL;
-                switch ((pci_space >> 24) & 0x3) {
+                switch (range.flags & IORESOURCE_TYPE_BITS) {
-                case 1:         /* PCI IO space */
+                case IORESOURCE_IO:
                        printk(KERN_INFO
                               "  IO 0x%016llx..0x%016llx -> 0x%016llx\n",
-                               cpu_addr, cpu_addr + size - 1, pci_addr);
+                               range.cpu_addr, range.cpu_addr + range.size - 1,
+                               range.pci_addr);
                        /* We support only one IO range */
                        if (hose->pci_io_size) {
@@ -709,11 +705,12 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
                        }
 #ifdef CONFIG_PPC32
                        /* On 32 bits, limit I/O space to 16MB */
-                        if (size > 0x01000000)
+                        if (range.size > 0x01000000)
-                                size = 0x01000000;
+                                range.size = 0x01000000;
                        /* 32 bits needs to map IOs here */
-                        hose->io_base_virt = ioremap(cpu_addr, size);
+                        hose->io_base_virt = ioremap(range.cpu_addr,
+                                                range.size);
                        /* Expect trouble if pci_addr is not 0 */
                        if (primary)
@@ -723,20 +720,20 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
                        /* pci_io_size and io_base_phys always represent IO
                         * space starting at 0 so we factor in pci_addr
                         */
-                        hose->pci_io_size = pci_addr + size;
+                        hose->pci_io_size = range.pci_addr + range.size;
-                        hose->io_base_phys = cpu_addr - pci_addr;
+                        hose->io_base_phys = range.cpu_addr - range.pci_addr;
                        /* Build resource */
                        res = &hose->io_resource;
-                        res->flags = IORESOURCE_IO;
+                        range.cpu_addr = range.pci_addr;
-                        res->start = pci_addr;
                        break;
-                case 2:         /* PCI Memory space */
+                case IORESOURCE_MEM:
-                case 3:         /* PCI 64 bits Memory space */
                        printk(KERN_INFO
                               " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
-                               cpu_addr, cpu_addr + size - 1, pci_addr,
+                               range.cpu_addr, range.cpu_addr + range.size - 1,
-                               (pci_space & 0x40000000) ? "Prefetch" : "");
+                               range.pci_addr,
+                               (range.pci_space & 0x40000000) ?
+                               "Prefetch" : "");
                        /* We support only 3 memory ranges */
                        if (memno >= 3) {
@@ -745,28 +742,21 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
                                continue;
                        }
                        /* Handles ISA memory hole space here */
-                        if (pci_addr == 0) {
+                        if (range.pci_addr == 0) {
                                if (primary || isa_mem_base == 0)
-                                        isa_mem_base = cpu_addr;
+                                        isa_mem_base = range.cpu_addr;
-                                hose->isa_mem_phys = cpu_addr;
+                                hose->isa_mem_phys = range.cpu_addr;
-                                hose->isa_mem_size = size;
+                                hose->isa_mem_size = range.size;
                        }
                        /* Build resource */
-                        hose->mem_offset[memno] = cpu_addr - pci_addr;
+                        hose->mem_offset[memno] = range.cpu_addr -
+                                                        range.pci_addr;
                        res = &hose->mem_resources[memno++];
-                        res->flags = IORESOURCE_MEM;
-                        if (pci_space & 0x40000000)
-                                res->flags |= IORESOURCE_PREFETCH;
-                        res->start = cpu_addr;
                        break;
                }
                if (res != NULL) {
-                        res->name = dev->full_name;
+                        of_pci_range_to_resource(&range, dev, res);
-                        res->end = res->start + size - 1;
-                        res->parent = NULL;
-                        res->sibling = NULL;
-                        res->child = NULL;
                }
        }
 }
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index 059e244484fe..44562aa97f16 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -304,6 +304,9 @@ static struct pci_dev *of_scan_pci_dev(struct pci_bus *bus,
        struct pci_dev *dev = NULL;
        const __be32 *reg;
        int reglen, devfn;
+#ifdef CONFIG_EEH
+        struct eeh_dev *edev = of_node_to_eeh_dev(dn);
+#endif
        pr_debug("  * %s\n", dn->full_name);
        if (!of_device_is_available(dn))
@@ -321,6 +324,12 @@ static struct pci_dev *of_scan_pci_dev(struct pci_bus *bus,
                return dev;
        }
+        /* Device removed permanently ? */
+#ifdef CONFIG_EEH
+        if (edev && (edev->mode & EEH_DEV_REMOVED))
+                return NULL;
+#endif
        /* create a new pci_dev for this device */
        dev = of_create_pci_dev(dn, bus, devfn);
        if (!dev)
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index 450850a49dce..48d17d6fca5b 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -155,9 +155,7 @@ EXPORT_SYMBOL(__cmpdi2);
 #endif
 long long __bswapdi2(long long);
 EXPORT_SYMBOL(__bswapdi2);
-#ifdef __BIG_ENDIAN__
 EXPORT_SYMBOL(memcpy);
-#endif
 EXPORT_SYMBOL(memset);
 EXPORT_SYMBOL(memmove);
 EXPORT_SYMBOL(memcmp);
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 31d021506d21..8a1edbe26b8f 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -54,6 +54,7 @@
 #ifdef CONFIG_PPC64
 #include <asm/firmware.h>
 #endif
+#include <asm/code-patching.h>
 #include <linux/kprobes.h>
 #include <linux/kdebug.h>
@@ -495,14 +496,21 @@ static inline int set_dawr(struct arch_hw_breakpoint *brk)
        return 0;
 }
-int set_breakpoint(struct arch_hw_breakpoint *brk)
+void __set_breakpoint(struct arch_hw_breakpoint *brk)
 {
        __get_cpu_var(current_brk) = *brk;
        if (cpu_has_feature(CPU_FTR_DAWR))
-                return set_dawr(brk);
+                set_dawr(brk);
+        else
+                set_dabr(brk);
+}
-        return set_dabr(brk);
+void set_breakpoint(struct arch_hw_breakpoint *brk)
+{
+        preempt_disable();
+        __set_breakpoint(brk);
+        preempt_enable();
 }
 #ifdef CONFIG_PPC64
@@ -834,7 +842,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
 */
 #ifndef CONFIG_HAVE_HW_BREAKPOINT
        if (unlikely(!hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk)))
-                set_breakpoint(&new->thread.hw_brk);
+                __set_breakpoint(&new->thread.hw_brk);
 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 #endif
@@ -1108,7 +1116,9 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
                struct thread_info *ti = (void *)task_stack_page(p);
                memset(childregs, 0, sizeof(struct pt_regs));
                childregs->gpr[1] = sp + sizeof(struct pt_regs);
-                childregs->gpr[14] = usp;       /* function */
+                /* function */
+                if (usp)
+                        childregs->gpr[14] = ppc_function_entry((void *)usp);
 #ifdef CONFIG_PPC64
                clear_tsk_thread_flag(p, TIF_32BIT);
                childregs->softe = 1;
@@ -1187,17 +1197,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
        if (cpu_has_feature(CPU_FTR_HAS_PPR))
                p->thread.ppr = INIT_PPR;
 #endif
-        /*
+        kregs->nip = ppc_function_entry(f);
-         * The PPC64 ABI makes use of a TOC to contain function 
-         * pointers.  The function (ret_from_except) is actually a pointer
-         * to the TOC entry.  The first entry is a pointer to the actual
-         * function.
-         */
-#ifdef CONFIG_PPC64
-        kregs->nip = *((unsigned long *)f);
-#else
-        kregs->nip = (unsigned long)f;
-#endif
        return 0;
 }
diff --git a/arch/powerpc/kernel/prom_init_check.sh b/arch/powerpc/kernel/prom_init_check.sh
index b0c263da219a..77aa1e95e904 100644
--- a/arch/powerpc/kernel/prom_init_check.sh
+++ b/arch/powerpc/kernel/prom_init_check.sh
@@ -23,7 +23,7 @@ strcmp strcpy strlcpy strlen strncmp strstr logo_linux_clut224
 reloc_got2 kernstart_addr memstart_addr linux_banner _stext
 opal_query_takeover opal_do_takeover opal_enter_rtas opal_secondary_entry
 boot_command_line __prom_init_toc_start __prom_init_toc_end
-btext_setup_display"
+btext_setup_display TOC."
 NM="$1"
 OBJ="$2"
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c
index 7d4c7172f38e..c168337aef9d 100644
--- a/arch/powerpc/kernel/rtas_pci.c
+++ b/arch/powerpc/kernel/rtas_pci.c
@@ -80,10 +80,6 @@ int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
        if (ret)
                return PCIBIOS_DEVICE_NOT_FOUND;
-        if (returnval == EEH_IO_ERROR_VALUE(size) &&
-            eeh_dev_check_failure(of_node_to_eeh_dev(pdn->node)))
-                return PCIBIOS_DEVICE_NOT_FOUND;
        return PCIBIOS_SUCCESSFUL;
 }
@@ -92,18 +88,39 @@ static int rtas_pci_read_config(struct pci_bus *bus,
                                int where, int size, u32 *val)
 {
        struct device_node *busdn, *dn;
+        struct pci_dn *pdn;
-        busdn = pci_bus_to_OF_node(bus);
+        bool found = false;
+#ifdef CONFIG_EEH
+        struct eeh_dev *edev;
+#endif
+        int ret;
        /* Search only direct children of the bus */
+        *val = 0xFFFFFFFF;
+        busdn = pci_bus_to_OF_node(bus);
        for (dn = busdn->child; dn; dn = dn->sibling) {
-                struct pci_dn *pdn = PCI_DN(dn);
+                pdn = PCI_DN(dn);
                if (pdn && pdn->devfn == devfn
-                    && of_device_is_available(dn))
+                    && of_device_is_available(dn)) {
-                        return rtas_read_config(pdn, where, size, val);
+                        found = true;
+                        break;
+                }
        }
-        return PCIBIOS_DEVICE_NOT_FOUND;
+        if (!found)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+#ifdef CONFIG_EEH
+        edev = of_node_to_eeh_dev(dn);
+        if (edev && edev->pe && edev->pe->state & EEH_PE_RESET)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+#endif
+        ret = rtas_read_config(pdn, where, size, val);
+        if (*val == EEH_IO_ERROR_VALUE(size) &&
+            eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        return ret;
 }
 int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
@@ -136,17 +153,34 @@ static int rtas_pci_write_config(struct pci_bus *bus,
                                 int where, int size, u32 val)
 {
        struct device_node *busdn, *dn;
+        struct pci_dn *pdn;
-        busdn = pci_bus_to_OF_node(bus);
+        bool found = false;
+#ifdef CONFIG_EEH
+        struct eeh_dev *edev;
+#endif
+        int ret;
        /* Search only direct children of the bus */
+        busdn = pci_bus_to_OF_node(bus);
        for (dn = busdn->child; dn; dn = dn->sibling) {
-                struct pci_dn *pdn = PCI_DN(dn);
+                pdn = PCI_DN(dn);
                if (pdn && pdn->devfn == devfn
-                    && of_device_is_available(dn))
+                    && of_device_is_available(dn)) {
-                        return rtas_write_config(pdn, where, size, val);
+                        found = true;
+                        break;
+                }
        }
-        return PCIBIOS_DEVICE_NOT_FOUND;
+        if (!found)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+#ifdef CONFIG_EEH
+        edev = of_node_to_eeh_dev(dn);
+        if (edev && edev->pe && (edev->pe->state & EEH_PE_RESET))
+                return PCIBIOS_DEVICE_NOT_FOUND;
+#endif
+        ret = rtas_write_config(pdn, where, size, val);
+        return ret;
 }
 static struct pci_ops rtas_pci_ops = {
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 79b7612ac6fa..aa0f5edd8570 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -212,6 +212,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 {
        unsigned long cpu_id = (unsigned long)v - 1;
        unsigned int pvr;
+        unsigned long proc_freq;
        unsigned short maj;
        unsigned short min;
@@ -263,12 +264,19 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 #endif /* CONFIG_TAU */
        /*
-         * Assume here that all clock rates are the same in a
+         * Platforms that have variable clock rates, should implement
-         * smp system.  -- Cort
+         * the method ppc_md.get_proc_freq() that reports the clock
+         * rate of a given cpu. The rest can use ppc_proc_freq to
+         * report the clock rate that is same across all cpus.
         */
-        if (ppc_proc_freq)
+        if (ppc_md.get_proc_freq)
+                proc_freq = ppc_md.get_proc_freq(cpu_id);
+        else
+                proc_freq = ppc_proc_freq;
+        if (proc_freq)
                seq_printf(m, "clock\t\t: %lu.%06luMHz\n",
-                           ppc_proc_freq / 1000000, ppc_proc_freq % 1000000);
+                           proc_freq / 1000000, proc_freq % 1000000);
        if (ppc_md.show_percpuinfo != NULL)
                ppc_md.show_percpuinfo(m, cpu_id);
@@ -382,9 +390,10 @@ void __init check_for_initrd(void)
 #ifdef CONFIG_SMP
-int threads_per_core, threads_shift;
+int threads_per_core, threads_per_subcore, threads_shift;
 cpumask_t threads_core_mask;
 EXPORT_SYMBOL_GPL(threads_per_core);
+EXPORT_SYMBOL_GPL(threads_per_subcore);
 EXPORT_SYMBOL_GPL(threads_shift);
 EXPORT_SYMBOL_GPL(threads_core_mask);
@@ -393,6 +402,7 @@ static void __init cpu_init_thread_core_maps(int tpc)
        int i;
        threads_per_core = tpc;
+        threads_per_subcore = tpc;
        cpumask_clear(&threads_core_mask);
        /* This implementation only supports power of 2 number of threads
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index fbe24377eda3..ee082d771178 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -36,6 +36,7 @@
 #include <linux/lockdep.h>
 #include <linux/memblock.h>
 #include <linux/hugetlb.h>
+#include <linux/memory.h>
 #include <asm/io.h>
 #include <asm/kdump.h>
@@ -341,7 +342,7 @@ void smp_release_cpus(void)
        ptr  = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
                        - PHYSICAL_START);
-        *ptr = __pa(generic_secondary_smp_init);
+        *ptr = ppc_function_entry(generic_secondary_smp_init);
        /* And wait a bit for them to catch up */
        for (i = 0; i < 100000; i++) {
@@ -780,6 +781,15 @@ void __init setup_per_cpu_areas(void)
 }
 #endif
+#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
+unsigned long memory_block_size_bytes(void)
+{
+        if (ppc_md.memory_block_size)
+                return ppc_md.memory_block_size();
+        return MIN_MEMORY_BLOCK_SIZE;
+}
+#endif
 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
 struct ppc_pci_io ppc_pci_io;
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index 8fc4177ed65a..1c794cef2883 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -134,7 +134,7 @@ static int do_signal(struct pt_regs *regs)
         */
        if (current->thread.hw_brk.address &&
                current->thread.hw_brk.type)
-                set_breakpoint(&current->thread.hw_brk);
+                __set_breakpoint(&current->thread.hw_brk);
 #endif
        /* Re-enable the breakpoints for the signal stack */
        thread_change_pc(current, regs);
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 10ffffef0414..7753af2d2613 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -36,6 +36,7 @@
 #include <linux/atomic.h>
 #include <asm/irq.h>
 #include <asm/hw_irq.h>
+#include <asm/kvm_ppc.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/prom.h>
@@ -390,6 +391,7 @@ void smp_prepare_boot_cpu(void)
 #ifdef CONFIG_PPC64
        paca[boot_cpuid].__current = current;
 #endif
+        set_numa_node(numa_cpu_lookup_table[boot_cpuid]);
        current_set[boot_cpuid] = task_thread_info(current);
 }
@@ -457,38 +459,9 @@ int generic_check_cpu_restart(unsigned int cpu)
        return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE;
 }
-static atomic_t secondary_inhibit_count;
+static bool secondaries_inhibited(void)
-/*
- * Don't allow secondary CPU threads to come online
- */
-void inhibit_secondary_onlining(void)
 {
-        /*
+        return kvm_hv_mode_active();
-         * This makes secondary_inhibit_count stable during cpu
-         * online/offline operations.
-         */
-        get_online_cpus();
-        atomic_inc(&secondary_inhibit_count);
-        put_online_cpus();
-}
-EXPORT_SYMBOL_GPL(inhibit_secondary_onlining);
-/*
- * Allow secondary CPU threads to come online again
- */
-void uninhibit_secondary_onlining(void)
-{
-        get_online_cpus();
-        atomic_dec(&secondary_inhibit_count);
-        put_online_cpus();
-}
-EXPORT_SYMBOL_GPL(uninhibit_secondary_onlining);
-static int secondaries_inhibited(void)
-{
-        return atomic_read(&secondary_inhibit_count);
 }
 #else /* HOTPLUG_CPU */
@@ -517,7 +490,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle)
         * Don't allow secondary threads to come online if inhibited
         */
        if (threads_per_core > 1 && secondaries_inhibited() &&
-            cpu % threads_per_core != 0)
+            cpu_thread_in_subcore(cpu))
                return -EBUSY;
        if (smp_ops == NULL ||
@@ -750,6 +723,12 @@ void start_secondary(void *unused)
        }
        traverse_core_siblings(cpu, true);
+        /*
+         * numa_node_id() works after this.
+         */
+        set_numa_node(numa_cpu_lookup_table[cpu]);
+        set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu]));
        smp_wmb();
        notify_cpu_starting(cpu);
        set_cpu_online(cpu, true);
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index d90d4b7810d6..67fd2fd2620a 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -404,7 +404,7 @@ void ppc_enable_pmcs(void)
 }
 EXPORT_SYMBOL(ppc_enable_pmcs);
-#define __SYSFS_SPRSETUP(NAME, ADDRESS, EXTRA) \
+#define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
 static void read_##NAME(void *val) \
 { \
        *(unsigned long *)val = mfspr(ADDRESS); \
@@ -413,7 +413,9 @@ static void write_##NAME(void *val) \
 { \
        EXTRA; \
        mtspr(ADDRESS, *(unsigned long *)val);  \
-} \
+}
+#define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 static ssize_t show_##NAME(struct device *dev, \
                        struct device_attribute *attr, \
                        char *buf) \
@@ -436,10 +438,15 @@ static ssize_t __used \
        return count; \
 }
-#define SYSFS_PMCSETUP(NAME, ADDRESS)   \
+#define SYSFS_PMCSETUP(NAME, ADDRESS) \
-        __SYSFS_SPRSETUP(NAME, ADDRESS, ppc_enable_pmcs())
+        __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
-#define SYSFS_SPRSETUP(NAME, ADDRESS)   \
+        __SYSFS_SPRSETUP_SHOW_STORE(NAME)
-        __SYSFS_SPRSETUP(NAME, ADDRESS, )
+#define SYSFS_SPRSETUP(NAME, ADDRESS) \
+        __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
+        __SYSFS_SPRSETUP_SHOW_STORE(NAME)
+#define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
+        __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 /* Let's define all possible registers, we'll only hook up the ones
 * that are implemented on the current processor
@@ -477,7 +484,6 @@ SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
 SYSFS_SPRSETUP(purr, SPRN_PURR);
 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
-SYSFS_SPRSETUP(dscr, SPRN_DSCR);
 SYSFS_SPRSETUP(pir, SPRN_PIR);
 /*
@@ -487,12 +493,27 @@ SYSFS_SPRSETUP(pir, SPRN_PIR);
 */
 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
-static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
-unsigned long dscr_default = 0;
+static unsigned long dscr_default;
-EXPORT_SYMBOL(dscr_default);
+static void read_dscr(void *val)
+{
+        *(unsigned long *)val = get_paca()->dscr_default;
+}
+static void write_dscr(void *val)
+{
+        get_paca()->dscr_default = *(unsigned long *)val;
+        if (!current->thread.dscr_inherit) {
+                current->thread.dscr = *(unsigned long *)val;
+                mtspr(SPRN_DSCR, *(unsigned long *)val);
+        }
+}
+SYSFS_SPRSETUP_SHOW_STORE(dscr);
+static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
 static void add_write_permission_dev_attr(struct device_attribute *attr)
 {
@@ -505,14 +526,6 @@ static ssize_t show_dscr_default(struct device *dev,
        return sprintf(buf, "%lx\n", dscr_default);
 }
-static void update_dscr(void *dummy)
-{
-        if (!current->thread.dscr_inherit) {
-                current->thread.dscr = dscr_default;
-                mtspr(SPRN_DSCR, dscr_default);
-        }
-}
 static ssize_t __used store_dscr_default(struct device *dev,
                struct device_attribute *attr, const char *buf,
                size_t count)
@@ -525,7 +538,7 @@ static ssize_t __used store_dscr_default(struct device *dev,
                return -EINVAL;
        dscr_default = val;
-        on_each_cpu(update_dscr, NULL, 1);
+        on_each_cpu(write_dscr, &val, 1);
        return count;
 }
diff --git a/arch/powerpc/kernel/systbl.S b/arch/powerpc/kernel/systbl.S
index 93219c34af32..895c50ca943c 100644
--- a/arch/powerpc/kernel/systbl.S
+++ b/arch/powerpc/kernel/systbl.S
@@ -17,12 +17,12 @@
 #include <asm/ppc_asm.h>
 #ifdef CONFIG_PPC64
-#define SYSCALL(func)           .llong  .sys_##func,.sys_##func
+#define SYSCALL(func)           .llong  DOTSYM(sys_##func),DOTSYM(sys_##func)
-#define COMPAT_SYS(func)        .llong  .sys_##func,.compat_sys_##func
+#define COMPAT_SYS(func)        .llong  DOTSYM(sys_##func),DOTSYM(compat_sys_##func)
-#define PPC_SYS(func)           .llong  .ppc_##func,.ppc_##func
+#define PPC_SYS(func)           .llong  DOTSYM(ppc_##func),DOTSYM(ppc_##func)
-#define OLDSYS(func)            .llong  .sys_ni_syscall,.sys_ni_syscall
+#define OLDSYS(func)            .llong  DOTSYM(sys_ni_syscall),DOTSYM(sys_ni_syscall)
-#define SYS32ONLY(func)         .llong  .sys_ni_syscall,.compat_sys_##func
+#define SYS32ONLY(func)         .llong  DOTSYM(sys_ni_syscall),DOTSYM(compat_sys_##func)
-#define SYSX(f, f3264, f32)     .llong  .f,.f3264
+#define SYSX(f, f3264, f32)     .llong  DOTSYM(f),DOTSYM(f3264)
 #else
 #define SYSCALL(func)           .long   sys_##func
 #define COMPAT_SYS(func)        .long   sys_##func
@@ -36,6 +36,8 @@
 #define PPC_SYS_SPU(func)       PPC_SYS(func)
 #define SYSX_SPU(f, f3264, f32) SYSX(f, f3264, f32)
+.section .rodata,"a"
 #ifdef CONFIG_PPC64
 #define sys_sigpending  sys_ni_syscall
 #define sys_old_getrlimit sys_ni_syscall
@@ -43,5 +45,7 @@
        .p2align        3
 #endif
-_GLOBAL(sys_call_table)
+.globl sys_call_table
+sys_call_table:
 #include <asm/systbl.h>
diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
index 03567c05950a..2a324f4cb1b9 100644
--- a/arch/powerpc/kernel/tm.S
+++ b/arch/powerpc/kernel/tm.S
@@ -10,6 +10,7 @@
 #include <asm/ppc-opcode.h>
 #include <asm/ptrace.h>
 #include <asm/reg.h>
+#include <asm/bug.h>
 #ifdef CONFIG_VSX
 /* See fpu.S, this is borrowed from there */
@@ -41,7 +42,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX);		\
 /* Stack frame offsets for local variables. */
 #define TM_FRAME_L0     TM_FRAME_SIZE-16
 #define TM_FRAME_L1     TM_FRAME_SIZE-8
-#define STACK_PARAM(x)  (48+((x)*8))
 /* In order to access the TM SPRs, TM must be enabled.  So, do so: */
@@ -78,12 +78,6 @@ _GLOBAL(tm_abort)
        TABORT(R3)
        blr
-        .section        ".toc","aw"
-DSCR_DEFAULT:
-        .tc dscr_default[TC],dscr_default
-        .section        ".text"
 /* void tm_reclaim(struct thread_struct *thread,
 *                 unsigned long orig_msr,
 *                 uint8_t cause)
@@ -108,12 +102,12 @@ _GLOBAL(tm_reclaim)
        mflr    r0
        stw     r6, 8(r1)
        std     r0, 16(r1)
-        std     r2, 40(r1)
+        std     r2, STK_GOT(r1)
        stdu    r1, -TM_FRAME_SIZE(r1)
        /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
-        std     r3, STACK_PARAM(0)(r1)
+        std     r3, STK_PARAM(R3)(r1)
        SAVE_NVGPRS(r1)
        /* We need to setup MSR for VSX register save instructions.  Here we
@@ -175,6 +169,13 @@ dont_backup_vec:
        stfd    fr0,FPSTATE_FPSCR(r7)
 dont_backup_fp:
+        /* Do sanity check on MSR to make sure we are suspended */
+        li      r7, (MSR_TS_S)@higher
+        srdi    r6, r14, 32
+        and     r6, r6, r7
+1:      tdeqi   r6, 0
+        EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
        /* The moment we treclaim, ALL of our GPRs will switch
         * to user register state.  (FPRs, CCR etc. also!)
         * Use an sprg and a tm_scratch in the PACA to shuffle.
@@ -202,7 +203,7 @@ dont_backup_fp:
        /* Now get some more GPRS free */
        std     r7, GPR7(r1)                    /* Temporary stash */
        std     r12, GPR12(r1)                  /* ''   ''    ''   */
-        ld      r12, STACK_PARAM(0)(r1)         /* Param 0, thread_struct * */
+        ld      r12, STK_PARAM(R3)(r1)          /* Param 0, thread_struct * */
        std     r11, THREAD_TM_PPR(r12)         /* Store PPR and free r11 */
@@ -289,11 +290,10 @@ dont_backup_fp:
        ld      r0, 16(r1)
        mtcr    r4
        mtlr    r0
-        ld      r2, 40(r1)
+        ld      r2, STK_GOT(r1)
-        /* Load system default DSCR */
+        /* Load CPU's default DSCR */
-        ld      r4, DSCR_DEFAULT@toc(r2)
+        ld      r0, PACA_DSCR(r13)
-        ld      r0, 0(r4)
        mtspr   SPRN_DSCR, r0
        blr
@@ -312,7 +312,7 @@ _GLOBAL(__tm_recheckpoint)
        mflr    r0
        stw     r5, 8(r1)
        std     r0, 16(r1)
-        std     r2, 40(r1)
+        std     r2, STK_GOT(r1)
        stdu    r1, -TM_FRAME_SIZE(r1)
        /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
@@ -320,8 +320,6 @@ _GLOBAL(__tm_recheckpoint)
         */
        SAVE_NVGPRS(r1)
-        std     r1, PACAR1(r13)
        /* Load complete register state from ts_ckpt* registers */
        addi    r7, r3, PT_CKPT_REGS            /* Thread's ckpt_regs */
@@ -385,12 +383,10 @@ restore_gprs:
        /* ******************** CR,LR,CCR,MSR ********** */
        ld      r4, _CTR(r7)
        ld      r5, _LINK(r7)
-        ld      r6, _CCR(r7)
        ld      r8, _XER(r7)
        mtctr   r4
        mtlr    r5
-        mtcr    r6
        mtxer   r8
        /* ******************** TAR ******************** */
@@ -406,7 +402,8 @@ restore_gprs:
        li      r4, 0
        mtmsrd  r4, 1
-        REST_4GPRS(0, r7)                       /* GPR0-3 */
+        REST_GPR(0, r7)                         /* GPR0 */
+        REST_2GPRS(2, r7)                       /* GPR2-3 */
        REST_GPR(4, r7)                         /* GPR4 */
        REST_4GPRS(8, r7)                       /* GPR8-11 */
        REST_2GPRS(12, r7)                      /* GPR12-13 */
@@ -418,6 +415,31 @@ restore_gprs:
        mtspr   SPRN_DSCR, r5
        mtspr   SPRN_PPR, r6
+        /* Do final sanity check on TEXASR to make sure FS is set.  Do this
+         * here before we load up the userspace r1 so any bugs we hit will get
+         * a call chain */
+        mfspr   r5, SPRN_TEXASR
+        srdi    r5, r5, 16
+        li      r6, (TEXASR_FS)@h
+        and     r6, r6, r5
+1:      tdeqi   r6, 0
+        EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
+        /* Do final sanity check on MSR to make sure we are not transactional
+         * or suspended
+         */
+        mfmsr   r6
+        li      r5, (MSR_TS_MASK)@higher
+        srdi    r6, r6, 32
+        and     r6, r6, r5
+1:      tdnei   r6, 0
+        EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
+        /* Restore CR */
+        ld      r6, _CCR(r7)
+        mtcr    r6
+        REST_GPR(1, r7)                         /* GPR1 */
        REST_GPR(5, r7)                         /* GPR5-7 */
        REST_GPR(6, r7)
        ld      r7, GPR7(r7)
@@ -448,11 +470,10 @@ restore_gprs:
        ld      r0, 16(r1)
        mtcr    r4
        mtlr    r0
-        ld      r2, 40(r1)
+        ld      r2, STK_GOT(r1)
-        /* Load system default DSCR */
+        /* Load CPU's default DSCR */
-        ld      r4, DSCR_DEFAULT@toc(r2)
+        ld      r0, PACA_DSCR(r13)
-        ld      r0, 0(r4)
        mtspr   SPRN_DSCR, r0
        blr
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index aba05bbb3e74..7a12edbb61e7 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -1236,7 +1236,7 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_hv(struct kvm *kvm,
        int core;
        struct kvmppc_vcore *vcore;
-        core = id / threads_per_core;
+        core = id / threads_per_subcore;
        if (core >= KVM_MAX_VCORES)
                goto out;
@@ -1286,7 +1286,7 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_hv(struct kvm *kvm,
                        init_waitqueue_head(&vcore->wq);
                        vcore->preempt_tb = TB_NIL;
                        vcore->lpcr = kvm->arch.lpcr;
-                        vcore->first_vcpuid = core * threads_per_core;
+                        vcore->first_vcpuid = core * threads_per_subcore;
                        vcore->kvm = kvm;
                }
                kvm->arch.vcores[core] = vcore;
@@ -1476,16 +1476,19 @@ static void kvmppc_wait_for_nap(struct kvmppc_vcore *vc)
 static int on_primary_thread(void)
 {
        int cpu = smp_processor_id();
-        int thr = cpu_thread_in_core(cpu);
+        int thr;
-        if (thr)
+        /* Are we on a primary subcore? */
+        if (cpu_thread_in_subcore(cpu))
                return 0;
-        while (++thr < threads_per_core)
+        thr = 0;
+        while (++thr < threads_per_subcore)
                if (cpu_online(cpu + thr))
                        return 0;
        /* Grab all hw threads so they can't go into the kernel */
-        for (thr = 1; thr < threads_per_core; ++thr) {
+        for (thr = 1; thr < threads_per_subcore; ++thr) {
                if (kvmppc_grab_hwthread(cpu + thr)) {
                        /* Couldn't grab one; let the others go */
                        do {
@@ -1544,15 +1547,18 @@ static void kvmppc_run_core(struct kvmppc_vcore *vc)
        }
        /*
-         * Make sure we are running on thread 0, and that
+         * Make sure we are running on primary threads, and that secondary
-         * secondary threads are offline.
+         * threads are offline.  Also check if the number of threads in this
+         * guest are greater than the current system threads per guest.
         */
-        if (threads_per_core > 1 && !on_primary_thread()) {
+        if ((threads_per_core > 1) &&
+            ((vc->num_threads > threads_per_subcore) || !on_primary_thread())) {
                list_for_each_entry(vcpu, &vc->runnable_threads, arch.run_list)
                        vcpu->arch.ret = -EBUSY;
                goto out;
        }
        vc->pcpu = smp_processor_id();
        list_for_each_entry(vcpu, &vc->runnable_threads, arch.run_list) {
                kvmppc_start_thread(vcpu);
@@ -1580,7 +1586,7 @@ static void kvmppc_run_core(struct kvmppc_vcore *vc)
        /* wait for secondary threads to finish writing their state to memory */
        if (vc->nap_count < vc->n_woken)
                kvmppc_wait_for_nap(vc);
-        for (i = 0; i < threads_per_core; ++i)
+        for (i = 0; i < threads_per_subcore; ++i)
                kvmppc_release_hwthread(vc->pcpu + i);
        /* prevent other vcpu threads from doing kvmppc_start_thread() now */
        vc->vcore_state = VCORE_EXITING;
@@ -2305,10 +2311,10 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm)
        spin_lock_init(&kvm->arch.slot_phys_lock);
        /*
-         * Don't allow secondary CPU threads to come online
+         * Track that we now have a HV mode VM active. This blocks secondary
-         * while any KVM VMs exist.
+         * CPU threads from coming online.
         */
-        inhibit_secondary_onlining();
+        kvm_hv_vm_activated();
        return 0;
 }
@@ -2324,7 +2330,7 @@ static void kvmppc_free_vcores(struct kvm *kvm)
 static void kvmppc_core_destroy_vm_hv(struct kvm *kvm)
 {
-        uninhibit_secondary_onlining();
+        kvm_hv_vm_deactivated();
        kvmppc_free_vcores(kvm);
        if (kvm->arch.rma) {
diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c
index 8cd0daebb82d..7cde8a665205 100644
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -6,6 +6,7 @@
 * published by the Free Software Foundation.
 */
+#include <linux/cpu.h>
 #include <linux/kvm_host.h>
 #include <linux/preempt.h>
 #include <linux/export.h>
@@ -181,3 +182,33 @@ void __init kvm_cma_reserve(void)
                kvm_cma_declare_contiguous(selected_size, align_size);
        }
 }
+/*
+ * When running HV mode KVM we need to block certain operations while KVM VMs
+ * exist in the system. We use a counter of VMs to track this.
+ *
+ * One of the operations we need to block is onlining of secondaries, so we
+ * protect hv_vm_count with get/put_online_cpus().
+ */
+static atomic_t hv_vm_count;
+void kvm_hv_vm_activated(void)
+{
+        get_online_cpus();
+        atomic_inc(&hv_vm_count);
+        put_online_cpus();
+}
+EXPORT_SYMBOL_GPL(kvm_hv_vm_activated);
+void kvm_hv_vm_deactivated(void)
+{
+        get_online_cpus();
+        atomic_dec(&hv_vm_count);
+        put_online_cpus();
+}
+EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated);
+bool kvm_hv_mode_active(void)
+{
+        return atomic_read(&hv_vm_count) != 0;
+}
diff --git a/arch/powerpc/kvm/book3s_hv_interrupts.S b/arch/powerpc/kvm/book3s_hv_interrupts.S
index e18e3cfc32de..8c86422a1e37 100644
--- a/arch/powerpc/kvm/book3s_hv_interrupts.S
+++ b/arch/powerpc/kvm/book3s_hv_interrupts.S
@@ -171,7 +171,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
 #endif /* CONFIG_SMP */
        /* Jump to partition switch code */
-        bl      .kvmppc_hv_entry_trampoline
+        bl      kvmppc_hv_entry_trampoline
        nop
 /*
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 974793435a2e..77356fd25ccc 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -292,8 +292,7 @@ kvm_start_guest:
        beq     kvm_no_guest
        /* Set HSTATE_DSCR(r13) to something sensible */
-        LOAD_REG_ADDR(r6, dscr_default)
+        ld      r6, PACA_DSCR(r13)
-        ld      r6, 0(r6)
        std     r6, HSTATE_DSCR(r13)
        bl      kvmppc_hv_entry
@@ -1799,7 +1798,7 @@ kvmppc_hdsi:
        /* Search the hash table. */
        mr      r3, r9                  /* vcpu pointer */
        li      r7, 1                   /* data fault */
-        bl      .kvmppc_hpte_hv_fault
+        bl      kvmppc_hpte_hv_fault
        ld      r9, HSTATE_KVM_VCPU(r13)
        ld      r10, VCPU_PC(r9)
        ld      r11, VCPU_MSR(r9)
@@ -1873,7 +1872,7 @@ kvmppc_hisi:
        mr      r4, r10
        mr      r6, r11
        li      r7, 0                   /* instruction fault */
-        bl      .kvmppc_hpte_hv_fault
+        bl      kvmppc_hpte_hv_fault
        ld      r9, HSTATE_KVM_VCPU(r13)
        ld      r10, VCPU_PC(r9)
        ld      r11, VCPU_MSR(r9)
@@ -1947,16 +1946,16 @@ hcall_real_fallback:
        .globl  hcall_real_table
 hcall_real_table:
        .long   0               /* 0 - unused */
-        .long   .kvmppc_h_remove - hcall_real_table
+        .long   DOTSYM(kvmppc_h_remove) - hcall_real_table
-        .long   .kvmppc_h_enter - hcall_real_table
+        .long   DOTSYM(kvmppc_h_enter) - hcall_real_table
-        .long   .kvmppc_h_read - hcall_real_table
+        .long   DOTSYM(kvmppc_h_read) - hcall_real_table
        .long   0               /* 0x10 - H_CLEAR_MOD */
        .long   0               /* 0x14 - H_CLEAR_REF */
-        .long   .kvmppc_h_protect - hcall_real_table
+        .long   DOTSYM(kvmppc_h_protect) - hcall_real_table
-        .long   .kvmppc_h_get_tce - hcall_real_table
+        .long   DOTSYM(kvmppc_h_get_tce) - hcall_real_table
-        .long   .kvmppc_h_put_tce - hcall_real_table
+        .long   DOTSYM(kvmppc_h_put_tce) - hcall_real_table
        .long   0               /* 0x24 - H_SET_SPRG0 */
-        .long   .kvmppc_h_set_dabr - hcall_real_table
+        .long   DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
        .long   0               /* 0x2c */
        .long   0               /* 0x30 */
        .long   0               /* 0x34 */
@@ -1972,11 +1971,11 @@ hcall_real_table:
        .long   0               /* 0x5c */
        .long   0               /* 0x60 */
 #ifdef CONFIG_KVM_XICS
-        .long   .kvmppc_rm_h_eoi - hcall_real_table
+        .long   DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
-        .long   .kvmppc_rm_h_cppr - hcall_real_table
+        .long   DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
-        .long   .kvmppc_rm_h_ipi - hcall_real_table
+        .long   DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
        .long   0               /* 0x70 - H_IPOLL */
-        .long   .kvmppc_rm_h_xirr - hcall_real_table
+        .long   DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
 #else
        .long   0               /* 0x64 - H_EOI */
        .long   0               /* 0x68 - H_CPPR */
@@ -2010,7 +2009,7 @@ hcall_real_table:
        .long   0               /* 0xd4 */
        .long   0               /* 0xd8 */
        .long   0               /* 0xdc */
-        .long   .kvmppc_h_cede - hcall_real_table
+        .long   DOTSYM(kvmppc_h_cede) - hcall_real_table
        .long   0               /* 0xe4 */
        .long   0               /* 0xe8 */
        .long   0               /* 0xec */
@@ -2027,11 +2026,11 @@ hcall_real_table:
        .long   0               /* 0x118 */
        .long   0               /* 0x11c */
        .long   0               /* 0x120 */
-        .long   .kvmppc_h_bulk_remove - hcall_real_table
+        .long   DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
        .long   0               /* 0x128 */
        .long   0               /* 0x12c */
        .long   0               /* 0x130 */
-        .long   .kvmppc_h_set_xdabr - hcall_real_table
+        .long   DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
 hcall_real_table_end:
 ignore_hdec:
@@ -2256,7 +2255,7 @@ kvm_cede_exit:
        /* Try to handle a machine check in real mode */
 machine_check_realmode:
        mr      r3, r9          /* get vcpu pointer */
-        bl      .kvmppc_realmode_machine_check
+        bl      kvmppc_realmode_machine_check
        nop
        cmpdi   r3, 0           /* continue exiting from guest? */
        ld      r9, HSTATE_KVM_VCPU(r13)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index bab20f410443..61c738ab1283 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -426,7 +426,7 @@ int kvm_dev_ioctl_check_extension(long ext)
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
        case KVM_CAP_PPC_SMT:
                if (hv_enabled)
-                        r = threads_per_core;
+                        r = threads_per_subcore;
                else
                        r = 0;
                break;
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 95a20e17dbff..59fa2de9546d 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -23,9 +23,7 @@ obj-y			+= checksum_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_PPC64)     += checksum_wrappers_64.o
 endif
-ifeq ($(CONFIG_CPU_LITTLE_ENDIAN),)
 obj-$(CONFIG_PPC64)             += memcpy_power7.o memcpy_64.o 
-endif
 obj-$(CONFIG_PPC_EMULATE_SSTEP) += sstep.o ldstfp.o
diff --git a/arch/powerpc/lib/copypage_64.S b/arch/powerpc/lib/copypage_64.S
index 9f9434a85264..a3c4dc4defdd 100644
--- a/arch/powerpc/lib/copypage_64.S
+++ b/arch/powerpc/lib/copypage_64.S
@@ -16,11 +16,11 @@ PPC64_CACHES:
        .tc             ppc64_caches[TC],ppc64_caches
        .section        ".text"
-_GLOBAL(copy_page)
+_GLOBAL_TOC(copy_page)
 BEGIN_FTR_SECTION
        lis     r5,PAGE_SIZE@h
 FTR_SECTION_ELSE
-        b       .copypage_power7
+        b       copypage_power7
 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
        ori     r5,r5,PAGE_SIZE@l
 BEGIN_FTR_SECTION
diff --git a/arch/powerpc/lib/copypage_power7.S b/arch/powerpc/lib/copypage_power7.S
index 395c594722a2..d7dafb3777ac 100644
--- a/arch/powerpc/lib/copypage_power7.S
+++ b/arch/powerpc/lib/copypage_power7.S
@@ -56,15 +56,15 @@ _GLOBAL(copypage_power7)
 #ifdef CONFIG_ALTIVEC
        mflr    r0
-        std     r3,48(r1)
+        std     r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
-        std     r4,56(r1)
+        std     r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
        std     r0,16(r1)
        stdu    r1,-STACKFRAMESIZE(r1)
-        bl      .enter_vmx_copy
+        bl      enter_vmx_copy
        cmpwi   r3,0
        ld      r0,STACKFRAMESIZE+16(r1)
-        ld      r3,STACKFRAMESIZE+48(r1)
+        ld      r3,STK_REG(R31)(r1)
-        ld      r4,STACKFRAMESIZE+56(r1)
+        ld      r4,STK_REG(R30)(r1)
        mtlr    r0
        li      r0,(PAGE_SIZE/128)
@@ -103,7 +103,7 @@ _GLOBAL(copypage_power7)
        addi    r3,r3,128
        bdnz    1b
-        b       .exit_vmx_copy          /* tail call optimise */
+        b       exit_vmx_copy           /* tail call optimise */
 #else
        li      r0,(PAGE_SIZE/128)
diff --git a/arch/powerpc/lib/copyuser_64.S b/arch/powerpc/lib/copyuser_64.S
index 596a285c0755..0860ee46013c 100644
--- a/arch/powerpc/lib/copyuser_64.S
+++ b/arch/powerpc/lib/copyuser_64.S
@@ -18,7 +18,7 @@
 #endif
        .align  7
-_GLOBAL(__copy_tofrom_user)
+_GLOBAL_TOC(__copy_tofrom_user)
 BEGIN_FTR_SECTION
        nop
 FTR_SECTION_ELSE
diff --git a/arch/powerpc/lib/copyuser_power7.S b/arch/powerpc/lib/copyuser_power7.S
index e8e9c36dc784..c46c876ac96a 100644
--- a/arch/powerpc/lib/copyuser_power7.S
+++ b/arch/powerpc/lib/copyuser_power7.S
@@ -66,7 +66,7 @@
        ld      r15,STK_REG(R15)(r1)
        ld      r14,STK_REG(R14)(r1)
 .Ldo_err3:
-        bl      .exit_vmx_usercopy
+        bl      exit_vmx_usercopy
        ld      r0,STACKFRAMESIZE+16(r1)
        mtlr    r0
        b       .Lexit
@@ -85,9 +85,9 @@
 .Lexit:
        addi    r1,r1,STACKFRAMESIZE
 .Ldo_err1:
-        ld      r3,48(r1)
+        ld      r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
-        ld      r4,56(r1)
+        ld      r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
-        ld      r5,64(r1)
+        ld      r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
        b       __copy_tofrom_user_base
@@ -96,18 +96,18 @@ _GLOBAL(__copy_tofrom_user_power7)
        cmpldi  r5,16
        cmpldi  cr1,r5,4096
-        std     r3,48(r1)
+        std     r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
-        std     r4,56(r1)
+        std     r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
-        std     r5,64(r1)
+        std     r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
        blt     .Lshort_copy
        bgt     cr1,.Lvmx_copy
 #else
        cmpldi  r5,16
-        std     r3,48(r1)
+        std     r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
-        std     r4,56(r1)
+        std     r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
-        std     r5,64(r1)
+        std     r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
        blt     .Lshort_copy
 #endif
@@ -295,12 +295,12 @@ err1;	stb	r0,0(r3)
        mflr    r0
        std     r0,16(r1)
        stdu    r1,-STACKFRAMESIZE(r1)
-        bl      .enter_vmx_usercopy
+        bl      enter_vmx_usercopy
        cmpwi   cr1,r3,0
        ld      r0,STACKFRAMESIZE+16(r1)
-        ld      r3,STACKFRAMESIZE+48(r1)
+        ld      r3,STK_REG(R31)(r1)
-        ld      r4,STACKFRAMESIZE+56(r1)
+        ld      r4,STK_REG(R30)(r1)
-        ld      r5,STACKFRAMESIZE+64(r1)
+        ld      r5,STK_REG(R29)(r1)
        mtlr    r0
        /*
@@ -514,7 +514,7 @@ err3;	lbz	r0,0(r4)
 err3;   stb     r0,0(r3)
 15:     addi    r1,r1,STACKFRAMESIZE
-        b       .exit_vmx_usercopy      /* tail call optimise */
+        b       exit_vmx_usercopy       /* tail call optimise */
 .Lvmx_unaligned_copy:
        /* Get the destination 16B aligned */
@@ -717,5 +717,5 @@ err3;	lbz	r0,0(r4)
 err3;   stb     r0,0(r3)
 15:     addi    r1,r1,STACKFRAMESIZE
-        b       .exit_vmx_usercopy      /* tail call optimise */
+        b       exit_vmx_usercopy       /* tail call optimise */
 #endif /* CONFiG_ALTIVEC */
diff --git a/arch/powerpc/lib/hweight_64.S b/arch/powerpc/lib/hweight_64.S
index 9b96ff2ecd4d..19e66001a4f9 100644
--- a/arch/powerpc/lib/hweight_64.S
+++ b/arch/powerpc/lib/hweight_64.S
@@ -24,7 +24,7 @@
 _GLOBAL(__arch_hweight8)
 BEGIN_FTR_SECTION
-        b .__sw_hweight8
+        b __sw_hweight8
        nop
        nop
 FTR_SECTION_ELSE
@@ -35,7 +35,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
 _GLOBAL(__arch_hweight16)
 BEGIN_FTR_SECTION
-        b .__sw_hweight16
+        b __sw_hweight16
        nop
        nop
        nop
@@ -57,7 +57,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
 _GLOBAL(__arch_hweight32)
 BEGIN_FTR_SECTION
-        b .__sw_hweight32
+        b __sw_hweight32
        nop
        nop
        nop
@@ -82,7 +82,7 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
 _GLOBAL(__arch_hweight64)
 BEGIN_FTR_SECTION
-        b .__sw_hweight64
+        b __sw_hweight64
        nop
        nop
        nop
diff --git a/arch/powerpc/lib/mem_64.S b/arch/powerpc/lib/mem_64.S
index f4fcb0bc6563..0738f96befbf 100644
--- a/arch/powerpc/lib/mem_64.S
+++ b/arch/powerpc/lib/mem_64.S
@@ -79,8 +79,8 @@ _GLOBAL(memset)
 _GLOBAL(memmove)
        cmplw   0,r3,r4
-        bgt     .backwards_memcpy
+        bgt     backwards_memcpy
-        b       .memcpy
+        b       memcpy
 _GLOBAL(backwards_memcpy)
        rlwinm. r7,r5,32-3,3,31         /* r0 = r5 >> 3 */
diff --git a/arch/powerpc/lib/memcpy_64.S b/arch/powerpc/lib/memcpy_64.S
index 72ad055168a3..32a06ec395d2 100644
--- a/arch/powerpc/lib/memcpy_64.S
+++ b/arch/powerpc/lib/memcpy_64.S
@@ -10,14 +10,29 @@
 #include <asm/ppc_asm.h>
        .align  7
-_GLOBAL(memcpy)
+_GLOBAL_TOC(memcpy)
 BEGIN_FTR_SECTION
-        std     r3,48(r1)       /* save destination pointer for return value */
+#ifdef __LITTLE_ENDIAN__
+        cmpdi   cr7,r5,0
+#else
+        std     r3,-STACKFRAMESIZE+STK_REG(R31)(r1)     /* save destination pointer for return value */
+#endif
 FTR_SECTION_ELSE
 #ifndef SELFTEST
        b       memcpy_power7
 #endif
 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
+#ifdef __LITTLE_ENDIAN__
+        /* dumb little-endian memcpy that will get replaced at runtime */
+        addi r9,r3,-1
+        addi r4,r4,-1
+        beqlr cr7
+        mtctr r5
+1:      lbzu r10,1(r4)
+        stbu r10,1(r9)
+        bdnz 1b
+        blr
+#else
        PPC_MTOCRF(0x01,r5)
        cmpldi  cr1,r5,16
        neg     r6,r3           # LS 3 bits = # bytes to 8-byte dest bdry
@@ -73,7 +88,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
 2:      bf      cr7*4+3,3f
        lbz     r9,8(r4)
        stb     r9,0(r3)
-3:      ld      r3,48(r1)       /* return dest pointer */
+3:      ld      r3,-STACKFRAMESIZE+STK_REG(R31)(r1)     /* return dest pointer */
        blr
 .Lsrc_unaligned:
@@ -156,7 +171,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
 2:      bf      cr7*4+3,3f
        rotldi  r9,r9,8
        stb     r9,0(r3)
-3:      ld      r3,48(r1)       /* return dest pointer */
+3:      ld      r3,-STACKFRAMESIZE+STK_REG(R31)(r1)     /* return dest pointer */
        blr
 .Ldst_unaligned:
@@ -201,5 +216,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
 3:      bf      cr7*4+3,4f
        lbz     r0,0(r4)
        stb     r0,0(r3)
-4:      ld      r3,48(r1)       /* return dest pointer */
+4:      ld      r3,-STACKFRAMESIZE+STK_REG(R31)(r1)     /* return dest pointer */
        blr
+#endif
diff --git a/arch/powerpc/lib/memcpy_power7.S b/arch/powerpc/lib/memcpy_power7.S
index e4177dbea6bd..2ff5c142f87b 100644
--- a/arch/powerpc/lib/memcpy_power7.S
+++ b/arch/powerpc/lib/memcpy_power7.S
@@ -33,14 +33,14 @@ _GLOBAL(memcpy_power7)
        cmpldi  r5,16
        cmpldi  cr1,r5,4096
-        std     r3,48(r1)
+        std     r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
        blt     .Lshort_copy
        bgt     cr1,.Lvmx_copy
 #else
        cmpldi  r5,16
-        std     r3,48(r1)
+        std     r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
        blt     .Lshort_copy
 #endif
@@ -216,7 +216,7 @@ _GLOBAL(memcpy_power7)
        lbz     r0,0(r4)
        stb     r0,0(r3)
-15:     ld      r3,48(r1)
+15:     ld      r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
        blr
 .Lunwind_stack_nonvmx_copy:
@@ -226,16 +226,16 @@ _GLOBAL(memcpy_power7)
 #ifdef CONFIG_ALTIVEC
 .Lvmx_copy:
        mflr    r0
-        std     r4,56(r1)
+        std     r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
-        std     r5,64(r1)
+        std     r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
        std     r0,16(r1)
        stdu    r1,-STACKFRAMESIZE(r1)
-        bl      .enter_vmx_copy
+        bl      enter_vmx_copy
        cmpwi   cr1,r3,0
        ld      r0,STACKFRAMESIZE+16(r1)
-        ld      r3,STACKFRAMESIZE+48(r1)
+        ld      r3,STK_REG(R31)(r1)
-        ld      r4,STACKFRAMESIZE+56(r1)
+        ld      r4,STK_REG(R30)(r1)
-        ld      r5,STACKFRAMESIZE+64(r1)
+        ld      r5,STK_REG(R29)(r1)
        mtlr    r0
        /*
@@ -447,8 +447,8 @@ _GLOBAL(memcpy_power7)
        stb     r0,0(r3)
 15:     addi    r1,r1,STACKFRAMESIZE
-        ld      r3,48(r1)
+        ld      r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
-        b       .exit_vmx_copy          /* tail call optimise */
+        b       exit_vmx_copy           /* tail call optimise */
 .Lvmx_unaligned_copy:
        /* Get the destination 16B aligned */
@@ -651,6 +651,6 @@ _GLOBAL(memcpy_power7)
        stb     r0,0(r3)
 15:     addi    r1,r1,STACKFRAMESIZE
-        ld      r3,48(r1)
+        ld      r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
-        b       .exit_vmx_copy          /* tail call optimise */
+        b       exit_vmx_copy           /* tail call optimise */
 #endif /* CONFiG_ALTIVEC */
diff --git a/arch/powerpc/lib/string_64.S b/arch/powerpc/lib/string_64.S
index 3b1e48049faf..7bd9549a90a2 100644
--- a/arch/powerpc/lib/string_64.S
+++ b/arch/powerpc/lib/string_64.S
@@ -77,7 +77,7 @@ err3;	stb	r0,0(r3)
        mr      r3,r4
        blr
-_GLOBAL(__clear_user)
+_GLOBAL_TOC(__clear_user)
        cmpdi   r4,32
        neg     r6,r3
        li      r0,0
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index 1136d26a95ae..057cbbb4c576 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -159,7 +159,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
 BEGIN_FTR_SECTION
        mr      r4,r30
        mr      r5,r7
-        bl      .hash_page_do_lazy_icache
+        bl      hash_page_do_lazy_icache
 END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
        /* At this point, r3 contains new PP bits, save them in
@@ -201,7 +201,8 @@ htab_insert_pte:
        li      r8,MMU_PAGE_4K          /* page size */
        li      r9,MMU_PAGE_4K          /* actual page size */
        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
-_GLOBAL(htab_call_hpte_insert1)
+.globl htab_call_hpte_insert1
+htab_call_hpte_insert1:
        bl      .                       /* Patched by htab_finish_init() */
        cmpdi   0,r3,0
        bge     htab_pte_insert_ok      /* Insertion successful */
@@ -225,7 +226,8 @@ _GLOBAL(htab_call_hpte_insert1)
        li      r8,MMU_PAGE_4K          /* page size */
        li      r9,MMU_PAGE_4K          /* actual page size */
        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
-_GLOBAL(htab_call_hpte_insert2)
+.globl htab_call_hpte_insert2
+htab_call_hpte_insert2:
        bl      .                       /* Patched by htab_finish_init() */
        cmpdi   0,r3,0
        bge+    htab_pte_insert_ok      /* Insertion successful */
@@ -242,7 +244,8 @@ _GLOBAL(htab_call_hpte_insert2)
 2:      and     r0,r5,r27
        rldicr  r3,r0,3,63-3    /* r0 = (hash & mask) << 3 */   
        /* Call ppc_md.hpte_remove */
-_GLOBAL(htab_call_hpte_remove)
+.globl htab_call_hpte_remove
+htab_call_hpte_remove:
        bl      .                       /* Patched by htab_finish_init() */
        /* Try all again */
@@ -296,7 +299,8 @@ htab_modify_pte:
        li      r7,MMU_PAGE_4K          /* actual page size */
        ld      r8,STK_PARAM(R9)(r1)    /* segment size */
        ld      r9,STK_PARAM(R8)(r1)    /* get "local" param */
-_GLOBAL(htab_call_hpte_updatepp)
+.globl htab_call_hpte_updatepp
+htab_call_hpte_updatepp:
        bl      .                       /* Patched by htab_finish_init() */
        /* if we failed because typically the HPTE wasn't really here
@@ -471,7 +475,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
 BEGIN_FTR_SECTION
        mr      r4,r30
        mr      r5,r7
-        bl      .hash_page_do_lazy_icache
+        bl      hash_page_do_lazy_icache
 END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
        /* At this point, r3 contains new PP bits, save them in
@@ -526,7 +530,8 @@ htab_special_pfn:
        li      r8,MMU_PAGE_4K          /* page size */
        li      r9,MMU_PAGE_4K          /* actual page size */
        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
-_GLOBAL(htab_call_hpte_insert1)
+.globl htab_call_hpte_insert1
+htab_call_hpte_insert1:
        bl      .                       /* patched by htab_finish_init() */
        cmpdi   0,r3,0
        bge     htab_pte_insert_ok      /* Insertion successful */
@@ -554,7 +559,8 @@ _GLOBAL(htab_call_hpte_insert1)
        li      r8,MMU_PAGE_4K          /* page size */
        li      r9,MMU_PAGE_4K          /* actual page size */
        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
-_GLOBAL(htab_call_hpte_insert2)
+.globl htab_call_hpte_insert2
+htab_call_hpte_insert2:
        bl      .                       /* patched by htab_finish_init() */
        cmpdi   0,r3,0
        bge+    htab_pte_insert_ok      /* Insertion successful */
@@ -571,7 +577,8 @@ _GLOBAL(htab_call_hpte_insert2)
 2:      and     r0,r5,r27
        rldicr  r3,r0,3,63-3            /* r0 = (hash & mask) << 3 */
        /* Call ppc_md.hpte_remove */
-_GLOBAL(htab_call_hpte_remove)
+.globl htab_call_hpte_remove
+htab_call_hpte_remove:
        bl      .                       /* patched by htab_finish_init() */
        /* Try all again */
@@ -588,7 +595,7 @@ htab_inval_old_hpte:
        li      r6,MMU_PAGE_64K         /* psize */
        ld      r7,STK_PARAM(R9)(r1)    /* ssize */
        ld      r8,STK_PARAM(R8)(r1)    /* local */
-        bl      .flush_hash_page
+        bl      flush_hash_page
        /* Clear out _PAGE_HPTE_SUB bits in the new linux PTE */
        lis     r0,_PAGE_HPTE_SUB@h
        ori     r0,r0,_PAGE_HPTE_SUB@l
@@ -660,7 +667,8 @@ htab_modify_pte:
        li      r7,MMU_PAGE_4K          /* actual page size */
        ld      r8,STK_PARAM(R9)(r1)    /* segment size */
        ld      r9,STK_PARAM(R8)(r1)    /* get "local" param */
-_GLOBAL(htab_call_hpte_updatepp)
+.globl htab_call_hpte_updatepp
+htab_call_hpte_updatepp:
        bl      .                       /* patched by htab_finish_init() */
        /* if we failed because typically the HPTE wasn't really here
@@ -812,7 +820,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
 BEGIN_FTR_SECTION
        mr      r4,r30
        mr      r5,r7
-        bl      .hash_page_do_lazy_icache
+        bl      hash_page_do_lazy_icache
 END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
        /* At this point, r3 contains new PP bits, save them in
@@ -857,7 +865,8 @@ ht64_insert_pte:
        li      r8,MMU_PAGE_64K
        li      r9,MMU_PAGE_64K         /* actual page size */
        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
-_GLOBAL(ht64_call_hpte_insert1)
+.globl ht64_call_hpte_insert1
+ht64_call_hpte_insert1:
        bl      .                       /* patched by htab_finish_init() */
        cmpdi   0,r3,0
        bge     ht64_pte_insert_ok      /* Insertion successful */
@@ -881,7 +890,8 @@ _GLOBAL(ht64_call_hpte_insert1)
        li      r8,MMU_PAGE_64K
        li      r9,MMU_PAGE_64K         /* actual page size */
        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
-_GLOBAL(ht64_call_hpte_insert2)
+.globl ht64_call_hpte_insert2
+ht64_call_hpte_insert2:
        bl      .                       /* patched by htab_finish_init() */
        cmpdi   0,r3,0
        bge+    ht64_pte_insert_ok      /* Insertion successful */
@@ -898,7 +908,8 @@ _GLOBAL(ht64_call_hpte_insert2)
 2:      and     r0,r5,r27
        rldicr  r3,r0,3,63-3    /* r0 = (hash & mask) << 3 */
        /* Call ppc_md.hpte_remove */
-_GLOBAL(ht64_call_hpte_remove)
+.globl ht64_call_hpte_remove
+ht64_call_hpte_remove:
        bl      .                       /* patched by htab_finish_init() */
        /* Try all again */
@@ -952,7 +963,8 @@ ht64_modify_pte:
        li      r7,MMU_PAGE_64K         /* actual page size */
        ld      r8,STK_PARAM(R9)(r1)    /* segment size */
        ld      r9,STK_PARAM(R8)(r1)    /* get "local" param */
-_GLOBAL(ht64_call_hpte_updatepp)
+.globl ht64_call_hpte_updatepp
+ht64_call_hpte_updatepp:
        bl      .                       /* patched by htab_finish_init() */
        /* if we failed because typically the HPTE wasn't really here
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 350aa58a6f95..88fdd9d25077 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -449,6 +449,24 @@ static void mmu_psize_set_default_penc(void)
                        mmu_psize_defs[bpsize].penc[apsize] = -1;
 }
+#ifdef CONFIG_PPC_64K_PAGES
+static bool might_have_hea(void)
+{
+        /*
+         * The HEA ethernet adapter requires awareness of the
+         * GX bus. Without that awareness we can easily assume
+         * we will never see an HEA ethernet device.
+         */
+#ifdef CONFIG_IBMEBUS
+        return !cpu_has_feature(CPU_FTR_ARCH_207S);
+#else
+        return false;
+#endif
+}
+#endif /* #ifdef CONFIG_PPC_64K_PAGES */
 static void __init htab_init_page_sizes(void)
 {
        int rc;
@@ -503,10 +521,11 @@ static void __init htab_init_page_sizes(void)
                        mmu_linear_psize = MMU_PAGE_64K;
                if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
                        /*
-                         * Don't use 64k pages for ioremap on pSeries, since
+                         * When running on pSeries using 64k pages for ioremap
-                         * that would stop us accessing the HEA ethernet.
+                         * would stop us accessing the HEA ethernet. So if we
+                         * have the chance of ever seeing one, stay at 4k.
                         */
-                        if (!machine_is(pseries))
+                        if (!might_have_hea() || !machine_is(pseries))
                                mmu_io_psize = MMU_PAGE_64K;
                } else
                        mmu_ci_restrictions = 1;
@@ -607,47 +626,43 @@ int remove_section_mapping(unsigned long start, unsigned long end)
 }
 #endif /* CONFIG_MEMORY_HOTPLUG */
-#define FUNCTION_TEXT(A)        ((*(unsigned long *)(A)))
+extern u32 htab_call_hpte_insert1[];
+extern u32 htab_call_hpte_insert2[];
+extern u32 htab_call_hpte_remove[];
+extern u32 htab_call_hpte_updatepp[];
+extern u32 ht64_call_hpte_insert1[];
+extern u32 ht64_call_hpte_insert2[];
+extern u32 ht64_call_hpte_remove[];
+extern u32 ht64_call_hpte_updatepp[];
 static void __init htab_finish_init(void)
 {
-        extern unsigned int *htab_call_hpte_insert1;
-        extern unsigned int *htab_call_hpte_insert2;
-        extern unsigned int *htab_call_hpte_remove;
-        extern unsigned int *htab_call_hpte_updatepp;
 #ifdef CONFIG_PPC_HAS_HASH_64K
-        extern unsigned int *ht64_call_hpte_insert1;
-        extern unsigned int *ht64_call_hpte_insert2;
-        extern unsigned int *ht64_call_hpte_remove;
-        extern unsigned int *ht64_call_hpte_updatepp;
        patch_branch(ht64_call_hpte_insert1,
-                FUNCTION_TEXT(ppc_md.hpte_insert),
+                ppc_function_entry(ppc_md.hpte_insert),
                BRANCH_SET_LINK);
        patch_branch(ht64_call_hpte_insert2,
-                FUNCTION_TEXT(ppc_md.hpte_insert),
+                ppc_function_entry(ppc_md.hpte_insert),
                BRANCH_SET_LINK);
        patch_branch(ht64_call_hpte_remove,
-                FUNCTION_TEXT(ppc_md.hpte_remove),
+                ppc_function_entry(ppc_md.hpte_remove),
                BRANCH_SET_LINK);
        patch_branch(ht64_call_hpte_updatepp,
-                FUNCTION_TEXT(ppc_md.hpte_updatepp),
+                ppc_function_entry(ppc_md.hpte_updatepp),
                BRANCH_SET_LINK);
 #endif /* CONFIG_PPC_HAS_HASH_64K */
        patch_branch(htab_call_hpte_insert1,
-                FUNCTION_TEXT(ppc_md.hpte_insert),
+                ppc_function_entry(ppc_md.hpte_insert),
                BRANCH_SET_LINK);
        patch_branch(htab_call_hpte_insert2,
-                FUNCTION_TEXT(ppc_md.hpte_insert),
+                ppc_function_entry(ppc_md.hpte_insert),
                BRANCH_SET_LINK);
        patch_branch(htab_call_hpte_remove,
-                FUNCTION_TEXT(ppc_md.hpte_remove),
+                ppc_function_entry(ppc_md.hpte_remove),
                BRANCH_SET_LINK);
        patch_branch(htab_call_hpte_updatepp,
-                FUNCTION_TEXT(ppc_md.hpte_updatepp),
+                ppc_function_entry(ppc_md.hpte_updatepp),
                BRANCH_SET_LINK);
 }
@@ -964,6 +979,22 @@ void hash_failure_debug(unsigned long ea, unsigned long access,
                trap, vsid, ssize, psize, lpsize, pte);
 }
+static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
+                             int psize, bool user_region)
+{
+        if (user_region) {
+                if (psize != get_paca_psize(ea)) {
+                        get_paca()->context = mm->context;
+                        slb_flush_and_rebolt();
+                }
+        } else if (get_paca()->vmalloc_sllp !=
+                   mmu_psize_defs[mmu_vmalloc_psize].sllp) {
+                get_paca()->vmalloc_sllp =
+                        mmu_psize_defs[mmu_vmalloc_psize].sllp;
+                slb_vmalloc_update();
+        }
+}
 /* Result code is:
 *  0 - handled
 *  1 - normal page fault
@@ -1085,6 +1116,8 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
                        WARN_ON(1);
                }
 #endif
+                check_paca_psize(ea, mm, psize, user_region);
                goto bail;
        }
@@ -1125,17 +1158,8 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
 #endif
                }
        }
-        if (user_region) {
-                if (psize != get_paca_psize(ea)) {
+        check_paca_psize(ea, mm, psize, user_region);
-                        get_paca()->context = mm->context;
-                        slb_flush_and_rebolt();
-                }
-        } else if (get_paca()->vmalloc_sllp !=
-                   mmu_psize_defs[mmu_vmalloc_psize].sllp) {
-                get_paca()->vmalloc_sllp =
-                        mmu_psize_defs[mmu_vmalloc_psize].sllp;
-                slb_vmalloc_update();
-        }
 #endif /* CONFIG_PPC_64K_PAGES */
 #ifdef CONFIG_PPC_HAS_HASH_64K
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 964a5f61488a..0399a6702958 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -256,10 +256,14 @@ static inline void patch_slb_encoding(unsigned int *insn_addr,
        patch_instruction(insn_addr, insn);
 }
+extern u32 slb_compare_rr_to_size[];
+extern u32 slb_miss_kernel_load_linear[];
+extern u32 slb_miss_kernel_load_io[];
+extern u32 slb_compare_rr_to_size[];
+extern u32 slb_miss_kernel_load_vmemmap[];
 void slb_set_size(u16 size)
 {
-        extern unsigned int *slb_compare_rr_to_size;
        if (mmu_slb_size == size)
                return;
@@ -272,11 +276,7 @@ void slb_initialize(void)
        unsigned long linear_llp, vmalloc_llp, io_llp;
        unsigned long lflags, vflags;
        static int slb_encoding_inited;
-        extern unsigned int *slb_miss_kernel_load_linear;
-        extern unsigned int *slb_miss_kernel_load_io;
-        extern unsigned int *slb_compare_rr_to_size;
 #ifdef CONFIG_SPARSEMEM_VMEMMAP
-        extern unsigned int *slb_miss_kernel_load_vmemmap;
        unsigned long vmemmap_llp;
 #endif
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 17aa6dfceb34..736d18b3cefd 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -35,7 +35,7 @@ _GLOBAL(slb_allocate_realmode)
         * check for bad kernel/user address
         * (ea & ~REGION_MASK) >= PGTABLE_RANGE
         */
-        rldicr. r9,r3,4,(63 - 46 - 4)
+        rldicr. r9,r3,4,(63 - PGTABLE_EADDR_SIZE - 4)
        bne-    8f
        srdi    r9,r3,60                /* get region */
@@ -59,7 +59,8 @@ _GLOBAL(slb_allocate_realmode)
        /* Linear mapping encoding bits, the "li" instruction below will
         * be patched by the kernel at boot
         */
-_GLOBAL(slb_miss_kernel_load_linear)
+.globl slb_miss_kernel_load_linear
+slb_miss_kernel_load_linear:
        li      r11,0
        /*
         * context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
@@ -79,7 +80,8 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
        /* Check virtual memmap region. To be patches at kernel boot */
        cmpldi  cr0,r9,0xf
        bne     1f
-_GLOBAL(slb_miss_kernel_load_vmemmap)
+.globl slb_miss_kernel_load_vmemmap
+slb_miss_kernel_load_vmemmap:
        li      r11,0
        b       6f
 1:
@@ -95,7 +97,8 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
        b       6f
 5:
        /* IO mapping */
-        _GLOBAL(slb_miss_kernel_load_io)
+.globl slb_miss_kernel_load_io
+slb_miss_kernel_load_io:
        li      r11,0
 6:
        /*
@@ -250,7 +253,8 @@ slb_finish_load:
 7:      ld      r10,PACASTABRR(r13)
        addi    r10,r10,1
        /* This gets soft patched on boot. */
-_GLOBAL(slb_compare_rr_to_size)
+.globl slb_compare_rr_to_size
+slb_compare_rr_to_size:
        cmpldi  r10,0
        blt+    4f
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index ae3d5b799b90..92cb18d52ea8 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -596,8 +596,13 @@ static void __early_init_mmu(int boot_cpu)
        /* XXX This should be decided at runtime based on supported
         * page sizes in the TLB, but for now let's assume 16M is
         * always there and a good fit (which it probably is)
+         *
+         * Freescale booke only supports 4K pages in TLB0, so use that.
         */
-        mmu_vmemmap_psize = MMU_PAGE_16M;
+        if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
+                mmu_vmemmap_psize = MMU_PAGE_4K;
+        else
+                mmu_vmemmap_psize = MMU_PAGE_16M;
        /* XXX This code only checks for TLB 0 capabilities and doesn't
         *     check what page size combos are supported by the HW. It
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index dc1a264ec6e6..4d88f6a19058 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -199,6 +199,34 @@ config CURRITUCK
        help
          This option enables support for the IBM Currituck (476fpe) evaluation board
+config AKEBONO
+        bool "IBM Akebono (476gtr) Support"
+        depends on PPC_47x
+        default n
+        select SWIOTLB
+        select 476FPE
+        select PPC4xx_PCI_EXPRESS
+        select PCI_MSI
+        select PPC4xx_HSTA_MSI
+        select I2C
+        select I2C_IBM_IIC
+        select NETDEVICES
+        select ETHERNET
+        select NET_VENDOR_IBM
+        select IBM_EMAC_EMAC4
+        select IBM_EMAC_RGMII_WOL
+        select USB
+        select USB_OHCI_HCD_PLATFORM
+        select USB_EHCI_HCD_PLATFORM
+        select MMC_SDHCI
+        select MMC_SDHCI_PLTFM
+        select MMC_SDHCI_OF_476GTR
+        select ATA
+        select SATA_AHCI_PLATFORM
+        help
+          This option enables support for the IBM Akebono (476gtr) evaluation board
 config ICON
        bool "Icon"
        depends on 44x
@@ -323,6 +351,20 @@ config APM821xx
        select IBM_EMAC_EMAC4
        select IBM_EMAC_TAH
+config 476FPE_ERR46
+        depends on 476FPE
+        bool "Enable linker work around for PPC476FPE errata #46"
+        help
+          This option enables a work around for an icache bug on 476
+          that can cause execution of stale instructions when falling
+          through pages (IBM errata #46). It requires a recent version
+          of binutils which supports the --ppc476-workaround option.
+          The work around enables the appropriate linker options and
+          ensures that all module output sections are aligned to 4K
+          page boundaries. The work around is only required when
+          building modules.
 # 44x errata/workaround config symbols, selected by the CPU models above
 config IBM440EP_ERR42
        bool
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index d03833abec09..26d35b5941f7 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -10,4 +10,5 @@ obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
 obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
 obj-$(CONFIG_ISS4xx)    += iss4xx.o
 obj-$(CONFIG_CANYONLANDS)+= canyonlands.o
-obj-$(CONFIG_CURRITUCK) += currituck.o
+obj-$(CONFIG_CURRITUCK) += ppc476.o
+obj-$(CONFIG_AKEBONO)   += ppc476.o
diff --git a/arch/powerpc/platforms/44x/currituck.c b/arch/powerpc/platforms/44x/ppc476.c
index 7f1b71a01c6a..33986c1a05da 100644
--- a/arch/powerpc/platforms/44x/currituck.c
+++ b/arch/powerpc/platforms/44x/ppc476.c
@@ -1,7 +1,8 @@
 /*
- * Currituck board specific routines
+ * PowerPC 476FPE board specific routines
 *
- * Copyright © 2011 Tony Breeds IBM Corporation
+ * Copyright © 2013 Tony Breeds IBM Corporation
+ * Copyright © 2013 Alistair Popple IBM Corporation
 *
 * Based on earlier code:
 *    Matt Porter <mporter@kernel.crashing.org>
@@ -35,8 +36,9 @@
 #include <asm/mmu.h>
 #include <linux/pci.h>
+#include <linux/i2c.h>
-static __initdata struct of_device_id ppc47x_of_bus[] = {
+static struct of_device_id ppc47x_of_bus[] __initdata = {
        { .compatible = "ibm,plb4", },
        { .compatible = "ibm,plb6", },
        { .compatible = "ibm,opb", },
@@ -55,15 +57,69 @@ static void quirk_ppc_currituck_usb_fixup(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(0x1033, 0x0035, quirk_ppc_currituck_usb_fixup);
+/* Akebono has an AVR microcontroller attached to the I2C bus
+ * which is used to power off/reset the system. */
+/* AVR I2C Commands */
+#define AVR_PWRCTL_CMD (0x26)
+/* Flags for the power control I2C commands */
+#define AVR_PWRCTL_PWROFF (0x01)
+#define AVR_PWRCTL_RESET (0x02)
+static struct i2c_client *avr_i2c_client;
+static void avr_halt_system(int pwrctl_flags)
+{
+        /* Request the AVR to reset the system */
+        i2c_smbus_write_byte_data(avr_i2c_client,
+                                  AVR_PWRCTL_CMD, pwrctl_flags);
+        /* Wait for system to be reset */
+        while (1)
+                ;
+}
+static void avr_power_off_system(void)
+{
+        avr_halt_system(AVR_PWRCTL_PWROFF);
+}
+static void avr_reset_system(char *cmd)
+{
+        avr_halt_system(AVR_PWRCTL_RESET);
+}
+static int avr_probe(struct i2c_client *client,
+                            const struct i2c_device_id *id)
+{
+        avr_i2c_client = client;
+        ppc_md.restart = avr_reset_system;
+        ppc_md.power_off = avr_power_off_system;
+        return 0;
+}
+static const struct i2c_device_id avr_id[] = {
+        { "akebono-avr", 0 },
+        { }
+};
+static struct i2c_driver avr_driver = {
+        .driver = {
+                .name = "akebono-avr",
+        },
+        .probe = avr_probe,
+        .id_table = avr_id,
+};
 static int __init ppc47x_device_probe(void)
 {
+        i2c_add_driver(&avr_driver);
        of_platform_bus_probe(NULL, ppc47x_of_bus, NULL);
        return 0;
 }
 machine_device_initcall(ppc47x, ppc47x_device_probe);
-/* We can have either UICs or MPICs */
 static void __init ppc47x_init_irq(void)
 {
        struct device_node *np;
@@ -157,43 +213,36 @@ static void __init ppc47x_setup_arch(void)
 {
        /* No need to check the DMA config as we /know/ our windows are all of
-         * RAM.  Lets hope that doesn't change */
+         * RAM.  Lets hope that doesn't change */
        swiotlb_detect_4g();
        ppc47x_smp_init();
 }
-/*
- * Called very early, MMU is off, device-tree isn't unflattened
- */
-static int __init ppc47x_probe(void)
-{
-        unsigned long root = of_get_flat_dt_root();
-        if (!of_flat_dt_is_compatible(root, "ibm,currituck"))
-                return 0;
-        return 1;
-}
 static int board_rev = -1;
 static int __init ppc47x_get_board_rev(void)
 {
-        u8 fpga_reg0;
+        int reg;
-        void *fpga;
+        u8 *fpga;
-        struct device_node *np;
+        struct device_node *np = NULL;
+        if (of_machine_is_compatible("ibm,currituck")) {
+                np = of_find_compatible_node(NULL, NULL, "ibm,currituck-fpga");
+                reg = 0;
+        } else if (of_machine_is_compatible("ibm,akebono")) {
+                np = of_find_compatible_node(NULL, NULL, "ibm,akebono-fpga");
+                reg = 2;
+        }
-        np = of_find_compatible_node(NULL, NULL, "ibm,currituck-fpga");
        if (!np)
                goto fail;
-        fpga = of_iomap(np, 0);
+        fpga = (u8 *) of_iomap(np, 0);
        of_node_put(np);
        if (!fpga)
                goto fail;
-        fpga_reg0 = ioread8(fpga);
+        board_rev = ioread8(fpga + reg) & 0x03;
-        board_rev = fpga_reg0 & 0x03;
        pr_info("%s: Found board revision %d\n", __func__, board_rev);
        iounmap(fpga);
        return 0;
@@ -208,7 +257,7 @@ machine_arch_initcall(ppc47x, ppc47x_get_board_rev);
 static void ppc47x_pci_irq_fixup(struct pci_dev *dev)
 {
        if (dev->vendor == 0x1033 && (dev->device == 0x0035 ||
-                                      dev->device == 0x00e0)) {
+                                      dev->device == 0x00e0)) {
                if (board_rev == 0) {
                        dev->irq = irq_create_mapping(NULL, 47);
                        pr_info("%s: Mapping irq %d\n", __func__, dev->irq);
@@ -221,13 +270,30 @@ static void ppc47x_pci_irq_fixup(struct pci_dev *dev)
        }
 }
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init ppc47x_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+        if (of_flat_dt_is_compatible(root, "ibm,akebono"))
+                return 1;
+        if (of_flat_dt_is_compatible(root, "ibm,currituck")) {
+                ppc_md.pci_irq_fixup = ppc47x_pci_irq_fixup;
+                return 1;
+        }
+        return 0;
+}
 define_machine(ppc47x) {
        .name                   = "PowerPC 47x",
        .probe                  = ppc47x_probe,
        .progress               = udbg_progress,
        .init_IRQ               = ppc47x_init_irq,
        .setup_arch             = ppc47x_setup_arch,
-        .pci_irq_fixup          = ppc47x_pci_irq_fixup,
        .restart                = ppc4xx_reset_system,
        .calibrate_decr         = generic_calibrate_decr,
 };
diff --git a/arch/powerpc/platforms/44x/ppc476_modules.lds b/arch/powerpc/platforms/44x/ppc476_modules.lds
new file mode 100644
index 000000000000..9fec5d34ba8e
--- /dev/null
+++ b/arch/powerpc/platforms/44x/ppc476_modules.lds
@@ -0,0 +1,15 @@
+SECTIONS
+{
+        .text : ALIGN(4096)
+        {
+                *(.text .text.* .fixup)
+        }
+        .init.text : ALIGN(4096)
+        {
+                *(.init.text .init.text.*)
+        }
+        .exit.text : ALIGN(4096)
+        {
+                *(.exit.text .exit.text.*)
+        }
+}
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index c17aae80e7ff..f442120e0033 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -38,6 +38,15 @@ config C293_PCIE
          help
          This option enables support for the C293PCIE board
+config BSC9132_QDS
+        bool "Freescale BSC9132QDS"
+        select DEFAULT_UIMAGE
+        help
+          This option enables support for the Freescale BSC9132 QDS board.
+          BSC9132 is a heterogeneous SoC containing dual e500v2 powerpc cores
+          and dual StarCore SC3850 DSP cores.
+          Manufacturer : Freescale Semiconductor, Inc
 config MPC8540_ADS
        bool "Freescale MPC8540 ADS"
        select DEFAULT_UIMAGE
@@ -117,11 +126,11 @@ config P1022_RDK
          This option enables support for the Freescale / iVeia P1022RDK
          reference board.
-config P1023_RDS
+config P1023_RDB
-        bool "Freescale P1023 RDS/RDB"
+        bool "Freescale P1023 RDB"
        select DEFAULT_UIMAGE
        help
-          This option enables support for the P1023 RDS and RDB boards
+          This option enables support for the P1023 RDB board.
 config TWR_P102x
        bool "Freescale TWR-P102x"
@@ -263,11 +272,11 @@ config CORENET_GENERIC
        help
          This option enables support for the FSL CoreNet based boards.
          For 32bit kernel, the following boards are supported:
-            P2041 RDB, P3041 DS and P4080 DS
+            P2041 RDB, P3041 DS, P4080 DS, kmcoge4, and OCA4080
          For 64bit kernel, the following boards are supported:
            T4240 QDS and B4 QDS
          The following boards are supported for both 32bit and 64bit kernel:
-            P5020 DS and P5040 DS
+            P5020 DS, P5040 DS and T104xQDS
 endif # FSL_SOC_BOOKE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 25cebe74ac46..730326046625 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) += smp.o
 obj-y += common.o
 obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
+obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o
 obj-$(CONFIG_C293_PCIE)   += c293pcie.o
 obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
@@ -17,7 +18,7 @@ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
 obj-$(CONFIG_P1010_RDB)   += p1010rdb.o
 obj-$(CONFIG_P1022_DS)    += p1022_ds.o
 obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o
-obj-$(CONFIG_P1023_RDS)   += p1023_rds.o
+obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o
 obj-$(CONFIG_TWR_P102x)   += twr_p102x.o
 obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
diff --git a/arch/powerpc/platforms/85xx/bsc913x_qds.c b/arch/powerpc/platforms/85xx/bsc913x_qds.c
new file mode 100644
index 000000000000..f0927e58af25
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/bsc913x_qds.c
@@ -0,0 +1,74 @@
+/*
+ * BSC913xQDS Board Setup
+ *
+ * Author:
+ *   Harninder Rai <harninder.rai@freescale.com>
+ *   Priyanka Jain <Priyanka.Jain@freescale.com>
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <asm/mpic.h>
+#include <sysdev/fsl_soc.h>
+#include <asm/udbg.h>
+#include "mpc85xx.h"
+#include "smp.h"
+void __init bsc913x_qds_pic_init(void)
+{
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+          MPIC_SINGLE_DEST_CPU,
+          0, 256, " OpenPIC  ");
+        if (!mpic)
+                pr_err("bsc913x: Failed to allocate MPIC structure\n");
+        else
+                mpic_init(mpic);
+}
+/*
+ * Setup the architecture
+ */
+static void __init bsc913x_qds_setup_arch(void)
+{
+        if (ppc_md.progress)
+                ppc_md.progress("bsc913x_qds_setup_arch()", 0);
+#if defined(CONFIG_SMP)
+        mpc85xx_smp_init();
+#endif
+        pr_info("bsc913x board from Freescale Semiconductor\n");
+}
+machine_device_initcall(bsc9132_qds, mpc85xx_common_publish_devices);
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init bsc9132_qds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+        return of_flat_dt_is_compatible(root, "fsl,bsc9132qds");
+}
+define_machine(bsc9132_qds) {
+        .name                   = "BSC9132 QDS",
+        .probe                  = bsc9132_qds_probe,
+        .setup_arch             = bsc913x_qds_setup_arch,
+        .init_IRQ               = bsc913x_qds_pic_init,
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index 8e4b1e1a4911..5db1e117fdde 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -67,7 +67,7 @@ void __init corenet_gen_setup_arch(void)
        swiotlb_detect_4g();
-        pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
+        pr_info("%s board\n", ppc_md.name);
        mpc85xx_qe_init();
 }
@@ -115,6 +115,7 @@ int __init corenet_gen_publish_devices(void)
 static const char * const boards[] __initconst = {
        "fsl,P2041RDB",
        "fsl,P3041DS",
+        "fsl,OCA4080",
        "fsl,P4080DS",
        "fsl,P5020DS",
        "fsl,P5040DS",
@@ -122,12 +123,16 @@ static const char * const boards[] __initconst = {
        "fsl,B4860QDS",
        "fsl,B4420QDS",
        "fsl,B4220QDS",
+        "fsl,T1040QDS",
+        "fsl,T1042QDS",
+        "keymile,kmcoge4",
        NULL
 };
 static const char * const hv_boards[] __initconst = {
        "fsl,P2041RDB-hv",
        "fsl,P3041DS-hv",
+        "fsl,OCA4080-hv",
        "fsl,P4080DS-hv",
        "fsl,P5020DS-hv",
        "fsl,P5040DS-hv",
@@ -135,6 +140,8 @@ static const char * const hv_boards[] __initconst = {
        "fsl,B4860QDS-hv",
        "fsl,B4420QDS-hv",
        "fsl,B4220QDS-hv",
+        "fsl,T1040QDS-hv",
+        "fsl,T1042QDS-hv",
        NULL
 };
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rdb.c
index 0e614007acfb..d5b7509825de 100644
--- a/arch/powerpc/platforms/85xx/p1023_rds.c
+++ b/arch/powerpc/platforms/85xx/p1023_rdb.c
@@ -4,7 +4,7 @@
 * Author: Roy Zang <tie-fei.zang@freescale.com>
 *
 * Description:
- * P1023 RDS Board Setup
+ * P1023 RDB Board Setup
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
@@ -41,12 +41,12 @@
 * Setup the architecture
 *
 */
-static void __init mpc85xx_rds_setup_arch(void)
+static void __init mpc85xx_rdb_setup_arch(void)
 {
        struct device_node *np;
        if (ppc_md.progress)
-                ppc_md.progress("p1023_rds_setup_arch()", 0);
+                ppc_md.progress("p1023_rdb_setup_arch()", 0);
        /* Map BCSR area */
        np = of_find_node_by_name(NULL, "bcsr");
@@ -85,10 +85,9 @@ static void __init mpc85xx_rds_setup_arch(void)
        fsl_pci_assign_primary();
 }
-machine_arch_initcall(p1023_rds, mpc85xx_common_publish_devices);
 machine_arch_initcall(p1023_rdb, mpc85xx_common_publish_devices);
-static void __init mpc85xx_rds_pic_init(void)
+static void __init mpc85xx_rdb_pic_init(void)
 {
        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
                MPIC_SINGLE_DEST_CPU,
@@ -99,14 +98,6 @@ static void __init mpc85xx_rds_pic_init(void)
        mpic_init(mpic);
 }
-static int __init p1023_rds_probe(void)
-{
-        unsigned long root = of_get_flat_dt_root();
-        return of_flat_dt_is_compatible(root, "fsl,P1023RDS");
-}
 static int __init p1023_rdb_probe(void)
 {
        unsigned long root = of_get_flat_dt_root();
@@ -115,26 +106,11 @@ static int __init p1023_rdb_probe(void)
 }
-define_machine(p1023_rds) {
-        .name                   = "P1023 RDS",
-        .probe                  = p1023_rds_probe,
-        .setup_arch             = mpc85xx_rds_setup_arch,
-        .init_IRQ               = mpc85xx_rds_pic_init,
-        .get_irq                = mpic_get_irq,
-        .restart                = fsl_rstcr_restart,
-        .calibrate_decr         = generic_calibrate_decr,
-        .progress               = udbg_progress,
-#ifdef CONFIG_PCI
-        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
-        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
-#endif
-};
 define_machine(p1023_rdb) {
        .name                   = "P1023 RDB",
        .probe                  = p1023_rdb_probe,
-        .setup_arch             = mpc85xx_rds_setup_arch,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
-        .init_IRQ               = mpc85xx_rds_pic_init,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
        .calibrate_decr         = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 6382098d6f8d..ba093f553678 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -27,6 +27,7 @@
 #include <asm/cacheflush.h>
 #include <asm/dbell.h>
 #include <asm/fsl_guts.h>
+#include <asm/code-patching.h>
 #include <sysdev/fsl_soc.h>
 #include <sysdev/mpic.h>
@@ -267,7 +268,7 @@ out:
        flush_spin_table(spin_table);
        out_be32(&spin_table->pir, hw_cpu);
        out_be64((u64 *)(&spin_table->addr_h),
-          __pa((u64)*((unsigned long long *)generic_secondary_smp_init)));
+                __pa(ppc_function_entry(generic_secondary_smp_init)));
        flush_spin_table(spin_table);
 #endif
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index d9e2b19b7c8d..43b65ad1970a 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -422,6 +422,7 @@ config CPU_BIG_ENDIAN
 config CPU_LITTLE_ENDIAN
        bool "Build little endian kernel"
+        select PPC64_BOOT_WRAPPER
        help
          Build a little endian kernel.
@@ -430,3 +431,7 @@ config CPU_LITTLE_ENDIAN
          little endian powerpc.
 endchoice
+config PPC64_BOOT_WRAPPER
+        def_bool n
+        depends on CPU_LITTLE_ENDIAN
diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c
index 90745eaa45fe..c8017a7bcabd 100644
--- a/arch/powerpc/platforms/cell/smp.c
+++ b/arch/powerpc/platforms/cell/smp.c
@@ -40,6 +40,7 @@
 #include <asm/firmware.h>
 #include <asm/rtas.h>
 #include <asm/cputhreads.h>
+#include <asm/code-patching.h>
 #include "interrupt.h"
 #include <asm/udbg.h>
@@ -70,8 +71,8 @@ static cpumask_t of_spin_map;
 static inline int smp_startup_cpu(unsigned int lcpu)
 {
        int status;
-        unsigned long start_here = __pa((u32)*((unsigned long *)
+        unsigned long start_here =
-                                               generic_secondary_smp_init));
+                        __pa(ppc_function_entry(generic_secondary_smp_init));
        unsigned int pcpu;
        int start_cpu;
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 2a7024d8d8b1..a25f496c2ef9 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -65,6 +65,7 @@ config MVME5100
        select PPC_INDIRECT_PCI
        select PPC_I8259
        select PPC_NATIVE
+        select PPC_UDBG_16550
        help
          This option enables support for the Motorola (now Emerson) MVME5100
          board.
diff --git a/arch/powerpc/platforms/pasemi/powersave.S b/arch/powerpc/platforms/pasemi/powersave.S
index 56f45adcd089..81ab555aa491 100644
--- a/arch/powerpc/platforms/pasemi/powersave.S
+++ b/arch/powerpc/platforms/pasemi/powersave.S
@@ -66,7 +66,7 @@ sleep_common:
        std     r3, 48(r1)
        /* Only do power savings when in astate 0 */
-        bl      .check_astate
+        bl      check_astate
        cmpwi   r3,0
        bne     1f
diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
index 63cebb9b4d45..4ad0d345bc96 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -1,7 +1,7 @@
 obj-y                   += setup.o opal-takeover.o opal-wrappers.o opal.o opal-async.o
 obj-y                   += opal-rtc.o opal-nvram.o opal-lpc.o opal-flash.o
 obj-y                   += rng.o opal-elog.o opal-dump.o opal-sysparam.o opal-sensor.o
-obj-y                   += opal-msglog.o
+obj-y                   += opal-msglog.o subcore.o subcore-asm.o
 obj-$(CONFIG_SMP)       += smp.o
 obj-$(CONFIG_PCI)       += pci.o pci-p5ioc2.o pci-ioda.o
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
index 5b51079f3e3b..753f08e36dfa 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -42,11 +42,19 @@ static int ioda_eeh_event(struct notifier_block *nb,
 {
        uint64_t changed_evts = (uint64_t)change;
-        /* We simply send special EEH event */
+        /*
-        if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
+         * We simply send special EEH event if EEH has
-            (events & OPAL_EVENT_PCI_ERROR) &&
+         * been enabled, or clear pending events in
-            eeh_enabled())
+         * case that we enable EEH soon
+         */
+        if (!(changed_evts & OPAL_EVENT_PCI_ERROR) ||
+            !(events & OPAL_EVENT_PCI_ERROR))
+                return 0;
+        if (eeh_enabled())
                eeh_send_failure_event(NULL);
+        else
+                opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
        return 0;
 }
@@ -141,7 +149,9 @@ static int ioda_eeh_post_init(struct pci_controller *hose)
        }
 #ifdef CONFIG_DEBUG_FS
-        if (phb->dbgfs) {
+        if (!phb->has_dbgfs && phb->dbgfs) {
+                phb->has_dbgfs = 1;
                debugfs_create_file("err_injct_outbound", 0600,
                                    phb->dbgfs, hose,
                                    &ioda_eeh_outb_dbgfs_ops);
@@ -154,7 +164,14 @@ static int ioda_eeh_post_init(struct pci_controller *hose)
        }
 #endif
-        phb->eeh_state |= PNV_EEH_STATE_ENABLED;
+        /* If EEH is enabled, we're going to rely on that.
+         * Otherwise, we restore to conventional mechanism
+         * to clear frozen PE during PCI config access.
+         */
+        if (eeh_enabled())
+                phb->flags |= PNV_PHB_FLAG_EEH;
+        else
+                phb->flags &= ~PNV_PHB_FLAG_EEH;
        return 0;
 }
@@ -268,6 +285,21 @@ static int ioda_eeh_get_state(struct eeh_pe *pe)
                return EEH_STATE_NOT_SUPPORT;
        }
+        /*
+         * If we're in middle of PE reset, return normal
+         * state to keep EEH core going. For PHB reset, we
+         * still expect to have fenced PHB cleared with
+         * PHB reset.
+         */
+        if (!(pe->type & EEH_PE_PHB) &&
+            (pe->state & EEH_PE_RESET)) {
+                result = (EEH_STATE_MMIO_ACTIVE |
+                          EEH_STATE_DMA_ACTIVE |
+                          EEH_STATE_MMIO_ENABLED |
+                          EEH_STATE_DMA_ENABLED);
+                return result;
+        }
        /* Retrieve PE status through OPAL */
        pe_no = pe->addr;
        ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
@@ -347,52 +379,6 @@ static int ioda_eeh_get_state(struct eeh_pe *pe)
        return result;
 }
-static int ioda_eeh_pe_clear(struct eeh_pe *pe)
-{
-        struct pci_controller *hose;
-        struct pnv_phb *phb;
-        u32 pe_no;
-        u8 fstate;
-        u16 pcierr;
-        s64 ret;
-        pe_no = pe->addr;
-        hose = pe->phb;
-        phb = pe->phb->private_data;
-        /* Clear the EEH error on the PE */
-        ret = opal_pci_eeh_freeze_clear(phb->opal_id,
-                        pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
-        if (ret) {
-                pr_err("%s: Failed to clear EEH error for "
-                       "PHB#%x-PE#%x, err=%lld\n",
-                       __func__, hose->global_number, pe_no, ret);
-                return -EIO;
-        }
-        /*
-         * Read the PE state back and verify that the frozen
-         * state has been removed.
-         */
-        ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
-                        &fstate, &pcierr, NULL);
-        if (ret) {
-                pr_err("%s: Failed to get EEH status on "
-                       "PHB#%x-PE#%x\n, err=%lld\n",
-                       __func__, hose->global_number, pe_no, ret);
-                return -EIO;
-        }
-        if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) {
-                pr_err("%s: Frozen state not cleared on "
-                       "PHB#%x-PE#%x, sts=%x\n",
-                       __func__, hose->global_number, pe_no, fstate);
-                return -EIO;
-        }
-        return 0;
-}
 static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
 {
        s64 rc = OPAL_HARDWARE;
@@ -402,13 +388,16 @@ static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
                if (rc <= 0)
                        break;
-                msleep(rc);
+                if (system_state < SYSTEM_RUNNING)
+                        udelay(1000 * rc);
+                else
+                        msleep(rc);
        }
        return rc;
 }
-static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
+int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
 {
        struct pnv_phb *phb = hose->private_data;
        s64 rc = OPAL_HARDWARE;
@@ -431,9 +420,17 @@ static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
        /*
         * Poll state of the PHB until the request is done
-         * successfully.
+         * successfully. The PHB reset is usually PHB complete
+         * reset followed by hot reset on root bus. So we also
+         * need the PCI bus settlement delay.
         */
        rc = ioda_eeh_phb_poll(phb);
+        if (option == EEH_RESET_DEACTIVATE) {
+                if (system_state < SYSTEM_RUNNING)
+                        udelay(1000 * EEH_PE_RST_SETTLE_TIME);
+                else
+                        msleep(EEH_PE_RST_SETTLE_TIME);
+        }
 out:
        if (rc != OPAL_SUCCESS)
                return -EIO;
@@ -471,6 +468,8 @@ static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
        /* Poll state of the PHB until the request is done */
        rc = ioda_eeh_phb_poll(phb);
+        if (option == EEH_RESET_DEACTIVATE)
+                msleep(EEH_PE_RST_SETTLE_TIME);
 out:
        if (rc != OPAL_SUCCESS)
                return -EIO;
@@ -478,32 +477,71 @@ out:
        return 0;
 }
-static int ioda_eeh_bridge_reset(struct pci_controller *hose,
+static int ioda_eeh_bridge_reset(struct pci_dev *dev, int option)
-                struct pci_dev *dev, int option)
 {
-        u16 ctrl;
+        struct device_node *dn = pci_device_to_OF_node(dev);
+        struct eeh_dev *edev = of_node_to_eeh_dev(dn);
+        int aer = edev ? edev->aer_cap : 0;
+        u32 ctrl;
-        pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n",
+        pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
-                 __func__, hose->global_number, dev->bus->number,
+                 __func__, pci_domain_nr(dev->bus),
-                 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option);
+                 dev->bus->number, option);
        switch (option) {
        case EEH_RESET_FUNDAMENTAL:
        case EEH_RESET_HOT:
-                pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
+                /* Don't report linkDown event */
+                if (aer) {
+                        eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
+                                             4, &ctrl);
+                        ctrl |= PCI_ERR_UNC_SURPDN;
+                        eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
+                                              4, ctrl);
+                }
+                eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl);
                ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
-                pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
+                eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl);
+                msleep(EEH_PE_RST_HOLD_TIME);
                break;
        case EEH_RESET_DEACTIVATE:
-                pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
+                eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl);
                ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
-                pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
+                eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl);
+                msleep(EEH_PE_RST_SETTLE_TIME);
+                /* Continue reporting linkDown event */
+                if (aer) {
+                        eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
+                                             4, &ctrl);
+                        ctrl &= ~PCI_ERR_UNC_SURPDN;
+                        eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
+                                              4, ctrl);
+                }
                break;
        }
        return 0;
 }
+void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
+{
+        struct pci_controller *hose;
+        if (pci_is_root_bus(dev->bus)) {
+                hose = pci_bus_to_host(dev->bus);
+                ioda_eeh_root_reset(hose, EEH_RESET_HOT);
+                ioda_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
+        } else {
+                ioda_eeh_bridge_reset(dev, EEH_RESET_HOT);
+                ioda_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
+        }
+}
 /**
 * ioda_eeh_reset - Reset the indicated PE
 * @pe: EEH PE
@@ -523,27 +561,18 @@ static int ioda_eeh_reset(struct eeh_pe *pe, int option)
        int ret;
        /*
-         * Anyway, we have to clear the problematic state for the
+         * For PHB reset, we always have complete reset. For those PEs whose
-         * corresponding PE. However, we needn't do it if the PE
+         * primary bus derived from root complex (root bus) or root port
-         * is PHB associated. That means the PHB is having fatal
+         * (usually bus#1), we apply hot or fundamental reset on the root port.
-         * errors and it needs reset. Further more, the AIB interface
+         * For other PEs, we always have hot reset on the PE primary bus.
-         * isn't reliable any more.
-         */
-        if (!(pe->type & EEH_PE_PHB) &&
-            (option == EEH_RESET_HOT ||
-            option == EEH_RESET_FUNDAMENTAL)) {
-                ret = ioda_eeh_pe_clear(pe);
-                if (ret)
-                        return -EIO;
-        }
-        /*
-         * The rules applied to reset, either fundamental or hot reset:
         *
-         * We always reset the direct upstream bridge of the PE. If the
+         * Here, we have different design to pHyp, which always clear the
-         * direct upstream bridge isn't root bridge, we always take hot
+         * frozen state during PE reset. However, the good idea here from
-         * reset no matter what option (fundamental or hot) is. Otherwise,
+         * benh is to keep frozen state before we get PE reset done completely
-         * we should do the reset according to the required option.
+         * (until BAR restore). With the frozen state, HW drops illegal IO
+         * or MMIO access, which can incur recrusive frozen PE during PE
+         * reset. The side effect is that EEH core has to clear the frozen
+         * state explicitly after BAR restore.
         */
        if (pe->type & EEH_PE_PHB) {
                ret = ioda_eeh_phb_reset(hose, option);
@@ -553,7 +582,7 @@ static int ioda_eeh_reset(struct eeh_pe *pe, int option)
                    pci_is_root_bus(bus->parent))
                        ret = ioda_eeh_root_reset(hose, option);
                else
-                        ret = ioda_eeh_bridge_reset(hose, bus->self, option);
+                        ret = ioda_eeh_bridge_reset(bus->self, option);
        }
        return ret;
@@ -640,22 +669,6 @@ static void ioda_eeh_hub_diag(struct pci_controller *hose)
        }
 }
-static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
-                               struct eeh_pe **pe)
-{
-        struct eeh_pe *phb_pe;
-        phb_pe = eeh_phb_pe_get(hose);
-        if (!phb_pe) {
-                pr_warning("%s Can't find PE for PHB#%d\n",
-                           __func__, hose->global_number);
-                return -EEXIST;
-        }
-        *pe = phb_pe;
-        return 0;
-}
 static int ioda_eeh_get_pe(struct pci_controller *hose,
                           u16 pe_no, struct eeh_pe **pe)
 {
@@ -663,7 +676,8 @@ static int ioda_eeh_get_pe(struct pci_controller *hose,
        struct eeh_dev dev;
        /* Find the PHB PE */
-        if (ioda_eeh_get_phb_pe(hose, &phb_pe))
+        phb_pe = eeh_phb_pe_get(hose);
+        if (!phb_pe)
                return -EEXIST;
        /* Find the PE according to PE# */
@@ -691,6 +705,7 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
 {
        struct pci_controller *hose;
        struct pnv_phb *phb;
+        struct eeh_pe *phb_pe;
        u64 frozen_pe_no;
        u16 err_type, severity;
        long rc;
@@ -707,10 +722,12 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
        list_for_each_entry(hose, &hose_list, list_node) {
                /*
                 * If the subordinate PCI buses of the PHB has been
-                 * removed, we needn't take care of it any more.
+                 * removed or is exactly under error recovery, we
+                 * needn't take care of it any more.
                 */
                phb = hose->private_data;
-                if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
+                phb_pe = eeh_phb_pe_get(hose);
+                if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
                        continue;
                rc = opal_pci_next_error(phb->opal_id,
@@ -743,12 +760,6 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
                switch (err_type) {
                case OPAL_EEH_IOC_ERROR:
                        if (severity == OPAL_EEH_SEV_IOC_DEAD) {
-                                list_for_each_entry(hose, &hose_list,
-                                                    list_node) {
-                                        phb = hose->private_data;
-                                        phb->eeh_state |= PNV_EEH_STATE_REMOVED;
-                                }
                                pr_err("EEH: dead IOC detected\n");
                                ret = EEH_NEXT_ERR_DEAD_IOC;
                        } else if (severity == OPAL_EEH_SEV_INF) {
@@ -761,17 +772,12 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
                        break;
                case OPAL_EEH_PHB_ERROR:
                        if (severity == OPAL_EEH_SEV_PHB_DEAD) {
-                                if (ioda_eeh_get_phb_pe(hose, pe))
+                                *pe = phb_pe;
-                                        break;
                                pr_err("EEH: dead PHB#%x detected\n",
                                        hose->global_number);
-                                phb->eeh_state |= PNV_EEH_STATE_REMOVED;
                                ret = EEH_NEXT_ERR_DEAD_PHB;
                        } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
-                                if (ioda_eeh_get_phb_pe(hose, pe))
+                                *pe = phb_pe;
-                                        break;
                                pr_err("EEH: fenced PHB#%x detected\n",
                                        hose->global_number);
                                ret = EEH_NEXT_ERR_FENCED_PHB;
@@ -789,17 +795,21 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
                         * If we can't find the corresponding PE, the
                         * PEEV / PEST would be messy. So we force an
                         * fenced PHB so that it can be recovered.
+                         *
+                         * If the PE has been marked as isolated, that
+                         * should have been removed permanently or in
+                         * progress with recovery. We needn't report
+                         * it again.
                         */
                        if (ioda_eeh_get_pe(hose, frozen_pe_no, pe)) {
-                                if (!ioda_eeh_get_phb_pe(hose, pe)) {
+                                *pe = phb_pe;
-                                        pr_err("EEH: Escalated fenced PHB#%x "
+                                pr_err("EEH: Escalated fenced PHB#%x "
-                                               "detected for PE#%llx\n",
+                                       "detected for PE#%llx\n",
-                                                hose->global_number,
+                                        hose->global_number,
-                                                frozen_pe_no);
+                                        frozen_pe_no);
-                                        ret = EEH_NEXT_ERR_FENCED_PHB;
+                                ret = EEH_NEXT_ERR_FENCED_PHB;
-                                } else {
+                        } else if ((*pe)->state & EEH_PE_ISOLATED) {
-                                        ret = EEH_NEXT_ERR_NONE;
+                                ret = EEH_NEXT_ERR_NONE;
-                                }
                        } else {
                                pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
                                        (*pe)->addr, (*pe)->phb->global_number);
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
index a59788e83b8b..56a206f32f77 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -126,6 +126,7 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
        edev->mode      &= 0xFFFFFF00;
        if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
                edev->mode |= EEH_DEV_BRIDGE;
+        edev->pcix_cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
        if (pci_is_pcie(dev)) {
                edev->pcie_cap = pci_pcie_cap(dev);
@@ -133,6 +134,9 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
                        edev->mode |= EEH_DEV_ROOT_PORT;
                else if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)
                        edev->mode |= EEH_DEV_DS_PORT;
+                edev->aer_cap = pci_find_ext_capability(dev,
+                                                        PCI_EXT_CAP_ID_ERR);
        }
        edev->config_addr       = ((dev->bus->number << 8) | dev->devfn);
diff --git a/arch/powerpc/platforms/powernv/opal-flash.c b/arch/powerpc/platforms/powernv/opal-flash.c
index dc487ff04704..5c21d9c07f45 100644
--- a/arch/powerpc/platforms/powernv/opal-flash.c
+++ b/arch/powerpc/platforms/powernv/opal-flash.c
@@ -20,6 +20,7 @@
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
 #include <linux/pagemap.h>
+#include <linux/delay.h>
 #include <asm/opal.h>
@@ -130,7 +131,8 @@ static inline void opal_flash_validate(void)
 {
        long ret;
        void *buf = validate_flash_data.buf;
-        __be32 size, result;
+        __be32 size = cpu_to_be32(validate_flash_data.buf_size);
+        __be32 result;
        ret = opal_validate_flash(__pa(buf), &size, &result);
@@ -290,11 +292,6 @@ static int opal_flash_update(int op)
        /* First entry address */
        addr = __pa(list);
-        pr_alert("FLASH: Image is %u bytes\n", image_data.size);
-        pr_alert("FLASH: Image update requested\n");
-        pr_alert("FLASH: Image will be updated during system reboot\n");
-        pr_alert("FLASH: This will take several minutes. Do not power off!\n");
 flash:
        rc = opal_update_flash(addr);
@@ -302,6 +299,47 @@ invalid_img:
        return rc;
 }
+/* Return CPUs to OPAL before starting FW update */
+static void flash_return_cpu(void *info)
+{
+        int cpu = smp_processor_id();
+        if (!cpu_online(cpu))
+                return;
+        /* Disable IRQ */
+        hard_irq_disable();
+        /* Return the CPU to OPAL */
+        opal_return_cpu();
+}
+/* This gets called just before system reboots */
+void opal_flash_term_callback(void)
+{
+        struct cpumask mask;
+        if (update_flash_data.status != FLASH_IMG_READY)
+                return;
+        pr_alert("FLASH: Flashing new firmware\n");
+        pr_alert("FLASH: Image is %u bytes\n", image_data.size);
+        pr_alert("FLASH: Performing flash and reboot/shutdown\n");
+        pr_alert("FLASH: This will take several minutes. Do not power off!\n");
+        /* Small delay to help getting the above message out */
+        msleep(500);
+        /* Return secondary CPUs to firmware */
+        cpumask_copy(&mask, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &mask);
+        if (!cpumask_empty(&mask))
+                smp_call_function_many(&mask,
+                                       flash_return_cpu, NULL, false);
+        /* Hard disable interrupts */
+        hard_irq_disable();
+}
 /*
 * Show candidate image status
 */
diff --git a/arch/powerpc/platforms/powernv/opal-lpc.c b/arch/powerpc/platforms/powernv/opal-lpc.c
index 79d83cad3d67..f04b4d8aca5a 100644
--- a/arch/powerpc/platforms/powernv/opal-lpc.c
+++ b/arch/powerpc/platforms/powernv/opal-lpc.c
@@ -12,12 +12,17 @@
 #include <linux/kernel.h>
 #include <linux/of.h>
 #include <linux/bug.h>
+#include <linux/debugfs.h>
+#include <linux/io.h>
+#include <linux/slab.h>
 #include <asm/machdep.h>
 #include <asm/firmware.h>
 #include <asm/xics.h>
 #include <asm/opal.h>
 #include <asm/prom.h>
+#include <asm/uaccess.h>
+#include <asm/debug.h>
 static int opal_lpc_chip_id = -1;
@@ -176,6 +181,152 @@ static const struct ppc_pci_io opal_lpc_io = {
        .outsl  = opal_lpc_outsl,
 };
+#ifdef CONFIG_DEBUG_FS
+struct lpc_debugfs_entry {
+        enum OpalLPCAddressType lpc_type;
+};
+static ssize_t lpc_debug_read(struct file *filp, char __user *ubuf,
+                              size_t count, loff_t *ppos)
+{
+        struct lpc_debugfs_entry *lpc = filp->private_data;
+        u32 data, pos, len, todo;
+        int rc;
+        if (!access_ok(VERIFY_WRITE, ubuf, count))
+                return -EFAULT;
+        todo = count;
+        while (todo) {
+                pos = *ppos;
+                /*
+                 * Select access size based on count and alignment and
+                 * access type. IO and MEM only support byte acceses,
+                 * FW supports all 3.
+                 */
+                len = 1;
+                if (lpc->lpc_type == OPAL_LPC_FW) {
+                        if (todo > 3 && (pos & 3) == 0)
+                                len = 4;
+                        else if (todo > 1 && (pos & 1) == 0)
+                                len = 2;
+                }
+                rc = opal_lpc_read(opal_lpc_chip_id, lpc->lpc_type, pos,
+                                   &data, len);
+                if (rc)
+                        return -ENXIO;
+                switch(len) {
+                case 4:
+                        rc = __put_user((u32)data, (u32 __user *)ubuf);
+                        break;
+                case 2:
+                        rc = __put_user((u16)data, (u16 __user *)ubuf);
+                        break;
+                default:
+                        rc = __put_user((u8)data, (u8 __user *)ubuf);
+                        break;
+                }
+                if (rc)
+                        return -EFAULT;
+                *ppos += len;
+                ubuf += len;
+                todo -= len;
+        }
+        return count;
+}
+static ssize_t lpc_debug_write(struct file *filp, const char __user *ubuf,
+                               size_t count, loff_t *ppos)
+{
+        struct lpc_debugfs_entry *lpc = filp->private_data;
+        u32 data, pos, len, todo;
+        int rc;
+        if (!access_ok(VERIFY_READ, ubuf, count))
+                return -EFAULT;
+        todo = count;
+        while (todo) {
+                pos = *ppos;
+                /*
+                 * Select access size based on count and alignment and
+                 * access type. IO and MEM only support byte acceses,
+                 * FW supports all 3.
+                 */
+                len = 1;
+                if (lpc->lpc_type == OPAL_LPC_FW) {
+                        if (todo > 3 && (pos & 3) == 0)
+                                len = 4;
+                        else if (todo > 1 && (pos & 1) == 0)
+                                len = 2;
+                }
+                switch(len) {
+                case 4:
+                        rc = __get_user(data, (u32 __user *)ubuf);
+                        break;
+                case 2:
+                        rc = __get_user(data, (u16 __user *)ubuf);
+                        break;
+                default:
+                        rc = __get_user(data, (u8 __user *)ubuf);
+                        break;
+                }
+                if (rc)
+                        return -EFAULT;
+                rc = opal_lpc_write(opal_lpc_chip_id, lpc->lpc_type, pos,
+                                    data, len);
+                if (rc)
+                        return -ENXIO;
+                *ppos += len;
+                ubuf += len;
+                todo -= len;
+        }
+        return count;
+}
+static const struct file_operations lpc_fops = {
+        .read =         lpc_debug_read,
+        .write =        lpc_debug_write,
+        .open =         simple_open,
+        .llseek =       default_llseek,
+};
+static int opal_lpc_debugfs_create_type(struct dentry *folder,
+                                        const char *fname,
+                                        enum OpalLPCAddressType type)
+{
+        struct lpc_debugfs_entry *entry;
+        entry = kzalloc(sizeof(*entry), GFP_KERNEL);
+        if (!entry)
+                return -ENOMEM;
+        entry->lpc_type = type;
+        debugfs_create_file(fname, 0600, folder, entry, &lpc_fops);
+        return 0;
+}
+static int opal_lpc_init_debugfs(void)
+{
+        struct dentry *root;
+        int rc = 0;
+        if (opal_lpc_chip_id < 0)
+                return -ENODEV;
+        root = debugfs_create_dir("lpc", powerpc_debugfs_root);
+        rc |= opal_lpc_debugfs_create_type(root, "io", OPAL_LPC_IO);
+        rc |= opal_lpc_debugfs_create_type(root, "mem", OPAL_LPC_MEM);
+        rc |= opal_lpc_debugfs_create_type(root, "fw", OPAL_LPC_FW);
+        return rc;
+}
+device_initcall(opal_lpc_init_debugfs);
+#endif  /* CONFIG_DEBUG_FS */
 void opal_lpc_init(void)
 {
        struct device_node *np;
diff --git a/arch/powerpc/platforms/powernv/opal-memory-errors.c b/arch/powerpc/platforms/powernv/opal-memory-errors.c
index ec4132239cdf..b17a34b695ef 100644
--- a/arch/powerpc/platforms/powernv/opal-memory-errors.c
+++ b/arch/powerpc/platforms/powernv/opal-memory-errors.c
@@ -47,12 +47,12 @@ static void handle_memory_error_event(struct OpalMemoryErrorData *merr_evt)
                  __func__, merr_evt->type);
        switch (merr_evt->type) {
        case OPAL_MEM_ERR_TYPE_RESILIENCE:
-                paddr_start = merr_evt->u.resilience.physical_address_start;
+                paddr_start = be64_to_cpu(merr_evt->u.resilience.physical_address_start);
-                paddr_end = merr_evt->u.resilience.physical_address_end;
+                paddr_end = be64_to_cpu(merr_evt->u.resilience.physical_address_end);
                break;
        case OPAL_MEM_ERR_TYPE_DYN_DALLOC:
-                paddr_start = merr_evt->u.dyn_dealloc.physical_address_start;
+                paddr_start = be64_to_cpu(merr_evt->u.dyn_dealloc.physical_address_start);
-                paddr_end = merr_evt->u.dyn_dealloc.physical_address_end;
+                paddr_end = be64_to_cpu(merr_evt->u.dyn_dealloc.physical_address_end);
                break;
        default:
                return;
diff --git a/arch/powerpc/platforms/powernv/opal-takeover.S b/arch/powerpc/platforms/powernv/opal-takeover.S
index 3cd262897c27..11a3169ee583 100644
--- a/arch/powerpc/platforms/powernv/opal-takeover.S
+++ b/arch/powerpc/platforms/powernv/opal-takeover.S
@@ -21,11 +21,13 @@
 _GLOBAL(opal_query_takeover)
        mfcr    r0
        stw     r0,8(r1)
+        stdu    r1,-STACKFRAMESIZE(r1)
        std     r3,STK_PARAM(R3)(r1)
        std     r4,STK_PARAM(R4)(r1)
        li      r3,H_HAL_TAKEOVER
        li      r4,H_HAL_TAKEOVER_QUERY_MAGIC
        HVSC
+        addi    r1,r1,STACKFRAMESIZE
        ld      r10,STK_PARAM(R3)(r1)
        std     r4,0(r10)
        ld      r10,STK_PARAM(R4)(r1)
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index f531ffe35b3e..4abbff22a61f 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -32,7 +32,7 @@
        std     r12,PACASAVEDMSR(r13);  \
        andc    r12,r12,r0;             \
        mtmsrd  r12,1;                  \
-        LOAD_REG_ADDR(r0,.opal_return); \
+        LOAD_REG_ADDR(r0,opal_return);  \
        mtlr    r0;                     \
        li      r0,MSR_DR|MSR_IR|MSR_LE;\
        andc    r12,r12,r0;             \
@@ -44,7 +44,7 @@
        mtspr   SPRN_HSRR0,r12;         \
        hrfid
-_STATIC(opal_return)
+opal_return:
        /*
         * Fixup endian on OPAL return... we should be able to simplify
         * this by instead converting the below trampoline to a set of
@@ -124,6 +124,7 @@ OPAL_CALL(opal_xscom_write,			OPAL_XSCOM_WRITE);
 OPAL_CALL(opal_lpc_read,                        OPAL_LPC_READ);
 OPAL_CALL(opal_lpc_write,                       OPAL_LPC_WRITE);
 OPAL_CALL(opal_return_cpu,                      OPAL_RETURN_CPU);
+OPAL_CALL(opal_reinit_cpus,                     OPAL_REINIT_CPUS);
 OPAL_CALL(opal_read_elog,                       OPAL_ELOG_READ);
 OPAL_CALL(opal_send_ack_elog,                   OPAL_ELOG_ACK);
 OPAL_CALL(opal_get_elog_size,                   OPAL_ELOG_SIZE);
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index f343183add07..199975613fe9 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -57,6 +57,21 @@ static DEFINE_SPINLOCK(opal_notifier_lock);
 static uint64_t last_notified_mask = 0x0ul;
 static atomic_t opal_notifier_hold = ATOMIC_INIT(0);
+static void opal_reinit_cores(void)
+{
+        /* Do the actual re-init, This will clobber all FPRs, VRs, etc...
+         *
+         * It will preserve non volatile GPRs and HSPRG0/1. It will
+         * also restore HIDs and other SPRs to their original value
+         * but it might clobber a bunch.
+         */
+#ifdef __BIG_ENDIAN__
+        opal_reinit_cpus(OPAL_REINIT_CPUS_HILE_BE);
+#else
+        opal_reinit_cpus(OPAL_REINIT_CPUS_HILE_LE);
+#endif
+}
 int __init early_init_dt_scan_opal(unsigned long node,
                                   const char *uname, int depth, void *data)
 {
@@ -96,6 +111,13 @@ int __init early_init_dt_scan_opal(unsigned long node,
                printk("OPAL V1 detected !\n");
        }
+        /* Reinit all cores with the right endian */
+        opal_reinit_cores();
+        /* Restore some bits */
+        if (cur_cpu_spec->cpu_restore)
+                cur_cpu_spec->cpu_restore();
        return 1;
 }
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 98824aa99173..de19edeaa7a7 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/crash_dump.h>
 #include <linux/debugfs.h>
 #include <linux/delay.h>
 #include <linux/string.h>
@@ -663,15 +664,15 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
                 * errors, and on the first pass the data will be a relative
                 * bus number, print that out instead.
                 */
-                tbl->it_busno = 0;
                pe->tce_inval_reg_phys = be64_to_cpup(swinvp);
                tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys,
                                8);
-                tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE |
+                tbl->it_type |= (TCE_PCI_SWINV_CREATE |
-                               TCE_PCI_SWINV_PAIR;
+                                 TCE_PCI_SWINV_FREE   |
+                                 TCE_PCI_SWINV_PAIR);
        }
        iommu_init_table(tbl, phb->hose->node);
-        iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number);
+        iommu_register_group(tbl, phb->hose->global_number, pe->pe_number);
        if (pe->pdev)
                set_iommu_table_base_and_group(&pe->pdev->dev, tbl);
@@ -793,14 +794,13 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
                 * errors, and on the first pass the data will be a relative
                 * bus number, print that out instead.
                 */
-                tbl->it_busno = 0;
                pe->tce_inval_reg_phys = be64_to_cpup(swinvp);
                tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys,
                                8);
-                tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
+                tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
        }
        iommu_init_table(tbl, phb->hose->node);
-        iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number);
+        iommu_register_group(tbl, phb->hose->global_number, pe->pe_number);
        if (pe->pdev)
                set_iommu_table_base_and_group(&pe->pdev->dev, tbl);
@@ -1386,12 +1386,24 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np,
        ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
        ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
        ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
+        ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus;
        pci_add_flags(PCI_REASSIGN_ALL_RSRC);
        /* Reset IODA tables to a clean state */
        rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
        if (rc)
                pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
+        /* If we're running in kdump kerenl, the previous kerenl never
+         * shutdown PCI devices correctly. We already got IODA table
+         * cleaned out. So we have to issue PHB reset to stop all PCI
+         * transactions from previous kerenl.
+         */
+        if (is_kdump_kernel()) {
+                pr_info("  Issue PHB reset ...\n");
+                ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
+                ioda_eeh_phb_reset(hose, OPAL_DEASSERT_RESET);
+        }
 }
 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 8518817dcdfd..eefbfcc3fd8c 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -131,65 +131,60 @@ static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose,
        int i;
        data = (struct OpalIoP7IOCPhbErrorData *)common;
-        pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n\n",
+        pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n",
                hose->global_number, common->version);
        if (data->brdgCtl)
-                pr_info("  brdgCtl:     %08x\n",
+                pr_info("brdgCtl:     %08x\n",
                        data->brdgCtl);
        if (data->portStatusReg || data->rootCmplxStatus ||
            data->busAgentStatus)
-                pr_info("  UtlSts:      %08x %08x %08x\n",
+                pr_info("UtlSts:      %08x %08x %08x\n",
                        data->portStatusReg, data->rootCmplxStatus,
                        data->busAgentStatus);
        if (data->deviceStatus || data->slotStatus   ||
            data->linkStatus   || data->devCmdStatus ||
            data->devSecStatus)
-                pr_info("  RootSts:     %08x %08x %08x %08x %08x\n",
+                pr_info("RootSts:     %08x %08x %08x %08x %08x\n",
                        data->deviceStatus, data->slotStatus,
                        data->linkStatus, data->devCmdStatus,
                        data->devSecStatus);
        if (data->rootErrorStatus   || data->uncorrErrorStatus ||
            data->corrErrorStatus)
-                pr_info("  RootErrSts:  %08x %08x %08x\n",
+                pr_info("RootErrSts:  %08x %08x %08x\n",
                        data->rootErrorStatus, data->uncorrErrorStatus,
                        data->corrErrorStatus);
        if (data->tlpHdr1 || data->tlpHdr2 ||
            data->tlpHdr3 || data->tlpHdr4)
-                pr_info("  RootErrLog:  %08x %08x %08x %08x\n",
+                pr_info("RootErrLog:  %08x %08x %08x %08x\n",
                        data->tlpHdr1, data->tlpHdr2,
                        data->tlpHdr3, data->tlpHdr4);
        if (data->sourceId || data->errorClass ||
            data->correlator)
-                pr_info("  RootErrLog1: %08x %016llx %016llx\n",
+                pr_info("RootErrLog1: %08x %016llx %016llx\n",
                        data->sourceId, data->errorClass,
                        data->correlator);
        if (data->p7iocPlssr || data->p7iocCsr)
-                pr_info("  PhbSts:      %016llx %016llx\n",
+                pr_info("PhbSts:      %016llx %016llx\n",
                        data->p7iocPlssr, data->p7iocCsr);
-        if (data->lemFir || data->lemErrorMask ||
+        if (data->lemFir)
-            data->lemWOF)
+                pr_info("Lem:         %016llx %016llx %016llx\n",
-                pr_info("  Lem:         %016llx %016llx %016llx\n",
                        data->lemFir, data->lemErrorMask,
                        data->lemWOF);
-        if (data->phbErrorStatus || data->phbFirstErrorStatus ||
+        if (data->phbErrorStatus)
-            data->phbErrorLog0   || data->phbErrorLog1)
+                pr_info("PhbErr:      %016llx %016llx %016llx %016llx\n",
-                pr_info("  PhbErr:      %016llx %016llx %016llx %016llx\n",
                        data->phbErrorStatus, data->phbFirstErrorStatus,
                        data->phbErrorLog0, data->phbErrorLog1);
-        if (data->mmioErrorStatus || data->mmioFirstErrorStatus ||
+        if (data->mmioErrorStatus)
-            data->mmioErrorLog0   || data->mmioErrorLog1)
+                pr_info("OutErr:      %016llx %016llx %016llx %016llx\n",
-                pr_info("  OutErr:      %016llx %016llx %016llx %016llx\n",
                        data->mmioErrorStatus, data->mmioFirstErrorStatus,
                        data->mmioErrorLog0, data->mmioErrorLog1);
-        if (data->dma0ErrorStatus || data->dma0FirstErrorStatus ||
+        if (data->dma0ErrorStatus)
-            data->dma0ErrorLog0   || data->dma0ErrorLog1)
+                pr_info("InAErr:      %016llx %016llx %016llx %016llx\n",
-                pr_info("  InAErr:      %016llx %016llx %016llx %016llx\n",
                        data->dma0ErrorStatus, data->dma0FirstErrorStatus,
                        data->dma0ErrorLog0, data->dma0ErrorLog1);
-        if (data->dma1ErrorStatus || data->dma1FirstErrorStatus ||
+        if (data->dma1ErrorStatus)
-            data->dma1ErrorLog0   || data->dma1ErrorLog1)
+                pr_info("InBErr:      %016llx %016llx %016llx %016llx\n",
-                pr_info("  InBErr:      %016llx %016llx %016llx %016llx\n",
                        data->dma1ErrorStatus, data->dma1FirstErrorStatus,
                        data->dma1ErrorLog0, data->dma1ErrorLog1);
@@ -198,7 +193,7 @@ static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose,
                    (data->pestB[i] >> 63) == 0)
                        continue;
-                pr_info("  PE[%3d] A/B: %016llx %016llx\n",
+                pr_info("PE[%3d] A/B: %016llx %016llx\n",
                        i, data->pestA[i], data->pestB[i]);
        }
 }
@@ -210,69 +205,63 @@ static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose,
        int i;
        data = (struct OpalIoPhb3ErrorData*)common;
-        pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n\n",
+        pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n",
                hose->global_number, common->version);
        if (data->brdgCtl)
-                pr_info("  brdgCtl:     %08x\n",
+                pr_info("brdgCtl:     %08x\n",
                        data->brdgCtl);
        if (data->portStatusReg || data->rootCmplxStatus ||
            data->busAgentStatus)
-                pr_info("  UtlSts:      %08x %08x %08x\n",
+                pr_info("UtlSts:      %08x %08x %08x\n",
                        data->portStatusReg, data->rootCmplxStatus,
                        data->busAgentStatus);
        if (data->deviceStatus || data->slotStatus   ||
            data->linkStatus   || data->devCmdStatus ||
            data->devSecStatus)
-                pr_info("  RootSts:     %08x %08x %08x %08x %08x\n",
+                pr_info("RootSts:     %08x %08x %08x %08x %08x\n",
                        data->deviceStatus, data->slotStatus,
                        data->linkStatus, data->devCmdStatus,
                        data->devSecStatus);
        if (data->rootErrorStatus || data->uncorrErrorStatus ||
            data->corrErrorStatus)
-                pr_info("  RootErrSts:  %08x %08x %08x\n",
+                pr_info("RootErrSts:  %08x %08x %08x\n",
                        data->rootErrorStatus, data->uncorrErrorStatus,
                        data->corrErrorStatus);
        if (data->tlpHdr1 || data->tlpHdr2 ||
            data->tlpHdr3 || data->tlpHdr4)
-                pr_info("  RootErrLog:  %08x %08x %08x %08x\n",
+                pr_info("RootErrLog:  %08x %08x %08x %08x\n",
                        data->tlpHdr1, data->tlpHdr2,
                        data->tlpHdr3, data->tlpHdr4);
        if (data->sourceId || data->errorClass ||
            data->correlator)
-                pr_info("  RootErrLog1: %08x %016llx %016llx\n",
+                pr_info("RootErrLog1: %08x %016llx %016llx\n",
                        data->sourceId, data->errorClass,
                        data->correlator);
-        if (data->nFir || data->nFirMask ||
+        if (data->nFir)
-            data->nFirWOF)
+                pr_info("nFir:        %016llx %016llx %016llx\n",
-                pr_info("  nFir:        %016llx %016llx %016llx\n",
                        data->nFir, data->nFirMask,
                        data->nFirWOF);
        if (data->phbPlssr || data->phbCsr)
-                pr_info("  PhbSts:      %016llx %016llx\n",
+                pr_info("PhbSts:      %016llx %016llx\n",
                        data->phbPlssr, data->phbCsr);
-        if (data->lemFir || data->lemErrorMask ||
+        if (data->lemFir)
-            data->lemWOF)
+                pr_info("Lem:         %016llx %016llx %016llx\n",
-                pr_info("  Lem:         %016llx %016llx %016llx\n",
                        data->lemFir, data->lemErrorMask,
                        data->lemWOF);
-        if (data->phbErrorStatus || data->phbFirstErrorStatus ||
+        if (data->phbErrorStatus)
-            data->phbErrorLog0   || data->phbErrorLog1)
+                pr_info("PhbErr:      %016llx %016llx %016llx %016llx\n",
-                pr_info("  PhbErr:      %016llx %016llx %016llx %016llx\n",
                        data->phbErrorStatus, data->phbFirstErrorStatus,
                        data->phbErrorLog0, data->phbErrorLog1);
-        if (data->mmioErrorStatus || data->mmioFirstErrorStatus ||
+        if (data->mmioErrorStatus)
-            data->mmioErrorLog0   || data->mmioErrorLog1)
+                pr_info("OutErr:      %016llx %016llx %016llx %016llx\n",
-                pr_info("  OutErr:      %016llx %016llx %016llx %016llx\n",
                        data->mmioErrorStatus, data->mmioFirstErrorStatus,
                        data->mmioErrorLog0, data->mmioErrorLog1);
-        if (data->dma0ErrorStatus || data->dma0FirstErrorStatus ||
+        if (data->dma0ErrorStatus)
-            data->dma0ErrorLog0   || data->dma0ErrorLog1)
+                pr_info("InAErr:      %016llx %016llx %016llx %016llx\n",
-                pr_info("  InAErr:      %016llx %016llx %016llx %016llx\n",
                        data->dma0ErrorStatus, data->dma0FirstErrorStatus,
                        data->dma0ErrorLog0, data->dma0ErrorLog1);
-        if (data->dma1ErrorStatus || data->dma1FirstErrorStatus ||
+        if (data->dma1ErrorStatus)
-            data->dma1ErrorLog0   || data->dma1ErrorLog1)
+                pr_info("InBErr:      %016llx %016llx %016llx %016llx\n",
-                pr_info("  InBErr:      %016llx %016llx %016llx %016llx\n",
                        data->dma1ErrorStatus, data->dma1FirstErrorStatus,
                        data->dma1ErrorLog0, data->dma1ErrorLog1);
@@ -281,7 +270,7 @@ static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose,
                    (data->pestB[i] >> 63) == 0)
                        continue;
-                pr_info("  PE[%3d] A/B: %016llx %016llx\n",
+                pr_info("PE[%3d] A/B: %016llx %016llx\n",
                        i, data->pestA[i], data->pestB[i]);
        }
 }
@@ -384,9 +373,6 @@ int pnv_pci_cfg_read(struct device_node *dn,
        struct pci_dn *pdn = PCI_DN(dn);
        struct pnv_phb *phb = pdn->phb->private_data;
        u32 bdfn = (pdn->busno << 8) | pdn->devfn;
-#ifdef CONFIG_EEH
-        struct eeh_pe *phb_pe = NULL;
-#endif
        s64 rc;
        switch (size) {
@@ -412,31 +398,9 @@ int pnv_pci_cfg_read(struct device_node *dn,
        default:
                return PCIBIOS_FUNC_NOT_SUPPORTED;
        }
        cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
                __func__, pdn->busno, pdn->devfn, where, size, *val);
-        /*
-         * Check if the specified PE has been put into frozen
-         * state. On the other hand, we needn't do that while
-         * the PHB has been put into frozen state because of
-         * PHB-fatal errors.
-         */
-#ifdef CONFIG_EEH
-        phb_pe = eeh_phb_pe_get(pdn->phb);
-        if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED))
-                return PCIBIOS_SUCCESSFUL;
-        if (phb->eeh_state & PNV_EEH_STATE_ENABLED) {
-                if (*val == EEH_IO_ERROR_VALUE(size) &&
-                    eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
-                        return PCIBIOS_DEVICE_NOT_FOUND;
-        } else {
-                pnv_pci_config_check_eeh(phb, dn);
-        }
-#else
-        pnv_pci_config_check_eeh(phb, dn);
-#endif
        return PCIBIOS_SUCCESSFUL;
 }
@@ -463,33 +427,74 @@ int pnv_pci_cfg_write(struct device_node *dn,
                return PCIBIOS_FUNC_NOT_SUPPORTED;
        }
-        /* Check if the PHB got frozen due to an error (no response) */
-#ifdef CONFIG_EEH
-        if (!(phb->eeh_state & PNV_EEH_STATE_ENABLED))
-                pnv_pci_config_check_eeh(phb, dn);
-#else
-        pnv_pci_config_check_eeh(phb, dn);
-#endif
        return PCIBIOS_SUCCESSFUL;
 }
+#if CONFIG_EEH
+static bool pnv_pci_cfg_check(struct pci_controller *hose,
+                              struct device_node *dn)
+{
+        struct eeh_dev *edev = NULL;
+        struct pnv_phb *phb = hose->private_data;
+        /* EEH not enabled ? */
+        if (!(phb->flags & PNV_PHB_FLAG_EEH))
+                return true;
+        /* PE reset or device removed ? */
+        edev = of_node_to_eeh_dev(dn);
+        if (edev) {
+                if (edev->pe &&
+                    (edev->pe->state & EEH_PE_RESET))
+                        return false;
+                if (edev->mode & EEH_DEV_REMOVED)
+                        return false;
+        }
+        return true;
+}
+#else
+static inline pnv_pci_cfg_check(struct pci_controller *hose,
+                                struct device_node *dn)
+{
+        return true;
+}
+#endif /* CONFIG_EEH */
 static int pnv_pci_read_config(struct pci_bus *bus,
                               unsigned int devfn,
                               int where, int size, u32 *val)
 {
        struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
        struct pci_dn *pdn;
+        struct pnv_phb *phb;
+        bool found = false;
+        int ret;
+        *val = 0xFFFFFFFF;
        for (dn = busdn->child; dn; dn = dn->sibling) {
                pdn = PCI_DN(dn);
-                if (pdn && pdn->devfn == devfn)
+                if (pdn && pdn->devfn == devfn) {
-                        return pnv_pci_cfg_read(dn, where, size, val);
+                        phb = pdn->phb->private_data;
+                        found = true;
+                        break;
+                }
        }
-        *val = 0xFFFFFFFF;
+        if (!found || !pnv_pci_cfg_check(pdn->phb, dn))
-        return PCIBIOS_DEVICE_NOT_FOUND;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        ret = pnv_pci_cfg_read(dn, where, size, val);
+        if (phb->flags & PNV_PHB_FLAG_EEH) {
+                if (*val == EEH_IO_ERROR_VALUE(size) &&
+                    eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+        } else {
+                pnv_pci_config_check_eeh(phb, dn);
+        }
+        return ret;
 }
 static int pnv_pci_write_config(struct pci_bus *bus,
@@ -498,14 +503,27 @@ static int pnv_pci_write_config(struct pci_bus *bus,
 {
        struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
        struct pci_dn *pdn;
+        struct pnv_phb *phb;
+        bool found = false;
+        int ret;
        for (dn = busdn->child; dn; dn = dn->sibling) {
                pdn = PCI_DN(dn);
-                if (pdn && pdn->devfn == devfn)
+                if (pdn && pdn->devfn == devfn) {
-                        return pnv_pci_cfg_write(dn, where, size, val);
+                        phb = pdn->phb->private_data;
+                        found = true;
+                        break;
+                }
        }
-        return PCIBIOS_DEVICE_NOT_FOUND;
+        if (!found || !pnv_pci_cfg_check(pdn->phb, dn))
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        ret = pnv_pci_cfg_write(dn, where, size, val);
+        if (!(phb->flags & PNV_PHB_FLAG_EEH))
+                pnv_pci_config_check_eeh(phb, dn);
+        return ret;
 }
 struct pci_ops pnv_pci_ops = {
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index cde169442775..676232c34328 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -81,28 +81,27 @@ struct pnv_eeh_ops {
        int (*configure_bridge)(struct eeh_pe *pe);
        int (*next_error)(struct eeh_pe **pe);
 };
-#define PNV_EEH_STATE_ENABLED   (1 << 0)        /* EEH enabled  */
-#define PNV_EEH_STATE_REMOVED   (1 << 1)        /* PHB removed  */
 #endif /* CONFIG_EEH */
+#define PNV_PHB_FLAG_EEH        (1 << 0)
 struct pnv_phb {
        struct pci_controller   *hose;
        enum pnv_phb_type       type;
        enum pnv_phb_model      model;
        u64                     hub_id;
        u64                     opal_id;
+        int                     flags;
        void __iomem            *regs;
        int                     initialized;
        spinlock_t              lock;
 #ifdef CONFIG_EEH
        struct pnv_eeh_ops      *eeh_ops;
-        int                     eeh_state;
 #endif
 #ifdef CONFIG_DEBUG_FS
+        int                     has_dbgfs;
        struct dentry           *dbgfs;
 #endif
@@ -205,5 +204,7 @@ extern void pnv_pci_init_ioda_hub(struct device_node *np);
 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
                                        __be64 *startp, __be64 *endp, bool rm);
+extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
+extern int ioda_eeh_phb_reset(struct pci_controller *hose, int option);
 #endif /* __POWERNV_PCI_H */
diff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h
index 0051e108ef0f..75501bfede7f 100644
--- a/arch/powerpc/platforms/powernv/powernv.h
+++ b/arch/powerpc/platforms/powernv/powernv.h
@@ -25,4 +25,6 @@ static inline int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
 extern void pnv_lpc_init(void);
+bool cpu_core_split_required(void);
 #endif /* _POWERNV_H */
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 8723d32632f5..8c16a5f96728 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -27,6 +27,7 @@
 #include <linux/interrupt.h>
 #include <linux/bug.h>
 #include <linux/pci.h>
+#include <linux/cpufreq.h>
 #include <asm/machdep.h>
 #include <asm/firmware.h>
@@ -98,11 +99,32 @@ static void pnv_show_cpuinfo(struct seq_file *m)
        of_node_put(root);
 }
+static void pnv_prepare_going_down(void)
+{
+        /*
+         * Disable all notifiers from OPAL, we can't
+         * service interrupts anymore anyway
+         */
+        opal_notifier_disable();
+        /* Soft disable interrupts */
+        local_irq_disable();
+        /*
+         * Return secondary CPUs to firwmare if a flash update
+         * is pending otherwise we will get all sort of error
+         * messages about CPU being stuck etc.. This will also
+         * have the side effect of hard disabling interrupts so
+         * past this point, the kernel is effectively dead.
+         */
+        opal_flash_term_callback();
+}
 static void  __noreturn pnv_restart(char *cmd)
 {
        long rc = OPAL_BUSY;
-        opal_notifier_disable();
+        pnv_prepare_going_down();
        while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
                rc = opal_cec_reboot();
@@ -119,7 +141,7 @@ static void __noreturn pnv_power_off(void)
 {
        long rc = OPAL_BUSY;
-        opal_notifier_disable();
+        pnv_prepare_going_down();
        while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
                rc = opal_cec_power_down(0);
@@ -222,6 +244,13 @@ static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
 }
 #endif /* CONFIG_KEXEC */
+#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
+static unsigned long pnv_memory_block_size(void)
+{
+        return 256UL * 1024 * 1024;
+}
+#endif
 static void __init pnv_setup_machdep_opal(void)
 {
        ppc_md.get_boot_time = opal_get_boot_time;
@@ -269,6 +298,25 @@ static int __init pnv_probe(void)
        return 1;
 }
+/*
+ * Returns the cpu frequency for 'cpu' in Hz. This is used by
+ * /proc/cpuinfo
+ */
+unsigned long pnv_get_proc_freq(unsigned int cpu)
+{
+        unsigned long ret_freq;
+        ret_freq = cpufreq_quick_get(cpu) * 1000ul;
+        /*
+         * If the backend cpufreq driver does not exist,
+         * then fallback to old way of reporting the clockrate.
+         */
+        if (!ret_freq)
+                ret_freq = ppc_proc_freq;
+        return ret_freq;
+}
 define_machine(powernv) {
        .name                   = "PowerNV",
        .probe                  = pnv_probe,
@@ -276,6 +324,7 @@ define_machine(powernv) {
        .setup_arch             = pnv_setup_arch,
        .init_IRQ               = pnv_init_IRQ,
        .show_cpuinfo           = pnv_show_cpuinfo,
+        .get_proc_freq          = pnv_get_proc_freq,
        .progress               = pnv_progress,
        .machine_shutdown       = pnv_shutdown,
        .power_save             = power7_idle,
@@ -284,4 +333,7 @@ define_machine(powernv) {
 #ifdef CONFIG_KEXEC
        .kexec_cpu_down         = pnv_kexec_cpu_down,
 #endif
+#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
+        .memory_block_size      = pnv_memory_block_size,
+#endif
 };
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
index bf5fcd452168..0062a43a2e0d 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -31,6 +31,7 @@
 #include <asm/xics.h>
 #include <asm/opal.h>
 #include <asm/runlatch.h>
+#include <asm/code-patching.h>
 #include "powernv.h"
@@ -50,8 +51,8 @@ static void pnv_smp_setup_cpu(int cpu)
 int pnv_smp_kick_cpu(int nr)
 {
        unsigned int pcpu = get_hard_smp_processor_id(nr);
-        unsigned long start_here = __pa(*((unsigned long *)
+        unsigned long start_here =
-                                          generic_secondary_smp_init));
+                        __pa(ppc_function_entry(generic_secondary_smp_init));
        long rc;
        BUG_ON(nr < 0 || nr >= NR_CPUS);
@@ -158,17 +159,19 @@ static void pnv_smp_cpu_kill_self(void)
        mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1);
        while (!generic_check_cpu_restart(cpu)) {
                ppc64_runlatch_off();
-                power7_nap();
+                power7_nap(1);
                ppc64_runlatch_on();
-                if (!generic_check_cpu_restart(cpu)) {
+                /* Reenable IRQs briefly to clear the IPI that woke us */
+                local_irq_enable();
+                local_irq_disable();
+                mb();
+                if (cpu_core_split_required())
+                        continue;
+                if (!generic_check_cpu_restart(cpu))
                        DBG("CPU%d Unexpected exit while offline !\n", cpu);
-                        /* We may be getting an IPI, so we re-enable
-                         * interrupts to process it, it will be ignored
-                         * since we aren't online (hopefully)
-                         */
-                        local_irq_enable();
-                        local_irq_disable();
-                }
        }
        mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_PECE1);
        DBG("CPU%d coming online...\n", cpu);
diff --git a/arch/powerpc/platforms/powernv/subcore-asm.S b/arch/powerpc/platforms/powernv/subcore-asm.S
new file mode 100644
index 000000000000..39bb24aa8f34
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/subcore-asm.S
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2013, Michael (Ellerman|Neuling), IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <asm/asm-offsets.h>
+#include <asm/ppc_asm.h>
+#include <asm/reg.h>
+#include "subcore.h"
+_GLOBAL(split_core_secondary_loop)
+        /*
+         * r3 = u8 *state, used throughout the routine
+         * r4 = temp
+         * r5 = temp
+         * ..
+         * r12 = MSR
+         */
+        mfmsr   r12
+        /* Disable interrupts so SRR0/1 don't get trashed */
+        li      r4,0
+        ori     r4,r4,MSR_EE|MSR_SE|MSR_BE|MSR_RI
+        andc    r4,r12,r4
+        sync
+        mtmsrd  r4
+        /* Switch to real mode and leave interrupts off */
+        li      r5, MSR_IR|MSR_DR
+        andc    r5, r4, r5
+        LOAD_REG_ADDR(r4, real_mode)
+        mtspr   SPRN_SRR0,r4
+        mtspr   SPRN_SRR1,r5
+        rfid
+        b       .       /* prevent speculative execution */
+real_mode:
+        /* Grab values from unsplit SPRs */
+        mfspr   r6,  SPRN_LDBAR
+        mfspr   r7,  SPRN_PMMAR
+        mfspr   r8,  SPRN_PMCR
+        mfspr   r9,  SPRN_RPR
+        mfspr   r10, SPRN_SDR1
+        /* Order reading the SPRs vs telling the primary we are ready to split */
+        sync
+        /* Tell thread 0 we are in real mode */
+        li      r4, SYNC_STEP_REAL_MODE
+        stb     r4, 0(r3)
+        li      r5, (HID0_POWER8_4LPARMODE | HID0_POWER8_2LPARMODE)@highest
+        sldi    r5, r5, 48
+        /* Loop until we see the split happen in HID0 */
+1:      mfspr   r4, SPRN_HID0
+        and.    r4, r4, r5
+        beq     1b
+        /*
+         * We only need to initialise the below regs once for each subcore,
+         * but it's simpler and harmless to do it on each thread.
+         */
+        /* Make sure various SPRS have sane values */
+        li      r4, 0
+        mtspr   SPRN_LPID, r4
+        mtspr   SPRN_PCR, r4
+        mtspr   SPRN_HDEC, r4
+        /* Restore SPR values now we are split */
+        mtspr   SPRN_LDBAR, r6
+        mtspr   SPRN_PMMAR, r7
+        mtspr   SPRN_PMCR, r8
+        mtspr   SPRN_RPR, r9
+        mtspr   SPRN_SDR1, r10
+        LOAD_REG_ADDR(r5, virtual_mode)
+        /* Get out of real mode */
+        mtspr   SPRN_SRR0,r5
+        mtspr   SPRN_SRR1,r12
+        rfid
+        b       .       /* prevent speculative execution */
+virtual_mode:
+        blr
diff --git a/arch/powerpc/platforms/powernv/subcore.c b/arch/powerpc/platforms/powernv/subcore.c
new file mode 100644
index 000000000000..894ecb3eb596
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/subcore.c
@@ -0,0 +1,392 @@
+/*
+ * Copyright 2013, Michael (Ellerman|Neuling), IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#define pr_fmt(fmt)     "powernv: " fmt
+#include <linux/kernel.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/device.h>
+#include <linux/gfp.h>
+#include <linux/smp.h>
+#include <linux/stop_machine.h>
+#include <asm/cputhreads.h>
+#include <asm/kvm_ppc.h>
+#include <asm/machdep.h>
+#include <asm/opal.h>
+#include <asm/smp.h>
+#include "subcore.h"
+/*
+ * Split/unsplit procedure:
+ *
+ * A core can be in one of three states, unsplit, 2-way split, and 4-way split.
+ *
+ * The mapping to subcores_per_core is simple:
+ *
+ *  State       | subcores_per_core
+ *  ------------|------------------
+ *  Unsplit     |        1
+ *  2-way split |        2
+ *  4-way split |        4
+ *
+ * The core is split along thread boundaries, the mapping between subcores and
+ * threads is as follows:
+ *
+ *  Unsplit:
+ *          ----------------------------
+ *  Subcore |            0             |
+ *          ----------------------------
+ *  Thread  |  0  1  2  3  4  5  6  7  |
+ *          ----------------------------
+ *
+ *  2-way split:
+ *          -------------------------------------
+ *  Subcore |        0        |        1        |
+ *          -------------------------------------
+ *  Thread  |  0   1   2   3  |  4   5   6   7  |
+ *          -------------------------------------
+ *
+ *  4-way split:
+ *          -----------------------------------------
+ *  Subcore |    0    |    1    |    2    |    3    |
+ *          -----------------------------------------
+ *  Thread  |  0   1  |  2   3  |  4   5  |  6   7  |
+ *          -----------------------------------------
+ *
+ *
+ * Transitions
+ * -----------
+ *
+ * It is not possible to transition between either of the split states, the
+ * core must first be unsplit. The legal transitions are:
+ *
+ *  -----------          ---------------
+ *  |         |  <---->  | 2-way split |
+ *  |         |          ---------------
+ *  | Unsplit |
+ *  |         |          ---------------
+ *  |         |  <---->  | 4-way split |
+ *  -----------          ---------------
+ *
+ * Unsplitting
+ * -----------
+ *
+ * Unsplitting is the simpler procedure. It requires thread 0 to request the
+ * unsplit while all other threads NAP.
+ *
+ * Thread 0 clears HID0_POWER8_DYNLPARDIS (Dynamic LPAR Disable). This tells
+ * the hardware that if all threads except 0 are napping, the hardware should
+ * unsplit the core.
+ *
+ * Non-zero threads are sent to a NAP loop, they don't exit the loop until they
+ * see the core unsplit.
+ *
+ * Core 0 spins waiting for the hardware to see all the other threads napping
+ * and perform the unsplit.
+ *
+ * Once thread 0 sees the unsplit, it IPIs the secondary threads to wake them
+ * out of NAP. They will then see the core unsplit and exit the NAP loop.
+ *
+ * Splitting
+ * ---------
+ *
+ * The basic splitting procedure is fairly straight forward. However it is
+ * complicated by the fact that after the split occurs, the newly created
+ * subcores are not in a fully initialised state.
+ *
+ * Most notably the subcores do not have the correct value for SDR1, which
+ * means they must not be running in virtual mode when the split occurs. The
+ * subcores have separate timebases SPRs but these are pre-synchronised by
+ * opal.
+ *
+ * To begin with secondary threads are sent to an assembly routine. There they
+ * switch to real mode, so they are immune to the uninitialised SDR1 value.
+ * Once in real mode they indicate that they are in real mode, and spin waiting
+ * to see the core split.
+ *
+ * Thread 0 waits to see that all secondaries are in real mode, and then begins
+ * the splitting procedure. It firstly sets HID0_POWER8_DYNLPARDIS, which
+ * prevents the hardware from unsplitting. Then it sets the appropriate HID bit
+ * to request the split, and spins waiting to see that the split has happened.
+ *
+ * Concurrently the secondaries will notice the split. When they do they set up
+ * their SPRs, notably SDR1, and then they can return to virtual mode and exit
+ * the procedure.
+ */
+/* Initialised at boot by subcore_init() */
+static int subcores_per_core;
+/*
+ * Used to communicate to offline cpus that we want them to pop out of the
+ * offline loop and do a split or unsplit.
+ *
+ * 0 - no split happening
+ * 1 - unsplit in progress
+ * 2 - split to 2 in progress
+ * 4 - split to 4 in progress
+ */
+static int new_split_mode;
+static cpumask_var_t cpu_offline_mask;
+struct split_state {
+        u8 step;
+        u8 master;
+};
+static DEFINE_PER_CPU(struct split_state, split_state);
+static void wait_for_sync_step(int step)
+{
+        int i, cpu = smp_processor_id();
+        for (i = cpu + 1; i < cpu + threads_per_core; i++)
+                while(per_cpu(split_state, i).step < step)
+                        barrier();
+        /* Order the wait loop vs any subsequent loads/stores. */
+        mb();
+}
+static void unsplit_core(void)
+{
+        u64 hid0, mask;
+        int i, cpu;
+        mask = HID0_POWER8_2LPARMODE | HID0_POWER8_4LPARMODE;
+        cpu = smp_processor_id();
+        if (cpu_thread_in_core(cpu) != 0) {
+                while (mfspr(SPRN_HID0) & mask)
+                        power7_nap(0);
+                per_cpu(split_state, cpu).step = SYNC_STEP_UNSPLIT;
+                return;
+        }
+        hid0 = mfspr(SPRN_HID0);
+        hid0 &= ~HID0_POWER8_DYNLPARDIS;
+        mtspr(SPRN_HID0, hid0);
+        while (mfspr(SPRN_HID0) & mask)
+                cpu_relax();
+        /* Wake secondaries out of NAP */
+        for (i = cpu + 1; i < cpu + threads_per_core; i++)
+                smp_send_reschedule(i);
+        wait_for_sync_step(SYNC_STEP_UNSPLIT);
+}
+static void split_core(int new_mode)
+{
+        struct {  u64 value; u64 mask; } split_parms[2] = {
+                { HID0_POWER8_1TO2LPAR, HID0_POWER8_2LPARMODE },
+                { HID0_POWER8_1TO4LPAR, HID0_POWER8_4LPARMODE }
+        };
+        int i, cpu;
+        u64 hid0;
+        /* Convert new_mode (2 or 4) into an index into our parms array */
+        i = (new_mode >> 1) - 1;
+        BUG_ON(i < 0 || i > 1);
+        cpu = smp_processor_id();
+        if (cpu_thread_in_core(cpu) != 0) {
+                split_core_secondary_loop(&per_cpu(split_state, cpu).step);
+                return;
+        }
+        wait_for_sync_step(SYNC_STEP_REAL_MODE);
+        /* Write new mode */
+        hid0  = mfspr(SPRN_HID0);
+        hid0 |= HID0_POWER8_DYNLPARDIS | split_parms[i].value;
+        mtspr(SPRN_HID0, hid0);
+        /* Wait for it to happen */
+        while (!(mfspr(SPRN_HID0) & split_parms[i].mask))
+                cpu_relax();
+}
+static void cpu_do_split(int new_mode)
+{
+        /*
+         * At boot subcores_per_core will be 0, so we will always unsplit at
+         * boot. In the usual case where the core is already unsplit it's a
+         * nop, and this just ensures the kernel's notion of the mode is
+         * consistent with the hardware.
+         */
+        if (subcores_per_core != 1)
+                unsplit_core();
+        if (new_mode != 1)
+                split_core(new_mode);
+        mb();
+        per_cpu(split_state, smp_processor_id()).step = SYNC_STEP_FINISHED;
+}
+bool cpu_core_split_required(void)
+{
+        smp_rmb();
+        if (!new_split_mode)
+                return false;
+        cpu_do_split(new_split_mode);
+        return true;
+}
+static int cpu_update_split_mode(void *data)
+{
+        int cpu, new_mode = *(int *)data;
+        if (this_cpu_ptr(&split_state)->master) {
+                new_split_mode = new_mode;
+                smp_wmb();
+                cpumask_andnot(cpu_offline_mask, cpu_present_mask,
+                               cpu_online_mask);
+                /* This should work even though the cpu is offline */
+                for_each_cpu(cpu, cpu_offline_mask)
+                        smp_send_reschedule(cpu);
+        }
+        cpu_do_split(new_mode);
+        if (this_cpu_ptr(&split_state)->master) {
+                /* Wait for all cpus to finish before we touch subcores_per_core */
+                for_each_present_cpu(cpu) {
+                        if (cpu >= setup_max_cpus)
+                                break;
+                        while(per_cpu(split_state, cpu).step < SYNC_STEP_FINISHED)
+                                barrier();
+                }
+                new_split_mode = 0;
+                /* Make the new mode public */
+                subcores_per_core = new_mode;
+                threads_per_subcore = threads_per_core / subcores_per_core;
+                /* Make sure the new mode is written before we exit */
+                mb();
+        }
+        return 0;
+}
+static int set_subcores_per_core(int new_mode)
+{
+        struct split_state *state;
+        int cpu;
+        if (kvm_hv_mode_active()) {
+                pr_err("Unable to change split core mode while KVM active.\n");
+                return -EBUSY;
+        }
+        /*
+         * We are only called at boot, or from the sysfs write. If that ever
+         * changes we'll need a lock here.
+         */
+        BUG_ON(new_mode < 1 || new_mode > 4 || new_mode == 3);
+        for_each_present_cpu(cpu) {
+                state = &per_cpu(split_state, cpu);
+                state->step = SYNC_STEP_INITIAL;
+                state->master = 0;
+        }
+        get_online_cpus();
+        /* This cpu will update the globals before exiting stop machine */
+        this_cpu_ptr(&split_state)->master = 1;
+        /* Ensure state is consistent before we call the other cpus */
+        mb();
+        stop_machine(cpu_update_split_mode, &new_mode, cpu_online_mask);
+        put_online_cpus();
+        return 0;
+}
+static ssize_t __used store_subcores_per_core(struct device *dev,
+                struct device_attribute *attr, const char *buf,
+                size_t count)
+{
+        unsigned long val;
+        int rc;
+        /* We are serialised by the attribute lock */
+        rc = sscanf(buf, "%lx", &val);
+        if (rc != 1)
+                return -EINVAL;
+        switch (val) {
+        case 1:
+        case 2:
+        case 4:
+                if (subcores_per_core == val)
+                        /* Nothing to do */
+                        goto out;
+                break;
+        default:
+                return -EINVAL;
+        }
+        rc = set_subcores_per_core(val);
+        if (rc)
+                return rc;
+out:
+        return count;
+}
+static ssize_t show_subcores_per_core(struct device *dev,
+                struct device_attribute *attr, char *buf)
+{
+        return sprintf(buf, "%x\n", subcores_per_core);
+}
+static DEVICE_ATTR(subcores_per_core, 0644,
+                show_subcores_per_core, store_subcores_per_core);
+static int subcore_init(void)
+{
+        if (!cpu_has_feature(CPU_FTR_ARCH_207S))
+                return 0;
+        /*
+         * We need all threads in a core to be present to split/unsplit so
+         * continue only if max_cpus are aligned to threads_per_core.
+         */
+        if (setup_max_cpus % threads_per_core)
+                return 0;
+        BUG_ON(!alloc_cpumask_var(&cpu_offline_mask, GFP_KERNEL));
+        set_subcores_per_core(1);
+        return device_create_file(cpu_subsys.dev_root,
+                                  &dev_attr_subcores_per_core);
+}
+machine_device_initcall(powernv, subcore_init);
diff --git a/arch/powerpc/platforms/powernv/subcore.h b/arch/powerpc/platforms/powernv/subcore.h
new file mode 100644
index 000000000000..148abc91debf
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/subcore.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2013, Michael Ellerman, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+/* These are ordered and tested with <= */
+#define SYNC_STEP_INITIAL       0
+#define SYNC_STEP_UNSPLIT       1       /* Set by secondary when it sees unsplit */
+#define SYNC_STEP_REAL_MODE     2       /* Set by secondary when in real mode  */
+#define SYNC_STEP_FINISHED      3       /* Set by secondary when split/unsplit is done */
+#ifndef __ASSEMBLY__
+void split_core_secondary_loop(u8 *state);
+#endif
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index 8a8f0472d98f..0bec0c02c5e7 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -175,6 +175,36 @@ static int pseries_eeh_find_cap(struct device_node *dn, int cap)
        return 0;
 }
+static int pseries_eeh_find_ecap(struct device_node *dn, int cap)
+{
+        struct pci_dn *pdn = PCI_DN(dn);
+        struct eeh_dev *edev = of_node_to_eeh_dev(dn);
+        u32 header;
+        int pos = 256;
+        int ttl = (4096 - 256) / 8;
+        if (!edev || !edev->pcie_cap)
+                return 0;
+        if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
+                return 0;
+        else if (!header)
+                return 0;
+        while (ttl-- > 0) {
+                if (PCI_EXT_CAP_ID(header) == cap && pos)
+                        return pos;
+                pos = PCI_EXT_CAP_NEXT(header);
+                if (pos < 256)
+                        break;
+                if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
+                        break;
+        }
+        return 0;
+}
 /**
 * pseries_eeh_of_probe - EEH probe on the given device
 * @dn: OF node
@@ -220,7 +250,9 @@ static void *pseries_eeh_of_probe(struct device_node *dn, void *flag)
         * or PCIe switch downstream port.
         */
        edev->class_code = class_code;
+        edev->pcix_cap = pseries_eeh_find_cap(dn, PCI_CAP_ID_PCIX);
        edev->pcie_cap = pseries_eeh_find_cap(dn, PCI_CAP_ID_EXP);
+        edev->aer_cap = pseries_eeh_find_ecap(dn, PCI_EXT_CAP_ID_ERR);
        edev->mode &= 0xFFFFFF00;
        if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
                edev->mode |= EEH_DEV_BRIDGE;
@@ -464,6 +496,7 @@ static int pseries_eeh_get_state(struct eeh_pe *pe, int *state)
                        } else {
                                result = EEH_STATE_NOT_SUPPORT;
                        }
+                        break;
                default:
                        result = EEH_STATE_NOT_SUPPORT;
                }
@@ -499,11 +532,19 @@ static int pseries_eeh_reset(struct eeh_pe *pe, int option)
        /* If fundamental-reset not supported, try hot-reset */
        if (option == EEH_RESET_FUNDAMENTAL &&
            ret == -8) {
+                option = EEH_RESET_HOT;
                ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
                                config_addr, BUID_HI(pe->phb->buid),
-                                BUID_LO(pe->phb->buid), EEH_RESET_HOT);
+                                BUID_LO(pe->phb->buid), option);
        }
+        /* We need reset hold or settlement delay */
+        if (option == EEH_RESET_FUNDAMENTAL ||
+            option == EEH_RESET_HOT)
+                msleep(EEH_PE_RST_HOLD_TIME);
+        else
+                msleep(EEH_PE_RST_SETTLE_TIME);
        return ret;
 }
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index 7f75c94af822..7995135170a3 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -21,7 +21,7 @@
 #include <asm/prom.h>
 #include <asm/sparsemem.h>
-static unsigned long get_memblock_size(void)
+unsigned long pseries_memory_block_size(void)
 {
        struct device_node *np;
        unsigned int memblock_size = MIN_MEMORY_BLOCK_SIZE;
@@ -64,17 +64,6 @@ static unsigned long get_memblock_size(void)
        return memblock_size;
 }
-/* WARNING: This is going to override the generic definition whenever
- * pseries is built-in regardless of what platform is active at boot
- * time. This is fine for now as this is the only "option" and it
- * should work everywhere. If not, we'll have to turn this into a
- * ppc_md. callback
- */
-unsigned long memory_block_size_bytes(void)
-{
-        return get_memblock_size();
-}
 #ifdef CONFIG_MEMORY_HOTREMOVE
 static int pseries_remove_memory(u64 start, u64 size)
 {
@@ -105,7 +94,7 @@ static int pseries_remove_memblock(unsigned long base, unsigned int memblock_siz
        if (!pfn_valid(start_pfn))
                goto out;
-        block_sz = memory_block_size_bytes();
+        block_sz = pseries_memory_block_size();
        sections_per_block = block_sz / MIN_MEMORY_BLOCK_SIZE;
        nid = memory_add_physaddr_to_nid(base);
@@ -201,7 +190,7 @@ static int pseries_update_drconf_memory(struct of_prop_reconfig *pr)
        u32 *p;
        int i, rc = -EINVAL;
-        memblock_size = get_memblock_size();
+        memblock_size = pseries_memory_block_size();
        if (!memblock_size)
                return -EINVAL;
diff --git a/arch/powerpc/platforms/pseries/hvCall.S b/arch/powerpc/platforms/pseries/hvCall.S
index 444fe7759e55..99ecf0a5a929 100644
--- a/arch/powerpc/platforms/pseries/hvCall.S
+++ b/arch/powerpc/platforms/pseries/hvCall.S
@@ -49,7 +49,7 @@ END_FTR_SECTION(0, 1);						\
        std     r0,16(r1);                                      \
        addi    r4,r1,STK_PARAM(FIRST_REG);                     \
        stdu    r1,-STACK_FRAME_OVERHEAD(r1);                   \
-        bl      .__trace_hcall_entry;                           \
+        bl      __trace_hcall_entry;                            \
        addi    r1,r1,STACK_FRAME_OVERHEAD;                     \
        ld      r0,16(r1);                                      \
        ld      r3,STK_PARAM(R3)(r1);                           \
@@ -83,7 +83,7 @@ END_FTR_SECTION(0, 1);						\
        mr      r3,r6;                                          \
        std     r0,16(r1);                                      \
        stdu    r1,-STACK_FRAME_OVERHEAD(r1);                   \
-        bl      .__trace_hcall_exit;                            \
+        bl      __trace_hcall_exit;                             \
        addi    r1,r1,STACK_FRAME_OVERHEAD;                     \
        ld      r0,16(r1);                                      \
        ld      r3,STK_PARAM(R3)(r1);                           \
@@ -106,7 +106,7 @@ END_FTR_SECTION(0, 1);						\
        .text
-_GLOBAL(plpar_hcall_norets)
+_GLOBAL_TOC(plpar_hcall_norets)
        HMT_MEDIUM
        mfcr    r0
@@ -122,7 +122,7 @@ _GLOBAL(plpar_hcall_norets)
        mtcrf   0xff,r0
        blr                             /* return r3 = status */
-_GLOBAL(plpar_hcall)
+_GLOBAL_TOC(plpar_hcall)
        HMT_MEDIUM
        mfcr    r0
@@ -188,7 +188,7 @@ _GLOBAL(plpar_hcall_raw)
        blr                             /* return r3 = status */
-_GLOBAL(plpar_hcall9)
+_GLOBAL_TOC(plpar_hcall9)
        HMT_MEDIUM
        mfcr    r0
diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index 99219530ea4a..361add62abf1 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -64,4 +64,6 @@ extern int dlpar_detach_node(struct device_node *);
 struct pci_host_bridge;
 int pseries_root_bridge_prepare(struct pci_host_bridge *bridge);
+unsigned long pseries_memory_block_size(void);
 #endif /* _PSERIES_PSERIES_H */
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 099d2df976a2..f2f40e64658f 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -510,7 +510,11 @@ static void __init pSeries_setup_arch(void)
 static int __init pSeries_init_panel(void)
 {
        /* Manually leave the kernel version on the panel. */
+#ifdef __BIG_ENDIAN__
        ppc_md.progress("Linux ppc64\n", 0);
+#else
+        ppc_md.progress("Linux ppc64le\n", 0);
+#endif
        ppc_md.progress(init_utsname()->version, 0);
        return 0;
@@ -806,4 +810,7 @@ define_machine(pseries) {
 #ifdef CONFIG_KEXEC
        .machine_kexec          = pSeries_machine_kexec,
 #endif
+#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
+        .memory_block_size      = pseries_memory_block_size,
+#endif
 };
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index 24f58cb0a543..a3555b10c1a5 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -44,6 +44,7 @@
 #include <asm/xics.h>
 #include <asm/dbell.h>
 #include <asm/plpar_wrappers.h>
+#include <asm/code-patching.h>
 #include "pseries.h"
 #include "offline_states.h"
@@ -96,8 +97,8 @@ int smp_query_cpu_stopped(unsigned int pcpu)
 static inline int smp_startup_cpu(unsigned int lcpu)
 {
        int status;
-        unsigned long start_here = __pa((u32)*((unsigned long *)
+        unsigned long start_here =
-                                               generic_secondary_smp_init));
+                        __pa(ppc_function_entry(generic_secondary_smp_init));
        unsigned int pcpu;
        int start_cpu;
diff --git a/arch/powerpc/platforms/wsp/scom_smp.c b/arch/powerpc/platforms/wsp/scom_smp.c
index 268bc899c1f7..8c79ce016cf1 100644
--- a/arch/powerpc/platforms/wsp/scom_smp.c
+++ b/arch/powerpc/platforms/wsp/scom_smp.c
@@ -20,6 +20,7 @@
 #include <asm/reg_a2.h>
 #include <asm/scom.h>
 #include <asm/udbg.h>
+#include <asm/code-patching.h>
 #include "wsp.h"
@@ -405,7 +406,7 @@ int a2_scom_startup_cpu(unsigned int lcpu, int thr_idx, struct device_node *np)
                        goto fail;
        }
-        start_here = *(unsigned long *)(core_setup ? generic_secondary_smp_init
+        start_here = ppc_function_entry(core_setup ? generic_secondary_smp_init
                                        : generic_secondary_thread_init);
        pr_devel("CPU%d entry point at 0x%lx...\n", lcpu, start_here);
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index 7baa70d6dc01..a19332a38715 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -7,6 +7,12 @@ config PPC4xx_PCI_EXPRESS
        depends on PCI && 4xx
        default n
+config PPC4xx_HSTA_MSI
+        bool
+        depends on PCI_MSI
+        depends on PCI && 4xx
+        default n
 config PPC4xx_MSI
        bool
        depends on PCI_MSI
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index afbcc37aa094..f7cb2a1b01fa 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_OF_RTC)		+= of_rtc.o
 ifeq ($(CONFIG_PCI),y)
 obj-$(CONFIG_4xx)               += ppc4xx_pci.o
 endif
+obj-$(CONFIG_PPC4xx_HSTA_MSI)   += ppc4xx_hsta_msi.o
 obj-$(CONFIG_PPC4xx_MSI)        += ppc4xx_msi.o
 obj-$(CONFIG_PPC4xx_CPM)        += ppc4xx_cpm.o
 obj-$(CONFIG_PPC4xx_GPIO)       += ppc4xx_gpio.o
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 3f415e252ea5..4bd091a05583 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1150,8 +1150,7 @@ static int fsl_pci_pme_probe(struct pci_controller *hose)
        pci = hose->private_data;
        /* Enable PTOD, ENL23D & EXL23D */
-        out_be32(&pci->pex_pme_mes_disr, 0);
+        clrbits32(&pci->pex_pme_mes_disr,
-        setbits32(&pci->pex_pme_mes_disr,
                  PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
        out_be32(&pci->pex_pme_mes_ier, 0);
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index cf2b0840a672..c04b718307c8 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -391,8 +391,10 @@ int fsl_rio_setup(struct platform_device *dev)
        ops->get_inb_message = fsl_get_inb_message;
        rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
-        if (!rmu_node)
+        if (!rmu_node) {
+                dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
                goto err_rmu;
+        }
        rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
        if (rc) {
                dev_err(&dev->dev, "Can't get %s property 'reg'\n",
@@ -413,6 +415,7 @@ int fsl_rio_setup(struct platform_device *dev)
        /*set up doobell node*/
        np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
        if (!np) {
+                dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
                rc = -ENODEV;
                goto err_dbell;
        }
@@ -441,6 +444,7 @@ int fsl_rio_setup(struct platform_device *dev)
        /*set up port write node*/
        np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
        if (!np) {
+                dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
                rc = -ENODEV;
                goto err_pw;
        }
@@ -633,14 +637,18 @@ int fsl_rio_setup(struct platform_device *dev)
        return 0;
 err:
        kfree(pw);
+        pw = NULL;
 err_pw:
        kfree(dbell);
+        dbell = NULL;
 err_dbell:
        iounmap(rmu_regs_win);
+        rmu_regs_win = NULL;
 err_rmu:
        kfree(ops);
 err_ops:
        iounmap(rio_regs_win);
+        rio_regs_win = NULL;
 err_rio_regs:
        return rc;
 }
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
index 00e224a1048c..b48197ae44d0 100644
--- a/arch/powerpc/sysdev/fsl_rmu.c
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -881,9 +881,9 @@ fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
        rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
                         "msg_rx", (void *)mport);
        if (rc < 0) {
-                dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
+                dma_free_coherent(priv->dev,
-                        rmu->msg_tx_ring.virt_buffer[i],
+                        rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
-                        rmu->msg_tx_ring.phys_buffer[i]);
+                        rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
                goto out;
        }
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 8209744b2829..be33c9768ea1 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1588,10 +1588,6 @@ void __init mpic_init(struct mpic *mpic)
                        num_timers = 8;
        }
-        /* FSL mpic error interrupt intialization */
-        if (mpic->flags & MPIC_FSL_HAS_EIMR)
-                mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
        /* Initialize timers to our reserved vectors and mask them for now */
        for (i = 0; i < num_timers; i++) {
                unsigned int offset = mpic_tm_offset(mpic, i);
@@ -1675,6 +1671,10 @@ void __init mpic_init(struct mpic *mpic)
                        irq_set_chained_handler(virq, &mpic_cascade);
                }
        }
+        /* FSL mpic error interrupt intialization */
+        if (mpic->flags & MPIC_FSL_HAS_EIMR)
+                mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
 }
 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
diff --git a/arch/powerpc/sysdev/ppc4xx_hsta_msi.c b/arch/powerpc/sysdev/ppc4xx_hsta_msi.c
new file mode 100644
index 000000000000..11c888416f0a
--- /dev/null
+++ b/arch/powerpc/sysdev/ppc4xx_hsta_msi.c
@@ -0,0 +1,215 @@
+/*
+ * MSI support for PPC4xx SoCs using High Speed Transfer Assist (HSTA) for
+ * generation of the interrupt.
+ *
+ * Copyright © 2013 Alistair Popple <alistair@popple.id.au> IBM Corporation
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/msi.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/semaphore.h>
+#include <asm/msi_bitmap.h>
+struct ppc4xx_hsta_msi {
+        struct device *dev;
+        /* The ioremapped HSTA MSI IO space */
+        u32 __iomem *data;
+        /* Physical address of HSTA MSI IO space */
+        u64 address;
+        struct msi_bitmap bmp;
+        /* An array mapping offsets to hardware IRQs */
+        int *irq_map;
+        /* Number of hwirqs supported */
+        int irq_count;
+};
+static struct ppc4xx_hsta_msi ppc4xx_hsta_msi;
+static int hsta_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        struct msi_msg msg;
+        struct msi_desc *entry;
+        int irq, hwirq;
+        u64 addr;
+        list_for_each_entry(entry, &dev->msi_list, list) {
+                irq = msi_bitmap_alloc_hwirqs(&ppc4xx_hsta_msi.bmp, 1);
+                if (irq < 0) {
+                        pr_debug("%s: Failed to allocate msi interrupt\n",
+                                 __func__);
+                        return irq;
+                }
+                hwirq = ppc4xx_hsta_msi.irq_map[irq];
+                if (hwirq == NO_IRQ) {
+                        pr_err("%s: Failed mapping irq %d\n", __func__, irq);
+                        return -EINVAL;
+                }
+                /*
+                 * HSTA generates interrupts on writes to 128-bit aligned
+                 * addresses.
+                 */
+                addr = ppc4xx_hsta_msi.address + irq*0x10;
+                msg.address_hi = upper_32_bits(addr);
+                msg.address_lo = lower_32_bits(addr);
+                /* Data is not used by the HSTA. */
+                msg.data = 0;
+                pr_debug("%s: Setup irq %d (0x%0llx)\n", __func__, hwirq,
+                         (((u64) msg.address_hi) << 32) | msg.address_lo);
+                if (irq_set_msi_desc(hwirq, entry)) {
+                        pr_err(
+                        "%s: Invalid hwirq %d specified in device tree\n",
+                        __func__, hwirq);
+                        msi_bitmap_free_hwirqs(&ppc4xx_hsta_msi.bmp, irq, 1);
+                        return -EINVAL;
+                }
+                write_msi_msg(hwirq, &msg);
+        }
+        return 0;
+}
+static int hsta_find_hwirq_offset(int hwirq)
+{
+        int irq;
+        /* Find the offset given the hwirq */
+        for (irq = 0; irq < ppc4xx_hsta_msi.irq_count; irq++)
+                if (ppc4xx_hsta_msi.irq_map[irq] == hwirq)
+                        return irq;
+        return -EINVAL;
+}
+static void hsta_teardown_msi_irqs(struct pci_dev *dev)
+{
+        struct msi_desc *entry;
+        int irq;
+        list_for_each_entry(entry, &dev->msi_list, list) {
+                if (entry->irq == NO_IRQ)
+                        continue;
+                irq = hsta_find_hwirq_offset(entry->irq);
+                /* entry->irq should always be in irq_map */
+                BUG_ON(irq < 0);
+                irq_set_msi_desc(entry->irq, NULL);
+                msi_bitmap_free_hwirqs(&ppc4xx_hsta_msi.bmp, irq, 1);
+                pr_debug("%s: Teardown IRQ %u (index %u)\n", __func__,
+                         entry->irq, irq);
+        }
+}
+static int hsta_msi_check_device(struct pci_dev *pdev, int nvec, int type)
+{
+        /* We don't support MSI-X */
+        if (type == PCI_CAP_ID_MSIX) {
+                pr_debug("%s: MSI-X not supported.\n", __func__);
+                return -EINVAL;
+        }
+        return 0;
+}
+static int hsta_msi_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct resource *mem;
+        int irq, ret, irq_count;
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (IS_ERR(mem)) {
+                dev_err(dev, "Unable to get mmio space\n");
+                return -EINVAL;
+        }
+        irq_count = of_irq_count(dev->of_node);
+        if (!irq_count) {
+                dev_err(dev, "Unable to find IRQ range\n");
+                return -EINVAL;
+        }
+        ppc4xx_hsta_msi.dev = dev;
+        ppc4xx_hsta_msi.address = mem->start;
+        ppc4xx_hsta_msi.data = ioremap(mem->start, resource_size(mem));
+        ppc4xx_hsta_msi.irq_count = irq_count;
+        if (IS_ERR(ppc4xx_hsta_msi.data)) {
+                dev_err(dev, "Unable to map memory\n");
+                return -ENOMEM;
+        }
+        ret = msi_bitmap_alloc(&ppc4xx_hsta_msi.bmp, irq_count, dev->of_node);
+        if (ret)
+                goto out;
+        ppc4xx_hsta_msi.irq_map = kmalloc(sizeof(int) * irq_count, GFP_KERNEL);
+        if (IS_ERR(ppc4xx_hsta_msi.irq_map)) {
+                ret = -ENOMEM;
+                goto out1;
+        }
+        /* Setup a mapping from irq offsets to hardware irq numbers */
+        for (irq = 0; irq < irq_count; irq++) {
+                ppc4xx_hsta_msi.irq_map[irq] =
+                        irq_of_parse_and_map(dev->of_node, irq);
+                if (ppc4xx_hsta_msi.irq_map[irq] == NO_IRQ) {
+                        dev_err(dev, "Unable to map IRQ\n");
+                        ret = -EINVAL;
+                        goto out2;
+                }
+        }
+        ppc_md.setup_msi_irqs = hsta_setup_msi_irqs;
+        ppc_md.teardown_msi_irqs = hsta_teardown_msi_irqs;
+        ppc_md.msi_check_device = hsta_msi_check_device;
+        return 0;
+out2:
+        kfree(ppc4xx_hsta_msi.irq_map);
+out1:
+        msi_bitmap_free(&ppc4xx_hsta_msi.bmp);
+out:
+        iounmap(ppc4xx_hsta_msi.data);
+        return ret;
+}
+static const struct of_device_id hsta_msi_ids[] = {
+        {
+                .compatible = "ibm,hsta-msi",
+        },
+        {}
+};
+static struct platform_driver hsta_msi_driver = {
+        .probe = hsta_msi_probe,
+        .driver = {
+                .name = "hsta-msi",
+                .owner = THIS_MODULE,
+                .of_match_table = hsta_msi_ids,
+        },
+};
+static int hsta_msi_init(void)
+{
+        return platform_driver_register(&hsta_msi_driver);
+}
+subsys_initcall(hsta_msi_init);
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 4914fd3f41ec..df6e2fc4ff92 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -176,8 +176,12 @@ static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
                return -ENXIO;
        }
-        /* Check that we are fully contained within 32 bits space */
+        /* Check that we are fully contained within 32 bits space if we are not
-        if (res->end > 0xffffffff) {
+         * running on a 460sx or 476fpe which have 64 bit bus addresses.
+         */
+        if (res->end > 0xffffffff &&
+            !(of_device_is_compatible(hose->dn, "ibm,plb-pciex-460sx")
+              || of_device_is_compatible(hose->dn, "ibm,plb-pciex-476fpe"))) {
                printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
                       hose->dn->full_name);
                return -ENXIO;
@@ -1440,7 +1444,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
                ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
 #endif
 #ifdef CONFIG_476FPE
-        if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe"))
+        if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe")
+                || of_device_is_compatible(np, "ibm,plb-pciex-476gtr"))
                ppc4xx_pciex_hwops = &ppc_476fpe_pcie_hwops;
 #endif
        if (ppc4xx_pciex_hwops == NULL) {
@@ -1751,7 +1756,10 @@ static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port	*port,
                        dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
                                sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT
                                        | DCRO_PEGPL_OMRxMSKL_VAL);
-                else if (of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
+                else if (of_device_is_compatible(
+                                port->node, "ibm,plb-pciex-476fpe") ||
+                        of_device_is_compatible(
+                                port->node, "ibm,plb-pciex-476gtr"))
                        dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
                                sa | DCRO_PEGPL_476FPE_OMR1MSKL_UOT
                                        | DCRO_PEGPL_OMRxMSKL_VAL);
@@ -1881,7 +1889,10 @@ static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
                        sa |= PCI_BASE_ADDRESS_MEM_PREFETCH;
                if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
-                    of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
+                    of_device_is_compatible(
+                            port->node, "ibm,plb-pciex-476fpe") ||
+                    of_device_is_compatible(
+                            port->node, "ibm,plb-pciex-476gtr"))
                        sa |= PCI_BASE_ADDRESS_MEM_TYPE_64;
                out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 08504e75b2c7..d199bfa2f1fa 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -419,7 +419,7 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
                get_output_lock();
                excprint(regs);
                if (bp) {
-                        printf("cpu 0x%x stopped at breakpoint 0x%x (",
+                        printf("cpu 0x%x stopped at breakpoint 0x%lx (",
                               cpu, BP_NUM(bp));
                        xmon_print_symbol(regs->nip, " ", ")\n");
                }
@@ -513,7 +513,7 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
                excprint(regs);
                bp = at_breakpoint(regs->nip);
                if (bp) {
-                        printf("Stopped at breakpoint %x (", BP_NUM(bp));
+                        printf("Stopped at breakpoint %lx (", BP_NUM(bp));
                        xmon_print_symbol(regs->nip, " ", ")\n");
                }
                if (unrecoverable_excp(regs))
@@ -759,7 +759,7 @@ static void insert_cpu_bpts(void)
                brk.address = dabr.address;
                brk.type = (dabr.enabled & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL;
                brk.len = 8;
-                set_breakpoint(&brk);
+                __set_breakpoint(&brk);
        }
        if (iabr && cpu_has_feature(CPU_FTR_IABR))
                mtspr(SPRN_IABR, iabr->address
@@ -997,14 +997,14 @@ static int cpu_cmd(void)
                                        last_cpu = cpu;
                                } else {
                                        if (last_cpu != first_cpu)
-                                                printf("-%lx", last_cpu);
+                                                printf("-0x%lx", last_cpu);
                                        last_cpu = first_cpu = cpu;
-                                        printf(" %lx", cpu);
+                                        printf(" 0x%lx", cpu);
                                }
                        }
                }
                if (last_cpu != first_cpu)
-                        printf("-%lx", last_cpu);
+                        printf("-0x%lx", last_cpu);
                printf("\n");
                return 0;
        }
@@ -1024,7 +1024,7 @@ static int cpu_cmd(void)
                        /* take control back */
                        mb();
                        xmon_owner = smp_processor_id();
-                        printf("cpu %u didn't take control\n", cpu);
+                        printf("cpu 0x%x didn't take control\n", cpu);
                        return 0;
                }
                barrier();
@@ -1086,7 +1086,7 @@ csum(void)
        fcs = 0xffff;
        for (i = 0; i < ncsum; ++i) {
                if (mread(adrs+i, &v, 1) == 0) {
-                        printf("csum stopped at %x\n", adrs+i);
+                        printf("csum stopped at "REG"\n", adrs+i);
                        break;
                }
                fcs = FCS(fcs, v);
@@ -1202,12 +1202,12 @@ bpt_cmds(void)
                        /* assume a breakpoint address */
                        bp = at_breakpoint(a);
                        if (bp == NULL) {
-                                printf("No breakpoint at %x\n", a);
+                                printf("No breakpoint at %lx\n", a);
                                break;
                        }
                }
-                printf("Cleared breakpoint %x (", BP_NUM(bp));
+                printf("Cleared breakpoint %lx (", BP_NUM(bp));
                xmon_print_symbol(bp->address, " ", ")\n");
                bp->enabled = 0;
                break;
@@ -1746,7 +1746,7 @@ mwrite(unsigned long adrs, void *buf, int size)
                __delay(200);
                n = size;
        } else {
-                printf("*** Error writing address %x\n", adrs + n);
+                printf("*** Error writing address "REG"\n", adrs + n);
        }
        catch_memory_errors = 0;
        return n;
@@ -2435,7 +2435,7 @@ static void proccall(void)
                ret = func(args[0], args[1], args[2], args[3],
                           args[4], args[5], args[6], args[7]);
                sync();
-                printf("return value is %x\n", ret);
+                printf("return value is 0x%lx\n", ret);
        } else {
                printf("*** %x exception occurred\n", fault_except);
        }
@@ -2700,7 +2700,7 @@ static void dump_slb(void)
        unsigned long esid,vsid,valid;
        unsigned long llp;
-        printf("SLB contents of cpu %x\n", smp_processor_id());
+        printf("SLB contents of cpu 0x%x\n", smp_processor_id());
        for (i = 0; i < mmu_slb_size; i++) {
                asm volatile("slbmfee  %0,%1" : "=r" (esid) : "r" (i));
@@ -2732,7 +2732,7 @@ static void dump_stab(void)
        int i;
        unsigned long *tmp = (unsigned long *)local_paca->stab_addr;
-        printf("Segment table contents of cpu %x\n", smp_processor_id());
+        printf("Segment table contents of cpu 0x%x\n", smp_processor_id());
        for (i = 0; i < PAGE_SIZE/16; i++) {
                unsigned long a, b;
diff --git a/drivers/macintosh/windfarm_pm121.c b/drivers/macintosh/windfarm_pm121.c
index 7fe58b0ae8b4..b350fb86ff08 100644
--- a/drivers/macintosh/windfarm_pm121.c
+++ b/drivers/macintosh/windfarm_pm121.c
@@ -555,8 +555,18 @@ static void pm121_create_sys_fans(int loop_id)
        pid_param.interval      = PM121_SYS_INTERVAL;
        pid_param.history_len   = PM121_SYS_HISTORY_SIZE;
        pid_param.itarget       = param->itarget;
-        pid_param.min           = control->ops->get_min(control);
+        if(control)
-        pid_param.max           = control->ops->get_max(control);
+        {
+                pid_param.min           = control->ops->get_min(control);
+                pid_param.max           = control->ops->get_max(control);
+        } else {
+                /*
+                 * This is probably not the right!?
+                 * Perhaps goto fail  if control == NULL  above?
+                 */
+                pid_param.min           = 0;
+                pid_param.max           = 0;
+        }
        wf_pid_init(&pm121_sys_state[loop_id]->pid, &pid_param);
@@ -571,7 +581,7 @@ static void pm121_create_sys_fans(int loop_id)
           control the same control */
        printk(KERN_WARNING "pm121: failed to set up %s loop "
               "setting \"%s\" to max speed.\n",
-               loop_names[loop_id], control->name);
+               loop_names[loop_id], control ? control->name : "uninitialized value");
        if (control)
                wf_control_set_max(control);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 436a76ab4bb1..212c63d780e7 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3179,14 +3179,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
        return 0;
 }
-/**
+void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
- * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
- * @dev: Bridge device
- *
- * Use the bridge control register to assert reset on the secondary bus.
- * Devices on the secondary bus are left in power-on state.
- */
-void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
 {
        u16 ctrl;
@@ -3211,6 +3204,18 @@ void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
         */
        ssleep(1);
 }
+/**
+ * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
+ * @dev: Bridge device
+ *
+ * Use the bridge control register to assert reset on the secondary bus.
+ * Devices on the secondary bus are left in power-on state.
+ */
+void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
+{
+        pcibios_reset_secondary_bus(dev);
+}
 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
diff --git a/tools/testing/selftests/powerpc/Makefile b/tools/testing/selftests/powerpc/Makefile
index 316194f26ff4..b3dbe9ef1a40 100644
--- a/tools/testing/selftests/powerpc/Makefile
+++ b/tools/testing/selftests/powerpc/Makefile
@@ -13,7 +13,7 @@ CFLAGS := -Wall -O2 -flto -Wall -Werror -DGIT_VERSION='"$(GIT_VERSION)"' -I$(CUR
 export CC CFLAGS
-TARGETS = pmu copyloops
+TARGETS = pmu copyloops mm
 endif
diff --git a/tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h b/tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h
index ccd9c84c4e3f..d1dc37425510 100644
--- a/tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h
+++ b/tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h
@@ -46,12 +46,15 @@
 #define R20 r20
 #define R21 r21
 #define R22 r22
+#define R29 r29
+#define R30 r30
+#define R31 r31
 #define STACKFRAMESIZE  256
-#define STK_PARAM(i)    (48 + ((i)-3)*8)
 #define STK_REG(i)      (112 + ((i)-14)*8)
 #define _GLOBAL(A) FUNC_START(test_ ## A)
+#define _GLOBAL_TOC(A) _GLOBAL(A)
 #define PPC_MTOCRF(A, B)        mtocrf A, B
diff --git a/tools/testing/selftests/powerpc/mm/Makefile b/tools/testing/selftests/powerpc/mm/Makefile
new file mode 100644
index 000000000000..357ccbd6bad9
--- /dev/null
+++ b/tools/testing/selftests/powerpc/mm/Makefile
@@ -0,0 +1,18 @@
+noarg:
+        $(MAKE) -C ../
+PROGS := hugetlb_vs_thp_test
+all: $(PROGS)
+$(PROGS): ../harness.c
+run_tests: all
+        @-for PROG in $(PROGS); do \
+                ./$$PROG; \
+        done;
+clean:
+        rm -f $(PROGS)
+.PHONY: all run_tests clean
diff --git a/tools/testing/selftests/powerpc/mm/hugetlb_vs_thp_test.c b/tools/testing/selftests/powerpc/mm/hugetlb_vs_thp_test.c
new file mode 100644
index 000000000000..3d8e5b033e1d
--- /dev/null
+++ b/tools/testing/selftests/powerpc/mm/hugetlb_vs_thp_test.c
@@ -0,0 +1,72 @@
+#include <stdio.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include "utils.h"
+/* This must match the huge page & THP size */
+#define SIZE    (16 * 1024 * 1024)
+static int test_body(void)
+{
+        void *addr;
+        char *p;
+        addr = (void *)0xa0000000;
+        p = mmap(addr, SIZE, PROT_READ | PROT_WRITE,
+                 MAP_HUGETLB | MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
+        if (p != MAP_FAILED) {
+                /*
+                 * Typically the mmap will fail because no huge pages are
+                 * allocated on the system. But if there are huge pages
+                 * allocated the mmap will succeed. That's fine too, we just
+                 * munmap here before continuing.
+                 */
+                munmap(addr, SIZE);
+        }
+        p = mmap(addr, SIZE, PROT_READ | PROT_WRITE,
+                 MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
+        if (p == MAP_FAILED) {
+                printf("Mapping failed @ %p\n", addr);
+                perror("mmap");
+                return 1;
+        }
+        /*
+         * Either a user or kernel access is sufficient to trigger the bug.
+         * A kernel access is easier to spot & debug, as it will trigger the
+         * softlockup or RCU stall detectors, and when the system is kicked
+         * into xmon we get a backtrace in the kernel.
+         *
+         * A good option is:
+         *  getcwd(p, SIZE);
+         *
+         * For the purposes of this testcase it's preferable to spin in
+         * userspace, so the harness can kill us if we get stuck. That way we
+         * see a test failure rather than a dead system.
+         */
+        *p = 0xf;
+        munmap(addr, SIZE);
+        return 0;
+}
+static int test_main(void)
+{
+        int i;
+        /* 10,000 because it's a "bunch", and completes reasonably quickly */
+        for (i = 0; i < 10000; i++)
+                if (test_body())
+                        return 1;
+        return 0;
+}
+int main(void)
+{
+        return test_harness(test_main, "hugetlb_vs_thp");
+}