Merge tag 'char-misc-3.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver patches from Greg KH:
 "Here's the big char/misc driver patches for 3.14-rc1.

  Lots of little things, and a new "big" driver, genwqe.  Full details
  are in the shortlog"

* tag 'char-misc-3.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (90 commits)
  mei: limit the number of consecutive resets
  mei: revamp mei reset state machine
  drivers/char: don't use module_init in non-modular ttyprintk.c
  VMCI: fix error handling path when registering guest driver
  extcon: gpio: Add power resume support
  Documentation: HOWTO: Updates on subsystem trees, patchwork, -next (vs. -mm) in ko_KR
  Documentation: HOWTO: update for 2.6.x -> 3.x versioning in ko_KR
  Documentation: HOWTO: update stable address in ko_KR
  Documentation: HOWTO: update LXR web link in ko_KR
  char: nwbutton: open-code interruptible_sleep_on
  mei: fix syntax in comments and debug output
  mei: nfc: mei_nfc_free has to be called under lock
  mei: use hbm idle state to prevent spurious resets
  mei: do not run reset flow from the interrupt thread
  misc: genwqe: fix return value check in genwqe_device_create()
  GenWQE: Fix warnings for sparc
  GenWQE: Fix compile problems for Alpha
  Documentation/misc-devices/mei/mei-amt-version.c: remove unneeded call of mei_deinit()
  GenWQE: Rework return code for flash-update ioctl
  sgi-xp: open-code interruptible_sleep_on_timeout
  ...

64 files changed, 8428 insertions, 573 deletions

diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index d79d692d05b8..896413b59aae 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -735,7 +735,7 @@ static struct pci_device_id agp_amd64_pci_table[] = {
 
 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
 
-static DEFINE_PCI_DEVICE_TABLE(agp_amd64_pci_promisc_table) = {
+static const struct pci_device_id agp_amd64_pci_promisc_table[] = {
         { PCI_DEVICE_CLASS(0, 0) },
         { }
 };
diff --git a/drivers/char/i8k.c b/drivers/char/i8k.c
index e6939e13e338..e210f858d3cb 100644
--- a/drivers/char/i8k.c
+++ b/drivers/char/i8k.c
@@ -1,12 +1,11 @@
 /*
  * i8k.c -- Linux driver for accessing the SMM BIOS on Dell laptops.
- *          See http://www.debian.org/~dz/i8k/ for more information
- *          and for latest version of this driver.
  *
  * Copyright (C) 2001  Massimo Dal Zotto <dz@debian.org>
  *
  * Hwmon integration:
  * Copyright (C) 2011  Jean Delvare <khali@linux-fr.org>
+ * Copyright (C) 2013  Guenter Roeck <linux@roeck-us.net>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -19,6 +18,8 @@
  * General Public License for more details.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/module.h>
 #include <linux/types.h>
 #include <linux/init.h>
@@ -29,13 +30,12 @@
 #include <linux/mutex.h>
 #include <linux/hwmon.h>
 #include <linux/hwmon-sysfs.h>
-#include <asm/uaccess.h>
-#include <asm/io.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/sched.h>
 
 #include <linux/i8k.h>
 
-#define I8K_VERSION             "1.14 21/02/2005"
-
 #define I8K_SMM_FN_STATUS       0x0025
 #define I8K_SMM_POWER_STATUS    0x0069
 #define I8K_SMM_SET_FAN         0x01a3
@@ -44,7 +44,6 @@
 #define I8K_SMM_GET_TEMP        0x10a3
 #define I8K_SMM_GET_DELL_SIG1   0xfea3
 #define I8K_SMM_GET_DELL_SIG2   0xffa3
-#define I8K_SMM_BIOS_VERSION    0x00a6
 
 #define I8K_FAN_MULT            30
 #define I8K_MAX_TEMP            127
@@ -64,6 +63,15 @@
 static DEFINE_MUTEX(i8k_mutex);
 static char bios_version[4];
 static struct device *i8k_hwmon_dev;
+static u32 i8k_hwmon_flags;
+static int i8k_fan_mult;
+
+#define I8K_HWMON_HAVE_TEMP1    (1 << 0)
+#define I8K_HWMON_HAVE_TEMP2    (1 << 1)
+#define I8K_HWMON_HAVE_TEMP3    (1 << 2)
+#define I8K_HWMON_HAVE_TEMP4    (1 << 3)
+#define I8K_HWMON_HAVE_FAN1     (1 << 4)
+#define I8K_HWMON_HAVE_FAN2     (1 << 5)
 
 MODULE_AUTHOR("Massimo Dal Zotto (dz@debian.org)");
 MODULE_DESCRIPTION("Driver for accessing SMM BIOS on Dell laptops");
@@ -103,11 +111,11 @@ static const struct file_operations i8k_fops = {
 
 struct smm_regs {
         unsigned int eax;
-        unsigned int ebx __attribute__ ((packed));
-        unsigned int ecx __attribute__ ((packed));
-        unsigned int edx __attribute__ ((packed));
-        unsigned int esi __attribute__ ((packed));
-        unsigned int edi __attribute__ ((packed));
+        unsigned int ebx __packed;
+        unsigned int ecx __packed;
+        unsigned int edx __packed;
+        unsigned int esi __packed;
+        unsigned int edi __packed;
 };
 
 static inline const char *i8k_get_dmi_data(int field)
@@ -124,6 +132,17 @@ static int i8k_smm(struct smm_regs *regs)
 {
         int rc;
         int eax = regs->eax;
+        cpumask_var_t old_mask;
+
+        /* SMM requires CPU 0 */
+        if (!alloc_cpumask_var(&old_mask, GFP_KERNEL))
+                return -ENOMEM;
+        cpumask_copy(old_mask, &current->cpus_allowed);
+        set_cpus_allowed_ptr(current, cpumask_of(0));
+        if (smp_processor_id() != 0) {
+                rc = -EBUSY;
+                goto out;
+        }
 
 #if defined(CONFIG_X86_64)
         asm volatile("pushq %%rax\n\t"
@@ -148,7 +167,7 @@ static int i8k_smm(struct smm_regs *regs)
                 "pushfq\n\t"
                 "popq %%rax\n\t"
                 "andl $1,%%eax\n"
-                :"=a"(rc)
+                : "=a"(rc)
                 :    "a"(regs)
                 :    "%ebx", "%ecx", "%edx", "%esi", "%edi", "memory");
 #else
@@ -174,25 +193,17 @@ static int i8k_smm(struct smm_regs *regs)
             "lahf\n\t"
             "shrl $8,%%eax\n\t"
             "andl $1,%%eax\n"
-            :"=a"(rc)
+            : "=a"(rc)
             :    "a"(regs)
             :    "%ebx", "%ecx", "%edx", "%esi", "%edi", "memory");
 #endif
         if (rc != 0 || (regs->eax & 0xffff) == 0xffff || regs->eax == eax)
-                return -EINVAL;
+                rc = -EINVAL;
 
-        return 0;
-}
-
-/*
- * Read the bios version. Return the version as an integer corresponding
- * to the ascii value, for example "A17" is returned as 0x00413137.
- */
-static int i8k_get_bios_version(void)
-{
-        struct smm_regs regs = { .eax = I8K_SMM_BIOS_VERSION, };
-
-        return i8k_smm(&regs) ? : regs.eax;
+out:
+        set_cpus_allowed_ptr(current, old_mask);
+        free_cpumask_var(old_mask);
+        return rc;
 }
 
 /*
@@ -203,7 +214,8 @@ static int i8k_get_fn_status(void)
         struct smm_regs regs = { .eax = I8K_SMM_FN_STATUS, };
         int rc;
 
-        if ((rc = i8k_smm(&regs)) < 0)
+        rc = i8k_smm(&regs);
+        if (rc < 0)
                 return rc;
 
         switch ((regs.eax >> I8K_FN_SHIFT) & I8K_FN_MASK) {
@@ -226,7 +238,8 @@ static int i8k_get_power_status(void)
         struct smm_regs regs = { .eax = I8K_SMM_POWER_STATUS, };
         int rc;
 
-        if ((rc = i8k_smm(&regs)) < 0)
+        rc = i8k_smm(&regs);
+        if (rc < 0)
                 return rc;
 
         return (regs.eax & 0xff) == I8K_POWER_AC ? I8K_AC : I8K_BATTERY;
@@ -251,7 +264,7 @@ static int i8k_get_fan_speed(int fan)
         struct smm_regs regs = { .eax = I8K_SMM_GET_SPEED, };
 
         regs.ebx = fan & 0xff;
-        return i8k_smm(&regs) ? : (regs.eax & 0xffff) * fan_mult;
+        return i8k_smm(&regs) ? : (regs.eax & 0xffff) * i8k_fan_mult;
 }
 
 /*
@@ -277,10 +290,11 @@ static int i8k_get_temp(int sensor)
         int temp;
 
 #ifdef I8K_TEMPERATURE_BUG
-        static int prev;
+        static int prev[4];
 #endif
         regs.ebx = sensor & 0xff;
-        if ((rc = i8k_smm(&regs)) < 0)
+        rc = i8k_smm(&regs);
+        if (rc < 0)
                 return rc;
 
         temp = regs.eax & 0xff;
@@ -294,10 +308,10 @@ static int i8k_get_temp(int sensor)
          # 1003655139 00000054 00005c52
          */
         if (temp > I8K_MAX_TEMP) {
-                temp = prev;
-                prev = I8K_MAX_TEMP;
+                temp = prev[sensor];
+                prev[sensor] = I8K_MAX_TEMP;
         } else {
-                prev = temp;
+                prev[sensor] = temp;
         }
 #endif
 
@@ -309,7 +323,8 @@ static int i8k_get_dell_signature(int req_fn)
         struct smm_regs regs = { .eax = req_fn, };
         int rc;
 
-        if ((rc = i8k_smm(&regs)) < 0)
+        rc = i8k_smm(&regs);
+        if (rc < 0)
                 return rc;
 
         return regs.eax == 1145651527 && regs.edx == 1145392204 ? 0 : -1;
@@ -328,12 +343,14 @@ i8k_ioctl_unlocked(struct file *fp, unsigned int cmd, unsigned long arg)
 
         switch (cmd) {
         case I8K_BIOS_VERSION:
-                val = i8k_get_bios_version();
+                val = (bios_version[0] << 16) |
+                                (bios_version[1] << 8) | bios_version[2];
                 break;
 
         case I8K_MACHINE_ID:
                 memset(buff, 0, 16);
-                strlcpy(buff, i8k_get_dmi_data(DMI_PRODUCT_SERIAL), sizeof(buff));
+                strlcpy(buff, i8k_get_dmi_data(DMI_PRODUCT_SERIAL),
+                        sizeof(buff));
                 break;
 
         case I8K_FN_STATUS:
@@ -470,12 +487,13 @@ static ssize_t i8k_hwmon_show_temp(struct device *dev,
                                    struct device_attribute *devattr,
                                    char *buf)
 {
-        int cpu_temp;
+        int index = to_sensor_dev_attr(devattr)->index;
+        int temp;
 
-        cpu_temp = i8k_get_temp(0);
-        if (cpu_temp < 0)
-                return cpu_temp;
-        return sprintf(buf, "%d\n", cpu_temp * 1000);
+        temp = i8k_get_temp(index);
+        if (temp < 0)
+                return temp;
+        return sprintf(buf, "%d\n", temp * 1000);
 }
 
 static ssize_t i8k_hwmon_show_fan(struct device *dev,
@@ -491,12 +509,44 @@ static ssize_t i8k_hwmon_show_fan(struct device *dev,
         return sprintf(buf, "%d\n", fan_speed);
 }
 
+static ssize_t i8k_hwmon_show_pwm(struct device *dev,
+                                  struct device_attribute *devattr,
+                                  char *buf)
+{
+        int index = to_sensor_dev_attr(devattr)->index;
+        int status;
+
+        status = i8k_get_fan_status(index);
+        if (status < 0)
+                return -EIO;
+        return sprintf(buf, "%d\n", clamp_val(status * 128, 0, 255));
+}
+
+static ssize_t i8k_hwmon_set_pwm(struct device *dev,
+                                 struct device_attribute *attr,
+                                 const char *buf, size_t count)
+{
+        int index = to_sensor_dev_attr(attr)->index;
+        unsigned long val;
+        int err;
+
+        err = kstrtoul(buf, 10, &val);
+        if (err)
+                return err;
+        val = clamp_val(DIV_ROUND_CLOSEST(val, 128), 0, 2);
+
+        mutex_lock(&i8k_mutex);
+        err = i8k_set_fan(index, val);
+        mutex_unlock(&i8k_mutex);
+
+        return err < 0 ? -EIO : count;
+}
+
 static ssize_t i8k_hwmon_show_label(struct device *dev,
                                     struct device_attribute *devattr,
                                     char *buf)
 {
-        static const char *labels[4] = {
-                "i8k",
+        static const char *labels[3] = {
                 "CPU",
                 "Left Fan",
                 "Right Fan",
@@ -506,108 +556,108 @@ static ssize_t i8k_hwmon_show_label(struct device *dev,
         return sprintf(buf, "%s\n", labels[index]);
 }
 
-static DEVICE_ATTR(temp1_input, S_IRUGO, i8k_hwmon_show_temp, NULL);
+static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, i8k_hwmon_show_temp, NULL, 0);
+static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, i8k_hwmon_show_temp, NULL, 1);
+static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, i8k_hwmon_show_temp, NULL, 2);
+static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, i8k_hwmon_show_temp, NULL, 3);
 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, i8k_hwmon_show_fan, NULL,
                           I8K_FAN_LEFT);
+static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, i8k_hwmon_show_pwm,
+                          i8k_hwmon_set_pwm, I8K_FAN_LEFT);
 static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO, i8k_hwmon_show_fan, NULL,
                           I8K_FAN_RIGHT);
-static SENSOR_DEVICE_ATTR(name, S_IRUGO, i8k_hwmon_show_label, NULL, 0);
-static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, i8k_hwmon_show_label, NULL, 1);
-static SENSOR_DEVICE_ATTR(fan1_label, S_IRUGO, i8k_hwmon_show_label, NULL, 2);
-static SENSOR_DEVICE_ATTR(fan2_label, S_IRUGO, i8k_hwmon_show_label, NULL, 3);
+static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, i8k_hwmon_show_pwm,
+                          i8k_hwmon_set_pwm, I8K_FAN_RIGHT);
+static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, i8k_hwmon_show_label, NULL, 0);
+static SENSOR_DEVICE_ATTR(fan1_label, S_IRUGO, i8k_hwmon_show_label, NULL, 1);
+static SENSOR_DEVICE_ATTR(fan2_label, S_IRUGO, i8k_hwmon_show_label, NULL, 2);
+
+static struct attribute *i8k_attrs[] = {
+        &sensor_dev_attr_temp1_input.dev_attr.attr,     /* 0 */
+        &sensor_dev_attr_temp1_label.dev_attr.attr,     /* 1 */
+        &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 2 */
+        &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 3 */
+        &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 4 */
+        &sensor_dev_attr_fan1_input.dev_attr.attr,      /* 5 */
+        &sensor_dev_attr_pwm1.dev_attr.attr,            /* 6 */
+        &sensor_dev_attr_fan1_label.dev_attr.attr,      /* 7 */
+        &sensor_dev_attr_fan2_input.dev_attr.attr,      /* 8 */
+        &sensor_dev_attr_pwm2.dev_attr.attr,            /* 9 */
+        &sensor_dev_attr_fan2_label.dev_attr.attr,      /* 10 */
+        NULL
+};
 
-static void i8k_hwmon_remove_files(struct device *dev)
+static umode_t i8k_is_visible(struct kobject *kobj, struct attribute *attr,
+                              int index)
 {
-        device_remove_file(dev, &dev_attr_temp1_input);
-        device_remove_file(dev, &sensor_dev_attr_fan1_input.dev_attr);
-        device_remove_file(dev, &sensor_dev_attr_fan2_input.dev_attr);
-        device_remove_file(dev, &sensor_dev_attr_temp1_label.dev_attr);
-        device_remove_file(dev, &sensor_dev_attr_fan1_label.dev_attr);
-        device_remove_file(dev, &sensor_dev_attr_fan2_label.dev_attr);
-        device_remove_file(dev, &sensor_dev_attr_name.dev_attr);
+        if ((index == 0 || index == 1) &&
+            !(i8k_hwmon_flags & I8K_HWMON_HAVE_TEMP1))
+                return 0;
+        if (index == 2 && !(i8k_hwmon_flags & I8K_HWMON_HAVE_TEMP2))
+                return 0;
+        if (index == 3 && !(i8k_hwmon_flags & I8K_HWMON_HAVE_TEMP3))
+                return 0;
+        if (index == 4 && !(i8k_hwmon_flags & I8K_HWMON_HAVE_TEMP4))
+                return 0;
+        if (index >= 5 && index <= 7 &&
+            !(i8k_hwmon_flags & I8K_HWMON_HAVE_FAN1))
+                return 0;
+        if (index >= 8 && index <= 10 &&
+            !(i8k_hwmon_flags & I8K_HWMON_HAVE_FAN2))
+                return 0;
+
+        return attr->mode;
 }
 
+static const struct attribute_group i8k_group = {
+        .attrs = i8k_attrs,
+        .is_visible = i8k_is_visible,
+};
+__ATTRIBUTE_GROUPS(i8k);
+
 static int __init i8k_init_hwmon(void)
 {
         int err;
 
-        i8k_hwmon_dev = hwmon_device_register(NULL);
-        if (IS_ERR(i8k_hwmon_dev)) {
-                err = PTR_ERR(i8k_hwmon_dev);
-                i8k_hwmon_dev = NULL;
-                printk(KERN_ERR "i8k: hwmon registration failed (%d)\n", err);
-                return err;
-        }
-
-        /* Required name attribute */
-        err = device_create_file(i8k_hwmon_dev,
-                                 &sensor_dev_attr_name.dev_attr);
-        if (err)
-                goto exit_unregister;
+        i8k_hwmon_flags = 0;
 
         /* CPU temperature attributes, if temperature reading is OK */
         err = i8k_get_temp(0);
-        if (err < 0) {
-                dev_dbg(i8k_hwmon_dev,
-                        "Not creating temperature attributes (%d)\n", err);
-        } else {
-                err = device_create_file(i8k_hwmon_dev, &dev_attr_temp1_input);
-                if (err)
-                        goto exit_remove_files;
-                err = device_create_file(i8k_hwmon_dev,
-                                         &sensor_dev_attr_temp1_label.dev_attr);
-                if (err)
-                        goto exit_remove_files;
-        }
+        if (err >= 0)
+                i8k_hwmon_flags |= I8K_HWMON_HAVE_TEMP1;
+        /* check for additional temperature sensors */
+        err = i8k_get_temp(1);
+        if (err >= 0)
+                i8k_hwmon_flags |= I8K_HWMON_HAVE_TEMP2;
+        err = i8k_get_temp(2);
+        if (err >= 0)
+                i8k_hwmon_flags |= I8K_HWMON_HAVE_TEMP3;
+        err = i8k_get_temp(3);
+        if (err >= 0)
+                i8k_hwmon_flags |= I8K_HWMON_HAVE_TEMP4;
 
         /* Left fan attributes, if left fan is present */
         err = i8k_get_fan_status(I8K_FAN_LEFT);
-        if (err < 0) {
-                dev_dbg(i8k_hwmon_dev,
-                        "Not creating %s fan attributes (%d)\n", "left", err);
-        } else {
-                err = device_create_file(i8k_hwmon_dev,
-                                         &sensor_dev_attr_fan1_input.dev_attr);
-                if (err)
-                        goto exit_remove_files;
-                err = device_create_file(i8k_hwmon_dev,
-                                         &sensor_dev_attr_fan1_label.dev_attr);
-                if (err)
-                        goto exit_remove_files;
-        }
+        if (err >= 0)
+                i8k_hwmon_flags |= I8K_HWMON_HAVE_FAN1;
 
         /* Right fan attributes, if right fan is present */
         err = i8k_get_fan_status(I8K_FAN_RIGHT);
-        if (err < 0) {
-                dev_dbg(i8k_hwmon_dev,
-                        "Not creating %s fan attributes (%d)\n", "right", err);
-        } else {
-                err = device_create_file(i8k_hwmon_dev,
-                                         &sensor_dev_attr_fan2_input.dev_attr);
-                if (err)
-                        goto exit_remove_files;
-                err = device_create_file(i8k_hwmon_dev,
-                                         &sensor_dev_attr_fan2_label.dev_attr);
-                if (err)
-                        goto exit_remove_files;
-        }
+        if (err >= 0)
+                i8k_hwmon_flags |= I8K_HWMON_HAVE_FAN2;
 
+        i8k_hwmon_dev = hwmon_device_register_with_groups(NULL, "i8k", NULL,
+                                                          i8k_groups);
+        if (IS_ERR(i8k_hwmon_dev)) {
+                err = PTR_ERR(i8k_hwmon_dev);
+                i8k_hwmon_dev = NULL;
+                pr_err("hwmon registration failed (%d)\n", err);
+                return err;
+        }
         return 0;
-
- exit_remove_files:
-        i8k_hwmon_remove_files(i8k_hwmon_dev);
- exit_unregister:
-        hwmon_device_unregister(i8k_hwmon_dev);
-        return err;
 }
 
-static void __exit i8k_exit_hwmon(void)
-{
-        i8k_hwmon_remove_files(i8k_hwmon_dev);
-        hwmon_device_unregister(i8k_hwmon_dev);
-}
-
-static struct dmi_system_id __initdata i8k_dmi_table[] = {
+static struct dmi_system_id i8k_dmi_table[] __initdata = {
         {
                 .ident = "Dell Inspiron",
                 .matches = {
@@ -671,7 +721,23 @@ static struct dmi_system_id __initdata i8k_dmi_table[] = {
                         DMI_MATCH(DMI_PRODUCT_NAME, "XPS L421X"),
                 },
         },
-        { }
+        {
+                .ident = "Dell Studio",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "Studio"),
+                },
+                .driver_data = (void *)1,       /* fan multiplier override */
+        },
+        {
+                .ident = "Dell XPS M140",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "MXC051"),
+                },
+                .driver_data = (void *)1,       /* fan multiplier override */
+        },
+        { }
 };
 
 /*
@@ -679,8 +745,7 @@ static struct dmi_system_id __initdata i8k_dmi_table[] = {
  */
 static int __init i8k_probe(void)
 {
-        char buff[4];
-        int version;
+        const struct dmi_system_id *id;
 
         /*
          * Get DMI information
@@ -689,49 +754,30 @@ static int __init i8k_probe(void)
                 if (!ignore_dmi && !force)
                         return -ENODEV;
 
-                printk(KERN_INFO "i8k: not running on a supported Dell system.\n");
-                printk(KERN_INFO "i8k: vendor=%s, model=%s, version=%s\n",
+                pr_info("not running on a supported Dell system.\n");
+                pr_info("vendor=%s, model=%s, version=%s\n",
                         i8k_get_dmi_data(DMI_SYS_VENDOR),
                         i8k_get_dmi_data(DMI_PRODUCT_NAME),
                         i8k_get_dmi_data(DMI_BIOS_VERSION));
         }
 
-        strlcpy(bios_version, i8k_get_dmi_data(DMI_BIOS_VERSION), sizeof(bios_version));
+        strlcpy(bios_version, i8k_get_dmi_data(DMI_BIOS_VERSION),
+                sizeof(bios_version));
 
         /*
          * Get SMM Dell signature
          */
         if (i8k_get_dell_signature(I8K_SMM_GET_DELL_SIG1) &&
             i8k_get_dell_signature(I8K_SMM_GET_DELL_SIG2)) {
-                printk(KERN_ERR "i8k: unable to get SMM Dell signature\n");
+                pr_err("unable to get SMM Dell signature\n");
                 if (!force)
                         return -ENODEV;
         }
 
-        /*
-         * Get SMM BIOS version.
-         */
-        version = i8k_get_bios_version();
-        if (version <= 0) {
-                printk(KERN_WARNING "i8k: unable to get SMM BIOS version\n");
-        } else {
-                buff[0] = (version >> 16) & 0xff;
-                buff[1] = (version >> 8) & 0xff;
-                buff[2] = (version) & 0xff;
-                buff[3] = '\0';
-                /*
-                 * If DMI BIOS version is unknown use SMM BIOS version.
-                 */
-                if (!dmi_get_system_info(DMI_BIOS_VERSION))
-                        strlcpy(bios_version, buff, sizeof(bios_version));
-
-                /*
-                 * Check if the two versions match.
-                 */
-                if (strncmp(buff, bios_version, sizeof(bios_version)) != 0)
-                        printk(KERN_WARNING "i8k: BIOS version mismatch: %s != %s\n",
-                                buff, bios_version);
-        }
+        i8k_fan_mult = fan_mult;
+        id = dmi_first_match(i8k_dmi_table);
+        if (id && fan_mult == I8K_FAN_MULT && id->driver_data)
+                i8k_fan_mult = (unsigned long)id->driver_data;
 
         return 0;
 }
@@ -754,10 +800,6 @@ static int __init i8k_init(void)
         if (err)
                 goto exit_remove_proc;
 
-        printk(KERN_INFO
-               "Dell laptop SMM driver v%s Massimo Dal Zotto (dz@debian.org)\n",
-               I8K_VERSION);
-
         return 0;
 
  exit_remove_proc:
@@ -767,7 +809,7 @@ static int __init i8k_init(void)
 
 static void __exit i8k_exit(void)
 {
-        i8k_exit_hwmon();
+        hwmon_device_unregister(i8k_hwmon_dev);
         remove_proc_entry("i8k", NULL);
 }
 
diff --git a/drivers/char/lp.c b/drivers/char/lp.c
index 0913d79424d3..c4094c4e22c1 100644
--- a/drivers/char/lp.c
+++ b/drivers/char/lp.c
@@ -587,6 +587,8 @@ static int lp_do_ioctl(unsigned int minor, unsigned int cmd,
                 return -ENODEV;
         switch ( cmd ) {
                 case LPTIME:
+                        if (arg > UINT_MAX / HZ)
+                                return -EINVAL;
                         LP_TIME(minor) = arg * HZ/100;
                         break;
                 case LPCHAR:
diff --git a/drivers/char/nwbutton.c b/drivers/char/nwbutton.c
index 1fd00dc06897..76c490fa0511 100644
--- a/drivers/char/nwbutton.c
+++ b/drivers/char/nwbutton.c
@@ -168,7 +168,10 @@ static irqreturn_t button_handler (int irq, void *dev_id)
 static int button_read (struct file *filp, char __user *buffer,
                         size_t count, loff_t *ppos)
 {
-        interruptible_sleep_on (&button_wait_queue);
+        DEFINE_WAIT(wait);
+        prepare_to_wait(&button_wait_queue, &wait, TASK_INTERRUPTIBLE);
+        schedule();
+        finish_wait(&button_wait_queue, &wait);
         return (copy_to_user (buffer, &button_output_buffer, bcount))
                  ? -EFAULT : bcount;
 }
diff --git a/drivers/char/ttyprintk.c b/drivers/char/ttyprintk.c
index d5d2e4a985aa..daea84c41743 100644
--- a/drivers/char/ttyprintk.c
+++ b/drivers/char/ttyprintk.c
@@ -216,4 +216,4 @@ error:
         ttyprintk_driver = NULL;
         return ret;
 }
-module_init(ttyprintk_init);
+device_initcall(ttyprintk_init);
diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
index f1d54a3985bd..bdb5a00f1dfa 100644
--- a/drivers/extcon/Kconfig
+++ b/drivers/extcon/Kconfig
@@ -31,6 +31,16 @@ config EXTCON_ADC_JACK
         help
           Say Y here to enable extcon device driver based on ADC values.
 
+config EXTCON_MAX14577
+        tristate "MAX14577 EXTCON Support"
+        depends on MFD_MAX14577
+        select IRQ_DOMAIN
+        select REGMAP_I2C
+        help
+          If you say yes here you get support for the MUIC device of
+          Maxim MAX14577 PMIC. The MAX14577 MUIC is a USB port accessory
+          detector and switch.
+
 config EXTCON_MAX77693
         tristate "MAX77693 EXTCON Support"
         depends on MFD_MAX77693 && INPUT
diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
index 759fdae46f95..43eccc0e3448 100644
--- a/drivers/extcon/Makefile
+++ b/drivers/extcon/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_OF_EXTCON)		+= of_extcon.o
 obj-$(CONFIG_EXTCON)            += extcon-class.o
 obj-$(CONFIG_EXTCON_GPIO)       += extcon-gpio.o
 obj-$(CONFIG_EXTCON_ADC_JACK)   += extcon-adc-jack.o
+obj-$(CONFIG_EXTCON_MAX14577)   += extcon-max14577.o
 obj-$(CONFIG_EXTCON_MAX77693)   += extcon-max77693.o
 obj-$(CONFIG_EXTCON_MAX8997)    += extcon-max8997.o
 obj-$(CONFIG_EXTCON_ARIZONA)    += extcon-arizona.o
diff --git a/drivers/extcon/extcon-arizona.c b/drivers/extcon/extcon-arizona.c
index a287cece0593..c20602f601ee 100644
--- a/drivers/extcon/extcon-arizona.c
+++ b/drivers/extcon/extcon-arizona.c
@@ -44,6 +44,15 @@
 #define HPDET_DEBOUNCE 500
 #define DEFAULT_MICD_TIMEOUT 2000
 
+#define MICD_LVL_1_TO_7 (ARIZONA_MICD_LVL_1 | ARIZONA_MICD_LVL_2 | \
+                         ARIZONA_MICD_LVL_3 | ARIZONA_MICD_LVL_4 | \
+                         ARIZONA_MICD_LVL_5 | ARIZONA_MICD_LVL_6 | \
+                         ARIZONA_MICD_LVL_7)
+
+#define MICD_LVL_0_TO_7 (ARIZONA_MICD_LVL_0 | MICD_LVL_1_TO_7)
+
+#define MICD_LVL_0_TO_8 (MICD_LVL_0_TO_7 | ARIZONA_MICD_LVL_8)
+
 struct arizona_extcon_info {
         struct device *dev;
         struct arizona *arizona;
@@ -426,26 +435,15 @@ static int arizona_hpdet_read(struct arizona_extcon_info *info)
                 }
 
                 val &= ARIZONA_HP_LVL_B_MASK;
+                /* Convert to ohms, the value is in 0.5 ohm increments */
+                val /= 2;
 
                 regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1,
                             &range);
                 range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK)
                            >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT;
 
-                /* Skip up or down a range? */
-                if (range && (val < arizona_hpdet_c_ranges[range].min)) {
-                        range--;
-                        dev_dbg(arizona->dev, "Moving to HPDET range %d-%d\n",
-                                arizona_hpdet_c_ranges[range].min,
-                                arizona_hpdet_c_ranges[range].max);
-                        regmap_update_bits(arizona->regmap,
-                                           ARIZONA_HEADPHONE_DETECT_1,
-                                           ARIZONA_HP_IMPEDANCE_RANGE_MASK,
-                                           range <<
-                                           ARIZONA_HP_IMPEDANCE_RANGE_SHIFT);
-                        return -EAGAIN;
-                }
-
+                /* Skip up a range, or report? */
                 if (range < ARRAY_SIZE(arizona_hpdet_c_ranges) - 1 &&
                     (val >= arizona_hpdet_c_ranges[range].max)) {
                         range++;
@@ -459,6 +457,12 @@ static int arizona_hpdet_read(struct arizona_extcon_info *info)
                                            ARIZONA_HP_IMPEDANCE_RANGE_SHIFT);
                         return -EAGAIN;
                 }
+
+                if (range && (val < arizona_hpdet_c_ranges[range].min)) {
+                        dev_dbg(arizona->dev, "Reporting range boundary %d\n",
+                                arizona_hpdet_c_ranges[range].min);
+                        val = arizona_hpdet_c_ranges[range].min;
+                }
         }
 
         dev_dbg(arizona->dev, "HP impedance %d ohms\n", val);
@@ -594,9 +598,15 @@ static irqreturn_t arizona_hpdet_irq(int irq, void *data)
                 dev_err(arizona->dev, "Failed to report HP/line: %d\n",
                         ret);
 
+done:
+        /* Reset back to starting range */
+        regmap_update_bits(arizona->regmap,
+                           ARIZONA_HEADPHONE_DETECT_1,
+                           ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL,
+                           0);
+
         arizona_extcon_do_magic(info, 0);
 
-done:
         if (id_gpio)
                 gpio_set_value_cansleep(id_gpio, 0);
 
@@ -765,7 +775,20 @@ static void arizona_micd_detect(struct work_struct *work)
 
         mutex_lock(&info->lock);
 
-        for (i = 0; i < 10 && !(val & 0x7fc); i++) {
+        /* If the cable was removed while measuring ignore the result */
+        ret = extcon_get_cable_state_(&info->edev, ARIZONA_CABLE_MECHANICAL);
+        if (ret < 0) {
+                dev_err(arizona->dev, "Failed to check cable state: %d\n",
+                                ret);
+                mutex_unlock(&info->lock);
+                return;
+        } else if (!ret) {
+                dev_dbg(arizona->dev, "Ignoring MICDET for removed cable\n");
+                mutex_unlock(&info->lock);
+                return;
+        }
+
+        for (i = 0; i < 10 && !(val & MICD_LVL_0_TO_8); i++) {
                 ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_3, &val);
                 if (ret != 0) {
                         dev_err(arizona->dev,
@@ -784,7 +807,7 @@ static void arizona_micd_detect(struct work_struct *work)
                 }
         }
 
-        if (i == 10 && !(val & 0x7fc)) {
+        if (i == 10 && !(val & MICD_LVL_0_TO_8)) {
                 dev_err(arizona->dev, "Failed to get valid MICDET value\n");
                 mutex_unlock(&info->lock);
                 return;
@@ -798,7 +821,7 @@ static void arizona_micd_detect(struct work_struct *work)
         }
 
         /* If we got a high impedence we should have a headset, report it. */
-        if (info->detecting && (val & 0x400)) {
+        if (info->detecting && (val & ARIZONA_MICD_LVL_8)) {
                 arizona_identify_headphone(info);
 
                 ret = extcon_update_state(&info->edev,
@@ -827,7 +850,7 @@ static void arizona_micd_detect(struct work_struct *work)
          * plain headphones.  If both polarities report a low
          * impedence then give up and report headphones.
          */
-        if (info->detecting && (val & 0x3f8)) {
+        if (info->detecting && (val & MICD_LVL_1_TO_7)) {
                 if (info->jack_flips >= info->micd_num_modes * 10) {
                         dev_dbg(arizona->dev, "Detected HP/line\n");
                         arizona_identify_headphone(info);
@@ -851,7 +874,7 @@ static void arizona_micd_detect(struct work_struct *work)
          * If we're still detecting and we detect a short then we've
          * got a headphone.  Otherwise it's a button press.
          */
-        if (val & 0x3fc) {
+        if (val & MICD_LVL_0_TO_7) {
                 if (info->mic) {
                         dev_dbg(arizona->dev, "Mic button detected\n");
 
@@ -1126,6 +1149,16 @@ static int arizona_extcon_probe(struct platform_device *pdev)
                         break;
                 }
                 break;
+        case WM5110:
+                switch (arizona->rev) {
+                case 0 ... 2:
+                        break;
+                default:
+                        info->micd_clamp = true;
+                        info->hpdet_ip = 2;
+                        break;
+                }
+                break;
         default:
                 break;
         }
diff --git a/drivers/extcon/extcon-gpio.c b/drivers/extcon/extcon-gpio.c
index 7e0dff58e494..a63a6b21c9ad 100644
--- a/drivers/extcon/extcon-gpio.c
+++ b/drivers/extcon/extcon-gpio.c
@@ -40,6 +40,7 @@ struct gpio_extcon_data {
         int irq;
         struct delayed_work work;
         unsigned long debounce_jiffies;
+        bool check_on_resume;
 };
 
 static void gpio_extcon_work(struct work_struct *work)
@@ -103,8 +104,15 @@ static int gpio_extcon_probe(struct platform_device *pdev)
         extcon_data->gpio_active_low = pdata->gpio_active_low;
         extcon_data->state_on = pdata->state_on;
         extcon_data->state_off = pdata->state_off;
+        extcon_data->check_on_resume = pdata->check_on_resume;
         if (pdata->state_on && pdata->state_off)
                 extcon_data->edev.print_state = extcon_gpio_print_state;
+
+        ret = devm_gpio_request_one(&pdev->dev, extcon_data->gpio, GPIOF_DIR_IN,
+                                    pdev->name);
+        if (ret < 0)
+                return ret;
+
         if (pdata->debounce) {
                 ret = gpio_set_debounce(extcon_data->gpio,
                                         pdata->debounce * 1000);
@@ -117,11 +125,6 @@ static int gpio_extcon_probe(struct platform_device *pdev)
         if (ret < 0)
                 return ret;
 
-        ret = devm_gpio_request_one(&pdev->dev, extcon_data->gpio, GPIOF_DIR_IN,
-                                    pdev->name);
-        if (ret < 0)
-                goto err;
-
         INIT_DELAYED_WORK(&extcon_data->work, gpio_extcon_work);
 
         extcon_data->irq = gpio_to_irq(extcon_data->gpio);
@@ -159,12 +162,31 @@ static int gpio_extcon_remove(struct platform_device *pdev)
         return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int gpio_extcon_resume(struct device *dev)
+{
+        struct gpio_extcon_data *extcon_data;
+
+        extcon_data = dev_get_drvdata(dev);
+        if (extcon_data->check_on_resume)
+                queue_delayed_work(system_power_efficient_wq,
+                        &extcon_data->work, extcon_data->debounce_jiffies);
+
+        return 0;
+}
+#endif
+
+static const struct dev_pm_ops gpio_extcon_pm_ops = {
+        SET_SYSTEM_SLEEP_PM_OPS(NULL, gpio_extcon_resume)
+};
+
 static struct platform_driver gpio_extcon_driver = {
         .probe          = gpio_extcon_probe,
         .remove         = gpio_extcon_remove,
         .driver         = {
                 .name   = "extcon-gpio",
                 .owner  = THIS_MODULE,
+                .pm     = &gpio_extcon_pm_ops,
         },
 };
 
diff --git a/drivers/extcon/extcon-max14577.c b/drivers/extcon/extcon-max14577.c
new file mode 100644
index 000000000000..3846941801b8
--- /dev/null
+++ b/drivers/extcon/extcon-max14577.c
@@ -0,0 +1,752 @@
+/*
+ * extcon-max14577.c - MAX14577 extcon driver to support MAX14577 MUIC
+ *
+ * Copyright (C) 2013 Samsung Electrnoics
+ * Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/max14577.h>
+#include <linux/mfd/max14577-private.h>
+#include <linux/extcon.h>
+
+#define DEV_NAME                        "max14577-muic"
+#define DELAY_MS_DEFAULT                17000           /* unit: millisecond */
+
+enum max14577_muic_adc_debounce_time {
+        ADC_DEBOUNCE_TIME_5MS = 0,
+        ADC_DEBOUNCE_TIME_10MS,
+        ADC_DEBOUNCE_TIME_25MS,
+        ADC_DEBOUNCE_TIME_38_62MS,
+};
+
+enum max14577_muic_status {
+        MAX14577_MUIC_STATUS1 = 0,
+        MAX14577_MUIC_STATUS2 = 1,
+        MAX14577_MUIC_STATUS_END,
+};
+
+struct max14577_muic_info {
+        struct device *dev;
+        struct max14577 *max14577;
+        struct extcon_dev *edev;
+        int prev_cable_type;
+        int prev_chg_type;
+        u8 status[MAX14577_MUIC_STATUS_END];
+
+        bool irq_adc;
+        bool irq_chg;
+        struct work_struct irq_work;
+        struct mutex mutex;
+
+        /*
+         * Use delayed workqueue to detect cable state and then
+         * notify cable state to notifiee/platform through uevent.
+         * After completing the booting of platform, the extcon provider
+         * driver should notify cable state to upper layer.
+         */
+        struct delayed_work wq_detcable;
+
+        /*
+         * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
+         * h/w path of COMP2/COMN1 on CONTROL1 register.
+         */
+        int path_usb;
+        int path_uart;
+};
+
+enum max14577_muic_cable_group {
+        MAX14577_CABLE_GROUP_ADC = 0,
+        MAX14577_CABLE_GROUP_CHG,
+};
+
+/**
+ * struct max14577_muic_irq
+ * @irq: the index of irq list of MUIC device.
+ * @name: the name of irq.
+ * @virq: the virtual irq to use irq domain
+ */
+struct max14577_muic_irq {
+        unsigned int irq;
+        const char *name;
+        unsigned int virq;
+};
+
+static struct max14577_muic_irq muic_irqs[] = {
+        { MAX14577_IRQ_INT1_ADC,        "muic-ADC" },
+        { MAX14577_IRQ_INT1_ADCLOW,     "muic-ADCLOW" },
+        { MAX14577_IRQ_INT1_ADCERR,     "muic-ADCError" },
+        { MAX14577_IRQ_INT2_CHGTYP,     "muic-CHGTYP" },
+        { MAX14577_IRQ_INT2_CHGDETRUN,  "muic-CHGDETRUN" },
+        { MAX14577_IRQ_INT2_DCDTMR,     "muic-DCDTMR" },
+        { MAX14577_IRQ_INT2_DBCHG,      "muic-DBCHG" },
+        { MAX14577_IRQ_INT2_VBVOLT,     "muic-VBVOLT" },
+};
+
+/* Define supported accessory type */
+enum max14577_muic_acc_type {
+        MAX14577_MUIC_ADC_GROUND = 0x0,
+        MAX14577_MUIC_ADC_SEND_END_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S1_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S2_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S3_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S4_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S5_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S6_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S7_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S8_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S9_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S10_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S11_BUTTON,
+        MAX14577_MUIC_ADC_REMOTE_S12_BUTTON,
+        MAX14577_MUIC_ADC_RESERVED_ACC_1,
+        MAX14577_MUIC_ADC_RESERVED_ACC_2,
+        MAX14577_MUIC_ADC_RESERVED_ACC_3,
+        MAX14577_MUIC_ADC_RESERVED_ACC_4,
+        MAX14577_MUIC_ADC_RESERVED_ACC_5,
+        MAX14577_MUIC_ADC_AUDIO_DEVICE_TYPE2,
+        MAX14577_MUIC_ADC_PHONE_POWERED_DEV,
+        MAX14577_MUIC_ADC_TTY_CONVERTER,
+        MAX14577_MUIC_ADC_UART_CABLE,
+        MAX14577_MUIC_ADC_CEA936A_TYPE1_CHG,
+        MAX14577_MUIC_ADC_FACTORY_MODE_USB_OFF,
+        MAX14577_MUIC_ADC_FACTORY_MODE_USB_ON,
+        MAX14577_MUIC_ADC_AV_CABLE_NOLOAD,
+        MAX14577_MUIC_ADC_CEA936A_TYPE2_CHG,
+        MAX14577_MUIC_ADC_FACTORY_MODE_UART_OFF,
+        MAX14577_MUIC_ADC_FACTORY_MODE_UART_ON,
+        MAX14577_MUIC_ADC_AUDIO_DEVICE_TYPE1, /* with Remote and Simple Ctrl */
+        MAX14577_MUIC_ADC_OPEN,
+};
+
+/* max14577 MUIC device support below list of accessories(external connector) */
+enum {
+        EXTCON_CABLE_USB = 0,
+        EXTCON_CABLE_TA,
+        EXTCON_CABLE_FAST_CHARGER,
+        EXTCON_CABLE_SLOW_CHARGER,
+        EXTCON_CABLE_CHARGE_DOWNSTREAM,
+        EXTCON_CABLE_JIG_USB_ON,
+        EXTCON_CABLE_JIG_USB_OFF,
+        EXTCON_CABLE_JIG_UART_OFF,
+        EXTCON_CABLE_JIG_UART_ON,
+
+        _EXTCON_CABLE_NUM,
+};
+
+static const char *max14577_extcon_cable[] = {
+        [EXTCON_CABLE_USB]                      = "USB",
+        [EXTCON_CABLE_TA]                       = "TA",
+        [EXTCON_CABLE_FAST_CHARGER]             = "Fast-charger",
+        [EXTCON_CABLE_SLOW_CHARGER]             = "Slow-charger",
+        [EXTCON_CABLE_CHARGE_DOWNSTREAM]        = "Charge-downstream",
+        [EXTCON_CABLE_JIG_USB_ON]               = "JIG-USB-ON",
+        [EXTCON_CABLE_JIG_USB_OFF]              = "JIG-USB-OFF",
+        [EXTCON_CABLE_JIG_UART_OFF]             = "JIG-UART-OFF",
+        [EXTCON_CABLE_JIG_UART_ON]              = "JIG-UART-ON",
+
+        NULL,
+};
+
+/*
+ * max14577_muic_set_debounce_time - Set the debounce time of ADC
+ * @info: the instance including private data of max14577 MUIC
+ * @time: the debounce time of ADC
+ */
+static int max14577_muic_set_debounce_time(struct max14577_muic_info *info,
+                enum max14577_muic_adc_debounce_time time)
+{
+        u8 ret;
+
+        switch (time) {
+        case ADC_DEBOUNCE_TIME_5MS:
+        case ADC_DEBOUNCE_TIME_10MS:
+        case ADC_DEBOUNCE_TIME_25MS:
+        case ADC_DEBOUNCE_TIME_38_62MS:
+                ret = max14577_update_reg(info->max14577->regmap,
+                                          MAX14577_MUIC_REG_CONTROL3,
+                                          CTRL3_ADCDBSET_MASK,
+                                          time << CTRL3_ADCDBSET_SHIFT);
+                if (ret) {
+                        dev_err(info->dev, "failed to set ADC debounce time\n");
+                        return ret;
+                }
+                break;
+        default:
+                dev_err(info->dev, "invalid ADC debounce time\n");
+                return -EINVAL;
+        }
+
+        return 0;
+};
+
+/*
+ * max14577_muic_set_path - Set hardware line according to attached cable
+ * @info: the instance including private data of max14577 MUIC
+ * @value: the path according to attached cable
+ * @attached: the state of cable (true:attached, false:detached)
+ *
+ * The max14577 MUIC device share outside H/W line among a varity of cables
+ * so, this function set internal path of H/W line according to the type of
+ * attached cable.
+ */
+static int max14577_muic_set_path(struct max14577_muic_info *info,
+                u8 val, bool attached)
+{
+        int ret = 0;
+        u8 ctrl1, ctrl2 = 0;
+
+        /* Set open state to path before changing hw path */
+        ret = max14577_update_reg(info->max14577->regmap,
+                                MAX14577_MUIC_REG_CONTROL1,
+                                CLEAR_IDBEN_MICEN_MASK, CTRL1_SW_OPEN);
+        if (ret < 0) {
+                dev_err(info->dev, "failed to update MUIC register\n");
+                return ret;
+        }
+
+        if (attached)
+                ctrl1 = val;
+        else
+                ctrl1 = CTRL1_SW_OPEN;
+
+        ret = max14577_update_reg(info->max14577->regmap,
+                                MAX14577_MUIC_REG_CONTROL1,
+                                CLEAR_IDBEN_MICEN_MASK, ctrl1);
+        if (ret < 0) {
+                dev_err(info->dev, "failed to update MUIC register\n");
+                return ret;
+        }
+
+        if (attached)
+                ctrl2 |= CTRL2_CPEN_MASK;       /* LowPwr=0, CPEn=1 */
+        else
+                ctrl2 |= CTRL2_LOWPWR_MASK;     /* LowPwr=1, CPEn=0 */
+
+        ret = max14577_update_reg(info->max14577->regmap,
+                        MAX14577_REG_CONTROL2,
+                        CTRL2_LOWPWR_MASK | CTRL2_CPEN_MASK, ctrl2);
+        if (ret < 0) {
+                dev_err(info->dev, "failed to update MUIC register\n");
+                return ret;
+        }
+
+        dev_dbg(info->dev,
+                "CONTROL1 : 0x%02x, CONTROL2 : 0x%02x, state : %s\n",
+                ctrl1, ctrl2, attached ? "attached" : "detached");
+
+        return 0;
+}
+
+/*
+ * max14577_muic_get_cable_type - Return cable type and check cable state
+ * @info: the instance including private data of max14577 MUIC
+ * @group: the path according to attached cable
+ * @attached: store cable state and return
+ *
+ * This function check the cable state either attached or detached,
+ * and then divide precise type of cable according to cable group.
+ *      - max14577_CABLE_GROUP_ADC
+ *      - max14577_CABLE_GROUP_CHG
+ */
+static int max14577_muic_get_cable_type(struct max14577_muic_info *info,
+                enum max14577_muic_cable_group group, bool *attached)
+{
+        int cable_type = 0;
+        int adc;
+        int chg_type;
+
+        switch (group) {
+        case MAX14577_CABLE_GROUP_ADC:
+                /*
+                 * Read ADC value to check cable type and decide cable state
+                 * according to cable type
+                 */
+                adc = info->status[MAX14577_MUIC_STATUS1] & STATUS1_ADC_MASK;
+                adc >>= STATUS1_ADC_SHIFT;
+
+                /*
+                 * Check current cable state/cable type and store cable type
+                 * (info->prev_cable_type) for handling cable when cable is
+                 * detached.
+                 */
+                if (adc == MAX14577_MUIC_ADC_OPEN) {
+                        *attached = false;
+
+                        cable_type = info->prev_cable_type;
+                        info->prev_cable_type = MAX14577_MUIC_ADC_OPEN;
+                } else {
+                        *attached = true;
+
+                        cable_type = info->prev_cable_type = adc;
+                }
+                break;
+        case MAX14577_CABLE_GROUP_CHG:
+                /*
+                 * Read charger type to check cable type and decide cable state
+                 * according to type of charger cable.
+                 */
+                chg_type = info->status[MAX14577_MUIC_STATUS2] &
+                        STATUS2_CHGTYP_MASK;
+                chg_type >>= STATUS2_CHGTYP_SHIFT;
+
+                if (chg_type == MAX14577_CHARGER_TYPE_NONE) {
+                        *attached = false;
+
+                        cable_type = info->prev_chg_type;
+                        info->prev_chg_type = MAX14577_CHARGER_TYPE_NONE;
+                } else {
+                        *attached = true;
+
+                        /*
+                         * Check current cable state/cable type and store cable
+                         * type(info->prev_chg_type) for handling cable when
+                         * charger cable is detached.
+                         */
+                        cable_type = info->prev_chg_type = chg_type;
+                }
+
+                break;
+        default:
+                dev_err(info->dev, "Unknown cable group (%d)\n", group);
+                cable_type = -EINVAL;
+                break;
+        }
+
+        return cable_type;
+}
+
+static int max14577_muic_jig_handler(struct max14577_muic_info *info,
+                int cable_type, bool attached)
+{
+        char cable_name[32];
+        int ret = 0;
+        u8 path = CTRL1_SW_OPEN;
+
+        dev_dbg(info->dev,
+                "external connector is %s (adc:0x%02x)\n",
+                attached ? "attached" : "detached", cable_type);
+
+        switch (cable_type) {
+        case MAX14577_MUIC_ADC_FACTORY_MODE_USB_OFF:    /* ADC_JIG_USB_OFF */
+                /* PATH:AP_USB */
+                strcpy(cable_name, "JIG-USB-OFF");
+                path = CTRL1_SW_USB;
+                break;
+        case MAX14577_MUIC_ADC_FACTORY_MODE_USB_ON:     /* ADC_JIG_USB_ON */
+                /* PATH:AP_USB */
+                strcpy(cable_name, "JIG-USB-ON");
+                path = CTRL1_SW_USB;
+                break;
+        case MAX14577_MUIC_ADC_FACTORY_MODE_UART_OFF:   /* ADC_JIG_UART_OFF */
+                /* PATH:AP_UART */
+                strcpy(cable_name, "JIG-UART-OFF");
+                path = CTRL1_SW_UART;
+                break;
+        default:
+                dev_err(info->dev, "failed to detect %s jig cable\n",
+                        attached ? "attached" : "detached");
+                return -EINVAL;
+        }
+
+        ret = max14577_muic_set_path(info, path, attached);
+        if (ret < 0)
+                return ret;
+
+        extcon_set_cable_state(info->edev, cable_name, attached);
+
+        return 0;
+}
+
+static int max14577_muic_adc_handler(struct max14577_muic_info *info)
+{
+        int cable_type;
+        bool attached;
+        int ret = 0;
+
+        /* Check accessory state which is either detached or attached */
+        cable_type = max14577_muic_get_cable_type(info,
+                                MAX14577_CABLE_GROUP_ADC, &attached);
+
+        dev_dbg(info->dev,
+                "external connector is %s (adc:0x%02x, prev_adc:0x%x)\n",
+                attached ? "attached" : "detached", cable_type,
+                info->prev_cable_type);
+
+        switch (cable_type) {
+        case MAX14577_MUIC_ADC_FACTORY_MODE_USB_OFF:
+        case MAX14577_MUIC_ADC_FACTORY_MODE_USB_ON:
+        case MAX14577_MUIC_ADC_FACTORY_MODE_UART_OFF:
+                /* JIG */
+                ret = max14577_muic_jig_handler(info, cable_type, attached);
+                if (ret < 0)
+                        return ret;
+                break;
+        case MAX14577_MUIC_ADC_GROUND:
+        case MAX14577_MUIC_ADC_SEND_END_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S1_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S2_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S3_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S4_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S5_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S6_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S7_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S8_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S9_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S10_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S11_BUTTON:
+        case MAX14577_MUIC_ADC_REMOTE_S12_BUTTON:
+        case MAX14577_MUIC_ADC_RESERVED_ACC_1:
+        case MAX14577_MUIC_ADC_RESERVED_ACC_2:
+        case MAX14577_MUIC_ADC_RESERVED_ACC_3:
+        case MAX14577_MUIC_ADC_RESERVED_ACC_4:
+        case MAX14577_MUIC_ADC_RESERVED_ACC_5:
+        case MAX14577_MUIC_ADC_AUDIO_DEVICE_TYPE2:
+        case MAX14577_MUIC_ADC_PHONE_POWERED_DEV:
+        case MAX14577_MUIC_ADC_TTY_CONVERTER:
+        case MAX14577_MUIC_ADC_UART_CABLE:
+        case MAX14577_MUIC_ADC_CEA936A_TYPE1_CHG:
+        case MAX14577_MUIC_ADC_AV_CABLE_NOLOAD:
+        case MAX14577_MUIC_ADC_CEA936A_TYPE2_CHG:
+        case MAX14577_MUIC_ADC_FACTORY_MODE_UART_ON:
+        case MAX14577_MUIC_ADC_AUDIO_DEVICE_TYPE1:
+                /*
+                 * This accessory isn't used in general case if it is specially
+                 * needed to detect additional accessory, should implement
+                 * proper operation when this accessory is attached/detached.
+                 */
+                dev_info(info->dev,
+                        "accessory is %s but it isn't used (adc:0x%x)\n",
+                        attached ? "attached" : "detached", cable_type);
+                return -EAGAIN;
+        default:
+                dev_err(info->dev,
+                        "failed to detect %s accessory (adc:0x%x)\n",
+                        attached ? "attached" : "detached", cable_type);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int max14577_muic_chg_handler(struct max14577_muic_info *info)
+{
+        int chg_type;
+        bool attached;
+        int ret = 0;
+
+        chg_type = max14577_muic_get_cable_type(info,
+                                MAX14577_CABLE_GROUP_CHG, &attached);
+
+        dev_dbg(info->dev,
+                "external connector is %s(chg_type:0x%x, prev_chg_type:0x%x)\n",
+                        attached ? "attached" : "detached",
+                        chg_type, info->prev_chg_type);
+
+        switch (chg_type) {
+        case MAX14577_CHARGER_TYPE_USB:
+                /* PATH:AP_USB */
+                ret = max14577_muic_set_path(info, info->path_usb, attached);
+                if (ret < 0)
+                        return ret;
+
+                extcon_set_cable_state(info->edev, "USB", attached);
+                break;
+        case MAX14577_CHARGER_TYPE_DEDICATED_CHG:
+                extcon_set_cable_state(info->edev, "TA", attached);
+                break;
+        case MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT:
+                extcon_set_cable_state(info->edev,
+                                "Charge-downstream", attached);
+                break;
+        case MAX14577_CHARGER_TYPE_SPECIAL_500MA:
+                extcon_set_cable_state(info->edev, "Slow-charger", attached);
+                break;
+        case MAX14577_CHARGER_TYPE_SPECIAL_1A:
+                extcon_set_cable_state(info->edev, "Fast-charger", attached);
+                break;
+        case MAX14577_CHARGER_TYPE_NONE:
+        case MAX14577_CHARGER_TYPE_DEAD_BATTERY:
+                break;
+        default:
+                dev_err(info->dev,
+                        "failed to detect %s accessory (chg_type:0x%x)\n",
+                        attached ? "attached" : "detached", chg_type);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static void max14577_muic_irq_work(struct work_struct *work)
+{
+        struct max14577_muic_info *info = container_of(work,
+                        struct max14577_muic_info, irq_work);
+        int ret = 0;
+
+        if (!info->edev)
+                return;
+
+        mutex_lock(&info->mutex);
+
+        ret = max14577_bulk_read(info->max14577->regmap,
+                        MAX14577_MUIC_REG_STATUS1, info->status, 2);
+        if (ret) {
+                dev_err(info->dev, "failed to read MUIC register\n");
+                mutex_unlock(&info->mutex);
+                return;
+        }
+
+        if (info->irq_adc) {
+                ret = max14577_muic_adc_handler(info);
+                info->irq_adc = false;
+        }
+        if (info->irq_chg) {
+                ret = max14577_muic_chg_handler(info);
+                info->irq_chg = false;
+        }
+
+        if (ret < 0)
+                dev_err(info->dev, "failed to handle MUIC interrupt\n");
+
+        mutex_unlock(&info->mutex);
+
+        return;
+}
+
+static irqreturn_t max14577_muic_irq_handler(int irq, void *data)
+{
+        struct max14577_muic_info *info = data;
+        int i, irq_type = -1;
+
+        /*
+         * We may be called multiple times for different nested IRQ-s.
+         * Including changes in INT1_ADC and INT2_CGHTYP at once.
+         * However we only need to know whether it was ADC, charger
+         * or both interrupts so decode IRQ and turn on proper flags.
+         */
+        for (i = 0; i < ARRAY_SIZE(muic_irqs); i++)
+                if (irq == muic_irqs[i].virq)
+                        irq_type = muic_irqs[i].irq;
+
+        switch (irq_type) {
+        case MAX14577_IRQ_INT1_ADC:
+        case MAX14577_IRQ_INT1_ADCLOW:
+        case MAX14577_IRQ_INT1_ADCERR:
+                /* Handle all of accessory except for
+                   type of charger accessory */
+                info->irq_adc = true;
+                break;
+        case MAX14577_IRQ_INT2_CHGTYP:
+        case MAX14577_IRQ_INT2_CHGDETRUN:
+        case MAX14577_IRQ_INT2_DCDTMR:
+        case MAX14577_IRQ_INT2_DBCHG:
+        case MAX14577_IRQ_INT2_VBVOLT:
+                /* Handle charger accessory */
+                info->irq_chg = true;
+                break;
+        default:
+                dev_err(info->dev, "muic interrupt: irq %d occurred, skipped\n",
+                                irq_type);
+                return IRQ_HANDLED;
+        }
+        schedule_work(&info->irq_work);
+
+        return IRQ_HANDLED;
+}
+
+static int max14577_muic_detect_accessory(struct max14577_muic_info *info)
+{
+        int ret = 0;
+        int adc;
+        int chg_type;
+        bool attached;
+
+        mutex_lock(&info->mutex);
+
+        /* Read STATUSx register to detect accessory */
+        ret = max14577_bulk_read(info->max14577->regmap,
+                        MAX14577_MUIC_REG_STATUS1, info->status, 2);
+        if (ret) {
+                dev_err(info->dev, "failed to read MUIC register\n");
+                mutex_unlock(&info->mutex);
+                return ret;
+        }
+
+        adc = max14577_muic_get_cable_type(info, MAX14577_CABLE_GROUP_ADC,
+                                        &attached);
+        if (attached && adc != MAX14577_MUIC_ADC_OPEN) {
+                ret = max14577_muic_adc_handler(info);
+                if (ret < 0) {
+                        dev_err(info->dev, "Cannot detect accessory\n");
+                        mutex_unlock(&info->mutex);
+                        return ret;
+                }
+        }
+
+        chg_type = max14577_muic_get_cable_type(info, MAX14577_CABLE_GROUP_CHG,
+                                        &attached);
+        if (attached && chg_type != MAX14577_CHARGER_TYPE_NONE) {
+                ret = max14577_muic_chg_handler(info);
+                if (ret < 0) {
+                        dev_err(info->dev, "Cannot detect charger accessory\n");
+                        mutex_unlock(&info->mutex);
+                        return ret;
+                }
+        }
+
+        mutex_unlock(&info->mutex);
+
+        return 0;
+}
+
+static void max14577_muic_detect_cable_wq(struct work_struct *work)
+{
+        struct max14577_muic_info *info = container_of(to_delayed_work(work),
+                                struct max14577_muic_info, wq_detcable);
+
+        max14577_muic_detect_accessory(info);
+}
+
+static int max14577_muic_probe(struct platform_device *pdev)
+{
+        struct max14577 *max14577 = dev_get_drvdata(pdev->dev.parent);
+        struct max14577_muic_info *info;
+        int delay_jiffies;
+        int ret;
+        int i;
+        u8 id;
+
+        info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
+        if (!info) {
+                dev_err(&pdev->dev, "failed to allocate memory\n");
+                return -ENOMEM;
+        }
+        info->dev = &pdev->dev;
+        info->max14577 = max14577;
+
+        platform_set_drvdata(pdev, info);
+        mutex_init(&info->mutex);
+
+        INIT_WORK(&info->irq_work, max14577_muic_irq_work);
+
+        /* Support irq domain for max14577 MUIC device */
+        for (i = 0; i < ARRAY_SIZE(muic_irqs); i++) {
+                struct max14577_muic_irq *muic_irq = &muic_irqs[i];
+                unsigned int virq = 0;
+
+                virq = regmap_irq_get_virq(max14577->irq_data, muic_irq->irq);
+                if (!virq)
+                        return -EINVAL;
+                muic_irq->virq = virq;
+
+                ret = devm_request_threaded_irq(&pdev->dev, virq, NULL,
+                                max14577_muic_irq_handler,
+                                IRQF_NO_SUSPEND,
+                                muic_irq->name, info);
+                if (ret) {
+                        dev_err(&pdev->dev,
+                                "failed: irq request (IRQ: %d,"
+                                " error :%d)\n",
+                                muic_irq->irq, ret);
+                        return ret;
+                }
+        }
+
+        /* Initialize extcon device */
+        info->edev = devm_kzalloc(&pdev->dev, sizeof(*info->edev), GFP_KERNEL);
+        if (!info->edev) {
+                dev_err(&pdev->dev, "failed to allocate memory for extcon\n");
+                return -ENOMEM;
+        }
+        info->edev->name = DEV_NAME;
+        info->edev->supported_cable = max14577_extcon_cable;
+        ret = extcon_dev_register(info->edev);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register extcon device\n");
+                return ret;
+        }
+
+        /* Default h/w line path */
+        info->path_usb = CTRL1_SW_USB;
+        info->path_uart = CTRL1_SW_UART;
+        delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT);
+
+        /* Set initial path for UART */
+        max14577_muic_set_path(info, info->path_uart, true);
+
+        /* Check revision number of MUIC device*/
+        ret = max14577_read_reg(info->max14577->regmap,
+                        MAX14577_REG_DEVICEID, &id);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "failed to read revision number\n");
+                goto err_extcon;
+        }
+        dev_info(info->dev, "device ID : 0x%x\n", id);
+
+        /* Set ADC debounce time */
+        max14577_muic_set_debounce_time(info, ADC_DEBOUNCE_TIME_25MS);
+
+        /*
+         * Detect accessory after completing the initialization of platform
+         *
+         * - Use delayed workqueue to detect cable state and then
+         * notify cable state to notifiee/platform through uevent.
+         * After completing the booting of platform, the extcon provider
+         * driver should notify cable state to upper layer.
+         */
+        INIT_DELAYED_WORK(&info->wq_detcable, max14577_muic_detect_cable_wq);
+        ret = queue_delayed_work(system_power_efficient_wq, &info->wq_detcable,
+                        delay_jiffies);
+        if (ret < 0) {
+                dev_err(&pdev->dev,
+                        "failed to schedule delayed work for cable detect\n");
+                goto err_extcon;
+        }
+
+        return ret;
+
+err_extcon:
+        extcon_dev_unregister(info->edev);
+        return ret;
+}
+
+static int max14577_muic_remove(struct platform_device *pdev)
+{
+        struct max14577_muic_info *info = platform_get_drvdata(pdev);
+
+        cancel_work_sync(&info->irq_work);
+        extcon_dev_unregister(info->edev);
+
+        return 0;
+}
+
+static struct platform_driver max14577_muic_driver = {
+        .driver         = {
+                .name   = DEV_NAME,
+                .owner  = THIS_MODULE,
+        },
+        .probe          = max14577_muic_probe,
+        .remove         = max14577_muic_remove,
+};
+
+module_platform_driver(max14577_muic_driver);
+
+MODULE_DESCRIPTION("MAXIM 14577 Extcon driver");
+MODULE_AUTHOR("Chanwoo Choi <cw00.choi@samsung.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:extcon-max14577");
diff --git a/drivers/extcon/extcon-palmas.c b/drivers/extcon/extcon-palmas.c
index 6c91976dd823..2aea4bcdd7f3 100644
--- a/drivers/extcon/extcon-palmas.c
+++ b/drivers/extcon/extcon-palmas.c
@@ -78,20 +78,24 @@ static irqreturn_t palmas_vbus_irq_handler(int irq, void *_palmas_usb)
 
 static irqreturn_t palmas_id_irq_handler(int irq, void *_palmas_usb)
 {
-        unsigned int set;
+        unsigned int set, id_src;
         struct palmas_usb *palmas_usb = _palmas_usb;
 
         palmas_read(palmas_usb->palmas, PALMAS_USB_OTG_BASE,
                 PALMAS_USB_ID_INT_LATCH_SET, &set);
+        palmas_read(palmas_usb->palmas, PALMAS_USB_OTG_BASE,
+                PALMAS_USB_ID_INT_SRC, &id_src);
 
-        if (set & PALMAS_USB_ID_INT_SRC_ID_GND) {
+        if ((set & PALMAS_USB_ID_INT_SRC_ID_GND) &&
+                                (id_src & PALMAS_USB_ID_INT_SRC_ID_GND)) {
                 palmas_write(palmas_usb->palmas, PALMAS_USB_OTG_BASE,
                         PALMAS_USB_ID_INT_LATCH_CLR,
                         PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND);
                 palmas_usb->linkstat = PALMAS_USB_STATE_ID;
                 extcon_set_cable_state(&palmas_usb->edev, "USB-HOST", true);
                 dev_info(palmas_usb->dev, "USB-HOST cable is attached\n");
-        } else if (set & PALMAS_USB_ID_INT_SRC_ID_FLOAT) {
+        } else if ((set & PALMAS_USB_ID_INT_SRC_ID_FLOAT) &&
+                                (id_src & PALMAS_USB_ID_INT_SRC_ID_FLOAT)) {
                 palmas_write(palmas_usb->palmas, PALMAS_USB_OTG_BASE,
                         PALMAS_USB_ID_INT_LATCH_CLR,
                         PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT);
@@ -103,6 +107,11 @@ static irqreturn_t palmas_id_irq_handler(int irq, void *_palmas_usb)
                 palmas_usb->linkstat = PALMAS_USB_STATE_DISCONNECT;
                 extcon_set_cable_state(&palmas_usb->edev, "USB-HOST", false);
                 dev_info(palmas_usb->dev, "USB-HOST cable is detached\n");
+        } else if ((palmas_usb->linkstat == PALMAS_USB_STATE_DISCONNECT) &&
+                                (id_src & PALMAS_USB_ID_INT_SRC_ID_GND)) {
+                palmas_usb->linkstat = PALMAS_USB_STATE_ID;
+                extcon_set_cable_state(&palmas_usb->edev, "USB-HOST", true);
+                dev_info(palmas_usb->dev, " USB-HOST cable is attached\n");
         }
 
         return IRQ_HANDLED;
@@ -269,7 +278,9 @@ static const struct dev_pm_ops palmas_pm_ops = {
 
 static struct of_device_id of_palmas_match_tbl[] = {
         { .compatible = "ti,palmas-usb", },
+        { .compatible = "ti,palmas-usb-vid", },
         { .compatible = "ti,twl6035-usb", },
+        { .compatible = "ti,twl6035-usb-vid", },
         { /* end */ }
 };
 
diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c
index f0c5e07c25ec..bcb49502c3bf 100644
--- a/drivers/hv/hv.c
+++ b/drivers/hv/hv.c
@@ -301,7 +301,7 @@ err:
         return -ENOMEM;
 }
 
-void hv_synic_free_cpu(int cpu)
+static void hv_synic_free_cpu(int cpu)
 {
         kfree(hv_context.event_dpc[cpu]);
         if (hv_context.synic_event_page[cpu])
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index a3e291d0df9a..6cb388e8fb7d 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -525,4 +525,5 @@ source "drivers/misc/altera-stapl/Kconfig"
 source "drivers/misc/mei/Kconfig"
 source "drivers/misc/vmw_vmci/Kconfig"
 source "drivers/misc/mic/Kconfig"
+source "drivers/misc/genwqe/Kconfig"
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f45473e68bf7..99b9424ce31d 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_VMWARE_VMCI)	+= vmw_vmci/
 obj-$(CONFIG_LATTICE_ECP3_CONFIG)       += lattice-ecp3-config.o
 obj-$(CONFIG_SRAM)              += sram.o
 obj-y                           += mic/
+obj-$(CONFIG_GENWQE)            += genwqe/
diff --git a/drivers/misc/ad525x_dpot.c b/drivers/misc/ad525x_dpot.c
index 0daadcf1ed7a..d3eee113baeb 100644
--- a/drivers/misc/ad525x_dpot.c
+++ b/drivers/misc/ad525x_dpot.c
@@ -641,7 +641,7 @@ static const struct attribute_group ad525x_group_commands = {
         .attrs = ad525x_attributes_commands,
 };
 
-int ad_dpot_add_files(struct device *dev,
+static int ad_dpot_add_files(struct device *dev,
                 unsigned features, unsigned rdac)
 {
         int err = sysfs_create_file(&dev->kobj,
@@ -666,7 +666,7 @@ int ad_dpot_add_files(struct device *dev,
         return err;
 }
 
-inline void ad_dpot_remove_files(struct device *dev,
+static inline void ad_dpot_remove_files(struct device *dev,
                 unsigned features, unsigned rdac)
 {
         sysfs_remove_file(&dev->kobj,
diff --git a/drivers/misc/bmp085-i2c.c b/drivers/misc/bmp085-i2c.c
index 3abfcecf8424..a7c16295b816 100644
--- a/drivers/misc/bmp085-i2c.c
+++ b/drivers/misc/bmp085-i2c.c
@@ -49,7 +49,7 @@ static int bmp085_i2c_probe(struct i2c_client *client,
                 return err;
         }
 
-        return bmp085_probe(&client->dev, regmap);
+        return bmp085_probe(&client->dev, regmap, client->irq);
 }
 
 static int bmp085_i2c_remove(struct i2c_client *client)
diff --git a/drivers/misc/bmp085-spi.c b/drivers/misc/bmp085-spi.c
index d6a52659cf24..864ecac32373 100644
--- a/drivers/misc/bmp085-spi.c
+++ b/drivers/misc/bmp085-spi.c
@@ -41,7 +41,7 @@ static int bmp085_spi_probe(struct spi_device *client)
                 return err;
         }
 
-        return bmp085_probe(&client->dev, regmap);
+        return bmp085_probe(&client->dev, regmap, client->irq);
 }
 
 static int bmp085_spi_remove(struct spi_device *client)
diff --git a/drivers/misc/bmp085.c b/drivers/misc/bmp085.c
index 2704d885a9b3..820e53d0048f 100644
--- a/drivers/misc/bmp085.c
+++ b/drivers/misc/bmp085.c
@@ -49,9 +49,11 @@
 #include <linux/device.h>
 #include <linux/init.h>
 #include <linux/slab.h>
-#include <linux/delay.h>
 #include <linux/of.h>
 #include "bmp085.h"
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/gpio.h>
 
 #define BMP085_CHIP_ID                  0x55
 #define BMP085_CALIBRATION_DATA_START   0xAA
@@ -84,8 +86,19 @@ struct bmp085_data {
         unsigned long last_temp_measurement;
         u8      chip_id;
         s32     b6; /* calculated temperature correction coefficient */
+        int     irq;
+        struct  completion done;
 };
 
+static irqreturn_t bmp085_eoc_isr(int irq, void *devid)
+{
+        struct bmp085_data *data = devid;
+
+        complete(&data->done);
+
+        return IRQ_HANDLED;
+}
+
 static s32 bmp085_read_calibration_data(struct bmp085_data *data)
 {
         u16 tmp[BMP085_CALIBRATION_DATA_LENGTH];
@@ -116,6 +129,9 @@ static s32 bmp085_update_raw_temperature(struct bmp085_data *data)
         s32 status;
 
         mutex_lock(&data->lock);
+
+        init_completion(&data->done);
+
         status = regmap_write(data->regmap, BMP085_CTRL_REG,
                               BMP085_TEMP_MEASUREMENT);
         if (status < 0) {
@@ -123,7 +139,8 @@ static s32 bmp085_update_raw_temperature(struct bmp085_data *data)
                         "Error while requesting temperature measurement.\n");
                 goto exit;
         }
-        msleep(BMP085_TEMP_CONVERSION_TIME);
+        wait_for_completion_timeout(&data->done, 1 + msecs_to_jiffies(
+                                            BMP085_TEMP_CONVERSION_TIME));
 
         status = regmap_bulk_read(data->regmap, BMP085_CONVERSION_REGISTER_MSB,
                                  &tmp, sizeof(tmp));
@@ -147,6 +164,9 @@ static s32 bmp085_update_raw_pressure(struct bmp085_data *data)
         s32 status;
 
         mutex_lock(&data->lock);
+
+        init_completion(&data->done);
+
         status = regmap_write(data->regmap, BMP085_CTRL_REG,
                         BMP085_PRESSURE_MEASUREMENT +
                         (data->oversampling_setting << 6));
@@ -157,8 +177,8 @@ static s32 bmp085_update_raw_pressure(struct bmp085_data *data)
         }
 
         /* wait for the end of conversion */
-        msleep(2+(3 << data->oversampling_setting));
-
+        wait_for_completion_timeout(&data->done, 1 + msecs_to_jiffies(
+                                        2+(3 << data->oversampling_setting)));
         /* copy data into a u32 (4 bytes), but skip the first byte. */
         status = regmap_bulk_read(data->regmap, BMP085_CONVERSION_REGISTER_MSB,
                                  ((u8 *)&tmp)+1, 3);
@@ -420,7 +440,7 @@ struct regmap_config bmp085_regmap_config = {
 };
 EXPORT_SYMBOL_GPL(bmp085_regmap_config);
 
-int bmp085_probe(struct device *dev, struct regmap *regmap)
+int bmp085_probe(struct device *dev, struct regmap *regmap, int irq)
 {
         struct bmp085_data *data;
         int err = 0;
@@ -434,6 +454,15 @@ int bmp085_probe(struct device *dev, struct regmap *regmap)
         dev_set_drvdata(dev, data);
         data->dev = dev;
         data->regmap = regmap;
+        data->irq = irq;
+
+        if (data->irq > 0) {
+                err = devm_request_irq(dev, data->irq, bmp085_eoc_isr,
+                                              IRQF_TRIGGER_RISING, "bmp085",
+                                              data);
+                if (err < 0)
+                        goto exit_free;
+        }
 
         /* Initialize the BMP085 chip */
         err = bmp085_init_client(data);
diff --git a/drivers/misc/bmp085.h b/drivers/misc/bmp085.h
index 2b8f615bca92..8b8e3b1f5ca5 100644
--- a/drivers/misc/bmp085.h
+++ b/drivers/misc/bmp085.h
@@ -26,7 +26,7 @@
 
 extern struct regmap_config bmp085_regmap_config;
 
-int bmp085_probe(struct device *dev, struct regmap *regmap);
+int bmp085_probe(struct device *dev, struct regmap *regmap, int irq);
 int bmp085_remove(struct device *dev);
 int bmp085_detect(struct device *dev);
 
diff --git a/drivers/misc/eeprom/eeprom_93xx46.c b/drivers/misc/eeprom/eeprom_93xx46.c
index 3a015abb444a..78e55b501c94 100644
--- a/drivers/misc/eeprom/eeprom_93xx46.c
+++ b/drivers/misc/eeprom/eeprom_93xx46.c
@@ -378,7 +378,6 @@ static int eeprom_93xx46_remove(struct spi_device *spi)
                 device_remove_file(&spi->dev, &dev_attr_erase);
 
         sysfs_remove_bin_file(&spi->dev.kobj, &edev->bin);
-        spi_set_drvdata(spi, NULL);
         kfree(edev);
         return 0;
 }
diff --git a/drivers/misc/genwqe/Kconfig b/drivers/misc/genwqe/Kconfig
new file mode 100644
index 000000000000..6069d8cd79d7
--- /dev/null
+++ b/drivers/misc/genwqe/Kconfig
@@ -0,0 +1,13 @@
+#
+# IBM Accelerator Family 'GenWQE'
+#
+
+menuconfig GENWQE
+        tristate "GenWQE PCIe Accelerator"
+        depends on PCI && 64BIT
+        select CRC_ITU_T
+        default n
+        help
+          Enables PCIe card driver for IBM GenWQE accelerators.
+          The user-space interface is described in
+          include/linux/genwqe/genwqe_card.h.
diff --git a/drivers/misc/genwqe/Makefile b/drivers/misc/genwqe/Makefile
new file mode 100644
index 000000000000..98a2b4f0b18b
--- /dev/null
+++ b/drivers/misc/genwqe/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for GenWQE driver
+#
+
+obj-$(CONFIG_GENWQE) := genwqe_card.o
+genwqe_card-objs := card_base.o card_dev.o card_ddcb.o card_sysfs.o \
+        card_debugfs.o card_utils.o
diff --git a/drivers/misc/genwqe/card_base.c b/drivers/misc/genwqe/card_base.c
new file mode 100644
index 000000000000..74d51c9bb858
--- /dev/null
+++ b/drivers/misc/genwqe/card_base.c
@@ -0,0 +1,1205 @@
+/**
+ * IBM Accelerator Family 'GenWQE'
+ *
+ * (C) Copyright IBM Corp. 2013
+ *
+ * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
+ * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
+ * Author: Michael Jung <mijung@de.ibm.com>
+ * Author: Michael Ruettger <michael@ibmra.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Module initialization and PCIe setup. Card health monitoring and
+ * recovery functionality. Character device creation and deletion are
+ * controlled from here.
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/err.h>
+#include <linux/aer.h>
+#include <linux/string.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/notifier.h>
+#include <linux/device.h>
+#include <linux/log2.h>
+#include <linux/genwqe/genwqe_card.h>
+
+#include "card_base.h"
+#include "card_ddcb.h"
+
+MODULE_AUTHOR("Frank Haverkamp <haver@linux.vnet.ibm.com>");
+MODULE_AUTHOR("Michael Ruettger <michael@ibmra.de>");
+MODULE_AUTHOR("Joerg-Stephan Vogt <jsvogt@de.ibm.com>");
+MODULE_AUTHOR("Michal Jung <mijung@de.ibm.com>");
+
+MODULE_DESCRIPTION("GenWQE Card");
+MODULE_VERSION(DRV_VERS_STRING);
+MODULE_LICENSE("GPL");
+
+static char genwqe_driver_name[] = GENWQE_DEVNAME;
+static struct class *class_genwqe;
+static struct dentry *debugfs_genwqe;
+static struct genwqe_dev *genwqe_devices[GENWQE_CARD_NO_MAX];
+
+/* PCI structure for identifying device by PCI vendor and device ID */
+static DEFINE_PCI_DEVICE_TABLE(genwqe_device_table) = {
+        { .vendor      = PCI_VENDOR_ID_IBM,
+          .device      = PCI_DEVICE_GENWQE,
+          .subvendor   = PCI_SUBVENDOR_ID_IBM,
+          .subdevice   = PCI_SUBSYSTEM_ID_GENWQE5,
+          .class       = (PCI_CLASSCODE_GENWQE5 << 8),
+          .class_mask  = ~0,
+          .driver_data = 0 },
+
+        /* Initial SR-IOV bring-up image */
+        { .vendor      = PCI_VENDOR_ID_IBM,
+          .device      = PCI_DEVICE_GENWQE,
+          .subvendor   = PCI_SUBVENDOR_ID_IBM_SRIOV,
+          .subdevice   = PCI_SUBSYSTEM_ID_GENWQE5_SRIOV,
+          .class       = (PCI_CLASSCODE_GENWQE5_SRIOV << 8),
+          .class_mask  = ~0,
+          .driver_data = 0 },
+
+        { .vendor      = PCI_VENDOR_ID_IBM,  /* VF Vendor ID */
+          .device      = 0x0000,  /* VF Device ID */
+          .subvendor   = PCI_SUBVENDOR_ID_IBM_SRIOV,
+          .subdevice   = PCI_SUBSYSTEM_ID_GENWQE5_SRIOV,
+          .class       = (PCI_CLASSCODE_GENWQE5_SRIOV << 8),
+          .class_mask  = ~0,
+          .driver_data = 0 },
+
+        /* Fixed up image */
+        { .vendor      = PCI_VENDOR_ID_IBM,
+          .device      = PCI_DEVICE_GENWQE,
+          .subvendor   = PCI_SUBVENDOR_ID_IBM_SRIOV,
+          .subdevice   = PCI_SUBSYSTEM_ID_GENWQE5,
+          .class       = (PCI_CLASSCODE_GENWQE5_SRIOV << 8),
+          .class_mask  = ~0,
+          .driver_data = 0 },
+
+        { .vendor      = PCI_VENDOR_ID_IBM,  /* VF Vendor ID */
+          .device      = 0x0000,  /* VF Device ID */
+          .subvendor   = PCI_SUBVENDOR_ID_IBM_SRIOV,
+          .subdevice   = PCI_SUBSYSTEM_ID_GENWQE5,
+          .class       = (PCI_CLASSCODE_GENWQE5_SRIOV << 8),
+          .class_mask  = ~0,
+          .driver_data = 0 },
+
+        /* Even one more ... */
+        { .vendor      = PCI_VENDOR_ID_IBM,
+          .device      = PCI_DEVICE_GENWQE,
+          .subvendor   = PCI_SUBVENDOR_ID_IBM,
+          .subdevice   = PCI_SUBSYSTEM_ID_GENWQE5_NEW,
+          .class       = (PCI_CLASSCODE_GENWQE5 << 8),
+          .class_mask  = ~0,
+          .driver_data = 0 },
+
+        { 0, }                  /* 0 terminated list. */
+};
+
+MODULE_DEVICE_TABLE(pci, genwqe_device_table);
+
+/**
+ * genwqe_dev_alloc() - Create and prepare a new card descriptor
+ *
+ * Return: Pointer to card descriptor, or ERR_PTR(err) on error
+ */
+static struct genwqe_dev *genwqe_dev_alloc(void)
+{
+        unsigned int i = 0, j;
+        struct genwqe_dev *cd;
+
+        for (i = 0; i < GENWQE_CARD_NO_MAX; i++) {
+                if (genwqe_devices[i] == NULL)
+                        break;
+        }
+        if (i >= GENWQE_CARD_NO_MAX)
+                return ERR_PTR(-ENODEV);
+
+        cd = kzalloc(sizeof(struct genwqe_dev), GFP_KERNEL);
+        if (!cd)
+                return ERR_PTR(-ENOMEM);
+
+        cd->card_idx = i;
+        cd->class_genwqe = class_genwqe;
+        cd->debugfs_genwqe = debugfs_genwqe;
+
+        init_waitqueue_head(&cd->queue_waitq);
+
+        spin_lock_init(&cd->file_lock);
+        INIT_LIST_HEAD(&cd->file_list);
+
+        cd->card_state = GENWQE_CARD_UNUSED;
+        spin_lock_init(&cd->print_lock);
+
+        cd->ddcb_software_timeout = genwqe_ddcb_software_timeout;
+        cd->kill_timeout = genwqe_kill_timeout;
+
+        for (j = 0; j < GENWQE_MAX_VFS; j++)
+                cd->vf_jobtimeout_msec[j] = genwqe_vf_jobtimeout_msec;
+
+        genwqe_devices[i] = cd;
+        return cd;
+}
+
+static void genwqe_dev_free(struct genwqe_dev *cd)
+{
+        if (!cd)
+                return;
+
+        genwqe_devices[cd->card_idx] = NULL;
+        kfree(cd);
+}
+
+/**
+ * genwqe_bus_reset() - Card recovery
+ *
+ * pci_reset_function() will recover the device and ensure that the
+ * registers are accessible again when it completes with success. If
+ * not, the card will stay dead and registers will be unaccessible
+ * still.
+ */
+static int genwqe_bus_reset(struct genwqe_dev *cd)
+{
+        int bars, rc = 0;
+        struct pci_dev *pci_dev = cd->pci_dev;
+        void __iomem *mmio;
+
+        if (cd->err_inject & GENWQE_INJECT_BUS_RESET_FAILURE)
+                return -EIO;
+
+        mmio = cd->mmio;
+        cd->mmio = NULL;
+        pci_iounmap(pci_dev, mmio);
+
+        bars = pci_select_bars(pci_dev, IORESOURCE_MEM);
+        pci_release_selected_regions(pci_dev, bars);
+
+        /*
+         * Firmware/BIOS might change memory mapping during bus reset.
+         * Settings like enable bus-mastering, ... are backuped and
+         * restored by the pci_reset_function().
+         */
+        dev_dbg(&pci_dev->dev, "[%s] pci_reset function ...\n", __func__);
+        rc = pci_reset_function(pci_dev);
+        if (rc) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: failed reset func (rc %d)\n", __func__, rc);
+                return rc;
+        }
+        dev_dbg(&pci_dev->dev, "[%s] done with rc=%d\n", __func__, rc);
+
+        /*
+         * Here is the right spot to clear the register read
+         * failure. pci_bus_reset() does this job in real systems.
+         */
+        cd->err_inject &= ~(GENWQE_INJECT_HARDWARE_FAILURE |
+                            GENWQE_INJECT_GFIR_FATAL |
+                            GENWQE_INJECT_GFIR_INFO);
+
+        rc = pci_request_selected_regions(pci_dev, bars, genwqe_driver_name);
+        if (rc) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: request bars failed (%d)\n", __func__, rc);
+                return -EIO;
+        }
+
+        cd->mmio = pci_iomap(pci_dev, 0, 0);
+        if (cd->mmio == NULL) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: mapping BAR0 failed\n", __func__);
+                return -ENOMEM;
+        }
+        return 0;
+}
+
+/*
+ * Hardware circumvention section. Certain bitstreams in our test-lab
+ * had different kinds of problems. Here is where we adjust those
+ * bitstreams to function will with this version of our device driver.
+ *
+ * Thise circumventions are applied to the physical function only.
+ * The magical numbers below are identifying development/manufacturing
+ * versions of the bitstream used on the card.
+ *
+ * Turn off error reporting for old/manufacturing images.
+ */
+
+bool genwqe_need_err_masking(struct genwqe_dev *cd)
+{
+        return (cd->slu_unitcfg & 0xFFFF0ull) < 0x32170ull;
+}
+
+static void genwqe_tweak_hardware(struct genwqe_dev *cd)
+{
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        /* Mask FIRs for development images */
+        if (((cd->slu_unitcfg & 0xFFFF0ull) >= 0x32000ull) &&
+            ((cd->slu_unitcfg & 0xFFFF0ull) <= 0x33250ull)) {
+                dev_warn(&pci_dev->dev,
+                         "FIRs masked due to bitstream %016llx.%016llx\n",
+                         cd->slu_unitcfg, cd->app_unitcfg);
+
+                __genwqe_writeq(cd, IO_APP_SEC_LEM_DEBUG_OVR,
+                                0xFFFFFFFFFFFFFFFFull);
+
+                __genwqe_writeq(cd, IO_APP_ERR_ACT_MASK,
+                                0x0000000000000000ull);
+        }
+}
+
+/**
+ * genwqe_recovery_on_fatal_gfir_required() - Version depended actions
+ *
+ * Bitstreams older than 2013-02-17 have a bug where fatal GFIRs must
+ * be ignored. This is e.g. true for the bitstream we gave to the card
+ * manufacturer, but also for some old bitstreams we released to our
+ * test-lab.
+ */
+int genwqe_recovery_on_fatal_gfir_required(struct genwqe_dev *cd)
+{
+        return (cd->slu_unitcfg & 0xFFFF0ull) >= 0x32170ull;
+}
+
+int genwqe_flash_readback_fails(struct genwqe_dev *cd)
+{
+        return (cd->slu_unitcfg & 0xFFFF0ull) < 0x32170ull;
+}
+
+/**
+ * genwqe_T_psec() - Calculate PF/VF timeout register content
+ *
+ * Note: From a design perspective it turned out to be a bad idea to
+ * use codes here to specifiy the frequency/speed values. An old
+ * driver cannot understand new codes and is therefore always a
+ * problem. Better is to measure out the value or put the
+ * speed/frequency directly into a register which is always a valid
+ * value for old as well as for new software.
+ */
+/* T = 1/f */
+static int genwqe_T_psec(struct genwqe_dev *cd)
+{
+        u16 speed;      /* 1/f -> 250,  200,  166,  175 */
+        static const int T[] = { 4000, 5000, 6000, 5714 };
+
+        speed = (u16)((cd->slu_unitcfg >> 28) & 0x0full);
+        if (speed >= ARRAY_SIZE(T))
+                return -1;      /* illegal value */
+
+        return T[speed];
+}
+
+/**
+ * genwqe_setup_pf_jtimer() - Setup PF hardware timeouts for DDCB execution
+ *
+ * Do this _after_ card_reset() is called. Otherwise the values will
+ * vanish. The settings need to be done when the queues are inactive.
+ *
+ * The max. timeout value is 2^(10+x) * T (6ns for 166MHz) * 15/16.
+ * The min. timeout value is 2^(10+x) * T (6ns for 166MHz) * 14/16.
+ */
+static bool genwqe_setup_pf_jtimer(struct genwqe_dev *cd)
+{
+        u32 T = genwqe_T_psec(cd);
+        u64 x;
+
+        if (genwqe_pf_jobtimeout_msec == 0)
+                return false;
+
+        /* PF: large value needed, flash update 2sec per block */
+        x = ilog2(genwqe_pf_jobtimeout_msec *
+                  16000000000uL/(T * 15)) - 10;
+
+        genwqe_write_vreg(cd, IO_SLC_VF_APPJOB_TIMEOUT,
+                          0xff00 | (x & 0xff), 0);
+        return true;
+}
+
+/**
+ * genwqe_setup_vf_jtimer() - Setup VF hardware timeouts for DDCB execution
+ */
+static bool genwqe_setup_vf_jtimer(struct genwqe_dev *cd)
+{
+        struct pci_dev *pci_dev = cd->pci_dev;
+        unsigned int vf;
+        u32 T = genwqe_T_psec(cd);
+        u64 x;
+
+        for (vf = 0; vf < pci_sriov_get_totalvfs(pci_dev); vf++) {
+
+                if (cd->vf_jobtimeout_msec[vf] == 0)
+                        continue;
+
+                x = ilog2(cd->vf_jobtimeout_msec[vf] *
+                          16000000000uL/(T * 15)) - 10;
+
+                genwqe_write_vreg(cd, IO_SLC_VF_APPJOB_TIMEOUT,
+                                  0xff00 | (x & 0xff), vf + 1);
+        }
+        return true;
+}
+
+static int genwqe_ffdc_buffs_alloc(struct genwqe_dev *cd)
+{
+        unsigned int type, e = 0;
+
+        for (type = 0; type < GENWQE_DBG_UNITS; type++) {
+                switch (type) {
+                case GENWQE_DBG_UNIT0:
+                        e = genwqe_ffdc_buff_size(cd, 0);
+                        break;
+                case GENWQE_DBG_UNIT1:
+                        e = genwqe_ffdc_buff_size(cd, 1);
+                        break;
+                case GENWQE_DBG_UNIT2:
+                        e = genwqe_ffdc_buff_size(cd, 2);
+                        break;
+                case GENWQE_DBG_REGS:
+                        e = GENWQE_FFDC_REGS;
+                        break;
+                }
+
+                /* currently support only the debug units mentioned here */
+                cd->ffdc[type].entries = e;
+                cd->ffdc[type].regs = kmalloc(e * sizeof(struct genwqe_reg),
+                                              GFP_KERNEL);
+                /*
+                 * regs == NULL is ok, the using code treats this as no regs,
+                 * Printing warning is ok in this case.
+                 */
+        }
+        return 0;
+}
+
+static void genwqe_ffdc_buffs_free(struct genwqe_dev *cd)
+{
+        unsigned int type;
+
+        for (type = 0; type < GENWQE_DBG_UNITS; type++) {
+                kfree(cd->ffdc[type].regs);
+                cd->ffdc[type].regs = NULL;
+        }
+}
+
+static int genwqe_read_ids(struct genwqe_dev *cd)
+{
+        int err = 0;
+        int slu_id;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        cd->slu_unitcfg = __genwqe_readq(cd, IO_SLU_UNITCFG);
+        if (cd->slu_unitcfg == IO_ILLEGAL_VALUE) {
+                dev_err(&pci_dev->dev,
+                        "err: SLUID=%016llx\n", cd->slu_unitcfg);
+                err = -EIO;
+                goto out_err;
+        }
+
+        slu_id = genwqe_get_slu_id(cd);
+        if (slu_id < GENWQE_SLU_ARCH_REQ || slu_id == 0xff) {
+                dev_err(&pci_dev->dev,
+                        "err: incompatible SLU Architecture %u\n", slu_id);
+                err = -ENOENT;
+                goto out_err;
+        }
+
+        cd->app_unitcfg = __genwqe_readq(cd, IO_APP_UNITCFG);
+        if (cd->app_unitcfg == IO_ILLEGAL_VALUE) {
+                dev_err(&pci_dev->dev,
+                        "err: APPID=%016llx\n", cd->app_unitcfg);
+                err = -EIO;
+                goto out_err;
+        }
+        genwqe_read_app_id(cd, cd->app_name, sizeof(cd->app_name));
+
+        /*
+         * Is access to all registers possible? If we are a VF the
+         * answer is obvious. If we run fully virtualized, we need to
+         * check if we can access all registers. If we do not have
+         * full access we will cause an UR and some informational FIRs
+         * in the PF, but that should not harm.
+         */
+        if (pci_dev->is_virtfn)
+                cd->is_privileged = 0;
+        else
+                cd->is_privileged = (__genwqe_readq(cd, IO_SLU_BITSTREAM)
+                                     != IO_ILLEGAL_VALUE);
+
+ out_err:
+        return err;
+}
+
+static int genwqe_start(struct genwqe_dev *cd)
+{
+        int err;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        err = genwqe_read_ids(cd);
+        if (err)
+                return err;
+
+        if (genwqe_is_privileged(cd)) {
+                /* do this after the tweaks. alloc fail is acceptable */
+                genwqe_ffdc_buffs_alloc(cd);
+                genwqe_stop_traps(cd);
+
+                /* Collect registers e.g. FIRs, UNITIDs, traces ... */
+                genwqe_read_ffdc_regs(cd, cd->ffdc[GENWQE_DBG_REGS].regs,
+                                      cd->ffdc[GENWQE_DBG_REGS].entries, 0);
+
+                genwqe_ffdc_buff_read(cd, GENWQE_DBG_UNIT0,
+                                      cd->ffdc[GENWQE_DBG_UNIT0].regs,
+                                      cd->ffdc[GENWQE_DBG_UNIT0].entries);
+
+                genwqe_ffdc_buff_read(cd, GENWQE_DBG_UNIT1,
+                                      cd->ffdc[GENWQE_DBG_UNIT1].regs,
+                                      cd->ffdc[GENWQE_DBG_UNIT1].entries);
+
+                genwqe_ffdc_buff_read(cd, GENWQE_DBG_UNIT2,
+                                      cd->ffdc[GENWQE_DBG_UNIT2].regs,
+                                      cd->ffdc[GENWQE_DBG_UNIT2].entries);
+
+                genwqe_start_traps(cd);
+
+                if (cd->card_state == GENWQE_CARD_FATAL_ERROR) {
+                        dev_warn(&pci_dev->dev,
+                                 "[%s] chip reload/recovery!\n", __func__);
+
+                        /*
+                         * Stealth Mode: Reload chip on either hot
+                         * reset or PERST.
+                         */
+                        cd->softreset = 0x7Cull;
+                        __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET,
+                                       cd->softreset);
+
+                        err = genwqe_bus_reset(cd);
+                        if (err != 0) {
+                                dev_err(&pci_dev->dev,
+                                        "[%s] err: bus reset failed!\n",
+                                        __func__);
+                                goto out;
+                        }
+
+                        /*
+                         * Re-read the IDs because
+                         * it could happen that the bitstream load
+                         * failed!
+                         */
+                        err = genwqe_read_ids(cd);
+                        if (err)
+                                goto out;
+                }
+        }
+
+        err = genwqe_setup_service_layer(cd);  /* does a reset to the card */
+        if (err != 0) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: could not setup servicelayer!\n", __func__);
+                err = -ENODEV;
+                goto out;
+        }
+
+        if (genwqe_is_privileged(cd)) {  /* code is running _after_ reset */
+                genwqe_tweak_hardware(cd);
+
+                genwqe_setup_pf_jtimer(cd);
+                genwqe_setup_vf_jtimer(cd);
+        }
+
+        err = genwqe_device_create(cd);
+        if (err < 0) {
+                dev_err(&pci_dev->dev,
+                        "err: chdev init failed! (err=%d)\n", err);
+                goto out_release_service_layer;
+        }
+        return 0;
+
+ out_release_service_layer:
+        genwqe_release_service_layer(cd);
+ out:
+        if (genwqe_is_privileged(cd))
+                genwqe_ffdc_buffs_free(cd);
+        return -EIO;
+}
+
+/**
+ * genwqe_stop() - Stop card operation
+ *
+ * Recovery notes:
+ *   As long as genwqe_thread runs we might access registers during
+ *   error data capture. Same is with the genwqe_health_thread.
+ *   When genwqe_bus_reset() fails this function might called two times:
+ *   first by the genwqe_health_thread() and later by genwqe_remove() to
+ *   unbind the device. We must be able to survive that.
+ *
+ * This function must be robust enough to be called twice.
+ */
+static int genwqe_stop(struct genwqe_dev *cd)
+{
+        genwqe_finish_queue(cd);            /* no register access */
+        genwqe_device_remove(cd);           /* device removed, procs killed */
+        genwqe_release_service_layer(cd);   /* here genwqe_thread is stopped */
+
+        if (genwqe_is_privileged(cd)) {
+                pci_disable_sriov(cd->pci_dev); /* access pci config space */
+                genwqe_ffdc_buffs_free(cd);
+        }
+
+        return 0;
+}
+
+/**
+ * genwqe_recover_card() - Try to recover the card if it is possible
+ *
+ * If fatal_err is set no register access is possible anymore. It is
+ * likely that genwqe_start fails in that situation. Proper error
+ * handling is required in this case.
+ *
+ * genwqe_bus_reset() will cause the pci code to call genwqe_remove()
+ * and later genwqe_probe() for all virtual functions.
+ */
+static int genwqe_recover_card(struct genwqe_dev *cd, int fatal_err)
+{
+        int rc;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        genwqe_stop(cd);
+
+        /*
+         * Make sure chip is not reloaded to maintain FFDC. Write SLU
+         * Reset Register, CPLDReset field to 0.
+         */
+        if (!fatal_err) {
+                cd->softreset = 0x70ull;
+                __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET, cd->softreset);
+        }
+
+        rc = genwqe_bus_reset(cd);
+        if (rc != 0) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: card recovery impossible!\n", __func__);
+                return rc;
+        }
+
+        rc = genwqe_start(cd);
+        if (rc < 0) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: failed to launch device!\n", __func__);
+                return rc;
+        }
+        return 0;
+}
+
+static int genwqe_health_check_cond(struct genwqe_dev *cd, u64 *gfir)
+{
+        *gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
+        return (*gfir & GFIR_ERR_TRIGGER) &&
+                genwqe_recovery_on_fatal_gfir_required(cd);
+}
+
+/**
+ * genwqe_fir_checking() - Check the fault isolation registers of the card
+ *
+ * If this code works ok, can be tried out with help of the genwqe_poke tool:
+ *   sudo ./tools/genwqe_poke 0x8 0xfefefefefef
+ *
+ * Now the relevant FIRs/sFIRs should be printed out and the driver should
+ * invoke recovery (devices are removed and readded).
+ */
+static u64 genwqe_fir_checking(struct genwqe_dev *cd)
+{
+        int j, iterations = 0;
+        u64 mask, fir, fec, uid, gfir, gfir_masked, sfir, sfec;
+        u32 fir_addr, fir_clr_addr, fec_addr, sfir_addr, sfec_addr;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+ healthMonitor:
+        iterations++;
+        if (iterations > 16) {
+                dev_err(&pci_dev->dev, "* exit looping after %d times\n",
+                        iterations);
+                goto fatal_error;
+        }
+
+        gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
+        if (gfir != 0x0)
+                dev_err(&pci_dev->dev, "* 0x%08x 0x%016llx\n",
+                                    IO_SLC_CFGREG_GFIR, gfir);
+        if (gfir == IO_ILLEGAL_VALUE)
+                goto fatal_error;
+
+        /*
+         * Avoid printing when to GFIR bit is on prevents contignous
+         * printout e.g. for the following bug:
+         *   FIR set without a 2ndary FIR/FIR cannot be cleared
+         * Comment out the following if to get the prints:
+         */
+        if (gfir == 0)
+                return 0;
+
+        gfir_masked = gfir & GFIR_ERR_TRIGGER;  /* fatal errors */
+
+        for (uid = 0; uid < GENWQE_MAX_UNITS; uid++) { /* 0..2 in zEDC */
+
+                /* read the primary FIR (pfir) */
+                fir_addr = (uid << 24) + 0x08;
+                fir = __genwqe_readq(cd, fir_addr);
+                if (fir == 0x0)
+                        continue;  /* no error in this unit */
+
+                dev_err(&pci_dev->dev, "* 0x%08x 0x%016llx\n", fir_addr, fir);
+                if (fir == IO_ILLEGAL_VALUE)
+                        goto fatal_error;
+
+                /* read primary FEC */
+                fec_addr = (uid << 24) + 0x18;
+                fec = __genwqe_readq(cd, fec_addr);
+
+                dev_err(&pci_dev->dev, "* 0x%08x 0x%016llx\n", fec_addr, fec);
+                if (fec == IO_ILLEGAL_VALUE)
+                        goto fatal_error;
+
+                for (j = 0, mask = 1ULL; j < 64; j++, mask <<= 1) {
+
+                        /* secondary fir empty, skip it */
+                        if ((fir & mask) == 0x0)
+                                continue;
+
+                        sfir_addr = (uid << 24) + 0x100 + 0x08 * j;
+                        sfir = __genwqe_readq(cd, sfir_addr);
+
+                        if (sfir == IO_ILLEGAL_VALUE)
+                                goto fatal_error;
+                        dev_err(&pci_dev->dev,
+                                "* 0x%08x 0x%016llx\n", sfir_addr, sfir);
+
+                        sfec_addr = (uid << 24) + 0x300 + 0x08 * j;
+                        sfec = __genwqe_readq(cd, sfec_addr);
+
+                        if (sfec == IO_ILLEGAL_VALUE)
+                                goto fatal_error;
+                        dev_err(&pci_dev->dev,
+                                "* 0x%08x 0x%016llx\n", sfec_addr, sfec);
+
+                        gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
+                        if (gfir == IO_ILLEGAL_VALUE)
+                                goto fatal_error;
+
+                        /* gfir turned on during routine! get out and
+                           start over. */
+                        if ((gfir_masked == 0x0) &&
+                            (gfir & GFIR_ERR_TRIGGER)) {
+                                goto healthMonitor;
+                        }
+
+                        /* do not clear if we entered with a fatal gfir */
+                        if (gfir_masked == 0x0) {
+
+                                /* NEW clear by mask the logged bits */
+                                sfir_addr = (uid << 24) + 0x100 + 0x08 * j;
+                                __genwqe_writeq(cd, sfir_addr, sfir);
+
+                                dev_dbg(&pci_dev->dev,
+                                        "[HM] Clearing  2ndary FIR 0x%08x "
+                                        "with 0x%016llx\n", sfir_addr, sfir);
+
+                                /*
+                                 * note, these cannot be error-Firs
+                                 * since gfir_masked is 0 after sfir
+                                 * was read. Also, it is safe to do
+                                 * this write if sfir=0. Still need to
+                                 * clear the primary. This just means
+                                 * there is no secondary FIR.
+                                 */
+
+                                /* clear by mask the logged bit. */
+                                fir_clr_addr = (uid << 24) + 0x10;
+                                __genwqe_writeq(cd, fir_clr_addr, mask);
+
+                                dev_dbg(&pci_dev->dev,
+                                        "[HM] Clearing primary FIR 0x%08x "
+                                        "with 0x%016llx\n", fir_clr_addr,
+                                        mask);
+                        }
+                }
+        }
+        gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
+        if (gfir == IO_ILLEGAL_VALUE)
+                goto fatal_error;
+
+        if ((gfir_masked == 0x0) && (gfir & GFIR_ERR_TRIGGER)) {
+                /*
+                 * Check once more that it didn't go on after all the
+                 * FIRS were cleared.
+                 */
+                dev_dbg(&pci_dev->dev, "ACK! Another FIR! Recursing %d!\n",
+                        iterations);
+                goto healthMonitor;
+        }
+        return gfir_masked;
+
+ fatal_error:
+        return IO_ILLEGAL_VALUE;
+}
+
+/**
+ * genwqe_health_thread() - Health checking thread
+ *
+ * This thread is only started for the PF of the card.
+ *
+ * This thread monitors the health of the card. A critical situation
+ * is when we read registers which contain -1 (IO_ILLEGAL_VALUE). In
+ * this case we need to be recovered from outside. Writing to
+ * registers will very likely not work either.
+ *
+ * This thread must only exit if kthread_should_stop() becomes true.
+ *
+ * Condition for the health-thread to trigger:
+ *   a) when a kthread_stop() request comes in or
+ *   b) a critical GFIR occured
+ *
+ * Informational GFIRs are checked and potentially printed in
+ * health_check_interval seconds.
+ */
+static int genwqe_health_thread(void *data)
+{
+        int rc, should_stop = 0;
+        struct genwqe_dev *cd = data;
+        struct pci_dev *pci_dev = cd->pci_dev;
+        u64 gfir, gfir_masked, slu_unitcfg, app_unitcfg;
+
+        while (!kthread_should_stop()) {
+                rc = wait_event_interruptible_timeout(cd->health_waitq,
+                         (genwqe_health_check_cond(cd, &gfir) ||
+                          (should_stop = kthread_should_stop())),
+                                genwqe_health_check_interval * HZ);
+
+                if (should_stop)
+                        break;
+
+                if (gfir == IO_ILLEGAL_VALUE) {
+                        dev_err(&pci_dev->dev,
+                                "[%s] GFIR=%016llx\n", __func__, gfir);
+                        goto fatal_error;
+                }
+
+                slu_unitcfg = __genwqe_readq(cd, IO_SLU_UNITCFG);
+                if (slu_unitcfg == IO_ILLEGAL_VALUE) {
+                        dev_err(&pci_dev->dev,
+                                "[%s] SLU_UNITCFG=%016llx\n",
+                                __func__, slu_unitcfg);
+                        goto fatal_error;
+                }
+
+                app_unitcfg = __genwqe_readq(cd, IO_APP_UNITCFG);
+                if (app_unitcfg == IO_ILLEGAL_VALUE) {
+                        dev_err(&pci_dev->dev,
+                                "[%s] APP_UNITCFG=%016llx\n",
+                                __func__, app_unitcfg);
+                        goto fatal_error;
+                }
+
+                gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
+                if (gfir == IO_ILLEGAL_VALUE) {
+                        dev_err(&pci_dev->dev,
+                                "[%s] %s: GFIR=%016llx\n", __func__,
+                                (gfir & GFIR_ERR_TRIGGER) ? "err" : "info",
+                                gfir);
+                        goto fatal_error;
+                }
+
+                gfir_masked = genwqe_fir_checking(cd);
+                if (gfir_masked == IO_ILLEGAL_VALUE)
+                        goto fatal_error;
+
+                /*
+                 * GFIR ErrorTrigger bits set => reset the card!
+                 * Never do this for old/manufacturing images!
+                 */
+                if ((gfir_masked) && !cd->skip_recovery &&
+                    genwqe_recovery_on_fatal_gfir_required(cd)) {
+
+                        cd->card_state = GENWQE_CARD_FATAL_ERROR;
+
+                        rc = genwqe_recover_card(cd, 0);
+                        if (rc < 0) {
+                                /* FIXME Card is unusable and needs unbind! */
+                                goto fatal_error;
+                        }
+                }
+
+                cd->last_gfir = gfir;
+                cond_resched();
+        }
+
+        return 0;
+
+ fatal_error:
+        dev_err(&pci_dev->dev,
+                "[%s] card unusable. Please trigger unbind!\n", __func__);
+
+        /* Bring down logical devices to inform user space via udev remove. */
+        cd->card_state = GENWQE_CARD_FATAL_ERROR;
+        genwqe_stop(cd);
+
+        /* genwqe_bus_reset failed(). Now wait for genwqe_remove(). */
+        while (!kthread_should_stop())
+                cond_resched();
+
+        return -EIO;
+}
+
+static int genwqe_health_check_start(struct genwqe_dev *cd)
+{
+        int rc;
+
+        if (genwqe_health_check_interval <= 0)
+                return 0;       /* valid for disabling the service */
+
+        /* moved before request_irq() */
+        /* init_waitqueue_head(&cd->health_waitq); */
+
+        cd->health_thread = kthread_run(genwqe_health_thread, cd,
+                                        GENWQE_DEVNAME "%d_health",
+                                        cd->card_idx);
+        if (IS_ERR(cd->health_thread)) {
+                rc = PTR_ERR(cd->health_thread);
+                cd->health_thread = NULL;
+                return rc;
+        }
+        return 0;
+}
+
+static int genwqe_health_thread_running(struct genwqe_dev *cd)
+{
+        return cd->health_thread != NULL;
+}
+
+static int genwqe_health_check_stop(struct genwqe_dev *cd)
+{
+        int rc;
+
+        if (!genwqe_health_thread_running(cd))
+                return -EIO;
+
+        rc = kthread_stop(cd->health_thread);
+        cd->health_thread = NULL;
+        return 0;
+}
+
+/**
+ * genwqe_pci_setup() - Allocate PCIe related resources for our card
+ */
+static int genwqe_pci_setup(struct genwqe_dev *cd)
+{
+        int err, bars;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        bars = pci_select_bars(pci_dev, IORESOURCE_MEM);
+        err = pci_enable_device_mem(pci_dev);
+        if (err) {
+                dev_err(&pci_dev->dev,
+                        "err: failed to enable pci memory (err=%d)\n", err);
+                goto err_out;
+        }
+
+        /* Reserve PCI I/O and memory resources */
+        err = pci_request_selected_regions(pci_dev, bars, genwqe_driver_name);
+        if (err) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: request bars failed (%d)\n", __func__, err);
+                err = -EIO;
+                goto err_disable_device;
+        }
+
+        /* check for 64-bit DMA address supported (DAC) */
+        if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) {
+                err = pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(64));
+                if (err) {
+                        dev_err(&pci_dev->dev,
+                                "err: DMA64 consistent mask error\n");
+                        err = -EIO;
+                        goto out_release_resources;
+                }
+        /* check for 32-bit DMA address supported (SAC) */
+        } else if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) {
+                err = pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(32));
+                if (err) {
+                        dev_err(&pci_dev->dev,
+                                "err: DMA32 consistent mask error\n");
+                        err = -EIO;
+                        goto out_release_resources;
+                }
+        } else {
+                dev_err(&pci_dev->dev,
+                        "err: neither DMA32 nor DMA64 supported\n");
+                err = -EIO;
+                goto out_release_resources;
+        }
+
+        pci_set_master(pci_dev);
+        pci_enable_pcie_error_reporting(pci_dev);
+
+        /* request complete BAR-0 space (length = 0) */
+        cd->mmio_len = pci_resource_len(pci_dev, 0);
+        cd->mmio = pci_iomap(pci_dev, 0, 0);
+        if (cd->mmio == NULL) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: mapping BAR0 failed\n", __func__);
+                err = -ENOMEM;
+                goto out_release_resources;
+        }
+
+        cd->num_vfs = pci_sriov_get_totalvfs(pci_dev);
+
+        err = genwqe_read_ids(cd);
+        if (err)
+                goto out_iounmap;
+
+        return 0;
+
+ out_iounmap:
+        pci_iounmap(pci_dev, cd->mmio);
+ out_release_resources:
+        pci_release_selected_regions(pci_dev, bars);
+ err_disable_device:
+        pci_disable_device(pci_dev);
+ err_out:
+        return err;
+}
+
+/**
+ * genwqe_pci_remove() - Free PCIe related resources for our card
+ */
+static void genwqe_pci_remove(struct genwqe_dev *cd)
+{
+        int bars;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if (cd->mmio)
+                pci_iounmap(pci_dev, cd->mmio);
+
+        bars = pci_select_bars(pci_dev, IORESOURCE_MEM);
+        pci_release_selected_regions(pci_dev, bars);
+        pci_disable_device(pci_dev);
+}
+
+/**
+ * genwqe_probe() - Device initialization
+ * @pdev:       PCI device information struct
+ *
+ * Callable for multiple cards. This function is called on bind.
+ *
+ * Return: 0 if succeeded, < 0 when failed
+ */
+static int genwqe_probe(struct pci_dev *pci_dev,
+                        const struct pci_device_id *id)
+{
+        int err;
+        struct genwqe_dev *cd;
+
+        genwqe_init_crc32();
+
+        cd = genwqe_dev_alloc();
+        if (IS_ERR(cd)) {
+                dev_err(&pci_dev->dev, "err: could not alloc mem (err=%d)!\n",
+                        (int)PTR_ERR(cd));
+                return PTR_ERR(cd);
+        }
+
+        dev_set_drvdata(&pci_dev->dev, cd);
+        cd->pci_dev = pci_dev;
+
+        err = genwqe_pci_setup(cd);
+        if (err < 0) {
+                dev_err(&pci_dev->dev,
+                        "err: problems with PCI setup (err=%d)\n", err);
+                goto out_free_dev;
+        }
+
+        err = genwqe_start(cd);
+        if (err < 0) {
+                dev_err(&pci_dev->dev,
+                        "err: cannot start card services! (err=%d)\n", err);
+                goto out_pci_remove;
+        }
+
+        if (genwqe_is_privileged(cd)) {
+                err = genwqe_health_check_start(cd);
+                if (err < 0) {
+                        dev_err(&pci_dev->dev,
+                                "err: cannot start health checking! "
+                                "(err=%d)\n", err);
+                        goto out_stop_services;
+                }
+        }
+        return 0;
+
+ out_stop_services:
+        genwqe_stop(cd);
+ out_pci_remove:
+        genwqe_pci_remove(cd);
+ out_free_dev:
+        genwqe_dev_free(cd);
+        return err;
+}
+
+/**
+ * genwqe_remove() - Called when device is removed (hot-plugable)
+ *
+ * Or when driver is unloaded respecitively when unbind is done.
+ */
+static void genwqe_remove(struct pci_dev *pci_dev)
+{
+        struct genwqe_dev *cd = dev_get_drvdata(&pci_dev->dev);
+
+        genwqe_health_check_stop(cd);
+
+        /*
+         * genwqe_stop() must survive if it is called twice
+         * sequentially. This happens when the health thread calls it
+         * and fails on genwqe_bus_reset().
+         */
+        genwqe_stop(cd);
+        genwqe_pci_remove(cd);
+        genwqe_dev_free(cd);
+}
+
+/*
+ * genwqe_err_error_detected() - Error detection callback
+ *
+ * This callback is called by the PCI subsystem whenever a PCI bus
+ * error is detected.
+ */
+static pci_ers_result_t genwqe_err_error_detected(struct pci_dev *pci_dev,
+                                                 enum pci_channel_state state)
+{
+        struct genwqe_dev *cd;
+
+        dev_err(&pci_dev->dev, "[%s] state=%d\n", __func__, state);
+
+        if (pci_dev == NULL)
+                return PCI_ERS_RESULT_NEED_RESET;
+
+        cd = dev_get_drvdata(&pci_dev->dev);
+        if (cd == NULL)
+                return PCI_ERS_RESULT_NEED_RESET;
+
+        switch (state) {
+        case pci_channel_io_normal:
+                return PCI_ERS_RESULT_CAN_RECOVER;
+        case pci_channel_io_frozen:
+                return PCI_ERS_RESULT_NEED_RESET;
+        case pci_channel_io_perm_failure:
+                return PCI_ERS_RESULT_DISCONNECT;
+        }
+
+        return PCI_ERS_RESULT_NEED_RESET;
+}
+
+static pci_ers_result_t genwqe_err_result_none(struct pci_dev *dev)
+{
+        return PCI_ERS_RESULT_NONE;
+}
+
+static void genwqe_err_resume(struct pci_dev *dev)
+{
+}
+
+static int genwqe_sriov_configure(struct pci_dev *dev, int numvfs)
+{
+        struct genwqe_dev *cd = dev_get_drvdata(&dev->dev);
+
+        if (numvfs > 0) {
+                genwqe_setup_vf_jtimer(cd);
+                pci_enable_sriov(dev, numvfs);
+                return numvfs;
+        }
+        if (numvfs == 0) {
+                pci_disable_sriov(dev);
+                return 0;
+        }
+        return 0;
+}
+
+static struct pci_error_handlers genwqe_err_handler = {
+        .error_detected = genwqe_err_error_detected,
+        .mmio_enabled   = genwqe_err_result_none,
+        .link_reset     = genwqe_err_result_none,
+        .slot_reset     = genwqe_err_result_none,
+        .resume         = genwqe_err_resume,
+};
+
+static struct pci_driver genwqe_driver = {
+        .name     = genwqe_driver_name,
+        .id_table = genwqe_device_table,
+        .probe    = genwqe_probe,
+        .remove   = genwqe_remove,
+        .sriov_configure = genwqe_sriov_configure,
+        .err_handler = &genwqe_err_handler,
+};
+
+/**
+ * genwqe_init_module() - Driver registration and initialization
+ */
+static int __init genwqe_init_module(void)
+{
+        int rc;
+
+        class_genwqe = class_create(THIS_MODULE, GENWQE_DEVNAME);
+        if (IS_ERR(class_genwqe)) {
+                pr_err("[%s] create class failed\n", __func__);
+                return -ENOMEM;
+        }
+
+        debugfs_genwqe = debugfs_create_dir(GENWQE_DEVNAME, NULL);
+        if (!debugfs_genwqe) {
+                rc = -ENOMEM;
+                goto err_out;
+        }
+
+        rc = pci_register_driver(&genwqe_driver);
+        if (rc != 0) {
+                pr_err("[%s] pci_reg_driver (rc=%d)\n", __func__, rc);
+                goto err_out0;
+        }
+
+        return rc;
+
+ err_out0:
+        debugfs_remove(debugfs_genwqe);
+ err_out:
+        class_destroy(class_genwqe);
+        return rc;
+}
+
+/**
+ * genwqe_exit_module() - Driver exit
+ */
+static void __exit genwqe_exit_module(void)
+{
+        pci_unregister_driver(&genwqe_driver);
+        debugfs_remove(debugfs_genwqe);
+        class_destroy(class_genwqe);
+}
+
+module_init(genwqe_init_module);
+module_exit(genwqe_exit_module);
diff --git a/drivers/misc/genwqe/card_base.h b/drivers/misc/genwqe/card_base.h
new file mode 100644
index 000000000000..5e4dbd21f89a
--- /dev/null
+++ b/drivers/misc/genwqe/card_base.h
@@ -0,0 +1,557 @@
+#ifndef __CARD_BASE_H__
+#define __CARD_BASE_H__
+
+/**
+ * IBM Accelerator Family 'GenWQE'
+ *
+ * (C) Copyright IBM Corp. 2013
+ *
+ * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
+ * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
+ * Author: Michael Jung <mijung@de.ibm.com>
+ * Author: Michael Ruettger <michael@ibmra.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Interfaces within the GenWQE module. Defines genwqe_card and
+ * ddcb_queue as well as ddcb_requ.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/cdev.h>
+#include <linux/stringify.h>
+#include <linux/pci.h>
+#include <linux/semaphore.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/version.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+
+#include <linux/genwqe/genwqe_card.h>
+#include "genwqe_driver.h"
+
+#define GENWQE_MSI_IRQS                 4  /* Just one supported, no MSIx */
+#define GENWQE_FLAG_MSI_ENABLED         (1 << 0)
+
+#define GENWQE_MAX_VFS                  15 /* maximum 15 VFs are possible */
+#define GENWQE_MAX_FUNCS                16 /* 1 PF and 15 VFs */
+#define GENWQE_CARD_NO_MAX              (16 * GENWQE_MAX_FUNCS)
+
+/* Compile parameters, some of them appear in debugfs for later adjustment */
+#define genwqe_ddcb_max                 32 /* DDCBs on the work-queue */
+#define genwqe_polling_enabled          0  /* in case of irqs not working */
+#define genwqe_ddcb_software_timeout    10 /* timeout per DDCB in seconds */
+#define genwqe_kill_timeout             8  /* time until process gets killed */
+#define genwqe_vf_jobtimeout_msec       250  /* 250 msec */
+#define genwqe_pf_jobtimeout_msec       8000 /* 8 sec should be ok */
+#define genwqe_health_check_interval    4 /* <= 0: disabled */
+
+/* Sysfs attribute groups used when we create the genwqe device */
+extern const struct attribute_group *genwqe_attribute_groups[];
+
+/*
+ * Config space for Genwqe5 A7:
+ * 00:[14 10 4b 04]40 00 10 00[00 00 00 12]00 00 00 00
+ * 10: 0c 00 00 f0 07 3c 00 00 00 00 00 00 00 00 00 00
+ * 20: 00 00 00 00 00 00 00 00 00 00 00 00[14 10 4b 04]
+ * 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00
+ */
+#define PCI_DEVICE_GENWQE               0x044b /* Genwqe DeviceID */
+
+#define PCI_SUBSYSTEM_ID_GENWQE5        0x035f /* Genwqe A5 Subsystem-ID */
+#define PCI_SUBSYSTEM_ID_GENWQE5_NEW    0x044b /* Genwqe A5 Subsystem-ID */
+#define PCI_CLASSCODE_GENWQE5           0x1200 /* UNKNOWN */
+
+#define PCI_SUBVENDOR_ID_IBM_SRIOV      0x0000
+#define PCI_SUBSYSTEM_ID_GENWQE5_SRIOV  0x0000 /* Genwqe A5 Subsystem-ID */
+#define PCI_CLASSCODE_GENWQE5_SRIOV     0x1200 /* UNKNOWN */
+
+#define GENWQE_SLU_ARCH_REQ             2 /* Required SLU architecture level */
+
+/**
+ * struct genwqe_reg - Genwqe data dump functionality
+ */
+struct genwqe_reg {
+        u32 addr;
+        u32 idx;
+        u64 val;
+};
+
+/*
+ * enum genwqe_dbg_type - Specify chip unit to dump/debug
+ */
+enum genwqe_dbg_type {
+        GENWQE_DBG_UNIT0 = 0,  /* captured before prev errs cleared */
+        GENWQE_DBG_UNIT1 = 1,
+        GENWQE_DBG_UNIT2 = 2,
+        GENWQE_DBG_UNIT3 = 3,
+        GENWQE_DBG_UNIT4 = 4,
+        GENWQE_DBG_UNIT5 = 5,
+        GENWQE_DBG_UNIT6 = 6,
+        GENWQE_DBG_UNIT7 = 7,
+        GENWQE_DBG_REGS  = 8,
+        GENWQE_DBG_DMA   = 9,
+        GENWQE_DBG_UNITS = 10, /* max number of possible debug units  */
+};
+
+/* Software error injection to simulate card failures */
+#define GENWQE_INJECT_HARDWARE_FAILURE  0x00000001 /* injects -1 reg reads */
+#define GENWQE_INJECT_BUS_RESET_FAILURE 0x00000002 /* pci_bus_reset fail */
+#define GENWQE_INJECT_GFIR_FATAL        0x00000004 /* GFIR = 0x0000ffff */
+#define GENWQE_INJECT_GFIR_INFO         0x00000008 /* GFIR = 0xffff0000 */
+
+/*
+ * Genwqe card description and management data.
+ *
+ * Error-handling in case of card malfunction
+ * ------------------------------------------
+ *
+ * If the card is detected to be defective the outside environment
+ * will cause the PCI layer to call deinit (the cleanup function for
+ * probe). This is the same effect like doing a unbind/bind operation
+ * on the card.
+ *
+ * The genwqe card driver implements a health checking thread which
+ * verifies the card function. If this detects a problem the cards
+ * device is being shutdown and restarted again, along with a reset of
+ * the card and queue.
+ *
+ * All functions accessing the card device return either -EIO or -ENODEV
+ * code to indicate the malfunction to the user. The user has to close
+ * the file descriptor and open a new one, once the card becomes
+ * available again.
+ *
+ * If the open file descriptor is setup to receive SIGIO, the signal is
+ * genereated for the application which has to provide a handler to
+ * react on it. If the application does not close the open
+ * file descriptor a SIGKILL is send to enforce freeing the cards
+ * resources.
+ *
+ * I did not find a different way to prevent kernel problems due to
+ * reference counters for the cards character devices getting out of
+ * sync. The character device deallocation does not block, even if
+ * there is still an open file descriptor pending. If this pending
+ * descriptor is closed, the data structures used by the character
+ * device is reinstantiated, which will lead to the reference counter
+ * dropping below the allowed values.
+ *
+ * Card recovery
+ * -------------
+ *
+ * To test the internal driver recovery the following command can be used:
+ *   sudo sh -c 'echo 0xfffff > /sys/class/genwqe/genwqe0_card/err_inject'
+ */
+
+
+/**
+ * struct dma_mapping_type - Mapping type definition
+ *
+ * To avoid memcpying data arround we use user memory directly. To do
+ * this we need to pin/swap-in the memory and request a DMA address
+ * for it.
+ */
+enum dma_mapping_type {
+        GENWQE_MAPPING_RAW = 0,         /* contignous memory buffer */
+        GENWQE_MAPPING_SGL_TEMP,        /* sglist dynamically used */
+        GENWQE_MAPPING_SGL_PINNED,      /* sglist used with pinning */
+};
+
+/**
+ * struct dma_mapping - Information about memory mappings done by the driver
+ */
+struct dma_mapping {
+        enum dma_mapping_type type;
+
+        void *u_vaddr;                  /* user-space vaddr/non-aligned */
+        void *k_vaddr;                  /* kernel-space vaddr/non-aligned */
+        dma_addr_t dma_addr;            /* physical DMA address */
+
+        struct page **page_list;        /* list of pages used by user buff */
+        dma_addr_t *dma_list;           /* list of dma addresses per page */
+        unsigned int nr_pages;          /* number of pages */
+        unsigned int size;              /* size in bytes */
+
+        struct list_head card_list;     /* list of usr_maps for card */
+        struct list_head pin_list;      /* list of pinned memory for dev */
+};
+
+static inline void genwqe_mapping_init(struct dma_mapping *m,
+                                       enum dma_mapping_type type)
+{
+        memset(m, 0, sizeof(*m));
+        m->type = type;
+}
+
+/**
+ * struct ddcb_queue - DDCB queue data
+ * @ddcb_max:          Number of DDCBs on the queue
+ * @ddcb_next:         Next free DDCB
+ * @ddcb_act:          Next DDCB supposed to finish
+ * @ddcb_seq:          Sequence number of last DDCB
+ * @ddcbs_in_flight:   Currently enqueued DDCBs
+ * @ddcbs_completed:   Number of already completed DDCBs
+ * @busy:              Number of -EBUSY returns
+ * @ddcb_daddr:        DMA address of first DDCB in the queue
+ * @ddcb_vaddr:        Kernel virtual address of first DDCB in the queue
+ * @ddcb_req:          Associated requests (one per DDCB)
+ * @ddcb_waitqs:       Associated wait queues (one per DDCB)
+ * @ddcb_lock:         Lock to protect queuing operations
+ * @ddcb_waitq:        Wait on next DDCB finishing
+ */
+
+struct ddcb_queue {
+        int ddcb_max;                   /* amount of DDCBs  */
+        int ddcb_next;                  /* next available DDCB num */
+        int ddcb_act;                   /* DDCB to be processed */
+        u16 ddcb_seq;                   /* slc seq num */
+        unsigned int ddcbs_in_flight;   /* number of ddcbs in processing */
+        unsigned int ddcbs_completed;
+        unsigned int ddcbs_max_in_flight;
+        unsigned int busy;              /* how many times -EBUSY? */
+
+        dma_addr_t ddcb_daddr;          /* DMA address */
+        struct ddcb *ddcb_vaddr;        /* kernel virtual addr for DDCBs */
+        struct ddcb_requ **ddcb_req;    /* ddcb processing parameter */
+        wait_queue_head_t *ddcb_waitqs; /* waitqueue per ddcb */
+
+        spinlock_t ddcb_lock;           /* exclusive access to queue */
+        wait_queue_head_t ddcb_waitq;   /* wait for ddcb processing */
+
+        /* registers or the respective queue to be used */
+        u32 IO_QUEUE_CONFIG;
+        u32 IO_QUEUE_STATUS;
+        u32 IO_QUEUE_SEGMENT;
+        u32 IO_QUEUE_INITSQN;
+        u32 IO_QUEUE_WRAP;
+        u32 IO_QUEUE_OFFSET;
+        u32 IO_QUEUE_WTIME;
+        u32 IO_QUEUE_ERRCNTS;
+        u32 IO_QUEUE_LRW;
+};
+
+/*
+ * GFIR, SLU_UNITCFG, APP_UNITCFG
+ *   8 Units with FIR/FEC + 64 * 2ndary FIRS/FEC.
+ */
+#define GENWQE_FFDC_REGS        (3 + (8 * (2 + 2 * 64)))
+
+struct genwqe_ffdc {
+        unsigned int entries;
+        struct genwqe_reg *regs;
+};
+
+/**
+ * struct genwqe_dev - GenWQE device information
+ * @card_state:       Card operation state, see above
+ * @ffdc:             First Failure Data Capture buffers for each unit
+ * @card_thread:      Working thread to operate the DDCB queue
+ * @card_waitq:       Wait queue used in card_thread
+ * @queue:            DDCB queue
+ * @health_thread:    Card monitoring thread (only for PFs)
+ * @health_waitq:     Wait queue used in health_thread
+ * @pci_dev:          Associated PCI device (function)
+ * @mmio:             Base address of 64-bit register space
+ * @mmio_len:         Length of register area
+ * @file_lock:        Lock to protect access to file_list
+ * @file_list:        List of all processes with open GenWQE file descriptors
+ *
+ * This struct contains all information needed to communicate with a
+ * GenWQE card. It is initialized when a GenWQE device is found and
+ * destroyed when it goes away. It holds data to maintain the queue as
+ * well as data needed to feed the user interfaces.
+ */
+struct genwqe_dev {
+        enum genwqe_card_state card_state;
+        spinlock_t print_lock;
+
+        int card_idx;                   /* card index 0..CARD_NO_MAX-1 */
+        u64 flags;                      /* general flags */
+
+        /* FFDC data gathering */
+        struct genwqe_ffdc ffdc[GENWQE_DBG_UNITS];
+
+        /* DDCB workqueue */
+        struct task_struct *card_thread;
+        wait_queue_head_t queue_waitq;
+        struct ddcb_queue queue;        /* genwqe DDCB queue */
+        unsigned int irqs_processed;
+
+        /* Card health checking thread */
+        struct task_struct *health_thread;
+        wait_queue_head_t health_waitq;
+
+        /* char device */
+        dev_t  devnum_genwqe;           /* major/minor num card */
+        struct class *class_genwqe;     /* reference to class object */
+        struct device *dev;             /* for device creation */
+        struct cdev cdev_genwqe;        /* char device for card */
+
+        struct dentry *debugfs_root;    /* debugfs card root directory */
+        struct dentry *debugfs_genwqe;  /* debugfs driver root directory */
+
+        /* pci resources */
+        struct pci_dev *pci_dev;        /* PCI device */
+        void __iomem *mmio;             /* BAR-0 MMIO start */
+        unsigned long mmio_len;
+        u16 num_vfs;
+        u32 vf_jobtimeout_msec[GENWQE_MAX_VFS];
+        int is_privileged;              /* access to all regs possible */
+
+        /* config regs which we need often */
+        u64 slu_unitcfg;
+        u64 app_unitcfg;
+        u64 softreset;
+        u64 err_inject;
+        u64 last_gfir;
+        char app_name[5];
+
+        spinlock_t file_lock;           /* lock for open files */
+        struct list_head file_list;     /* list of open files */
+
+        /* debugfs parameters */
+        int ddcb_software_timeout;      /* wait until DDCB times out */
+        int skip_recovery;              /* circumvention if recovery fails */
+        int kill_timeout;               /* wait after sending SIGKILL */
+};
+
+/**
+ * enum genwqe_requ_state - State of a DDCB execution request
+ */
+enum genwqe_requ_state {
+        GENWQE_REQU_NEW      = 0,
+        GENWQE_REQU_ENQUEUED = 1,
+        GENWQE_REQU_TAPPED   = 2,
+        GENWQE_REQU_FINISHED = 3,
+        GENWQE_REQU_STATE_MAX,
+};
+
+/**
+ * struct ddcb_requ - Kernel internal representation of the DDCB request
+ * @cmd:          User space representation of the DDCB execution request
+ */
+struct ddcb_requ {
+        /* kernel specific content */
+        enum genwqe_requ_state req_state; /* request status */
+        int num;                          /* ddcb_no for this request */
+        struct ddcb_queue *queue;         /* associated queue */
+
+        struct dma_mapping  dma_mappings[DDCB_FIXUPS];
+        struct sg_entry     *sgl[DDCB_FIXUPS];
+        dma_addr_t          sgl_dma_addr[DDCB_FIXUPS];
+        size_t              sgl_size[DDCB_FIXUPS];
+
+        /* kernel/user shared content */
+        struct genwqe_ddcb_cmd cmd;     /* ddcb_no for this request */
+        struct genwqe_debug_data debug_data;
+};
+
+/**
+ * struct genwqe_file - Information for open GenWQE devices
+ */
+struct genwqe_file {
+        struct genwqe_dev *cd;
+        struct genwqe_driver *client;
+        struct file *filp;
+
+        struct fasync_struct *async_queue;
+        struct task_struct *owner;
+        struct list_head list;          /* entry in list of open files */
+
+        spinlock_t map_lock;            /* lock for dma_mappings */
+        struct list_head map_list;      /* list of dma_mappings */
+
+        spinlock_t pin_lock;            /* lock for pinned memory */
+        struct list_head pin_list;      /* list of pinned memory */
+};
+
+int  genwqe_setup_service_layer(struct genwqe_dev *cd); /* for PF only */
+int  genwqe_finish_queue(struct genwqe_dev *cd);
+int  genwqe_release_service_layer(struct genwqe_dev *cd);
+
+/**
+ * genwqe_get_slu_id() - Read Service Layer Unit Id
+ * Return: 0x00: Development code
+ *         0x01: SLC1 (old)
+ *         0x02: SLC2 (sept2012)
+ *         0x03: SLC2 (feb2013, generic driver)
+ */
+static inline int genwqe_get_slu_id(struct genwqe_dev *cd)
+{
+        return (int)((cd->slu_unitcfg >> 32) & 0xff);
+}
+
+int  genwqe_ddcbs_in_flight(struct genwqe_dev *cd);
+
+u8   genwqe_card_type(struct genwqe_dev *cd);
+int  genwqe_card_reset(struct genwqe_dev *cd);
+int  genwqe_set_interrupt_capability(struct genwqe_dev *cd, int count);
+void genwqe_reset_interrupt_capability(struct genwqe_dev *cd);
+
+int  genwqe_device_create(struct genwqe_dev *cd);
+int  genwqe_device_remove(struct genwqe_dev *cd);
+
+/* debugfs */
+int  genwqe_init_debugfs(struct genwqe_dev *cd);
+void genqwe_exit_debugfs(struct genwqe_dev *cd);
+
+int  genwqe_read_softreset(struct genwqe_dev *cd);
+
+/* Hardware Circumventions */
+int  genwqe_recovery_on_fatal_gfir_required(struct genwqe_dev *cd);
+int  genwqe_flash_readback_fails(struct genwqe_dev *cd);
+
+/**
+ * genwqe_write_vreg() - Write register in VF window
+ * @cd:    genwqe device
+ * @reg:   register address
+ * @val:   value to write
+ * @func:  0: PF, 1: VF0, ..., 15: VF14
+ */
+int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func);
+
+/**
+ * genwqe_read_vreg() - Read register in VF window
+ * @cd:    genwqe device
+ * @reg:   register address
+ * @func:  0: PF, 1: VF0, ..., 15: VF14
+ *
+ * Return: content of the register
+ */
+u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func);
+
+/* FFDC Buffer Management */
+int  genwqe_ffdc_buff_size(struct genwqe_dev *cd, int unit_id);
+int  genwqe_ffdc_buff_read(struct genwqe_dev *cd, int unit_id,
+                           struct genwqe_reg *regs, unsigned int max_regs);
+int  genwqe_read_ffdc_regs(struct genwqe_dev *cd, struct genwqe_reg *regs,
+                           unsigned int max_regs, int all);
+int  genwqe_ffdc_dump_dma(struct genwqe_dev *cd,
+                          struct genwqe_reg *regs, unsigned int max_regs);
+
+int  genwqe_init_debug_data(struct genwqe_dev *cd,
+                            struct genwqe_debug_data *d);
+
+void genwqe_init_crc32(void);
+int  genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len);
+
+/* Memory allocation/deallocation; dma address handling */
+int  genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m,
+                      void *uaddr, unsigned long size,
+                      struct ddcb_requ *req);
+
+int  genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m,
+                        struct ddcb_requ *req);
+
+struct sg_entry *genwqe_alloc_sgl(struct genwqe_dev *cd, int num_pages,
+                                 dma_addr_t *dma_addr, size_t *sgl_size);
+
+void genwqe_free_sgl(struct genwqe_dev *cd, struct sg_entry *sg_list,
+                    dma_addr_t dma_addr, size_t size);
+
+int genwqe_setup_sgl(struct genwqe_dev *cd,
+                    unsigned long offs,
+                    unsigned long size,
+                    struct sg_entry *sgl, /* genwqe sgl */
+                    dma_addr_t dma_addr, size_t sgl_size,
+                    dma_addr_t *dma_list, int page_offs, int num_pages);
+
+int genwqe_check_sgl(struct genwqe_dev *cd, struct sg_entry *sg_list,
+                     int size);
+
+static inline bool dma_mapping_used(struct dma_mapping *m)
+{
+        if (!m)
+                return 0;
+        return m->size != 0;
+}
+
+/**
+ * __genwqe_execute_ddcb() - Execute DDCB request with addr translation
+ *
+ * This function will do the address translation changes to the DDCBs
+ * according to the definitions required by the ATS field. It looks up
+ * the memory allocation buffer or does vmap/vunmap for the respective
+ * user-space buffers, inclusive page pinning and scatter gather list
+ * buildup and teardown.
+ */
+int  __genwqe_execute_ddcb(struct genwqe_dev *cd,
+                           struct genwqe_ddcb_cmd *cmd);
+
+/**
+ * __genwqe_execute_raw_ddcb() - Execute DDCB request without addr translation
+ *
+ * This version will not do address translation or any modifcation of
+ * the DDCB data. It is used e.g. for the MoveFlash DDCB which is
+ * entirely prepared by the driver itself. That means the appropriate
+ * DMA addresses are already in the DDCB and do not need any
+ * modification.
+ */
+int  __genwqe_execute_raw_ddcb(struct genwqe_dev *cd,
+                               struct genwqe_ddcb_cmd *cmd);
+
+int  __genwqe_enqueue_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req);
+int  __genwqe_wait_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req);
+int  __genwqe_purge_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req);
+
+/* register access */
+int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val);
+u64 __genwqe_readq(struct genwqe_dev *cd, u64 byte_offs);
+int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val);
+u32 __genwqe_readl(struct genwqe_dev *cd, u64 byte_offs);
+
+void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size,
+                                 dma_addr_t *dma_handle);
+void __genwqe_free_consistent(struct genwqe_dev *cd, size_t size,
+                              void *vaddr, dma_addr_t dma_handle);
+
+/* Base clock frequency in MHz */
+int  genwqe_base_clock_frequency(struct genwqe_dev *cd);
+
+/* Before FFDC is captured the traps should be stopped. */
+void genwqe_stop_traps(struct genwqe_dev *cd);
+void genwqe_start_traps(struct genwqe_dev *cd);
+
+/* Hardware circumvention */
+bool genwqe_need_err_masking(struct genwqe_dev *cd);
+
+/**
+ * genwqe_is_privileged() - Determine operation mode for PCI function
+ *
+ * On Intel with SRIOV support we see:
+ *   PF: is_physfn = 1 is_virtfn = 0
+ *   VF: is_physfn = 0 is_virtfn = 1
+ *
+ * On Systems with no SRIOV support _and_ virtualized systems we get:
+ *       is_physfn = 0 is_virtfn = 0
+ *
+ * Other vendors have individual pci device ids to distinguish between
+ * virtual function drivers and physical function drivers. GenWQE
+ * unfortunately has just on pci device id for both, VFs and PF.
+ *
+ * The following code is used to distinguish if the card is running in
+ * privileged mode, either as true PF or in a virtualized system with
+ * full register access e.g. currently on PowerPC.
+ *
+ * if (pci_dev->is_virtfn)
+ *          cd->is_privileged = 0;
+ *  else
+ *          cd->is_privileged = (__genwqe_readq(cd, IO_SLU_BITSTREAM)
+ *                               != IO_ILLEGAL_VALUE);
+ */
+static inline int genwqe_is_privileged(struct genwqe_dev *cd)
+{
+        return cd->is_privileged;
+}
+
+#endif  /* __CARD_BASE_H__ */
diff --git a/drivers/misc/genwqe/card_ddcb.c b/drivers/misc/genwqe/card_ddcb.c
new file mode 100644
index 000000000000..6f1acc0ccf88
--- /dev/null
+++ b/drivers/misc/genwqe/card_ddcb.c
@@ -0,0 +1,1376 @@
+/**
+ * IBM Accelerator Family 'GenWQE'
+ *
+ * (C) Copyright IBM Corp. 2013
+ *
+ * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
+ * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
+ * Author: Michael Jung <mijung@de.ibm.com>
+ * Author: Michael Ruettger <michael@ibmra.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Device Driver Control Block (DDCB) queue support. Definition of
+ * interrupt handlers for queue support as well as triggering the
+ * health monitor code in case of problems. The current hardware uses
+ * an MSI interrupt which is shared between error handling and
+ * functional code.
+ */
+
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/pci.h>
+#include <linux/string.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/crc-itu-t.h>
+
+#include "card_base.h"
+#include "card_ddcb.h"
+
+/*
+ * N: next DDCB, this is where the next DDCB will be put.
+ * A: active DDCB, this is where the code will look for the next completion.
+ * x: DDCB is enqueued, we are waiting for its completion.
+
+ * Situation (1): Empty queue
+ *  +---+---+---+---+---+---+---+---+
+ *  | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
+ *  |   |   |   |   |   |   |   |   |
+ *  +---+---+---+---+---+---+---+---+
+ *           A/N
+ *  enqueued_ddcbs = A - N = 2 - 2 = 0
+ *
+ * Situation (2): Wrapped, N > A
+ *  +---+---+---+---+---+---+---+---+
+ *  | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
+ *  |   |   | x | x |   |   |   |   |
+ *  +---+---+---+---+---+---+---+---+
+ *            A       N
+ *  enqueued_ddcbs = N - A = 4 - 2 = 2
+ *
+ * Situation (3): Queue wrapped, A > N
+ *  +---+---+---+---+---+---+---+---+
+ *  | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
+ *  | x | x |   |   | x | x | x | x |
+ *  +---+---+---+---+---+---+---+---+
+ *            N       A
+ *  enqueued_ddcbs = queue_max  - (A - N) = 8 - (4 - 2) = 6
+ *
+ * Situation (4a): Queue full N > A
+ *  +---+---+---+---+---+---+---+---+
+ *  | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
+ *  | x | x | x | x | x | x | x |   |
+ *  +---+---+---+---+---+---+---+---+
+ *    A                           N
+ *
+ *  enqueued_ddcbs = N - A = 7 - 0 = 7
+ *
+ * Situation (4a): Queue full A > N
+ *  +---+---+---+---+---+---+---+---+
+ *  | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
+ *  | x | x | x |   | x | x | x | x |
+ *  +---+---+---+---+---+---+---+---+
+ *                N   A
+ *  enqueued_ddcbs = queue_max - (A - N) = 8 - (4 - 3) = 7
+ */
+
+static int queue_empty(struct ddcb_queue *queue)
+{
+        return queue->ddcb_next == queue->ddcb_act;
+}
+
+static int queue_enqueued_ddcbs(struct ddcb_queue *queue)
+{
+        if (queue->ddcb_next >= queue->ddcb_act)
+                return queue->ddcb_next - queue->ddcb_act;
+
+        return queue->ddcb_max - (queue->ddcb_act - queue->ddcb_next);
+}
+
+static int queue_free_ddcbs(struct ddcb_queue *queue)
+{
+        int free_ddcbs = queue->ddcb_max - queue_enqueued_ddcbs(queue) - 1;
+
+        if (WARN_ON_ONCE(free_ddcbs < 0)) { /* must never ever happen! */
+                return 0;
+        }
+        return free_ddcbs;
+}
+
+/*
+ * Use of the PRIV field in the DDCB for queue debugging:
+ *
+ * (1) Trying to get rid of a DDCB which saw a timeout:
+ *     pddcb->priv[6] = 0xcc;   # cleared
+ *
+ * (2) Append a DDCB via NEXT bit:
+ *     pddcb->priv[7] = 0xaa;   # appended
+ *
+ * (3) DDCB needed tapping:
+ *     pddcb->priv[7] = 0xbb;   # tapped
+ *
+ * (4) DDCB marked as correctly finished:
+ *     pddcb->priv[6] = 0xff;   # finished
+ */
+
+static inline void ddcb_mark_tapped(struct ddcb *pddcb)
+{
+        pddcb->priv[7] = 0xbb;  /* tapped */
+}
+
+static inline void ddcb_mark_appended(struct ddcb *pddcb)
+{
+        pddcb->priv[7] = 0xaa;  /* appended */
+}
+
+static inline void ddcb_mark_cleared(struct ddcb *pddcb)
+{
+        pddcb->priv[6] = 0xcc; /* cleared */
+}
+
+static inline void ddcb_mark_finished(struct ddcb *pddcb)
+{
+        pddcb->priv[6] = 0xff;  /* finished */
+}
+
+static inline void ddcb_mark_unused(struct ddcb *pddcb)
+{
+        pddcb->priv_64 = cpu_to_be64(0); /* not tapped */
+}
+
+/**
+ * genwqe_crc16() - Generate 16-bit crc as required for DDCBs
+ * @buff:       pointer to data buffer
+ * @len:        length of data for calculation
+ * @init:       initial crc (0xffff at start)
+ *
+ * Polynomial = x^16 + x^12 + x^5 + 1   (0x1021)
+ * Example: 4 bytes 0x01 0x02 0x03 0x04 with init = 0xffff
+ *          should result in a crc16 of 0x89c3
+ *
+ * Return: crc16 checksum in big endian format !
+ */
+static inline u16 genwqe_crc16(const u8 *buff, size_t len, u16 init)
+{
+        return crc_itu_t(init, buff, len);
+}
+
+static void print_ddcb_info(struct genwqe_dev *cd, struct ddcb_queue *queue)
+{
+        int i;
+        struct ddcb *pddcb;
+        unsigned long flags;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        spin_lock_irqsave(&cd->print_lock, flags);
+
+        dev_info(&pci_dev->dev,
+                 "DDCB list for card #%d (ddcb_act=%d / ddcb_next=%d):\n",
+                 cd->card_idx, queue->ddcb_act, queue->ddcb_next);
+
+        pddcb = queue->ddcb_vaddr;
+        for (i = 0; i < queue->ddcb_max; i++) {
+                dev_err(&pci_dev->dev,
+                        "  %c %-3d: RETC=%03x SEQ=%04x "
+                        "HSI=%02X SHI=%02x PRIV=%06llx CMD=%03x\n",
+                        i == queue->ddcb_act ? '>' : ' ',
+                        i,
+                        be16_to_cpu(pddcb->retc_16),
+                        be16_to_cpu(pddcb->seqnum_16),
+                        pddcb->hsi,
+                        pddcb->shi,
+                        be64_to_cpu(pddcb->priv_64),
+                        pddcb->cmd);
+                pddcb++;
+        }
+        spin_unlock_irqrestore(&cd->print_lock, flags);
+}
+
+struct genwqe_ddcb_cmd *ddcb_requ_alloc(void)
+{
+        struct ddcb_requ *req;
+
+        req = kzalloc(sizeof(*req), GFP_ATOMIC);
+        if (!req)
+                return NULL;
+
+        return &req->cmd;
+}
+
+void ddcb_requ_free(struct genwqe_ddcb_cmd *cmd)
+{
+        struct ddcb_requ *req = container_of(cmd, struct ddcb_requ, cmd);
+        kfree(req);
+}
+
+static inline enum genwqe_requ_state ddcb_requ_get_state(struct ddcb_requ *req)
+{
+        return req->req_state;
+}
+
+static inline void ddcb_requ_set_state(struct ddcb_requ *req,
+                                       enum genwqe_requ_state new_state)
+{
+        req->req_state = new_state;
+}
+
+static inline int ddcb_requ_collect_debug_data(struct ddcb_requ *req)
+{
+        return req->cmd.ddata_addr != 0x0;
+}
+
+/**
+ * ddcb_requ_finished() - Returns the hardware state of the associated DDCB
+ * @cd:          pointer to genwqe device descriptor
+ * @req:         DDCB work request
+ *
+ * Status of ddcb_requ mirrors this hardware state, but is copied in
+ * the ddcb_requ on interrupt/polling function. The lowlevel code
+ * should check the hardware state directly, the higher level code
+ * should check the copy.
+ *
+ * This function will also return true if the state of the queue is
+ * not GENWQE_CARD_USED. This enables us to purge all DDCBs in the
+ * shutdown case.
+ */
+static int ddcb_requ_finished(struct genwqe_dev *cd, struct ddcb_requ *req)
+{
+        return (ddcb_requ_get_state(req) == GENWQE_REQU_FINISHED) ||
+                (cd->card_state != GENWQE_CARD_USED);
+}
+
+/**
+ * enqueue_ddcb() - Enqueue a DDCB
+ * @cd:         pointer to genwqe device descriptor
+ * @queue:      queue this operation should be done on
+ * @ddcb_no:    pointer to ddcb number being tapped
+ *
+ * Start execution of DDCB by tapping or append to queue via NEXT
+ * bit. This is done by an atomic 'compare and swap' instruction and
+ * checking SHI and HSI of the previous DDCB.
+ *
+ * This function must only be called with ddcb_lock held.
+ *
+ * Return: 1 if new DDCB is appended to previous
+ *         2 if DDCB queue is tapped via register/simulation
+ */
+#define RET_DDCB_APPENDED 1
+#define RET_DDCB_TAPPED   2
+
+static int enqueue_ddcb(struct genwqe_dev *cd, struct ddcb_queue *queue,
+                        struct ddcb *pddcb, int ddcb_no)
+{
+        unsigned int try;
+        int prev_no;
+        struct ddcb *prev_ddcb;
+        __be32 old, new, icrc_hsi_shi;
+        u64 num;
+
+        /*
+         * For performance checks a Dispatch Timestamp can be put into
+         * DDCB It is supposed to use the SLU's free running counter,
+         * but this requires PCIe cycles.
+         */
+        ddcb_mark_unused(pddcb);
+
+        /* check previous DDCB if already fetched */
+        prev_no = (ddcb_no == 0) ? queue->ddcb_max - 1 : ddcb_no - 1;
+        prev_ddcb = &queue->ddcb_vaddr[prev_no];
+
+        /*
+         * It might have happened that the HSI.FETCHED bit is
+         * set. Retry in this case. Therefore I expect maximum 2 times
+         * trying.
+         */
+        ddcb_mark_appended(pddcb);
+        for (try = 0; try < 2; try++) {
+                old = prev_ddcb->icrc_hsi_shi_32; /* read SHI/HSI in BE32 */
+
+                /* try to append via NEXT bit if prev DDCB is not completed */
+                if ((old & DDCB_COMPLETED_BE32) != 0x00000000)
+                        break;
+
+                new = (old | DDCB_NEXT_BE32);
+                icrc_hsi_shi = cmpxchg(&prev_ddcb->icrc_hsi_shi_32, old, new);
+
+                if (icrc_hsi_shi == old)
+                        return RET_DDCB_APPENDED; /* appended to queue */
+        }
+
+        /* Queue must be re-started by updating QUEUE_OFFSET */
+        ddcb_mark_tapped(pddcb);
+        num = (u64)ddcb_no << 8;
+        __genwqe_writeq(cd, queue->IO_QUEUE_OFFSET, num); /* start queue */
+
+        return RET_DDCB_TAPPED;
+}
+
+/**
+ * copy_ddcb_results() - Copy output state from real DDCB to request
+ *
+ * Copy DDCB ASV to request struct. There is no endian
+ * conversion made, since data structure in ASV is still
+ * unknown here.
+ *
+ * This is needed by:
+ *   - genwqe_purge_ddcb()
+ *   - genwqe_check_ddcb_queue()
+ */
+static void copy_ddcb_results(struct ddcb_requ *req, int ddcb_no)
+{
+        struct ddcb_queue *queue = req->queue;
+        struct ddcb *pddcb = &queue->ddcb_vaddr[req->num];
+
+        memcpy(&req->cmd.asv[0], &pddcb->asv[0], DDCB_ASV_LENGTH);
+
+        /* copy status flags of the variant part */
+        req->cmd.vcrc     = be16_to_cpu(pddcb->vcrc_16);
+        req->cmd.deque_ts = be64_to_cpu(pddcb->deque_ts_64);
+        req->cmd.cmplt_ts = be64_to_cpu(pddcb->cmplt_ts_64);
+
+        req->cmd.attn     = be16_to_cpu(pddcb->attn_16);
+        req->cmd.progress = be32_to_cpu(pddcb->progress_32);
+        req->cmd.retc     = be16_to_cpu(pddcb->retc_16);
+
+        if (ddcb_requ_collect_debug_data(req)) {
+                int prev_no = (ddcb_no == 0) ?
+                        queue->ddcb_max - 1 : ddcb_no - 1;
+                struct ddcb *prev_pddcb = &queue->ddcb_vaddr[prev_no];
+
+                memcpy(&req->debug_data.ddcb_finished, pddcb,
+                       sizeof(req->debug_data.ddcb_finished));
+                memcpy(&req->debug_data.ddcb_prev, prev_pddcb,
+                       sizeof(req->debug_data.ddcb_prev));
+        }
+}
+
+/**
+ * genwqe_check_ddcb_queue() - Checks DDCB queue for completed work equests.
+ * @cd:         pointer to genwqe device descriptor
+ *
+ * Return: Number of DDCBs which were finished
+ */
+static int genwqe_check_ddcb_queue(struct genwqe_dev *cd,
+                                   struct ddcb_queue *queue)
+{
+        unsigned long flags;
+        int ddcbs_finished = 0;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        spin_lock_irqsave(&queue->ddcb_lock, flags);
+
+        /* FIXME avoid soft locking CPU */
+        while (!queue_empty(queue) && (ddcbs_finished < queue->ddcb_max)) {
+
+                struct ddcb *pddcb;
+                struct ddcb_requ *req;
+                u16 vcrc, vcrc_16, retc_16;
+
+                pddcb = &queue->ddcb_vaddr[queue->ddcb_act];
+
+                if ((pddcb->icrc_hsi_shi_32 & DDCB_COMPLETED_BE32) ==
+                    0x00000000)
+                        goto go_home; /* not completed, continue waiting */
+
+                /* Note: DDCB could be purged */
+
+                req = queue->ddcb_req[queue->ddcb_act];
+                if (req == NULL) {
+                        /* this occurs if DDCB is purged, not an error */
+                        /* Move active DDCB further; Nothing to do anymore. */
+                        goto pick_next_one;
+                }
+
+                /*
+                 * HSI=0x44 (fetched and completed), but RETC is
+                 * 0x101, or even worse 0x000.
+                 *
+                 * In case of seeing the queue in inconsistent state
+                 * we read the errcnts and the queue status to provide
+                 * a trigger for our PCIe analyzer stop capturing.
+                 */
+                retc_16 = be16_to_cpu(pddcb->retc_16);
+                if ((pddcb->hsi == 0x44) && (retc_16 <= 0x101)) {
+                        u64 errcnts, status;
+                        u64 ddcb_offs = (u64)pddcb - (u64)queue->ddcb_vaddr;
+
+                        errcnts = __genwqe_readq(cd, queue->IO_QUEUE_ERRCNTS);
+                        status  = __genwqe_readq(cd, queue->IO_QUEUE_STATUS);
+
+                        dev_err(&pci_dev->dev,
+                                "[%s] SEQN=%04x HSI=%02x RETC=%03x "
+                                " Q_ERRCNTS=%016llx Q_STATUS=%016llx\n"
+                                " DDCB_DMA_ADDR=%016llx\n",
+                                __func__, be16_to_cpu(pddcb->seqnum_16),
+                                pddcb->hsi, retc_16, errcnts, status,
+                                queue->ddcb_daddr + ddcb_offs);
+                }
+
+                copy_ddcb_results(req, queue->ddcb_act);
+                queue->ddcb_req[queue->ddcb_act] = NULL; /* take from queue */
+
+                dev_dbg(&pci_dev->dev, "FINISHED DDCB#%d\n", req->num);
+                genwqe_hexdump(pci_dev, pddcb, sizeof(*pddcb));
+
+                ddcb_mark_finished(pddcb);
+
+                /* calculate CRC_16 to see if VCRC is correct */
+                vcrc = genwqe_crc16(pddcb->asv,
+                                   VCRC_LENGTH(req->cmd.asv_length),
+                                   0xffff);
+                vcrc_16 = be16_to_cpu(pddcb->vcrc_16);
+                if (vcrc != vcrc_16) {
+                        printk_ratelimited(KERN_ERR
+                                "%s %s: err: wrong VCRC pre=%02x vcrc_len=%d "
+                                "bytes vcrc_data=%04x is not vcrc_card=%04x\n",
+                                GENWQE_DEVNAME, dev_name(&pci_dev->dev),
+                                pddcb->pre, VCRC_LENGTH(req->cmd.asv_length),
+                                vcrc, vcrc_16);
+                }
+
+                ddcb_requ_set_state(req, GENWQE_REQU_FINISHED);
+                queue->ddcbs_completed++;
+                queue->ddcbs_in_flight--;
+
+                /* wake up process waiting for this DDCB */
+                wake_up_interruptible(&queue->ddcb_waitqs[queue->ddcb_act]);
+
+pick_next_one:
+                queue->ddcb_act = (queue->ddcb_act + 1) % queue->ddcb_max;
+                ddcbs_finished++;
+        }
+
+ go_home:
+        spin_unlock_irqrestore(&queue->ddcb_lock, flags);
+        return ddcbs_finished;
+}
+
+/**
+ * __genwqe_wait_ddcb(): Waits until DDCB is completed
+ * @cd:         pointer to genwqe device descriptor
+ * @req:        pointer to requsted DDCB parameters
+ *
+ * The Service Layer will update the RETC in DDCB when processing is
+ * pending or done.
+ *
+ * Return: > 0 remaining jiffies, DDCB completed
+ *           -ETIMEDOUT when timeout
+ *           -ERESTARTSYS when ^C
+ *           -EINVAL when unknown error condition
+ *
+ * When an error is returned the called needs to ensure that
+ * purge_ddcb() is being called to get the &req removed from the
+ * queue.
+ */
+int __genwqe_wait_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req)
+{
+        int rc;
+        unsigned int ddcb_no;
+        struct ddcb_queue *queue;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if (req == NULL)
+                return -EINVAL;
+
+        queue = req->queue;
+        if (queue == NULL)
+                return -EINVAL;
+
+        ddcb_no = req->num;
+        if (ddcb_no >= queue->ddcb_max)
+                return -EINVAL;
+
+        rc = wait_event_interruptible_timeout(queue->ddcb_waitqs[ddcb_no],
+                                ddcb_requ_finished(cd, req),
+                                genwqe_ddcb_software_timeout * HZ);
+
+        /*
+         * We need to distinguish 3 cases here:
+         *   1. rc == 0              timeout occured
+         *   2. rc == -ERESTARTSYS   signal received
+         *   3. rc > 0               remaining jiffies condition is true
+         */
+        if (rc == 0) {
+                struct ddcb_queue *queue = req->queue;
+                struct ddcb *pddcb;
+
+                /*
+                 * Timeout may be caused by long task switching time.
+                 * When timeout happens, check if the request has
+                 * meanwhile completed.
+                 */
+                genwqe_check_ddcb_queue(cd, req->queue);
+                if (ddcb_requ_finished(cd, req))
+                        return rc;
+
+                dev_err(&pci_dev->dev,
+                        "[%s] err: DDCB#%d timeout rc=%d state=%d req @ %p\n",
+                        __func__, req->num, rc, ddcb_requ_get_state(req),
+                        req);
+                dev_err(&pci_dev->dev,
+                        "[%s]      IO_QUEUE_STATUS=0x%016llx\n", __func__,
+                        __genwqe_readq(cd, queue->IO_QUEUE_STATUS));
+
+                pddcb = &queue->ddcb_vaddr[req->num];
+                genwqe_hexdump(pci_dev, pddcb, sizeof(*pddcb));
+
+                print_ddcb_info(cd, req->queue);
+                return -ETIMEDOUT;
+
+        } else if (rc == -ERESTARTSYS) {
+                return rc;
+                /*
+                 * EINTR:       Stops the application
+                 * ERESTARTSYS: Restartable systemcall; called again
+                 */
+
+        } else if (rc < 0) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: DDCB#%d unknown result (rc=%d) %d!\n",
+                        __func__, req->num, rc, ddcb_requ_get_state(req));
+                return -EINVAL;
+        }
+
+        /* Severe error occured. Driver is forced to stop operation */
+        if (cd->card_state != GENWQE_CARD_USED) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: DDCB#%d forced to stop (rc=%d)\n",
+                        __func__, req->num, rc);
+                return -EIO;
+        }
+        return rc;
+}
+
+/**
+ * get_next_ddcb() - Get next available DDCB
+ * @cd:         pointer to genwqe device descriptor
+ *
+ * DDCB's content is completely cleared but presets for PRE and
+ * SEQNUM. This function must only be called when ddcb_lock is held.
+ *
+ * Return: NULL if no empty DDCB available otherwise ptr to next DDCB.
+ */
+static struct ddcb *get_next_ddcb(struct genwqe_dev *cd,
+                                  struct ddcb_queue *queue,
+                                  int *num)
+{
+        u64 *pu64;
+        struct ddcb *pddcb;
+
+        if (queue_free_ddcbs(queue) == 0) /* queue is  full */
+                return NULL;
+
+        /* find new ddcb */
+        pddcb = &queue->ddcb_vaddr[queue->ddcb_next];
+
+        /* if it is not completed, we are not allowed to use it */
+        /* barrier(); */
+        if ((pddcb->icrc_hsi_shi_32 & DDCB_COMPLETED_BE32) == 0x00000000)
+                return NULL;
+
+        *num = queue->ddcb_next;        /* internal DDCB number */
+        queue->ddcb_next = (queue->ddcb_next + 1) % queue->ddcb_max;
+
+        /* clear important DDCB fields */
+        pu64 = (u64 *)pddcb;
+        pu64[0] = 0ULL;         /* offs 0x00 (ICRC,HSI,SHI,...) */
+        pu64[1] = 0ULL;         /* offs 0x01 (ACFUNC,CMD...) */
+
+        /* destroy previous results in ASV */
+        pu64[0x80/8] = 0ULL;    /* offs 0x80 (ASV + 0) */
+        pu64[0x88/8] = 0ULL;    /* offs 0x88 (ASV + 0x08) */
+        pu64[0x90/8] = 0ULL;    /* offs 0x90 (ASV + 0x10) */
+        pu64[0x98/8] = 0ULL;    /* offs 0x98 (ASV + 0x18) */
+        pu64[0xd0/8] = 0ULL;    /* offs 0xd0 (RETC,ATTN...) */
+
+        pddcb->pre = DDCB_PRESET_PRE; /* 128 */
+        pddcb->seqnum_16 = cpu_to_be16(queue->ddcb_seq++);
+        return pddcb;
+}
+
+/**
+ * __genwqe_purge_ddcb() - Remove a DDCB from the workqueue
+ * @cd:         genwqe device descriptor
+ * @req:        DDCB request
+ *
+ * This will fail when the request was already FETCHED. In this case
+ * we need to wait until it is finished. Else the DDCB can be
+ * reused. This function also ensures that the request data structure
+ * is removed from ddcb_req[].
+ *
+ * Do not forget to call this function when genwqe_wait_ddcb() fails,
+ * such that the request gets really removed from ddcb_req[].
+ *
+ * Return: 0 success
+ */
+int __genwqe_purge_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req)
+{
+        struct ddcb *pddcb = NULL;
+        unsigned int t;
+        unsigned long flags;
+        struct ddcb_queue *queue = req->queue;
+        struct pci_dev *pci_dev = cd->pci_dev;
+        u64 queue_status;
+        __be32 icrc_hsi_shi = 0x0000;
+        __be32 old, new;
+
+        /* unsigned long flags; */
+        if (genwqe_ddcb_software_timeout <= 0) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: software timeout is not set!\n", __func__);
+                return -EFAULT;
+        }
+
+        pddcb = &queue->ddcb_vaddr[req->num];
+
+        for (t = 0; t < genwqe_ddcb_software_timeout * 10; t++) {
+
+                spin_lock_irqsave(&queue->ddcb_lock, flags);
+
+                /* Check if req was meanwhile finished */
+                if (ddcb_requ_get_state(req) == GENWQE_REQU_FINISHED)
+                        goto go_home;
+
+                /* try to set PURGE bit if FETCHED/COMPLETED are not set */
+                old = pddcb->icrc_hsi_shi_32;   /* read SHI/HSI in BE32 */
+                if ((old & DDCB_FETCHED_BE32) == 0x00000000) {
+
+                        new = (old | DDCB_PURGE_BE32);
+                        icrc_hsi_shi = cmpxchg(&pddcb->icrc_hsi_shi_32,
+                                               old, new);
+                        if (icrc_hsi_shi == old)
+                                goto finish_ddcb;
+                }
+
+                /* normal finish with HSI bit */
+                barrier();
+                icrc_hsi_shi = pddcb->icrc_hsi_shi_32;
+                if (icrc_hsi_shi & DDCB_COMPLETED_BE32)
+                        goto finish_ddcb;
+
+                spin_unlock_irqrestore(&queue->ddcb_lock, flags);
+
+                /*
+                 * Here the check_ddcb() function will most likely
+                 * discover this DDCB to be finished some point in
+                 * time. It will mark the req finished and free it up
+                 * in the list.
+                 */
+
+                copy_ddcb_results(req, req->num); /* for the failing case */
+                msleep(100); /* sleep for 1/10 second and try again */
+                continue;
+
+finish_ddcb:
+                copy_ddcb_results(req, req->num);
+                ddcb_requ_set_state(req, GENWQE_REQU_FINISHED);
+                queue->ddcbs_in_flight--;
+                queue->ddcb_req[req->num] = NULL; /* delete from array */
+                ddcb_mark_cleared(pddcb);
+
+                /* Move active DDCB further; Nothing to do here anymore. */
+
+                /*
+                 * We need to ensure that there is at least one free
+                 * DDCB in the queue. To do that, we must update
+                 * ddcb_act only if the COMPLETED bit is set for the
+                 * DDCB we are working on else we treat that DDCB even
+                 * if we PURGED it as occupied (hardware is supposed
+                 * to set the COMPLETED bit yet!).
+                 */
+                icrc_hsi_shi = pddcb->icrc_hsi_shi_32;
+                if ((icrc_hsi_shi & DDCB_COMPLETED_BE32) &&
+                    (queue->ddcb_act == req->num)) {
+                        queue->ddcb_act = ((queue->ddcb_act + 1) %
+                                           queue->ddcb_max);
+                }
+go_home:
+                spin_unlock_irqrestore(&queue->ddcb_lock, flags);
+                return 0;
+        }
+
+        /*
+         * If the card is dead and the queue is forced to stop, we
+         * might see this in the queue status register.
+         */
+        queue_status = __genwqe_readq(cd, queue->IO_QUEUE_STATUS);
+
+        dev_dbg(&pci_dev->dev, "UN/FINISHED DDCB#%d\n", req->num);
+        genwqe_hexdump(pci_dev, pddcb, sizeof(*pddcb));
+
+        dev_err(&pci_dev->dev,
+                "[%s] err: DDCB#%d not purged and not completed "
+                "after %d seconds QSTAT=%016llx!!\n",
+                __func__, req->num, genwqe_ddcb_software_timeout,
+                queue_status);
+
+        print_ddcb_info(cd, req->queue);
+
+        return -EFAULT;
+}
+
+int genwqe_init_debug_data(struct genwqe_dev *cd, struct genwqe_debug_data *d)
+{
+        int len;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if (d == NULL) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: invalid memory for debug data!\n",
+                        __func__);
+                return -EFAULT;
+        }
+
+        len  = sizeof(d->driver_version);
+        snprintf(d->driver_version, len, "%s", DRV_VERS_STRING);
+        d->slu_unitcfg = cd->slu_unitcfg;
+        d->app_unitcfg = cd->app_unitcfg;
+        return 0;
+}
+
+/**
+ * __genwqe_enqueue_ddcb() - Enqueue a DDCB
+ * @cd:          pointer to genwqe device descriptor
+ * @req:         pointer to DDCB execution request
+ *
+ * Return: 0 if enqueuing succeeded
+ *         -EIO if card is unusable/PCIe problems
+ *         -EBUSY if enqueuing failed
+ */
+int __genwqe_enqueue_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req)
+{
+        struct ddcb *pddcb;
+        unsigned long flags;
+        struct ddcb_queue *queue;
+        struct pci_dev *pci_dev = cd->pci_dev;
+        u16 icrc;
+
+        if (cd->card_state != GENWQE_CARD_USED) {
+                printk_ratelimited(KERN_ERR
+                        "%s %s: [%s] Card is unusable/PCIe problem Req#%d\n",
+                        GENWQE_DEVNAME, dev_name(&pci_dev->dev),
+                        __func__, req->num);
+                return -EIO;
+        }
+
+        queue = req->queue = &cd->queue;
+
+        /* FIXME circumvention to improve performance when no irq is
+         * there.
+         */
+        if (genwqe_polling_enabled)
+                genwqe_check_ddcb_queue(cd, queue);
+
+        /*
+         * It must be ensured to process all DDCBs in successive
+         * order. Use a lock here in order to prevent nested DDCB
+         * enqueuing.
+         */
+        spin_lock_irqsave(&queue->ddcb_lock, flags);
+
+        pddcb = get_next_ddcb(cd, queue, &req->num);    /* get ptr and num */
+        if (pddcb == NULL) {
+                spin_unlock_irqrestore(&queue->ddcb_lock, flags);
+                queue->busy++;
+                return -EBUSY;
+        }
+
+        if (queue->ddcb_req[req->num] != NULL) {
+                spin_unlock_irqrestore(&queue->ddcb_lock, flags);
+
+                dev_err(&pci_dev->dev,
+                        "[%s] picked DDCB %d with req=%p still in use!!\n",
+                        __func__, req->num, req);
+                return -EFAULT;
+        }
+        ddcb_requ_set_state(req, GENWQE_REQU_ENQUEUED);
+        queue->ddcb_req[req->num] = req;
+
+        pddcb->cmdopts_16 = cpu_to_be16(req->cmd.cmdopts);
+        pddcb->cmd = req->cmd.cmd;
+        pddcb->acfunc = req->cmd.acfunc;        /* functional unit */
+
+        /*
+         * We know that we can get retc 0x104 with CRC error, do not
+         * stop the queue in those cases for this command. XDIR = 1
+         * does not work for old SLU versions.
+         *
+         * Last bitstream with the old XDIR behavior had SLU_ID
+         * 0x34199.
+         */
+        if ((cd->slu_unitcfg & 0xFFFF0ull) > 0x34199ull)
+                pddcb->xdir = 0x1;
+        else
+                pddcb->xdir = 0x0;
+
+
+        pddcb->psp = (((req->cmd.asiv_length / 8) << 4) |
+                      ((req->cmd.asv_length  / 8)));
+        pddcb->disp_ts_64 = cpu_to_be64(req->cmd.disp_ts);
+
+        /*
+         * If copying the whole DDCB_ASIV_LENGTH is impacting
+         * performance we need to change it to
+         * req->cmd.asiv_length. But simulation benefits from some
+         * non-architectured bits behind the architectured content.
+         *
+         * How much data is copied depends on the availability of the
+         * ATS field, which was introduced late. If the ATS field is
+         * supported ASIV is 8 bytes shorter than it used to be. Since
+         * the ATS field is copied too, the code should do exactly
+         * what it did before, but I wanted to make copying of the ATS
+         * field very explicit.
+         */
+        if (genwqe_get_slu_id(cd) <= 0x2) {
+                memcpy(&pddcb->__asiv[0],       /* destination */
+                       &req->cmd.__asiv[0],     /* source */
+                       DDCB_ASIV_LENGTH);       /* req->cmd.asiv_length */
+        } else {
+                pddcb->n.ats_64 = cpu_to_be64(req->cmd.ats);
+                memcpy(&pddcb->n.asiv[0],       /* destination */
+                        &req->cmd.asiv[0],      /* source */
+                        DDCB_ASIV_LENGTH_ATS);  /* req->cmd.asiv_length */
+        }
+
+        pddcb->icrc_hsi_shi_32 = cpu_to_be32(0x00000000); /* for crc */
+
+        /*
+         * Calculate CRC_16 for corresponding range PSP(7:4). Include
+         * empty 4 bytes prior to the data.
+         */
+        icrc = genwqe_crc16((const u8 *)pddcb,
+                           ICRC_LENGTH(req->cmd.asiv_length), 0xffff);
+        pddcb->icrc_hsi_shi_32 = cpu_to_be32((u32)icrc << 16);
+
+        /* enable DDCB completion irq */
+        if (!genwqe_polling_enabled)
+                pddcb->icrc_hsi_shi_32 |= DDCB_INTR_BE32;
+
+        dev_dbg(&pci_dev->dev, "INPUT DDCB#%d\n", req->num);
+        genwqe_hexdump(pci_dev, pddcb, sizeof(*pddcb));
+
+        if (ddcb_requ_collect_debug_data(req)) {
+                /* use the kernel copy of debug data. copying back to
+                   user buffer happens later */
+
+                genwqe_init_debug_data(cd, &req->debug_data);
+                memcpy(&req->debug_data.ddcb_before, pddcb,
+                       sizeof(req->debug_data.ddcb_before));
+        }
+
+        enqueue_ddcb(cd, queue, pddcb, req->num);
+        queue->ddcbs_in_flight++;
+
+        if (queue->ddcbs_in_flight > queue->ddcbs_max_in_flight)
+                queue->ddcbs_max_in_flight = queue->ddcbs_in_flight;
+
+        ddcb_requ_set_state(req, GENWQE_REQU_TAPPED);
+        spin_unlock_irqrestore(&queue->ddcb_lock, flags);
+        wake_up_interruptible(&cd->queue_waitq);
+
+        return 0;
+}
+
+/**
+ * __genwqe_execute_raw_ddcb() - Setup and execute DDCB
+ * @cd:         pointer to genwqe device descriptor
+ * @req:        user provided DDCB request
+ */
+int __genwqe_execute_raw_ddcb(struct genwqe_dev *cd,
+                             struct genwqe_ddcb_cmd *cmd)
+{
+        int rc = 0;
+        struct pci_dev *pci_dev = cd->pci_dev;
+        struct ddcb_requ *req = container_of(cmd, struct ddcb_requ, cmd);
+
+        if (cmd->asiv_length > DDCB_ASIV_LENGTH) {
+                dev_err(&pci_dev->dev, "[%s] err: wrong asiv_length of %d\n",
+                        __func__, cmd->asiv_length);
+                return -EINVAL;
+        }
+        if (cmd->asv_length > DDCB_ASV_LENGTH) {
+                dev_err(&pci_dev->dev, "[%s] err: wrong asv_length of %d\n",
+                        __func__, cmd->asiv_length);
+                return -EINVAL;
+        }
+        rc = __genwqe_enqueue_ddcb(cd, req);
+        if (rc != 0)
+                return rc;
+
+        rc = __genwqe_wait_ddcb(cd, req);
+        if (rc < 0)             /* error or signal interrupt */
+                goto err_exit;
+
+        if (ddcb_requ_collect_debug_data(req)) {
+                if (copy_to_user((struct genwqe_debug_data __user *)
+                                 (unsigned long)cmd->ddata_addr,
+                                 &req->debug_data,
+                                 sizeof(struct genwqe_debug_data)))
+                        return -EFAULT;
+        }
+
+        /*
+         * Higher values than 0x102 indicate completion with faults,
+         * lower values than 0x102 indicate processing faults. Note
+         * that DDCB might have been purged. E.g. Cntl+C.
+         */
+        if (cmd->retc != DDCB_RETC_COMPLETE) {
+                /* This might happen e.g. flash read, and needs to be
+                   handled by the upper layer code. */
+                rc = -EBADMSG;  /* not processed/error retc */
+        }
+
+        return rc;
+
+ err_exit:
+        __genwqe_purge_ddcb(cd, req);
+
+        if (ddcb_requ_collect_debug_data(req)) {
+                if (copy_to_user((struct genwqe_debug_data __user *)
+                                 (unsigned long)cmd->ddata_addr,
+                                 &req->debug_data,
+                                 sizeof(struct genwqe_debug_data)))
+                        return -EFAULT;
+        }
+        return rc;
+}
+
+/**
+ * genwqe_next_ddcb_ready() - Figure out if the next DDCB is already finished
+ *
+ * We use this as condition for our wait-queue code.
+ */
+static int genwqe_next_ddcb_ready(struct genwqe_dev *cd)
+{
+        unsigned long flags;
+        struct ddcb *pddcb;
+        struct ddcb_queue *queue = &cd->queue;
+
+        spin_lock_irqsave(&queue->ddcb_lock, flags);
+
+        if (queue_empty(queue)) { /* emtpy queue */
+                spin_unlock_irqrestore(&queue->ddcb_lock, flags);
+                return 0;
+        }
+
+        pddcb = &queue->ddcb_vaddr[queue->ddcb_act];
+        if (pddcb->icrc_hsi_shi_32 & DDCB_COMPLETED_BE32) { /* ddcb ready */
+                spin_unlock_irqrestore(&queue->ddcb_lock, flags);
+                return 1;
+        }
+
+        spin_unlock_irqrestore(&queue->ddcb_lock, flags);
+        return 0;
+}
+
+/**
+ * genwqe_ddcbs_in_flight() - Check how many DDCBs are in flight
+ *
+ * Keep track on the number of DDCBs which ware currently in the
+ * queue. This is needed for statistics as well as conditon if we want
+ * to wait or better do polling in case of no interrupts available.
+ */
+int genwqe_ddcbs_in_flight(struct genwqe_dev *cd)
+{
+        unsigned long flags;
+        int ddcbs_in_flight = 0;
+        struct ddcb_queue *queue = &cd->queue;
+
+        spin_lock_irqsave(&queue->ddcb_lock, flags);
+        ddcbs_in_flight += queue->ddcbs_in_flight;
+        spin_unlock_irqrestore(&queue->ddcb_lock, flags);
+
+        return ddcbs_in_flight;
+}
+
+static int setup_ddcb_queue(struct genwqe_dev *cd, struct ddcb_queue *queue)
+{
+        int rc, i;
+        struct ddcb *pddcb;
+        u64 val64;
+        unsigned int queue_size;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if (genwqe_ddcb_max < 2)
+                return -EINVAL;
+
+        queue_size = roundup(genwqe_ddcb_max * sizeof(struct ddcb), PAGE_SIZE);
+
+        queue->ddcbs_in_flight = 0;  /* statistics */
+        queue->ddcbs_max_in_flight = 0;
+        queue->ddcbs_completed = 0;
+        queue->busy = 0;
+
+        queue->ddcb_seq   = 0x100; /* start sequence number */
+        queue->ddcb_max   = genwqe_ddcb_max; /* module parameter */
+        queue->ddcb_vaddr = __genwqe_alloc_consistent(cd, queue_size,
+                                                &queue->ddcb_daddr);
+        if (queue->ddcb_vaddr == NULL) {
+                dev_err(&pci_dev->dev,
+                        "[%s] **err: could not allocate DDCB **\n", __func__);
+                return -ENOMEM;
+        }
+        memset(queue->ddcb_vaddr, 0, queue_size);
+
+        queue->ddcb_req = kzalloc(sizeof(struct ddcb_requ *) *
+                                  queue->ddcb_max, GFP_KERNEL);
+        if (!queue->ddcb_req) {
+                rc = -ENOMEM;
+                goto free_ddcbs;
+        }
+
+        queue->ddcb_waitqs = kzalloc(sizeof(wait_queue_head_t) *
+                                     queue->ddcb_max, GFP_KERNEL);
+        if (!queue->ddcb_waitqs) {
+                rc = -ENOMEM;
+                goto free_requs;
+        }
+
+        for (i = 0; i < queue->ddcb_max; i++) {
+                pddcb = &queue->ddcb_vaddr[i];               /* DDCBs */
+                pddcb->icrc_hsi_shi_32 = DDCB_COMPLETED_BE32;
+                pddcb->retc_16 = cpu_to_be16(0xfff);
+
+                queue->ddcb_req[i] = NULL;                   /* requests */
+                init_waitqueue_head(&queue->ddcb_waitqs[i]); /* waitqueues */
+        }
+
+        queue->ddcb_act  = 0;
+        queue->ddcb_next = 0;   /* queue is empty */
+
+        spin_lock_init(&queue->ddcb_lock);
+        init_waitqueue_head(&queue->ddcb_waitq);
+
+        val64 = ((u64)(queue->ddcb_max - 1) <<  8); /* lastptr */
+        __genwqe_writeq(cd, queue->IO_QUEUE_CONFIG,  0x07);  /* iCRC/vCRC */
+        __genwqe_writeq(cd, queue->IO_QUEUE_SEGMENT, queue->ddcb_daddr);
+        __genwqe_writeq(cd, queue->IO_QUEUE_INITSQN, queue->ddcb_seq);
+        __genwqe_writeq(cd, queue->IO_QUEUE_WRAP,    val64);
+        return 0;
+
+ free_requs:
+        kfree(queue->ddcb_req);
+        queue->ddcb_req = NULL;
+ free_ddcbs:
+        __genwqe_free_consistent(cd, queue_size, queue->ddcb_vaddr,
+                                queue->ddcb_daddr);
+        queue->ddcb_vaddr = NULL;
+        queue->ddcb_daddr = 0ull;
+        return -ENODEV;
+
+}
+
+static int ddcb_queue_initialized(struct ddcb_queue *queue)
+{
+        return queue->ddcb_vaddr != NULL;
+}
+
+static void free_ddcb_queue(struct genwqe_dev *cd, struct ddcb_queue *queue)
+{
+        unsigned int queue_size;
+
+        queue_size = roundup(queue->ddcb_max * sizeof(struct ddcb), PAGE_SIZE);
+
+        kfree(queue->ddcb_req);
+        queue->ddcb_req = NULL;
+
+        if (queue->ddcb_vaddr) {
+                __genwqe_free_consistent(cd, queue_size, queue->ddcb_vaddr,
+                                        queue->ddcb_daddr);
+                queue->ddcb_vaddr = NULL;
+                queue->ddcb_daddr = 0ull;
+        }
+}
+
+static irqreturn_t genwqe_pf_isr(int irq, void *dev_id)
+{
+        u64 gfir;
+        struct genwqe_dev *cd = (struct genwqe_dev *)dev_id;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        /*
+         * In case of fatal FIR error the queue is stopped, such that
+         * we can safely check it without risking anything.
+         */
+        cd->irqs_processed++;
+        wake_up_interruptible(&cd->queue_waitq);
+
+        /*
+         * Checking for errors before kicking the queue might be
+         * safer, but slower for the good-case ... See above.
+         */
+        gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
+        if ((gfir & GFIR_ERR_TRIGGER) != 0x0) {
+
+                wake_up_interruptible(&cd->health_waitq);
+
+                /*
+                 * By default GFIRs causes recovery actions. This
+                 * count is just for debug when recovery is masked.
+                 */
+                printk_ratelimited(KERN_ERR
+                                   "%s %s: [%s] GFIR=%016llx\n",
+                                   GENWQE_DEVNAME, dev_name(&pci_dev->dev),
+                                   __func__, gfir);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t genwqe_vf_isr(int irq, void *dev_id)
+{
+        struct genwqe_dev *cd = (struct genwqe_dev *)dev_id;
+
+        cd->irqs_processed++;
+        wake_up_interruptible(&cd->queue_waitq);
+
+        return IRQ_HANDLED;
+}
+
+/**
+ * genwqe_card_thread() - Work thread for the DDCB queue
+ *
+ * The idea is to check if there are DDCBs in processing. If there are
+ * some finished DDCBs, we process them and wakeup the
+ * requestors. Otherwise we give other processes time using
+ * cond_resched().
+ */
+static int genwqe_card_thread(void *data)
+{
+        int should_stop = 0, rc = 0;
+        struct genwqe_dev *cd = (struct genwqe_dev *)data;
+
+        while (!kthread_should_stop()) {
+
+                genwqe_check_ddcb_queue(cd, &cd->queue);
+
+                if (genwqe_polling_enabled) {
+                        rc = wait_event_interruptible_timeout(
+                                cd->queue_waitq,
+                                genwqe_ddcbs_in_flight(cd) ||
+                                (should_stop = kthread_should_stop()), 1);
+                } else {
+                        rc = wait_event_interruptible_timeout(
+                                cd->queue_waitq,
+                                genwqe_next_ddcb_ready(cd) ||
+                                (should_stop = kthread_should_stop()), HZ);
+                }
+                if (should_stop)
+                        break;
+
+                /*
+                 * Avoid soft lockups on heavy loads; we do not want
+                 * to disable our interrupts.
+                 */
+                cond_resched();
+        }
+        return 0;
+}
+
+/**
+ * genwqe_setup_service_layer() - Setup DDCB queue
+ * @cd:         pointer to genwqe device descriptor
+ *
+ * Allocate DDCBs. Configure Service Layer Controller (SLC).
+ *
+ * Return: 0 success
+ */
+int genwqe_setup_service_layer(struct genwqe_dev *cd)
+{
+        int rc;
+        struct ddcb_queue *queue;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if (genwqe_is_privileged(cd)) {
+                rc = genwqe_card_reset(cd);
+                if (rc < 0) {
+                        dev_err(&pci_dev->dev,
+                                "[%s] err: reset failed.\n", __func__);
+                        return rc;
+                }
+                genwqe_read_softreset(cd);
+        }
+
+        queue = &cd->queue;
+        queue->IO_QUEUE_CONFIG  = IO_SLC_QUEUE_CONFIG;
+        queue->IO_QUEUE_STATUS  = IO_SLC_QUEUE_STATUS;
+        queue->IO_QUEUE_SEGMENT = IO_SLC_QUEUE_SEGMENT;
+        queue->IO_QUEUE_INITSQN = IO_SLC_QUEUE_INITSQN;
+        queue->IO_QUEUE_OFFSET  = IO_SLC_QUEUE_OFFSET;
+        queue->IO_QUEUE_WRAP    = IO_SLC_QUEUE_WRAP;
+        queue->IO_QUEUE_WTIME   = IO_SLC_QUEUE_WTIME;
+        queue->IO_QUEUE_ERRCNTS = IO_SLC_QUEUE_ERRCNTS;
+        queue->IO_QUEUE_LRW     = IO_SLC_QUEUE_LRW;
+
+        rc = setup_ddcb_queue(cd, queue);
+        if (rc != 0) {
+                rc = -ENODEV;
+                goto err_out;
+        }
+
+        init_waitqueue_head(&cd->queue_waitq);
+        cd->card_thread = kthread_run(genwqe_card_thread, cd,
+                                      GENWQE_DEVNAME "%d_thread",
+                                      cd->card_idx);
+        if (IS_ERR(cd->card_thread)) {
+                rc = PTR_ERR(cd->card_thread);
+                cd->card_thread = NULL;
+                goto stop_free_queue;
+        }
+
+        rc = genwqe_set_interrupt_capability(cd, GENWQE_MSI_IRQS);
+        if (rc > 0)
+                rc = genwqe_set_interrupt_capability(cd, rc);
+        if (rc != 0) {
+                rc = -ENODEV;
+                goto stop_kthread;
+        }
+
+        /*
+         * We must have all wait-queues initialized when we enable the
+         * interrupts. Otherwise we might crash if we get an early
+         * irq.
+         */
+        init_waitqueue_head(&cd->health_waitq);
+
+        if (genwqe_is_privileged(cd)) {
+                rc = request_irq(pci_dev->irq, genwqe_pf_isr, IRQF_SHARED,
+                                 GENWQE_DEVNAME, cd);
+        } else {
+                rc = request_irq(pci_dev->irq, genwqe_vf_isr, IRQF_SHARED,
+                                 GENWQE_DEVNAME, cd);
+        }
+        if (rc < 0) {
+                dev_err(&pci_dev->dev, "irq %d not free.\n", pci_dev->irq);
+                goto stop_irq_cap;
+        }
+
+        cd->card_state = GENWQE_CARD_USED;
+        return 0;
+
+ stop_irq_cap:
+        genwqe_reset_interrupt_capability(cd);
+ stop_kthread:
+        kthread_stop(cd->card_thread);
+        cd->card_thread = NULL;
+ stop_free_queue:
+        free_ddcb_queue(cd, queue);
+ err_out:
+        return rc;
+}
+
+/**
+ * queue_wake_up_all() - Handles fatal error case
+ *
+ * The PCI device got unusable and we have to stop all pending
+ * requests as fast as we can. The code after this must purge the
+ * DDCBs in question and ensure that all mappings are freed.
+ */
+static int queue_wake_up_all(struct genwqe_dev *cd)
+{
+        unsigned int i;
+        unsigned long flags;
+        struct ddcb_queue *queue = &cd->queue;
+
+        spin_lock_irqsave(&queue->ddcb_lock, flags);
+
+        for (i = 0; i < queue->ddcb_max; i++)
+                wake_up_interruptible(&queue->ddcb_waitqs[queue->ddcb_act]);
+
+        spin_unlock_irqrestore(&queue->ddcb_lock, flags);
+
+        return 0;
+}
+
+/**
+ * genwqe_finish_queue() - Remove any genwqe devices and user-interfaces
+ *
+ * Relies on the pre-condition that there are no users of the card
+ * device anymore e.g. with open file-descriptors.
+ *
+ * This function must be robust enough to be called twice.
+ */
+int genwqe_finish_queue(struct genwqe_dev *cd)
+{
+        int i, rc, in_flight;
+        int waitmax = genwqe_ddcb_software_timeout;
+        struct pci_dev *pci_dev = cd->pci_dev;
+        struct ddcb_queue *queue = &cd->queue;
+
+        if (!ddcb_queue_initialized(queue))
+                return 0;
+
+        /* Do not wipe out the error state. */
+        if (cd->card_state == GENWQE_CARD_USED)
+                cd->card_state = GENWQE_CARD_UNUSED;
+
+        /* Wake up all requests in the DDCB queue such that they
+           should be removed nicely. */
+        queue_wake_up_all(cd);
+
+        /* We must wait to get rid of the DDCBs in flight */
+        for (i = 0; i < waitmax; i++) {
+                in_flight = genwqe_ddcbs_in_flight(cd);
+
+                if (in_flight == 0)
+                        break;
+
+                dev_dbg(&pci_dev->dev,
+                        "  DEBUG [%d/%d] waiting for queue to get empty: "
+                        "%d requests!\n", i, waitmax, in_flight);
+
+                /*
+                 * Severe severe error situation: The card itself has
+                 * 16 DDCB queues, each queue has e.g. 32 entries,
+                 * each DDBC has a hardware timeout of currently 250
+                 * msec but the PFs have a hardware timeout of 8 sec
+                 * ... so I take something large.
+                 */
+                msleep(1000);
+        }
+        if (i == waitmax) {
+                dev_err(&pci_dev->dev, "  [%s] err: queue is not empty!!\n",
+                        __func__);
+                rc = -EIO;
+        }
+        return rc;
+}
+
+/**
+ * genwqe_release_service_layer() - Shutdown DDCB queue
+ * @cd:       genwqe device descriptor
+ *
+ * This function must be robust enough to be called twice.
+ */
+int genwqe_release_service_layer(struct genwqe_dev *cd)
+{
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if (!ddcb_queue_initialized(&cd->queue))
+                return 1;
+
+        free_irq(pci_dev->irq, cd);
+        genwqe_reset_interrupt_capability(cd);
+
+        if (cd->card_thread != NULL) {
+                kthread_stop(cd->card_thread);
+                cd->card_thread = NULL;
+        }
+
+        free_ddcb_queue(cd, &cd->queue);
+        return 0;
+}
diff --git a/drivers/misc/genwqe/card_ddcb.h b/drivers/misc/genwqe/card_ddcb.h
new file mode 100644
index 000000000000..c4f26720753e
--- /dev/null
+++ b/drivers/misc/genwqe/card_ddcb.h
@@ -0,0 +1,188 @@
+#ifndef __CARD_DDCB_H__
+#define __CARD_DDCB_H__
+
+/**
+ * IBM Accelerator Family 'GenWQE'
+ *
+ * (C) Copyright IBM Corp. 2013
+ *
+ * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
+ * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
+ * Author: Michael Jung <mijung@de.ibm.com>
+ * Author: Michael Ruettger <michael@ibmra.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+#include "genwqe_driver.h"
+#include "card_base.h"
+
+/**
+ * struct ddcb - Device Driver Control Block DDCB
+ * @hsi:        Hardware software interlock
+ * @shi:        Software hardware interlock. Hsi and shi are used to interlock
+ *              software and hardware activities. We are using a compare and
+ *              swap operation to ensure that there are no races when
+ *              activating new DDCBs on the queue, or when we need to
+ *              purge a DDCB from a running queue.
+ * @acfunc:     Accelerator function addresses a unit within the chip
+ * @cmd:        Command to work on
+ * @cmdopts_16: Options for the command
+ * @asiv:       Input data
+ * @asv:        Output data
+ *
+ * The DDCB data format is big endian. Multiple consequtive DDBCs form
+ * a DDCB queue.
+ */
+#define ASIV_LENGTH             104 /* Old specification without ATS field */
+#define ASIV_LENGTH_ATS         96  /* New specification with ATS field */
+#define ASV_LENGTH              64
+
+struct ddcb {
+        union {
+                __be32 icrc_hsi_shi_32; /* iCRC, Hardware/SW interlock */
+                struct {
+                        __be16  icrc_16;
+                        u8      hsi;
+                        u8      shi;
+                };
+        };
+        u8  pre;                /* Preamble */
+        u8  xdir;               /* Execution Directives */
+        __be16 seqnum_16;       /* Sequence Number */
+
+        u8  acfunc;             /* Accelerator Function.. */
+        u8  cmd;                /* Command. */
+        __be16 cmdopts_16;      /* Command Options */
+        u8  sur;                /* Status Update Rate */
+        u8  psp;                /* Protection Section Pointer */
+        __be16 rsvd_0e_16;      /* Reserved invariant */
+
+        __be64 fwiv_64;         /* Firmware Invariant. */
+
+        union {
+                struct {
+                        __be64 ats_64;  /* Address Translation Spec */
+                        u8     asiv[ASIV_LENGTH_ATS]; /* New ASIV */
+                } n;
+                u8  __asiv[ASIV_LENGTH];        /* obsolete */
+        };
+        u8     asv[ASV_LENGTH]; /* Appl Spec Variant */
+
+        __be16 rsvd_c0_16;      /* Reserved Variant */
+        __be16 vcrc_16;         /* Variant CRC */
+        __be32 rsvd_32;         /* Reserved unprotected */
+
+        __be64 deque_ts_64;     /* Deque Time Stamp. */
+
+        __be16 retc_16;         /* Return Code */
+        __be16 attn_16;         /* Attention/Extended Error Codes */
+        __be32 progress_32;     /* Progress indicator. */
+
+        __be64 cmplt_ts_64;     /* Completion Time Stamp. */
+
+        /* The following layout matches the new service layer format */
+        __be32 ibdc_32;         /* Inbound Data Count  (* 256) */
+        __be32 obdc_32;         /* Outbound Data Count (* 256) */
+
+        __be64 rsvd_SLH_64;     /* Reserved for hardware */
+        union {                 /* private data for driver */
+                u8      priv[8];
+                __be64  priv_64;
+        };
+        __be64 disp_ts_64;      /* Dispatch TimeStamp */
+} __attribute__((__packed__));
+
+/* CRC polynomials for DDCB */
+#define CRC16_POLYNOMIAL        0x1021
+
+/*
+ * SHI: Software to Hardware Interlock
+ *   This 1 byte field is written by software to interlock the
+ *   movement of one queue entry to another with the hardware in the
+ *   chip.
+ */
+#define DDCB_SHI_INTR           0x04 /* Bit 2 */
+#define DDCB_SHI_PURGE          0x02 /* Bit 1 */
+#define DDCB_SHI_NEXT           0x01 /* Bit 0 */
+
+/*
+ * HSI: Hardware to Software interlock
+ * This 1 byte field is written by hardware to interlock the movement
+ * of one queue entry to another with the software in the chip.
+ */
+#define DDCB_HSI_COMPLETED      0x40 /* Bit 6 */
+#define DDCB_HSI_FETCHED        0x04 /* Bit 2 */
+
+/*
+ * Accessing HSI/SHI is done 32-bit wide
+ *   Normally 16-bit access would work too, but on some platforms the
+ *   16 compare and swap operation is not supported. Therefore
+ *   switching to 32-bit such that those platforms will work too.
+ *
+ *                                         iCRC HSI/SHI
+ */
+#define DDCB_INTR_BE32          cpu_to_be32(0x00000004)
+#define DDCB_PURGE_BE32         cpu_to_be32(0x00000002)
+#define DDCB_NEXT_BE32          cpu_to_be32(0x00000001)
+#define DDCB_COMPLETED_BE32     cpu_to_be32(0x00004000)
+#define DDCB_FETCHED_BE32       cpu_to_be32(0x00000400)
+
+/* Definitions of DDCB presets */
+#define DDCB_PRESET_PRE         0x80
+#define ICRC_LENGTH(n)          ((n) + 8 + 8 + 8)  /* used ASIV + hdr fields */
+#define VCRC_LENGTH(n)          ((n))              /* used ASV */
+
+/*
+ * Genwqe Scatter Gather list
+ *   Each element has up to 8 entries.
+ *   The chaining element is element 0 cause of prefetching needs.
+ */
+
+/*
+ * 0b0110 Chained descriptor. The descriptor is describing the next
+ * descriptor list.
+ */
+#define SG_CHAINED              (0x6)
+
+/*
+ * 0b0010 First entry of a descriptor list. Start from a Buffer-Empty
+ * condition.
+ */
+#define SG_DATA                 (0x2)
+
+/*
+ * 0b0000 Early terminator. This is the last entry on the list
+ * irregardless of the length indicated.
+ */
+#define SG_END_LIST             (0x0)
+
+/**
+ * struct sglist - Scatter gather list
+ * @target_addr:       Either a dma addr of memory to work on or a
+ *                     dma addr or a subsequent sglist block.
+ * @len:               Length of the data block.
+ * @flags:             See above.
+ *
+ * Depending on the command the GenWQE card can use a scatter gather
+ * list to describe the memory it works on. Always 8 sg_entry's form
+ * a block.
+ */
+struct sg_entry {
+        __be64 target_addr;
+        __be32 len;
+        __be32 flags;
+};
+
+#endif /* __CARD_DDCB_H__ */
diff --git a/drivers/misc/genwqe/card_debugfs.c b/drivers/misc/genwqe/card_debugfs.c
new file mode 100644
index 000000000000..3bfdc07a7248
--- /dev/null
+++ b/drivers/misc/genwqe/card_debugfs.c
@@ -0,0 +1,500 @@
+/**
+ * IBM Accelerator Family 'GenWQE'
+ *
+ * (C) Copyright IBM Corp. 2013
+ *
+ * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
+ * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
+ * Author: Michael Jung <mijung@de.ibm.com>
+ * Author: Michael Ruettger <michael@ibmra.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Debugfs interfaces for the GenWQE card. Help to debug potential
+ * problems. Dump internal chip state for debugging and failure
+ * determination.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+
+#include "card_base.h"
+#include "card_ddcb.h"
+
+#define GENWQE_DEBUGFS_RO(_name, _showfn)                               \
+        static int genwqe_debugfs_##_name##_open(struct inode *inode,   \
+                                                 struct file *file)     \
+        {                                                               \
+                return single_open(file, _showfn, inode->i_private);    \
+        }                                                               \
+        static const struct file_operations genwqe_##_name##_fops = {   \
+                .open = genwqe_debugfs_##_name##_open,                  \
+                .read = seq_read,                                       \
+                .llseek = seq_lseek,                                    \
+                .release = single_release,                              \
+        }
+
+static void dbg_uidn_show(struct seq_file *s, struct genwqe_reg *regs,
+                          int entries)
+{
+        unsigned int i;
+        u32 v_hi, v_lo;
+
+        for (i = 0; i < entries; i++) {
+                v_hi = (regs[i].val >> 32) & 0xffffffff;
+                v_lo = (regs[i].val)       & 0xffffffff;
+
+                seq_printf(s, "  0x%08x 0x%08x 0x%08x 0x%08x EXT_ERR_REC\n",
+                           regs[i].addr, regs[i].idx, v_hi, v_lo);
+        }
+}
+
+static int curr_dbg_uidn_show(struct seq_file *s, void *unused, int uid)
+{
+        struct genwqe_dev *cd = s->private;
+        int entries;
+        struct genwqe_reg *regs;
+
+        entries = genwqe_ffdc_buff_size(cd, uid);
+        if (entries < 0)
+                return -EINVAL;
+
+        if (entries == 0)
+                return 0;
+
+        regs = kcalloc(entries, sizeof(*regs), GFP_KERNEL);
+        if (regs == NULL)
+                return -ENOMEM;
+
+        genwqe_stop_traps(cd); /* halt the traps while dumping data */
+        genwqe_ffdc_buff_read(cd, uid, regs, entries);
+        genwqe_start_traps(cd);
+
+        dbg_uidn_show(s, regs, entries);
+        kfree(regs);
+        return 0;
+}
+
+static int genwqe_curr_dbg_uid0_show(struct seq_file *s, void *unused)
+{
+        return curr_dbg_uidn_show(s, unused, 0);
+}
+
+GENWQE_DEBUGFS_RO(curr_dbg_uid0, genwqe_curr_dbg_uid0_show);
+
+static int genwqe_curr_dbg_uid1_show(struct seq_file *s, void *unused)
+{
+        return curr_dbg_uidn_show(s, unused, 1);
+}
+
+GENWQE_DEBUGFS_RO(curr_dbg_uid1, genwqe_curr_dbg_uid1_show);
+
+static int genwqe_curr_dbg_uid2_show(struct seq_file *s, void *unused)
+{
+        return curr_dbg_uidn_show(s, unused, 2);
+}
+
+GENWQE_DEBUGFS_RO(curr_dbg_uid2, genwqe_curr_dbg_uid2_show);
+
+static int prev_dbg_uidn_show(struct seq_file *s, void *unused, int uid)
+{
+        struct genwqe_dev *cd = s->private;
+
+        dbg_uidn_show(s, cd->ffdc[uid].regs,  cd->ffdc[uid].entries);
+        return 0;
+}
+
+static int genwqe_prev_dbg_uid0_show(struct seq_file *s, void *unused)
+{
+        return prev_dbg_uidn_show(s, unused, 0);
+}
+
+GENWQE_DEBUGFS_RO(prev_dbg_uid0, genwqe_prev_dbg_uid0_show);
+
+static int genwqe_prev_dbg_uid1_show(struct seq_file *s, void *unused)
+{
+        return prev_dbg_uidn_show(s, unused, 1);
+}
+
+GENWQE_DEBUGFS_RO(prev_dbg_uid1, genwqe_prev_dbg_uid1_show);
+
+static int genwqe_prev_dbg_uid2_show(struct seq_file *s, void *unused)
+{
+        return prev_dbg_uidn_show(s, unused, 2);
+}
+
+GENWQE_DEBUGFS_RO(prev_dbg_uid2, genwqe_prev_dbg_uid2_show);
+
+static int genwqe_curr_regs_show(struct seq_file *s, void *unused)
+{
+        struct genwqe_dev *cd = s->private;
+        unsigned int i;
+        struct genwqe_reg *regs;
+
+        regs = kcalloc(GENWQE_FFDC_REGS, sizeof(*regs), GFP_KERNEL);
+        if (regs == NULL)
+                return -ENOMEM;
+
+        genwqe_stop_traps(cd);
+        genwqe_read_ffdc_regs(cd, regs, GENWQE_FFDC_REGS, 1);
+        genwqe_start_traps(cd);
+
+        for (i = 0; i < GENWQE_FFDC_REGS; i++) {
+                if (regs[i].addr == 0xffffffff)
+                        break;  /* invalid entries */
+
+                if (regs[i].val == 0x0ull)
+                        continue;  /* do not print 0x0 FIRs */
+
+                seq_printf(s, "  0x%08x 0x%016llx\n",
+                           regs[i].addr, regs[i].val);
+        }
+        return 0;
+}
+
+GENWQE_DEBUGFS_RO(curr_regs, genwqe_curr_regs_show);
+
+static int genwqe_prev_regs_show(struct seq_file *s, void *unused)
+{
+        struct genwqe_dev *cd = s->private;
+        unsigned int i;
+        struct genwqe_reg *regs = cd->ffdc[GENWQE_DBG_REGS].regs;
+
+        if (regs == NULL)
+                return -EINVAL;
+
+        for (i = 0; i < GENWQE_FFDC_REGS; i++) {
+                if (regs[i].addr == 0xffffffff)
+                        break;  /* invalid entries */
+
+                if (regs[i].val == 0x0ull)
+                        continue;  /* do not print 0x0 FIRs */
+
+                seq_printf(s, "  0x%08x 0x%016llx\n",
+                           regs[i].addr, regs[i].val);
+        }
+        return 0;
+}
+
+GENWQE_DEBUGFS_RO(prev_regs, genwqe_prev_regs_show);
+
+static int genwqe_jtimer_show(struct seq_file *s, void *unused)
+{
+        struct genwqe_dev *cd = s->private;
+        unsigned int vf_num;
+        u64 jtimer;
+
+        jtimer = genwqe_read_vreg(cd, IO_SLC_VF_APPJOB_TIMEOUT, 0);
+        seq_printf(s, "  PF   0x%016llx %d msec\n", jtimer,
+                   genwqe_pf_jobtimeout_msec);
+
+        for (vf_num = 0; vf_num < cd->num_vfs; vf_num++) {
+                jtimer = genwqe_read_vreg(cd, IO_SLC_VF_APPJOB_TIMEOUT,
+                                          vf_num + 1);
+                seq_printf(s, "  VF%-2d 0x%016llx %d msec\n", vf_num, jtimer,
+                           cd->vf_jobtimeout_msec[vf_num]);
+        }
+        return 0;
+}
+
+GENWQE_DEBUGFS_RO(jtimer, genwqe_jtimer_show);
+
+static int genwqe_queue_working_time_show(struct seq_file *s, void *unused)
+{
+        struct genwqe_dev *cd = s->private;
+        unsigned int vf_num;
+        u64 t;
+
+        t = genwqe_read_vreg(cd, IO_SLC_VF_QUEUE_WTIME, 0);
+        seq_printf(s, "  PF   0x%016llx\n", t);
+
+        for (vf_num = 0; vf_num < cd->num_vfs; vf_num++) {
+                t = genwqe_read_vreg(cd, IO_SLC_VF_QUEUE_WTIME, vf_num + 1);
+                seq_printf(s, "  VF%-2d 0x%016llx\n", vf_num, t);
+        }
+        return 0;
+}
+
+GENWQE_DEBUGFS_RO(queue_working_time, genwqe_queue_working_time_show);
+
+static int genwqe_ddcb_info_show(struct seq_file *s, void *unused)
+{
+        struct genwqe_dev *cd = s->private;
+        unsigned int i;
+        struct ddcb_queue *queue;
+        struct ddcb *pddcb;
+
+        queue = &cd->queue;
+        seq_puts(s, "DDCB QUEUE:\n");
+        seq_printf(s, "  ddcb_max:            %d\n"
+                   "  ddcb_daddr:          %016llx - %016llx\n"
+                   "  ddcb_vaddr:          %016llx\n"
+                   "  ddcbs_in_flight:     %u\n"
+                   "  ddcbs_max_in_flight: %u\n"
+                   "  ddcbs_completed:     %u\n"
+                   "  busy:                %u\n"
+                   "  irqs_processed:      %u\n",
+                   queue->ddcb_max, (long long)queue->ddcb_daddr,
+                   (long long)queue->ddcb_daddr +
+                   (queue->ddcb_max * DDCB_LENGTH),
+                   (long long)queue->ddcb_vaddr, queue->ddcbs_in_flight,
+                   queue->ddcbs_max_in_flight, queue->ddcbs_completed,
+                   queue->busy, cd->irqs_processed);
+
+        /* Hardware State */
+        seq_printf(s, "  0x%08x 0x%016llx IO_QUEUE_CONFIG\n"
+                   "  0x%08x 0x%016llx IO_QUEUE_STATUS\n"
+                   "  0x%08x 0x%016llx IO_QUEUE_SEGMENT\n"
+                   "  0x%08x 0x%016llx IO_QUEUE_INITSQN\n"
+                   "  0x%08x 0x%016llx IO_QUEUE_WRAP\n"
+                   "  0x%08x 0x%016llx IO_QUEUE_OFFSET\n"
+                   "  0x%08x 0x%016llx IO_QUEUE_WTIME\n"
+                   "  0x%08x 0x%016llx IO_QUEUE_ERRCNTS\n"
+                   "  0x%08x 0x%016llx IO_QUEUE_LRW\n",
+                   queue->IO_QUEUE_CONFIG,
+                   __genwqe_readq(cd, queue->IO_QUEUE_CONFIG),
+                   queue->IO_QUEUE_STATUS,
+                   __genwqe_readq(cd, queue->IO_QUEUE_STATUS),
+                   queue->IO_QUEUE_SEGMENT,
+                   __genwqe_readq(cd, queue->IO_QUEUE_SEGMENT),
+                   queue->IO_QUEUE_INITSQN,
+                   __genwqe_readq(cd, queue->IO_QUEUE_INITSQN),
+                   queue->IO_QUEUE_WRAP,
+                   __genwqe_readq(cd, queue->IO_QUEUE_WRAP),
+                   queue->IO_QUEUE_OFFSET,
+                   __genwqe_readq(cd, queue->IO_QUEUE_OFFSET),
+                   queue->IO_QUEUE_WTIME,
+                   __genwqe_readq(cd, queue->IO_QUEUE_WTIME),
+                   queue->IO_QUEUE_ERRCNTS,
+                   __genwqe_readq(cd, queue->IO_QUEUE_ERRCNTS),
+                   queue->IO_QUEUE_LRW,
+                   __genwqe_readq(cd, queue->IO_QUEUE_LRW));
+
+        seq_printf(s, "DDCB list (ddcb_act=%d/ddcb_next=%d):\n",
+                   queue->ddcb_act, queue->ddcb_next);
+
+        pddcb = queue->ddcb_vaddr;
+        for (i = 0; i < queue->ddcb_max; i++) {
+                seq_printf(s, "  %-3d: RETC=%03x SEQ=%04x HSI/SHI=%02x/%02x ",
+                           i, be16_to_cpu(pddcb->retc_16),
+                           be16_to_cpu(pddcb->seqnum_16),
+                           pddcb->hsi, pddcb->shi);
+                seq_printf(s, "PRIV=%06llx CMD=%02x\n",
+                           be64_to_cpu(pddcb->priv_64), pddcb->cmd);
+                pddcb++;
+        }
+        return 0;
+}
+
+GENWQE_DEBUGFS_RO(ddcb_info, genwqe_ddcb_info_show);
+
+static int genwqe_info_show(struct seq_file *s, void *unused)
+{
+        struct genwqe_dev *cd = s->private;
+        u16 val16, type;
+        u64 app_id, slu_id, bitstream = -1;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        slu_id = __genwqe_readq(cd, IO_SLU_UNITCFG);
+        app_id = __genwqe_readq(cd, IO_APP_UNITCFG);
+
+        if (genwqe_is_privileged(cd))
+                bitstream = __genwqe_readq(cd, IO_SLU_BITSTREAM);
+
+        val16 = (u16)(slu_id & 0x0fLLU);
+        type  = (u16)((slu_id >> 20) & 0xffLLU);
+
+        seq_printf(s, "%s driver version: %s\n"
+                   "    Device Name/Type: %s %s CardIdx: %d\n"
+                   "    SLU/APP Config  : 0x%016llx/0x%016llx\n"
+                   "    Build Date      : %u/%x/%u\n"
+                   "    Base Clock      : %u MHz\n"
+                   "    Arch/SVN Release: %u/%llx\n"
+                   "    Bitstream       : %llx\n",
+                   GENWQE_DEVNAME, DRV_VERS_STRING, dev_name(&pci_dev->dev),
+                   genwqe_is_privileged(cd) ?
+                   "Physical" : "Virtual or no SR-IOV",
+                   cd->card_idx, slu_id, app_id,
+                   (u16)((slu_id >> 12) & 0x0fLLU),        /* month */
+                   (u16)((slu_id >>  4) & 0xffLLU),        /* day */
+                   (u16)((slu_id >> 16) & 0x0fLLU) + 2010, /* year */
+                   genwqe_base_clock_frequency(cd),
+                   (u16)((slu_id >> 32) & 0xffLLU), slu_id >> 40,
+                   bitstream);
+
+        return 0;
+}
+
+GENWQE_DEBUGFS_RO(info, genwqe_info_show);
+
+int genwqe_init_debugfs(struct genwqe_dev *cd)
+{
+        struct dentry *root;
+        struct dentry *file;
+        int ret;
+        char card_name[64];
+        char name[64];
+        unsigned int i;
+
+        sprintf(card_name, "%s%u_card", GENWQE_DEVNAME, cd->card_idx);
+
+        root = debugfs_create_dir(card_name, cd->debugfs_genwqe);
+        if (!root) {
+                ret = -ENOMEM;
+                goto err0;
+        }
+
+        /* non privileged interfaces are done here */
+        file = debugfs_create_file("ddcb_info", S_IRUGO, root, cd,
+                                   &genwqe_ddcb_info_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_file("info", S_IRUGO, root, cd,
+                                   &genwqe_info_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_x64("err_inject", 0666, root, &cd->err_inject);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_u32("ddcb_software_timeout", 0666, root,
+                                  &cd->ddcb_software_timeout);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_u32("kill_timeout", 0666, root,
+                                  &cd->kill_timeout);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        /* privileged interfaces follow here */
+        if (!genwqe_is_privileged(cd)) {
+                cd->debugfs_root = root;
+                return 0;
+        }
+
+        file = debugfs_create_file("curr_regs", S_IRUGO, root, cd,
+                                   &genwqe_curr_regs_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_file("curr_dbg_uid0", S_IRUGO, root, cd,
+                                   &genwqe_curr_dbg_uid0_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_file("curr_dbg_uid1", S_IRUGO, root, cd,
+                                   &genwqe_curr_dbg_uid1_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_file("curr_dbg_uid2", S_IRUGO, root, cd,
+                                   &genwqe_curr_dbg_uid2_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_file("prev_regs", S_IRUGO, root, cd,
+                                   &genwqe_prev_regs_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_file("prev_dbg_uid0", S_IRUGO, root, cd,
+                                   &genwqe_prev_dbg_uid0_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_file("prev_dbg_uid1", S_IRUGO, root, cd,
+                                   &genwqe_prev_dbg_uid1_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_file("prev_dbg_uid2", S_IRUGO, root, cd,
+                                   &genwqe_prev_dbg_uid2_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        for (i = 0; i <  GENWQE_MAX_VFS; i++) {
+                sprintf(name, "vf%d_jobtimeout_msec", i);
+
+                file = debugfs_create_u32(name, 0666, root,
+                                          &cd->vf_jobtimeout_msec[i]);
+                if (!file) {
+                        ret = -ENOMEM;
+                        goto err1;
+                }
+        }
+
+        file = debugfs_create_file("jobtimer", S_IRUGO, root, cd,
+                                   &genwqe_jtimer_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_file("queue_working_time", S_IRUGO, root, cd,
+                                   &genwqe_queue_working_time_fops);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        file = debugfs_create_u32("skip_recovery", 0666, root,
+                                  &cd->skip_recovery);
+        if (!file) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        cd->debugfs_root = root;
+        return 0;
+err1:
+        debugfs_remove_recursive(root);
+err0:
+        return ret;
+}
+
+void genqwe_exit_debugfs(struct genwqe_dev *cd)
+{
+        debugfs_remove_recursive(cd->debugfs_root);
+}
diff --git a/drivers/misc/genwqe/card_dev.c b/drivers/misc/genwqe/card_dev.c
new file mode 100644
index 000000000000..8f8a6b327cdb
--- /dev/null
+++ b/drivers/misc/genwqe/card_dev.c
@@ -0,0 +1,1414 @@
+/**
+ * IBM Accelerator Family 'GenWQE'
+ *
+ * (C) Copyright IBM Corp. 2013
+ *
+ * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
+ * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
+ * Author: Michael Jung <mijung@de.ibm.com>
+ * Author: Michael Ruettger <michael@ibmra.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Character device representation of the GenWQE device. This allows
+ * user-space applications to communicate with the card.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/string.h>
+#include <linux/fs.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/delay.h>
+#include <linux/atomic.h>
+
+#include "card_base.h"
+#include "card_ddcb.h"
+
+static int genwqe_open_files(struct genwqe_dev *cd)
+{
+        int rc;
+        unsigned long flags;
+
+        spin_lock_irqsave(&cd->file_lock, flags);
+        rc = list_empty(&cd->file_list);
+        spin_unlock_irqrestore(&cd->file_lock, flags);
+        return !rc;
+}
+
+static void genwqe_add_file(struct genwqe_dev *cd, struct genwqe_file *cfile)
+{
+        unsigned long flags;
+
+        cfile->owner = current;
+        spin_lock_irqsave(&cd->file_lock, flags);
+        list_add(&cfile->list, &cd->file_list);
+        spin_unlock_irqrestore(&cd->file_lock, flags);
+}
+
+static int genwqe_del_file(struct genwqe_dev *cd, struct genwqe_file *cfile)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&cd->file_lock, flags);
+        list_del(&cfile->list);
+        spin_unlock_irqrestore(&cd->file_lock, flags);
+
+        return 0;
+}
+
+static void genwqe_add_pin(struct genwqe_file *cfile, struct dma_mapping *m)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&cfile->pin_lock, flags);
+        list_add(&m->pin_list, &cfile->pin_list);
+        spin_unlock_irqrestore(&cfile->pin_lock, flags);
+}
+
+static int genwqe_del_pin(struct genwqe_file *cfile, struct dma_mapping *m)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&cfile->pin_lock, flags);
+        list_del(&m->pin_list);
+        spin_unlock_irqrestore(&cfile->pin_lock, flags);
+
+        return 0;
+}
+
+/**
+ * genwqe_search_pin() - Search for the mapping for a userspace address
+ * @cfile:      Descriptor of opened file
+ * @u_addr:     User virtual address
+ * @size:       Size of buffer
+ * @dma_addr:   DMA address to be updated
+ *
+ * Return: Pointer to the corresponding mapping NULL if not found
+ */
+static struct dma_mapping *genwqe_search_pin(struct genwqe_file *cfile,
+                                            unsigned long u_addr,
+                                            unsigned int size,
+                                            void **virt_addr)
+{
+        unsigned long flags;
+        struct dma_mapping *m;
+
+        spin_lock_irqsave(&cfile->pin_lock, flags);
+
+        list_for_each_entry(m, &cfile->pin_list, pin_list) {
+                if ((((u64)m->u_vaddr) <= (u_addr)) &&
+                    (((u64)m->u_vaddr + m->size) >= (u_addr + size))) {
+
+                        if (virt_addr)
+                                *virt_addr = m->k_vaddr +
+                                        (u_addr - (u64)m->u_vaddr);
+
+                        spin_unlock_irqrestore(&cfile->pin_lock, flags);
+                        return m;
+                }
+        }
+        spin_unlock_irqrestore(&cfile->pin_lock, flags);
+        return NULL;
+}
+
+static void __genwqe_add_mapping(struct genwqe_file *cfile,
+                              struct dma_mapping *dma_map)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&cfile->map_lock, flags);
+        list_add(&dma_map->card_list, &cfile->map_list);
+        spin_unlock_irqrestore(&cfile->map_lock, flags);
+}
+
+static void __genwqe_del_mapping(struct genwqe_file *cfile,
+                              struct dma_mapping *dma_map)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&cfile->map_lock, flags);
+        list_del(&dma_map->card_list);
+        spin_unlock_irqrestore(&cfile->map_lock, flags);
+}
+
+
+/**
+ * __genwqe_search_mapping() - Search for the mapping for a userspace address
+ * @cfile:      descriptor of opened file
+ * @u_addr:     user virtual address
+ * @size:       size of buffer
+ * @dma_addr:   DMA address to be updated
+ * Return: Pointer to the corresponding mapping NULL if not found
+ */
+static struct dma_mapping *__genwqe_search_mapping(struct genwqe_file *cfile,
+                                                   unsigned long u_addr,
+                                                   unsigned int size,
+                                                   dma_addr_t *dma_addr,
+                                                   void **virt_addr)
+{
+        unsigned long flags;
+        struct dma_mapping *m;
+        struct pci_dev *pci_dev = cfile->cd->pci_dev;
+
+        spin_lock_irqsave(&cfile->map_lock, flags);
+        list_for_each_entry(m, &cfile->map_list, card_list) {
+
+                if ((((u64)m->u_vaddr) <= (u_addr)) &&
+                    (((u64)m->u_vaddr + m->size) >= (u_addr + size))) {
+
+                        /* match found: current is as expected and
+                           addr is in range */
+                        if (dma_addr)
+                                *dma_addr = m->dma_addr +
+                                        (u_addr - (u64)m->u_vaddr);
+
+                        if (virt_addr)
+                                *virt_addr = m->k_vaddr +
+                                        (u_addr - (u64)m->u_vaddr);
+
+                        spin_unlock_irqrestore(&cfile->map_lock, flags);
+                        return m;
+                }
+        }
+        spin_unlock_irqrestore(&cfile->map_lock, flags);
+
+        dev_err(&pci_dev->dev,
+                "[%s] Entry not found: u_addr=%lx, size=%x\n",
+                __func__, u_addr, size);
+
+        return NULL;
+}
+
+static void genwqe_remove_mappings(struct genwqe_file *cfile)
+{
+        int i = 0;
+        struct list_head *node, *next;
+        struct dma_mapping *dma_map;
+        struct genwqe_dev *cd = cfile->cd;
+        struct pci_dev *pci_dev = cfile->cd->pci_dev;
+
+        list_for_each_safe(node, next, &cfile->map_list) {
+                dma_map = list_entry(node, struct dma_mapping, card_list);
+
+                list_del_init(&dma_map->card_list);
+
+                /*
+                 * This is really a bug, because those things should
+                 * have been already tidied up.
+                 *
+                 * GENWQE_MAPPING_RAW should have been removed via mmunmap().
+                 * GENWQE_MAPPING_SGL_TEMP should be removed by tidy up code.
+                 */
+                dev_err(&pci_dev->dev,
+                        "[%s] %d. cleanup mapping: u_vaddr=%p "
+                        "u_kaddr=%016lx dma_addr=%lx\n", __func__, i++,
+                        dma_map->u_vaddr, (unsigned long)dma_map->k_vaddr,
+                        (unsigned long)dma_map->dma_addr);
+
+                if (dma_map->type == GENWQE_MAPPING_RAW) {
+                        /* we allocated this dynamically */
+                        __genwqe_free_consistent(cd, dma_map->size,
+                                                dma_map->k_vaddr,
+                                                dma_map->dma_addr);
+                        kfree(dma_map);
+                } else if (dma_map->type == GENWQE_MAPPING_SGL_TEMP) {
+                        /* we use dma_map statically from the request */
+                        genwqe_user_vunmap(cd, dma_map, NULL);
+                }
+        }
+}
+
+static void genwqe_remove_pinnings(struct genwqe_file *cfile)
+{
+        struct list_head *node, *next;
+        struct dma_mapping *dma_map;
+        struct genwqe_dev *cd = cfile->cd;
+
+        list_for_each_safe(node, next, &cfile->pin_list) {
+                dma_map = list_entry(node, struct dma_mapping, pin_list);
+
+                /*
+                 * This is not a bug, because a killed processed might
+                 * not call the unpin ioctl, which is supposed to free
+                 * the resources.
+                 *
+                 * Pinnings are dymically allocated and need to be
+                 * deleted.
+                 */
+                list_del_init(&dma_map->pin_list);
+                genwqe_user_vunmap(cd, dma_map, NULL);
+                kfree(dma_map);
+        }
+}
+
+/**
+ * genwqe_kill_fasync() - Send signal to all processes with open GenWQE files
+ *
+ * E.g. genwqe_send_signal(cd, SIGIO);
+ */
+static int genwqe_kill_fasync(struct genwqe_dev *cd, int sig)
+{
+        unsigned int files = 0;
+        unsigned long flags;
+        struct genwqe_file *cfile;
+
+        spin_lock_irqsave(&cd->file_lock, flags);
+        list_for_each_entry(cfile, &cd->file_list, list) {
+                if (cfile->async_queue)
+                        kill_fasync(&cfile->async_queue, sig, POLL_HUP);
+                files++;
+        }
+        spin_unlock_irqrestore(&cd->file_lock, flags);
+        return files;
+}
+
+static int genwqe_force_sig(struct genwqe_dev *cd, int sig)
+{
+        unsigned int files = 0;
+        unsigned long flags;
+        struct genwqe_file *cfile;
+
+        spin_lock_irqsave(&cd->file_lock, flags);
+        list_for_each_entry(cfile, &cd->file_list, list) {
+                force_sig(sig, cfile->owner);
+                files++;
+        }
+        spin_unlock_irqrestore(&cd->file_lock, flags);
+        return files;
+}
+
+/**
+ * genwqe_open() - file open
+ * @inode:      file system information
+ * @filp:       file handle
+ *
+ * This function is executed whenever an application calls
+ * open("/dev/genwqe",..).
+ *
+ * Return: 0 if successful or <0 if errors
+ */
+static int genwqe_open(struct inode *inode, struct file *filp)
+{
+        struct genwqe_dev *cd;
+        struct genwqe_file *cfile;
+        struct pci_dev *pci_dev;
+
+        cfile = kzalloc(sizeof(*cfile), GFP_KERNEL);
+        if (cfile == NULL)
+                return -ENOMEM;
+
+        cd = container_of(inode->i_cdev, struct genwqe_dev, cdev_genwqe);
+        pci_dev = cd->pci_dev;
+        cfile->cd = cd;
+        cfile->filp = filp;
+        cfile->client = NULL;
+
+        spin_lock_init(&cfile->map_lock);  /* list of raw memory allocations */
+        INIT_LIST_HEAD(&cfile->map_list);
+
+        spin_lock_init(&cfile->pin_lock);  /* list of user pinned memory */
+        INIT_LIST_HEAD(&cfile->pin_list);
+
+        filp->private_data = cfile;
+
+        genwqe_add_file(cd, cfile);
+        return 0;
+}
+
+/**
+ * genwqe_fasync() - Setup process to receive SIGIO.
+ * @fd:        file descriptor
+ * @filp:      file handle
+ * @mode:      file mode
+ *
+ * Sending a signal is working as following:
+ *
+ * if (cdev->async_queue)
+ *         kill_fasync(&cdev->async_queue, SIGIO, POLL_IN);
+ *
+ * Some devices also implement asynchronous notification to indicate
+ * when the device can be written; in this case, of course,
+ * kill_fasync must be called with a mode of POLL_OUT.
+ */
+static int genwqe_fasync(int fd, struct file *filp, int mode)
+{
+        struct genwqe_file *cdev = (struct genwqe_file *)filp->private_data;
+        return fasync_helper(fd, filp, mode, &cdev->async_queue);
+}
+
+
+/**
+ * genwqe_release() - file close
+ * @inode:      file system information
+ * @filp:       file handle
+ *
+ * This function is executed whenever an application calls 'close(fd_genwqe)'
+ *
+ * Return: always 0
+ */
+static int genwqe_release(struct inode *inode, struct file *filp)
+{
+        struct genwqe_file *cfile = (struct genwqe_file *)filp->private_data;
+        struct genwqe_dev *cd = cfile->cd;
+
+        /* there must be no entries in these lists! */
+        genwqe_remove_mappings(cfile);
+        genwqe_remove_pinnings(cfile);
+
+        /* remove this filp from the asynchronously notified filp's */
+        genwqe_fasync(-1, filp, 0);
+
+        /*
+         * For this to work we must not release cd when this cfile is
+         * not yet released, otherwise the list entry is invalid,
+         * because the list itself gets reinstantiated!
+         */
+        genwqe_del_file(cd, cfile);
+        kfree(cfile);
+        return 0;
+}
+
+static void genwqe_vma_open(struct vm_area_struct *vma)
+{
+        /* nothing ... */
+}
+
+/**
+ * genwqe_vma_close() - Called each time when vma is unmapped
+ *
+ * Free memory which got allocated by GenWQE mmap().
+ */
+static void genwqe_vma_close(struct vm_area_struct *vma)
+{
+        unsigned long vsize = vma->vm_end - vma->vm_start;
+        struct inode *inode = vma->vm_file->f_dentry->d_inode;
+        struct dma_mapping *dma_map;
+        struct genwqe_dev *cd = container_of(inode->i_cdev, struct genwqe_dev,
+                                            cdev_genwqe);
+        struct pci_dev *pci_dev = cd->pci_dev;
+        dma_addr_t d_addr = 0;
+        struct genwqe_file *cfile = vma->vm_private_data;
+
+        dma_map = __genwqe_search_mapping(cfile, vma->vm_start, vsize,
+                                         &d_addr, NULL);
+        if (dma_map == NULL) {
+                dev_err(&pci_dev->dev,
+                        "  [%s] err: mapping not found: v=%lx, p=%lx s=%lx\n",
+                        __func__, vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
+                        vsize);
+                return;
+        }
+        __genwqe_del_mapping(cfile, dma_map);
+        __genwqe_free_consistent(cd, dma_map->size, dma_map->k_vaddr,
+                                 dma_map->dma_addr);
+        kfree(dma_map);
+}
+
+static struct vm_operations_struct genwqe_vma_ops = {
+        .open   = genwqe_vma_open,
+        .close  = genwqe_vma_close,
+};
+
+/**
+ * genwqe_mmap() - Provide contignous buffers to userspace
+ *
+ * We use mmap() to allocate contignous buffers used for DMA
+ * transfers. After the buffer is allocated we remap it to user-space
+ * and remember a reference to our dma_mapping data structure, where
+ * we store the associated DMA address and allocated size.
+ *
+ * When we receive a DDCB execution request with the ATS bits set to
+ * plain buffer, we lookup our dma_mapping list to find the
+ * corresponding DMA address for the associated user-space address.
+ */
+static int genwqe_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+        int rc;
+        unsigned long pfn, vsize = vma->vm_end - vma->vm_start;
+        struct genwqe_file *cfile = (struct genwqe_file *)filp->private_data;
+        struct genwqe_dev *cd = cfile->cd;
+        struct dma_mapping *dma_map;
+
+        if (vsize == 0)
+                return -EINVAL;
+
+        if (get_order(vsize) > MAX_ORDER)
+                return -ENOMEM;
+
+        dma_map = kzalloc(sizeof(struct dma_mapping), GFP_ATOMIC);
+        if (dma_map == NULL)
+                return -ENOMEM;
+
+        genwqe_mapping_init(dma_map, GENWQE_MAPPING_RAW);
+        dma_map->u_vaddr = (void *)vma->vm_start;
+        dma_map->size = vsize;
+        dma_map->nr_pages = DIV_ROUND_UP(vsize, PAGE_SIZE);
+        dma_map->k_vaddr = __genwqe_alloc_consistent(cd, vsize,
+                                                     &dma_map->dma_addr);
+        if (dma_map->k_vaddr == NULL) {
+                rc = -ENOMEM;
+                goto free_dma_map;
+        }
+
+        if (capable(CAP_SYS_ADMIN) && (vsize > sizeof(dma_addr_t)))
+                *(dma_addr_t *)dma_map->k_vaddr = dma_map->dma_addr;
+
+        pfn = virt_to_phys(dma_map->k_vaddr) >> PAGE_SHIFT;
+        rc = remap_pfn_range(vma,
+                             vma->vm_start,
+                             pfn,
+                             vsize,
+                             vma->vm_page_prot);
+        if (rc != 0) {
+                rc = -EFAULT;
+                goto free_dma_mem;
+        }
+
+        vma->vm_private_data = cfile;
+        vma->vm_ops = &genwqe_vma_ops;
+        __genwqe_add_mapping(cfile, dma_map);
+
+        return 0;
+
+ free_dma_mem:
+        __genwqe_free_consistent(cd, dma_map->size,
+                                dma_map->k_vaddr,
+                                dma_map->dma_addr);
+ free_dma_map:
+        kfree(dma_map);
+        return rc;
+}
+
+/**
+ * do_flash_update() - Excute flash update (write image or CVPD)
+ * @cd:        genwqe device
+ * @load:      details about image load
+ *
+ * Return: 0 if successful
+ */
+
+#define FLASH_BLOCK     0x40000 /* we use 256k blocks */
+
+static int do_flash_update(struct genwqe_file *cfile,
+                           struct genwqe_bitstream *load)
+{
+        int rc = 0;
+        int blocks_to_flash;
+        dma_addr_t dma_addr;
+        u64 flash = 0;
+        size_t tocopy = 0;
+        u8 __user *buf;
+        u8 *xbuf;
+        u32 crc;
+        u8 cmdopts;
+        struct genwqe_dev *cd = cfile->cd;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if ((load->size & 0x3) != 0)
+                return -EINVAL;
+
+        if (((unsigned long)(load->data_addr) & ~PAGE_MASK) != 0)
+                return -EINVAL;
+
+        /* FIXME Bits have changed for new service layer! */
+        switch ((char)load->partition) {
+        case '0':
+                cmdopts = 0x14;
+                break;          /* download/erase_first/part_0 */
+        case '1':
+                cmdopts = 0x1C;
+                break;          /* download/erase_first/part_1 */
+        case 'v':               /* cmdopts = 0x0c (VPD) */
+        default:
+                return -EINVAL;
+        }
+
+        buf = (u8 __user *)load->data_addr;
+        xbuf = __genwqe_alloc_consistent(cd, FLASH_BLOCK, &dma_addr);
+        if (xbuf == NULL)
+                return -ENOMEM;
+
+        blocks_to_flash = load->size / FLASH_BLOCK;
+        while (load->size) {
+                struct genwqe_ddcb_cmd *req;
+
+                /*
+                 * We must be 4 byte aligned. Buffer must be 0 appened
+                 * to have defined values when calculating CRC.
+                 */
+                tocopy = min_t(size_t, load->size, FLASH_BLOCK);
+
+                rc = copy_from_user(xbuf, buf, tocopy);
+                if (rc) {
+                        rc = -EFAULT;
+                        goto free_buffer;
+                }
+                crc = genwqe_crc32(xbuf, tocopy, 0xffffffff);
+
+                dev_dbg(&pci_dev->dev,
+                        "[%s] DMA: %lx CRC: %08x SZ: %ld %d\n",
+                        __func__, (unsigned long)dma_addr, crc, tocopy,
+                        blocks_to_flash);
+
+                /* prepare DDCB for SLU process */
+                req = ddcb_requ_alloc();
+                if (req == NULL) {
+                        rc = -ENOMEM;
+                        goto free_buffer;
+                }
+
+                req->cmd = SLCMD_MOVE_FLASH;
+                req->cmdopts = cmdopts;
+
+                /* prepare invariant values */
+                if (genwqe_get_slu_id(cd) <= 0x2) {
+                        *(__be64 *)&req->__asiv[0]  = cpu_to_be64(dma_addr);
+                        *(__be64 *)&req->__asiv[8]  = cpu_to_be64(tocopy);
+                        *(__be64 *)&req->__asiv[16] = cpu_to_be64(flash);
+                        *(__be32 *)&req->__asiv[24] = cpu_to_be32(0);
+                        req->__asiv[24]        = load->uid;
+                        *(__be32 *)&req->__asiv[28] = cpu_to_be32(crc);
+
+                        /* for simulation only */
+                        *(__be64 *)&req->__asiv[88] = cpu_to_be64(load->slu_id);
+                        *(__be64 *)&req->__asiv[96] = cpu_to_be64(load->app_id);
+                        req->asiv_length = 32; /* bytes included in crc calc */
+                } else {        /* setup DDCB for ATS architecture */
+                        *(__be64 *)&req->asiv[0]  = cpu_to_be64(dma_addr);
+                        *(__be32 *)&req->asiv[8]  = cpu_to_be32(tocopy);
+                        *(__be32 *)&req->asiv[12] = cpu_to_be32(0); /* resvd */
+                        *(__be64 *)&req->asiv[16] = cpu_to_be64(flash);
+                        *(__be32 *)&req->asiv[24] = cpu_to_be32(load->uid<<24);
+                        *(__be32 *)&req->asiv[28] = cpu_to_be32(crc);
+
+                        /* for simulation only */
+                        *(__be64 *)&req->asiv[80] = cpu_to_be64(load->slu_id);
+                        *(__be64 *)&req->asiv[88] = cpu_to_be64(load->app_id);
+
+                        /* Rd only */
+                        req->ats = 0x4ULL << 44;
+                        req->asiv_length = 40; /* bytes included in crc calc */
+                }
+                req->asv_length  = 8;
+
+                /* For Genwqe5 we get back the calculated CRC */
+                *(u64 *)&req->asv[0] = 0ULL;                    /* 0x80 */
+
+                rc = __genwqe_execute_raw_ddcb(cd, req);
+
+                load->retc = req->retc;
+                load->attn = req->attn;
+                load->progress = req->progress;
+
+                if (rc < 0) {
+                        ddcb_requ_free(req);
+                        goto free_buffer;
+                }
+
+                if (req->retc != DDCB_RETC_COMPLETE) {
+                        rc = -EIO;
+                        ddcb_requ_free(req);
+                        goto free_buffer;
+                }
+
+                load->size  -= tocopy;
+                flash += tocopy;
+                buf += tocopy;
+                blocks_to_flash--;
+                ddcb_requ_free(req);
+        }
+
+ free_buffer:
+        __genwqe_free_consistent(cd, FLASH_BLOCK, xbuf, dma_addr);
+        return rc;
+}
+
+static int do_flash_read(struct genwqe_file *cfile,
+                         struct genwqe_bitstream *load)
+{
+        int rc, blocks_to_flash;
+        dma_addr_t dma_addr;
+        u64 flash = 0;
+        size_t tocopy = 0;
+        u8 __user *buf;
+        u8 *xbuf;
+        u8 cmdopts;
+        struct genwqe_dev *cd = cfile->cd;
+        struct pci_dev *pci_dev = cd->pci_dev;
+        struct genwqe_ddcb_cmd *cmd;
+
+        if ((load->size & 0x3) != 0)
+                return -EINVAL;
+
+        if (((unsigned long)(load->data_addr) & ~PAGE_MASK) != 0)
+                return -EINVAL;
+
+        /* FIXME Bits have changed for new service layer! */
+        switch ((char)load->partition) {
+        case '0':
+                cmdopts = 0x12;
+                break;          /* upload/part_0 */
+        case '1':
+                cmdopts = 0x1A;
+                break;          /* upload/part_1 */
+        case 'v':
+        default:
+                return -EINVAL;
+        }
+
+        buf = (u8 __user *)load->data_addr;
+        xbuf = __genwqe_alloc_consistent(cd, FLASH_BLOCK, &dma_addr);
+        if (xbuf == NULL)
+                return -ENOMEM;
+
+        blocks_to_flash = load->size / FLASH_BLOCK;
+        while (load->size) {
+                /*
+                 * We must be 4 byte aligned. Buffer must be 0 appened
+                 * to have defined values when calculating CRC.
+                 */
+                tocopy = min_t(size_t, load->size, FLASH_BLOCK);
+
+                dev_dbg(&pci_dev->dev,
+                        "[%s] DMA: %lx SZ: %ld %d\n",
+                        __func__, (unsigned long)dma_addr, tocopy,
+                        blocks_to_flash);
+
+                /* prepare DDCB for SLU process */
+                cmd = ddcb_requ_alloc();
+                if (cmd == NULL) {
+                        rc = -ENOMEM;
+                        goto free_buffer;
+                }
+                cmd->cmd = SLCMD_MOVE_FLASH;
+                cmd->cmdopts = cmdopts;
+
+                /* prepare invariant values */
+                if (genwqe_get_slu_id(cd) <= 0x2) {
+                        *(__be64 *)&cmd->__asiv[0]  = cpu_to_be64(dma_addr);
+                        *(__be64 *)&cmd->__asiv[8]  = cpu_to_be64(tocopy);
+                        *(__be64 *)&cmd->__asiv[16] = cpu_to_be64(flash);
+                        *(__be32 *)&cmd->__asiv[24] = cpu_to_be32(0);
+                        cmd->__asiv[24] = load->uid;
+                        *(__be32 *)&cmd->__asiv[28] = cpu_to_be32(0) /* CRC */;
+                        cmd->asiv_length = 32; /* bytes included in crc calc */
+                } else {        /* setup DDCB for ATS architecture */
+                        *(__be64 *)&cmd->asiv[0]  = cpu_to_be64(dma_addr);
+                        *(__be32 *)&cmd->asiv[8]  = cpu_to_be32(tocopy);
+                        *(__be32 *)&cmd->asiv[12] = cpu_to_be32(0); /* resvd */
+                        *(__be64 *)&cmd->asiv[16] = cpu_to_be64(flash);
+                        *(__be32 *)&cmd->asiv[24] = cpu_to_be32(load->uid<<24);
+                        *(__be32 *)&cmd->asiv[28] = cpu_to_be32(0); /* CRC */
+
+                        /* rd/wr */
+                        cmd->ats = 0x5ULL << 44;
+                        cmd->asiv_length = 40; /* bytes included in crc calc */
+                }
+                cmd->asv_length  = 8;
+
+                /* we only get back the calculated CRC */
+                *(u64 *)&cmd->asv[0] = 0ULL;    /* 0x80 */
+
+                rc = __genwqe_execute_raw_ddcb(cd, cmd);
+
+                load->retc = cmd->retc;
+                load->attn = cmd->attn;
+                load->progress = cmd->progress;
+
+                if ((rc < 0) && (rc != -EBADMSG)) {
+                        ddcb_requ_free(cmd);
+                        goto free_buffer;
+                }
+
+                rc = copy_to_user(buf, xbuf, tocopy);
+                if (rc) {
+                        rc = -EFAULT;
+                        ddcb_requ_free(cmd);
+                        goto free_buffer;
+                }
+
+                /* We know that we can get retc 0x104 with CRC err */
+                if (((cmd->retc == DDCB_RETC_FAULT) &&
+                     (cmd->attn != 0x02)) ||  /* Normally ignore CRC error */
+                    ((cmd->retc == DDCB_RETC_COMPLETE) &&
+                     (cmd->attn != 0x00))) {  /* Everything was fine */
+                        rc = -EIO;
+                        ddcb_requ_free(cmd);
+                        goto free_buffer;
+                }
+
+                load->size  -= tocopy;
+                flash += tocopy;
+                buf += tocopy;
+                blocks_to_flash--;
+                ddcb_requ_free(cmd);
+        }
+        rc = 0;
+
+ free_buffer:
+        __genwqe_free_consistent(cd, FLASH_BLOCK, xbuf, dma_addr);
+        return rc;
+}
+
+static int genwqe_pin_mem(struct genwqe_file *cfile, struct genwqe_mem *m)
+{
+        int rc;
+        struct genwqe_dev *cd = cfile->cd;
+        struct pci_dev *pci_dev = cfile->cd->pci_dev;
+        struct dma_mapping *dma_map;
+        unsigned long map_addr;
+        unsigned long map_size;
+
+        if ((m->addr == 0x0) || (m->size == 0))
+                return -EINVAL;
+
+        map_addr = (m->addr & PAGE_MASK);
+        map_size = round_up(m->size + (m->addr & ~PAGE_MASK), PAGE_SIZE);
+
+        dma_map = kzalloc(sizeof(struct dma_mapping), GFP_ATOMIC);
+        if (dma_map == NULL)
+                return -ENOMEM;
+
+        genwqe_mapping_init(dma_map, GENWQE_MAPPING_SGL_PINNED);
+        rc = genwqe_user_vmap(cd, dma_map, (void *)map_addr, map_size, NULL);
+        if (rc != 0) {
+                dev_err(&pci_dev->dev,
+                        "[%s] genwqe_user_vmap rc=%d\n", __func__, rc);
+                return rc;
+        }
+
+        genwqe_add_pin(cfile, dma_map);
+        return 0;
+}
+
+static int genwqe_unpin_mem(struct genwqe_file *cfile, struct genwqe_mem *m)
+{
+        struct genwqe_dev *cd = cfile->cd;
+        struct dma_mapping *dma_map;
+        unsigned long map_addr;
+        unsigned long map_size;
+
+        if (m->addr == 0x0)
+                return -EINVAL;
+
+        map_addr = (m->addr & PAGE_MASK);
+        map_size = round_up(m->size + (m->addr & ~PAGE_MASK), PAGE_SIZE);
+
+        dma_map = genwqe_search_pin(cfile, map_addr, map_size, NULL);
+        if (dma_map == NULL)
+                return -ENOENT;
+
+        genwqe_del_pin(cfile, dma_map);
+        genwqe_user_vunmap(cd, dma_map, NULL);
+        kfree(dma_map);
+        return 0;
+}
+
+/**
+ * ddcb_cmd_cleanup() - Remove dynamically created fixup entries
+ *
+ * Only if there are any. Pinnings are not removed.
+ */
+static int ddcb_cmd_cleanup(struct genwqe_file *cfile, struct ddcb_requ *req)
+{
+        unsigned int i;
+        struct dma_mapping *dma_map;
+        struct genwqe_dev *cd = cfile->cd;
+
+        for (i = 0; i < DDCB_FIXUPS; i++) {
+                dma_map = &req->dma_mappings[i];
+
+                if (dma_mapping_used(dma_map)) {
+                        __genwqe_del_mapping(cfile, dma_map);
+                        genwqe_user_vunmap(cd, dma_map, req);
+                }
+                if (req->sgl[i] != NULL) {
+                        genwqe_free_sgl(cd, req->sgl[i],
+                                       req->sgl_dma_addr[i],
+                                       req->sgl_size[i]);
+                        req->sgl[i] = NULL;
+                        req->sgl_dma_addr[i] = 0x0;
+                        req->sgl_size[i] = 0;
+                }
+
+        }
+        return 0;
+}
+
+/**
+ * ddcb_cmd_fixups() - Establish DMA fixups/sglists for user memory references
+ *
+ * Before the DDCB gets executed we need to handle the fixups. We
+ * replace the user-space addresses with DMA addresses or do
+ * additional setup work e.g. generating a scatter-gather list which
+ * is used to describe the memory referred to in the fixup.
+ */
+static int ddcb_cmd_fixups(struct genwqe_file *cfile, struct ddcb_requ *req)
+{
+        int rc;
+        unsigned int asiv_offs, i;
+        struct genwqe_dev *cd = cfile->cd;
+        struct genwqe_ddcb_cmd *cmd = &req->cmd;
+        struct dma_mapping *m;
+        const char *type = "UNKNOWN";
+
+        for (i = 0, asiv_offs = 0x00; asiv_offs <= 0x58;
+             i++, asiv_offs += 0x08) {
+
+                u64 u_addr;
+                dma_addr_t d_addr;
+                u32 u_size = 0;
+                u64 ats_flags;
+
+                ats_flags = ATS_GET_FLAGS(cmd->ats, asiv_offs);
+
+                switch (ats_flags) {
+
+                case ATS_TYPE_DATA:
+                        break;  /* nothing to do here */
+
+                case ATS_TYPE_FLAT_RDWR:
+                case ATS_TYPE_FLAT_RD: {
+                        u_addr = be64_to_cpu(*((__be64 *)&cmd->
+                                               asiv[asiv_offs]));
+                        u_size = be32_to_cpu(*((__be32 *)&cmd->
+                                               asiv[asiv_offs + 0x08]));
+
+                        /*
+                         * No data available. Ignore u_addr in this
+                         * case and set addr to 0. Hardware must not
+                         * fetch the buffer.
+                         */
+                        if (u_size == 0x0) {
+                                *((__be64 *)&cmd->asiv[asiv_offs]) =
+                                        cpu_to_be64(0x0);
+                                break;
+                        }
+
+                        m = __genwqe_search_mapping(cfile, u_addr, u_size,
+                                                   &d_addr, NULL);
+                        if (m == NULL) {
+                                rc = -EFAULT;
+                                goto err_out;
+                        }
+
+                        *((__be64 *)&cmd->asiv[asiv_offs]) =
+                                cpu_to_be64(d_addr);
+                        break;
+                }
+
+                case ATS_TYPE_SGL_RDWR:
+                case ATS_TYPE_SGL_RD: {
+                        int page_offs, nr_pages, offs;
+
+                        u_addr = be64_to_cpu(*((__be64 *)
+                                               &cmd->asiv[asiv_offs]));
+                        u_size = be32_to_cpu(*((__be32 *)
+                                               &cmd->asiv[asiv_offs + 0x08]));
+
+                        /*
+                         * No data available. Ignore u_addr in this
+                         * case and set addr to 0. Hardware must not
+                         * fetch the empty sgl.
+                         */
+                        if (u_size == 0x0) {
+                                *((__be64 *)&cmd->asiv[asiv_offs]) =
+                                        cpu_to_be64(0x0);
+                                break;
+                        }
+
+                        m = genwqe_search_pin(cfile, u_addr, u_size, NULL);
+                        if (m != NULL) {
+                                type = "PINNING";
+                                page_offs = (u_addr -
+                                             (u64)m->u_vaddr)/PAGE_SIZE;
+                        } else {
+                                type = "MAPPING";
+                                m = &req->dma_mappings[i];
+
+                                genwqe_mapping_init(m,
+                                                    GENWQE_MAPPING_SGL_TEMP);
+                                rc = genwqe_user_vmap(cd, m, (void *)u_addr,
+                                                      u_size, req);
+                                if (rc != 0)
+                                        goto err_out;
+
+                                __genwqe_add_mapping(cfile, m);
+                                page_offs = 0;
+                        }
+
+                        offs = offset_in_page(u_addr);
+                        nr_pages = DIV_ROUND_UP(offs + u_size, PAGE_SIZE);
+
+                        /* create genwqe style scatter gather list */
+                        req->sgl[i] = genwqe_alloc_sgl(cd, m->nr_pages,
+                                                      &req->sgl_dma_addr[i],
+                                                      &req->sgl_size[i]);
+                        if (req->sgl[i] == NULL) {
+                                rc = -ENOMEM;
+                                goto err_out;
+                        }
+                        genwqe_setup_sgl(cd, offs, u_size,
+                                        req->sgl[i],
+                                        req->sgl_dma_addr[i],
+                                        req->sgl_size[i],
+                                        m->dma_list,
+                                        page_offs,
+                                        nr_pages);
+
+                        *((__be64 *)&cmd->asiv[asiv_offs]) =
+                                cpu_to_be64(req->sgl_dma_addr[i]);
+
+                        break;
+                }
+                default:
+                        rc = -EINVAL;
+                        goto err_out;
+                }
+        }
+        return 0;
+
+ err_out:
+        ddcb_cmd_cleanup(cfile, req);
+        return rc;
+}
+
+/**
+ * genwqe_execute_ddcb() - Execute DDCB using userspace address fixups
+ *
+ * The code will build up the translation tables or lookup the
+ * contignous memory allocation table to find the right translations
+ * and DMA addresses.
+ */
+static int genwqe_execute_ddcb(struct genwqe_file *cfile,
+                               struct genwqe_ddcb_cmd *cmd)
+{
+        int rc;
+        struct genwqe_dev *cd = cfile->cd;
+        struct ddcb_requ *req = container_of(cmd, struct ddcb_requ, cmd);
+
+        rc = ddcb_cmd_fixups(cfile, req);
+        if (rc != 0)
+                return rc;
+
+        rc = __genwqe_execute_raw_ddcb(cd, cmd);
+        ddcb_cmd_cleanup(cfile, req);
+        return rc;
+}
+
+static int do_execute_ddcb(struct genwqe_file *cfile,
+                           unsigned long arg, int raw)
+{
+        int rc;
+        struct genwqe_ddcb_cmd *cmd;
+        struct ddcb_requ *req;
+        struct genwqe_dev *cd = cfile->cd;
+
+        cmd = ddcb_requ_alloc();
+        if (cmd == NULL)
+                return -ENOMEM;
+
+        req = container_of(cmd, struct ddcb_requ, cmd);
+
+        if (copy_from_user(cmd, (void __user *)arg, sizeof(*cmd))) {
+                ddcb_requ_free(cmd);
+                return -EFAULT;
+        }
+
+        if (!raw)
+                rc = genwqe_execute_ddcb(cfile, cmd);
+        else
+                rc = __genwqe_execute_raw_ddcb(cd, cmd);
+
+        /* Copy back only the modifed fields. Do not copy ASIV
+           back since the copy got modified by the driver. */
+        if (copy_to_user((void __user *)arg, cmd,
+                         sizeof(*cmd) - DDCB_ASIV_LENGTH)) {
+                ddcb_requ_free(cmd);
+                return -EFAULT;
+        }
+
+        ddcb_requ_free(cmd);
+        return rc;
+}
+
+/**
+ * genwqe_ioctl() - IO control
+ * @filp:       file handle
+ * @cmd:        command identifier (passed from user)
+ * @arg:        argument (passed from user)
+ *
+ * Return: 0 success
+ */
+static long genwqe_ioctl(struct file *filp, unsigned int cmd,
+                         unsigned long arg)
+{
+        int rc = 0;
+        struct genwqe_file *cfile = (struct genwqe_file *)filp->private_data;
+        struct genwqe_dev *cd = cfile->cd;
+        struct genwqe_reg_io __user *io;
+        u64 val;
+        u32 reg_offs;
+
+        if (_IOC_TYPE(cmd) != GENWQE_IOC_CODE)
+                return -EINVAL;
+
+        switch (cmd) {
+
+        case GENWQE_GET_CARD_STATE:
+                put_user(cd->card_state, (enum genwqe_card_state __user *)arg);
+                return 0;
+
+                /* Register access */
+        case GENWQE_READ_REG64: {
+                io = (struct genwqe_reg_io __user *)arg;
+
+                if (get_user(reg_offs, &io->num))
+                        return -EFAULT;
+
+                if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x7))
+                        return -EINVAL;
+
+                val = __genwqe_readq(cd, reg_offs);
+                put_user(val, &io->val64);
+                return 0;
+        }
+
+        case GENWQE_WRITE_REG64: {
+                io = (struct genwqe_reg_io __user *)arg;
+
+                if (!capable(CAP_SYS_ADMIN))
+                        return -EPERM;
+
+                if ((filp->f_flags & O_ACCMODE) == O_RDONLY)
+                        return -EPERM;
+
+                if (get_user(reg_offs, &io->num))
+                        return -EFAULT;
+
+                if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x7))
+                        return -EINVAL;
+
+                if (get_user(val, &io->val64))
+                        return -EFAULT;
+
+                __genwqe_writeq(cd, reg_offs, val);
+                return 0;
+        }
+
+        case GENWQE_READ_REG32: {
+                io = (struct genwqe_reg_io __user *)arg;
+
+                if (get_user(reg_offs, &io->num))
+                        return -EFAULT;
+
+                if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x3))
+                        return -EINVAL;
+
+                val = __genwqe_readl(cd, reg_offs);
+                put_user(val, &io->val64);
+                return 0;
+        }
+
+        case GENWQE_WRITE_REG32: {
+                io = (struct genwqe_reg_io __user *)arg;
+
+                if (!capable(CAP_SYS_ADMIN))
+                        return -EPERM;
+
+                if ((filp->f_flags & O_ACCMODE) == O_RDONLY)
+                        return -EPERM;
+
+                if (get_user(reg_offs, &io->num))
+                        return -EFAULT;
+
+                if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x3))
+                        return -EINVAL;
+
+                if (get_user(val, &io->val64))
+                        return -EFAULT;
+
+                __genwqe_writel(cd, reg_offs, val);
+                return 0;
+        }
+
+                /* Flash update/reading */
+        case GENWQE_SLU_UPDATE: {
+                struct genwqe_bitstream load;
+
+                if (!genwqe_is_privileged(cd))
+                        return -EPERM;
+
+                if ((filp->f_flags & O_ACCMODE) == O_RDONLY)
+                        return -EPERM;
+
+                if (copy_from_user(&load, (void __user *)arg,
+                                   sizeof(load)))
+                        return -EFAULT;
+
+                rc = do_flash_update(cfile, &load);
+
+                if (copy_to_user((void __user *)arg, &load, sizeof(load)))
+                        return -EFAULT;
+
+                return rc;
+        }
+
+        case GENWQE_SLU_READ: {
+                struct genwqe_bitstream load;
+
+                if (!genwqe_is_privileged(cd))
+                        return -EPERM;
+
+                if (genwqe_flash_readback_fails(cd))
+                        return -ENOSPC;  /* known to fail for old versions */
+
+                if (copy_from_user(&load, (void __user *)arg, sizeof(load)))
+                        return -EFAULT;
+
+                rc = do_flash_read(cfile, &load);
+
+                if (copy_to_user((void __user *)arg, &load, sizeof(load)))
+                        return -EFAULT;
+
+                return rc;
+        }
+
+                /* memory pinning and unpinning */
+        case GENWQE_PIN_MEM: {
+                struct genwqe_mem m;
+
+                if (copy_from_user(&m, (void __user *)arg, sizeof(m)))
+                        return -EFAULT;
+
+                return genwqe_pin_mem(cfile, &m);
+        }
+
+        case GENWQE_UNPIN_MEM: {
+                struct genwqe_mem m;
+
+                if (copy_from_user(&m, (void __user *)arg, sizeof(m)))
+                        return -EFAULT;
+
+                return genwqe_unpin_mem(cfile, &m);
+        }
+
+                /* launch an DDCB and wait for completion */
+        case GENWQE_EXECUTE_DDCB:
+                return do_execute_ddcb(cfile, arg, 0);
+
+        case GENWQE_EXECUTE_RAW_DDCB: {
+
+                if (!capable(CAP_SYS_ADMIN))
+                        return -EPERM;
+
+                return do_execute_ddcb(cfile, arg, 1);
+        }
+
+        default:
+                return -EINVAL;
+        }
+
+        return rc;
+}
+
+#if defined(CONFIG_COMPAT)
+/**
+ * genwqe_compat_ioctl() - Compatibility ioctl
+ *
+ * Called whenever a 32-bit process running under a 64-bit kernel
+ * performs an ioctl on /dev/genwqe<n>_card.
+ *
+ * @filp:        file pointer.
+ * @cmd:         command.
+ * @arg:         user argument.
+ * Return:       zero on success or negative number on failure.
+ */
+static long genwqe_compat_ioctl(struct file *filp, unsigned int cmd,
+                                unsigned long arg)
+{
+        return genwqe_ioctl(filp, cmd, arg);
+}
+#endif /* defined(CONFIG_COMPAT) */
+
+static const struct file_operations genwqe_fops = {
+        .owner          = THIS_MODULE,
+        .open           = genwqe_open,
+        .fasync         = genwqe_fasync,
+        .mmap           = genwqe_mmap,
+        .unlocked_ioctl = genwqe_ioctl,
+#if defined(CONFIG_COMPAT)
+        .compat_ioctl   = genwqe_compat_ioctl,
+#endif
+        .release        = genwqe_release,
+};
+
+static int genwqe_device_initialized(struct genwqe_dev *cd)
+{
+        return cd->dev != NULL;
+}
+
+/**
+ * genwqe_device_create() - Create and configure genwqe char device
+ * @cd:      genwqe device descriptor
+ *
+ * This function must be called before we create any more genwqe
+ * character devices, because it is allocating the major and minor
+ * number which are supposed to be used by the client drivers.
+ */
+int genwqe_device_create(struct genwqe_dev *cd)
+{
+        int rc;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        /*
+         * Here starts the individual setup per client. It must
+         * initialize its own cdev data structure with its own fops.
+         * The appropriate devnum needs to be created. The ranges must
+         * not overlap.
+         */
+        rc = alloc_chrdev_region(&cd->devnum_genwqe, 0,
+                                 GENWQE_MAX_MINOR, GENWQE_DEVNAME);
+        if (rc < 0) {
+                dev_err(&pci_dev->dev, "err: alloc_chrdev_region failed\n");
+                goto err_dev;
+        }
+
+        cdev_init(&cd->cdev_genwqe, &genwqe_fops);
+        cd->cdev_genwqe.owner = THIS_MODULE;
+
+        rc = cdev_add(&cd->cdev_genwqe, cd->devnum_genwqe, 1);
+        if (rc < 0) {
+                dev_err(&pci_dev->dev, "err: cdev_add failed\n");
+                goto err_add;
+        }
+
+        /*
+         * Finally the device in /dev/... must be created. The rule is
+         * to use card%d_clientname for each created device.
+         */
+        cd->dev = device_create_with_groups(cd->class_genwqe,
+                                            &cd->pci_dev->dev,
+                                            cd->devnum_genwqe, cd,
+                                            genwqe_attribute_groups,
+                                            GENWQE_DEVNAME "%u_card",
+                                            cd->card_idx);
+        if (IS_ERR(cd->dev)) {
+                rc = PTR_ERR(cd->dev);
+                goto err_cdev;
+        }
+
+        rc = genwqe_init_debugfs(cd);
+        if (rc != 0)
+                goto err_debugfs;
+
+        return 0;
+
+ err_debugfs:
+        device_destroy(cd->class_genwqe, cd->devnum_genwqe);
+ err_cdev:
+        cdev_del(&cd->cdev_genwqe);
+ err_add:
+        unregister_chrdev_region(cd->devnum_genwqe, GENWQE_MAX_MINOR);
+ err_dev:
+        cd->dev = NULL;
+        return rc;
+}
+
+static int genwqe_inform_and_stop_processes(struct genwqe_dev *cd)
+{
+        int rc;
+        unsigned int i;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if (!genwqe_open_files(cd))
+                return 0;
+
+        dev_warn(&pci_dev->dev, "[%s] send SIGIO and wait ...\n", __func__);
+
+        rc = genwqe_kill_fasync(cd, SIGIO);
+        if (rc > 0) {
+                /* give kill_timeout seconds to close file descriptors ... */
+                for (i = 0; (i < genwqe_kill_timeout) &&
+                             genwqe_open_files(cd); i++) {
+                        dev_info(&pci_dev->dev, "  %d sec ...", i);
+
+                        cond_resched();
+                        msleep(1000);
+                }
+
+                /* if no open files we can safely continue, else ... */
+                if (!genwqe_open_files(cd))
+                        return 0;
+
+                dev_warn(&pci_dev->dev,
+                         "[%s] send SIGKILL and wait ...\n", __func__);
+
+                rc = genwqe_force_sig(cd, SIGKILL); /* force terminate */
+                if (rc) {
+                        /* Give kill_timout more seconds to end processes */
+                        for (i = 0; (i < genwqe_kill_timeout) &&
+                                     genwqe_open_files(cd); i++) {
+                                dev_warn(&pci_dev->dev, "  %d sec ...", i);
+
+                                cond_resched();
+                                msleep(1000);
+                        }
+                }
+        }
+        return 0;
+}
+
+/**
+ * genwqe_device_remove() - Remove genwqe's char device
+ *
+ * This function must be called after the client devices are removed
+ * because it will free the major/minor number range for the genwqe
+ * drivers.
+ *
+ * This function must be robust enough to be called twice.
+ */
+int genwqe_device_remove(struct genwqe_dev *cd)
+{
+        int rc;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if (!genwqe_device_initialized(cd))
+                return 1;
+
+        genwqe_inform_and_stop_processes(cd);
+
+        /*
+         * We currently do wait until all filedescriptors are
+         * closed. This leads to a problem when we abort the
+         * application which will decrease this reference from
+         * 1/unused to 0/illegal and not from 2/used 1/empty.
+         */
+        rc = atomic_read(&cd->cdev_genwqe.kobj.kref.refcount);
+        if (rc != 1) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: cdev_genwqe...refcount=%d\n", __func__, rc);
+                panic("Fatal err: cannot free resources with pending references!");
+        }
+
+        genqwe_exit_debugfs(cd);
+        device_destroy(cd->class_genwqe, cd->devnum_genwqe);
+        cdev_del(&cd->cdev_genwqe);
+        unregister_chrdev_region(cd->devnum_genwqe, GENWQE_MAX_MINOR);
+        cd->dev = NULL;
+
+        return 0;
+}
diff --git a/drivers/misc/genwqe/card_sysfs.c b/drivers/misc/genwqe/card_sysfs.c
new file mode 100644
index 000000000000..a72a99266c3c
--- /dev/null
+++ b/drivers/misc/genwqe/card_sysfs.c
@@ -0,0 +1,288 @@
+/**
+ * IBM Accelerator Family 'GenWQE'
+ *
+ * (C) Copyright IBM Corp. 2013
+ *
+ * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
+ * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
+ * Author: Michael Jung <mijung@de.ibm.com>
+ * Author: Michael Ruettger <michael@ibmra.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Sysfs interfaces for the GenWQE card. There are attributes to query
+ * the version of the bitstream as well as some for the driver. For
+ * debugging, please also see the debugfs interfaces of this driver.
+ */
+
+#include <linux/version.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/string.h>
+#include <linux/fs.h>
+#include <linux/sysfs.h>
+#include <linux/ctype.h>
+#include <linux/device.h>
+
+#include "card_base.h"
+#include "card_ddcb.h"
+
+static const char * const genwqe_types[] = {
+        [GENWQE_TYPE_ALTERA_230] = "GenWQE4-230",
+        [GENWQE_TYPE_ALTERA_530] = "GenWQE4-530",
+        [GENWQE_TYPE_ALTERA_A4]  = "GenWQE5-A4",
+        [GENWQE_TYPE_ALTERA_A7]  = "GenWQE5-A7",
+};
+
+static ssize_t status_show(struct device *dev, struct device_attribute *attr,
+                           char *buf)
+{
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+        const char *cs[GENWQE_CARD_STATE_MAX] = { "unused", "used", "error" };
+
+        return sprintf(buf, "%s\n", cs[cd->card_state]);
+}
+static DEVICE_ATTR_RO(status);
+
+static ssize_t appid_show(struct device *dev, struct device_attribute *attr,
+                          char *buf)
+{
+        char app_name[5];
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+
+        genwqe_read_app_id(cd, app_name, sizeof(app_name));
+        return sprintf(buf, "%s\n", app_name);
+}
+static DEVICE_ATTR_RO(appid);
+
+static ssize_t version_show(struct device *dev, struct device_attribute *attr,
+                            char *buf)
+{
+        u64 slu_id, app_id;
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+
+        slu_id = __genwqe_readq(cd, IO_SLU_UNITCFG);
+        app_id = __genwqe_readq(cd, IO_APP_UNITCFG);
+
+        return sprintf(buf, "%016llx.%016llx\n", slu_id, app_id);
+}
+static DEVICE_ATTR_RO(version);
+
+static ssize_t type_show(struct device *dev, struct device_attribute *attr,
+                         char *buf)
+{
+        u8 card_type;
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+
+        card_type = genwqe_card_type(cd);
+        return sprintf(buf, "%s\n", (card_type >= ARRAY_SIZE(genwqe_types)) ?
+                       "invalid" : genwqe_types[card_type]);
+}
+static DEVICE_ATTR_RO(type);
+
+static ssize_t driver_show(struct device *dev, struct device_attribute *attr,
+                           char *buf)
+{
+        return sprintf(buf, "%s\n", DRV_VERS_STRING);
+}
+static DEVICE_ATTR_RO(driver);
+
+static ssize_t tempsens_show(struct device *dev, struct device_attribute *attr,
+                             char *buf)
+{
+        u64 tempsens;
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+
+        tempsens = __genwqe_readq(cd, IO_SLU_TEMPERATURE_SENSOR);
+        return sprintf(buf, "%016llx\n", tempsens);
+}
+static DEVICE_ATTR_RO(tempsens);
+
+static ssize_t freerunning_timer_show(struct device *dev,
+                                      struct device_attribute *attr,
+                                      char *buf)
+{
+        u64 t;
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+
+        t = __genwqe_readq(cd, IO_SLC_FREE_RUNNING_TIMER);
+        return sprintf(buf, "%016llx\n", t);
+}
+static DEVICE_ATTR_RO(freerunning_timer);
+
+static ssize_t queue_working_time_show(struct device *dev,
+                                       struct device_attribute *attr,
+                                       char *buf)
+{
+        u64 t;
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+
+        t = __genwqe_readq(cd, IO_SLC_QUEUE_WTIME);
+        return sprintf(buf, "%016llx\n", t);
+}
+static DEVICE_ATTR_RO(queue_working_time);
+
+static ssize_t base_clock_show(struct device *dev,
+                               struct device_attribute *attr,
+                               char *buf)
+{
+        u64 base_clock;
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+
+        base_clock = genwqe_base_clock_frequency(cd);
+        return sprintf(buf, "%lld\n", base_clock);
+}
+static DEVICE_ATTR_RO(base_clock);
+
+/**
+ * curr_bitstream_show() - Show the current bitstream id
+ *
+ * There is a bug in some old versions of the CPLD which selects the
+ * bitstream, which causes the IO_SLU_BITSTREAM register to report
+ * unreliable data in very rare cases. This makes this sysfs
+ * unreliable up to the point were a new CPLD version is being used.
+ *
+ * Unfortunately there is no automatic way yet to query the CPLD
+ * version, such that you need to manually ensure via programming
+ * tools that you have a recent version of the CPLD software.
+ *
+ * The proposed circumvention is to use a special recovery bitstream
+ * on the backup partition (0) to identify problems while loading the
+ * image.
+ */
+static ssize_t curr_bitstream_show(struct device *dev,
+                                   struct device_attribute *attr, char *buf)
+{
+        int curr_bitstream;
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+
+        curr_bitstream = __genwqe_readq(cd, IO_SLU_BITSTREAM) & 0x1;
+        return sprintf(buf, "%d\n", curr_bitstream);
+}
+static DEVICE_ATTR_RO(curr_bitstream);
+
+/**
+ * next_bitstream_show() - Show the next activated bitstream
+ *
+ * IO_SLC_CFGREG_SOFTRESET: This register can only be accessed by the PF.
+ */
+static ssize_t next_bitstream_show(struct device *dev,
+                                   struct device_attribute *attr, char *buf)
+{
+        int next_bitstream;
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+
+        switch ((cd->softreset & 0xc) >> 2) {
+        case 0x2:
+                next_bitstream =  0;
+                break;
+        case 0x3:
+                next_bitstream =  1;
+                break;
+        default:
+                next_bitstream = -1;
+                break;          /* error */
+        }
+        return sprintf(buf, "%d\n", next_bitstream);
+}
+
+static ssize_t next_bitstream_store(struct device *dev,
+                                    struct device_attribute *attr,
+                                    const char *buf, size_t count)
+{
+        int partition;
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+
+        if (kstrtoint(buf, 0, &partition) < 0)
+                return -EINVAL;
+
+        switch (partition) {
+        case 0x0:
+                cd->softreset = 0x78;
+                break;
+        case 0x1:
+                cd->softreset = 0x7c;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET, cd->softreset);
+        return count;
+}
+static DEVICE_ATTR_RW(next_bitstream);
+
+/*
+ * Create device_attribute structures / params: name, mode, show, store
+ * additional flag if valid in VF
+ */
+static struct attribute *genwqe_attributes[] = {
+        &dev_attr_tempsens.attr,
+        &dev_attr_next_bitstream.attr,
+        &dev_attr_curr_bitstream.attr,
+        &dev_attr_base_clock.attr,
+        &dev_attr_driver.attr,
+        &dev_attr_type.attr,
+        &dev_attr_version.attr,
+        &dev_attr_appid.attr,
+        &dev_attr_status.attr,
+        &dev_attr_freerunning_timer.attr,
+        &dev_attr_queue_working_time.attr,
+        NULL,
+};
+
+static struct attribute *genwqe_normal_attributes[] = {
+        &dev_attr_driver.attr,
+        &dev_attr_type.attr,
+        &dev_attr_version.attr,
+        &dev_attr_appid.attr,
+        &dev_attr_status.attr,
+        &dev_attr_freerunning_timer.attr,
+        &dev_attr_queue_working_time.attr,
+        NULL,
+};
+
+/**
+ * genwqe_is_visible() - Determine if sysfs attribute should be visible or not
+ *
+ * VFs have restricted mmio capabilities, so not all sysfs entries
+ * are allowed in VFs.
+ */
+static umode_t genwqe_is_visible(struct kobject *kobj,
+                                 struct attribute *attr, int n)
+{
+        unsigned int j;
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct genwqe_dev *cd = dev_get_drvdata(dev);
+        umode_t mode = attr->mode;
+
+        if (genwqe_is_privileged(cd))
+                return mode;
+
+        for (j = 0; genwqe_normal_attributes[j] != NULL;  j++)
+                if (genwqe_normal_attributes[j] == attr)
+                        return mode;
+
+        return 0;
+}
+
+static struct attribute_group genwqe_attribute_group = {
+        .is_visible = genwqe_is_visible,
+        .attrs      = genwqe_attributes,
+};
+
+const struct attribute_group *genwqe_attribute_groups[] = {
+        &genwqe_attribute_group,
+        NULL,
+};
diff --git a/drivers/misc/genwqe/card_utils.c b/drivers/misc/genwqe/card_utils.c
new file mode 100644
index 000000000000..6b1a6ef9f1a8
--- /dev/null
+++ b/drivers/misc/genwqe/card_utils.c
@@ -0,0 +1,944 @@
+/**
+ * IBM Accelerator Family 'GenWQE'
+ *
+ * (C) Copyright IBM Corp. 2013
+ *
+ * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
+ * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
+ * Author: Michael Jung <mijung@de.ibm.com>
+ * Author: Michael Ruettger <michael@ibmra.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Miscelanous functionality used in the other GenWQE driver parts.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/sched.h>
+#include <linux/vmalloc.h>
+#include <linux/page-flags.h>
+#include <linux/scatterlist.h>
+#include <linux/hugetlb.h>
+#include <linux/iommu.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/ctype.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <asm/pgtable.h>
+
+#include "genwqe_driver.h"
+#include "card_base.h"
+#include "card_ddcb.h"
+
+/**
+ * __genwqe_writeq() - Write 64-bit register
+ * @cd:         genwqe device descriptor
+ * @byte_offs:  byte offset within BAR
+ * @val:        64-bit value
+ *
+ * Return: 0 if success; < 0 if error
+ */
+int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val)
+{
+        if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE)
+                return -EIO;
+
+        if (cd->mmio == NULL)
+                return -EIO;
+
+        __raw_writeq((__force u64)cpu_to_be64(val), cd->mmio + byte_offs);
+        return 0;
+}
+
+/**
+ * __genwqe_readq() - Read 64-bit register
+ * @cd:         genwqe device descriptor
+ * @byte_offs:  offset within BAR
+ *
+ * Return: value from register
+ */
+u64 __genwqe_readq(struct genwqe_dev *cd, u64 byte_offs)
+{
+        if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE)
+                return 0xffffffffffffffffull;
+
+        if ((cd->err_inject & GENWQE_INJECT_GFIR_FATAL) &&
+            (byte_offs == IO_SLC_CFGREG_GFIR))
+                return 0x000000000000ffffull;
+
+        if ((cd->err_inject & GENWQE_INJECT_GFIR_INFO) &&
+            (byte_offs == IO_SLC_CFGREG_GFIR))
+                return 0x00000000ffff0000ull;
+
+        if (cd->mmio == NULL)
+                return 0xffffffffffffffffull;
+
+        return be64_to_cpu((__force __be64)__raw_readq(cd->mmio + byte_offs));
+}
+
+/**
+ * __genwqe_writel() - Write 32-bit register
+ * @cd:         genwqe device descriptor
+ * @byte_offs:  byte offset within BAR
+ * @val:        32-bit value
+ *
+ * Return: 0 if success; < 0 if error
+ */
+int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val)
+{
+        if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE)
+                return -EIO;
+
+        if (cd->mmio == NULL)
+                return -EIO;
+
+        __raw_writel((__force u32)cpu_to_be32(val), cd->mmio + byte_offs);
+        return 0;
+}
+
+/**
+ * __genwqe_readl() - Read 32-bit register
+ * @cd:         genwqe device descriptor
+ * @byte_offs:  offset within BAR
+ *
+ * Return: Value from register
+ */
+u32 __genwqe_readl(struct genwqe_dev *cd, u64 byte_offs)
+{
+        if (cd->err_inject & GENWQE_INJECT_HARDWARE_FAILURE)
+                return 0xffffffff;
+
+        if (cd->mmio == NULL)
+                return 0xffffffff;
+
+        return be32_to_cpu((__force __be32)__raw_readl(cd->mmio + byte_offs));
+}
+
+/**
+ * genwqe_read_app_id() - Extract app_id
+ *
+ * app_unitcfg need to be filled with valid data first
+ */
+int genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len)
+{
+        int i, j;
+        u32 app_id = (u32)cd->app_unitcfg;
+
+        memset(app_name, 0, len);
+        for (i = 0, j = 0; j < min(len, 4); j++) {
+                char ch = (char)((app_id >> (24 - j*8)) & 0xff);
+                if (ch == ' ')
+                        continue;
+                app_name[i++] = isprint(ch) ? ch : 'X';
+        }
+        return i;
+}
+
+/**
+ * genwqe_init_crc32() - Prepare a lookup table for fast crc32 calculations
+ *
+ * Existing kernel functions seem to use a different polynom,
+ * therefore we could not use them here.
+ *
+ * Genwqe's Polynomial = 0x20044009
+ */
+#define CRC32_POLYNOMIAL        0x20044009
+static u32 crc32_tab[256];      /* crc32 lookup table */
+
+void genwqe_init_crc32(void)
+{
+        int i, j;
+        u32 crc;
+
+        for (i = 0;  i < 256;  i++) {
+                crc = i << 24;
+                for (j = 0;  j < 8;  j++) {
+                        if (crc & 0x80000000)
+                                crc = (crc << 1) ^ CRC32_POLYNOMIAL;
+                        else
+                                crc = (crc << 1);
+                }
+                crc32_tab[i] = crc;
+        }
+}
+
+/**
+ * genwqe_crc32() - Generate 32-bit crc as required for DDCBs
+ * @buff:       pointer to data buffer
+ * @len:        length of data for calculation
+ * @init:       initial crc (0xffffffff at start)
+ *
+ * polynomial = x^32 * + x^29 + x^18 + x^14 + x^3 + 1 (0x20044009)
+
+ * Example: 4 bytes 0x01 0x02 0x03 0x04 with init=0xffffffff should
+ * result in a crc32 of 0xf33cb7d3.
+ *
+ * The existing kernel crc functions did not cover this polynom yet.
+ *
+ * Return: crc32 checksum.
+ */
+u32 genwqe_crc32(u8 *buff, size_t len, u32 init)
+{
+        int i;
+        u32 crc;
+
+        crc = init;
+        while (len--) {
+                i = ((crc >> 24) ^ *buff++) & 0xFF;
+                crc = (crc << 8) ^ crc32_tab[i];
+        }
+        return crc;
+}
+
+void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size,
+                               dma_addr_t *dma_handle)
+{
+        if (get_order(size) > MAX_ORDER)
+                return NULL;
+
+        return pci_alloc_consistent(cd->pci_dev, size, dma_handle);
+}
+
+void __genwqe_free_consistent(struct genwqe_dev *cd, size_t size,
+                             void *vaddr, dma_addr_t dma_handle)
+{
+        if (vaddr == NULL)
+                return;
+
+        pci_free_consistent(cd->pci_dev, size, vaddr, dma_handle);
+}
+
+static void genwqe_unmap_pages(struct genwqe_dev *cd, dma_addr_t *dma_list,
+                              int num_pages)
+{
+        int i;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        for (i = 0; (i < num_pages) && (dma_list[i] != 0x0); i++) {
+                pci_unmap_page(pci_dev, dma_list[i],
+                               PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+                dma_list[i] = 0x0;
+        }
+}
+
+static int genwqe_map_pages(struct genwqe_dev *cd,
+                           struct page **page_list, int num_pages,
+                           dma_addr_t *dma_list)
+{
+        int i;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        /* establish DMA mapping for requested pages */
+        for (i = 0; i < num_pages; i++) {
+                dma_addr_t daddr;
+
+                dma_list[i] = 0x0;
+                daddr = pci_map_page(pci_dev, page_list[i],
+                                     0,  /* map_offs */
+                                     PAGE_SIZE,
+                                     PCI_DMA_BIDIRECTIONAL);  /* FIXME rd/rw */
+
+                if (pci_dma_mapping_error(pci_dev, daddr)) {
+                        dev_err(&pci_dev->dev,
+                                "[%s] err: no dma addr daddr=%016llx!\n",
+                                __func__, (long long)daddr);
+                        goto err;
+                }
+
+                dma_list[i] = daddr;
+        }
+        return 0;
+
+ err:
+        genwqe_unmap_pages(cd, dma_list, num_pages);
+        return -EIO;
+}
+
+static int genwqe_sgl_size(int num_pages)
+{
+        int len, num_tlb = num_pages / 7;
+
+        len = sizeof(struct sg_entry) * (num_pages+num_tlb + 1);
+        return roundup(len, PAGE_SIZE);
+}
+
+struct sg_entry *genwqe_alloc_sgl(struct genwqe_dev *cd, int num_pages,
+                                  dma_addr_t *dma_addr, size_t *sgl_size)
+{
+        struct pci_dev *pci_dev = cd->pci_dev;
+        struct sg_entry *sgl;
+
+        *sgl_size = genwqe_sgl_size(num_pages);
+        if (get_order(*sgl_size) > MAX_ORDER) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: too much memory requested!\n", __func__);
+                return NULL;
+        }
+
+        sgl = __genwqe_alloc_consistent(cd, *sgl_size, dma_addr);
+        if (sgl == NULL) {
+                dev_err(&pci_dev->dev,
+                        "[%s] err: no memory available!\n", __func__);
+                return NULL;
+        }
+
+        return sgl;
+}
+
+int genwqe_setup_sgl(struct genwqe_dev *cd,
+                     unsigned long offs,
+                     unsigned long size,
+                     struct sg_entry *sgl,
+                     dma_addr_t dma_addr, size_t sgl_size,
+                     dma_addr_t *dma_list, int page_offs, int num_pages)
+{
+        int i = 0, j = 0, p;
+        unsigned long dma_offs, map_offs;
+        struct pci_dev *pci_dev = cd->pci_dev;
+        dma_addr_t prev_daddr = 0;
+        struct sg_entry *s, *last_s = NULL;
+
+        /* sanity checks */
+        if (offs > PAGE_SIZE) {
+                dev_err(&pci_dev->dev,
+                        "[%s] too large start offs %08lx\n", __func__, offs);
+                return -EFAULT;
+        }
+        if (sgl_size < genwqe_sgl_size(num_pages)) {
+                dev_err(&pci_dev->dev,
+                        "[%s] sgl_size too small %08lx for %d pages\n",
+                        __func__, sgl_size, num_pages);
+                return -EFAULT;
+        }
+
+        dma_offs = 128;         /* next block if needed/dma_offset */
+        map_offs = offs;        /* offset in first page */
+
+        s = &sgl[0];            /* first set of 8 entries */
+        p = 0;                  /* page */
+        while (p < num_pages) {
+                dma_addr_t daddr;
+                unsigned int size_to_map;
+
+                /* always write the chaining entry, cleanup is done later */
+                j = 0;
+                s[j].target_addr = cpu_to_be64(dma_addr + dma_offs);
+                s[j].len         = cpu_to_be32(128);
+                s[j].flags       = cpu_to_be32(SG_CHAINED);
+                j++;
+
+                while (j < 8) {
+                        /* DMA mapping for requested page, offs, size */
+                        size_to_map = min(size, PAGE_SIZE - map_offs);
+                        daddr = dma_list[page_offs + p] + map_offs;
+                        size -= size_to_map;
+                        map_offs = 0;
+
+                        if (prev_daddr == daddr) {
+                                u32 prev_len = be32_to_cpu(last_s->len);
+
+                                /* pr_info("daddr combining: "
+                                        "%016llx/%08x -> %016llx\n",
+                                        prev_daddr, prev_len, daddr); */
+
+                                last_s->len = cpu_to_be32(prev_len +
+                                                          size_to_map);
+
+                                p++; /* process next page */
+                                if (p == num_pages)
+                                        goto fixup;  /* nothing to do */
+
+                                prev_daddr = daddr + size_to_map;
+                                continue;
+                        }
+
+                        /* start new entry */
+                        s[j].target_addr = cpu_to_be64(daddr);
+                        s[j].len         = cpu_to_be32(size_to_map);
+                        s[j].flags       = cpu_to_be32(SG_DATA);
+                        prev_daddr = daddr + size_to_map;
+                        last_s = &s[j];
+                        j++;
+
+                        p++;    /* process next page */
+                        if (p == num_pages)
+                                goto fixup;  /* nothing to do */
+                }
+                dma_offs += 128;
+                s += 8;         /* continue 8 elements further */
+        }
+ fixup:
+        if (j == 1) {           /* combining happend on last entry! */
+                s -= 8;         /* full shift needed on previous sgl block */
+                j =  7;         /* shift all elements */
+        }
+
+        for (i = 0; i < j; i++) /* move elements 1 up */
+                s[i] = s[i + 1];
+
+        s[i].target_addr = cpu_to_be64(0);
+        s[i].len         = cpu_to_be32(0);
+        s[i].flags       = cpu_to_be32(SG_END_LIST);
+        return 0;
+}
+
+void genwqe_free_sgl(struct genwqe_dev *cd, struct sg_entry *sg_list,
+                    dma_addr_t dma_addr, size_t size)
+{
+        __genwqe_free_consistent(cd, size, sg_list, dma_addr);
+}
+
+/**
+ * free_user_pages() - Give pinned pages back
+ *
+ * Documentation of get_user_pages is in mm/memory.c:
+ *
+ * If the page is written to, set_page_dirty (or set_page_dirty_lock,
+ * as appropriate) must be called after the page is finished with, and
+ * before put_page is called.
+ *
+ * FIXME Could be of use to others and might belong in the generic
+ * code, if others agree. E.g.
+ *    ll_free_user_pages in drivers/staging/lustre/lustre/llite/rw26.c
+ *    ceph_put_page_vector in net/ceph/pagevec.c
+ *    maybe more?
+ */
+static int free_user_pages(struct page **page_list, unsigned int nr_pages,
+                           int dirty)
+{
+        unsigned int i;
+
+        for (i = 0; i < nr_pages; i++) {
+                if (page_list[i] != NULL) {
+                        if (dirty)
+                                set_page_dirty_lock(page_list[i]);
+                        put_page(page_list[i]);
+                }
+        }
+        return 0;
+}
+
+/**
+ * genwqe_user_vmap() - Map user-space memory to virtual kernel memory
+ * @cd:         pointer to genwqe device
+ * @m:          mapping params
+ * @uaddr:      user virtual address
+ * @size:       size of memory to be mapped
+ *
+ * We need to think about how we could speed this up. Of course it is
+ * not a good idea to do this over and over again, like we are
+ * currently doing it. Nevertheless, I am curious where on the path
+ * the performance is spend. Most probably within the memory
+ * allocation functions, but maybe also in the DMA mapping code.
+ *
+ * Restrictions: The maximum size of the possible mapping currently depends
+ *               on the amount of memory we can get using kzalloc() for the
+ *               page_list and pci_alloc_consistent for the sg_list.
+ *               The sg_list is currently itself not scattered, which could
+ *               be fixed with some effort. The page_list must be split into
+ *               PAGE_SIZE chunks too. All that will make the complicated
+ *               code more complicated.
+ *
+ * Return: 0 if success
+ */
+int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, void *uaddr,
+                     unsigned long size, struct ddcb_requ *req)
+{
+        int rc = -EINVAL;
+        unsigned long data, offs;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if ((uaddr == NULL) || (size == 0)) {
+                m->size = 0;    /* mark unused and not added */
+                return -EINVAL;
+        }
+        m->u_vaddr = uaddr;
+        m->size    = size;
+
+        /* determine space needed for page_list. */
+        data = (unsigned long)uaddr;
+        offs = offset_in_page(data);
+        m->nr_pages = DIV_ROUND_UP(offs + size, PAGE_SIZE);
+
+        m->page_list = kcalloc(m->nr_pages,
+                               sizeof(struct page *) + sizeof(dma_addr_t),
+                               GFP_KERNEL);
+        if (!m->page_list) {
+                dev_err(&pci_dev->dev, "err: alloc page_list failed\n");
+                m->nr_pages = 0;
+                m->u_vaddr = NULL;
+                m->size = 0;    /* mark unused and not added */
+                return -ENOMEM;
+        }
+        m->dma_list = (dma_addr_t *)(m->page_list + m->nr_pages);
+
+        /* pin user pages in memory */
+        rc = get_user_pages_fast(data & PAGE_MASK, /* page aligned addr */
+                                 m->nr_pages,
+                                 1,             /* write by caller */
+                                 m->page_list); /* ptrs to pages */
+
+        /* assumption: get_user_pages can be killed by signals. */
+        if (rc < m->nr_pages) {
+                free_user_pages(m->page_list, rc, 0);
+                rc = -EFAULT;
+                goto fail_get_user_pages;
+        }
+
+        rc = genwqe_map_pages(cd, m->page_list, m->nr_pages, m->dma_list);
+        if (rc != 0)
+                goto fail_free_user_pages;
+
+        return 0;
+
+ fail_free_user_pages:
+        free_user_pages(m->page_list, m->nr_pages, 0);
+
+ fail_get_user_pages:
+        kfree(m->page_list);
+        m->page_list = NULL;
+        m->dma_list = NULL;
+        m->nr_pages = 0;
+        m->u_vaddr = NULL;
+        m->size = 0;            /* mark unused and not added */
+        return rc;
+}
+
+/**
+ * genwqe_user_vunmap() - Undo mapping of user-space mem to virtual kernel
+ *                        memory
+ * @cd:         pointer to genwqe device
+ * @m:          mapping params
+ */
+int genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m,
+                       struct ddcb_requ *req)
+{
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if (!dma_mapping_used(m)) {
+                dev_err(&pci_dev->dev, "[%s] err: mapping %p not used!\n",
+                        __func__, m);
+                return -EINVAL;
+        }
+
+        if (m->dma_list)
+                genwqe_unmap_pages(cd, m->dma_list, m->nr_pages);
+
+        if (m->page_list) {
+                free_user_pages(m->page_list, m->nr_pages, 1);
+
+                kfree(m->page_list);
+                m->page_list = NULL;
+                m->dma_list = NULL;
+                m->nr_pages = 0;
+        }
+
+        m->u_vaddr = NULL;
+        m->size = 0;            /* mark as unused and not added */
+        return 0;
+}
+
+/**
+ * genwqe_card_type() - Get chip type SLU Configuration Register
+ * @cd:         pointer to the genwqe device descriptor
+ * Return: 0: Altera Stratix-IV 230
+ *         1: Altera Stratix-IV 530
+ *         2: Altera Stratix-V A4
+ *         3: Altera Stratix-V A7
+ */
+u8 genwqe_card_type(struct genwqe_dev *cd)
+{
+        u64 card_type = cd->slu_unitcfg;
+        return (u8)((card_type & IO_SLU_UNITCFG_TYPE_MASK) >> 20);
+}
+
+/**
+ * genwqe_card_reset() - Reset the card
+ * @cd:         pointer to the genwqe device descriptor
+ */
+int genwqe_card_reset(struct genwqe_dev *cd)
+{
+        u64 softrst;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if (!genwqe_is_privileged(cd))
+                return -ENODEV;
+
+        /* new SL */
+        __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET, 0x1ull);
+        msleep(1000);
+        __genwqe_readq(cd, IO_HSU_FIR_CLR);
+        __genwqe_readq(cd, IO_APP_FIR_CLR);
+        __genwqe_readq(cd, IO_SLU_FIR_CLR);
+
+        /*
+         * Read-modify-write to preserve the stealth bits
+         *
+         * For SL >= 039, Stealth WE bit allows removing
+         * the read-modify-wrote.
+         * r-m-w may require a mask 0x3C to avoid hitting hard
+         * reset again for error reset (should be 0, chicken).
+         */
+        softrst = __genwqe_readq(cd, IO_SLC_CFGREG_SOFTRESET) & 0x3cull;
+        __genwqe_writeq(cd, IO_SLC_CFGREG_SOFTRESET, softrst | 0x2ull);
+
+        /* give ERRORRESET some time to finish */
+        msleep(50);
+
+        if (genwqe_need_err_masking(cd)) {
+                dev_info(&pci_dev->dev,
+                         "[%s] masking errors for old bitstreams\n", __func__);
+                __genwqe_writeq(cd, IO_SLC_MISC_DEBUG, 0x0aull);
+        }
+        return 0;
+}
+
+int genwqe_read_softreset(struct genwqe_dev *cd)
+{
+        u64 bitstream;
+
+        if (!genwqe_is_privileged(cd))
+                return -ENODEV;
+
+        bitstream = __genwqe_readq(cd, IO_SLU_BITSTREAM) & 0x1;
+        cd->softreset = (bitstream == 0) ? 0x8ull : 0xcull;
+        return 0;
+}
+
+/**
+ * genwqe_set_interrupt_capability() - Configure MSI capability structure
+ * @cd:         pointer to the device
+ * Return: 0 if no error
+ */
+int genwqe_set_interrupt_capability(struct genwqe_dev *cd, int count)
+{
+        int rc;
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        rc = pci_enable_msi_block(pci_dev, count);
+        if (rc == 0)
+                cd->flags |= GENWQE_FLAG_MSI_ENABLED;
+        return rc;
+}
+
+/**
+ * genwqe_reset_interrupt_capability() - Undo genwqe_set_interrupt_capability()
+ * @cd:         pointer to the device
+ */
+void genwqe_reset_interrupt_capability(struct genwqe_dev *cd)
+{
+        struct pci_dev *pci_dev = cd->pci_dev;
+
+        if (cd->flags & GENWQE_FLAG_MSI_ENABLED) {
+                pci_disable_msi(pci_dev);
+                cd->flags &= ~GENWQE_FLAG_MSI_ENABLED;
+        }
+}
+
+/**
+ * set_reg_idx() - Fill array with data. Ignore illegal offsets.
+ * @cd:         card device
+ * @r:          debug register array
+ * @i:          index to desired entry
+ * @m:          maximum possible entries
+ * @addr:       addr which is read
+ * @index:      index in debug array
+ * @val:        read value
+ */
+static int set_reg_idx(struct genwqe_dev *cd, struct genwqe_reg *r,
+                       unsigned int *i, unsigned int m, u32 addr, u32 idx,
+                       u64 val)
+{
+        if (WARN_ON_ONCE(*i >= m))
+                return -EFAULT;
+
+        r[*i].addr = addr;
+        r[*i].idx = idx;
+        r[*i].val = val;
+        ++*i;
+        return 0;
+}
+
+static int set_reg(struct genwqe_dev *cd, struct genwqe_reg *r,
+                   unsigned int *i, unsigned int m, u32 addr, u64 val)
+{
+        return set_reg_idx(cd, r, i, m, addr, 0, val);
+}
+
+int genwqe_read_ffdc_regs(struct genwqe_dev *cd, struct genwqe_reg *regs,
+                         unsigned int max_regs, int all)
+{
+        unsigned int i, j, idx = 0;
+        u32 ufir_addr, ufec_addr, sfir_addr, sfec_addr;
+        u64 gfir, sluid, appid, ufir, ufec, sfir, sfec;
+
+        /* Global FIR */
+        gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
+        set_reg(cd, regs, &idx, max_regs, IO_SLC_CFGREG_GFIR, gfir);
+
+        /* UnitCfg for SLU */
+        sluid = __genwqe_readq(cd, IO_SLU_UNITCFG); /* 0x00000000 */
+        set_reg(cd, regs, &idx, max_regs, IO_SLU_UNITCFG, sluid);
+
+        /* UnitCfg for APP */
+        appid = __genwqe_readq(cd, IO_APP_UNITCFG); /* 0x02000000 */
+        set_reg(cd, regs, &idx, max_regs, IO_APP_UNITCFG, appid);
+
+        /* Check all chip Units */
+        for (i = 0; i < GENWQE_MAX_UNITS; i++) {
+
+                /* Unit FIR */
+                ufir_addr = (i << 24) | 0x008;
+                ufir = __genwqe_readq(cd, ufir_addr);
+                set_reg(cd, regs, &idx, max_regs, ufir_addr, ufir);
+
+                /* Unit FEC */
+                ufec_addr = (i << 24) | 0x018;
+                ufec = __genwqe_readq(cd, ufec_addr);
+                set_reg(cd, regs, &idx, max_regs, ufec_addr, ufec);
+
+                for (j = 0; j < 64; j++) {
+                        /* wherever there is a primary 1, read the 2ndary */
+                        if (!all && (!(ufir & (1ull << j))))
+                                continue;
+
+                        sfir_addr = (i << 24) | (0x100 + 8 * j);
+                        sfir = __genwqe_readq(cd, sfir_addr);
+                        set_reg(cd, regs, &idx, max_regs, sfir_addr, sfir);
+
+                        sfec_addr = (i << 24) | (0x300 + 8 * j);
+                        sfec = __genwqe_readq(cd, sfec_addr);
+                        set_reg(cd, regs, &idx, max_regs, sfec_addr, sfec);
+                }
+        }
+
+        /* fill with invalid data until end */
+        for (i = idx; i < max_regs; i++) {
+                regs[i].addr = 0xffffffff;
+                regs[i].val = 0xffffffffffffffffull;
+        }
+        return idx;
+}
+
+/**
+ * genwqe_ffdc_buff_size() - Calculates the number of dump registers
+ */
+int genwqe_ffdc_buff_size(struct genwqe_dev *cd, int uid)
+{
+        int entries = 0, ring, traps, traces, trace_entries;
+        u32 eevptr_addr, l_addr, d_len, d_type;
+        u64 eevptr, val, addr;
+
+        eevptr_addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_ERROR_POINTER;
+        eevptr = __genwqe_readq(cd, eevptr_addr);
+
+        if ((eevptr != 0x0) && (eevptr != -1ull)) {
+                l_addr = GENWQE_UID_OFFS(uid) | eevptr;
+
+                while (1) {
+                        val = __genwqe_readq(cd, l_addr);
+
+                        if ((val == 0x0) || (val == -1ull))
+                                break;
+
+                        /* 38:24 */
+                        d_len  = (val & 0x0000007fff000000ull) >> 24;
+
+                        /* 39 */
+                        d_type = (val & 0x0000008000000000ull) >> 36;
+
+                        if (d_type) {   /* repeat */
+                                entries += d_len;
+                        } else {        /* size in bytes! */
+                                entries += d_len >> 3;
+                        }
+
+                        l_addr += 8;
+                }
+        }
+
+        for (ring = 0; ring < 8; ring++) {
+                addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_DIAG_MAP(ring);
+                val = __genwqe_readq(cd, addr);
+
+                if ((val == 0x0ull) || (val == -1ull))
+                        continue;
+
+                traps = (val >> 24) & 0xff;
+                traces = (val >> 16) & 0xff;
+                trace_entries = val & 0xffff;
+
+                entries += traps + (traces * trace_entries);
+        }
+        return entries;
+}
+
+/**
+ * genwqe_ffdc_buff_read() - Implements LogoutExtendedErrorRegisters procedure
+ */
+int genwqe_ffdc_buff_read(struct genwqe_dev *cd, int uid,
+                          struct genwqe_reg *regs, unsigned int max_regs)
+{
+        int i, traps, traces, trace, trace_entries, trace_entry, ring;
+        unsigned int idx = 0;
+        u32 eevptr_addr, l_addr, d_addr, d_len, d_type;
+        u64 eevptr, e, val, addr;
+
+        eevptr_addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_ERROR_POINTER;
+        eevptr = __genwqe_readq(cd, eevptr_addr);
+
+        if ((eevptr != 0x0) && (eevptr != 0xffffffffffffffffull)) {
+                l_addr = GENWQE_UID_OFFS(uid) | eevptr;
+                while (1) {
+                        e = __genwqe_readq(cd, l_addr);
+                        if ((e == 0x0) || (e == 0xffffffffffffffffull))
+                                break;
+
+                        d_addr = (e & 0x0000000000ffffffull);       /* 23:0 */
+                        d_len  = (e & 0x0000007fff000000ull) >> 24; /* 38:24 */
+                        d_type = (e & 0x0000008000000000ull) >> 36; /* 39 */
+                        d_addr |= GENWQE_UID_OFFS(uid);
+
+                        if (d_type) {
+                                for (i = 0; i < (int)d_len; i++) {
+                                        val = __genwqe_readq(cd, d_addr);
+                                        set_reg_idx(cd, regs, &idx, max_regs,
+                                                    d_addr, i, val);
+                                }
+                        } else {
+                                d_len >>= 3; /* Size in bytes! */
+                                for (i = 0; i < (int)d_len; i++, d_addr += 8) {
+                                        val = __genwqe_readq(cd, d_addr);
+                                        set_reg_idx(cd, regs, &idx, max_regs,
+                                                    d_addr, 0, val);
+                                }
+                        }
+                        l_addr += 8;
+                }
+        }
+
+        /*
+         * To save time, there are only 6 traces poplulated on Uid=2,
+         * Ring=1. each with iters=512.
+         */
+        for (ring = 0; ring < 8; ring++) { /* 0 is fls, 1 is fds,
+                                              2...7 are ASI rings */
+                addr = GENWQE_UID_OFFS(uid) | IO_EXTENDED_DIAG_MAP(ring);
+                val = __genwqe_readq(cd, addr);
+
+                if ((val == 0x0ull) || (val == -1ull))
+                        continue;
+
+                traps = (val >> 24) & 0xff;     /* Number of Traps      */
+                traces = (val >> 16) & 0xff;    /* Number of Traces     */
+                trace_entries = val & 0xffff;   /* Entries per trace    */
+
+                /* Note: This is a combined loop that dumps both the traps */
+                /* (for the trace == 0 case) as well as the traces 1 to    */
+                /* 'traces'.                                               */
+                for (trace = 0; trace <= traces; trace++) {
+                        u32 diag_sel =
+                                GENWQE_EXTENDED_DIAG_SELECTOR(ring, trace);
+
+                        addr = (GENWQE_UID_OFFS(uid) |
+                                IO_EXTENDED_DIAG_SELECTOR);
+                        __genwqe_writeq(cd, addr, diag_sel);
+
+                        for (trace_entry = 0;
+                             trace_entry < (trace ? trace_entries : traps);
+                             trace_entry++) {
+                                addr = (GENWQE_UID_OFFS(uid) |
+                                        IO_EXTENDED_DIAG_READ_MBX);
+                                val = __genwqe_readq(cd, addr);
+                                set_reg_idx(cd, regs, &idx, max_regs, addr,
+                                            (diag_sel<<16) | trace_entry, val);
+                        }
+                }
+        }
+        return 0;
+}
+
+/**
+ * genwqe_write_vreg() - Write register in virtual window
+ *
+ * Note, these registers are only accessible to the PF through the
+ * VF-window. It is not intended for the VF to access.
+ */
+int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func)
+{
+        __genwqe_writeq(cd, IO_PF_SLC_VIRTUAL_WINDOW, func & 0xf);
+        __genwqe_writeq(cd, reg, val);
+        return 0;
+}
+
+/**
+ * genwqe_read_vreg() - Read register in virtual window
+ *
+ * Note, these registers are only accessible to the PF through the
+ * VF-window. It is not intended for the VF to access.
+ */
+u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func)
+{
+        __genwqe_writeq(cd, IO_PF_SLC_VIRTUAL_WINDOW, func & 0xf);
+        return __genwqe_readq(cd, reg);
+}
+
+/**
+ * genwqe_base_clock_frequency() - Deteremine base clock frequency of the card
+ *
+ * Note: From a design perspective it turned out to be a bad idea to
+ * use codes here to specifiy the frequency/speed values. An old
+ * driver cannot understand new codes and is therefore always a
+ * problem. Better is to measure out the value or put the
+ * speed/frequency directly into a register which is always a valid
+ * value for old as well as for new software.
+ *
+ * Return: Card clock in MHz
+ */
+int genwqe_base_clock_frequency(struct genwqe_dev *cd)
+{
+        u16 speed;              /*         MHz  MHz  MHz  MHz */
+        static const int speed_grade[] = { 250, 200, 166, 175 };
+
+        speed = (u16)((cd->slu_unitcfg >> 28) & 0x0full);
+        if (speed >= ARRAY_SIZE(speed_grade))
+                return 0;       /* illegal value */
+
+        return speed_grade[speed];
+}
+
+/**
+ * genwqe_stop_traps() - Stop traps
+ *
+ * Before reading out the analysis data, we need to stop the traps.
+ */
+void genwqe_stop_traps(struct genwqe_dev *cd)
+{
+        __genwqe_writeq(cd, IO_SLC_MISC_DEBUG_SET, 0xcull);
+}
+
+/**
+ * genwqe_start_traps() - Start traps
+ *
+ * After having read the data, we can/must enable the traps again.
+ */
+void genwqe_start_traps(struct genwqe_dev *cd)
+{
+        __genwqe_writeq(cd, IO_SLC_MISC_DEBUG_CLR, 0xcull);
+
+        if (genwqe_need_err_masking(cd))
+                __genwqe_writeq(cd, IO_SLC_MISC_DEBUG, 0x0aull);
+}
diff --git a/drivers/misc/genwqe/genwqe_driver.h b/drivers/misc/genwqe/genwqe_driver.h
new file mode 100644
index 000000000000..46e916b36c70
--- /dev/null
+++ b/drivers/misc/genwqe/genwqe_driver.h
@@ -0,0 +1,77 @@
+#ifndef __GENWQE_DRIVER_H__
+#define __GENWQE_DRIVER_H__
+
+/**
+ * IBM Accelerator Family 'GenWQE'
+ *
+ * (C) Copyright IBM Corp. 2013
+ *
+ * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
+ * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
+ * Author: Michael Jung <mijung@de.ibm.com>
+ * Author: Michael Ruettger <michael@ibmra.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/stddef.h>
+#include <linux/cdev.h>
+#include <linux/list.h>
+#include <linux/kthread.h>
+#include <linux/scatterlist.h>
+#include <linux/iommu.h>
+#include <linux/spinlock.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/printk.h>
+
+#include <asm/byteorder.h>
+#include <linux/genwqe/genwqe_card.h>
+
+#define DRV_VERS_STRING         "2.0.0"
+
+/*
+ * Static minor number assignement, until we decide/implement
+ * something dynamic.
+ */
+#define GENWQE_MAX_MINOR        128 /* up to 128 possible genwqe devices */
+
+/**
+ * genwqe_requ_alloc() - Allocate a new DDCB execution request
+ *
+ * This data structure contains the user visiable fields of the DDCB
+ * to be executed.
+ *
+ * Return: ptr to genwqe_ddcb_cmd data structure
+ */
+struct genwqe_ddcb_cmd *ddcb_requ_alloc(void);
+
+/**
+ * ddcb_requ_free() - Free DDCB execution request.
+ * @req:       ptr to genwqe_ddcb_cmd data structure.
+ */
+void ddcb_requ_free(struct genwqe_ddcb_cmd *req);
+
+u32  genwqe_crc32(u8 *buff, size_t len, u32 init);
+
+static inline void genwqe_hexdump(struct pci_dev *pci_dev,
+                                  const void *buff, unsigned int size)
+{
+        char prefix[32];
+
+        scnprintf(prefix, sizeof(prefix), "%s %s: ",
+                  GENWQE_DEVNAME, pci_name(pci_dev));
+
+        print_hex_dump_debug(prefix, DUMP_PREFIX_OFFSET, 16, 1, buff,
+                             size, true);
+}
+
+#endif  /* __GENWQE_DRIVER_H__ */
diff --git a/drivers/misc/lkdtm.c b/drivers/misc/lkdtm.c
index a2edb2ee0921..49c7a23f02fc 100644
--- a/drivers/misc/lkdtm.c
+++ b/drivers/misc/lkdtm.c
@@ -224,7 +224,7 @@ static int jp_scsi_dispatch_cmd(struct scsi_cmnd *cmd)
 }
 
 #ifdef CONFIG_IDE
-int jp_generic_ide_ioctl(ide_drive_t *drive, struct file *file,
+static int jp_generic_ide_ioctl(ide_drive_t *drive, struct file *file,
                         struct block_device *bdev, unsigned int cmd,
                         unsigned long arg)
 {
@@ -334,9 +334,10 @@ static void execute_location(void *dst)
 
 static void execute_user_location(void *dst)
 {
+        /* Intentionally crossing kernel/user memory boundary. */
         void (*func)(void) = dst;
 
-        if (copy_to_user(dst, do_nothing, EXEC_SIZE))
+        if (copy_to_user((void __user *)dst, do_nothing, EXEC_SIZE))
                 return;
         func();
 }
@@ -408,6 +409,8 @@ static void lkdtm_do_action(enum ctype which)
         case CT_SPINLOCKUP:
                 /* Must be called twice to trigger. */
                 spin_lock(&lock_me_up);
+                /* Let sparse know we intended to exit holding the lock. */
+                __release(&lock_me_up);
                 break;
         case CT_HUNG_TASK:
                 set_current_state(TASK_UNINTERRUPTIBLE);
diff --git a/drivers/misc/mei/amthif.c b/drivers/misc/mei/amthif.c
index d22c6864508b..2fad84432829 100644
--- a/drivers/misc/mei/amthif.c
+++ b/drivers/misc/mei/amthif.c
@@ -177,7 +177,7 @@ int mei_amthif_read(struct mei_device *dev, struct file *file,
         unsigned long timeout;
         int i;
 
-        /* Only Posible if we are in timeout */
+        /* Only possible if we are in timeout */
         if (!cl || cl != &dev->iamthif_cl) {
                 dev_dbg(&dev->pdev->dev, "bad file ext.\n");
                 return -ETIMEDOUT;
@@ -249,7 +249,7 @@ int mei_amthif_read(struct mei_device *dev, struct file *file,
             cb->response_buffer.size);
         dev_dbg(&dev->pdev->dev, "amthif cb->buf_idx - %lu\n", cb->buf_idx);
 
-        /* length is being turncated to PAGE_SIZE, however,
+        /* length is being truncated to PAGE_SIZE, however,
          * the buf_idx may point beyond */
         length = min_t(size_t, length, (cb->buf_idx - *offset));
 
@@ -316,6 +316,7 @@ static int mei_amthif_send_cmd(struct mei_device *dev, struct mei_cl_cb *cb)
                 mei_hdr.host_addr = dev->iamthif_cl.host_client_id;
                 mei_hdr.me_addr = dev->iamthif_cl.me_client_id;
                 mei_hdr.reserved = 0;
+                mei_hdr.internal = 0;
                 dev->iamthif_msg_buf_index += mei_hdr.length;
                 ret = mei_write_message(dev, &mei_hdr, dev->iamthif_msg_buf);
                 if (ret)
@@ -477,6 +478,7 @@ int mei_amthif_irq_write_complete(struct mei_cl *cl, struct mei_cl_cb *cb,
         mei_hdr.host_addr = cl->host_client_id;
         mei_hdr.me_addr = cl->me_client_id;
         mei_hdr.reserved = 0;
+        mei_hdr.internal = 0;
 
         if (*slots >= msg_slots) {
                 mei_hdr.length = len;
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index 87c96e4669e2..1ee2b9492a82 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -154,7 +154,7 @@ int mei_io_cb_alloc_req_buf(struct mei_cl_cb *cb, size_t length)
         return 0;
 }
 /**
- * mei_io_cb_alloc_resp_buf - allocate respose buffer
+ * mei_io_cb_alloc_resp_buf - allocate response buffer
  *
  * @cb: io callback structure
  * @length: size of the buffer
@@ -207,7 +207,7 @@ int mei_cl_flush_queues(struct mei_cl *cl)
 
 
 /**
- * mei_cl_init - initializes intialize cl.
+ * mei_cl_init - initializes cl.
  *
  * @cl: host client to be initialized
  * @dev: mei device
@@ -263,10 +263,10 @@ struct mei_cl_cb *mei_cl_find_read_cb(struct mei_cl *cl)
         return NULL;
 }
 
-/** mei_cl_link: allocte host id in the host map
+/** mei_cl_link: allocate host id in the host map
  *
  * @cl - host client
- * @id - fixed host id or -1 for genereting one
+ * @id - fixed host id or -1 for generic one
  *
  * returns 0 on success
  *      -EINVAL on incorrect values
@@ -282,19 +282,19 @@ int mei_cl_link(struct mei_cl *cl, int id)
 
         dev = cl->dev;
 
-        /* If Id is not asigned get one*/
+        /* If Id is not assigned get one*/
         if (id == MEI_HOST_CLIENT_ID_ANY)
                 id = find_first_zero_bit(dev->host_clients_map,
                                         MEI_CLIENTS_MAX);
 
         if (id >= MEI_CLIENTS_MAX) {
-                dev_err(&dev->pdev->dev, "id exceded %d", MEI_CLIENTS_MAX) ;
+                dev_err(&dev->pdev->dev, "id exceeded %d", MEI_CLIENTS_MAX);
                 return -EMFILE;
         }
 
         open_handle_count = dev->open_handle_count + dev->iamthif_open_count;
         if (open_handle_count >= MEI_MAX_OPEN_HANDLE_COUNT) {
-                dev_err(&dev->pdev->dev, "open_handle_count exceded %d",
+                dev_err(&dev->pdev->dev, "open_handle_count exceeded %d",
                         MEI_MAX_OPEN_HANDLE_COUNT);
                 return -EMFILE;
         }
@@ -344,8 +344,6 @@ int mei_cl_unlink(struct mei_cl *cl)
 
         cl->state = MEI_FILE_INITIALIZING;
 
-        list_del_init(&cl->link);
-
         return 0;
 }
 
@@ -372,13 +370,14 @@ void mei_host_client_init(struct work_struct *work)
         }
 
         dev->dev_state = MEI_DEV_ENABLED;
+        dev->reset_count = 0;
 
         mutex_unlock(&dev->device_lock);
 }
 
 
 /**
- * mei_cl_disconnect - disconnect host clinet form the me one
+ * mei_cl_disconnect - disconnect host client from the me one
  *
  * @cl: host client
  *
@@ -457,7 +456,7 @@ free:
  *
  * @cl: private data of the file object
  *
- * returns ture if other client is connected, 0 - otherwise.
+ * returns true if other client is connected, false - otherwise.
  */
 bool mei_cl_is_other_connecting(struct mei_cl *cl)
 {
@@ -481,7 +480,7 @@ bool mei_cl_is_other_connecting(struct mei_cl *cl)
 }
 
 /**
- * mei_cl_connect - connect host clinet to the me one
+ * mei_cl_connect - connect host client to the me one
  *
  * @cl: host client
  *
@@ -729,6 +728,7 @@ int mei_cl_irq_write_complete(struct mei_cl *cl, struct mei_cl_cb *cb,
         mei_hdr.host_addr = cl->host_client_id;
         mei_hdr.me_addr = cl->me_client_id;
         mei_hdr.reserved = 0;
+        mei_hdr.internal = cb->internal;
 
         if (*slots >= msg_slots) {
                 mei_hdr.length = len;
@@ -775,7 +775,7 @@ int mei_cl_irq_write_complete(struct mei_cl *cl, struct mei_cl_cb *cb,
  * @cl: host client
  * @cl: write callback with filled data
  *
- * returns numbe of bytes sent on success, <0 on failure.
+ * returns number of bytes sent on success, <0 on failure.
  */
 int mei_cl_write(struct mei_cl *cl, struct mei_cl_cb *cb, bool blocking)
 {
@@ -828,6 +828,7 @@ int mei_cl_write(struct mei_cl *cl, struct mei_cl_cb *cb, bool blocking)
         mei_hdr.host_addr = cl->host_client_id;
         mei_hdr.me_addr = cl->me_client_id;
         mei_hdr.reserved = 0;
+        mei_hdr.internal = cb->internal;
 
 
         rets = mei_write_message(dev, &mei_hdr, buf->data);
diff --git a/drivers/misc/mei/debugfs.c b/drivers/misc/mei/debugfs.c
index e3870f22d238..a3ae154444b2 100644
--- a/drivers/misc/mei/debugfs.c
+++ b/drivers/misc/mei/debugfs.c
@@ -43,7 +43,7 @@ static ssize_t mei_dbgfs_read_meclients(struct file *fp, char __user *ubuf,
 
         mutex_lock(&dev->device_lock);
 
-        /*  if the driver is not enabled the list won't b consitent */
+        /*  if the driver is not enabled the list won't be consistent */
         if (dev->dev_state != MEI_DEV_ENABLED)
                 goto out;
 
@@ -101,7 +101,7 @@ static const struct file_operations mei_dbgfs_fops_devstate = {
 
 /**
  * mei_dbgfs_deregister - Remove the debugfs files and directories
- * @mei - pointer to mei device private dat
+ * @mei - pointer to mei device private data
  */
 void mei_dbgfs_deregister(struct mei_device *dev)
 {
diff --git a/drivers/misc/mei/hbm.c b/drivers/misc/mei/hbm.c
index 9b3a0fb7f265..28cd74c073b9 100644
--- a/drivers/misc/mei/hbm.c
+++ b/drivers/misc/mei/hbm.c
@@ -28,9 +28,9 @@
  *
  * @dev: the device structure
  *
- * returns none.
+ * returns 0 on success -ENOMEM on allocation failure
  */
-static void mei_hbm_me_cl_allocate(struct mei_device *dev)
+static int mei_hbm_me_cl_allocate(struct mei_device *dev)
 {
         struct mei_me_client *clients;
         int b;
@@ -44,7 +44,7 @@ static void mei_hbm_me_cl_allocate(struct mei_device *dev)
                 dev->me_clients_num++;
 
         if (dev->me_clients_num == 0)
-                return;
+                return 0;
 
         kfree(dev->me_clients);
         dev->me_clients = NULL;
@@ -56,12 +56,10 @@ static void mei_hbm_me_cl_allocate(struct mei_device *dev)
                         sizeof(struct mei_me_client), GFP_KERNEL);
         if (!clients) {
                 dev_err(&dev->pdev->dev, "memory allocation for ME clients failed.\n");
-                dev->dev_state = MEI_DEV_RESETTING;
-                mei_reset(dev, 1);
-                return;
+                return -ENOMEM;
         }
         dev->me_clients = clients;
-        return;
+        return 0;
 }
 
 /**
@@ -85,12 +83,12 @@ void mei_hbm_cl_hdr(struct mei_cl *cl, u8 hbm_cmd, void *buf, size_t len)
 }
 
 /**
- * same_disconn_addr - tells if they have the same address
+ * mei_hbm_cl_addr_equal - tells if they have the same address
  *
- * @file: private data of the file object.
- * @disconn: disconnection request.
+ * @cl: - client
+ * @buf: buffer with cl header
  *
- * returns true if addres are same
+ * returns true if addresses are the same
  */
 static inline
 bool mei_hbm_cl_addr_equal(struct mei_cl *cl, void *buf)
@@ -128,6 +126,17 @@ static bool is_treat_specially_client(struct mei_cl *cl,
         return false;
 }
 
+/**
+ * mei_hbm_idle - set hbm to idle state
+ *
+ * @dev: the device structure
+ */
+void mei_hbm_idle(struct mei_device *dev)
+{
+        dev->init_clients_timer = 0;
+        dev->hbm_state = MEI_HBM_IDLE;
+}
+
 int mei_hbm_start_wait(struct mei_device *dev)
 {
         int ret;
@@ -137,7 +146,7 @@ int mei_hbm_start_wait(struct mei_device *dev)
         mutex_unlock(&dev->device_lock);
         ret = wait_event_interruptible_timeout(dev->wait_recvd_msg,
                         dev->hbm_state == MEI_HBM_IDLE ||
-                        dev->hbm_state > MEI_HBM_START,
+                        dev->hbm_state >= MEI_HBM_STARTED,
                         mei_secs_to_jiffies(MEI_INTEROP_TIMEOUT));
         mutex_lock(&dev->device_lock);
 
@@ -153,12 +162,15 @@ int mei_hbm_start_wait(struct mei_device *dev)
  * mei_hbm_start_req - sends start request message.
  *
  * @dev: the device structure
+ *
+ * returns 0 on success and < 0 on failure
  */
 int mei_hbm_start_req(struct mei_device *dev)
 {
         struct mei_msg_hdr *mei_hdr = &dev->wr_msg.hdr;
         struct hbm_host_version_request *start_req;
         const size_t len = sizeof(struct hbm_host_version_request);
+        int ret;
 
         mei_hbm_hdr(mei_hdr, len);
 
@@ -170,12 +182,13 @@ int mei_hbm_start_req(struct mei_device *dev)
         start_req->host_version.minor_version = HBM_MINOR_VERSION;
 
         dev->hbm_state = MEI_HBM_IDLE;
-        if (mei_write_message(dev, mei_hdr, dev->wr_msg.data)) {
-                dev_err(&dev->pdev->dev, "version message write failed\n");
-                dev->dev_state = MEI_DEV_RESETTING;
-                mei_reset(dev, 1);
-                return -EIO;
+        ret = mei_write_message(dev, mei_hdr, dev->wr_msg.data);
+        if (ret) {
+                dev_err(&dev->pdev->dev, "version message write failed: ret = %d\n",
+                        ret);
+                return ret;
         }
+
         dev->hbm_state = MEI_HBM_START;
         dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
         return 0;
@@ -186,13 +199,15 @@ int mei_hbm_start_req(struct mei_device *dev)
  *
  * @dev: the device structure
  *
- * returns none.
+ * returns 0 on success and < 0 on failure
  */
-static void mei_hbm_enum_clients_req(struct mei_device *dev)
+static int mei_hbm_enum_clients_req(struct mei_device *dev)
 {
         struct mei_msg_hdr *mei_hdr = &dev->wr_msg.hdr;
         struct hbm_host_enum_request *enum_req;
         const size_t len = sizeof(struct hbm_host_enum_request);
+        int ret;
+
         /* enumerate clients */
         mei_hbm_hdr(mei_hdr, len);
 
@@ -200,14 +215,15 @@ static void mei_hbm_enum_clients_req(struct mei_device *dev)
         memset(enum_req, 0, len);
         enum_req->hbm_cmd = HOST_ENUM_REQ_CMD;
 
-        if (mei_write_message(dev, mei_hdr, dev->wr_msg.data)) {
-                dev->dev_state = MEI_DEV_RESETTING;
-                dev_err(&dev->pdev->dev, "enumeration request write failed.\n");
-                mei_reset(dev, 1);
+        ret = mei_write_message(dev, mei_hdr, dev->wr_msg.data);
+        if (ret) {
+                dev_err(&dev->pdev->dev, "enumeration request write failed: ret = %d.\n",
+                        ret);
+                return ret;
         }
         dev->hbm_state = MEI_HBM_ENUM_CLIENTS;
         dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
-        return;
+        return 0;
 }
 
 /**
@@ -215,7 +231,7 @@ static void mei_hbm_enum_clients_req(struct mei_device *dev)
  *
  * @dev: the device structure
  *
- * returns none.
+ * returns 0 on success and < 0 on failure
  */
 
 static int mei_hbm_prop_req(struct mei_device *dev)
@@ -226,7 +242,7 @@ static int mei_hbm_prop_req(struct mei_device *dev)
         const size_t len = sizeof(struct hbm_props_request);
         unsigned long next_client_index;
         unsigned long client_num;
-
+        int ret;
 
         client_num = dev->me_client_presentation_num;
 
@@ -253,12 +269,11 @@ static int mei_hbm_prop_req(struct mei_device *dev)
         prop_req->hbm_cmd = HOST_CLIENT_PROPERTIES_REQ_CMD;
         prop_req->address = next_client_index;
 
-        if (mei_write_message(dev, mei_hdr, dev->wr_msg.data)) {
-                dev->dev_state = MEI_DEV_RESETTING;
-                dev_err(&dev->pdev->dev, "properties request write failed\n");
-                mei_reset(dev, 1);
-
-                return -EIO;
+        ret = mei_write_message(dev, mei_hdr, dev->wr_msg.data);
+        if (ret) {
+                dev_err(&dev->pdev->dev, "properties request write failed: ret = %d\n",
+                        ret);
+                return ret;
         }
 
         dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
@@ -268,7 +283,7 @@ static int mei_hbm_prop_req(struct mei_device *dev)
 }
 
 /**
- * mei_hbm_stop_req_prepare - perpare stop request message
+ * mei_hbm_stop_req_prepare - prepare stop request message
  *
  * @dev - mei device
  * @mei_hdr - mei message header
@@ -289,7 +304,7 @@ static void mei_hbm_stop_req_prepare(struct mei_device *dev,
 }
 
 /**
- * mei_hbm_cl_flow_control_req - sends flow control requst.
+ * mei_hbm_cl_flow_control_req - sends flow control request.
  *
  * @dev: the device structure
  * @cl: client info
@@ -451,7 +466,7 @@ int mei_hbm_cl_connect_req(struct mei_device *dev, struct mei_cl *cl)
 }
 
 /**
- * mei_hbm_cl_connect_res - connect resposne from the ME
+ * mei_hbm_cl_connect_res - connect response from the ME
  *
  * @dev: the device structure
  * @rs: connect response bus message
@@ -505,8 +520,8 @@ static void mei_hbm_cl_connect_res(struct mei_device *dev,
 
 
 /**
- * mei_hbm_fw_disconnect_req - disconnect request initiated by me
- *  host sends disoconnect response
+ * mei_hbm_fw_disconnect_req - disconnect request initiated by ME firmware
+ *  host sends disconnect response
  *
  * @dev: the device structure.
  * @disconnect_req: disconnect request bus message from the me
@@ -559,8 +574,10 @@ bool mei_hbm_version_is_supported(struct mei_device *dev)
  *
  * @dev: the device structure
  * @mei_hdr: header of bus message
+ *
+ * returns 0 on success and < 0 on failure
  */
-void mei_hbm_dispatch(struct mei_device *dev, struct mei_msg_hdr *hdr)
+int mei_hbm_dispatch(struct mei_device *dev, struct mei_msg_hdr *hdr)
 {
         struct mei_bus_message *mei_msg;
         struct mei_me_client *me_client;
@@ -577,8 +594,20 @@ void mei_hbm_dispatch(struct mei_device *dev, struct mei_msg_hdr *hdr)
         mei_read_slots(dev, dev->rd_msg_buf, hdr->length);
         mei_msg = (struct mei_bus_message *)dev->rd_msg_buf;
 
+        /* ignore spurious message and prevent reset nesting
+         * hbm is put to idle during system reset
+         */
+        if (dev->hbm_state == MEI_HBM_IDLE) {
+                dev_dbg(&dev->pdev->dev, "hbm: state is idle ignore spurious messages\n");
+                return 0;
+        }
+
         switch (mei_msg->hbm_cmd) {
         case HOST_START_RES_CMD:
+                dev_dbg(&dev->pdev->dev, "hbm: start: response message received.\n");
+
+                dev->init_clients_timer = 0;
+
                 version_res = (struct hbm_host_version_response *)mei_msg;
 
                 dev_dbg(&dev->pdev->dev, "HBM VERSION: DRIVER=%02d:%02d DEVICE=%02d:%02d\n",
@@ -597,73 +626,89 @@ void mei_hbm_dispatch(struct mei_device *dev, struct mei_msg_hdr *hdr)
                 }
 
                 if (!mei_hbm_version_is_supported(dev)) {
-                        dev_warn(&dev->pdev->dev, "hbm version mismatch: stopping the driver.\n");
+                        dev_warn(&dev->pdev->dev, "hbm: start: version mismatch - stopping the driver.\n");
 
-                        dev->hbm_state = MEI_HBM_STOP;
+                        dev->hbm_state = MEI_HBM_STOPPED;
                         mei_hbm_stop_req_prepare(dev, &dev->wr_msg.hdr,
                                                 dev->wr_msg.data);
-                        mei_write_message(dev, &dev->wr_msg.hdr,
-                                        dev->wr_msg.data);
+                        if (mei_write_message(dev, &dev->wr_msg.hdr,
+                                        dev->wr_msg.data)) {
+                                dev_err(&dev->pdev->dev, "hbm: start: failed to send stop request\n");
+                                return -EIO;
+                        }
+                        break;
+                }
 
-                        return;
+                if (dev->dev_state != MEI_DEV_INIT_CLIENTS ||
+                    dev->hbm_state != MEI_HBM_START) {
+                        dev_err(&dev->pdev->dev, "hbm: start: state mismatch, [%d, %d]\n",
+                                dev->dev_state, dev->hbm_state);
+                        return -EPROTO;
                 }
 
-                if (dev->dev_state == MEI_DEV_INIT_CLIENTS &&
-                    dev->hbm_state == MEI_HBM_START) {
-                        dev->init_clients_timer = 0;
-                        mei_hbm_enum_clients_req(dev);
-                } else {
-                        dev_err(&dev->pdev->dev, "reset: wrong host start response\n");
-                        mei_reset(dev, 1);
-                        return;
+                dev->hbm_state = MEI_HBM_STARTED;
+
+                if (mei_hbm_enum_clients_req(dev)) {
+                        dev_err(&dev->pdev->dev, "hbm: start: failed to send enumeration request\n");
+                        return -EIO;
                 }
 
                 wake_up_interruptible(&dev->wait_recvd_msg);
-                dev_dbg(&dev->pdev->dev, "host start response message received.\n");
                 break;
 
         case CLIENT_CONNECT_RES_CMD:
+                dev_dbg(&dev->pdev->dev, "hbm: client connect response: message received.\n");
+
                 connect_res = (struct hbm_client_connect_response *) mei_msg;
                 mei_hbm_cl_connect_res(dev, connect_res);
-                dev_dbg(&dev->pdev->dev, "client connect response message received.\n");
                 wake_up(&dev->wait_recvd_msg);
                 break;
 
         case CLIENT_DISCONNECT_RES_CMD:
+                dev_dbg(&dev->pdev->dev, "hbm: client disconnect response: message received.\n");
+
                 disconnect_res = (struct hbm_client_connect_response *) mei_msg;
                 mei_hbm_cl_disconnect_res(dev, disconnect_res);
-                dev_dbg(&dev->pdev->dev, "client disconnect response message received.\n");
                 wake_up(&dev->wait_recvd_msg);
                 break;
 
         case MEI_FLOW_CONTROL_CMD:
+                dev_dbg(&dev->pdev->dev, "hbm: client flow control response: message received.\n");
+
                 flow_control = (struct hbm_flow_control *) mei_msg;
                 mei_hbm_cl_flow_control_res(dev, flow_control);
-                dev_dbg(&dev->pdev->dev, "client flow control response message received.\n");
                 break;
 
         case HOST_CLIENT_PROPERTIES_RES_CMD:
+                dev_dbg(&dev->pdev->dev, "hbm: properties response: message received.\n");
+
+                dev->init_clients_timer = 0;
+
+                if (dev->me_clients == NULL) {
+                        dev_err(&dev->pdev->dev, "hbm: properties response: mei_clients not allocated\n");
+                        return -EPROTO;
+                }
+
                 props_res = (struct hbm_props_response *)mei_msg;
                 me_client = &dev->me_clients[dev->me_client_presentation_num];
 
-                if (props_res->status || !dev->me_clients) {
-                        dev_err(&dev->pdev->dev, "reset: properties response hbm wrong status.\n");
-                        mei_reset(dev, 1);
-                        return;
+                if (props_res->status) {
+                        dev_err(&dev->pdev->dev, "hbm: properties response: wrong status = %d\n",
+                                props_res->status);
+                        return -EPROTO;
                 }
 
                 if (me_client->client_id != props_res->address) {
-                        dev_err(&dev->pdev->dev, "reset: host properties response address mismatch\n");
-                        mei_reset(dev, 1);
-                        return;
+                        dev_err(&dev->pdev->dev, "hbm: properties response: address mismatch %d ?= %d\n",
+                                me_client->client_id, props_res->address);
+                        return -EPROTO;
                 }
 
                 if (dev->dev_state != MEI_DEV_INIT_CLIENTS ||
                     dev->hbm_state != MEI_HBM_CLIENT_PROPERTIES) {
-                        dev_err(&dev->pdev->dev, "reset: unexpected properties response\n");
-                        mei_reset(dev, 1);
-
-                        return;
+                        dev_err(&dev->pdev->dev, "hbm: properties response: state mismatch, [%d, %d]\n",
+                                dev->dev_state, dev->hbm_state);
+                        return -EPROTO;
                 }
 
                 me_client->props = props_res->client_properties;
@@ -671,49 +716,70 @@ void mei_hbm_dispatch(struct mei_device *dev, struct mei_msg_hdr *hdr)
                 dev->me_client_presentation_num++;
 
                 /* request property for the next client */
-                mei_hbm_prop_req(dev);
+                if (mei_hbm_prop_req(dev))
+                        return -EIO;
 
                 break;
 
         case HOST_ENUM_RES_CMD:
+                dev_dbg(&dev->pdev->dev, "hbm: enumeration response: message received\n");
+
+                dev->init_clients_timer = 0;
+
                 enum_res = (struct hbm_host_enum_response *) mei_msg;
                 BUILD_BUG_ON(sizeof(dev->me_clients_map)
                                 < sizeof(enum_res->valid_addresses));
                 memcpy(dev->me_clients_map, enum_res->valid_addresses,
                         sizeof(enum_res->valid_addresses));
-                if (dev->dev_state == MEI_DEV_INIT_CLIENTS &&
-                    dev->hbm_state == MEI_HBM_ENUM_CLIENTS) {
-                                dev->init_clients_timer = 0;
-                                mei_hbm_me_cl_allocate(dev);
-                                dev->hbm_state = MEI_HBM_CLIENT_PROPERTIES;
-
-                                /* first property reqeust */
-                                mei_hbm_prop_req(dev);
-                } else {
-                        dev_err(&dev->pdev->dev, "reset: unexpected enumeration response hbm.\n");
-                        mei_reset(dev, 1);
-                        return;
+
+                if (dev->dev_state != MEI_DEV_INIT_CLIENTS ||
+                    dev->hbm_state != MEI_HBM_ENUM_CLIENTS) {
+                        dev_err(&dev->pdev->dev, "hbm: enumeration response: state mismatch, [%d, %d]\n",
+                                dev->dev_state, dev->hbm_state);
+                        return -EPROTO;
+                }
+
+                if (mei_hbm_me_cl_allocate(dev)) {
+                        dev_err(&dev->pdev->dev, "hbm: enumeration response: cannot allocate clients array\n");
+                        return -ENOMEM;
                 }
+
+                dev->hbm_state = MEI_HBM_CLIENT_PROPERTIES;
+
+                /* first property request */
+                if (mei_hbm_prop_req(dev))
+                        return -EIO;
+
                 break;
 
         case HOST_STOP_RES_CMD:
+                dev_dbg(&dev->pdev->dev, "hbm: stop response: message received\n");
+
+                dev->init_clients_timer = 0;
 
-                if (dev->hbm_state != MEI_HBM_STOP)
-                        dev_err(&dev->pdev->dev, "unexpected stop response hbm.\n");
-                dev->dev_state = MEI_DEV_DISABLED;
-                dev_info(&dev->pdev->dev, "reset: FW stop response.\n");
-                mei_reset(dev, 1);
+                if (dev->hbm_state != MEI_HBM_STOPPED) {
+                        dev_err(&dev->pdev->dev, "hbm: stop response: state mismatch, [%d, %d]\n",
+                                dev->dev_state, dev->hbm_state);
+                        return -EPROTO;
+                }
+
+                dev->dev_state = MEI_DEV_POWER_DOWN;
+                dev_info(&dev->pdev->dev, "hbm: stop response: resetting.\n");
+                /* force the reset */
+                return -EPROTO;
                 break;
 
         case CLIENT_DISCONNECT_REQ_CMD:
-                /* search for client */
+                dev_dbg(&dev->pdev->dev, "hbm: disconnect request: message received\n");
+
                 disconnect_req = (struct hbm_client_connect_request *)mei_msg;
                 mei_hbm_fw_disconnect_req(dev, disconnect_req);
                 break;
 
         case ME_STOP_REQ_CMD:
+                dev_dbg(&dev->pdev->dev, "hbm: stop request: message received\n");
 
-                dev->hbm_state = MEI_HBM_STOP;
+                dev->hbm_state = MEI_HBM_STOPPED;
                 mei_hbm_stop_req_prepare(dev, &dev->wr_ext_msg.hdr,
                                         dev->wr_ext_msg.data);
                 break;
@@ -722,5 +788,6 @@ void mei_hbm_dispatch(struct mei_device *dev, struct mei_msg_hdr *hdr)
                 break;
 
         }
+        return 0;
 }
 
diff --git a/drivers/misc/mei/hbm.h b/drivers/misc/mei/hbm.h
index 4ae2e56e404f..5f92188a5cd7 100644
--- a/drivers/misc/mei/hbm.h
+++ b/drivers/misc/mei/hbm.h
@@ -32,13 +32,13 @@ struct mei_cl;
 enum mei_hbm_state {
         MEI_HBM_IDLE = 0,
         MEI_HBM_START,
+        MEI_HBM_STARTED,
         MEI_HBM_ENUM_CLIENTS,
         MEI_HBM_CLIENT_PROPERTIES,
-        MEI_HBM_STARTED,
-        MEI_HBM_STOP,
+        MEI_HBM_STOPPED,
 };
 
-void mei_hbm_dispatch(struct mei_device *dev, struct mei_msg_hdr *hdr);
+int mei_hbm_dispatch(struct mei_device *dev, struct mei_msg_hdr *hdr);
 
 static inline void mei_hbm_hdr(struct mei_msg_hdr *hdr, size_t length)
 {
@@ -49,6 +49,7 @@ static inline void mei_hbm_hdr(struct mei_msg_hdr *hdr, size_t length)
         hdr->reserved = 0;
 }
 
+void mei_hbm_idle(struct mei_device *dev);
 int mei_hbm_start_req(struct mei_device *dev);
 int mei_hbm_start_wait(struct mei_device *dev);
 int mei_hbm_cl_flow_control_req(struct mei_device *dev, struct mei_cl *cl);
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 3412adcdaeb0..6f656c053b14 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -185,7 +185,7 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
 
         mei_me_reg_write(hw, H_CSR, hcsr);
 
-        if (dev->dev_state == MEI_DEV_POWER_DOWN)
+        if (intr_enable == false)
                 mei_me_hw_reset_release(dev);
 
         return 0;
@@ -469,7 +469,7 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
         struct mei_device *dev = (struct mei_device *) dev_id;
         struct mei_cl_cb complete_list;
         s32 slots;
-        int rets;
+        int rets = 0;
 
         dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
         /* initialize our complete list */
@@ -482,15 +482,10 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
                 mei_clear_interrupts(dev);
 
         /* check if ME wants a reset */
-        if (!mei_hw_is_ready(dev) &&
-            dev->dev_state != MEI_DEV_RESETTING &&
-            dev->dev_state != MEI_DEV_INITIALIZING &&
-            dev->dev_state != MEI_DEV_POWER_DOWN &&
-            dev->dev_state != MEI_DEV_POWER_UP) {
-                dev_dbg(&dev->pdev->dev, "FW not ready.\n");
-                mei_reset(dev, 1);
-                mutex_unlock(&dev->device_lock);
-                return IRQ_HANDLED;
+        if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
+                dev_warn(&dev->pdev->dev, "FW not ready: resetting.\n");
+                schedule_work(&dev->reset_work);
+                goto end;
         }
 
         /*  check if we need to start the dev */
@@ -500,15 +495,12 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
 
                         dev->recvd_hw_ready = true;
                         wake_up_interruptible(&dev->wait_hw_ready);
-
-                        mutex_unlock(&dev->device_lock);
-                        return IRQ_HANDLED;
                 } else {
+
                         dev_dbg(&dev->pdev->dev, "Reset Completed.\n");
                         mei_me_hw_reset_release(dev);
-                        mutex_unlock(&dev->device_lock);
-                        return IRQ_HANDLED;
                 }
+                goto end;
         }
         /* check slots available for reading */
         slots = mei_count_full_read_slots(dev);
@@ -516,21 +508,23 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
                 /* we have urgent data to send so break the read */
                 if (dev->wr_ext_msg.hdr.length)
                         break;
-                dev_dbg(&dev->pdev->dev, "slots =%08x\n", slots);
-                dev_dbg(&dev->pdev->dev, "call mei_irq_read_handler.\n");
+                dev_dbg(&dev->pdev->dev, "slots to read = %08x\n", slots);
                 rets = mei_irq_read_handler(dev, &complete_list, &slots);
-                if (rets)
+                if (rets && dev->dev_state != MEI_DEV_RESETTING) {
+                        schedule_work(&dev->reset_work);
                         goto end;
+                }
         }
+
         rets = mei_irq_write_handler(dev, &complete_list);
-end:
-        dev_dbg(&dev->pdev->dev, "end of bottom half function.\n");
-        dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
 
-        mutex_unlock(&dev->device_lock);
+        dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
 
         mei_irq_compl_handler(dev, &complete_list);
 
+end:
+        dev_dbg(&dev->pdev->dev, "interrupt thread end ret = %d\n", rets);
+        mutex_unlock(&dev->device_lock);
         return IRQ_HANDLED;
 }
 static const struct mei_hw_ops mei_me_hw_ops = {
diff --git a/drivers/misc/mei/hw.h b/drivers/misc/mei/hw.h
index cb2f556b4252..dd44e33ad2b6 100644
--- a/drivers/misc/mei/hw.h
+++ b/drivers/misc/mei/hw.h
@@ -111,7 +111,8 @@ struct mei_msg_hdr {
         u32 me_addr:8;
         u32 host_addr:8;
         u32 length:9;
-        u32 reserved:6;
+        u32 reserved:5;
+        u32 internal:1;
         u32 msg_complete:1;
 } __packed;
 
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index f7f3abbe12b6..cdd31c2a2a2b 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -43,41 +43,119 @@ const char *mei_dev_state_str(int state)
 #undef MEI_DEV_STATE
 }
 
-void mei_device_init(struct mei_device *dev)
-{
-        /* setup our list array */
-        INIT_LIST_HEAD(&dev->file_list);
-        INIT_LIST_HEAD(&dev->device_list);
-        mutex_init(&dev->device_lock);
-        init_waitqueue_head(&dev->wait_hw_ready);
-        init_waitqueue_head(&dev->wait_recvd_msg);
-        init_waitqueue_head(&dev->wait_stop_wd);
-        dev->dev_state = MEI_DEV_INITIALIZING;
 
-        mei_io_list_init(&dev->read_list);
-        mei_io_list_init(&dev->write_list);
-        mei_io_list_init(&dev->write_waiting_list);
-        mei_io_list_init(&dev->ctrl_wr_list);
-        mei_io_list_init(&dev->ctrl_rd_list);
+/**
+ * mei_cancel_work. Cancel mei background jobs
+ *
+ * @dev: the device structure
+ *
+ * returns 0 on success or < 0 if the reset hasn't succeeded
+ */
+void mei_cancel_work(struct mei_device *dev)
+{
+        cancel_work_sync(&dev->init_work);
+        cancel_work_sync(&dev->reset_work);
 
-        INIT_DELAYED_WORK(&dev->timer_work, mei_timer);
-        INIT_WORK(&dev->init_work, mei_host_client_init);
+        cancel_delayed_work(&dev->timer_work);
+}
+EXPORT_SYMBOL_GPL(mei_cancel_work);
 
-        INIT_LIST_HEAD(&dev->wd_cl.link);
-        INIT_LIST_HEAD(&dev->iamthif_cl.link);
-        mei_io_list_init(&dev->amthif_cmd_list);
-        mei_io_list_init(&dev->amthif_rd_complete_list);
+/**
+ * mei_reset - resets host and fw.
+ *
+ * @dev: the device structure
+ */
+int mei_reset(struct mei_device *dev)
+{
+        enum mei_dev_state state = dev->dev_state;
+        bool interrupts_enabled;
+        int ret;
 
-        bitmap_zero(dev->host_clients_map, MEI_CLIENTS_MAX);
-        dev->open_handle_count = 0;
+        if (state != MEI_DEV_INITIALIZING &&
+            state != MEI_DEV_DISABLED &&
+            state != MEI_DEV_POWER_DOWN &&
+            state != MEI_DEV_POWER_UP)
+                dev_warn(&dev->pdev->dev, "unexpected reset: dev_state = %s\n",
+                         mei_dev_state_str(state));
 
-        /*
-         * Reserving the first client ID
-         * 0: Reserved for MEI Bus Message communications
+        /* we're already in reset, cancel the init timer
+         * if the reset was called due the hbm protocol error
+         * we need to call it before hw start
+         * so the hbm watchdog won't kick in
          */
-        bitmap_set(dev->host_clients_map, 0, 1);
+        mei_hbm_idle(dev);
+
+        /* enter reset flow */
+        interrupts_enabled = state != MEI_DEV_POWER_DOWN;
+        dev->dev_state = MEI_DEV_RESETTING;
+
+        dev->reset_count++;
+        if (dev->reset_count > MEI_MAX_CONSEC_RESET) {
+                dev_err(&dev->pdev->dev, "reset: reached maximal consecutive resets: disabling the device\n");
+                dev->dev_state = MEI_DEV_DISABLED;
+                return -ENODEV;
+        }
+
+        ret = mei_hw_reset(dev, interrupts_enabled);
+        /* fall through and remove the sw state even if hw reset has failed */
+
+        /* no need to clean up software state in case of power up */
+        if (state != MEI_DEV_INITIALIZING &&
+            state != MEI_DEV_POWER_UP) {
+
+                /* remove all waiting requests */
+                mei_cl_all_write_clear(dev);
+
+                mei_cl_all_disconnect(dev);
+
+                /* wake up all readers and writers so they can be interrupted */
+                mei_cl_all_wakeup(dev);
+
+                /* remove entry if already in list */
+                dev_dbg(&dev->pdev->dev, "remove iamthif and wd from the file list.\n");
+                mei_cl_unlink(&dev->wd_cl);
+                mei_cl_unlink(&dev->iamthif_cl);
+                mei_amthif_reset_params(dev);
+                memset(&dev->wr_ext_msg, 0, sizeof(dev->wr_ext_msg));
+        }
+
+
+        dev->me_clients_num = 0;
+        dev->rd_msg_hdr = 0;
+        dev->wd_pending = false;
+
+        if (ret) {
+                dev_err(&dev->pdev->dev, "hw_reset failed ret = %d\n", ret);
+                dev->dev_state = MEI_DEV_DISABLED;
+                return ret;
+        }
+
+        if (state == MEI_DEV_POWER_DOWN) {
+                dev_dbg(&dev->pdev->dev, "powering down: end of reset\n");
+                dev->dev_state = MEI_DEV_DISABLED;
+                return 0;
+        }
+
+        ret = mei_hw_start(dev);
+        if (ret) {
+                dev_err(&dev->pdev->dev, "hw_start failed ret = %d\n", ret);
+                dev->dev_state = MEI_DEV_DISABLED;
+                return ret;
+        }
+
+        dev_dbg(&dev->pdev->dev, "link is established start sending messages.\n");
+
+        dev->dev_state = MEI_DEV_INIT_CLIENTS;
+        ret = mei_hbm_start_req(dev);
+        if (ret) {
+                dev_err(&dev->pdev->dev, "hbm_start failed ret = %d\n", ret);
+                dev->dev_state = MEI_DEV_DISABLED;
+                return ret;
+        }
+
+        return 0;
 }
-EXPORT_SYMBOL_GPL(mei_device_init);
+EXPORT_SYMBOL_GPL(mei_reset);
 
 /**
  * mei_start - initializes host and fw to start work.
@@ -90,14 +168,21 @@ int mei_start(struct mei_device *dev)
 {
         mutex_lock(&dev->device_lock);
 
-        /* acknowledge interrupt and stop interupts */
+        /* acknowledge interrupt and stop interrupts */
         mei_clear_interrupts(dev);
 
         mei_hw_config(dev);
 
         dev_dbg(&dev->pdev->dev, "reset in start the mei device.\n");
 
-        mei_reset(dev, 1);
+        dev->dev_state = MEI_DEV_INITIALIZING;
+        dev->reset_count = 0;
+        mei_reset(dev);
+
+        if (dev->dev_state == MEI_DEV_DISABLED) {
+                dev_err(&dev->pdev->dev, "reset failed");
+                goto err;
+        }
 
         if (mei_hbm_start_wait(dev)) {
                 dev_err(&dev->pdev->dev, "HBM haven't started");
@@ -132,101 +217,64 @@ err:
 EXPORT_SYMBOL_GPL(mei_start);
 
 /**
- * mei_reset - resets host and fw.
+ * mei_restart - restart device after suspend
  *
  * @dev: the device structure
- * @interrupts_enabled: if interrupt should be enabled after reset.
+ *
+ * returns 0 on success or -ENODEV if the restart hasn't succeeded
  */
-void mei_reset(struct mei_device *dev, int interrupts_enabled)
+int mei_restart(struct mei_device *dev)
 {
-        bool unexpected;
-        int ret;
-
-        unexpected = (dev->dev_state != MEI_DEV_INITIALIZING &&
-                        dev->dev_state != MEI_DEV_DISABLED &&
-                        dev->dev_state != MEI_DEV_POWER_DOWN &&
-                        dev->dev_state != MEI_DEV_POWER_UP);
+        int err;
 
-        if (unexpected)
-                dev_warn(&dev->pdev->dev, "unexpected reset: dev_state = %s\n",
-                         mei_dev_state_str(dev->dev_state));
-
-        ret = mei_hw_reset(dev, interrupts_enabled);
-        if (ret) {
-                dev_err(&dev->pdev->dev, "hw reset failed disabling the device\n");
-                interrupts_enabled = false;
-                dev->dev_state = MEI_DEV_DISABLED;
-        }
-
-        dev->hbm_state = MEI_HBM_IDLE;
+        mutex_lock(&dev->device_lock);
 
-        if (dev->dev_state != MEI_DEV_INITIALIZING &&
-            dev->dev_state != MEI_DEV_POWER_UP) {
-                if (dev->dev_state != MEI_DEV_DISABLED &&
-                    dev->dev_state != MEI_DEV_POWER_DOWN)
-                        dev->dev_state = MEI_DEV_RESETTING;
+        mei_clear_interrupts(dev);
 
-                /* remove all waiting requests */
-                mei_cl_all_write_clear(dev);
+        dev->dev_state = MEI_DEV_POWER_UP;
+        dev->reset_count = 0;
 
-                mei_cl_all_disconnect(dev);
+        err = mei_reset(dev);
 
-                /* wake up all readings so they can be interrupted */
-                mei_cl_all_wakeup(dev);
-
-                /* remove entry if already in list */
-                dev_dbg(&dev->pdev->dev, "remove iamthif and wd from the file list.\n");
-                mei_cl_unlink(&dev->wd_cl);
-                mei_cl_unlink(&dev->iamthif_cl);
-                mei_amthif_reset_params(dev);
-                memset(&dev->wr_ext_msg, 0, sizeof(dev->wr_ext_msg));
-        }
+        mutex_unlock(&dev->device_lock);
 
-        /* we're already in reset, cancel the init timer */
-        dev->init_clients_timer = 0;
+        if (err || dev->dev_state == MEI_DEV_DISABLED)
+                return -ENODEV;
 
-        dev->me_clients_num = 0;
-        dev->rd_msg_hdr = 0;
-        dev->wd_pending = false;
+        return 0;
+}
+EXPORT_SYMBOL_GPL(mei_restart);
 
-        if (!interrupts_enabled) {
-                dev_dbg(&dev->pdev->dev, "intr not enabled end of reset\n");
-                return;
-        }
 
-        ret = mei_hw_start(dev);
-        if (ret) {
-                dev_err(&dev->pdev->dev, "hw_start failed disabling the device\n");
-                dev->dev_state = MEI_DEV_DISABLED;
-                return;
-        }
+static void mei_reset_work(struct work_struct *work)
+{
+        struct mei_device *dev =
+                container_of(work, struct mei_device,  reset_work);
 
-        dev_dbg(&dev->pdev->dev, "link is established start sending messages.\n");
-        /* link is established * start sending messages.  */
+        mutex_lock(&dev->device_lock);
 
-        dev->dev_state = MEI_DEV_INIT_CLIENTS;
+        mei_reset(dev);
 
-        mei_hbm_start_req(dev);
+        mutex_unlock(&dev->device_lock);
 
+        if (dev->dev_state == MEI_DEV_DISABLED)
+                dev_err(&dev->pdev->dev, "reset failed");
 }
-EXPORT_SYMBOL_GPL(mei_reset);
 
 void mei_stop(struct mei_device *dev)
 {
         dev_dbg(&dev->pdev->dev, "stopping the device.\n");
 
-        flush_scheduled_work();
+        mei_cancel_work(dev);
 
-        mutex_lock(&dev->device_lock);
+        mei_nfc_host_exit(dev);
 
-        cancel_delayed_work(&dev->timer_work);
+        mutex_lock(&dev->device_lock);
 
         mei_wd_stop(dev);
 
-        mei_nfc_host_exit();
-
         dev->dev_state = MEI_DEV_POWER_DOWN;
-        mei_reset(dev, 0);
+        mei_reset(dev);
 
         mutex_unlock(&dev->device_lock);
 
@@ -236,3 +284,41 @@ EXPORT_SYMBOL_GPL(mei_stop);
 
 
 
+void mei_device_init(struct mei_device *dev)
+{
+        /* setup our list array */
+        INIT_LIST_HEAD(&dev->file_list);
+        INIT_LIST_HEAD(&dev->device_list);
+        mutex_init(&dev->device_lock);
+        init_waitqueue_head(&dev->wait_hw_ready);
+        init_waitqueue_head(&dev->wait_recvd_msg);
+        init_waitqueue_head(&dev->wait_stop_wd);
+        dev->dev_state = MEI_DEV_INITIALIZING;
+        dev->reset_count = 0;
+
+        mei_io_list_init(&dev->read_list);
+        mei_io_list_init(&dev->write_list);
+        mei_io_list_init(&dev->write_waiting_list);
+        mei_io_list_init(&dev->ctrl_wr_list);
+        mei_io_list_init(&dev->ctrl_rd_list);
+
+        INIT_DELAYED_WORK(&dev->timer_work, mei_timer);
+        INIT_WORK(&dev->init_work, mei_host_client_init);
+        INIT_WORK(&dev->reset_work, mei_reset_work);
+
+        INIT_LIST_HEAD(&dev->wd_cl.link);
+        INIT_LIST_HEAD(&dev->iamthif_cl.link);
+        mei_io_list_init(&dev->amthif_cmd_list);
+        mei_io_list_init(&dev->amthif_rd_complete_list);
+
+        bitmap_zero(dev->host_clients_map, MEI_CLIENTS_MAX);
+        dev->open_handle_count = 0;
+
+        /*
+         * Reserving the first client ID
+         * 0: Reserved for MEI Bus Message communications
+         */
+        bitmap_set(dev->host_clients_map, 0, 1);
+}
+EXPORT_SYMBOL_GPL(mei_device_init);
+
diff --git a/drivers/misc/mei/interrupt.c b/drivers/misc/mei/interrupt.c
index 7a95c07e59a6..f0fbb5179f80 100644
--- a/drivers/misc/mei/interrupt.c
+++ b/drivers/misc/mei/interrupt.c
@@ -31,7 +31,7 @@
 
 
 /**
- * mei_irq_compl_handler - dispatch complete handelers
+ * mei_irq_compl_handler - dispatch complete handlers
  *      for the completed callbacks
  *
  * @dev - mei device
@@ -301,13 +301,11 @@ int mei_irq_read_handler(struct mei_device *dev,
                 struct mei_cl_cb *cmpl_list, s32 *slots)
 {
         struct mei_msg_hdr *mei_hdr;
-        struct mei_cl *cl_pos = NULL;
-        struct mei_cl *cl_next = NULL;
-        int ret = 0;
+        struct mei_cl *cl;
+        int ret;
 
         if (!dev->rd_msg_hdr) {
                 dev->rd_msg_hdr = mei_read_hdr(dev);
-                dev_dbg(&dev->pdev->dev, "slots =%08x.\n", *slots);
                 (*slots)--;
                 dev_dbg(&dev->pdev->dev, "slots =%08x.\n", *slots);
         }
@@ -315,61 +313,67 @@ int mei_irq_read_handler(struct mei_device *dev,
         dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(mei_hdr));
 
         if (mei_hdr->reserved || !dev->rd_msg_hdr) {
-                dev_dbg(&dev->pdev->dev, "corrupted message header.\n");
+                dev_err(&dev->pdev->dev, "corrupted message header 0x%08X\n",
+                                dev->rd_msg_hdr);
                 ret = -EBADMSG;
                 goto end;
         }
 
-        if (mei_hdr->host_addr || mei_hdr->me_addr) {
-                list_for_each_entry_safe(cl_pos, cl_next,
-                                        &dev->file_list, link) {
-                        dev_dbg(&dev->pdev->dev,
-                                        "list_for_each_entry_safe read host"
-                                        " client = %d, ME client = %d\n",
-                                        cl_pos->host_client_id,
-                                        cl_pos->me_client_id);
-                        if (mei_cl_hbm_equal(cl_pos, mei_hdr))
-                                break;
-                }
-
-                if (&cl_pos->link == &dev->file_list) {
-                        dev_dbg(&dev->pdev->dev, "corrupted message header\n");
-                        ret = -EBADMSG;
-                        goto end;
-                }
-        }
-        if (((*slots) * sizeof(u32)) < mei_hdr->length) {
-                dev_err(&dev->pdev->dev,
-                                "we can't read the message slots =%08x.\n",
+        if (mei_slots2data(*slots) < mei_hdr->length) {
+                dev_err(&dev->pdev->dev, "less data available than length=%08x.\n",
                                 *slots);
                 /* we can't read the message */
                 ret = -ERANGE;
                 goto end;
         }
 
-        /* decide where to read the message too */
-        if (!mei_hdr->host_addr) {
-                dev_dbg(&dev->pdev->dev, "call mei_hbm_dispatch.\n");
-                mei_hbm_dispatch(dev, mei_hdr);
-                dev_dbg(&dev->pdev->dev, "end mei_hbm_dispatch.\n");
-        } else if (mei_hdr->host_addr == dev->iamthif_cl.host_client_id &&
-                   (MEI_FILE_CONNECTED == dev->iamthif_cl.state) &&
-                   (dev->iamthif_state == MEI_IAMTHIF_READING)) {
+        /*  HBM message */
+        if (mei_hdr->host_addr == 0 && mei_hdr->me_addr == 0) {
+                ret = mei_hbm_dispatch(dev, mei_hdr);
+                if (ret) {
+                        dev_dbg(&dev->pdev->dev, "mei_hbm_dispatch failed ret = %d\n",
+                                        ret);
+                        goto end;
+                }
+                goto reset_slots;
+        }
+
+        /* find recipient cl */
+        list_for_each_entry(cl, &dev->file_list, link) {
+                if (mei_cl_hbm_equal(cl, mei_hdr)) {
+                        cl_dbg(dev, cl, "got a message\n");
+                        break;
+                }
+        }
+
+        /* if no recipient cl was found we assume corrupted header */
+        if (&cl->link == &dev->file_list) {
+                dev_err(&dev->pdev->dev, "no destination client found 0x%08X\n",
+                                dev->rd_msg_hdr);
+                ret = -EBADMSG;
+                goto end;
+        }
 
-                dev_dbg(&dev->pdev->dev, "call mei_amthif_irq_read_msg.\n");
-                dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(mei_hdr));
+        if (mei_hdr->host_addr == dev->iamthif_cl.host_client_id &&
+            MEI_FILE_CONNECTED == dev->iamthif_cl.state &&
+            dev->iamthif_state == MEI_IAMTHIF_READING) {
 
                 ret = mei_amthif_irq_read_msg(dev, mei_hdr, cmpl_list);
-                if (ret)
+                if (ret) {
+                        dev_err(&dev->pdev->dev, "mei_amthif_irq_read_msg failed = %d\n",
+                                        ret);
                         goto end;
+                }
         } else {
-                dev_dbg(&dev->pdev->dev, "call mei_cl_irq_read_msg.\n");
-                dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(mei_hdr));
                 ret = mei_cl_irq_read_msg(dev, mei_hdr, cmpl_list);
-                if (ret)
+                if (ret) {
+                        dev_err(&dev->pdev->dev, "mei_cl_irq_read_msg failed = %d\n",
+                                        ret);
                         goto end;
+                }
         }
 
+reset_slots:
         /* reset the number of slots and header */
         *slots = mei_count_full_read_slots(dev);
         dev->rd_msg_hdr = 0;
@@ -533,7 +537,6 @@ EXPORT_SYMBOL_GPL(mei_irq_write_handler);
  *
  * @work: pointer to the work_struct structure
  *
- * NOTE: This function is called by timer interrupt work
  */
 void mei_timer(struct work_struct *work)
 {
@@ -548,24 +551,30 @@ void mei_timer(struct work_struct *work)
 
 
         mutex_lock(&dev->device_lock);
-        if (dev->dev_state != MEI_DEV_ENABLED) {
-                if (dev->dev_state == MEI_DEV_INIT_CLIENTS) {
-                        if (dev->init_clients_timer) {
-                                if (--dev->init_clients_timer == 0) {
-                                        dev_err(&dev->pdev->dev, "reset: init clients timeout hbm_state = %d.\n",
-                                                dev->hbm_state);
-                                        mei_reset(dev, 1);
-                                }
+
+        /* Catch interrupt stalls during HBM init handshake */
+        if (dev->dev_state == MEI_DEV_INIT_CLIENTS &&
+            dev->hbm_state != MEI_HBM_IDLE) {
+
+                if (dev->init_clients_timer) {
+                        if (--dev->init_clients_timer == 0) {
+                                dev_err(&dev->pdev->dev, "timer: init clients timeout hbm_state = %d.\n",
+                                        dev->hbm_state);
+                                mei_reset(dev);
+                                goto out;
                         }
                 }
-                goto out;
         }
+
+        if (dev->dev_state != MEI_DEV_ENABLED)
+                goto out;
+
         /*** connect/disconnect timeouts ***/
         list_for_each_entry_safe(cl_pos, cl_next, &dev->file_list, link) {
                 if (cl_pos->timer_count) {
                         if (--cl_pos->timer_count == 0) {
-                                dev_err(&dev->pdev->dev, "reset: connect/disconnect timeout.\n");
-                                mei_reset(dev, 1);
+                                dev_err(&dev->pdev->dev, "timer: connect/disconnect timeout.\n");
+                                mei_reset(dev);
                                 goto out;
                         }
                 }
@@ -573,8 +582,8 @@ void mei_timer(struct work_struct *work)
 
         if (dev->iamthif_stall_timer) {
                 if (--dev->iamthif_stall_timer == 0) {
-                        dev_err(&dev->pdev->dev, "reset: amthif  hanged.\n");
-                        mei_reset(dev, 1);
+                        dev_err(&dev->pdev->dev, "timer: amthif  hanged.\n");
+                        mei_reset(dev);
                         dev->iamthif_msg_buf_size = 0;
                         dev->iamthif_msg_buf_index = 0;
                         dev->iamthif_canceled = false;
@@ -627,7 +636,8 @@ void mei_timer(struct work_struct *work)
                 }
         }
 out:
-        schedule_delayed_work(&dev->timer_work, 2 * HZ);
+        if (dev->dev_state != MEI_DEV_DISABLED)
+                schedule_delayed_work(&dev->timer_work, 2 * HZ);
         mutex_unlock(&dev->device_lock);
 }
 
diff --git a/drivers/misc/mei/main.c b/drivers/misc/mei/main.c
index 9661a812f550..5424f8ff3f7f 100644
--- a/drivers/misc/mei/main.c
+++ b/drivers/misc/mei/main.c
@@ -48,7 +48,7 @@
  *
  * @inode: pointer to inode structure
  * @file: pointer to file structure
- e
+ *
  * returns 0 on success, <0 on error
  */
 static int mei_open(struct inode *inode, struct file *file)
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 406f68e05b4e..f7de95b4cdd9 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -61,11 +61,16 @@ extern const uuid_le mei_wd_guid;
 #define MEI_CLIENTS_MAX 256
 
 /*
+ * maximum number of consecutive resets
+ */
+#define MEI_MAX_CONSEC_RESET  3
+
+/*
  * Number of File descriptors/handles
  * that can be opened to the driver.
  *
  * Limit to 255: 256 Total Clients
- * minus internal client for MEI Bus Messags
+ * minus internal client for MEI Bus Messages
  */
 #define  MEI_MAX_OPEN_HANDLE_COUNT (MEI_CLIENTS_MAX - 1)
 
@@ -178,9 +183,10 @@ struct mei_cl_cb {
         unsigned long buf_idx;
         unsigned long read_time;
         struct file *file_object;
+        u32 internal:1;
 };
 
-/* MEI client instance carried as file->pirvate_data*/
+/* MEI client instance carried as file->private_data*/
 struct mei_cl {
         struct list_head link;
         struct mei_device *dev;
@@ -326,6 +332,7 @@ struct mei_cl_device {
 /**
  * struct mei_device -  MEI private device struct
 
+ * @reset_count - limits the number of consecutive resets
  * @hbm_state - state of host bus message protocol
  * @mem_addr - mem mapped base register address
 
@@ -369,6 +376,7 @@ struct mei_device {
         /*
          * mei device  states
          */
+        unsigned long reset_count;
         enum mei_dev_state dev_state;
         enum mei_hbm_state hbm_state;
         u16 init_clients_timer;
@@ -427,6 +435,7 @@ struct mei_device {
         bool iamthif_canceled;
 
         struct work_struct init_work;
+        struct work_struct reset_work;
 
         /* List of bus devices */
         struct list_head device_list;
@@ -456,13 +465,25 @@ static inline u32 mei_data2slots(size_t length)
         return DIV_ROUND_UP(sizeof(struct mei_msg_hdr) + length, 4);
 }
 
+/**
+ * mei_slots2data- get data in slots - bytes from slots
+ * @slots -  number of available slots
+ * returns  - number of bytes in slots
+ */
+static inline u32 mei_slots2data(int slots)
+{
+        return slots * 4;
+}
+
 /*
  * mei init function prototypes
  */
 void mei_device_init(struct mei_device *dev);
-void mei_reset(struct mei_device *dev, int interrupts);
+int mei_reset(struct mei_device *dev);
 int mei_start(struct mei_device *dev);
+int mei_restart(struct mei_device *dev);
 void mei_stop(struct mei_device *dev);
+void mei_cancel_work(struct mei_device *dev);
 
 /*
  *  MEI interrupt functions prototype
@@ -510,7 +531,7 @@ int mei_amthif_irq_read(struct mei_device *dev, s32 *slots);
  * NFC functions
  */
 int mei_nfc_host_init(struct mei_device *dev);
-void mei_nfc_host_exit(void);
+void mei_nfc_host_exit(struct mei_device *dev);
 
 /*
  * NFC Client UUID
@@ -626,9 +647,9 @@ static inline void mei_dbgfs_deregister(struct mei_device *dev) {}
 int mei_register(struct mei_device *dev);
 void mei_deregister(struct mei_device *dev);
 
-#define MEI_HDR_FMT "hdr:host=%02d me=%02d len=%d comp=%1d"
+#define MEI_HDR_FMT "hdr:host=%02d me=%02d len=%d internal=%1d comp=%1d"
 #define MEI_HDR_PRM(hdr)                  \
         (hdr)->host_addr, (hdr)->me_addr, \
-        (hdr)->length, (hdr)->msg_complete
+        (hdr)->length, (hdr)->internal, (hdr)->msg_complete
 
 #endif
diff --git a/drivers/misc/mei/nfc.c b/drivers/misc/mei/nfc.c
index 994ca4aff1a3..a58320c0c049 100644
--- a/drivers/misc/mei/nfc.c
+++ b/drivers/misc/mei/nfc.c
@@ -92,7 +92,7 @@ struct mei_nfc_hci_hdr {
  * @cl: NFC host client
  * @cl_info: NFC info host client
  * @init_work: perform connection to the info client
- * @fw_ivn: NFC Intervace Version Number
+ * @fw_ivn: NFC Interface Version Number
  * @vendor_id: NFC manufacturer ID
  * @radio_type: NFC radio type
  */
@@ -163,7 +163,7 @@ static int mei_nfc_build_bus_name(struct mei_nfc_dev *ndev)
                         return 0;
 
                 default:
-                        dev_err(&dev->pdev->dev, "Unknow radio type 0x%x\n",
+                        dev_err(&dev->pdev->dev, "Unknown radio type 0x%x\n",
                                 ndev->radio_type);
 
                         return -EINVAL;
@@ -175,14 +175,14 @@ static int mei_nfc_build_bus_name(struct mei_nfc_dev *ndev)
                         ndev->bus_name = "pn544";
                         return 0;
                 default:
-                        dev_err(&dev->pdev->dev, "Unknow radio type 0x%x\n",
+                        dev_err(&dev->pdev->dev, "Unknown radio type 0x%x\n",
                                 ndev->radio_type);
 
                         return -EINVAL;
                 }
 
         default:
-                dev_err(&dev->pdev->dev, "Unknow vendor ID 0x%x\n",
+                dev_err(&dev->pdev->dev, "Unknown vendor ID 0x%x\n",
                         ndev->vendor_id);
 
                 return -EINVAL;
@@ -428,7 +428,7 @@ static void mei_nfc_init(struct work_struct *work)
         mutex_unlock(&dev->device_lock);
 
         if (mei_nfc_if_version(ndev) < 0) {
-                dev_err(&dev->pdev->dev, "Could not get the NFC interfave version");
+                dev_err(&dev->pdev->dev, "Could not get the NFC interface version");
 
                 goto err;
         }
@@ -469,7 +469,9 @@ static void mei_nfc_init(struct work_struct *work)
         return;
 
 err:
+        mutex_lock(&dev->device_lock);
         mei_nfc_free(ndev);
+        mutex_unlock(&dev->device_lock);
 
         return;
 }
@@ -481,7 +483,7 @@ int mei_nfc_host_init(struct mei_device *dev)
         struct mei_cl *cl_info, *cl = NULL;
         int i, ret;
 
-        /* already initialzed */
+        /* already initialized */
         if (ndev->cl_info)
                 return 0;
 
@@ -547,12 +549,16 @@ err:
         return ret;
 }
 
-void mei_nfc_host_exit(void)
+void mei_nfc_host_exit(struct mei_device *dev)
 {
         struct mei_nfc_dev *ndev = &nfc_dev;
 
+        cancel_work_sync(&ndev->init_work);
+
+        mutex_lock(&dev->device_lock);
         if (ndev->cl && ndev->cl->device)
                 mei_cl_remove_device(ndev->cl->device);
 
         mei_nfc_free(ndev);
+        mutex_unlock(&dev->device_lock);
 }
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index 2cab3c0a6805..ddadd08956f4 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -144,6 +144,21 @@ static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 dev_err(&pdev->dev, "failed to get pci regions.\n");
                 goto disable_device;
         }
+
+        if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
+            dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
+
+                err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+                if (err)
+                        err = dma_set_coherent_mask(&pdev->dev,
+                                                    DMA_BIT_MASK(32));
+        }
+        if (err) {
+                dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
+                goto release_regions;
+        }
+
+
         /* allocates and initializes the mei dev structure */
         dev = mei_me_dev_init(pdev);
         if (!dev) {
@@ -197,8 +212,8 @@ static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         return 0;
 
 release_irq:
+        mei_cancel_work(dev);
         mei_disable_interrupts(dev);
-        flush_scheduled_work();
         free_irq(pdev->irq, dev);
 disable_msi:
         pci_disable_msi(pdev);
@@ -306,16 +321,14 @@ static int mei_me_pci_resume(struct device *device)
                 return err;
         }
 
-        mutex_lock(&dev->device_lock);
-        dev->dev_state = MEI_DEV_POWER_UP;
-        mei_clear_interrupts(dev);
-        mei_reset(dev, 1);
-        mutex_unlock(&dev->device_lock);
+        err = mei_restart(dev);
+        if (err)
+                return err;
 
         /* Start timer if stopped in suspend */
         schedule_delayed_work(&dev->timer_work, HZ);
 
-        return err;
+        return 0;
 }
 static SIMPLE_DEV_PM_OPS(mei_me_pm_ops, mei_me_pci_suspend, mei_me_pci_resume);
 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
diff --git a/drivers/misc/mei/wd.c b/drivers/misc/mei/wd.c
index 9e354216c163..f70945ed96f6 100644
--- a/drivers/misc/mei/wd.c
+++ b/drivers/misc/mei/wd.c
@@ -115,6 +115,7 @@ int mei_wd_send(struct mei_device *dev)
         hdr.me_addr = dev->wd_cl.me_client_id;
         hdr.msg_complete = 1;
         hdr.reserved = 0;
+        hdr.internal = 0;
 
         if (!memcmp(dev->wd_data, mei_start_wd_params, MEI_WD_HDR_SIZE))
                 hdr.length = MEI_WD_START_MSG_SIZE;
diff --git a/drivers/misc/mic/host/mic_device.h b/drivers/misc/mic/host/mic_device.h
index 3574cc375bb9..b2da289320c9 100644
--- a/drivers/misc/mic/host/mic_device.h
+++ b/drivers/misc/mic/host/mic_device.h
@@ -134,6 +134,8 @@ struct mic_device {
  * @send_intr: Send an interrupt for a particular doorbell on the card.
  * @ack_interrupt: Hardware specific operations to ack the h/w on
  * receipt of an interrupt.
+ * @intr_workarounds: Hardware specific workarounds needed after
+ * handling an interrupt.
  * @reset: Reset the remote processor.
  * @reset_fw_ready: Reset firmware ready field.
  * @is_fw_ready: Check if firmware is ready for OS download.
@@ -149,6 +151,7 @@ struct mic_hw_ops {
         void (*write_spad)(struct mic_device *mdev, unsigned int idx, u32 val);
         void (*send_intr)(struct mic_device *mdev, int doorbell);
         u32 (*ack_interrupt)(struct mic_device *mdev);
+        void (*intr_workarounds)(struct mic_device *mdev);
         void (*reset)(struct mic_device *mdev);
         void (*reset_fw_ready)(struct mic_device *mdev);
         bool (*is_fw_ready)(struct mic_device *mdev);
diff --git a/drivers/misc/mic/host/mic_main.c b/drivers/misc/mic/host/mic_main.c
index ad838c7651c4..c04a021e20c7 100644
--- a/drivers/misc/mic/host/mic_main.c
+++ b/drivers/misc/mic/host/mic_main.c
@@ -115,7 +115,7 @@ static irqreturn_t mic_shutdown_db(int irq, void *data)
         struct mic_device *mdev = data;
         struct mic_bootparam *bootparam = mdev->dp;
 
-        mdev->ops->ack_interrupt(mdev);
+        mdev->ops->intr_workarounds(mdev);
 
         switch (bootparam->shutdown_status) {
         case MIC_HALTED:
diff --git a/drivers/misc/mic/host/mic_virtio.c b/drivers/misc/mic/host/mic_virtio.c
index e04bb4fe6823..752ff873f891 100644
--- a/drivers/misc/mic/host/mic_virtio.c
+++ b/drivers/misc/mic/host/mic_virtio.c
@@ -369,7 +369,7 @@ static irqreturn_t mic_virtio_intr_handler(int irq, void *data)
         struct mic_vdev *mvdev = data;
         struct mic_device *mdev = mvdev->mdev;
 
-        mdev->ops->ack_interrupt(mdev);
+        mdev->ops->intr_workarounds(mdev);
         schedule_work(&mvdev->virtio_bh_work);
         return IRQ_HANDLED;
 }
diff --git a/drivers/misc/mic/host/mic_x100.c b/drivers/misc/mic/host/mic_x100.c
index 0dfa8a81436e..5562fdd3ef4e 100644
--- a/drivers/misc/mic/host/mic_x100.c
+++ b/drivers/misc/mic/host/mic_x100.c
@@ -174,35 +174,38 @@ static void mic_x100_send_intr(struct mic_device *mdev, int doorbell)
 }
 
 /**
- * mic_ack_interrupt - Device specific interrupt handling.
- * @mdev: pointer to mic_device instance
+ * mic_x100_ack_interrupt - Read the interrupt sources register and
+ * clear it. This function will be called in the MSI/INTx case.
+ * @mdev: Pointer to mic_device instance.
  *
- * Returns: bitmask of doorbell events triggered.
+ * Returns: bitmask of interrupt sources triggered.
  */
 static u32 mic_x100_ack_interrupt(struct mic_device *mdev)
 {
-        u32 reg = 0;
-        struct mic_mw *mw = &mdev->mmio;
         u32 sicr0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SICR0;
+        u32 reg = mic_mmio_read(&mdev->mmio, sicr0);
+        mic_mmio_write(&mdev->mmio, reg, sicr0);
+        return reg;
+}
+
+/**
+ * mic_x100_intr_workarounds - These hardware specific workarounds are
+ * to be invoked everytime an interrupt is handled.
+ * @mdev: Pointer to mic_device instance.
+ *
+ * Returns: none
+ */
+static void mic_x100_intr_workarounds(struct mic_device *mdev)
+{
+        struct mic_mw *mw = &mdev->mmio;
 
         /* Clear pending bit array. */
         if (MIC_A0_STEP == mdev->stepping)
                 mic_mmio_write(mw, 1, MIC_X100_SBOX_BASE_ADDRESS +
                         MIC_X100_SBOX_MSIXPBACR);
 
-        if (mdev->irq_info.num_vectors <= 1) {
-                reg = mic_mmio_read(mw, sicr0);
-
-                if (unlikely(!reg))
-                        goto done;
-
-                mic_mmio_write(mw, reg, sicr0);
-        }
-
         if (mdev->stepping >= MIC_B0_STEP)
                 mdev->intr_ops->enable_interrupts(mdev);
-done:
-        return reg;
 }
 
 /**
@@ -553,6 +556,7 @@ struct mic_hw_ops mic_x100_ops = {
         .write_spad = mic_x100_write_spad,
         .send_intr = mic_x100_send_intr,
         .ack_interrupt = mic_x100_ack_interrupt,
+        .intr_workarounds = mic_x100_intr_workarounds,
         .reset = mic_x100_hw_reset,
         .reset_fw_ready = mic_x100_reset_fw_ready,
         .is_fw_ready = mic_x100_is_fw_ready,
diff --git a/drivers/misc/sgi-xp/xpc_channel.c b/drivers/misc/sgi-xp/xpc_channel.c
index 652593fc486d..128d5615c804 100644
--- a/drivers/misc/sgi-xp/xpc_channel.c
+++ b/drivers/misc/sgi-xp/xpc_channel.c
@@ -828,6 +828,7 @@ enum xp_retval
 xpc_allocate_msg_wait(struct xpc_channel *ch)
 {
         enum xp_retval ret;
+        DEFINE_WAIT(wait);
 
         if (ch->flags & XPC_C_DISCONNECTING) {
                 DBUG_ON(ch->reason == xpInterrupted);
@@ -835,7 +836,9 @@ xpc_allocate_msg_wait(struct xpc_channel *ch)
         }
 
         atomic_inc(&ch->n_on_msg_allocate_wq);
-        ret = interruptible_sleep_on_timeout(&ch->msg_allocate_wq, 1);
+        prepare_to_wait(&ch->msg_allocate_wq, &wait, TASK_INTERRUPTIBLE);
+        ret = schedule_timeout(1);
+        finish_wait(&ch->msg_allocate_wq, &wait);
         atomic_dec(&ch->n_on_msg_allocate_wq);
 
         if (ch->flags & XPC_C_DISCONNECTING) {
diff --git a/drivers/misc/ti-st/st_core.c b/drivers/misc/ti-st/st_core.c
index 8d64b681dd93..3aed525e55b4 100644
--- a/drivers/misc/ti-st/st_core.c
+++ b/drivers/misc/ti-st/st_core.c
@@ -812,7 +812,7 @@ static void st_tty_flush_buffer(struct tty_struct *tty)
         kfree_skb(st_gdata->tx_skb);
         st_gdata->tx_skb = NULL;
 
-        tty->ops->flush_buffer(tty);
+        tty_driver_flush_buffer(tty);
         return;
 }
 
diff --git a/drivers/misc/ti-st/st_kim.c b/drivers/misc/ti-st/st_kim.c
index 96853a09788a..9d3dbb28734b 100644
--- a/drivers/misc/ti-st/st_kim.c
+++ b/drivers/misc/ti-st/st_kim.c
@@ -531,7 +531,6 @@ long st_kim_stop(void *kim_data)
                 /* Flush any pending characters in the driver and discipline. */
                 tty_ldisc_flush(tty);
                 tty_driver_flush_buffer(tty);
-                tty->ops->flush_buffer(tty);
         }
 
         /* send uninstall notification to UIM */
diff --git a/drivers/misc/vmw_vmci/vmci_guest.c b/drivers/misc/vmw_vmci/vmci_guest.c
index c98b03b99353..d35cda06b5e8 100644
--- a/drivers/misc/vmw_vmci/vmci_guest.c
+++ b/drivers/misc/vmw_vmci/vmci_guest.c
@@ -165,7 +165,7 @@ static void vmci_guest_cid_update(u32 sub_id,
  * true if required hypercalls (or fallback hypercalls) are
  * supported by the host, false otherwise.
  */
-static bool vmci_check_host_caps(struct pci_dev *pdev)
+static int vmci_check_host_caps(struct pci_dev *pdev)
 {
         bool result;
         struct vmci_resource_query_msg *msg;
@@ -176,7 +176,7 @@ static bool vmci_check_host_caps(struct pci_dev *pdev)
         check_msg = kmalloc(msg_size, GFP_KERNEL);
         if (!check_msg) {
                 dev_err(&pdev->dev, "%s: Insufficient memory\n", __func__);
-                return false;
+                return -ENOMEM;
         }
 
         check_msg->dst = vmci_make_handle(VMCI_HYPERVISOR_CONTEXT_ID,
@@ -196,7 +196,7 @@ static bool vmci_check_host_caps(struct pci_dev *pdev)
                 __func__, result ? "PASSED" : "FAILED");
 
         /* We need the vector. There are no fallbacks. */
-        return result;
+        return result ? 0 : -ENXIO;
 }
 
 /*
@@ -564,12 +564,14 @@ static int vmci_guest_probe_device(struct pci_dev *pdev,
                         dev_warn(&pdev->dev,
                                  "VMCI device unable to register notification bitmap with PPN 0x%x\n",
                                  (u32) bitmap_ppn);
+                        error = -ENXIO;
                         goto err_remove_vmci_dev_g;
                 }
         }
 
         /* Check host capabilities. */
-        if (!vmci_check_host_caps(pdev))
+        error = vmci_check_host_caps(pdev);
+        if (error)
                 goto err_remove_bitmap;
 
         /* Enable device. */
diff --git a/drivers/parport/parport_pc.c b/drivers/parport/parport_pc.c
index 963761526229..76ee7750bc5e 100644
--- a/drivers/parport/parport_pc.c
+++ b/drivers/parport/parport_pc.c
@@ -2600,8 +2600,6 @@ enum parport_pc_pci_cards {
         syba_2p_epp,
         syba_1p_ecp,
         titan_010l,
-        titan_1284p1,
-        titan_1284p2,
         avlab_1p,
         avlab_2p,
         oxsemi_952,
@@ -2660,8 +2658,6 @@ static struct parport_pc_pci {
         /* syba_2p_epp AP138B */        { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
         /* syba_1p_ecp W83787 */        { 1, { { 0, 0x078 }, } },
         /* titan_010l */                { 1, { { 3, -1 }, } },
-        /* titan_1284p1 */              { 1, { { 0, 1 }, } },
-        /* titan_1284p2 */              { 2, { { 0, 1 }, { 2, 3 }, } },
         /* avlab_1p             */      { 1, { { 0, 1}, } },
         /* avlab_2p             */      { 2, { { 0, 1}, { 2, 3 },} },
         /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
@@ -2677,8 +2673,8 @@ static struct parport_pc_pci {
         /* netmos_9705 */               { 1, { { 0, -1 }, } },
         /* netmos_9715 */               { 2, { { 0, 1 }, { 2, 3 },} },
         /* netmos_9755 */               { 2, { { 0, 1 }, { 2, 3 },} },
-        /* netmos_9805 */               { 1, { { 0, -1 }, } },
-        /* netmos_9815 */               { 2, { { 0, -1 }, { 2, -1 }, } },
+        /* netmos_9805 */               { 1, { { 0, 1 }, } },
+        /* netmos_9815 */               { 2, { { 0, 1 }, { 2, 3 }, } },
         /* netmos_9901 */               { 1, { { 0, -1 }, } },
         /* netmos_9865 */               { 1, { { 0, -1 }, } },
         /* quatech_sppxp100 */          { 1, { { 0, 1 }, } },
@@ -2722,8 +2718,6 @@ static const struct pci_device_id parport_pc_pci_tbl[] = {
           PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
         { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
           PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
-        { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 },
-        { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
         /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
         /* AFAVLAB_TK9902 */
         { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
@@ -2827,16 +2821,12 @@ static int parport_pc_pci_probe(struct pci_dev *dev,
                 if (irq == IRQ_NONE) {
                         printk(KERN_DEBUG
         "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
-                                parport_pc_pci_tbl[i + last_sio].vendor,
-                                parport_pc_pci_tbl[i + last_sio].device,
-                                io_lo, io_hi);
+                                id->vendor, id->device, io_lo, io_hi);
                         irq = PARPORT_IRQ_NONE;
                 } else {
                         printk(KERN_DEBUG
         "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
-                                parport_pc_pci_tbl[i + last_sio].vendor,
-                                parport_pc_pci_tbl[i + last_sio].device,
-                                io_lo, io_hi, irq);
+                                id->vendor, id->device, io_lo, io_hi, irq);
                 }
                 data->ports[count] =
                         parport_pc_probe_port(io_lo, io_hi, irq,
@@ -2866,8 +2856,6 @@ static void parport_pc_pci_remove(struct pci_dev *dev)
         struct pci_parport_data *data = pci_get_drvdata(dev);
         int i;
 
-        pci_set_drvdata(dev, NULL);
-
         if (data) {
                 for (i = data->num - 1; i >= 0; i--)
                         parport_pc_unregister_port(data->ports[i]);
diff --git a/drivers/pcmcia/bfin_cf_pcmcia.c b/drivers/pcmcia/bfin_cf_pcmcia.c
index ed3b522601b3..971991bab975 100644
--- a/drivers/pcmcia/bfin_cf_pcmcia.c
+++ b/drivers/pcmcia/bfin_cf_pcmcia.c
@@ -303,7 +303,7 @@ static int bfin_cf_remove(struct platform_device *pdev)
 
 static struct platform_driver bfin_cf_driver = {
         .driver = {
-                   .name = (char *)driver_name,
+                   .name = driver_name,
                    .owner = THIS_MODULE,
                    },
         .probe = bfin_cf_probe,
diff --git a/drivers/pcmcia/electra_cf.c b/drivers/pcmcia/electra_cf.c
index 1b206eac5f93..5ea64d0f61ab 100644
--- a/drivers/pcmcia/electra_cf.c
+++ b/drivers/pcmcia/electra_cf.c
@@ -359,7 +359,7 @@ MODULE_DEVICE_TABLE(of, electra_cf_match);
 
 static struct platform_driver electra_cf_driver = {
         .driver = {
-                .name = (char *)driver_name,
+                .name = driver_name,
                 .owner = THIS_MODULE,
                 .of_match_table = electra_cf_match,
         },
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 330ef2d06567..d0611b84d7f7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -21,6 +21,12 @@ config PHY_EXYNOS_MIPI_VIDEO
           Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
           and EXYNOS SoCs.
 
+config PHY_MVEBU_SATA
+        def_bool y
+        depends on ARCH_KIRKWOOD || ARCH_DOVE
+        depends on OF
+        select GENERIC_PHY
+
 config OMAP_USB2
         tristate "OMAP USB2 PHY Driver"
         depends on ARCH_OMAP2PLUS
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d0caae9cfb83..4e4adc96f753 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -5,5 +5,6 @@
 obj-$(CONFIG_GENERIC_PHY)               += phy-core.o
 obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)       += phy-exynos-dp-video.o
 obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)     += phy-exynos-mipi-video.o
+obj-$(CONFIG_PHY_MVEBU_SATA)            += phy-mvebu-sata.o
 obj-$(CONFIG_OMAP_USB2)                 += phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)               += phy-twl4030-usb.o
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 58e0e9739028..645c867c1257 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -94,19 +94,31 @@ static struct phy_provider *of_phy_provider_lookup(struct device_node *node)
 
 int phy_pm_runtime_get(struct phy *phy)
 {
+        int ret;
+
         if (!pm_runtime_enabled(&phy->dev))
                 return -ENOTSUPP;
 
-        return pm_runtime_get(&phy->dev);
+        ret = pm_runtime_get(&phy->dev);
+        if (ret < 0 && ret != -EINPROGRESS)
+                pm_runtime_put_noidle(&phy->dev);
+
+        return ret;
 }
 EXPORT_SYMBOL_GPL(phy_pm_runtime_get);
 
 int phy_pm_runtime_get_sync(struct phy *phy)
 {
+        int ret;
+
         if (!pm_runtime_enabled(&phy->dev))
                 return -ENOTSUPP;
 
-        return pm_runtime_get_sync(&phy->dev);
+        ret = pm_runtime_get_sync(&phy->dev);
+        if (ret < 0)
+                pm_runtime_put_sync(&phy->dev);
+
+        return ret;
 }
 EXPORT_SYMBOL_GPL(phy_pm_runtime_get_sync);
 
@@ -155,13 +167,14 @@ int phy_init(struct phy *phy)
                 return ret;
 
         mutex_lock(&phy->mutex);
-        if (phy->init_count++ == 0 && phy->ops->init) {
+        if (phy->init_count == 0 && phy->ops->init) {
                 ret = phy->ops->init(phy);
                 if (ret < 0) {
                         dev_err(&phy->dev, "phy init failed --> %d\n", ret);
                         goto out;
                 }
         }
+        ++phy->init_count;
 
 out:
         mutex_unlock(&phy->mutex);
@@ -179,13 +192,14 @@ int phy_exit(struct phy *phy)
                 return ret;
 
         mutex_lock(&phy->mutex);
-        if (--phy->init_count == 0 && phy->ops->exit) {
+        if (phy->init_count == 1 && phy->ops->exit) {
                 ret = phy->ops->exit(phy);
                 if (ret < 0) {
                         dev_err(&phy->dev, "phy exit failed --> %d\n", ret);
                         goto out;
                 }
         }
+        --phy->init_count;
 
 out:
         mutex_unlock(&phy->mutex);
@@ -196,23 +210,27 @@ EXPORT_SYMBOL_GPL(phy_exit);
 
 int phy_power_on(struct phy *phy)
 {
-        int ret = -ENOTSUPP;
+        int ret;
 
         ret = phy_pm_runtime_get_sync(phy);
         if (ret < 0 && ret != -ENOTSUPP)
                 return ret;
 
         mutex_lock(&phy->mutex);
-        if (phy->power_count++ == 0 && phy->ops->power_on) {
+        if (phy->power_count == 0 && phy->ops->power_on) {
                 ret = phy->ops->power_on(phy);
                 if (ret < 0) {
                         dev_err(&phy->dev, "phy poweron failed --> %d\n", ret);
                         goto out;
                 }
         }
+        ++phy->power_count;
+        mutex_unlock(&phy->mutex);
+        return 0;
 
 out:
         mutex_unlock(&phy->mutex);
+        phy_pm_runtime_put_sync(phy);
 
         return ret;
 }
@@ -220,22 +238,22 @@ EXPORT_SYMBOL_GPL(phy_power_on);
 
 int phy_power_off(struct phy *phy)
 {
-        int ret = -ENOTSUPP;
+        int ret;
 
         mutex_lock(&phy->mutex);
-        if (--phy->power_count == 0 && phy->ops->power_off) {
+        if (phy->power_count == 1 && phy->ops->power_off) {
                 ret =  phy->ops->power_off(phy);
                 if (ret < 0) {
                         dev_err(&phy->dev, "phy poweroff failed --> %d\n", ret);
-                        goto out;
+                        mutex_unlock(&phy->mutex);
+                        return ret;
                 }
         }
-
-out:
+        --phy->power_count;
         mutex_unlock(&phy->mutex);
         phy_pm_runtime_put(phy);
 
-        return ret;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(phy_power_off);
 
@@ -360,7 +378,7 @@ EXPORT_SYMBOL_GPL(of_phy_simple_xlate);
 struct phy *phy_get(struct device *dev, const char *string)
 {
         int index = 0;
-        struct phy *phy = NULL;
+        struct phy *phy;
 
         if (string == NULL) {
                 dev_WARN(dev, "missing string\n");
diff --git a/drivers/phy/phy-mvebu-sata.c b/drivers/phy/phy-mvebu-sata.c
new file mode 100644
index 000000000000..d43786f62437
--- /dev/null
+++ b/drivers/phy/phy-mvebu-sata.c
@@ -0,0 +1,137 @@
+/*
+ *      phy-mvebu-sata.c: SATA Phy driver for the Marvell mvebu SoCs.
+ *
+ *      Copyright (C) 2013 Andrew Lunn <andrew@lunn.ch>
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+struct priv {
+        struct clk      *clk;
+        void __iomem    *base;
+};
+
+#define SATA_PHY_MODE_2 0x0330
+#define  MODE_2_FORCE_PU_TX     BIT(0)
+#define  MODE_2_FORCE_PU_RX     BIT(1)
+#define  MODE_2_PU_PLL          BIT(2)
+#define  MODE_2_PU_IVREF        BIT(3)
+#define SATA_IF_CTRL    0x0050
+#define  CTRL_PHY_SHUTDOWN      BIT(9)
+
+static int phy_mvebu_sata_power_on(struct phy *phy)
+{
+        struct priv *priv = phy_get_drvdata(phy);
+        u32 reg;
+
+        clk_prepare_enable(priv->clk);
+
+        /* Enable PLL and IVREF */
+        reg = readl(priv->base + SATA_PHY_MODE_2);
+        reg |= (MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
+                MODE_2_PU_PLL | MODE_2_PU_IVREF);
+        writel(reg , priv->base + SATA_PHY_MODE_2);
+
+        /* Enable PHY */
+        reg = readl(priv->base + SATA_IF_CTRL);
+        reg &= ~CTRL_PHY_SHUTDOWN;
+        writel(reg, priv->base + SATA_IF_CTRL);
+
+        clk_disable_unprepare(priv->clk);
+
+        return 0;
+}
+
+static int phy_mvebu_sata_power_off(struct phy *phy)
+{
+        struct priv *priv = phy_get_drvdata(phy);
+        u32 reg;
+
+        clk_prepare_enable(priv->clk);
+
+        /* Disable PLL and IVREF */
+        reg = readl(priv->base + SATA_PHY_MODE_2);
+        reg &= ~(MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
+                 MODE_2_PU_PLL | MODE_2_PU_IVREF);
+        writel(reg, priv->base + SATA_PHY_MODE_2);
+
+        /* Disable PHY */
+        reg = readl(priv->base + SATA_IF_CTRL);
+        reg |= CTRL_PHY_SHUTDOWN;
+        writel(reg, priv->base + SATA_IF_CTRL);
+
+        clk_disable_unprepare(priv->clk);
+
+        return 0;
+}
+
+static struct phy_ops phy_mvebu_sata_ops = {
+        .power_on       = phy_mvebu_sata_power_on,
+        .power_off      = phy_mvebu_sata_power_off,
+        .owner          = THIS_MODULE,
+};
+
+static int phy_mvebu_sata_probe(struct platform_device *pdev)
+{
+        struct phy_provider *phy_provider;
+        struct resource *res;
+        struct priv *priv;
+        struct phy *phy;
+
+        priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        priv->base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(priv->base))
+                return PTR_ERR(priv->base);
+
+        priv->clk = devm_clk_get(&pdev->dev, "sata");
+        if (IS_ERR(priv->clk))
+                return PTR_ERR(priv->clk);
+
+        phy_provider = devm_of_phy_provider_register(&pdev->dev,
+                                                     of_phy_simple_xlate);
+        if (IS_ERR(phy_provider))
+                return PTR_ERR(phy_provider);
+
+        phy = devm_phy_create(&pdev->dev, &phy_mvebu_sata_ops, NULL);
+        if (IS_ERR(phy))
+                return PTR_ERR(phy);
+
+        phy_set_drvdata(phy, priv);
+
+        /* The boot loader may of left it on. Turn it off. */
+        phy_mvebu_sata_power_off(phy);
+
+        return 0;
+}
+
+static const struct of_device_id phy_mvebu_sata_of_match[] = {
+        { .compatible = "marvell,mvebu-sata-phy" },
+        { },
+};
+MODULE_DEVICE_TABLE(of, phy_mvebu_sata_of_match);
+
+static struct platform_driver phy_mvebu_sata_driver = {
+        .probe  = phy_mvebu_sata_probe,
+        .driver = {
+                .name   = "phy-mvebu-sata",
+                .owner  = THIS_MODULE,
+                .of_match_table = phy_mvebu_sata_of_match,
+        }
+};
+module_platform_driver(phy_mvebu_sata_driver);
+
+MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
+MODULE_DESCRIPTION("Marvell MVEBU SATA PHY driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c
index f7beb6eb40c7..a673e5b6a2e0 100644
--- a/drivers/uio/uio.c
+++ b/drivers/uio/uio.c
@@ -847,7 +847,7 @@ int __uio_register_device(struct module *owner,
         info->uio_dev = idev;
 
         if (info->irq && (info->irq != UIO_IRQ_CUSTOM)) {
-                ret = devm_request_irq(parent, info->irq, uio_interrupt,
+                ret = devm_request_irq(idev->dev, info->irq, uio_interrupt,
                                   info->irq_flags, info->name, idev);
                 if (ret)
                         goto err_request_irq;
diff --git a/drivers/uio/uio_mf624.c b/drivers/uio/uio_mf624.c
index f764adbfe036..d1f95a1567bb 100644
--- a/drivers/uio/uio_mf624.c
+++ b/drivers/uio/uio_mf624.c
@@ -228,7 +228,7 @@ static void mf624_pci_remove(struct pci_dev *dev)
         kfree(info);
 }
 
-static DEFINE_PCI_DEVICE_TABLE(mf624_pci_id) = {
+static const struct pci_device_id mf624_pci_id[] = {
         { PCI_DEVICE(PCI_VENDOR_ID_HUMUSOFT, PCI_DEVICE_ID_MF624) },
         { 0, }
 };
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c
index 15c7251b0556..1e5d94c5afc9 100644
--- a/drivers/w1/masters/mxc_w1.c
+++ b/drivers/w1/masters/mxc_w1.c
@@ -46,7 +46,6 @@
 
 struct mxc_w1_device {
         void __iomem *regs;
-        unsigned int clkdiv;
         struct clk *clk;
         struct w1_bus_master bus_master;
 };
@@ -106,8 +105,10 @@ static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
 static int mxc_w1_probe(struct platform_device *pdev)
 {
         struct mxc_w1_device *mdev;
+        unsigned long clkrate;
         struct resource *res;
-        int err = 0;
+        unsigned int clkdiv;
+        int err;
 
         mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device),
                             GFP_KERNEL);
@@ -118,27 +119,39 @@ static int mxc_w1_probe(struct platform_device *pdev)
         if (IS_ERR(mdev->clk))
                 return PTR_ERR(mdev->clk);
 
-        mdev->clkdiv = (clk_get_rate(mdev->clk) / 1000000) - 1;
+        clkrate = clk_get_rate(mdev->clk);
+        if (clkrate < 10000000)
+                dev_warn(&pdev->dev,
+                         "Low clock frequency causes improper function\n");
+
+        clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000);
+        clkrate /= clkdiv;
+        if ((clkrate < 980000) || (clkrate > 1020000))
+                dev_warn(&pdev->dev,
+                         "Incorrect time base frequency %lu Hz\n", clkrate);
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         mdev->regs = devm_ioremap_resource(&pdev->dev, res);
         if (IS_ERR(mdev->regs))
                 return PTR_ERR(mdev->regs);
 
-        clk_prepare_enable(mdev->clk);
-        __raw_writeb(mdev->clkdiv, mdev->regs + MXC_W1_TIME_DIVIDER);
+        err = clk_prepare_enable(mdev->clk);
+        if (err)
+                return err;
+
+        __raw_writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);
 
         mdev->bus_master.data = mdev;
         mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;
         mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit;
 
-        err = w1_add_master_device(&mdev->bus_master);
+        platform_set_drvdata(pdev, mdev);
 
+        err = w1_add_master_device(&mdev->bus_master);
         if (err)
-                return err;
+                clk_disable_unprepare(mdev->clk);
 
-        platform_set_drvdata(pdev, mdev);
-        return 0;
+        return err;
 }
 
 /*