aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorBen Skeggs <bskeggs@redhat.com>2015-01-13 21:34:00 -0500
committerBen Skeggs <bskeggs@redhat.com>2015-01-21 21:17:47 -0500
commit8700287be2b12d091d477fe0568c3858bdedf4e7 (patch)
tree40a4b59a39a0f77f34b31d30db08b2fd51b9af37 /drivers
parentfd8666f7db94afc1b63b8439d902783b27a2f27f (diff)
drm/nouveau/sw: rename from software (no binary change)
Shorter device name, make consistent with our engine enums. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/device.h2
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/software.h51
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h51
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_chan.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_reg.h2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/Kbuild2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c10
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c12
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c34
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c30
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c20
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c18
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h46
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c (renamed from drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c)66
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c (renamed from drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c)60
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c (renamed from drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c)94
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h46
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c (renamed from drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c)68
32 files changed, 334 insertions, 334 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
index 7f1770beff21..90e2d9706f23 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -53,7 +53,7 @@ void nvif_device_ref(struct nvif_device *, struct nvif_device **);
53#include <engine/device.h> 53#include <engine/device.h>
54#include <engine/fifo.h> 54#include <engine/fifo.h>
55#include <engine/gr.h> 55#include <engine/gr.h>
56#include <engine/software.h> 56#include <engine/sw.h>
57 57
58#define nvkm_fifo(a) nouveau_fifo(nvkm_device(a)) 58#define nvkm_fifo(a) nouveau_fifo(nvkm_device(a))
59#define nvkm_fifo_chan(a) ((struct nouveau_fifo_chan *)nvkm_object(a)) 59#define nvkm_fifo_chan(a) ((struct nouveau_fifo_chan *)nvkm_object(a))
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/software.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/software.h
deleted file mode 100644
index 23a462b50d03..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/software.h
+++ /dev/null
@@ -1,51 +0,0 @@
1#ifndef __NOUVEAU_SOFTWARE_H__
2#define __NOUVEAU_SOFTWARE_H__
3
4#include <core/engine.h>
5#include <core/engctx.h>
6
7struct nouveau_software_chan {
8 struct nouveau_engctx base;
9
10 int (*flip)(void *);
11 void *flip_data;
12};
13
14#define nouveau_software_context_create(p,e,c,d) \
15 nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
16#define nouveau_software_context_destroy(d) \
17 nouveau_engctx_destroy(&(d)->base)
18#define nouveau_software_context_init(d) \
19 nouveau_engctx_init(&(d)->base)
20#define nouveau_software_context_fini(d,s) \
21 nouveau_engctx_fini(&(d)->base, (s))
22
23#define _nouveau_software_context_dtor _nouveau_engctx_dtor
24#define _nouveau_software_context_init _nouveau_engctx_init
25#define _nouveau_software_context_fini _nouveau_engctx_fini
26
27struct nouveau_software {
28 struct nouveau_engine base;
29};
30
31#define nouveau_software_create(p,e,c,d) \
32 nouveau_engine_create((p), (e), (c), true, "SW", "software", (d))
33#define nouveau_software_destroy(d) \
34 nouveau_engine_destroy(&(d)->base)
35#define nouveau_software_init(d) \
36 nouveau_engine_init(&(d)->base)
37#define nouveau_software_fini(d,s) \
38 nouveau_engine_fini(&(d)->base, (s))
39
40#define _nouveau_software_dtor _nouveau_engine_dtor
41#define _nouveau_software_init _nouveau_engine_init
42#define _nouveau_software_fini _nouveau_engine_fini
43
44extern struct nouveau_oclass *nv04_software_oclass;
45extern struct nouveau_oclass *nv10_software_oclass;
46extern struct nouveau_oclass *nv50_software_oclass;
47extern struct nouveau_oclass *nvc0_software_oclass;
48
49void nv04_software_intr(struct nouveau_subdev *);
50
51#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
new file mode 100644
index 000000000000..4c61a39222bb
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
@@ -0,0 +1,51 @@
1#ifndef __NOUVEAU_SW_H__
2#define __NOUVEAU_SW_H__
3
4#include <core/engine.h>
5#include <core/engctx.h>
6
7struct nouveau_sw_chan {
8 struct nouveau_engctx base;
9
10 int (*flip)(void *);
11 void *flip_data;
12};
13
14#define nouveau_sw_context_create(p,e,c,d) \
15 nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d))
16#define nouveau_sw_context_destroy(d) \
17 nouveau_engctx_destroy(&(d)->base)
18#define nouveau_sw_context_init(d) \
19 nouveau_engctx_init(&(d)->base)
20#define nouveau_sw_context_fini(d,s) \
21 nouveau_engctx_fini(&(d)->base, (s))
22
23#define _nouveau_sw_context_dtor _nouveau_engctx_dtor
24#define _nouveau_sw_context_init _nouveau_engctx_init
25#define _nouveau_sw_context_fini _nouveau_engctx_fini
26
27struct nouveau_sw {
28 struct nouveau_engine base;
29};
30
31#define nouveau_sw_create(p,e,c,d) \
32 nouveau_engine_create((p), (e), (c), true, "SW", "software", (d))
33#define nouveau_sw_destroy(d) \
34 nouveau_engine_destroy(&(d)->base)
35#define nouveau_sw_init(d) \
36 nouveau_engine_init(&(d)->base)
37#define nouveau_sw_fini(d,s) \
38 nouveau_engine_fini(&(d)->base, (s))
39
40#define _nouveau_sw_dtor _nouveau_engine_dtor
41#define _nouveau_sw_init _nouveau_engine_init
42#define _nouveau_sw_fini _nouveau_engine_fini
43
44extern struct nouveau_oclass *nv04_sw_oclass;
45extern struct nouveau_oclass *nv10_sw_oclass;
46extern struct nouveau_oclass *nv50_sw_oclass;
47extern struct nouveau_oclass *nvc0_sw_oclass;
48
49void nv04_sw_intr(struct nouveau_subdev *);
50
51#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c
index 80302530ead7..58b8b6423026 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
@@ -282,7 +282,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
282 struct nvif_device *device = chan->device; 282 struct nvif_device *device = chan->device;
283 struct nouveau_cli *cli = (void *)nvif_client(&device->base); 283 struct nouveau_cli *cli = (void *)nvif_client(&device->base);
284 struct nouveau_mmu *mmu = nvkm_mmu(device); 284 struct nouveau_mmu *mmu = nvkm_mmu(device);
285 struct nouveau_software_chan *swch; 285 struct nouveau_sw_chan *swch;
286 struct nv_dma_v0 args = {}; 286 struct nv_dma_v0 args = {};
287 int ret, i; 287 int ret, i;
288 288
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 1118efa56817..e684040ccf11 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -231,7 +231,7 @@ nouveau_accel_init(struct nouveau_drm *drm)
231 ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW, 231 ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW,
232 nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw); 232 nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
233 if (ret == 0) { 233 if (ret == 0) {
234 struct nouveau_software_chan *swch; 234 struct nouveau_sw_chan *swch;
235 ret = RING_SPACE(drm->channel, 2); 235 ret = RING_SPACE(drm->channel, 2);
236 if (ret == 0) { 236 if (ret == 0) {
237 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 237 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index 43a96b99e180..7226f1f60901 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -72,7 +72,7 @@
72# define NV_RAMHT_CONTEXT_VALID (1<<31) 72# define NV_RAMHT_CONTEXT_VALID (1<<31)
73# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24 73# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24
74# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16 74# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16
75# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0 75# define NV_RAMHT_CONTEXT_ENGINE_SW 0
76# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1 76# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1
77# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0 77# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0
78# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23 78# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
index 0607d595f6e7..bc51b0581ba5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -14,5 +14,5 @@ include $(src)/nvkm/engine/msvld/Kbuild
14include $(src)/nvkm/engine/pm/Kbuild 14include $(src)/nvkm/engine/pm/Kbuild
15include $(src)/nvkm/engine/msppp/Kbuild 15include $(src)/nvkm/engine/msppp/Kbuild
16include $(src)/nvkm/engine/sec/Kbuild 16include $(src)/nvkm/engine/sec/Kbuild
17include $(src)/nvkm/engine/software/Kbuild 17include $(src)/nvkm/engine/sw/Kbuild
18include $(src)/nvkm/engine/vp/Kbuild 18include $(src)/nvkm/engine/vp/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 690250503332..55e463396c8c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -45,7 +45,7 @@
45#include <engine/device.h> 45#include <engine/device.h>
46#include <engine/dmaobj.h> 46#include <engine/dmaobj.h>
47#include <engine/fifo.h> 47#include <engine/fifo.h>
48#include <engine/software.h> 48#include <engine/sw.h>
49#include <engine/gr.h> 49#include <engine/gr.h>
50#include <engine/disp.h> 50#include <engine/disp.h>
51#include <engine/ce.h> 51#include <engine/ce.h>
@@ -85,7 +85,7 @@ gm100_identify(struct nouveau_device *device)
85#endif 85#endif
86 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 86 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
87 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; 87 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
88 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 88 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
89 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; 89 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
90 device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass; 90 device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
91 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; 91 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -129,7 +129,7 @@ gm100_identify(struct nouveau_device *device)
129 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 129 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
130#if 0 130#if 0
131 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; 131 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
132 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 132 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
133 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; 133 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
134#endif 134#endif
135 device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; 135 device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index dcb53917b5e0..1d409af560da 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -36,7 +36,7 @@
36#include <engine/device.h> 36#include <engine/device.h>
37#include <engine/dmaobj.h> 37#include <engine/dmaobj.h>
38#include <engine/fifo.h> 38#include <engine/fifo.h>
39#include <engine/software.h> 39#include <engine/sw.h>
40#include <engine/gr.h> 40#include <engine/gr.h>
41#include <engine/disp.h> 41#include <engine/disp.h>
42 42
@@ -58,7 +58,7 @@ nv04_identify(struct nouveau_device *device)
58 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 58 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
59 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 59 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
60 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; 60 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
61 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; 61 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
62 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; 62 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
63 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 63 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
64 break; 64 break;
@@ -76,7 +76,7 @@ nv04_identify(struct nouveau_device *device)
76 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 76 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
78 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; 78 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
79 device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; 79 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
80 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; 80 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
81 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 81 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
82 break; 82 break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index f292e7b88628..66d8c338ae98 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -37,7 +37,7 @@
37#include <engine/device.h> 37#include <engine/device.h>
38#include <engine/dmaobj.h> 38#include <engine/dmaobj.h>
39#include <engine/fifo.h> 39#include <engine/fifo.h>
40#include <engine/software.h> 40#include <engine/sw.h>
41#include <engine/gr.h> 41#include <engine/gr.h>
42#include <engine/disp.h> 42#include <engine/disp.h>
43 43
@@ -77,7 +77,7 @@ nv10_identify(struct nouveau_device *device)
77 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 77 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
79 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 79 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
80 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 80 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
81 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 81 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
82 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 82 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
83 break; 83 break;
@@ -96,7 +96,7 @@ nv10_identify(struct nouveau_device *device)
96 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 96 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
98 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 98 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
99 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 99 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
100 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 100 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
101 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 101 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
102 break; 102 break;
@@ -115,7 +115,7 @@ nv10_identify(struct nouveau_device *device)
115 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 115 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
117 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 117 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
118 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 118 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
119 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 119 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
120 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 120 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
121 break; 121 break;
@@ -134,7 +134,7 @@ nv10_identify(struct nouveau_device *device)
134 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 134 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
136 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 136 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
137 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 137 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
138 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 138 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
139 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 139 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
140 break; 140 break;
@@ -153,7 +153,7 @@ nv10_identify(struct nouveau_device *device)
153 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 153 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
155 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 155 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
156 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 156 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
157 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 157 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
158 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 158 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
159 break; 159 break;
@@ -172,7 +172,7 @@ nv10_identify(struct nouveau_device *device)
172 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 172 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
174 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 174 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
175 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 175 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
176 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 176 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
177 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 177 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
178 break; 178 break;
@@ -191,7 +191,7 @@ nv10_identify(struct nouveau_device *device)
191 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 191 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
193 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 193 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
194 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 194 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
195 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 195 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
196 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 196 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
197 break; 197 break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index a03420ca82b1..59cefdd46897 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -38,7 +38,7 @@
38#include <engine/device.h> 38#include <engine/device.h>
39#include <engine/dmaobj.h> 39#include <engine/dmaobj.h>
40#include <engine/fifo.h> 40#include <engine/fifo.h>
41#include <engine/software.h> 41#include <engine/sw.h>
42#include <engine/gr.h> 42#include <engine/gr.h>
43#include <engine/disp.h> 43#include <engine/disp.h>
44 44
@@ -61,7 +61,7 @@ nv20_identify(struct nouveau_device *device)
61 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 61 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 64 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
65 device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; 65 device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass;
66 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 66 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
67 break; 67 break;
@@ -80,7 +80,7 @@ nv20_identify(struct nouveau_device *device)
80 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 80 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 83 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
84 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; 84 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
85 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 85 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
86 break; 86 break;
@@ -99,7 +99,7 @@ nv20_identify(struct nouveau_device *device)
99 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 99 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 102 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
103 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; 103 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
104 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 104 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
105 break; 105 break;
@@ -118,7 +118,7 @@ nv20_identify(struct nouveau_device *device)
118 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 118 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
119 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 119 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
120 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 120 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
121 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 121 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
122 device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; 122 device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass;
123 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 123 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
124 break; 124 break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index 59b6baa64b4c..dfb610f837b0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -37,7 +37,7 @@
37#include <engine/device.h> 37#include <engine/device.h>
38#include <engine/dmaobj.h> 38#include <engine/dmaobj.h>
39#include <engine/fifo.h> 39#include <engine/fifo.h>
40#include <engine/software.h> 40#include <engine/sw.h>
41#include <engine/gr.h> 41#include <engine/gr.h>
42#include <engine/mpeg.h> 42#include <engine/mpeg.h>
43#include <engine/disp.h> 43#include <engine/disp.h>
@@ -61,7 +61,7 @@ nv30_identify(struct nouveau_device *device)
61 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 61 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 63 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
64 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 64 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
65 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; 65 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
66 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 66 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
67 break; 67 break;
@@ -80,7 +80,7 @@ nv30_identify(struct nouveau_device *device)
80 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 80 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 82 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
83 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 83 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
84 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; 84 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
85 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 85 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
86 break; 86 break;
@@ -99,7 +99,7 @@ nv30_identify(struct nouveau_device *device)
99 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 99 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 101 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
102 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 102 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
103 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; 103 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
104 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; 104 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
105 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 105 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -119,7 +119,7 @@ nv30_identify(struct nouveau_device *device)
119 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 119 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
120 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 120 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
121 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 121 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
122 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 122 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
123 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; 123 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
124 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; 124 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
125 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 125 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -139,7 +139,7 @@ nv30_identify(struct nouveau_device *device)
139 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 139 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
140 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 140 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
141 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 141 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
142 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 142 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
143 device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; 143 device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass;
144 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; 144 device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
145 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 145 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index cd859b081db4..7bdb7d6729b7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -40,7 +40,7 @@
40#include <engine/device.h> 40#include <engine/device.h>
41#include <engine/dmaobj.h> 41#include <engine/dmaobj.h>
42#include <engine/fifo.h> 42#include <engine/fifo.h>
43#include <engine/software.h> 43#include <engine/sw.h>
44#include <engine/gr.h> 44#include <engine/gr.h>
45#include <engine/mpeg.h> 45#include <engine/mpeg.h>
46#include <engine/disp.h> 46#include <engine/disp.h>
@@ -67,7 +67,7 @@ nv40_identify(struct nouveau_device *device)
67 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 67 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
68 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 68 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
69 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 69 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
70 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 70 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
71 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 71 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
72 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 72 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
73 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 73 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -90,7 +90,7 @@ nv40_identify(struct nouveau_device *device)
90 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 90 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
91 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 91 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
92 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 92 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
93 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 93 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
94 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 94 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
95 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 95 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
96 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 96 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -113,7 +113,7 @@ nv40_identify(struct nouveau_device *device)
113 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 113 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
114 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 114 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
115 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 115 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
116 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 116 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
117 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 117 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
118 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 118 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
119 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 119 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -136,7 +136,7 @@ nv40_identify(struct nouveau_device *device)
136 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 136 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
137 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 137 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
138 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 138 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
139 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 139 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
140 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 140 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
141 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; 141 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
142 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 142 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -159,7 +159,7 @@ nv40_identify(struct nouveau_device *device)
159 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 159 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
160 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 160 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
161 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 161 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
162 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 162 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
163 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 163 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
164 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 164 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
165 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 165 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -182,7 +182,7 @@ nv40_identify(struct nouveau_device *device)
182 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 182 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
183 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 183 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
184 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 184 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
185 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 185 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
186 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 186 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
187 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 187 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
188 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 188 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -205,7 +205,7 @@ nv40_identify(struct nouveau_device *device)
205 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 205 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
206 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 206 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
207 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 207 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
208 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 208 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
209 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 209 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
210 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 210 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
211 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 211 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -228,7 +228,7 @@ nv40_identify(struct nouveau_device *device)
228 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 228 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
229 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 229 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
230 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 230 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
231 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 231 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
232 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 232 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
233 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 233 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
234 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 234 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -251,7 +251,7 @@ nv40_identify(struct nouveau_device *device)
251 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 251 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
253 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 253 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
254 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 254 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
255 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 255 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
256 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 256 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
257 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 257 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -274,7 +274,7 @@ nv40_identify(struct nouveau_device *device)
274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
276 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 276 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
277 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 277 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
278 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 278 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
279 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 279 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
280 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 280 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -297,7 +297,7 @@ nv40_identify(struct nouveau_device *device)
297 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 297 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
298 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 298 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
299 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 299 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
300 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 300 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
301 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 301 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
302 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 302 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
303 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 303 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -320,7 +320,7 @@ nv40_identify(struct nouveau_device *device)
320 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 320 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
321 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 321 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
322 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 322 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
323 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 323 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
324 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 324 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
325 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 325 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
326 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 326 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -343,7 +343,7 @@ nv40_identify(struct nouveau_device *device)
343 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 343 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
344 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 344 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
345 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 345 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
346 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 346 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
347 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 347 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
348 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 348 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
349 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 349 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -366,7 +366,7 @@ nv40_identify(struct nouveau_device *device)
366 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 366 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
367 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 367 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
368 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 368 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
369 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 369 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
370 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 370 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
371 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 371 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
372 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 372 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -389,7 +389,7 @@ nv40_identify(struct nouveau_device *device)
389 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 389 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
390 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 390 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
391 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 391 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
392 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 392 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
393 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 393 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
394 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 394 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
395 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 395 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
@@ -412,7 +412,7 @@ nv40_identify(struct nouveau_device *device)
412 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 412 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
413 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 413 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
414 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 414 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
415 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 415 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
416 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 416 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
417 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; 417 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
418 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 418 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 3f3d2ea1a930..13203f53c80d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -43,7 +43,7 @@
43#include <engine/device.h> 43#include <engine/device.h>
44#include <engine/dmaobj.h> 44#include <engine/dmaobj.h>
45#include <engine/fifo.h> 45#include <engine/fifo.h>
46#include <engine/software.h> 46#include <engine/sw.h>
47#include <engine/gr.h> 47#include <engine/gr.h>
48#include <engine/mpeg.h> 48#include <engine/mpeg.h>
49#include <engine/vp.h> 49#include <engine/vp.h>
@@ -80,7 +80,7 @@ nv50_identify(struct nouveau_device *device)
80 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 80 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
82 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; 82 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
83 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 83 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
84 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 84 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
85 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; 85 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
86 device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; 86 device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
@@ -106,7 +106,7 @@ nv50_identify(struct nouveau_device *device)
106 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 106 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
107 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 107 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
108 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 108 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
109 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 109 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
110 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 110 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
111 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 111 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
112 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; 112 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -135,7 +135,7 @@ nv50_identify(struct nouveau_device *device)
135 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 135 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
136 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 136 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
137 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 137 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
138 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 138 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
139 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 139 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
140 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 140 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
141 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; 141 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -164,7 +164,7 @@ nv50_identify(struct nouveau_device *device)
164 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 164 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
166 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 166 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
167 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 167 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
168 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 168 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
169 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 169 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
170 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; 170 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -193,7 +193,7 @@ nv50_identify(struct nouveau_device *device)
193 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 193 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
194 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 194 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
195 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 195 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
196 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 196 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
197 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 197 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
198 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 198 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
199 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; 199 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -222,7 +222,7 @@ nv50_identify(struct nouveau_device *device)
222 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 222 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
223 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 223 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
224 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 224 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
225 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 225 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
226 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 226 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
227 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 227 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
228 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; 228 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -251,7 +251,7 @@ nv50_identify(struct nouveau_device *device)
251 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 251 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
253 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 253 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
254 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 254 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
255 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 255 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
256 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 256 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
257 device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; 257 device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
@@ -280,7 +280,7 @@ nv50_identify(struct nouveau_device *device)
280 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 280 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
281 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 281 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
282 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 282 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
283 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 283 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
284 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 284 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
285 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 285 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
286 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; 286 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
@@ -309,7 +309,7 @@ nv50_identify(struct nouveau_device *device)
309 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 309 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
310 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 310 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
311 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 311 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
312 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 312 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
313 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 313 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
314 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 314 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
315 device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; 315 device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
@@ -338,7 +338,7 @@ nv50_identify(struct nouveau_device *device)
338 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 338 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
339 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 339 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
340 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 340 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
341 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 341 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
342 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 342 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
343 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 343 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
344 device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; 344 device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
@@ -368,7 +368,7 @@ nv50_identify(struct nouveau_device *device)
368 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 368 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
369 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 369 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
370 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 370 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
371 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 371 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
372 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 372 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
373 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; 373 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
374 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 374 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
@@ -399,7 +399,7 @@ nv50_identify(struct nouveau_device *device)
399 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 399 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
400 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 400 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
401 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 401 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
402 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 402 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
403 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 403 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
404 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 404 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
405 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; 405 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
@@ -429,7 +429,7 @@ nv50_identify(struct nouveau_device *device)
429 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 429 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
430 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 430 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
431 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 431 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
432 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 432 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
433 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 433 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
434 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 434 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
435 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; 435 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
@@ -459,7 +459,7 @@ nv50_identify(struct nouveau_device *device)
459 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 459 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
460 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 460 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
461 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; 461 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
462 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; 462 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
463 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 463 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
464 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; 464 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
465 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; 465 device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index b241421e76a2..ae856f8bcc75 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -45,7 +45,7 @@
45#include <engine/device.h> 45#include <engine/device.h>
46#include <engine/dmaobj.h> 46#include <engine/dmaobj.h>
47#include <engine/fifo.h> 47#include <engine/fifo.h>
48#include <engine/software.h> 48#include <engine/sw.h>
49#include <engine/gr.h> 49#include <engine/gr.h>
50#include <engine/vp.h> 50#include <engine/vp.h>
51#include <engine/bsp.h> 51#include <engine/bsp.h>
@@ -82,7 +82,7 @@ nvc0_identify(struct nouveau_device *device)
82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
83 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; 83 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
84 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 84 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
85 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 85 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
86 device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass; 86 device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
87 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 87 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
88 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; 88 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -115,7 +115,7 @@ nvc0_identify(struct nouveau_device *device)
115 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 115 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; 116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
117 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 117 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
118 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 118 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
119 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; 119 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
120 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 120 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
121 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; 121 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -148,7 +148,7 @@ nvc0_identify(struct nouveau_device *device)
148 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 148 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
149 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; 149 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
150 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 150 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
151 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 151 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
152 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; 152 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
153 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 153 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
154 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; 154 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -180,7 +180,7 @@ nvc0_identify(struct nouveau_device *device)
180 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 180 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
181 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; 181 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
182 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 182 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
183 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 183 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
184 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; 184 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
185 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 185 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
186 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; 186 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -213,7 +213,7 @@ nvc0_identify(struct nouveau_device *device)
213 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 213 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
214 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; 214 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
215 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 215 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
216 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 216 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
217 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass; 217 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
218 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 218 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
219 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; 219 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -245,7 +245,7 @@ nvc0_identify(struct nouveau_device *device)
245 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 245 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
246 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; 246 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
247 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 247 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
248 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 248 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
249 device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass; 249 device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
250 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 250 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
251 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; 251 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -277,7 +277,7 @@ nvc0_identify(struct nouveau_device *device)
277 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 277 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
278 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; 278 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
279 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 279 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
280 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 280 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
281 device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass; 281 device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
282 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 282 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
283 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; 283 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -310,7 +310,7 @@ nvc0_identify(struct nouveau_device *device)
310 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 310 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
311 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 311 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
312 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 312 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
313 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 313 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
314 device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass; 314 device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
315 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 315 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
316 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; 316 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
@@ -340,7 +340,7 @@ nvc0_identify(struct nouveau_device *device)
340 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; 340 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
341 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 341 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
342 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 342 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
343 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 343 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
344 device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass; 344 device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
345 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; 345 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
346 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; 346 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index df975987b9ca..13934f2b9cbd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -45,7 +45,7 @@
45#include <engine/device.h> 45#include <engine/device.h>
46#include <engine/dmaobj.h> 46#include <engine/dmaobj.h>
47#include <engine/fifo.h> 47#include <engine/fifo.h>
48#include <engine/software.h> 48#include <engine/sw.h>
49#include <engine/gr.h> 49#include <engine/gr.h>
50#include <engine/disp.h> 50#include <engine/disp.h>
51#include <engine/ce.h> 51#include <engine/ce.h>
@@ -82,7 +82,7 @@ nve0_identify(struct nouveau_device *device)
82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
83 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 83 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
84 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 84 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
85 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 85 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
86 device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; 86 device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
87 device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; 87 device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
88 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; 88 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -116,7 +116,7 @@ nve0_identify(struct nouveau_device *device)
116 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 116 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
117 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 117 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
118 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 118 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
119 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 119 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
120 device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; 120 device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
121 device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; 121 device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
122 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; 122 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -150,7 +150,7 @@ nve0_identify(struct nouveau_device *device)
150 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 150 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
151 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 151 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
152 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 152 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
153 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 153 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
154 device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass; 154 device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
155 device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; 155 device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
156 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; 156 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -176,7 +176,7 @@ nve0_identify(struct nouveau_device *device)
176 device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; 176 device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
177 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 177 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
178 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; 178 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
179 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 179 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
180 device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; 180 device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
181 device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass; 181 device->oclass[NVDEV_ENGINE_CE2 ] = &nve0_ce2_oclass;
182 device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; 182 device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
@@ -206,7 +206,7 @@ nve0_identify(struct nouveau_device *device)
206 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 206 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
207 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 207 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
208 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 208 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
209 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 209 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
210 device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass; 210 device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
211 device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; 211 device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
212 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; 212 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -240,7 +240,7 @@ nve0_identify(struct nouveau_device *device)
240 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 240 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
241 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 241 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
242 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; 242 device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
243 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 243 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
244 device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; 244 device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
245 device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; 245 device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
246 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; 246 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -274,7 +274,7 @@ nve0_identify(struct nouveau_device *device)
274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
276 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; 276 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
277 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 277 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
278 device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; 278 device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
279 device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; 279 device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
280 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; 280 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
@@ -307,7 +307,7 @@ nve0_identify(struct nouveau_device *device)
307 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 307 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
308 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 308 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
309 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; 309 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
310 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; 310 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
311 device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass; 311 device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
312 device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; 312 device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
313 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass; 313 device->oclass[NVDEV_ENGINE_CE0 ] = &nve0_ce0_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
index e2ad0543fb31..26aaa2a201e5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
@@ -22,7 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <engine/software.h> 25#include <engine/sw.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <nvif/class.h> 28#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
index 672ded79b2a9..40b44f990990 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c
@@ -22,7 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <engine/software.h> 25#include <engine/sw.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <nvif/class.h> 28#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
index 13eff5e4ee51..547926678710 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c
@@ -22,7 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <engine/software.h> 25#include <engine/sw.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <nvif/class.h> 28#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
index 2bb7ac5cd0e6..c009be4fb11c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c
@@ -22,7 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <engine/software.h> 25#include <engine/sw.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <nvif/class.h> 28#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
index b32456c9494f..317fd1a22076 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c
@@ -22,7 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <engine/software.h> 25#include <engine/sw.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <nvif/class.h> 28#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
index 951d79f9b781..af9441338239 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c
@@ -22,7 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <engine/software.h> 25#include <engine/sw.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <nvif/class.h> 28#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
index 55debec7e68f..063cb4ad304c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c
@@ -22,7 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <engine/software.h> 25#include <engine/sw.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <nvif/class.h> 28#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
index 3e7e2d28744c..3fd9b462d51f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c
@@ -22,7 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <engine/software.h> 25#include <engine/sw.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <nvif/class.h> 28#include <nvif/class.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild
deleted file mode 100644
index e1332a15dc1b..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/Kbuild
+++ /dev/null
@@ -1,4 +0,0 @@
1nvkm-y += nvkm/engine/software/nv04.o
2nvkm-y += nvkm/engine/software/nv10.o
3nvkm-y += nvkm/engine/software/nv50.o
4nvkm-y += nvkm/engine/software/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h
deleted file mode 100644
index 41542e725b4b..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.h
+++ /dev/null
@@ -1,46 +0,0 @@
1#ifndef __NVKM_SW_NV50_H__
2#define __NVKM_SW_NV50_H__
3
4#include <engine/software.h>
5
6struct nv50_software_oclass {
7 struct nouveau_oclass base;
8 struct nouveau_oclass *cclass;
9 struct nouveau_oclass *sclass;
10};
11
12struct nv50_software_priv {
13 struct nouveau_software base;
14};
15
16int nv50_software_ctor(struct nouveau_object *, struct nouveau_object *,
17 struct nouveau_oclass *, void *, u32,
18 struct nouveau_object **);
19
20struct nv50_software_cclass {
21 struct nouveau_oclass base;
22 int (*vblank)(struct nvkm_notify *);
23};
24
25struct nv50_software_chan {
26 struct nouveau_software_chan base;
27 struct {
28 struct nvkm_notify notify[4];
29 u32 channel;
30 u32 ctxdma;
31 u64 offset;
32 u32 value;
33 } vblank;
34};
35
36int nv50_software_context_ctor(struct nouveau_object *,
37 struct nouveau_object *,
38 struct nouveau_oclass *, void *, u32,
39 struct nouveau_object **);
40void nv50_software_context_dtor(struct nouveau_object *);
41
42int nv50_software_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32);
43int nv50_software_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32);
44int nv50_software_mthd_flip(struct nouveau_object *, u32, void *, u32);
45
46#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
new file mode 100644
index 000000000000..b8d215900fce
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
@@ -0,0 +1,4 @@
1nvkm-y += nvkm/engine/sw/nv04.o
2nvkm-y += nvkm/engine/sw/nv10.o
3nvkm-y += nvkm/engine/sw/nv50.o
4nvkm-y += nvkm/engine/sw/nvc0.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
index 64df15c7f051..3d0e4bc76389 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
@@ -25,15 +25,15 @@
25#include <core/os.h> 25#include <core/os.h>
26#include <core/engctx.h> 26#include <core/engctx.h>
27 27
28#include <engine/software.h> 28#include <engine/sw.h>
29#include <engine/fifo.h> 29#include <engine/fifo.h>
30 30
31struct nv04_software_priv { 31struct nv04_sw_priv {
32 struct nouveau_software base; 32 struct nouveau_sw base;
33}; 33};
34 34
35struct nv04_software_chan { 35struct nv04_sw_chan {
36 struct nouveau_software_chan base; 36 struct nouveau_sw_chan base;
37}; 37};
38 38
39/******************************************************************************* 39/*******************************************************************************
@@ -41,7 +41,7 @@ struct nv04_software_chan {
41 ******************************************************************************/ 41 ******************************************************************************/
42 42
43static int 43static int
44nv04_software_set_ref(struct nouveau_object *object, u32 mthd, 44nv04_sw_set_ref(struct nouveau_object *object, u32 mthd,
45 void *data, u32 size) 45 void *data, u32 size)
46{ 46{
47 struct nouveau_object *channel = (void *)nv_engctx(object->parent); 47 struct nouveau_object *channel = (void *)nv_engctx(object->parent);
@@ -51,25 +51,25 @@ nv04_software_set_ref(struct nouveau_object *object, u32 mthd,
51} 51}
52 52
53static int 53static int
54nv04_software_flip(struct nouveau_object *object, u32 mthd, 54nv04_sw_flip(struct nouveau_object *object, u32 mthd,
55 void *args, u32 size) 55 void *args, u32 size)
56{ 56{
57 struct nv04_software_chan *chan = (void *)nv_engctx(object->parent); 57 struct nv04_sw_chan *chan = (void *)nv_engctx(object->parent);
58 if (chan->base.flip) 58 if (chan->base.flip)
59 return chan->base.flip(chan->base.flip_data); 59 return chan->base.flip(chan->base.flip_data);
60 return -EINVAL; 60 return -EINVAL;
61} 61}
62 62
63static struct nouveau_omthds 63static struct nouveau_omthds
64nv04_software_omthds[] = { 64nv04_sw_omthds[] = {
65 { 0x0150, 0x0150, nv04_software_set_ref }, 65 { 0x0150, 0x0150, nv04_sw_set_ref },
66 { 0x0500, 0x0500, nv04_software_flip }, 66 { 0x0500, 0x0500, nv04_sw_flip },
67 {} 67 {}
68}; 68};
69 69
70static struct nouveau_oclass 70static struct nouveau_oclass
71nv04_software_sclass[] = { 71nv04_sw_sclass[] = {
72 { 0x006e, &nouveau_object_ofuncs, nv04_software_omthds }, 72 { 0x006e, &nouveau_object_ofuncs, nv04_sw_omthds },
73 {} 73 {}
74}; 74};
75 75
@@ -78,15 +78,15 @@ nv04_software_sclass[] = {
78 ******************************************************************************/ 78 ******************************************************************************/
79 79
80static int 80static int
81nv04_software_context_ctor(struct nouveau_object *parent, 81nv04_sw_context_ctor(struct nouveau_object *parent,
82 struct nouveau_object *engine, 82 struct nouveau_object *engine,
83 struct nouveau_oclass *oclass, void *data, u32 size, 83 struct nouveau_oclass *oclass, void *data, u32 size,
84 struct nouveau_object **pobject) 84 struct nouveau_object **pobject)
85{ 85{
86 struct nv04_software_chan *chan; 86 struct nv04_sw_chan *chan;
87 int ret; 87 int ret;
88 88
89 ret = nouveau_software_context_create(parent, engine, oclass, &chan); 89 ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
90 *pobject = nv_object(chan); 90 *pobject = nv_object(chan);
91 if (ret) 91 if (ret)
92 return ret; 92 return ret;
@@ -95,13 +95,13 @@ nv04_software_context_ctor(struct nouveau_object *parent,
95} 95}
96 96
97static struct nouveau_oclass 97static struct nouveau_oclass
98nv04_software_cclass = { 98nv04_sw_cclass = {
99 .handle = NV_ENGCTX(SW, 0x04), 99 .handle = NV_ENGCTX(SW, 0x04),
100 .ofuncs = &(struct nouveau_ofuncs) { 100 .ofuncs = &(struct nouveau_ofuncs) {
101 .ctor = nv04_software_context_ctor, 101 .ctor = nv04_sw_context_ctor,
102 .dtor = _nouveau_software_context_dtor, 102 .dtor = _nouveau_sw_context_dtor,
103 .init = _nouveau_software_context_init, 103 .init = _nouveau_sw_context_init,
104 .fini = _nouveau_software_context_fini, 104 .fini = _nouveau_sw_context_fini,
105 }, 105 },
106}; 106};
107 107
@@ -110,37 +110,37 @@ nv04_software_cclass = {
110 ******************************************************************************/ 110 ******************************************************************************/
111 111
112void 112void
113nv04_software_intr(struct nouveau_subdev *subdev) 113nv04_sw_intr(struct nouveau_subdev *subdev)
114{ 114{
115 nv_mask(subdev, 0x000100, 0x80000000, 0x00000000); 115 nv_mask(subdev, 0x000100, 0x80000000, 0x00000000);
116} 116}
117 117
118static int 118static int
119nv04_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 119nv04_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
120 struct nouveau_oclass *oclass, void *data, u32 size, 120 struct nouveau_oclass *oclass, void *data, u32 size,
121 struct nouveau_object **pobject) 121 struct nouveau_object **pobject)
122{ 122{
123 struct nv04_software_priv *priv; 123 struct nv04_sw_priv *priv;
124 int ret; 124 int ret;
125 125
126 ret = nouveau_software_create(parent, engine, oclass, &priv); 126 ret = nouveau_sw_create(parent, engine, oclass, &priv);
127 *pobject = nv_object(priv); 127 *pobject = nv_object(priv);
128 if (ret) 128 if (ret)
129 return ret; 129 return ret;
130 130
131 nv_engine(priv)->cclass = &nv04_software_cclass; 131 nv_engine(priv)->cclass = &nv04_sw_cclass;
132 nv_engine(priv)->sclass = nv04_software_sclass; 132 nv_engine(priv)->sclass = nv04_sw_sclass;
133 nv_subdev(priv)->intr = nv04_software_intr; 133 nv_subdev(priv)->intr = nv04_sw_intr;
134 return 0; 134 return 0;
135} 135}
136 136
137struct nouveau_oclass * 137struct nouveau_oclass *
138nv04_software_oclass = &(struct nouveau_oclass) { 138nv04_sw_oclass = &(struct nouveau_oclass) {
139 .handle = NV_ENGINE(SW, 0x04), 139 .handle = NV_ENGINE(SW, 0x04),
140 .ofuncs = &(struct nouveau_ofuncs) { 140 .ofuncs = &(struct nouveau_ofuncs) {
141 .ctor = nv04_software_ctor, 141 .ctor = nv04_sw_ctor,
142 .dtor = _nouveau_software_dtor, 142 .dtor = _nouveau_sw_dtor,
143 .init = _nouveau_software_init, 143 .init = _nouveau_sw_init,
144 .fini = _nouveau_software_fini, 144 .fini = _nouveau_sw_fini,
145 }, 145 },
146}; 146};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
index f54a2253deca..12775cdbde70 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
@@ -25,14 +25,14 @@
25#include <core/os.h> 25#include <core/os.h>
26#include <core/engctx.h> 26#include <core/engctx.h>
27 27
28#include <engine/software.h> 28#include <engine/sw.h>
29 29
30struct nv10_software_priv { 30struct nv10_sw_priv {
31 struct nouveau_software base; 31 struct nouveau_sw base;
32}; 32};
33 33
34struct nv10_software_chan { 34struct nv10_sw_chan {
35 struct nouveau_software_chan base; 35 struct nouveau_sw_chan base;
36}; 36};
37 37
38/******************************************************************************* 38/*******************************************************************************
@@ -40,24 +40,24 @@ struct nv10_software_chan {
40 ******************************************************************************/ 40 ******************************************************************************/
41 41
42static int 42static int
43nv10_software_flip(struct nouveau_object *object, u32 mthd, 43nv10_sw_flip(struct nouveau_object *object, u32 mthd,
44 void *args, u32 size) 44 void *args, u32 size)
45{ 45{
46 struct nv10_software_chan *chan = (void *)nv_engctx(object->parent); 46 struct nv10_sw_chan *chan = (void *)nv_engctx(object->parent);
47 if (chan->base.flip) 47 if (chan->base.flip)
48 return chan->base.flip(chan->base.flip_data); 48 return chan->base.flip(chan->base.flip_data);
49 return -EINVAL; 49 return -EINVAL;
50} 50}
51 51
52static struct nouveau_omthds 52static struct nouveau_omthds
53nv10_software_omthds[] = { 53nv10_sw_omthds[] = {
54 { 0x0500, 0x0500, nv10_software_flip }, 54 { 0x0500, 0x0500, nv10_sw_flip },
55 {} 55 {}
56}; 56};
57 57
58static struct nouveau_oclass 58static struct nouveau_oclass
59nv10_software_sclass[] = { 59nv10_sw_sclass[] = {
60 { 0x016e, &nouveau_object_ofuncs, nv10_software_omthds }, 60 { 0x016e, &nouveau_object_ofuncs, nv10_sw_omthds },
61 {} 61 {}
62}; 62};
63 63
@@ -66,15 +66,15 @@ nv10_software_sclass[] = {
66 ******************************************************************************/ 66 ******************************************************************************/
67 67
68static int 68static int
69nv10_software_context_ctor(struct nouveau_object *parent, 69nv10_sw_context_ctor(struct nouveau_object *parent,
70 struct nouveau_object *engine, 70 struct nouveau_object *engine,
71 struct nouveau_oclass *oclass, void *data, u32 size, 71 struct nouveau_oclass *oclass, void *data, u32 size,
72 struct nouveau_object **pobject) 72 struct nouveau_object **pobject)
73{ 73{
74 struct nv10_software_chan *chan; 74 struct nv10_sw_chan *chan;
75 int ret; 75 int ret;
76 76
77 ret = nouveau_software_context_create(parent, engine, oclass, &chan); 77 ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
78 *pobject = nv_object(chan); 78 *pobject = nv_object(chan);
79 if (ret) 79 if (ret)
80 return ret; 80 return ret;
@@ -83,13 +83,13 @@ nv10_software_context_ctor(struct nouveau_object *parent,
83} 83}
84 84
85static struct nouveau_oclass 85static struct nouveau_oclass
86nv10_software_cclass = { 86nv10_sw_cclass = {
87 .handle = NV_ENGCTX(SW, 0x04), 87 .handle = NV_ENGCTX(SW, 0x04),
88 .ofuncs = &(struct nouveau_ofuncs) { 88 .ofuncs = &(struct nouveau_ofuncs) {
89 .ctor = nv10_software_context_ctor, 89 .ctor = nv10_sw_context_ctor,
90 .dtor = _nouveau_software_context_dtor, 90 .dtor = _nouveau_sw_context_dtor,
91 .init = _nouveau_software_context_init, 91 .init = _nouveau_sw_context_init,
92 .fini = _nouveau_software_context_fini, 92 .fini = _nouveau_sw_context_fini,
93 }, 93 },
94}; 94};
95 95
@@ -98,31 +98,31 @@ nv10_software_cclass = {
98 ******************************************************************************/ 98 ******************************************************************************/
99 99
100static int 100static int
101nv10_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 101nv10_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
102 struct nouveau_oclass *oclass, void *data, u32 size, 102 struct nouveau_oclass *oclass, void *data, u32 size,
103 struct nouveau_object **pobject) 103 struct nouveau_object **pobject)
104{ 104{
105 struct nv10_software_priv *priv; 105 struct nv10_sw_priv *priv;
106 int ret; 106 int ret;
107 107
108 ret = nouveau_software_create(parent, engine, oclass, &priv); 108 ret = nouveau_sw_create(parent, engine, oclass, &priv);
109 *pobject = nv_object(priv); 109 *pobject = nv_object(priv);
110 if (ret) 110 if (ret)
111 return ret; 111 return ret;
112 112
113 nv_engine(priv)->cclass = &nv10_software_cclass; 113 nv_engine(priv)->cclass = &nv10_sw_cclass;
114 nv_engine(priv)->sclass = nv10_software_sclass; 114 nv_engine(priv)->sclass = nv10_sw_sclass;
115 nv_subdev(priv)->intr = nv04_software_intr; 115 nv_subdev(priv)->intr = nv04_sw_intr;
116 return 0; 116 return 0;
117} 117}
118 118
119struct nouveau_oclass * 119struct nouveau_oclass *
120nv10_software_oclass = &(struct nouveau_oclass) { 120nv10_sw_oclass = &(struct nouveau_oclass) {
121 .handle = NV_ENGINE(SW, 0x10), 121 .handle = NV_ENGINE(SW, 0x10),
122 .ofuncs = &(struct nouveau_ofuncs) { 122 .ofuncs = &(struct nouveau_ofuncs) {
123 .ctor = nv10_software_ctor, 123 .ctor = nv10_sw_ctor,
124 .dtor = _nouveau_software_dtor, 124 .dtor = _nouveau_sw_dtor,
125 .init = _nouveau_software_init, 125 .init = _nouveau_sw_init,
126 .fini = _nouveau_software_fini, 126 .fini = _nouveau_sw_fini,
127 }, 127 },
128}; 128};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
index a0fec205f9db..a214a4debcc4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
@@ -41,10 +41,10 @@
41 ******************************************************************************/ 41 ******************************************************************************/
42 42
43static int 43static int
44nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd, 44nv50_sw_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
45 void *args, u32 size) 45 void *args, u32 size)
46{ 46{
47 struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); 47 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
48 struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent; 48 struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent;
49 struct nouveau_handle *handle; 49 struct nouveau_handle *handle;
50 int ret = -EINVAL; 50 int ret = -EINVAL;
@@ -63,28 +63,28 @@ nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
63} 63}
64 64
65static int 65static int
66nv50_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd, 66nv50_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
67 void *args, u32 size) 67 void *args, u32 size)
68{ 68{
69 struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); 69 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
70 chan->vblank.offset = *(u32 *)args; 70 chan->vblank.offset = *(u32 *)args;
71 return 0; 71 return 0;
72} 72}
73 73
74int 74int
75nv50_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd, 75nv50_sw_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
76 void *args, u32 size) 76 void *args, u32 size)
77{ 77{
78 struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); 78 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
79 chan->vblank.value = *(u32 *)args; 79 chan->vblank.value = *(u32 *)args;
80 return 0; 80 return 0;
81} 81}
82 82
83int 83int
84nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd, 84nv50_sw_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
85 void *args, u32 size) 85 void *args, u32 size)
86{ 86{
87 struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); 87 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
88 u32 head = *(u32 *)args; 88 u32 head = *(u32 *)args;
89 if (head >= nouveau_disp(chan)->vblank.index_nr) 89 if (head >= nouveau_disp(chan)->vblank.index_nr)
90 return -EINVAL; 90 return -EINVAL;
@@ -94,28 +94,28 @@ nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
94} 94}
95 95
96int 96int
97nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd, 97nv50_sw_mthd_flip(struct nouveau_object *object, u32 mthd,
98 void *args, u32 size) 98 void *args, u32 size)
99{ 99{
100 struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); 100 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
101 if (chan->base.flip) 101 if (chan->base.flip)
102 return chan->base.flip(chan->base.flip_data); 102 return chan->base.flip(chan->base.flip_data);
103 return -EINVAL; 103 return -EINVAL;
104} 104}
105 105
106static struct nouveau_omthds 106static struct nouveau_omthds
107nv50_software_omthds[] = { 107nv50_sw_omthds[] = {
108 { 0x018c, 0x018c, nv50_software_mthd_dma_vblsem }, 108 { 0x018c, 0x018c, nv50_sw_mthd_dma_vblsem },
109 { 0x0400, 0x0400, nv50_software_mthd_vblsem_offset }, 109 { 0x0400, 0x0400, nv50_sw_mthd_vblsem_offset },
110 { 0x0404, 0x0404, nv50_software_mthd_vblsem_value }, 110 { 0x0404, 0x0404, nv50_sw_mthd_vblsem_value },
111 { 0x0408, 0x0408, nv50_software_mthd_vblsem_release }, 111 { 0x0408, 0x0408, nv50_sw_mthd_vblsem_release },
112 { 0x0500, 0x0500, nv50_software_mthd_flip }, 112 { 0x0500, 0x0500, nv50_sw_mthd_flip },
113 {} 113 {}
114}; 114};
115 115
116static struct nouveau_oclass 116static struct nouveau_oclass
117nv50_software_sclass[] = { 117nv50_sw_sclass[] = {
118 { 0x506e, &nouveau_object_ofuncs, nv50_software_omthds }, 118 { 0x506e, &nouveau_object_ofuncs, nv50_sw_omthds },
119 {} 119 {}
120}; 120};
121 121
@@ -124,11 +124,11 @@ nv50_software_sclass[] = {
124 ******************************************************************************/ 124 ******************************************************************************/
125 125
126static int 126static int
127nv50_software_vblsem_release(struct nvkm_notify *notify) 127nv50_sw_vblsem_release(struct nvkm_notify *notify)
128{ 128{
129 struct nv50_software_chan *chan = 129 struct nv50_sw_chan *chan =
130 container_of(notify, typeof(*chan), vblank.notify[notify->index]); 130 container_of(notify, typeof(*chan), vblank.notify[notify->index]);
131 struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; 131 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
132 struct nouveau_bar *bar = nouveau_bar(priv); 132 struct nouveau_bar *bar = nouveau_bar(priv);
133 133
134 nv_wr32(priv, 0x001704, chan->vblank.channel); 134 nv_wr32(priv, 0x001704, chan->vblank.channel);
@@ -147,29 +147,29 @@ nv50_software_vblsem_release(struct nvkm_notify *notify)
147} 147}
148 148
149void 149void
150nv50_software_context_dtor(struct nouveau_object *object) 150nv50_sw_context_dtor(struct nouveau_object *object)
151{ 151{
152 struct nv50_software_chan *chan = (void *)object; 152 struct nv50_sw_chan *chan = (void *)object;
153 int i; 153 int i;
154 154
155 for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++) 155 for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++)
156 nvkm_notify_fini(&chan->vblank.notify[i]); 156 nvkm_notify_fini(&chan->vblank.notify[i]);
157 157
158 nouveau_software_context_destroy(&chan->base); 158 nouveau_sw_context_destroy(&chan->base);
159} 159}
160 160
161int 161int
162nv50_software_context_ctor(struct nouveau_object *parent, 162nv50_sw_context_ctor(struct nouveau_object *parent,
163 struct nouveau_object *engine, 163 struct nouveau_object *engine,
164 struct nouveau_oclass *oclass, void *data, u32 size, 164 struct nouveau_oclass *oclass, void *data, u32 size,
165 struct nouveau_object **pobject) 165 struct nouveau_object **pobject)
166{ 166{
167 struct nouveau_disp *pdisp = nouveau_disp(parent); 167 struct nouveau_disp *pdisp = nouveau_disp(parent);
168 struct nv50_software_cclass *pclass = (void *)oclass; 168 struct nv50_sw_cclass *pclass = (void *)oclass;
169 struct nv50_software_chan *chan; 169 struct nv50_sw_chan *chan;
170 int ret, i; 170 int ret, i;
171 171
172 ret = nouveau_software_context_create(parent, engine, oclass, &chan); 172 ret = nouveau_sw_context_create(parent, engine, oclass, &chan);
173 *pobject = nv_object(chan); 173 *pobject = nv_object(chan);
174 if (ret) 174 if (ret)
175 return ret; 175 return ret;
@@ -191,16 +191,16 @@ nv50_software_context_ctor(struct nouveau_object *parent,
191 return 0; 191 return 0;
192} 192}
193 193
194static struct nv50_software_cclass 194static struct nv50_sw_cclass
195nv50_software_cclass = { 195nv50_sw_cclass = {
196 .base.handle = NV_ENGCTX(SW, 0x50), 196 .base.handle = NV_ENGCTX(SW, 0x50),
197 .base.ofuncs = &(struct nouveau_ofuncs) { 197 .base.ofuncs = &(struct nouveau_ofuncs) {
198 .ctor = nv50_software_context_ctor, 198 .ctor = nv50_sw_context_ctor,
199 .dtor = nv50_software_context_dtor, 199 .dtor = nv50_sw_context_dtor,
200 .init = _nouveau_software_context_init, 200 .init = _nouveau_sw_context_init,
201 .fini = _nouveau_software_context_fini, 201 .fini = _nouveau_sw_context_fini,
202 }, 202 },
203 .vblank = nv50_software_vblsem_release, 203 .vblank = nv50_sw_vblsem_release,
204}; 204};
205 205
206/******************************************************************************* 206/*******************************************************************************
@@ -208,34 +208,34 @@ nv50_software_cclass = {
208 ******************************************************************************/ 208 ******************************************************************************/
209 209
210int 210int
211nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 211nv50_sw_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
212 struct nouveau_oclass *oclass, void *data, u32 size, 212 struct nouveau_oclass *oclass, void *data, u32 size,
213 struct nouveau_object **pobject) 213 struct nouveau_object **pobject)
214{ 214{
215 struct nv50_software_oclass *pclass = (void *)oclass; 215 struct nv50_sw_oclass *pclass = (void *)oclass;
216 struct nv50_software_priv *priv; 216 struct nv50_sw_priv *priv;
217 int ret; 217 int ret;
218 218
219 ret = nouveau_software_create(parent, engine, oclass, &priv); 219 ret = nouveau_sw_create(parent, engine, oclass, &priv);
220 *pobject = nv_object(priv); 220 *pobject = nv_object(priv);
221 if (ret) 221 if (ret)
222 return ret; 222 return ret;
223 223
224 nv_engine(priv)->cclass = pclass->cclass; 224 nv_engine(priv)->cclass = pclass->cclass;
225 nv_engine(priv)->sclass = pclass->sclass; 225 nv_engine(priv)->sclass = pclass->sclass;
226 nv_subdev(priv)->intr = nv04_software_intr; 226 nv_subdev(priv)->intr = nv04_sw_intr;
227 return 0; 227 return 0;
228} 228}
229 229
230struct nouveau_oclass * 230struct nouveau_oclass *
231nv50_software_oclass = &(struct nv50_software_oclass) { 231nv50_sw_oclass = &(struct nv50_sw_oclass) {
232 .base.handle = NV_ENGINE(SW, 0x50), 232 .base.handle = NV_ENGINE(SW, 0x50),
233 .base.ofuncs = &(struct nouveau_ofuncs) { 233 .base.ofuncs = &(struct nouveau_ofuncs) {
234 .ctor = nv50_software_ctor, 234 .ctor = nv50_sw_ctor,
235 .dtor = _nouveau_software_dtor, 235 .dtor = _nouveau_sw_dtor,
236 .init = _nouveau_software_init, 236 .init = _nouveau_sw_init,
237 .fini = _nouveau_software_fini, 237 .fini = _nouveau_sw_fini,
238 }, 238 },
239 .cclass = &nv50_software_cclass.base, 239 .cclass = &nv50_sw_cclass.base,
240 .sclass = nv50_software_sclass, 240 .sclass = nv50_sw_sclass,
241}.base; 241}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
new file mode 100644
index 000000000000..618e41fa36d0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
@@ -0,0 +1,46 @@
1#ifndef __NVKM_SW_NV50_H__
2#define __NVKM_SW_NV50_H__
3
4#include <engine/sw.h>
5
6struct nv50_sw_oclass {
7 struct nouveau_oclass base;
8 struct nouveau_oclass *cclass;
9 struct nouveau_oclass *sclass;
10};
11
12struct nv50_sw_priv {
13 struct nouveau_sw base;
14};
15
16int nv50_sw_ctor(struct nouveau_object *, struct nouveau_object *,
17 struct nouveau_oclass *, void *, u32,
18 struct nouveau_object **);
19
20struct nv50_sw_cclass {
21 struct nouveau_oclass base;
22 int (*vblank)(struct nvkm_notify *);
23};
24
25struct nv50_sw_chan {
26 struct nouveau_sw_chan base;
27 struct {
28 struct nvkm_notify notify[4];
29 u32 channel;
30 u32 ctxdma;
31 u64 offset;
32 u32 value;
33 } vblank;
34};
35
36int nv50_sw_context_ctor(struct nouveau_object *,
37 struct nouveau_object *,
38 struct nouveau_oclass *, void *, u32,
39 struct nouveau_object **);
40void nv50_sw_context_dtor(struct nouveau_object *);
41
42int nv50_sw_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32);
43int nv50_sw_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32);
44int nv50_sw_mthd_flip(struct nouveau_object *, u32, void *, u32);
45
46#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c
index 6af370d3a06d..dcb056eae471 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/software/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nvc0.c
@@ -28,7 +28,7 @@
28 28
29#include <subdev/bar.h> 29#include <subdev/bar.h>
30 30
31#include <engine/software.h> 31#include <engine/sw.h>
32#include <engine/disp.h> 32#include <engine/disp.h>
33 33
34#include "nv50.h" 34#include "nv50.h"
@@ -38,10 +38,10 @@
38 ******************************************************************************/ 38 ******************************************************************************/
39 39
40static int 40static int
41nvc0_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd, 41nvc0_sw_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
42 void *args, u32 size) 42 void *args, u32 size)
43{ 43{
44 struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); 44 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
45 u64 data = *(u32 *)args; 45 u64 data = *(u32 *)args;
46 if (mthd == 0x0400) { 46 if (mthd == 0x0400) {
47 chan->vblank.offset &= 0x00ffffffffULL; 47 chan->vblank.offset &= 0x00ffffffffULL;
@@ -54,11 +54,11 @@ nvc0_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
54} 54}
55 55
56static int 56static int
57nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd, 57nvc0_sw_mthd_mp_control(struct nouveau_object *object, u32 mthd,
58 void *args, u32 size) 58 void *args, u32 size)
59{ 59{
60 struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); 60 struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
61 struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; 61 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
62 u32 data = *(u32 *)args; 62 u32 data = *(u32 *)args;
63 63
64 switch (mthd) { 64 switch (mthd) {
@@ -80,21 +80,21 @@ nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd,
80} 80}
81 81
82static struct nouveau_omthds 82static struct nouveau_omthds
83nvc0_software_omthds[] = { 83nvc0_sw_omthds[] = {
84 { 0x0400, 0x0400, nvc0_software_mthd_vblsem_offset }, 84 { 0x0400, 0x0400, nvc0_sw_mthd_vblsem_offset },
85 { 0x0404, 0x0404, nvc0_software_mthd_vblsem_offset }, 85 { 0x0404, 0x0404, nvc0_sw_mthd_vblsem_offset },
86 { 0x0408, 0x0408, nv50_software_mthd_vblsem_value }, 86 { 0x0408, 0x0408, nv50_sw_mthd_vblsem_value },
87 { 0x040c, 0x040c, nv50_software_mthd_vblsem_release }, 87 { 0x040c, 0x040c, nv50_sw_mthd_vblsem_release },
88 { 0x0500, 0x0500, nv50_software_mthd_flip }, 88 { 0x0500, 0x0500, nv50_sw_mthd_flip },
89 { 0x0600, 0x0600, nvc0_software_mthd_mp_control }, 89 { 0x0600, 0x0600, nvc0_sw_mthd_mp_control },
90 { 0x0644, 0x0644, nvc0_software_mthd_mp_control }, 90 { 0x0644, 0x0644, nvc0_sw_mthd_mp_control },
91 { 0x06ac, 0x06ac, nvc0_software_mthd_mp_control }, 91 { 0x06ac, 0x06ac, nvc0_sw_mthd_mp_control },
92 {} 92 {}
93}; 93};
94 94
95static struct nouveau_oclass 95static struct nouveau_oclass
96nvc0_software_sclass[] = { 96nvc0_sw_sclass[] = {
97 { 0x906e, &nouveau_object_ofuncs, nvc0_software_omthds }, 97 { 0x906e, &nouveau_object_ofuncs, nvc0_sw_omthds },
98 {} 98 {}
99}; 99};
100 100
@@ -103,11 +103,11 @@ nvc0_software_sclass[] = {
103 ******************************************************************************/ 103 ******************************************************************************/
104 104
105static int 105static int
106nvc0_software_vblsem_release(struct nvkm_notify *notify) 106nvc0_sw_vblsem_release(struct nvkm_notify *notify)
107{ 107{
108 struct nv50_software_chan *chan = 108 struct nv50_sw_chan *chan =
109 container_of(notify, typeof(*chan), vblank.notify[notify->index]); 109 container_of(notify, typeof(*chan), vblank.notify[notify->index]);
110 struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; 110 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
111 struct nouveau_bar *bar = nouveau_bar(priv); 111 struct nouveau_bar *bar = nouveau_bar(priv);
112 112
113 nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel); 113 nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
@@ -119,16 +119,16 @@ nvc0_software_vblsem_release(struct nvkm_notify *notify)
119 return NVKM_NOTIFY_DROP; 119 return NVKM_NOTIFY_DROP;
120} 120}
121 121
122static struct nv50_software_cclass 122static struct nv50_sw_cclass
123nvc0_software_cclass = { 123nvc0_sw_cclass = {
124 .base.handle = NV_ENGCTX(SW, 0xc0), 124 .base.handle = NV_ENGCTX(SW, 0xc0),
125 .base.ofuncs = &(struct nouveau_ofuncs) { 125 .base.ofuncs = &(struct nouveau_ofuncs) {
126 .ctor = nv50_software_context_ctor, 126 .ctor = nv50_sw_context_ctor,
127 .dtor = nv50_software_context_dtor, 127 .dtor = nv50_sw_context_dtor,
128 .init = _nouveau_software_context_init, 128 .init = _nouveau_sw_context_init,
129 .fini = _nouveau_software_context_fini, 129 .fini = _nouveau_sw_context_fini,
130 }, 130 },
131 .vblank = nvc0_software_vblsem_release, 131 .vblank = nvc0_sw_vblsem_release,
132}; 132};
133 133
134/******************************************************************************* 134/*******************************************************************************
@@ -136,14 +136,14 @@ nvc0_software_cclass = {
136 ******************************************************************************/ 136 ******************************************************************************/
137 137
138struct nouveau_oclass * 138struct nouveau_oclass *
139nvc0_software_oclass = &(struct nv50_software_oclass) { 139nvc0_sw_oclass = &(struct nv50_sw_oclass) {
140 .base.handle = NV_ENGINE(SW, 0xc0), 140 .base.handle = NV_ENGINE(SW, 0xc0),
141 .base.ofuncs = &(struct nouveau_ofuncs) { 141 .base.ofuncs = &(struct nouveau_ofuncs) {
142 .ctor = nv50_software_ctor, 142 .ctor = nv50_sw_ctor,
143 .dtor = _nouveau_software_dtor, 143 .dtor = _nouveau_sw_dtor,
144 .init = _nouveau_software_init, 144 .init = _nouveau_sw_init,
145 .fini = _nouveau_software_fini, 145 .fini = _nouveau_sw_fini,
146 }, 146 },
147 .cclass = &nvc0_software_cclass.base, 147 .cclass = &nvc0_sw_cclass.base,
148 .sclass = nvc0_software_sclass, 148 .sclass = nvc0_sw_sclass,
149}.base; 149}.base;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 19:06:21 -0500