diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index a03420ca82b1..59cefdd46897 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | |||
@@ -38,7 +38,7 @@ | |||
38 | #include <engine/device.h> | 38 | #include <engine/device.h> |
39 | #include <engine/dmaobj.h> | 39 | #include <engine/dmaobj.h> |
40 | #include <engine/fifo.h> | 40 | #include <engine/fifo.h> |
41 | #include <engine/software.h> | 41 | #include <engine/sw.h> |
42 | #include <engine/gr.h> | 42 | #include <engine/gr.h> |
43 | #include <engine/disp.h> | 43 | #include <engine/disp.h> |
44 | 44 | ||
@@ -61,7 +61,7 @@ nv20_identify(struct nouveau_device *device) | |||
61 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; | 61 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; |
62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; | 62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
64 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; | 64 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
65 | device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; | 65 | device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; |
66 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; | 66 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
67 | break; | 67 | break; |
@@ -80,7 +80,7 @@ nv20_identify(struct nouveau_device *device) | |||
80 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; | 80 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; |
81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; | 81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
83 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; | 83 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
84 | device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; | 84 | device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; |
85 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; | 85 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
86 | break; | 86 | break; |
@@ -99,7 +99,7 @@ nv20_identify(struct nouveau_device *device) | |||
99 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; | 99 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; |
100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; | 100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
102 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; | 102 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
103 | device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; | 103 | device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; |
104 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; | 104 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
105 | break; | 105 | break; |
@@ -118,7 +118,7 @@ nv20_identify(struct nouveau_device *device) | |||
118 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; | 118 | device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; |
119 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; | 119 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; |
120 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 120 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
121 | device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; | 121 | device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; |
122 | device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; | 122 | device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; |
123 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; | 123 | device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; |
124 | break; | 124 | break; |