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authorAlan Cox <alan@linux.intel.com>2012-03-08 11:00:31 -0500
committerDave Airlie <airlied@redhat.com>2012-03-10 08:05:28 -0500
commit648a8e342c5a754bdc62f003d3af90507c1abfde (patch)
tree95dd76398a23ac3d6a662c7f71445aa22a89302a /drivers
parent933315acb6e223d4da36cb0b95d18dcfa6323658 (diff)
gma500: now move the Oaktrail save state into its own structure
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/gma500/cdv_intel_display.c27
-rw-r--r--drivers/gpu/drm/gma500/cdv_intel_lvds.c6
-rw-r--r--drivers/gpu/drm/gma500/oaktrail_device.c204
-rw-r--r--drivers/gpu/drm/gma500/oaktrail_hdmi.c72
-rw-r--r--drivers/gpu/drm/gma500/oaktrail_lvds.c2
-rw-r--r--drivers/gpu/drm/gma500/power.c8
-rw-r--r--drivers/gpu/drm/gma500/psb_device.c34
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.h226
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_display.c27
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_lvds.c12
10 files changed, 322 insertions, 296 deletions
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c
index 18d11525095e..dc9e246768da 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -968,7 +968,7 @@ void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
968 gma_power_end(dev); 968 gma_power_end(dev);
969 } else { 969 } else {
970 for (i = 0; i < 256; i++) { 970 for (i = 0; i < 256; i++) {
971 dev_priv->save_palette_a[i] = 971 dev_priv->regs.save_palette_a[i] =
972 ((psb_intel_crtc->lut_r[i] + 972 ((psb_intel_crtc->lut_r[i] +
973 psb_intel_crtc->lut_adj[i]) << 16) | 973 psb_intel_crtc->lut_adj[i]) << 16) |
974 ((psb_intel_crtc->lut_g[i] + 974 ((psb_intel_crtc->lut_g[i] +
@@ -1338,18 +1338,19 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev,
1338 gma_power_end(dev); 1338 gma_power_end(dev);
1339 } else { 1339 } else {
1340 dpll = (pipe == 0) ? 1340 dpll = (pipe == 0) ?
1341 dev_priv->saveDPLL_A : dev_priv->saveDPLL_B; 1341 dev_priv->regs.saveDPLL_A : dev_priv->regs.saveDPLL_B;
1342 1342
1343 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1343 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1344 fp = (pipe == 0) ? 1344 fp = (pipe == 0) ?
1345 dev_priv->saveFPA0 : 1345 dev_priv->regs.saveFPA0 :
1346 dev_priv->saveFPB0; 1346 dev_priv->regs.saveFPB0;
1347 else 1347 else
1348 fp = (pipe == 0) ? 1348 fp = (pipe == 0) ?
1349 dev_priv->saveFPA1 : 1349 dev_priv->regs.saveFPA1 :
1350 dev_priv->saveFPB1; 1350 dev_priv->regs.saveFPB1;
1351 1351
1352 is_lvds = (pipe == 1) && (dev_priv->saveLVDS & LVDS_PORT_EN); 1352 is_lvds = (pipe == 1) &&
1353 (dev_priv->regs.saveLVDS & LVDS_PORT_EN);
1353 } 1354 }
1354 1355
1355 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 1356 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
@@ -1419,13 +1420,17 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
1419 gma_power_end(dev); 1420 gma_power_end(dev);
1420 } else { 1421 } else {
1421 htot = (pipe == 0) ? 1422 htot = (pipe == 0) ?
1422 dev_priv->saveHTOTAL_A : dev_priv->saveHTOTAL_B; 1423 dev_priv->regs.saveHTOTAL_A :
1424 dev_priv->regs.saveHTOTAL_B;
1423 hsync = (pipe == 0) ? 1425 hsync = (pipe == 0) ?
1424 dev_priv->saveHSYNC_A : dev_priv->saveHSYNC_B; 1426 dev_priv->regs.saveHSYNC_A :
1427 dev_priv->regs.saveHSYNC_B;
1425 vtot = (pipe == 0) ? 1428 vtot = (pipe == 0) ?
1426 dev_priv->saveVTOTAL_A : dev_priv->saveVTOTAL_B; 1429 dev_priv->regs.saveVTOTAL_A :
1430 dev_priv->regs.saveVTOTAL_B;
1427 vsync = (pipe == 0) ? 1431 vsync = (pipe == 0) ?
1428 dev_priv->saveVSYNC_A : dev_priv->saveVSYNC_B; 1432 dev_priv->regs.saveVSYNC_A :
1433 dev_priv->regs.saveVSYNC_B;
1429 } 1434 }
1430 1435
1431 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 1436 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
diff --git a/drivers/gpu/drm/gma500/cdv_intel_lvds.c b/drivers/gpu/drm/gma500/cdv_intel_lvds.c
index 50e744be9852..79b47d2748f3 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_lvds.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_lvds.c
@@ -78,7 +78,7 @@ static u32 cdv_intel_lvds_get_max_backlight(struct drm_device *dev)
78 78
79 gma_power_end(dev); 79 gma_power_end(dev);
80 } else 80 } else
81 retval = ((dev_priv->saveBLC_PWM_CTL & 81 retval = ((dev_priv->regs.saveBLC_PWM_CTL &
82 BACKLIGHT_MODULATION_FREQ_MASK) >> 82 BACKLIGHT_MODULATION_FREQ_MASK) >>
83 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2; 83 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
84 84
@@ -184,9 +184,9 @@ static void cdv_intel_lvds_set_backlight(struct drm_device *dev, int level)
184 (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); 184 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
185 gma_power_end(dev); 185 gma_power_end(dev);
186 } else { 186 } else {
187 blc_pwm_ctl = dev_priv->saveBLC_PWM_CTL & 187 blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL &
188 ~BACKLIGHT_DUTY_CYCLE_MASK; 188 ~BACKLIGHT_DUTY_CYCLE_MASK;
189 dev_priv->saveBLC_PWM_CTL = (blc_pwm_ctl | 189 dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |
190 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)); 190 (level << BACKLIGHT_DUTY_CYCLE_SHIFT));
191 } 191 }
192} 192}
diff --git a/drivers/gpu/drm/gma500/oaktrail_device.c b/drivers/gpu/drm/gma500/oaktrail_device.c
index 63aea2f010d9..08dcdc29d2eb 100644
--- a/drivers/gpu/drm/gma500/oaktrail_device.c
+++ b/drivers/gpu/drm/gma500/oaktrail_device.c
@@ -190,81 +190,82 @@ static void oaktrail_init_pm(struct drm_device *dev)
190static int oaktrail_save_display_registers(struct drm_device *dev) 190static int oaktrail_save_display_registers(struct drm_device *dev)
191{ 191{
192 struct drm_psb_private *dev_priv = dev->dev_private; 192 struct drm_psb_private *dev_priv = dev->dev_private;
193 struct psb_state *regs = &dev_priv->regs;
193 int i; 194 int i;
194 u32 pp_stat; 195 u32 pp_stat;
195 196
196 /* Display arbitration control + watermarks */ 197 /* Display arbitration control + watermarks */
197 dev_priv->saveDSPARB = PSB_RVDC32(DSPARB); 198 regs->saveDSPARB = PSB_RVDC32(DSPARB);
198 dev_priv->saveDSPFW1 = PSB_RVDC32(DSPFW1); 199 regs->saveDSPFW1 = PSB_RVDC32(DSPFW1);
199 dev_priv->saveDSPFW2 = PSB_RVDC32(DSPFW2); 200 regs->saveDSPFW2 = PSB_RVDC32(DSPFW2);
200 dev_priv->saveDSPFW3 = PSB_RVDC32(DSPFW3); 201 regs->saveDSPFW3 = PSB_RVDC32(DSPFW3);
201 dev_priv->saveDSPFW4 = PSB_RVDC32(DSPFW4); 202 regs->saveDSPFW4 = PSB_RVDC32(DSPFW4);
202 dev_priv->saveDSPFW5 = PSB_RVDC32(DSPFW5); 203 regs->saveDSPFW5 = PSB_RVDC32(DSPFW5);
203 dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6); 204 regs->saveDSPFW6 = PSB_RVDC32(DSPFW6);
204 dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); 205 regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
205 206
206 /* Pipe & plane A info */ 207 /* Pipe & plane A info */
207 dev_priv->savePIPEACONF = PSB_RVDC32(PIPEACONF); 208 regs->savePIPEACONF = PSB_RVDC32(PIPEACONF);
208 dev_priv->savePIPEASRC = PSB_RVDC32(PIPEASRC); 209 regs->savePIPEASRC = PSB_RVDC32(PIPEASRC);
209 dev_priv->saveFPA0 = PSB_RVDC32(MRST_FPA0); 210 regs->saveFPA0 = PSB_RVDC32(MRST_FPA0);
210 dev_priv->saveFPA1 = PSB_RVDC32(MRST_FPA1); 211 regs->saveFPA1 = PSB_RVDC32(MRST_FPA1);
211 dev_priv->saveDPLL_A = PSB_RVDC32(MRST_DPLL_A); 212 regs->saveDPLL_A = PSB_RVDC32(MRST_DPLL_A);
212 dev_priv->saveHTOTAL_A = PSB_RVDC32(HTOTAL_A); 213 regs->saveHTOTAL_A = PSB_RVDC32(HTOTAL_A);
213 dev_priv->saveHBLANK_A = PSB_RVDC32(HBLANK_A); 214 regs->saveHBLANK_A = PSB_RVDC32(HBLANK_A);
214 dev_priv->saveHSYNC_A = PSB_RVDC32(HSYNC_A); 215 regs->saveHSYNC_A = PSB_RVDC32(HSYNC_A);
215 dev_priv->saveVTOTAL_A = PSB_RVDC32(VTOTAL_A); 216 regs->saveVTOTAL_A = PSB_RVDC32(VTOTAL_A);
216 dev_priv->saveVBLANK_A = PSB_RVDC32(VBLANK_A); 217 regs->saveVBLANK_A = PSB_RVDC32(VBLANK_A);
217 dev_priv->saveVSYNC_A = PSB_RVDC32(VSYNC_A); 218 regs->saveVSYNC_A = PSB_RVDC32(VSYNC_A);
218 dev_priv->saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A); 219 regs->saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
219 dev_priv->saveDSPACNTR = PSB_RVDC32(DSPACNTR); 220 regs->saveDSPACNTR = PSB_RVDC32(DSPACNTR);
220 dev_priv->saveDSPASTRIDE = PSB_RVDC32(DSPASTRIDE); 221 regs->saveDSPASTRIDE = PSB_RVDC32(DSPASTRIDE);
221 dev_priv->saveDSPAADDR = PSB_RVDC32(DSPABASE); 222 regs->saveDSPAADDR = PSB_RVDC32(DSPABASE);
222 dev_priv->saveDSPASURF = PSB_RVDC32(DSPASURF); 223 regs->saveDSPASURF = PSB_RVDC32(DSPASURF);
223 dev_priv->saveDSPALINOFF = PSB_RVDC32(DSPALINOFF); 224 regs->saveDSPALINOFF = PSB_RVDC32(DSPALINOFF);
224 dev_priv->saveDSPATILEOFF = PSB_RVDC32(DSPATILEOFF); 225 regs->saveDSPATILEOFF = PSB_RVDC32(DSPATILEOFF);
225 226
226 /* Save cursor regs */ 227 /* Save cursor regs */
227 dev_priv->saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR); 228 regs->saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
228 dev_priv->saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE); 229 regs->saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
229 dev_priv->saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS); 230 regs->saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
230 231
231 /* Save palette (gamma) */ 232 /* Save palette (gamma) */
232 for (i = 0; i < 256; i++) 233 for (i = 0; i < 256; i++)
233 dev_priv->save_palette_a[i] = PSB_RVDC32(PALETTE_A + (i << 2)); 234 regs->save_palette_a[i] = PSB_RVDC32(PALETTE_A + (i << 2));
234 235
235 if (dev_priv->hdmi_priv) 236 if (dev_priv->hdmi_priv)
236 oaktrail_hdmi_save(dev); 237 oaktrail_hdmi_save(dev);
237 238
238 /* Save performance state */ 239 /* Save performance state */
239 dev_priv->savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE); 240 regs->savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
240 241
241 /* LVDS state */ 242 /* LVDS state */
242 dev_priv->savePP_CONTROL = PSB_RVDC32(PP_CONTROL); 243 regs->savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
243 dev_priv->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS); 244 regs->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
244 dev_priv->savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS); 245 regs->savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
245 dev_priv->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL); 246 regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
246 dev_priv->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2); 247 regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
247 dev_priv->saveLVDS = PSB_RVDC32(LVDS); 248 regs->saveLVDS = PSB_RVDC32(LVDS);
248 dev_priv->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); 249 regs->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
249 dev_priv->savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON); 250 regs->savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
250 dev_priv->savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF); 251 regs->savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
251 dev_priv->savePP_DIVISOR = PSB_RVDC32(PP_CYCLE); 252 regs->savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
252 253
253 /* HW overlay */ 254 /* HW overlay */
254 dev_priv->saveOV_OVADD = PSB_RVDC32(OV_OVADD); 255 regs->saveOV_OVADD = PSB_RVDC32(OV_OVADD);
255 dev_priv->saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0); 256 regs->saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
256 dev_priv->saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1); 257 regs->saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
257 dev_priv->saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2); 258 regs->saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
258 dev_priv->saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3); 259 regs->saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
259 dev_priv->saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4); 260 regs->saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
260 dev_priv->saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5); 261 regs->saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
261 262
262 /* DPST registers */ 263 /* DPST registers */
263 dev_priv->saveHISTOGRAM_INT_CONTROL_REG = 264 regs->saveHISTOGRAM_INT_CONTROL_REG =
264 PSB_RVDC32(HISTOGRAM_INT_CONTROL); 265 PSB_RVDC32(HISTOGRAM_INT_CONTROL);
265 dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG = 266 regs->saveHISTOGRAM_LOGIC_CONTROL_REG =
266 PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL); 267 PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
267 dev_priv->savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC); 268 regs->savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
268 269
269 if (dev_priv->iLVDS_enable) { 270 if (dev_priv->iLVDS_enable) {
270 /* Shut down the panel */ 271 /* Shut down the panel */
@@ -302,79 +303,80 @@ static int oaktrail_save_display_registers(struct drm_device *dev)
302static int oaktrail_restore_display_registers(struct drm_device *dev) 303static int oaktrail_restore_display_registers(struct drm_device *dev)
303{ 304{
304 struct drm_psb_private *dev_priv = dev->dev_private; 305 struct drm_psb_private *dev_priv = dev->dev_private;
306 struct psb_state *regs = &dev_priv->regs;
305 u32 pp_stat; 307 u32 pp_stat;
306 int i; 308 int i;
307 309
308 /* Display arbitration + watermarks */ 310 /* Display arbitration + watermarks */
309 PSB_WVDC32(dev_priv->saveDSPARB, DSPARB); 311 PSB_WVDC32(regs->saveDSPARB, DSPARB);
310 PSB_WVDC32(dev_priv->saveDSPFW1, DSPFW1); 312 PSB_WVDC32(regs->saveDSPFW1, DSPFW1);
311 PSB_WVDC32(dev_priv->saveDSPFW2, DSPFW2); 313 PSB_WVDC32(regs->saveDSPFW2, DSPFW2);
312 PSB_WVDC32(dev_priv->saveDSPFW3, DSPFW3); 314 PSB_WVDC32(regs->saveDSPFW3, DSPFW3);
313 PSB_WVDC32(dev_priv->saveDSPFW4, DSPFW4); 315 PSB_WVDC32(regs->saveDSPFW4, DSPFW4);
314 PSB_WVDC32(dev_priv->saveDSPFW5, DSPFW5); 316 PSB_WVDC32(regs->saveDSPFW5, DSPFW5);
315 PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6); 317 PSB_WVDC32(regs->saveDSPFW6, DSPFW6);
316 PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT); 318 PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT);
317 319
318 /* Make sure VGA plane is off. it initializes to on after reset!*/ 320 /* Make sure VGA plane is off. it initializes to on after reset!*/
319 PSB_WVDC32(0x80000000, VGACNTRL); 321 PSB_WVDC32(0x80000000, VGACNTRL);
320 322
321 /* set the plls */ 323 /* set the plls */
322 PSB_WVDC32(dev_priv->saveFPA0, MRST_FPA0); 324 PSB_WVDC32(regs->saveFPA0, MRST_FPA0);
323 PSB_WVDC32(dev_priv->saveFPA1, MRST_FPA1); 325 PSB_WVDC32(regs->saveFPA1, MRST_FPA1);
324 326
325 /* Actually enable it */ 327 /* Actually enable it */
326 PSB_WVDC32(dev_priv->saveDPLL_A, MRST_DPLL_A); 328 PSB_WVDC32(regs->saveDPLL_A, MRST_DPLL_A);
327 DRM_UDELAY(150); 329 DRM_UDELAY(150);
328 330
329 /* Restore mode */ 331 /* Restore mode */
330 PSB_WVDC32(dev_priv->saveHTOTAL_A, HTOTAL_A); 332 PSB_WVDC32(regs->saveHTOTAL_A, HTOTAL_A);
331 PSB_WVDC32(dev_priv->saveHBLANK_A, HBLANK_A); 333 PSB_WVDC32(regs->saveHBLANK_A, HBLANK_A);
332 PSB_WVDC32(dev_priv->saveHSYNC_A, HSYNC_A); 334 PSB_WVDC32(regs->saveHSYNC_A, HSYNC_A);
333 PSB_WVDC32(dev_priv->saveVTOTAL_A, VTOTAL_A); 335 PSB_WVDC32(regs->saveVTOTAL_A, VTOTAL_A);
334 PSB_WVDC32(dev_priv->saveVBLANK_A, VBLANK_A); 336 PSB_WVDC32(regs->saveVBLANK_A, VBLANK_A);
335 PSB_WVDC32(dev_priv->saveVSYNC_A, VSYNC_A); 337 PSB_WVDC32(regs->saveVSYNC_A, VSYNC_A);
336 PSB_WVDC32(dev_priv->savePIPEASRC, PIPEASRC); 338 PSB_WVDC32(regs->savePIPEASRC, PIPEASRC);
337 PSB_WVDC32(dev_priv->saveBCLRPAT_A, BCLRPAT_A); 339 PSB_WVDC32(regs->saveBCLRPAT_A, BCLRPAT_A);
338 340
339 /* Restore performance mode*/ 341 /* Restore performance mode*/
340 PSB_WVDC32(dev_priv->savePERF_MODE, MRST_PERF_MODE); 342 PSB_WVDC32(regs->savePERF_MODE, MRST_PERF_MODE);
341 343
342 /* Enable the pipe*/ 344 /* Enable the pipe*/
343 if (dev_priv->iLVDS_enable) 345 if (dev_priv->iLVDS_enable)
344 PSB_WVDC32(dev_priv->savePIPEACONF, PIPEACONF); 346 PSB_WVDC32(regs->savePIPEACONF, PIPEACONF);
345 347
346 /* Set up the plane*/ 348 /* Set up the plane*/
347 PSB_WVDC32(dev_priv->saveDSPALINOFF, DSPALINOFF); 349 PSB_WVDC32(regs->saveDSPALINOFF, DSPALINOFF);
348 PSB_WVDC32(dev_priv->saveDSPASTRIDE, DSPASTRIDE); 350 PSB_WVDC32(regs->saveDSPASTRIDE, DSPASTRIDE);
349 PSB_WVDC32(dev_priv->saveDSPATILEOFF, DSPATILEOFF); 351 PSB_WVDC32(regs->saveDSPATILEOFF, DSPATILEOFF);
350 352
351 /* Enable the plane */ 353 /* Enable the plane */
352 PSB_WVDC32(dev_priv->saveDSPACNTR, DSPACNTR); 354 PSB_WVDC32(regs->saveDSPACNTR, DSPACNTR);
353 PSB_WVDC32(dev_priv->saveDSPASURF, DSPASURF); 355 PSB_WVDC32(regs->saveDSPASURF, DSPASURF);
354 356
355 /* Enable Cursor A */ 357 /* Enable Cursor A */
356 PSB_WVDC32(dev_priv->saveDSPACURSOR_CTRL, CURACNTR); 358 PSB_WVDC32(regs->saveDSPACURSOR_CTRL, CURACNTR);
357 PSB_WVDC32(dev_priv->saveDSPACURSOR_POS, CURAPOS); 359 PSB_WVDC32(regs->saveDSPACURSOR_POS, CURAPOS);
358 PSB_WVDC32(dev_priv->saveDSPACURSOR_BASE, CURABASE); 360 PSB_WVDC32(regs->saveDSPACURSOR_BASE, CURABASE);
359 361
360 /* Restore palette (gamma) */ 362 /* Restore palette (gamma) */
361 for (i = 0; i < 256; i++) 363 for (i = 0; i < 256; i++)
362 PSB_WVDC32(dev_priv->save_palette_a[i], PALETTE_A + (i << 2)); 364 PSB_WVDC32(regs->save_palette_a[i], PALETTE_A + (i << 2));
363 365
364 if (dev_priv->hdmi_priv) 366 if (dev_priv->hdmi_priv)
365 oaktrail_hdmi_restore(dev); 367 oaktrail_hdmi_restore(dev);
366 368
367 if (dev_priv->iLVDS_enable) { 369 if (dev_priv->iLVDS_enable) {
368 PSB_WVDC32(dev_priv->saveBLC_PWM_CTL2, BLC_PWM_CTL2); 370 PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
369 PSB_WVDC32(dev_priv->saveLVDS, LVDS); /*port 61180h*/ 371 PSB_WVDC32(regs->saveLVDS, LVDS); /*port 61180h*/
370 PSB_WVDC32(dev_priv->savePFIT_CONTROL, PFIT_CONTROL); 372 PSB_WVDC32(regs->savePFIT_CONTROL, PFIT_CONTROL);
371 PSB_WVDC32(dev_priv->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); 373 PSB_WVDC32(regs->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
372 PSB_WVDC32(dev_priv->savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS); 374 PSB_WVDC32(regs->savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
373 PSB_WVDC32(dev_priv->saveBLC_PWM_CTL, BLC_PWM_CTL); 375 PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
374 PSB_WVDC32(dev_priv->savePP_ON_DELAYS, LVDSPP_ON); 376 PSB_WVDC32(regs->savePP_ON_DELAYS, LVDSPP_ON);
375 PSB_WVDC32(dev_priv->savePP_OFF_DELAYS, LVDSPP_OFF); 377 PSB_WVDC32(regs->savePP_OFF_DELAYS, LVDSPP_OFF);
376 PSB_WVDC32(dev_priv->savePP_DIVISOR, PP_CYCLE); 378 PSB_WVDC32(regs->savePP_DIVISOR, PP_CYCLE);
377 PSB_WVDC32(dev_priv->savePP_CONTROL, PP_CONTROL); 379 PSB_WVDC32(regs->savePP_CONTROL, PP_CONTROL);
378 } 380 }
379 381
380 /* Wait for cycle delay */ 382 /* Wait for cycle delay */
@@ -388,20 +390,20 @@ static int oaktrail_restore_display_registers(struct drm_device *dev)
388 } while (pp_stat & 0x10000000); 390 } while (pp_stat & 0x10000000);
389 391
390 /* Restore HW overlay */ 392 /* Restore HW overlay */
391 PSB_WVDC32(dev_priv->saveOV_OVADD, OV_OVADD); 393 PSB_WVDC32(regs->saveOV_OVADD, OV_OVADD);
392 PSB_WVDC32(dev_priv->saveOV_OGAMC0, OV_OGAMC0); 394 PSB_WVDC32(regs->saveOV_OGAMC0, OV_OGAMC0);
393 PSB_WVDC32(dev_priv->saveOV_OGAMC1, OV_OGAMC1); 395 PSB_WVDC32(regs->saveOV_OGAMC1, OV_OGAMC1);
394 PSB_WVDC32(dev_priv->saveOV_OGAMC2, OV_OGAMC2); 396 PSB_WVDC32(regs->saveOV_OGAMC2, OV_OGAMC2);
395 PSB_WVDC32(dev_priv->saveOV_OGAMC3, OV_OGAMC3); 397 PSB_WVDC32(regs->saveOV_OGAMC3, OV_OGAMC3);
396 PSB_WVDC32(dev_priv->saveOV_OGAMC4, OV_OGAMC4); 398 PSB_WVDC32(regs->saveOV_OGAMC4, OV_OGAMC4);
397 PSB_WVDC32(dev_priv->saveOV_OGAMC5, OV_OGAMC5); 399 PSB_WVDC32(regs->saveOV_OGAMC5, OV_OGAMC5);
398 400
399 /* DPST registers */ 401 /* DPST registers */
400 PSB_WVDC32(dev_priv->saveHISTOGRAM_INT_CONTROL_REG, 402 PSB_WVDC32(regs->saveHISTOGRAM_INT_CONTROL_REG,
401 HISTOGRAM_INT_CONTROL); 403 HISTOGRAM_INT_CONTROL);
402 PSB_WVDC32(dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG, 404 PSB_WVDC32(regs->saveHISTOGRAM_LOGIC_CONTROL_REG,
403 HISTOGRAM_LOGIC_CONTROL); 405 HISTOGRAM_LOGIC_CONTROL);
404 PSB_WVDC32(dev_priv->savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC); 406 PSB_WVDC32(regs->savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);
405 407
406 return 0; 408 return 0;
407} 409}
diff --git a/drivers/gpu/drm/gma500/oaktrail_hdmi.c b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
index 025d30970cc0..5a2de014f237 100644
--- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
+++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
@@ -766,6 +766,7 @@ void oaktrail_hdmi_save(struct drm_device *dev)
766{ 766{
767 struct drm_psb_private *dev_priv = dev->dev_private; 767 struct drm_psb_private *dev_priv = dev->dev_private;
768 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 768 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
769 struct psb_state *regs = &dev_priv->regs;
769 int i; 770 int i;
770 771
771 /* dpll */ 772 /* dpll */
@@ -776,14 +777,14 @@ void oaktrail_hdmi_save(struct drm_device *dev)
776 hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE); 777 hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE);
777 778
778 /* pipe B */ 779 /* pipe B */
779 dev_priv->savePIPEBCONF = PSB_RVDC32(PIPEBCONF); 780 regs->savePIPEBCONF = PSB_RVDC32(PIPEBCONF);
780 dev_priv->savePIPEBSRC = PSB_RVDC32(PIPEBSRC); 781 regs->savePIPEBSRC = PSB_RVDC32(PIPEBSRC);
781 dev_priv->saveHTOTAL_B = PSB_RVDC32(HTOTAL_B); 782 regs->saveHTOTAL_B = PSB_RVDC32(HTOTAL_B);
782 dev_priv->saveHBLANK_B = PSB_RVDC32(HBLANK_B); 783 regs->saveHBLANK_B = PSB_RVDC32(HBLANK_B);
783 dev_priv->saveHSYNC_B = PSB_RVDC32(HSYNC_B); 784 regs->saveHSYNC_B = PSB_RVDC32(HSYNC_B);
784 dev_priv->saveVTOTAL_B = PSB_RVDC32(VTOTAL_B); 785 regs->saveVTOTAL_B = PSB_RVDC32(VTOTAL_B);
785 dev_priv->saveVBLANK_B = PSB_RVDC32(VBLANK_B); 786 regs->saveVBLANK_B = PSB_RVDC32(VBLANK_B);
786 dev_priv->saveVSYNC_B = PSB_RVDC32(VSYNC_B); 787 regs->saveVSYNC_B = PSB_RVDC32(VSYNC_B);
787 788
788 hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF); 789 hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF);
789 hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC); 790 hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC);
@@ -795,21 +796,21 @@ void oaktrail_hdmi_save(struct drm_device *dev)
795 hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B); 796 hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B);
796 797
797 /* plane */ 798 /* plane */
798 dev_priv->saveDSPBCNTR = PSB_RVDC32(DSPBCNTR); 799 regs->saveDSPBCNTR = PSB_RVDC32(DSPBCNTR);
799 dev_priv->saveDSPBSTRIDE = PSB_RVDC32(DSPBSTRIDE); 800 regs->saveDSPBSTRIDE = PSB_RVDC32(DSPBSTRIDE);
800 dev_priv->saveDSPBADDR = PSB_RVDC32(DSPBBASE); 801 regs->saveDSPBADDR = PSB_RVDC32(DSPBBASE);
801 dev_priv->saveDSPBSURF = PSB_RVDC32(DSPBSURF); 802 regs->saveDSPBSURF = PSB_RVDC32(DSPBSURF);
802 dev_priv->saveDSPBLINOFF = PSB_RVDC32(DSPBLINOFF); 803 regs->saveDSPBLINOFF = PSB_RVDC32(DSPBLINOFF);
803 dev_priv->saveDSPBTILEOFF = PSB_RVDC32(DSPBTILEOFF); 804 regs->saveDSPBTILEOFF = PSB_RVDC32(DSPBTILEOFF);
804 805
805 /* cursor B */ 806 /* cursor B */
806 dev_priv->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR); 807 regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR);
807 dev_priv->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE); 808 regs->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE);
808 dev_priv->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS); 809 regs->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS);
809 810
810 /* save palette */ 811 /* save palette */
811 for (i = 0; i < 256; i++) 812 for (i = 0; i < 256; i++)
812 dev_priv->save_palette_b[i] = PSB_RVDC32(PALETTE_B + (i << 2)); 813 regs->save_palette_b[i] = PSB_RVDC32(PALETTE_B + (i << 2));
813} 814}
814 815
815/* restore HDMI register state */ 816/* restore HDMI register state */
@@ -817,6 +818,7 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
817{ 818{
818 struct drm_psb_private *dev_priv = dev->dev_private; 819 struct drm_psb_private *dev_priv = dev->dev_private;
819 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 820 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
821 struct psb_state *regs = &dev_priv->regs;
820 int i; 822 int i;
821 823
822 /* dpll */ 824 /* dpll */
@@ -828,13 +830,13 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
828 DRM_UDELAY(150); 830 DRM_UDELAY(150);
829 831
830 /* pipe */ 832 /* pipe */
831 PSB_WVDC32(dev_priv->savePIPEBSRC, PIPEBSRC); 833 PSB_WVDC32(regs->savePIPEBSRC, PIPEBSRC);
832 PSB_WVDC32(dev_priv->saveHTOTAL_B, HTOTAL_B); 834 PSB_WVDC32(regs->saveHTOTAL_B, HTOTAL_B);
833 PSB_WVDC32(dev_priv->saveHBLANK_B, HBLANK_B); 835 PSB_WVDC32(regs->saveHBLANK_B, HBLANK_B);
834 PSB_WVDC32(dev_priv->saveHSYNC_B, HSYNC_B); 836 PSB_WVDC32(regs->saveHSYNC_B, HSYNC_B);
835 PSB_WVDC32(dev_priv->saveVTOTAL_B, VTOTAL_B); 837 PSB_WVDC32(regs->saveVTOTAL_B, VTOTAL_B);
836 PSB_WVDC32(dev_priv->saveVBLANK_B, VBLANK_B); 838 PSB_WVDC32(regs->saveVBLANK_B, VBLANK_B);
837 PSB_WVDC32(dev_priv->saveVSYNC_B, VSYNC_B); 839 PSB_WVDC32(regs->saveVSYNC_B, VSYNC_B);
838 840
839 PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC); 841 PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC);
840 PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B); 842 PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B);
@@ -844,22 +846,22 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
844 PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B); 846 PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B);
845 PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B); 847 PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B);
846 848
847 PSB_WVDC32(dev_priv->savePIPEBCONF, PIPEBCONF); 849 PSB_WVDC32(regs->savePIPEBCONF, PIPEBCONF);
848 PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF); 850 PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF);
849 851
850 /* plane */ 852 /* plane */
851 PSB_WVDC32(dev_priv->saveDSPBLINOFF, DSPBLINOFF); 853 PSB_WVDC32(regs->saveDSPBLINOFF, DSPBLINOFF);
852 PSB_WVDC32(dev_priv->saveDSPBSTRIDE, DSPBSTRIDE); 854 PSB_WVDC32(regs->saveDSPBSTRIDE, DSPBSTRIDE);
853 PSB_WVDC32(dev_priv->saveDSPBTILEOFF, DSPBTILEOFF); 855 PSB_WVDC32(regs->saveDSPBTILEOFF, DSPBTILEOFF);
854 PSB_WVDC32(dev_priv->saveDSPBCNTR, DSPBCNTR); 856 PSB_WVDC32(regs->saveDSPBCNTR, DSPBCNTR);
855 PSB_WVDC32(dev_priv->saveDSPBSURF, DSPBSURF); 857 PSB_WVDC32(regs->saveDSPBSURF, DSPBSURF);
856 858
857 /* cursor B */ 859 /* cursor B */
858 PSB_WVDC32(dev_priv->saveDSPBCURSOR_CTRL, CURBCNTR); 860 PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR);
859 PSB_WVDC32(dev_priv->saveDSPBCURSOR_POS, CURBPOS); 861 PSB_WVDC32(regs->saveDSPBCURSOR_POS, CURBPOS);
860 PSB_WVDC32(dev_priv->saveDSPBCURSOR_BASE, CURBBASE); 862 PSB_WVDC32(regs->saveDSPBCURSOR_BASE, CURBBASE);
861 863
862 /* restore palette */ 864 /* restore palette */
863 for (i = 0; i < 256; i++) 865 for (i = 0; i < 256; i++)
864 PSB_WVDC32(dev_priv->save_palette_b[i], PALETTE_B + (i << 2)); 866 PSB_WVDC32(regs->save_palette_b[i], PALETTE_B + (i << 2));
865} 867}
diff --git a/drivers/gpu/drm/gma500/oaktrail_lvds.c b/drivers/gpu/drm/gma500/oaktrail_lvds.c
index 238bbe105304..37273b80bcd5 100644
--- a/drivers/gpu/drm/gma500/oaktrail_lvds.c
+++ b/drivers/gpu/drm/gma500/oaktrail_lvds.c
@@ -192,7 +192,7 @@ static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev)
192 192
193 gma_power_end(dev); 193 gma_power_end(dev);
194 } else 194 } else
195 ret = ((dev_priv->saveBLC_PWM_CTL & 195 ret = ((dev_priv->regs.saveBLC_PWM_CTL &
196 BACKLIGHT_MODULATION_FREQ_MASK) >> 196 BACKLIGHT_MODULATION_FREQ_MASK) >>
197 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2; 197 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
198 198
diff --git a/drivers/gpu/drm/gma500/power.c b/drivers/gpu/drm/gma500/power.c
index 94025693bae1..bbf635cebdbc 100644
--- a/drivers/gpu/drm/gma500/power.c
+++ b/drivers/gpu/drm/gma500/power.c
@@ -132,9 +132,9 @@ static void gma_suspend_pci(struct pci_dev *pdev)
132 132
133 pci_save_state(pdev); 133 pci_save_state(pdev);
134 pci_read_config_dword(pdev, 0x5C, &bsm); 134 pci_read_config_dword(pdev, 0x5C, &bsm);
135 dev_priv->saveBSM = bsm; 135 dev_priv->regs.saveBSM = bsm;
136 pci_read_config_dword(pdev, 0xFC, &vbt); 136 pci_read_config_dword(pdev, 0xFC, &vbt);
137 dev_priv->saveVBT = vbt; 137 dev_priv->regs.saveVBT = vbt;
138 pci_read_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, &dev_priv->msi_addr); 138 pci_read_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, &dev_priv->msi_addr);
139 pci_read_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, &dev_priv->msi_data); 139 pci_read_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, &dev_priv->msi_data);
140 140
@@ -162,8 +162,8 @@ static bool gma_resume_pci(struct pci_dev *pdev)
162 162
163 pci_set_power_state(pdev, PCI_D0); 163 pci_set_power_state(pdev, PCI_D0);
164 pci_restore_state(pdev); 164 pci_restore_state(pdev);
165 pci_write_config_dword(pdev, 0x5c, dev_priv->saveBSM); 165 pci_write_config_dword(pdev, 0x5c, dev_priv->regs.saveBSM);
166 pci_write_config_dword(pdev, 0xFC, dev_priv->saveVBT); 166 pci_write_config_dword(pdev, 0xFC, dev_priv->regs.saveVBT);
167 /* restoring MSI address and data in PCIx space */ 167 /* restoring MSI address and data in PCIx space */
168 pci_write_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, dev_priv->msi_addr); 168 pci_write_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, dev_priv->msi_addr);
169 pci_write_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, dev_priv->msi_data); 169 pci_write_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, dev_priv->msi_data);
diff --git a/drivers/gpu/drm/gma500/psb_device.c b/drivers/gpu/drm/gma500/psb_device.c
index e5f5906172b0..0d370e7094b8 100644
--- a/drivers/gpu/drm/gma500/psb_device.c
+++ b/drivers/gpu/drm/gma500/psb_device.c
@@ -177,16 +177,17 @@ static int psb_save_display_registers(struct drm_device *dev)
177 struct drm_psb_private *dev_priv = dev->dev_private; 177 struct drm_psb_private *dev_priv = dev->dev_private;
178 struct drm_crtc *crtc; 178 struct drm_crtc *crtc;
179 struct drm_connector *connector; 179 struct drm_connector *connector;
180 struct psb_state *regs = &dev_priv->regs;
180 181
181 /* Display arbitration control + watermarks */ 182 /* Display arbitration control + watermarks */
182 dev_priv->saveDSPARB = PSB_RVDC32(DSPARB); 183 regs->saveDSPARB = PSB_RVDC32(DSPARB);
183 dev_priv->saveDSPFW1 = PSB_RVDC32(DSPFW1); 184 regs->saveDSPFW1 = PSB_RVDC32(DSPFW1);
184 dev_priv->saveDSPFW2 = PSB_RVDC32(DSPFW2); 185 regs->saveDSPFW2 = PSB_RVDC32(DSPFW2);
185 dev_priv->saveDSPFW3 = PSB_RVDC32(DSPFW3); 186 regs->saveDSPFW3 = PSB_RVDC32(DSPFW3);
186 dev_priv->saveDSPFW4 = PSB_RVDC32(DSPFW4); 187 regs->saveDSPFW4 = PSB_RVDC32(DSPFW4);
187 dev_priv->saveDSPFW5 = PSB_RVDC32(DSPFW5); 188 regs->saveDSPFW5 = PSB_RVDC32(DSPFW5);
188 dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6); 189 regs->saveDSPFW6 = PSB_RVDC32(DSPFW6);
189 dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); 190 regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
190 191
191 /* Save crtc and output state */ 192 /* Save crtc and output state */
192 mutex_lock(&dev->mode_config.mutex); 193 mutex_lock(&dev->mode_config.mutex);
@@ -213,16 +214,17 @@ static int psb_restore_display_registers(struct drm_device *dev)
213 struct drm_psb_private *dev_priv = dev->dev_private; 214 struct drm_psb_private *dev_priv = dev->dev_private;
214 struct drm_crtc *crtc; 215 struct drm_crtc *crtc;
215 struct drm_connector *connector; 216 struct drm_connector *connector;
217 struct psb_state *regs = &dev_priv->regs;
216 218
217 /* Display arbitration + watermarks */ 219 /* Display arbitration + watermarks */
218 PSB_WVDC32(dev_priv->saveDSPARB, DSPARB); 220 PSB_WVDC32(regs->saveDSPARB, DSPARB);
219 PSB_WVDC32(dev_priv->saveDSPFW1, DSPFW1); 221 PSB_WVDC32(regs->saveDSPFW1, DSPFW1);
220 PSB_WVDC32(dev_priv->saveDSPFW2, DSPFW2); 222 PSB_WVDC32(regs->saveDSPFW2, DSPFW2);
221 PSB_WVDC32(dev_priv->saveDSPFW3, DSPFW3); 223 PSB_WVDC32(regs->saveDSPFW3, DSPFW3);
222 PSB_WVDC32(dev_priv->saveDSPFW4, DSPFW4); 224 PSB_WVDC32(regs->saveDSPFW4, DSPFW4);
223 PSB_WVDC32(dev_priv->saveDSPFW5, DSPFW5); 225 PSB_WVDC32(regs->saveDSPFW5, DSPFW5);
224 PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6); 226 PSB_WVDC32(regs->saveDSPFW6, DSPFW6);
225 PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT); 227 PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT);
226 228
227 /*make sure VGA plane is off. it initializes to on after reset!*/ 229 /*make sure VGA plane is off. it initializes to on after reset!*/
228 PSB_WVDC32(0x80000000, VGACNTRL); 230 PSB_WVDC32(0x80000000, VGACNTRL);
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index a84a9ec38bee..dee07e0d7c39 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -276,6 +276,123 @@ struct intel_gmbus {
276 u32 reg0; 276 u32 reg0;
277}; 277};
278 278
279/*
280 * Register save state. This is used to hold the context when the
281 * device is powered off. In the case of Oaktrail this can (but does not
282 * yet) include screen blank. Operations occuring during the save
283 * update the register cache instead.
284 */
285struct psb_state {
286 uint32_t saveDSPACNTR;
287 uint32_t saveDSPBCNTR;
288 uint32_t savePIPEACONF;
289 uint32_t savePIPEBCONF;
290 uint32_t savePIPEASRC;
291 uint32_t savePIPEBSRC;
292 uint32_t saveFPA0;
293 uint32_t saveFPA1;
294 uint32_t saveDPLL_A;
295 uint32_t saveDPLL_A_MD;
296 uint32_t saveHTOTAL_A;
297 uint32_t saveHBLANK_A;
298 uint32_t saveHSYNC_A;
299 uint32_t saveVTOTAL_A;
300 uint32_t saveVBLANK_A;
301 uint32_t saveVSYNC_A;
302 uint32_t saveDSPASTRIDE;
303 uint32_t saveDSPASIZE;
304 uint32_t saveDSPAPOS;
305 uint32_t saveDSPABASE;
306 uint32_t saveDSPASURF;
307 uint32_t saveDSPASTATUS;
308 uint32_t saveFPB0;
309 uint32_t saveFPB1;
310 uint32_t saveDPLL_B;
311 uint32_t saveDPLL_B_MD;
312 uint32_t saveHTOTAL_B;
313 uint32_t saveHBLANK_B;
314 uint32_t saveHSYNC_B;
315 uint32_t saveVTOTAL_B;
316 uint32_t saveVBLANK_B;
317 uint32_t saveVSYNC_B;
318 uint32_t saveDSPBSTRIDE;
319 uint32_t saveDSPBSIZE;
320 uint32_t saveDSPBPOS;
321 uint32_t saveDSPBBASE;
322 uint32_t saveDSPBSURF;
323 uint32_t saveDSPBSTATUS;
324 uint32_t saveVCLK_DIVISOR_VGA0;
325 uint32_t saveVCLK_DIVISOR_VGA1;
326 uint32_t saveVCLK_POST_DIV;
327 uint32_t saveVGACNTRL;
328 uint32_t saveADPA;
329 uint32_t saveLVDS;
330 uint32_t saveDVOA;
331 uint32_t saveDVOB;
332 uint32_t saveDVOC;
333 uint32_t savePP_ON;
334 uint32_t savePP_OFF;
335 uint32_t savePP_CONTROL;
336 uint32_t savePP_CYCLE;
337 uint32_t savePFIT_CONTROL;
338 uint32_t savePaletteA[256];
339 uint32_t savePaletteB[256];
340 uint32_t saveBLC_PWM_CTL2;
341 uint32_t saveBLC_PWM_CTL;
342 uint32_t saveCLOCKGATING;
343 uint32_t saveDSPARB;
344 uint32_t saveDSPATILEOFF;
345 uint32_t saveDSPBTILEOFF;
346 uint32_t saveDSPAADDR;
347 uint32_t saveDSPBADDR;
348 uint32_t savePFIT_AUTO_RATIOS;
349 uint32_t savePFIT_PGM_RATIOS;
350 uint32_t savePP_ON_DELAYS;
351 uint32_t savePP_OFF_DELAYS;
352 uint32_t savePP_DIVISOR;
353 uint32_t saveBSM;
354 uint32_t saveVBT;
355 uint32_t saveBCLRPAT_A;
356 uint32_t saveBCLRPAT_B;
357 uint32_t saveDSPALINOFF;
358 uint32_t saveDSPBLINOFF;
359 uint32_t savePERF_MODE;
360 uint32_t saveDSPFW1;
361 uint32_t saveDSPFW2;
362 uint32_t saveDSPFW3;
363 uint32_t saveDSPFW4;
364 uint32_t saveDSPFW5;
365 uint32_t saveDSPFW6;
366 uint32_t saveCHICKENBIT;
367 uint32_t saveDSPACURSOR_CTRL;
368 uint32_t saveDSPBCURSOR_CTRL;
369 uint32_t saveDSPACURSOR_BASE;
370 uint32_t saveDSPBCURSOR_BASE;
371 uint32_t saveDSPACURSOR_POS;
372 uint32_t saveDSPBCURSOR_POS;
373 uint32_t save_palette_a[256];
374 uint32_t save_palette_b[256];
375 uint32_t saveOV_OVADD;
376 uint32_t saveOV_OGAMC0;
377 uint32_t saveOV_OGAMC1;
378 uint32_t saveOV_OGAMC2;
379 uint32_t saveOV_OGAMC3;
380 uint32_t saveOV_OGAMC4;
381 uint32_t saveOV_OGAMC5;
382 uint32_t saveOVC_OVADD;
383 uint32_t saveOVC_OGAMC0;
384 uint32_t saveOVC_OGAMC1;
385 uint32_t saveOVC_OGAMC2;
386 uint32_t saveOVC_OGAMC3;
387 uint32_t saveOVC_OGAMC4;
388 uint32_t saveOVC_OGAMC5;
389
390 /* DPST register save */
391 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
392 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
393 uint32_t savePWM_CONTROL_LOGIC;
394};
395
279struct psb_ops; 396struct psb_ops;
280 397
281#define PSB_NUM_PIPE 3 398#define PSB_NUM_PIPE 3
@@ -403,118 +520,11 @@ struct drm_psb_private {
403 /* 520 /*
404 * Register state 521 * Register state
405 */ 522 */
406 uint32_t saveDSPACNTR; 523 struct psb_state regs;
407 uint32_t saveDSPBCNTR;
408 uint32_t savePIPEACONF;
409 uint32_t savePIPEBCONF;
410 uint32_t savePIPEASRC;
411 uint32_t savePIPEBSRC;
412 uint32_t saveFPA0;
413 uint32_t saveFPA1;
414 uint32_t saveDPLL_A;
415 uint32_t saveDPLL_A_MD;
416 uint32_t saveHTOTAL_A;
417 uint32_t saveHBLANK_A;
418 uint32_t saveHSYNC_A;
419 uint32_t saveVTOTAL_A;
420 uint32_t saveVBLANK_A;
421 uint32_t saveVSYNC_A;
422 uint32_t saveDSPASTRIDE;
423 uint32_t saveDSPASIZE;
424 uint32_t saveDSPAPOS;
425 uint32_t saveDSPABASE;
426 uint32_t saveDSPASURF;
427 uint32_t saveDSPASTATUS;
428 uint32_t saveFPB0;
429 uint32_t saveFPB1;
430 uint32_t saveDPLL_B;
431 uint32_t saveDPLL_B_MD;
432 uint32_t saveHTOTAL_B;
433 uint32_t saveHBLANK_B;
434 uint32_t saveHSYNC_B;
435 uint32_t saveVTOTAL_B;
436 uint32_t saveVBLANK_B;
437 uint32_t saveVSYNC_B;
438 uint32_t saveDSPBSTRIDE;
439 uint32_t saveDSPBSIZE;
440 uint32_t saveDSPBPOS;
441 uint32_t saveDSPBBASE;
442 uint32_t saveDSPBSURF;
443 uint32_t saveDSPBSTATUS;
444 uint32_t saveVCLK_DIVISOR_VGA0;
445 uint32_t saveVCLK_DIVISOR_VGA1;
446 uint32_t saveVCLK_POST_DIV;
447 uint32_t saveVGACNTRL;
448 uint32_t saveADPA;
449 uint32_t saveLVDS;
450 uint32_t saveDVOA;
451 uint32_t saveDVOB;
452 uint32_t saveDVOC;
453 uint32_t savePP_ON;
454 uint32_t savePP_OFF;
455 uint32_t savePP_CONTROL;
456 uint32_t savePP_CYCLE;
457 uint32_t savePFIT_CONTROL;
458 uint32_t savePaletteA[256];
459 uint32_t savePaletteB[256];
460 uint32_t saveBLC_PWM_CTL2;
461 uint32_t saveBLC_PWM_CTL;
462 uint32_t saveCLOCKGATING;
463 uint32_t saveDSPARB;
464 uint32_t saveDSPATILEOFF;
465 uint32_t saveDSPBTILEOFF;
466 uint32_t saveDSPAADDR;
467 uint32_t saveDSPBADDR;
468 uint32_t savePFIT_AUTO_RATIOS;
469 uint32_t savePFIT_PGM_RATIOS;
470 uint32_t savePP_ON_DELAYS;
471 uint32_t savePP_OFF_DELAYS;
472 uint32_t savePP_DIVISOR;
473 uint32_t saveBSM;
474 uint32_t saveVBT;
475 uint32_t saveBCLRPAT_A;
476 uint32_t saveBCLRPAT_B;
477 uint32_t saveDSPALINOFF;
478 uint32_t saveDSPBLINOFF;
479 uint32_t savePERF_MODE;
480 uint32_t saveDSPFW1;
481 uint32_t saveDSPFW2;
482 uint32_t saveDSPFW3;
483 uint32_t saveDSPFW4;
484 uint32_t saveDSPFW5;
485 uint32_t saveDSPFW6;
486 uint32_t saveCHICKENBIT;
487 uint32_t saveDSPACURSOR_CTRL;
488 uint32_t saveDSPBCURSOR_CTRL;
489 uint32_t saveDSPACURSOR_BASE;
490 uint32_t saveDSPBCURSOR_BASE;
491 uint32_t saveDSPACURSOR_POS;
492 uint32_t saveDSPBCURSOR_POS;
493 uint32_t save_palette_a[256];
494 uint32_t save_palette_b[256];
495 uint32_t saveOV_OVADD;
496 uint32_t saveOV_OGAMC0;
497 uint32_t saveOV_OGAMC1;
498 uint32_t saveOV_OGAMC2;
499 uint32_t saveOV_OGAMC3;
500 uint32_t saveOV_OGAMC4;
501 uint32_t saveOV_OGAMC5;
502 uint32_t saveOVC_OVADD;
503 uint32_t saveOVC_OGAMC0;
504 uint32_t saveOVC_OGAMC1;
505 uint32_t saveOVC_OGAMC2;
506 uint32_t saveOVC_OGAMC3;
507 uint32_t saveOVC_OGAMC4;
508 uint32_t saveOVC_OGAMC5;
509
510 /* MSI reg save */ 524 /* MSI reg save */
511 uint32_t msi_addr; 525 uint32_t msi_addr;
512 uint32_t msi_data; 526 uint32_t msi_data;
513 527
514 /* DPST register save */
515 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
516 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
517 uint32_t savePWM_CONTROL_LOGIC;
518 528
519 /* 529 /*
520 * LID-Switch 530 * LID-Switch
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c
index 49e983508d5c..4ba1ae8b5e30 100644
--- a/drivers/gpu/drm/gma500/psb_intel_display.c
+++ b/drivers/gpu/drm/gma500/psb_intel_display.c
@@ -845,7 +845,7 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
845 gma_power_end(dev); 845 gma_power_end(dev);
846 } else { 846 } else {
847 for (i = 0; i < 256; i++) { 847 for (i = 0; i < 256; i++) {
848 dev_priv->save_palette_a[i] = 848 dev_priv->regs.save_palette_a[i] =
849 ((psb_intel_crtc->lut_r[i] + 849 ((psb_intel_crtc->lut_r[i] +
850 psb_intel_crtc->lut_adj[i]) << 16) | 850 psb_intel_crtc->lut_adj[i]) << 16) |
851 ((psb_intel_crtc->lut_g[i] + 851 ((psb_intel_crtc->lut_g[i] +
@@ -1141,18 +1141,19 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev,
1141 gma_power_end(dev); 1141 gma_power_end(dev);
1142 } else { 1142 } else {
1143 dpll = (pipe == 0) ? 1143 dpll = (pipe == 0) ?
1144 dev_priv->saveDPLL_A : dev_priv->saveDPLL_B; 1144 dev_priv->regs.saveDPLL_A : dev_priv->regs.saveDPLL_B;
1145 1145
1146 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1146 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1147 fp = (pipe == 0) ? 1147 fp = (pipe == 0) ?
1148 dev_priv->saveFPA0 : 1148 dev_priv->regs.saveFPA0 :
1149 dev_priv->saveFPB0; 1149 dev_priv->regs.saveFPB0;
1150 else 1150 else
1151 fp = (pipe == 0) ? 1151 fp = (pipe == 0) ?
1152 dev_priv->saveFPA1 : 1152 dev_priv->regs.saveFPA1 :
1153 dev_priv->saveFPB1; 1153 dev_priv->regs.saveFPB1;
1154 1154
1155 is_lvds = (pipe == 1) && (dev_priv->saveLVDS & LVDS_PORT_EN); 1155 is_lvds = (pipe == 1) && (dev_priv->regs.saveLVDS &
1156 LVDS_PORT_EN);
1156 } 1157 }
1157 1158
1158 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 1159 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
@@ -1218,13 +1219,17 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
1218 gma_power_end(dev); 1219 gma_power_end(dev);
1219 } else { 1220 } else {
1220 htot = (pipe == 0) ? 1221 htot = (pipe == 0) ?
1221 dev_priv->saveHTOTAL_A : dev_priv->saveHTOTAL_B; 1222 dev_priv->regs.saveHTOTAL_A :
1223 dev_priv->regs.saveHTOTAL_B;
1222 hsync = (pipe == 0) ? 1224 hsync = (pipe == 0) ?
1223 dev_priv->saveHSYNC_A : dev_priv->saveHSYNC_B; 1225 dev_priv->regs.saveHSYNC_A :
1226 dev_priv->regs.saveHSYNC_B;
1224 vtot = (pipe == 0) ? 1227 vtot = (pipe == 0) ?
1225 dev_priv->saveVTOTAL_A : dev_priv->saveVTOTAL_B; 1228 dev_priv->regs.saveVTOTAL_A :
1229 dev_priv->regs.saveVTOTAL_B;
1226 vsync = (pipe == 0) ? 1230 vsync = (pipe == 0) ?
1227 dev_priv->saveVSYNC_A : dev_priv->saveVSYNC_B; 1231 dev_priv->regs.saveVSYNC_A :
1232 dev_priv->regs.saveVSYNC_B;
1228 } 1233 }
1229 1234
1230 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 1235 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
diff --git a/drivers/gpu/drm/gma500/psb_intel_lvds.c b/drivers/gpu/drm/gma500/psb_intel_lvds.c
index a25e4ca5e91c..69a96513752f 100644
--- a/drivers/gpu/drm/gma500/psb_intel_lvds.c
+++ b/drivers/gpu/drm/gma500/psb_intel_lvds.c
@@ -77,7 +77,7 @@ static u32 psb_intel_lvds_get_max_backlight(struct drm_device *dev)
77 ret = REG_READ(BLC_PWM_CTL); 77 ret = REG_READ(BLC_PWM_CTL);
78 gma_power_end(dev); 78 gma_power_end(dev);
79 } else /* Powered off, use the saved value */ 79 } else /* Powered off, use the saved value */
80 ret = dev_priv->saveBLC_PWM_CTL; 80 ret = dev_priv->regs.saveBLC_PWM_CTL;
81 81
82 /* Top 15bits hold the frequency mask */ 82 /* Top 15bits hold the frequency mask */
83 ret = (ret & BACKLIGHT_MODULATION_FREQ_MASK) >> 83 ret = (ret & BACKLIGHT_MODULATION_FREQ_MASK) >>
@@ -86,7 +86,7 @@ static u32 psb_intel_lvds_get_max_backlight(struct drm_device *dev)
86 ret *= 2; /* Return a 16bit range as needed for setting */ 86 ret *= 2; /* Return a 16bit range as needed for setting */
87 if (ret == 0) 87 if (ret == 0)
88 dev_err(dev->dev, "BL bug: Reg %08x save %08X\n", 88 dev_err(dev->dev, "BL bug: Reg %08x save %08X\n",
89 REG_READ(BLC_PWM_CTL), dev_priv->saveBLC_PWM_CTL); 89 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL);
90 return ret; 90 return ret;
91} 91}
92 92
@@ -203,13 +203,13 @@ static void psb_intel_lvds_set_backlight(struct drm_device *dev, int level)
203 REG_WRITE(BLC_PWM_CTL, 203 REG_WRITE(BLC_PWM_CTL,
204 (blc_pwm_ctl | 204 (blc_pwm_ctl |
205 (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); 205 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
206 dev_priv->saveBLC_PWM_CTL = (blc_pwm_ctl | 206 dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |
207 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)); 207 (level << BACKLIGHT_DUTY_CYCLE_SHIFT));
208 gma_power_end(dev); 208 gma_power_end(dev);
209 } else { 209 } else {
210 blc_pwm_ctl = dev_priv->saveBLC_PWM_CTL & 210 blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL &
211 ~BACKLIGHT_DUTY_CYCLE_MASK; 211 ~BACKLIGHT_DUTY_CYCLE_MASK;
212 dev_priv->saveBLC_PWM_CTL = (blc_pwm_ctl | 212 dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |
213 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)); 213 (level << BACKLIGHT_DUTY_CYCLE_SHIFT));
214 } 214 }
215} 215}
@@ -283,7 +283,7 @@ static void psb_intel_lvds_save(struct drm_connector *connector)
283 lvds_priv->savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); 283 lvds_priv->savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
284 284
285 /*TODO: move backlight_duty_cycle to psb_intel_lvds_priv*/ 285 /*TODO: move backlight_duty_cycle to psb_intel_lvds_priv*/
286 dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & 286 dev_priv->backlight_duty_cycle = (dev_priv->regs.saveBLC_PWM_CTL &
287 BACKLIGHT_DUTY_CYCLE_MASK); 287 BACKLIGHT_DUTY_CYCLE_MASK);
288 288
289 /* 289 /*
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-23 04:28:40 -0400