aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorAlan Cox <alan@linux.intel.com>2012-03-08 11:00:17 -0500
committerDave Airlie <airlied@redhat.com>2012-03-10 08:05:25 -0500
commit933315acb6e223d4da36cb0b95d18dcfa6323658 (patch)
tree16b9d140c35357d9b704901027d48ce599045dad /drivers
parent3df546be6b74c1e2633498104ba8879507fb06fd (diff)
gma500: clean up some of the struct fields we no longer use
Some this is Medfield stuff that may reappear in some form later, other bits are just dead stuff Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/gma500/oaktrail_crtc.c3
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.h94
2 files changed, 2 insertions, 95 deletions
diff --git a/drivers/gpu/drm/gma500/oaktrail_crtc.c b/drivers/gpu/drm/gma500/oaktrail_crtc.c
index 9d12a3ee1600..ff4f7adb48e8 100644
--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
+++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
@@ -428,9 +428,6 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
428 else 428 else
429 dspcntr |= DISPPLANE_SEL_PIPE_B; 429 dspcntr |= DISPPLANE_SEL_PIPE_B;
430 430
431 dev_priv->dspcntr = dspcntr |= DISPLAY_PLANE_ENABLE;
432 dev_priv->pipeconf = pipeconf |= PIPEACONF_ENABLE;
433
434 if (is_mipi) 431 if (is_mipi)
435 goto oaktrail_crtc_mode_set_exit; 432 goto oaktrail_crtc_mode_set_exit;
436 433
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index eb1568a0da95..a84a9ec38bee 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -397,33 +397,9 @@ struct drm_psb_private {
397 struct oaktrail_vbt vbt_data; 397 struct oaktrail_vbt vbt_data;
398 struct oaktrail_gct_data gct_data; 398 struct oaktrail_gct_data gct_data;
399 399
400 /* MIPI Panel type etc */ 400 /* Oaktrail HDMI state */
401 int panel_id;
402 bool dual_mipi; /* dual display - DPI & DBI */
403 bool dpi_panel_on; /* The DPI panel power is on */
404 bool dpi_panel_on2; /* The DPI panel power is on */
405 bool dbi_panel_on; /* The DBI panel power is on */
406 bool dbi_panel_on2; /* The DBI panel power is on */
407 u32 dsr_fb_update; /* DSR FB update counter */
408
409 /* Moorestown HDMI state */
410 struct oaktrail_hdmi_dev *hdmi_priv; 401 struct oaktrail_hdmi_dev *hdmi_priv;
411 402
412 /* Moorestown pipe config register value cache */
413 uint32_t pipeconf;
414 uint32_t pipeconf1;
415 uint32_t pipeconf2;
416
417 /* Moorestown plane control register value cache */
418 uint32_t dspcntr;
419 uint32_t dspcntr1;
420 uint32_t dspcntr2;
421
422 /* Moorestown MM backlight cache */
423 uint8_t saveBKLTCNT;
424 uint8_t saveBKLTREQ;
425 uint8_t saveBKLTBRTL;
426
427 /* 403 /*
428 * Register state 404 * Register state
429 */ 405 */
@@ -535,78 +511,12 @@ struct drm_psb_private {
535 uint32_t msi_addr; 511 uint32_t msi_addr;
536 uint32_t msi_data; 512 uint32_t msi_data;
537 513
538 /* Medfield specific register save state */
539 uint32_t saveHDMIPHYMISCCTL;
540 uint32_t saveHDMIB_CONTROL;
541 uint32_t saveDSPCCNTR;
542 uint32_t savePIPECCONF;
543 uint32_t savePIPECSRC;
544 uint32_t saveHTOTAL_C;
545 uint32_t saveHBLANK_C;
546 uint32_t saveHSYNC_C;
547 uint32_t saveVTOTAL_C;
548 uint32_t saveVBLANK_C;
549 uint32_t saveVSYNC_C;
550 uint32_t saveDSPCSTRIDE;
551 uint32_t saveDSPCSIZE;
552 uint32_t saveDSPCPOS;
553 uint32_t saveDSPCSURF;
554 uint32_t saveDSPCSTATUS;
555 uint32_t saveDSPCLINOFF;
556 uint32_t saveDSPCTILEOFF;
557 uint32_t saveDSPCCURSOR_CTRL;
558 uint32_t saveDSPCCURSOR_BASE;
559 uint32_t saveDSPCCURSOR_POS;
560 uint32_t save_palette_c[256];
561 uint32_t saveOV_OVADD_C;
562 uint32_t saveOV_OGAMC0_C;
563 uint32_t saveOV_OGAMC1_C;
564 uint32_t saveOV_OGAMC2_C;
565 uint32_t saveOV_OGAMC3_C;
566 uint32_t saveOV_OGAMC4_C;
567 uint32_t saveOV_OGAMC5_C;
568
569 /* DSI register save */
570 uint32_t saveDEVICE_READY_REG;
571 uint32_t saveINTR_EN_REG;
572 uint32_t saveDSI_FUNC_PRG_REG;
573 uint32_t saveHS_TX_TIMEOUT_REG;
574 uint32_t saveLP_RX_TIMEOUT_REG;
575 uint32_t saveTURN_AROUND_TIMEOUT_REG;
576 uint32_t saveDEVICE_RESET_REG;
577 uint32_t saveDPI_RESOLUTION_REG;
578 uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
579 uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
580 uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
581 uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
582 uint32_t saveVERT_SYNC_PAD_COUNT_REG;
583 uint32_t saveVERT_BACK_PORCH_COUNT_REG;
584 uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
585 uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
586 uint32_t saveINIT_COUNT_REG;
587 uint32_t saveMAX_RET_PAK_REG;
588 uint32_t saveVIDEO_FMT_REG;
589 uint32_t saveEOT_DISABLE_REG;
590 uint32_t saveLP_BYTECLK_REG;
591 uint32_t saveHS_LS_DBI_ENABLE_REG;
592 uint32_t saveTXCLKESC_REG;
593 uint32_t saveDPHY_PARAM_REG;
594 uint32_t saveMIPI_CONTROL_REG;
595 uint32_t saveMIPI;
596 uint32_t saveMIPI_C;
597
598 /* DPST register save */ 514 /* DPST register save */
599 uint32_t saveHISTOGRAM_INT_CONTROL_REG; 515 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
600 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG; 516 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
601 uint32_t savePWM_CONTROL_LOGIC; 517 uint32_t savePWM_CONTROL_LOGIC;
602 518
603 /* 519 /*
604 * DSI info.
605 */
606 void * dbi_dsr_info;
607 void * dbi_dpu_info;
608 void * dsi_configs[2];
609 /*
610 * LID-Switch 520 * LID-Switch
611 */ 521 */
612 spinlock_t lid_lock; 522 spinlock_t lid_lock;