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authorSylwester Nawrocki <s.nawrocki@samsung.com>2012-04-20 18:43:14 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-05-20 08:21:50 -0400
commit2b511edb986fc11b8fa2b5e124c885a99aded257 (patch)
treecf80ee4359e3e84edb1b35909272be828e6653a2 /drivers
parentc83a1ff063eb7cd8eb2025c08194f6bcb49334f1 (diff)
[media] s5p-fimc: Add FIMC-LITE register definitions
Add register definitions and register API for FIMC-LITE devices. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/media/video/s5p-fimc/fimc-lite-reg.c300
-rw-r--r--drivers/media/video/s5p-fimc/fimc-lite-reg.h150
-rw-r--r--drivers/media/video/s5p-fimc/fimc-lite.h213
3 files changed, 663 insertions, 0 deletions
diff --git a/drivers/media/video/s5p-fimc/fimc-lite-reg.c b/drivers/media/video/s5p-fimc/fimc-lite-reg.c
new file mode 100644
index 000000000000..419adfb7cdf9
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-lite-reg.c
@@ -0,0 +1,300 @@
1/*
2 * Register interface file for EXYNOS FIMC-LITE (camera interface) driver
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/io.h>
13#include <linux/delay.h>
14#include <media/s5p_fimc.h>
15
16#include "fimc-lite-reg.h"
17#include "fimc-lite.h"
18#include "fimc-core.h"
19
20#define FLITE_RESET_TIMEOUT 50 /* in ms */
21
22void flite_hw_reset(struct fimc_lite *dev)
23{
24 unsigned long end = jiffies + msecs_to_jiffies(FLITE_RESET_TIMEOUT);
25 u32 cfg;
26
27 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
28 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ;
29 writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
30
31 while (time_is_after_jiffies(end)) {
32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
33 if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY)
34 break;
35 usleep_range(1000, 5000);
36 }
37
38 cfg |= FLITE_REG_CIGCTRL_SWRST;
39 writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
40}
41
42void flite_hw_clear_pending_irq(struct fimc_lite *dev)
43{
44 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS);
45 cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM;
46 writel(cfg, dev->regs + FLITE_REG_CISTATUS);
47}
48
49u32 flite_hw_get_interrupt_source(struct fimc_lite *dev)
50{
51 u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS);
52 return intsrc & FLITE_REG_CISTATUS_IRQ_MASK;
53}
54
55void flite_hw_clear_last_capture_end(struct fimc_lite *dev)
56{
57
58 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2);
59 cfg &= ~FLITE_REG_CISTATUS2_LASTCAPEND;
60 writel(cfg, dev->regs + FLITE_REG_CISTATUS2);
61}
62
63void flite_hw_set_interrupt_mask(struct fimc_lite *dev)
64{
65 u32 cfg, intsrc;
66
67 /* Select interrupts to be enabled for each output mode */
68 if (dev->out_path == FIMC_IO_DMA) {
69 intsrc = FLITE_REG_CIGCTRL_IRQ_OVFEN |
70 FLITE_REG_CIGCTRL_IRQ_LASTEN |
71 FLITE_REG_CIGCTRL_IRQ_STARTEN;
72 } else {
73 /* An output to the FIMC-IS */
74 intsrc = FLITE_REG_CIGCTRL_IRQ_OVFEN |
75 FLITE_REG_CIGCTRL_IRQ_LASTEN;
76 }
77
78 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
79 cfg |= FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK;
80 cfg &= ~intsrc;
81 writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
82}
83
84void flite_hw_capture_start(struct fimc_lite *dev)
85{
86 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);
87 cfg |= FLITE_REG_CIIMGCPT_IMGCPTEN;
88 writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
89}
90
91void flite_hw_capture_stop(struct fimc_lite *dev)
92{
93 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);
94 cfg &= ~FLITE_REG_CIIMGCPT_IMGCPTEN;
95 writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
96}
97
98/*
99 * Test pattern (color bars) enable/disable. External sensor
100 * pixel clock must be active for the test pattern to work.
101 */
102void flite_hw_set_test_pattern(struct fimc_lite *dev, bool on)
103{
104 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
105 if (on)
106 cfg |= FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR;
107 else
108 cfg &= ~FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR;
109 writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
110}
111
112static const u32 src_pixfmt_map[8][3] = {
113 { V4L2_MBUS_FMT_YUYV8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR,
114 FLITE_REG_CIGCTRL_YUV422_1P },
115 { V4L2_MBUS_FMT_YVYU8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB,
116 FLITE_REG_CIGCTRL_YUV422_1P },
117 { V4L2_MBUS_FMT_UYVY8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY,
118 FLITE_REG_CIGCTRL_YUV422_1P },
119 { V4L2_MBUS_FMT_VYUY8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY,
120 FLITE_REG_CIGCTRL_YUV422_1P },
121 { V4L2_PIX_FMT_SGRBG8, 0, FLITE_REG_CIGCTRL_RAW8 },
122 { V4L2_PIX_FMT_SGRBG10, 0, FLITE_REG_CIGCTRL_RAW10 },
123 { V4L2_PIX_FMT_SGRBG12, 0, FLITE_REG_CIGCTRL_RAW12 },
124 { V4L2_MBUS_FMT_JPEG_1X8, 0, FLITE_REG_CIGCTRL_USER(1) },
125};
126
127/* Set camera input pixel format and resolution */
128void flite_hw_set_source_format(struct fimc_lite *dev, struct flite_frame *f)
129{
130 enum v4l2_mbus_pixelcode pixelcode = dev->fmt->mbus_code;
131 unsigned int i = ARRAY_SIZE(src_pixfmt_map);
132 u32 cfg;
133
134 while (i-- >= 0) {
135 if (src_pixfmt_map[i][0] == pixelcode)
136 break;
137 }
138
139 if (i == 0 && src_pixfmt_map[i][0] != pixelcode) {
140 v4l2_err(dev->vfd,
141 "Unsupported pixel code, falling back to %#08x\n",
142 src_pixfmt_map[i][0]);
143 }
144
145 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
146 cfg &= ~FLITE_REG_CIGCTRL_FMT_MASK;
147 cfg |= src_pixfmt_map[i][2];
148 writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
149
150 cfg = readl(dev->regs + FLITE_REG_CISRCSIZE);
151 cfg &= ~(FLITE_REG_CISRCSIZE_ORDER422_MASK |
152 FLITE_REG_CISRCSIZE_SIZE_CAM_MASK);
153 cfg |= (f->f_width << 16) | f->f_height;
154 cfg |= src_pixfmt_map[i][1];
155 writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);
156}
157
158/* Set the camera host input window offsets (cropping) */
159void flite_hw_set_window_offset(struct fimc_lite *dev, struct flite_frame *f)
160{
161 u32 hoff2, voff2;
162 u32 cfg;
163
164 cfg = readl(dev->regs + FLITE_REG_CIWDOFST);
165 cfg &= ~FLITE_REG_CIWDOFST_OFST_MASK;
166 cfg |= (f->rect.left << 16) | f->rect.top;
167 cfg |= FLITE_REG_CIWDOFST_WINOFSEN;
168 writel(cfg, dev->regs + FLITE_REG_CIWDOFST);
169
170 hoff2 = f->f_width - f->rect.width - f->rect.left;
171 voff2 = f->f_height - f->rect.height - f->rect.top;
172
173 cfg = (hoff2 << 16) | voff2;
174 writel(cfg, dev->regs + FLITE_REG_CIWDOFST2);
175}
176
177/* Select camera port (A, B) */
178static void flite_hw_set_camera_port(struct fimc_lite *dev, int id)
179{
180 u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL);
181 if (id == 0)
182 cfg &= ~FLITE_REG_CIGENERAL_CAM_B;
183 else
184 cfg |= FLITE_REG_CIGENERAL_CAM_B;
185 writel(cfg, dev->regs + FLITE_REG_CIGENERAL);
186}
187
188/* Select serial or parallel bus, camera port (A,B) and set signals polarity */
189void flite_hw_set_camera_bus(struct fimc_lite *dev,
190 struct s5p_fimc_isp_info *s_info)
191{
192 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
193 unsigned int flags = s_info->flags;
194
195 if (s_info->bus_type != FIMC_MIPI_CSI2) {
196 cfg &= ~(FLITE_REG_CIGCTRL_SELCAM_MIPI |
197 FLITE_REG_CIGCTRL_INVPOLPCLK |
198 FLITE_REG_CIGCTRL_INVPOLVSYNC |
199 FLITE_REG_CIGCTRL_INVPOLHREF);
200
201 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
202 cfg |= FLITE_REG_CIGCTRL_INVPOLPCLK;
203
204 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
205 cfg |= FLITE_REG_CIGCTRL_INVPOLVSYNC;
206
207 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
208 cfg |= FLITE_REG_CIGCTRL_INVPOLHREF;
209 } else {
210 cfg |= FLITE_REG_CIGCTRL_SELCAM_MIPI;
211 }
212
213 writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
214
215 flite_hw_set_camera_port(dev, s_info->mux_id);
216}
217
218void flite_hw_set_out_order(struct fimc_lite *dev, struct flite_frame *f)
219{
220 static const u32 pixcode[4][2] = {
221 { V4L2_MBUS_FMT_YUYV8_2X8, FLITE_REG_CIODMAFMT_YCBYCR },
222 { V4L2_MBUS_FMT_YVYU8_2X8, FLITE_REG_CIODMAFMT_YCRYCB },
223 { V4L2_MBUS_FMT_UYVY8_2X8, FLITE_REG_CIODMAFMT_CBYCRY },
224 { V4L2_MBUS_FMT_VYUY8_2X8, FLITE_REG_CIODMAFMT_CRYCBY },
225 };
226 u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);
227 unsigned int i = ARRAY_SIZE(pixcode);
228
229 while (i-- >= 0)
230 if (pixcode[i][0] == dev->fmt->mbus_code)
231 break;
232 cfg &= ~FLITE_REG_CIODMAFMT_YCBCR_ORDER_MASK;
233 writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT);
234}
235
236void flite_hw_set_dma_window(struct fimc_lite *dev, struct flite_frame *f)
237{
238 u32 cfg;
239
240 /* Maximum output pixel size */
241 cfg = readl(dev->regs + FLITE_REG_CIOCAN);
242 cfg &= ~FLITE_REG_CIOCAN_MASK;
243 cfg = (f->f_height << 16) | f->f_width;
244 writel(cfg, dev->regs + FLITE_REG_CIOCAN);
245
246 /* DMA offsets */
247 cfg = readl(dev->regs + FLITE_REG_CIOOFF);
248 cfg &= ~FLITE_REG_CIOOFF_MASK;
249 cfg |= (f->rect.top << 16) | f->rect.left;
250 writel(cfg, dev->regs + FLITE_REG_CIOOFF);
251}
252
253/* Enable/disable output DMA, set output pixel size and offsets (composition) */
254void flite_hw_set_output_dma(struct fimc_lite *dev, struct flite_frame *f,
255 bool enable)
256{
257 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
258
259 if (!enable) {
260 cfg |= FLITE_REG_CIGCTRL_ODMA_DISABLE;
261 writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
262 return;
263 }
264
265 cfg &= ~FLITE_REG_CIGCTRL_ODMA_DISABLE;
266 writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
267
268 flite_hw_set_out_order(dev, f);
269 flite_hw_set_dma_window(dev, f);
270}
271
272void flite_hw_dump_regs(struct fimc_lite *dev, const char *label)
273{
274 struct {
275 u32 offset;
276 const char * const name;
277 } registers[] = {
278 { 0x00, "CISRCSIZE" },
279 { 0x04, "CIGCTRL" },
280 { 0x08, "CIIMGCPT" },
281 { 0x0c, "CICPTSEQ" },
282 { 0x10, "CIWDOFST" },
283 { 0x14, "CIWDOFST2" },
284 { 0x18, "CIODMAFMT" },
285 { 0x20, "CIOCAN" },
286 { 0x24, "CIOOFF" },
287 { 0x30, "CIOSA" },
288 { 0x40, "CISTATUS" },
289 { 0x44, "CISTATUS2" },
290 { 0xf0, "CITHOLD" },
291 { 0xfc, "CIGENERAL" },
292 };
293 u32 i;
294
295 pr_info("--- %s ---\n", label);
296 for (i = 0; i < ARRAY_SIZE(registers); i++) {
297 u32 cfg = readl(dev->regs + registers[i].offset);
298 pr_info("%s: %s:\t0x%08x\n", __func__, registers[i].name, cfg);
299 }
300}
diff --git a/drivers/media/video/s5p-fimc/fimc-lite-reg.h b/drivers/media/video/s5p-fimc/fimc-lite-reg.h
new file mode 100644
index 000000000000..adb9e9e6f3c2
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-lite-reg.h
@@ -0,0 +1,150 @@
1/*
2 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef FIMC_LITE_REG_H_
10#define FIMC_LITE_REG_H_
11
12#include "fimc-lite.h"
13
14/* Camera Source size */
15#define FLITE_REG_CISRCSIZE 0x00
16#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR (0 << 14)
17#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB (1 << 14)
18#define FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY (2 << 14)
19#define FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY (3 << 14)
20#define FLITE_REG_CISRCSIZE_ORDER422_MASK (0x3 << 14)
21#define FLITE_REG_CISRCSIZE_SIZE_CAM_MASK (0x3fff << 16 | 0x3fff)
22
23/* Global control */
24#define FLITE_REG_CIGCTRL 0x04
25#define FLITE_REG_CIGCTRL_YUV422_1P (0x1e << 24)
26#define FLITE_REG_CIGCTRL_RAW8 (0x2a << 24)
27#define FLITE_REG_CIGCTRL_RAW10 (0x2b << 24)
28#define FLITE_REG_CIGCTRL_RAW12 (0x2c << 24)
29#define FLITE_REG_CIGCTRL_RAW14 (0x2d << 24)
30/* User defined formats. x = 0...15 */
31#define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24)
32#define FLITE_REG_CIGCTRL_FMT_MASK (0x3f << 24)
33#define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE (1 << 21)
34#define FLITE_REG_CIGCTRL_ODMA_DISABLE (1 << 20)
35#define FLITE_REG_CIGCTRL_SWRST_REQ (1 << 19)
36#define FLITE_REG_CIGCTRL_SWRST_RDY (1 << 18)
37#define FLITE_REG_CIGCTRL_SWRST (1 << 17)
38#define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR (1 << 15)
39#define FLITE_REG_CIGCTRL_INVPOLPCLK (1 << 14)
40#define FLITE_REG_CIGCTRL_INVPOLVSYNC (1 << 13)
41#define FLITE_REG_CIGCTRL_INVPOLHREF (1 << 12)
42/* Interrupts mask bits (1 disables an interrupt) */
43#define FLITE_REG_CIGCTRL_IRQ_LASTEN (1 << 8)
44#define FLITE_REG_CIGCTRL_IRQ_ENDEN (1 << 7)
45#define FLITE_REG_CIGCTRL_IRQ_STARTEN (1 << 6)
46#define FLITE_REG_CIGCTRL_IRQ_OVFEN (1 << 5)
47#define FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK (0xf << 5)
48#define FLITE_REG_CIGCTRL_SELCAM_MIPI (1 << 3)
49
50/* Image Capture Enable */
51#define FLITE_REG_CIIMGCPT 0x08
52#define FLITE_REG_CIIMGCPT_IMGCPTEN (1 << 31)
53#define FLITE_REG_CIIMGCPT_CPT_FREN (1 << 25)
54#define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT (1 << 18)
55#define FLITE_REG_CIIMGCPT_CPT_MOD_FREN (0 << 18)
56
57/* Capture Sequence */
58#define FLITE_REG_CICPTSEQ 0x0c
59
60/* Camera Window Offset */
61#define FLITE_REG_CIWDOFST 0x10
62#define FLITE_REG_CIWDOFST_WINOFSEN (1 << 31)
63#define FLITE_REG_CIWDOFST_CLROVIY (1 << 31)
64#define FLITE_REG_CIWDOFST_CLROVFICB (1 << 15)
65#define FLITE_REG_CIWDOFST_CLROVFICR (1 << 14)
66#define FLITE_REG_CIWDOFST_OFST_MASK ((0x1fff << 16) | 0x1fff)
67
68/* Camera Window Offset2 */
69#define FLITE_REG_CIWDOFST2 0x14
70
71/* Camera Output DMA Format */
72#define FLITE_REG_CIODMAFMT 0x18
73#define FLITE_REG_CIODMAFMT_RAW_CON (1 << 15)
74#define FLITE_REG_CIODMAFMT_PACK12 (1 << 14)
75#define FLITE_REG_CIODMAFMT_CRYCBY (0 << 4)
76#define FLITE_REG_CIODMAFMT_CBYCRY (1 << 4)
77#define FLITE_REG_CIODMAFMT_YCRYCB (2 << 4)
78#define FLITE_REG_CIODMAFMT_YCBYCR (3 << 4)
79#define FLITE_REG_CIODMAFMT_YCBCR_ORDER_MASK (0x3 << 4)
80
81/* Camera Output Canvas */
82#define FLITE_REG_CIOCAN 0x20
83#define FLITE_REG_CIOCAN_MASK ((0x3fff << 16) | 0x3fff)
84
85/* Camera Output DMA Offset */
86#define FLITE_REG_CIOOFF 0x24
87#define FLITE_REG_CIOOFF_MASK ((0x3fff << 16) | 0x3fff)
88
89/* Camera Output DMA Start Address */
90#define FLITE_REG_CIOSA 0x30
91
92/* Camera Status */
93#define FLITE_REG_CISTATUS 0x40
94#define FLITE_REG_CISTATUS_MIPI_VVALID (1 << 22)
95#define FLITE_REG_CISTATUS_MIPI_HVALID (1 << 21)
96#define FLITE_REG_CISTATUS_MIPI_DVALID (1 << 20)
97#define FLITE_REG_CISTATUS_ITU_VSYNC (1 << 14)
98#define FLITE_REG_CISTATUS_ITU_HREFF (1 << 13)
99#define FLITE_REG_CISTATUS_OVFIY (1 << 10)
100#define FLITE_REG_CISTATUS_OVFICB (1 << 9)
101#define FLITE_REG_CISTATUS_OVFICR (1 << 8)
102#define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW (1 << 7)
103#define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND (1 << 6)
104#define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART (1 << 5)
105#define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND (1 << 4)
106#define FLITE_REG_CISTATUS_IRQ_CAM (1 << 0)
107#define FLITE_REG_CISTATUS_IRQ_MASK (0xf << 4)
108
109/* Camera Status2 */
110#define FLITE_REG_CISTATUS2 0x44
111#define FLITE_REG_CISTATUS2_LASTCAPEND (1 << 1)
112#define FLITE_REG_CISTATUS2_FRMEND (1 << 0)
113
114/* Qos Threshold */
115#define FLITE_REG_CITHOLD 0xf0
116#define FLITE_REG_CITHOLD_W_QOS_EN (1 << 30)
117
118/* Camera General Purpose */
119#define FLITE_REG_CIGENERAL 0xfc
120/* b0: 1 - camera B, 0 - camera A */
121#define FLITE_REG_CIGENERAL_CAM_B (1 << 0)
122
123/* ----------------------------------------------------------------------------
124 * Function declarations
125 */
126void flite_hw_reset(struct fimc_lite *dev);
127void flite_hw_clear_pending_irq(struct fimc_lite *dev);
128u32 flite_hw_get_interrupt_source(struct fimc_lite *dev);
129void flite_hw_clear_last_capture_end(struct fimc_lite *dev);
130void flite_hw_set_interrupt_mask(struct fimc_lite *dev);
131void flite_hw_capture_start(struct fimc_lite *dev);
132void flite_hw_capture_stop(struct fimc_lite *dev);
133void flite_hw_set_camera_bus(struct fimc_lite *dev,
134 struct s5p_fimc_isp_info *s_info);
135void flite_hw_set_camera_polarity(struct fimc_lite *dev,
136 struct s5p_fimc_isp_info *cam);
137void flite_hw_set_window_offset(struct fimc_lite *dev, struct flite_frame *f);
138void flite_hw_set_source_format(struct fimc_lite *dev, struct flite_frame *f);
139
140void flite_hw_set_output_dma(struct fimc_lite *dev, struct flite_frame *f,
141 bool enable);
142void flite_hw_set_dma_window(struct fimc_lite *dev, struct flite_frame *f);
143void flite_hw_set_test_pattern(struct fimc_lite *dev, bool on);
144void flite_hw_dump_regs(struct fimc_lite *dev, const char *label);
145
146static inline void flite_hw_set_output_addr(struct fimc_lite *dev, u32 paddr)
147{
148 writel(paddr, dev->regs + FLITE_REG_CIOSA);
149}
150#endif /* FIMC_LITE_REG_H */
diff --git a/drivers/media/video/s5p-fimc/fimc-lite.h b/drivers/media/video/s5p-fimc/fimc-lite.h
new file mode 100644
index 000000000000..44424eee81d8
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-lite.h
@@ -0,0 +1,213 @@
1/*
2 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef FIMC_LITE_H_
10#define FIMC_LITE_H_
11
12#include <asm/sizes.h>
13#include <linux/io.h>
14#include <linux/irqreturn.h>
15#include <linux/platform_device.h>
16#include <linux/sched.h>
17#include <linux/spinlock.h>
18#include <linux/types.h>
19#include <linux/videodev2.h>
20
21#include <media/media-entity.h>
22#include <media/videobuf2-core.h>
23#include <media/v4l2-device.h>
24#include <media/v4l2-mediabus.h>
25#include <media/s5p_fimc.h>
26
27#include "fimc-core.h"
28
29#define FIMC_LITE_DRV_NAME "exynos-fimc-lite"
30#define FLITE_CLK_NAME "flite"
31#define FIMC_LITE_MAX_DEVS 2
32#define FLITE_REQ_BUFS_MIN 2
33
34/* Bit index definitions for struct fimc_lite::state */
35enum {
36 ST_FLITE_LPM,
37 ST_FLITE_PENDING,
38 ST_FLITE_RUN,
39 ST_FLITE_STREAM,
40 ST_FLITE_SUSPENDED,
41 ST_FLITE_OFF,
42 ST_FLITE_IN_USE,
43 ST_FLITE_CONFIG,
44 ST_SENSOR_STREAM,
45};
46
47#define FLITE_SD_PAD_SINK 0
48#define FLITE_SD_PAD_SOURCE 1
49#define FLITE_SD_PADS_NUM 2
50
51struct flite_variant {
52 unsigned short max_width;
53 unsigned short max_height;
54 unsigned short out_width_align;
55 unsigned short win_hor_offs_align;
56 unsigned short out_hor_offs_align;
57};
58
59struct flite_drvdata {
60 struct flite_variant *variant[FIMC_LITE_MAX_DEVS];
61};
62
63#define fimc_lite_get_drvdata(_pdev) \
64 ((struct flite_drvdata *) platform_get_device_id(_pdev)->driver_data)
65
66struct fimc_lite_events {
67 unsigned int data_overflow;
68};
69
70#define FLITE_MAX_PLANES 1
71
72/**
73 * struct flite_frame - source/target frame properties
74 * @f_width: full pixel width
75 * @f_height: full pixel height
76 * @rect: crop/composition rectangle
77 */
78struct flite_frame {
79 u16 f_width;
80 u16 f_height;
81 struct v4l2_rect rect;
82};
83
84/**
85 * struct flite_buffer - video buffer structure
86 * @vb: vb2 buffer
87 * @list: list head for the buffers queue
88 * @paddr: precalculated physical address
89 */
90struct flite_buffer {
91 struct vb2_buffer vb;
92 struct list_head list;
93 dma_addr_t paddr;
94};
95
96/**
97 * struct fimc_lite - fimc lite structure
98 * @pdev: pointer to FIMC-LITE platform device
99 * @variant: variant information for this IP
100 * @v4l2_dev: pointer to top the level v4l2_device
101 * @vfd: video device node
102 * @fh: v4l2 file handle
103 * @alloc_ctx: videobuf2 memory allocator context
104 * @subdev: FIMC-LITE subdev
105 * @vd_pad: media (sink) pad for the capture video node
106 * @subdev_pads: the subdev media pads
107 * @ctrl_handler: v4l2 control handler
108 * @test_pattern: test pattern controls
109 * @index: FIMC-LITE platform device index
110 * @pipeline: video capture pipeline data structure
111 * @slock: spinlock protecting this data structure and the hw registers
112 * @lock: mutex serializing video device and the subdev operations
113 * @clock: FIMC-LITE gate clock
114 * @regs: memory mapped io registers
115 * @irq_queue: interrupt handler waitqueue
116 * @fmt: pointer to color format description structure
117 * @payload: image size in bytes (w x h x bpp)
118 * @inp_frame: camera input frame structure
119 * @out_frame: DMA output frame structure
120 * @out_path: output data path (DMA or FIFO)
121 * @source_subdev_grp_id: source subdev group id
122 * @state: driver state flags
123 * @pending_buf_q: pending buffers queue head
124 * @active_buf_q: the queue head of buffers scheduled in hardware
125 * @vb_queue: vb2 buffers queue
126 * @active_buf_count: number of video buffers scheduled in hardware
127 * @frame_count: the captured frames counter
128 * @reqbufs_count: the number of buffers requested with REQBUFS ioctl
129 * @ref_count: driver's private reference counter
130 */
131struct fimc_lite {
132 struct platform_device *pdev;
133 struct flite_variant *variant;
134 struct v4l2_device *v4l2_dev;
135 struct video_device *vfd;
136 struct v4l2_fh fh;
137 struct vb2_alloc_ctx *alloc_ctx;
138 struct v4l2_subdev subdev;
139 struct media_pad vd_pad;
140 struct media_pad subdev_pads[FLITE_SD_PADS_NUM];
141 struct v4l2_ctrl_handler ctrl_handler;
142 struct v4l2_ctrl *test_pattern;
143 u32 index;
144 struct fimc_pipeline pipeline;
145
146 struct mutex lock;
147 spinlock_t slock;
148
149 struct clk *clock;
150 void __iomem *regs;
151 wait_queue_head_t irq_queue;
152
153 const struct fimc_fmt *fmt;
154 unsigned long payload[FLITE_MAX_PLANES];
155 struct flite_frame inp_frame;
156 struct flite_frame out_frame;
157 enum fimc_datapath out_path;
158 unsigned int source_subdev_grp_id;
159
160 unsigned long state;
161 struct list_head pending_buf_q;
162 struct list_head active_buf_q;
163 struct vb2_queue vb_queue;
164 unsigned int frame_count;
165 unsigned int reqbufs_count;
166 int ref_count;
167
168 struct fimc_lite_events events;
169};
170
171static inline bool fimc_lite_active(struct fimc_lite *fimc)
172{
173 unsigned long flags;
174 bool ret;
175
176 spin_lock_irqsave(&fimc->slock, flags);
177 ret = fimc->state & (1 << ST_FLITE_RUN) ||
178 fimc->state & (1 << ST_FLITE_PENDING);
179 spin_unlock_irqrestore(&fimc->slock, flags);
180 return ret;
181}
182
183static inline void fimc_lite_active_queue_add(struct fimc_lite *dev,
184 struct flite_buffer *buf)
185{
186 list_add_tail(&buf->list, &dev->active_buf_q);
187}
188
189static inline struct flite_buffer *fimc_lite_active_queue_pop(
190 struct fimc_lite *dev)
191{
192 struct flite_buffer *buf = list_entry(dev->active_buf_q.next,
193 struct flite_buffer, list);
194 list_del(&buf->list);
195 return buf;
196}
197
198static inline void fimc_lite_pending_queue_add(struct fimc_lite *dev,
199 struct flite_buffer *buf)
200{
201 list_add_tail(&buf->list, &dev->pending_buf_q);
202}
203
204static inline struct flite_buffer *fimc_lite_pending_queue_pop(
205 struct fimc_lite *dev)
206{
207 struct flite_buffer *buf = list_entry(dev->pending_buf_q.next,
208 struct flite_buffer, list);
209 list_del(&buf->list);
210 return buf;
211}
212
213#endif /* FIMC_LITE_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 21:52:56 -0500