[media] s5p-fimc: Add FIMC-LITE register definitions

Add register definitions and register API for FIMC-LITE devices.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

3 files changed, 663 insertions, 0 deletions

diff --git a/drivers/media/video/s5p-fimc/fimc-lite-reg.c b/drivers/media/video/s5p-fimc/fimc-lite-reg.c
new file mode 100644
index 000000000000..419adfb7cdf9
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-lite-reg.c
@@ -0,0 +1,300 @@
+/*
+ * Register interface file for EXYNOS FIMC-LITE (camera interface) driver
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Sylwester Nawrocki <s.nawrocki@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <media/s5p_fimc.h>
+
+#include "fimc-lite-reg.h"
+#include "fimc-lite.h"
+#include "fimc-core.h"
+
+#define FLITE_RESET_TIMEOUT 50 /* in ms */
+
+void flite_hw_reset(struct fimc_lite *dev)
+{
+        unsigned long end = jiffies + msecs_to_jiffies(FLITE_RESET_TIMEOUT);
+        u32 cfg;
+
+        cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+        cfg |= FLITE_REG_CIGCTRL_SWRST_REQ;
+        writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+
+        while (time_is_after_jiffies(end)) {
+                cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+                if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY)
+                        break;
+                usleep_range(1000, 5000);
+        }
+
+        cfg |= FLITE_REG_CIGCTRL_SWRST;
+        writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+void flite_hw_clear_pending_irq(struct fimc_lite *dev)
+{
+        u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS);
+        cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM;
+        writel(cfg, dev->regs + FLITE_REG_CISTATUS);
+}
+
+u32 flite_hw_get_interrupt_source(struct fimc_lite *dev)
+{
+        u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS);
+        return intsrc & FLITE_REG_CISTATUS_IRQ_MASK;
+}
+
+void flite_hw_clear_last_capture_end(struct fimc_lite *dev)
+{
+
+        u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2);
+        cfg &= ~FLITE_REG_CISTATUS2_LASTCAPEND;
+        writel(cfg, dev->regs + FLITE_REG_CISTATUS2);
+}
+
+void flite_hw_set_interrupt_mask(struct fimc_lite *dev)
+{
+        u32 cfg, intsrc;
+
+        /* Select interrupts to be enabled for each output mode */
+        if (dev->out_path == FIMC_IO_DMA) {
+                intsrc = FLITE_REG_CIGCTRL_IRQ_OVFEN |
+                         FLITE_REG_CIGCTRL_IRQ_LASTEN |
+                         FLITE_REG_CIGCTRL_IRQ_STARTEN;
+        } else {
+                /* An output to the FIMC-IS */
+                intsrc = FLITE_REG_CIGCTRL_IRQ_OVFEN |
+                         FLITE_REG_CIGCTRL_IRQ_LASTEN;
+        }
+
+        cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+        cfg |= FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK;
+        cfg &= ~intsrc;
+        writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+void flite_hw_capture_start(struct fimc_lite *dev)
+{
+        u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);
+        cfg |= FLITE_REG_CIIMGCPT_IMGCPTEN;
+        writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
+}
+
+void flite_hw_capture_stop(struct fimc_lite *dev)
+{
+        u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);
+        cfg &= ~FLITE_REG_CIIMGCPT_IMGCPTEN;
+        writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
+}
+
+/*
+ * Test pattern (color bars) enable/disable. External sensor
+ * pixel clock must be active for the test pattern to work.
+ */
+void flite_hw_set_test_pattern(struct fimc_lite *dev, bool on)
+{
+        u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+        if (on)
+                cfg |= FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR;
+        else
+                cfg &= ~FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR;
+        writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+}
+
+static const u32 src_pixfmt_map[8][3] = {
+        { V4L2_MBUS_FMT_YUYV8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR,
+          FLITE_REG_CIGCTRL_YUV422_1P },
+        { V4L2_MBUS_FMT_YVYU8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB,
+          FLITE_REG_CIGCTRL_YUV422_1P },
+        { V4L2_MBUS_FMT_UYVY8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY,
+          FLITE_REG_CIGCTRL_YUV422_1P },
+        { V4L2_MBUS_FMT_VYUY8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY,
+          FLITE_REG_CIGCTRL_YUV422_1P },
+        { V4L2_PIX_FMT_SGRBG8, 0, FLITE_REG_CIGCTRL_RAW8 },
+        { V4L2_PIX_FMT_SGRBG10, 0, FLITE_REG_CIGCTRL_RAW10 },
+        { V4L2_PIX_FMT_SGRBG12, 0, FLITE_REG_CIGCTRL_RAW12 },
+        { V4L2_MBUS_FMT_JPEG_1X8, 0, FLITE_REG_CIGCTRL_USER(1) },
+};
+
+/* Set camera input pixel format and resolution */
+void flite_hw_set_source_format(struct fimc_lite *dev, struct flite_frame *f)
+{
+        enum v4l2_mbus_pixelcode pixelcode = dev->fmt->mbus_code;
+        unsigned int i = ARRAY_SIZE(src_pixfmt_map);
+        u32 cfg;
+
+        while (i-- >= 0) {
+                if (src_pixfmt_map[i][0] == pixelcode)
+                        break;
+        }
+
+        if (i == 0 && src_pixfmt_map[i][0] != pixelcode) {
+                v4l2_err(dev->vfd,
+                         "Unsupported pixel code, falling back to %#08x\n",
+                         src_pixfmt_map[i][0]);
+        }
+
+        cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
+        cfg &= ~FLITE_REG_CIGCTRL_FMT_MASK;
+        cfg |= src_pixfmt_map[i][2];
+        writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
+
+        cfg = readl(dev->regs + FLITE_REG_CISRCSIZE);
+        cfg &= ~(FLITE_REG_CISRCSIZE_ORDER422_MASK |
+                 FLITE_REG_CISRCSIZE_SIZE_CAM_MASK);
+        cfg |= (f->f_width << 16) | f->f_height;
+        cfg |= src_pixfmt_map[i][1];
+        writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);
+}
+
+/* Set the camera host input window offsets (cropping) */
+void flite_hw_set_window_offset(struct fimc_lite *dev, struct flite_frame *f)
+{
+        u32 hoff2, voff2;
+        u32 cfg;
+
+        cfg = readl(dev->regs + FLITE_REG_CIWDOFST);
+        cfg &= ~FLITE_REG_CIWDOFST_OFST_MASK;
+        cfg |= (f->rect.left << 16) | f->rect.top;
+        cfg |= FLITE_REG_CIWDOFST_WINOFSEN;
+        writel(cfg, dev->regs + FLITE_REG_CIWDOFST);
+
+        hoff2 = f->f_width - f->rect.width - f->rect.left;
+        voff2 = f->f_height - f->rect.height - f->rect.top;
+
+        cfg = (hoff2 << 16) | voff2;
+        writel(cfg, dev->regs + FLITE_REG_CIWDOFST2);
+}
+
+/* Select camera port (A, B) */
+static void flite_hw_set_camera_port(struct fimc_lite *dev, int id)
+{
+        u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL);
+        if (id == 0)