[media] s5p-fimc: Refactor the register interface functions

Simplify the register API and use FIMC_REG_ prefix for all register
definitions for consistency with FIMC-LITE. The unused image effect
defines are removed.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

7 files changed, 641 insertions, 681 deletions

diff --git a/drivers/media/video/s5p-fimc/fimc-capture.c b/drivers/media/video/s5p-fimc/fimc-capture.c
index b45da2780213..52a5fb469b45 100644
--- a/drivers/media/video/s5p-fimc/fimc-capture.c
+++ b/drivers/media/video/s5p-fimc/fimc-capture.c
@@ -29,6 +29,7 @@
 
 #include "fimc-mdevice.h"
 #include "fimc-core.h"
+#include "fimc-reg.h"
 
 static int fimc_init_capture(struct fimc_dev *fimc)
 {
diff --git a/drivers/media/video/s5p-fimc/fimc-core.c b/drivers/media/video/s5p-fimc/fimc-core.c
index add24cd373a5..afd69e3d44c2 100644
--- a/drivers/media/video/s5p-fimc/fimc-core.c
+++ b/drivers/media/video/s5p-fimc/fimc-core.c
@@ -28,6 +28,7 @@
 #include <media/videobuf2-dma-contig.h>
 
 #include "fimc-core.h"
+#include "fimc-reg.h"
 #include "fimc-mdevice.h"
 
 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
@@ -388,40 +389,40 @@ int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 void fimc_set_yuv_order(struct fimc_ctx *ctx)
 {
         /* The one only mode supported in SoC. */
-        ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
-        ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
+        ctx->in_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
+        ctx->out_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
 
         /* Set order for 1 plane input formats. */
         switch (ctx->s_frame.fmt->color) {
         case S5P_FIMC_YCRYCB422:
-                ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
+                ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY;
                 break;
         case S5P_FIMC_CBYCRY422:
-                ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
+                ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB;
                 break;
         case S5P_FIMC_CRYCBY422:
-                ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
+                ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR;
                 break;
         case S5P_FIMC_YCBYCR422:
         default:
-                ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
+                ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY;
                 break;
         }
         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 
         switch (ctx->d_frame.fmt->color) {
         case S5P_FIMC_YCRYCB422:
-                ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
+                ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY;
                 break;
         case S5P_FIMC_CBYCRY422:
-                ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
+                ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB;
                 break;
         case S5P_FIMC_CRYCBY422:
-                ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
+                ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR;
                 break;
         case S5P_FIMC_YCBYCR422:
         default:
-                ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
+                ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY;
                 break;
         }
         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
diff --git a/drivers/media/video/s5p-fimc/fimc-core.h b/drivers/media/video/s5p-fimc/fimc-core.h
index ef7c6a23ca2a..34fbba424692 100644
--- a/drivers/media/video/s5p-fimc/fimc-core.h
+++ b/drivers/media/video/s5p-fimc/fimc-core.h
@@ -26,8 +26,6 @@
 #include <media/v4l2-mediabus.h>
 #include <media/s5p_fimc.h>
 
-#include "regs-fimc.h"
-
 #define err(fmt, args...) \
         printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
 
@@ -106,17 +104,6 @@ enum fimc_color_fmt {
 #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
                         __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
 
-/* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
-#define S5P_FIMC_LSB_CRCB       S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
-
-/* The embedded image effect selection */
-#define S5P_FIMC_EFFECT_ORIGINAL        S5P_CIIMGEFF_FIN_BYPASS
-#define S5P_FIMC_EFFECT_ARBITRARY       S5P_CIIMGEFF_FIN_ARBITRARY
-#define S5P_FIMC_EFFECT_NEGATIVE        S5P_CIIMGEFF_FIN_NEGATIVE
-#define S5P_FIMC_EFFECT_ARTFREEZE       S5P_CIIMGEFF_FIN_ARTFREEZE
-#define S5P_FIMC_EFFECT_EMBOSSING       S5P_CIIMGEFF_FIN_EMBOSSING
-#define S5P_FIMC_EFFECT_SIKHOUETTE      S5P_CIIMGEFF_FIN_SILHOUETTE
-
 /* The hardware context state. */
 #define FIMC_PARAMS             (1 << 0)
 #define FIMC_SRC_FMT            (1 << 3)
@@ -588,54 +575,6 @@ static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
         };
 }
 
-static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
-{
-        u32 cfg = readl(dev->regs + S5P_CIGCTRL);
-        cfg |= S5P_CIGCTRL_IRQ_CLR;
-        writel(cfg, dev->regs + S5P_CIGCTRL);
-}
-
-static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
-{
-        u32 cfg = readl(dev->regs + S5P_CISCCTRL);
-        if (on)
-                cfg |= S5P_CISCCTRL_SCALERSTART;
-        else
-                cfg &= ~S5P_CISCCTRL_SCALERSTART;
-        writel(cfg, dev->regs + S5P_CISCCTRL);
-}
-
-static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
-{
-        u32 cfg = readl(dev->regs + S5P_MSCTRL);
-        if (on)
-                cfg |= S5P_MSCTRL_ENVID;
-        else
-                cfg &= ~S5P_MSCTRL_ENVID;
-        writel(cfg, dev->regs + S5P_MSCTRL);
-}
-
-static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
-{
-        u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
-        cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
-        writel(cfg, dev->regs + S5P_CIIMGCPT);
-}
-
-/**
- * fimc_hw_set_dma_seq - configure output DMA buffer sequence
- * @mask: each bit corresponds to one of 32 output buffer registers set
- *        1 to include buffer in the sequence, 0 to disable
- *
- * This function mask output DMA ring buffers, i.e. it allows to configure
- * which of the output buffer address registers will be used by the DMA
- * engine.
- */
-static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)