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authorHarald Welte <laforge@gnumonks.org>2009-09-22 19:47:35 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-23 10:39:53 -0400
commit0306ab11c396f93056009152464ff104e4721817 (patch)
treeb4b2586011d0b2669a2c02897795aacdb74d31d8 /drivers/video/via/hw.h
parent5ff32f69e75deca5ee1a2f421ca8a3e43cfaa339 (diff)
viafb: add support for the VX855 chipset
Add support for a new VIA integrated graphics chipset, the VX855. Signed-off-by: HaraldWelte <HaraldWelte@viatech.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Cc: Scott Fang <ScottFang@viatech.com.cn> Cc: Joseph Chan <JosephChan@via.com.tw> Cc: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/via/hw.h')
-rw-r--r--drivers/video/via/hw.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index 7302b403e453..4e54b2f92d0f 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -324,6 +324,17 @@ is reserved, so it may have problem to set 1600x1200 on IGA2. */
324/* location: {CR94,0,6} */ 324/* location: {CR94,0,6} */
325#define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 325#define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
326 326
327/* For VT3409 */
328#define VX855_IGA1_FIFO_MAX_DEPTH 400
329#define VX855_IGA1_FIFO_THRESHOLD 320
330#define VX855_IGA1_FIFO_HIGH_THRESHOLD 320
331#define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160
332
333#define VX855_IGA2_FIFO_MAX_DEPTH 200
334#define VX855_IGA2_FIFO_THRESHOLD 160
335#define VX855_IGA2_FIFO_HIGH_THRESHOLD 160
336#define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320
337
327#define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1 338#define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1
328#define IGA1_FIFO_THRESHOLD_REG_NUM 2 339#define IGA1_FIFO_THRESHOLD_REG_NUM 2
329#define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2 340#define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2
@@ -688,6 +699,7 @@ struct pll_map {
688 u32 cle266_pll; 699 u32 cle266_pll;
689 u32 k800_pll; 700 u32 k800_pll;
690 u32 cx700_pll; 701 u32 cx700_pll;
702 u32 vx855_pll;
691}; 703};
692 704
693struct rgbLUT { 705struct rgbLUT {
@@ -832,6 +844,8 @@ struct iga2_crtc_timing {
832#define P4M900_FUNCTION3 0x3364 844#define P4M900_FUNCTION3 0x3364
833/* VT3353 chipset*/ 845/* VT3353 chipset*/
834#define VX800_FUNCTION3 0x3353 846#define VX800_FUNCTION3 0x3353
847/* VT3409 chipset*/
848#define VX855_FUNCTION3 0x3409
835 849
836#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value) 850#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
837 851