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authorHarald Welte <laforge@gnumonks.org>2009-09-22 19:47:35 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-23 10:39:53 -0400
commit0306ab11c396f93056009152464ff104e4721817 (patch)
treeb4b2586011d0b2669a2c02897795aacdb74d31d8
parent5ff32f69e75deca5ee1a2f421ca8a3e43cfaa339 (diff)
viafb: add support for the VX855 chipset
Add support for a new VIA integrated graphics chipset, the VX855. Signed-off-by: HaraldWelte <HaraldWelte@viatech.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Cc: Scott Fang <ScottFang@viatech.com.cn> Cc: Joseph Chan <JosephChan@via.com.tw> Cc: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat
-rw-r--r--drivers/video/via/chip.h3
-rw-r--r--drivers/video/via/hw.c208
-rw-r--r--drivers/video/via/hw.h14
-rw-r--r--drivers/video/via/share.h98
-rw-r--r--drivers/video/via/viafbdev.c3
-rw-r--r--drivers/video/via/viamode.c55
-rw-r--r--drivers/video/via/viamode.h2
7 files changed, 314 insertions, 69 deletions
diff --git a/drivers/video/via/chip.h b/drivers/video/via/chip.h
index 7f959676760c..474f428aea92 100644
--- a/drivers/video/via/chip.h
+++ b/drivers/video/via/chip.h
@@ -68,6 +68,9 @@
68#define UNICHROME_VX800 11 68#define UNICHROME_VX800 11
69#define UNICHROME_VX800_DID 0x1122 69#define UNICHROME_VX800_DID 0x1122
70 70
71#define UNICHROME_VX855 12
72#define UNICHROME_VX855_DID 0x5122
73
71/**************************************************/ 74/**************************************************/
72/* Definition TMDS Trasmitter Information */ 75/* Definition TMDS Trasmitter Information */
73/**************************************************/ 76/**************************************************/
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 4910561a9d34..95faf8be47aa 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -33,106 +33,147 @@ static const struct pci_device_id_info pciidlist[] = {
33 {PCI_VIA_VENDOR_ID, UNICHROME_P4M900_DID, UNICHROME_P4M900}, 33 {PCI_VIA_VENDOR_ID, UNICHROME_P4M900_DID, UNICHROME_P4M900},
34 {PCI_VIA_VENDOR_ID, UNICHROME_CN750_DID, UNICHROME_CN750}, 34 {PCI_VIA_VENDOR_ID, UNICHROME_CN750_DID, UNICHROME_CN750},
35 {PCI_VIA_VENDOR_ID, UNICHROME_VX800_DID, UNICHROME_VX800}, 35 {PCI_VIA_VENDOR_ID, UNICHROME_VX800_DID, UNICHROME_VX800},
36 {PCI_VIA_VENDOR_ID, UNICHROME_VX855_DID, UNICHROME_VX855},
36 {0, 0, 0} 37 {0, 0, 0}
37}; 38};
38 39
39static struct pll_map pll_value[] = { 40static struct pll_map pll_value[] = {
40 {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, CX700_25_175M}, 41 {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
41 {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, CX700_29_581M}, 42 CX700_25_175M, VX855_25_175M},
42 {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M, CX700_26_880M}, 43 {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
43 {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M, CX700_31_490M}, 44 CX700_29_581M, VX855_29_581M},
44 {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M, CX700_31_500M}, 45 {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
45 {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M, CX700_31_728M}, 46 CX700_26_880M, VX855_26_880M},
46 {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M, CX700_32_668M}, 47 {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
47 {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M, CX700_36_000M}, 48 CX700_31_490M, VX855_31_490M},
48 {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M, CX700_40_000M}, 49 {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
49 {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M, CX700_41_291M}, 50 CX700_31_500M, VX855_31_500M},
50 {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M, CX700_43_163M}, 51 {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
51 {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M, CX700_45_250M}, 52 CX700_31_728M, VX855_31_728M},
52 {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M, CX700_46_000M}, 53 {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
53 {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M, CX700_46_996M}, 54 CX700_32_668M, VX855_32_668M},
54 {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M, CX700_48_000M}, 55 {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
55 {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M, CX700_48_875M}, 56 CX700_36_000M, VX855_36_000M},
56 {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M, CX700_49_500M}, 57 {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
57 {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M, CX700_52_406M}, 58 CX700_40_000M, VX855_40_000M},
58 {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M, CX700_52_977M}, 59 {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
59 {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, CX700_56_250M}, 60 CX700_41_291M, VX855_41_291M},
60 {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M, CX700_60_466M}, 61 {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
61 {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M, CX700_61_500M}, 62 CX700_43_163M, VX855_43_163M},
62 {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M, CX700_65_000M}, 63 {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
63 {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M, CX700_65_178M}, 64 CX700_45_250M, VX855_45_250M},
64 {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M, CX700_66_750M}, 65 {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
65 {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M, CX700_68_179M}, 66 CX700_46_000M, VX855_46_000M},
66 {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M, CX700_69_924M}, 67 {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
67 {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M, CX700_70_159M}, 68 CX700_46_996M, VX855_46_996M},
68 {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M, CX700_72_000M}, 69 {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
69 {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M, CX700_78_750M}, 70 CX700_48_000M, VX855_48_000M},
70 {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M, CX700_80_136M}, 71 {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
71 {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M, CX700_83_375M}, 72 CX700_48_875M, VX855_48_875M},
72 {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M, CX700_83_950M}, 73 {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
73 {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M, CX700_84_750M}, 74 CX700_49_500M, VX855_49_500M},
74 {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M, CX700_85_860M}, 75 {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
75 {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M, CX700_88_750M}, 76 CX700_52_406M, VX855_52_406M},
76 {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M, CX700_94_500M}, 77 {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
77 {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M, CX700_97_750M}, 78 CX700_52_977M, VX855_52_977M},
79 {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
80 CX700_56_250M, VX855_56_250M},
81 {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
82 CX700_60_466M, VX855_60_466M},
83 {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
84 CX700_61_500M, VX855_61_500M},
85 {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
86 CX700_65_000M, VX855_65_000M},
87 {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
88 CX700_65_178M, VX855_65_178M},
89 {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
90 CX700_66_750M, VX855_66_750M},
91 {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
92 CX700_68_179M, VX855_68_179M},
93 {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
94 CX700_69_924M, VX855_69_924M},
95 {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
96 CX700_70_159M, VX855_70_159M},
97 {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
98 CX700_72_000M, VX855_72_000M},
99 {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
100 CX700_78_750M, VX855_78_750M},
101 {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
102 CX700_80_136M, VX855_80_136M},
103 {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
104 CX700_83_375M, VX855_83_375M},
105 {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
106 CX700_83_950M, VX855_83_950M},
107 {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
108 CX700_84_750M, VX855_84_750M},
109 {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
110 CX700_85_860M, VX855_85_860M},
111 {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
112 CX700_88_750M, VX855_88_750M},
113 {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
114 CX700_94_500M, VX855_94_500M},
115 {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
116 CX700_97_750M, VX855_97_750M},
78 {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M, 117 {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
79 CX700_101_000M}, 118 CX700_101_000M, VX855_101_000M},
80 {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M, 119 {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
81 CX700_106_500M}, 120 CX700_106_500M, VX855_106_500M},
82 {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M, 121 {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
83 CX700_108_000M}, 122 CX700_108_000M, VX855_108_000M},
84 {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M, 123 {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
85 CX700_113_309M}, 124 CX700_113_309M, VX855_113_309M},
86 {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M, 125 {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
87 CX700_118_840M}, 126 CX700_118_840M, VX855_118_840M},
88 {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M, 127 {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
89 CX700_119_000M}, 128 CX700_119_000M, VX855_119_000M},
90 {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M, 129 {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
91 CX700_121_750M}, 130 CX700_121_750M, 0},
92 {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M, 131 {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
93 CX700_125_104M}, 132 CX700_125_104M, 0},
94 {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M, 133 {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
95 CX700_133_308M}, 134 CX700_133_308M, 0},
96 {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M, 135 {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
97 CX700_135_000M}, 136 CX700_135_000M, VX855_135_000M},
98 {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M, 137 {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
99 CX700_136_700M}, 138 CX700_136_700M, VX855_136_700M},
100 {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M, 139 {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
101 CX700_138_400M}, 140 CX700_138_400M, VX855_138_400M},
102 {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M, 141 {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
103 CX700_146_760M}, 142 CX700_146_760M, VX855_146_760M},
104 {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M, 143 {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
105 CX700_153_920M}, 144 CX700_153_920M, VX855_153_920M},
106 {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M, 145 {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
107 CX700_156_000M}, 146 CX700_156_000M, VX855_156_000M},
108 {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M, 147 {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
109 CX700_157_500M}, 148 CX700_157_500M, VX855_157_500M},
110 {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M, 149 {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
111 CX700_162_000M}, 150 CX700_162_000M, VX855_162_000M},
112 {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M, 151 {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
113 CX700_187_000M}, 152 CX700_187_000M, VX855_187_000M},
114 {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M, 153 {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
115 CX700_193_295M}, 154 CX700_193_295M, VX855_193_295M},
116 {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M, 155 {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
117 CX700_202_500M}, 156 CX700_202_500M, VX855_202_500M},
118 {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M, 157 {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
119 CX700_204_000M}, 158 CX700_204_000M, VX855_204_000M},
120 {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M, 159 {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
121 CX700_218_500M}, 160 CX700_218_500M, VX855_218_500M},
122 {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M, 161 {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
123 CX700_234_000M}, 162 CX700_234_000M, VX855_234_000M},
124 {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M, 163 {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
125 CX700_267_250M}, 164 CX700_267_250M, VX855_267_250M},
126 {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M, 165 {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
127 CX700_297_500M}, 166 CX700_297_500M, VX855_297_500M},
128 {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M, CX700_74_481M}, 167 {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
168 CX700_74_481M, VX855_74_481M},
129 {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M, 169 {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
130 CX700_172_798M}, 170 CX700_172_798M, VX855_172_798M},
131 {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M, 171 {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
132 CX700_122_614M}, 172 CX700_122_614M, VX855_122_614M},
133 {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M, CX700_74_270M}, 173 {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
174 CX700_74_270M, 0},
134 {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M, 175 {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
135 CX700_148_500M} 176 CX700_148_500M, VX855_148_500M}
136}; 177};
137 178
138static struct fifo_depth_select display_fifo_depth_reg = { 179static struct fifo_depth_select display_fifo_depth_reg = {
@@ -1219,6 +1260,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1219 VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; 1260 VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1220 } 1261 }
1221 1262
1263 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1264 iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1265 iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1266 iga1_fifo_high_threshold =
1267 VX855_IGA1_FIFO_HIGH_THRESHOLD;
1268 iga1_display_queue_expire_num =
1269 VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1270 }
1271
1222 /* Set Display FIFO Depath Select */ 1272 /* Set Display FIFO Depath Select */
1223 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); 1273 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1224 viafb_load_reg_num = 1274 viafb_load_reg_num =
@@ -1350,6 +1400,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1350 VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; 1400 VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1351 } 1401 }
1352 1402
1403 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1404 iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1405 iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1406 iga2_fifo_high_threshold =
1407 VX855_IGA2_FIFO_HIGH_THRESHOLD;
1408 iga2_display_queue_expire_num =
1409 VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1410 }
1411
1353 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { 1412 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1354 /* Set Display FIFO Depath Select */ 1413 /* Set Display FIFO Depath Select */
1355 reg_value = 1414 reg_value =
@@ -1438,6 +1497,8 @@ u32 viafb_get_clk_value(int clk)
1438 case UNICHROME_P4M900: 1497 case UNICHROME_P4M900:
1439 case UNICHROME_VX800: 1498 case UNICHROME_VX800:
1440 return pll_value[i].cx700_pll; 1499 return pll_value[i].cx700_pll;
1500 case UNICHROME_VX855:
1501 return pll_value[i].vx855_pll;
1441 } 1502 }
1442 } 1503 }
1443 } 1504 }
@@ -1471,6 +1532,7 @@ void viafb_set_vclock(u32 CLK, int set_iga)
1471 case UNICHROME_P4M890: 1532 case UNICHROME_P4M890:
1472 case UNICHROME_P4M900: 1533 case UNICHROME_P4M900:
1473 case UNICHROME_VX800: 1534 case UNICHROME_VX800:
1535 case UNICHROME_VX855:
1474 viafb_write_reg(SR44, VIASR, CLK / 0x10000); 1536 viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1475 DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000); 1537 DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1476 viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100); 1538 viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
@@ -1499,6 +1561,7 @@ void viafb_set_vclock(u32 CLK, int set_iga)
1499 case UNICHROME_P4M890: 1561 case UNICHROME_P4M890:
1500 case UNICHROME_P4M900: 1562 case UNICHROME_P4M900:
1501 case UNICHROME_VX800: 1563 case UNICHROME_VX800:
1564 case UNICHROME_VX855:
1502 viafb_write_reg(SR4A, VIASR, CLK / 0x10000); 1565 viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1503 viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100); 1566 viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1504 viafb_write_reg(SR4C, VIASR, CLK % 0x100); 1567 viafb_write_reg(SR4C, VIASR, CLK % 0x100);
@@ -2215,6 +2278,10 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2215 case UNICHROME_VX800: 2278 case UNICHROME_VX800:
2216 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs); 2279 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2217 break; 2280 break;
2281
2282 case UNICHROME_VX855:
2283 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2284 break;
2218 } 2285 }
2219 2286
2220 device_off(); 2287 device_off();
@@ -2597,6 +2664,7 @@ static int get_fb_size_from_pci(void)
2597 case P4M890_FUNCTION3: 2664 case P4M890_FUNCTION3:
2598 case P4M900_FUNCTION3: 2665 case P4M900_FUNCTION3:
2599 case VX800_FUNCTION3: 2666 case VX800_FUNCTION3:
2667 case VX855_FUNCTION3:
2600 /*case CN750_FUNCTION3: */ 2668 /*case CN750_FUNCTION3: */
2601 outl(configid + 0xA0, (unsigned long)0xCF8); 2669 outl(configid + 0xA0, (unsigned long)0xCF8);
2602 FBSize = inl((unsigned long)0xCFC); 2670 FBSize = inl((unsigned long)0xCFC);
@@ -2660,6 +2728,10 @@ static int get_fb_size_from_pci(void)
2660 VideoMemSize = (256 << 20); /*256M */ 2728 VideoMemSize = (256 << 20); /*256M */
2661 break; 2729 break;
2662 2730
2731 case 0x00007000: /* Only on VX855/875 */
2732 VideoMemSize = (512 << 20); /*512M */
2733 break;
2734
2663 default: 2735 default:
2664 VideoMemSize = (32 << 20); /*32M */ 2736 VideoMemSize = (32 << 20); /*32M */
2665 break; 2737 break;
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index 7302b403e453..4e54b2f92d0f 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -324,6 +324,17 @@ is reserved, so it may have problem to set 1600x1200 on IGA2. */
324/* location: {CR94,0,6} */ 324/* location: {CR94,0,6} */
325#define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 325#define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
326 326
327/* For VT3409 */
328#define VX855_IGA1_FIFO_MAX_DEPTH 400
329#define VX855_IGA1_FIFO_THRESHOLD 320
330#define VX855_IGA1_FIFO_HIGH_THRESHOLD 320
331#define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160
332
333#define VX855_IGA2_FIFO_MAX_DEPTH 200
334#define VX855_IGA2_FIFO_THRESHOLD 160
335#define VX855_IGA2_FIFO_HIGH_THRESHOLD 160
336#define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320
337
327#define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1 338#define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1
328#define IGA1_FIFO_THRESHOLD_REG_NUM 2 339#define IGA1_FIFO_THRESHOLD_REG_NUM 2
329#define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2 340#define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2
@@ -688,6 +699,7 @@ struct pll_map {
688 u32 cle266_pll; 699 u32 cle266_pll;
689 u32 k800_pll; 700 u32 k800_pll;
690 u32 cx700_pll; 701 u32 cx700_pll;
702 u32 vx855_pll;
691}; 703};
692 704
693struct rgbLUT { 705struct rgbLUT {
@@ -832,6 +844,8 @@ struct iga2_crtc_timing {
832#define P4M900_FUNCTION3 0x3364 844#define P4M900_FUNCTION3 0x3364
833/* VT3353 chipset*/ 845/* VT3353 chipset*/
834#define VX800_FUNCTION3 0x3353 846#define VX800_FUNCTION3 0x3353
847/* VT3409 chipset*/
848#define VX855_FUNCTION3 0x3409
835 849
836#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value) 850#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
837 851
diff --git a/drivers/video/via/share.h b/drivers/video/via/share.h
index 2e1254da9c8c..7cd03e2a1275 100644
--- a/drivers/video/via/share.h
+++ b/drivers/video/via/share.h
@@ -167,6 +167,10 @@
167#define SR4B 0x4B 167#define SR4B 0x4B
168#define SR4C 0x4C 168#define SR4C 0x4C
169#define SR52 0x52 169#define SR52 0x52
170#define SR57 0x57
171#define SR58 0x58
172#define SR59 0x59
173#define SR5D 0x5D
170#define SR5E 0x5E 174#define SR5E 0x5E
171#define SR65 0x65 175#define SR65 0x65
172 176
@@ -966,6 +970,100 @@
966#define CX700_297_500M 0x00CE0403 970#define CX700_297_500M 0x00CE0403
967#define CX700_122_614M 0x00870802 971#define CX700_122_614M 0x00870802
968 972
973/* PLL for VX855 */
974#define VX855_22_000M 0x007B1005
975#define VX855_25_175M 0x008D1005
976#define VX855_26_719M 0x00961005
977#define VX855_26_880M 0x00961005
978#define VX855_27_000M 0x00971005
979#define VX855_29_581M 0x00A51005
980#define VX855_29_829M 0x00641003
981#define VX855_31_490M 0x00B01005
982#define VX855_31_500M 0x00B01005
983#define VX855_31_728M 0x008E1004
984#define VX855_32_668M 0x00921004
985#define VX855_36_000M 0x00A11004
986#define VX855_40_000M 0x00700C05
987#define VX855_41_291M 0x00730C05
988#define VX855_43_163M 0x00790C05
989#define VX855_45_250M 0x007F0C05 /* 45.46MHz */
990#define VX855_46_000M 0x00670C04
991#define VX855_46_996M 0x00690C04
992#define VX855_48_000M 0x00860C05
993#define VX855_48_875M 0x00890C05
994#define VX855_49_500M 0x00530C03
995#define VX855_52_406M 0x00580C03
996#define VX855_52_977M 0x00940C05
997#define VX855_56_250M 0x009D0C05
998#define VX855_60_466M 0x00A90C05
999#define VX855_61_500M 0x00AC0C05
1000#define VX855_65_000M 0x006D0C03
1001#define VX855_65_178M 0x00B60C05
1002#define VX855_66_750M 0x00700C03 /*67.116MHz */
1003#define VX855_67_295M 0x00BC0C05
1004#define VX855_68_179M 0x00BF0C05
1005#define VX855_68_369M 0x00BF0C05
1006#define VX855_69_924M 0x00C30C05
1007#define VX855_70_159M 0x00C30C05
1008#define VX855_72_000M 0x00A10C04
1009#define VX855_73_023M 0x00CC0C05
1010#define VX855_74_481M 0x00D10C05
1011#define VX855_78_750M 0x006E0805
1012#define VX855_79_466M 0x006F0805
1013#define VX855_80_136M 0x00700805
1014#define VX855_81_627M 0x00720805
1015#define VX855_83_375M 0x00750805
1016#define VX855_83_527M 0x00750805
1017#define VX855_83_950M 0x00750805
1018#define VX855_84_537M 0x00760805
1019#define VX855_84_750M 0x00760805 /* 84.537Mhz */
1020#define VX855_85_500M 0x00760805 /* 85.909080 MHz*/
1021#define VX855_85_860M 0x00760805
1022#define VX855_85_909M 0x00760805
1023#define VX855_88_750M 0x007C0805
1024#define VX855_89_489M 0x007D0805
1025#define VX855_94_500M 0x00840805
1026#define VX855_96_648M 0x00870805
1027#define VX855_97_750M 0x00890805
1028#define VX855_101_000M 0x008D0805
1029#define VX855_106_500M 0x00950805
1030#define VX855_108_000M 0x00970805
1031#define VX855_110_125M 0x00990805
1032#define VX855_112_000M 0x009D0805
1033#define VX855_113_309M 0x009F0805
1034#define VX855_115_000M 0x00A10805
1035#define VX855_118_840M 0x00A60805
1036#define VX855_119_000M 0x00A70805
1037#define VX855_121_750M 0x00AA0805 /* 121.704MHz */
1038#define VX855_122_614M 0x00AC0805
1039#define VX855_126_266M 0x00B10805
1040#define VX855_130_250M 0x00B60805 /* 130.250 */
1041#define VX855_135_000M 0x00BD0805
1042#define VX855_136_700M 0x00BF0805
1043#define VX855_137_750M 0x00C10805
1044#define VX855_138_400M 0x00C20805
1045#define VX855_144_300M 0x00CA0805
1046#define VX855_146_760M 0x00CE0805
1047#define VX855_148_500M 0x00D00805
1048#define VX855_153_920M 0x00540402
1049#define VX855_156_000M 0x006C0405
1050#define VX855_156_867M 0x006E0405
1051#define VX855_157_500M 0x006E0405
1052#define VX855_162_000M 0x00710405
1053#define VX855_172_798M 0x00790405
1054#define VX855_187_000M 0x00830405
1055#define VX855_193_295M 0x00870405
1056#define VX855_202_500M 0x008E0405
1057#define VX855_204_000M 0x008F0405
1058#define VX855_218_500M 0x00990405
1059#define VX855_229_500M 0x00A10405
1060#define VX855_234_000M 0x00A40405
1061#define VX855_267_250M 0x00BB0405
1062#define VX855_297_500M 0x00D00405
1063#define VX855_339_500M 0x00770005
1064#define VX855_340_772M 0x00770005
1065
1066
969/* Definition CRTC Timing Index */ 1067/* Definition CRTC Timing Index */
970#define H_TOTAL_INDEX 0 1068#define H_TOTAL_INDEX 0
971#define H_ADDR_INDEX 1 1069#define H_ADDR_INDEX 1
diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c
index 61e652cb2138..3815a9b07195 100644
--- a/drivers/video/via/viafbdev.c
+++ b/drivers/video/via/viafbdev.c
@@ -914,7 +914,8 @@ static int viafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
914 fg_color = cursor->image.fg_color; 914 fg_color = cursor->image.fg_color;
915 bg_color = cursor->image.bg_color; 915 bg_color = cursor->image.bg_color;
916 if (chip_name == UNICHROME_CX700 || 916 if (chip_name == UNICHROME_CX700 ||
917 chip_name == UNICHROME_VX800) { 917 chip_name == UNICHROME_VX800 ||
918 chip_name == UNICHROME_VX855) {
918 fg_color = 919 fg_color =
919 ((info->cmap.red[fg_color] & 0xFFC0) << 14) | 920 ((info->cmap.red[fg_color] & 0xFFC0) << 14) |
920 ((info->cmap.green[fg_color] & 0xFFC0) << 4) | 921 ((info->cmap.green[fg_color] & 0xFFC0) << 4) |
diff --git a/drivers/video/via/viamode.c b/drivers/video/via/viamode.c
index 16a8a97f6042..b74f8a67923c 100644
--- a/drivers/video/via/viamode.c
+++ b/drivers/video/via/viamode.c
@@ -312,6 +312,60 @@ struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
312{VIACR, CR9B, 0xFF, 0x00} 312{VIACR, CR9B, 0xFF, 0x00}
313}; 313};
314 314
315struct io_reg VX855_ModeXregs[] = {
316{VIASR, SR10, 0xFF, 0x01},
317{VIASR, SR15, 0x02, 0x02},
318{VIASR, SR16, 0xBF, 0x08},
319{VIASR, SR17, 0xFF, 0x1F},
320{VIASR, SR18, 0xFF, 0x4E},
321{VIASR, SR1A, 0xFB, 0x08},
322{VIASR, SR1B, 0xFF, 0xF0},
323{VIASR, SR1E, 0x07, 0x01},
324{VIASR, SR2A, 0xF0, 0x00},
325{VIASR, SR58, 0xFF, 0x00},
326{VIASR, SR59, 0xFF, 0x00},
327{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */
328{VIACR, CR09, 0xFF, 0x00}, /* Initial CR09=0*/
329{VIACR, CR11, 0x8F, 0x00}, /* IGA1 initial Vertical end */
330{VIACR, CR17, 0x7F, 0x00}, /* IGA1 CRT Mode control init */
331{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
332{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
333{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
334{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
335{VIACR, CR32, 0xFF, 0x00},
336{VIACR, CR33, 0x7F, 0x00},
337{VIACR, CR35, 0xFF, 0x00},
338{VIACR, CR36, 0x08, 0x00},
339{VIACR, CR69, 0xFF, 0x00},
340{VIACR, CR6A, 0xFD, 0x60},
341{VIACR, CR6B, 0xFF, 0x00},
342{VIACR, CR6C, 0xFF, 0x00},
343{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
344{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
345{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
346{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
347{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
348{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
349{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
350{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
351{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
352{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
353{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
354{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
355{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
356{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
357{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
358{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
359{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
360{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
361{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
362{VIACR, CR96, 0xFF, 0x00},
363{VIACR, CR97, 0xFF, 0x00},
364{VIACR, CR99, 0xFF, 0x00},
365{VIACR, CR9B, 0xFF, 0x00},
366{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
367};
368
315/* Video Mode Table */ 369/* Video Mode Table */
316/* Common Setting for Video Mode */ 370/* Common Setting for Video Mode */
317struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00}, 371struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
@@ -1012,6 +1066,7 @@ int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
1012int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs); 1066int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
1013int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs); 1067int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs);
1014int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs); 1068int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs);
1069int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs);
1015int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs); 1070int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
1016int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table); 1071int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
1017int NUM_TOTAL_MODETABLE = ARRAY_SIZE(CLE266Modes); 1072int NUM_TOTAL_MODETABLE = ARRAY_SIZE(CLE266Modes);
diff --git a/drivers/video/via/viamode.h b/drivers/video/via/viamode.h
index 504e16a9b515..a9d6554fabdf 100644
--- a/drivers/video/via/viamode.h
+++ b/drivers/video/via/viamode.h
@@ -56,6 +56,7 @@ extern int NUM_TOTAL_CN400_ModeXregs;
56extern int NUM_TOTAL_CN700_ModeXregs; 56extern int NUM_TOTAL_CN700_ModeXregs;
57extern int NUM_TOTAL_KM400_ModeXregs; 57extern int NUM_TOTAL_KM400_ModeXregs;
58extern int NUM_TOTAL_CX700_ModeXregs; 58extern int NUM_TOTAL_CX700_ModeXregs;
59extern int NUM_TOTAL_VX855_ModeXregs;
59extern int NUM_TOTAL_CLE266_ModeXregs; 60extern int NUM_TOTAL_CLE266_ModeXregs;
60extern int NUM_TOTAL_PATCH_MODE; 61extern int NUM_TOTAL_PATCH_MODE;
61extern int NUM_TOTAL_MODETABLE; 62extern int NUM_TOTAL_MODETABLE;
@@ -75,6 +76,7 @@ extern struct io_reg CN700_ModeXregs[];
75extern struct io_reg KM400_ModeXregs[]; 76extern struct io_reg KM400_ModeXregs[];
76extern struct io_reg CX700_ModeXregs[]; 77extern struct io_reg CX700_ModeXregs[];
77extern struct io_reg VX800_ModeXregs[]; 78extern struct io_reg VX800_ModeXregs[];
79extern struct io_reg VX855_ModeXregs[];
78extern struct io_reg CLE266_ModeXregs[]; 80extern struct io_reg CLE266_ModeXregs[];
79extern struct io_reg PM1024x768[]; 81extern struct io_reg PM1024x768[];
80extern struct patch_table res_patch_table[]; 82extern struct patch_table res_patch_table[];
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 04:27:23 -0500