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authorTomi Valkeinen <tomi.valkeinen@ti.com>2014-11-07 09:44:02 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2014-11-12 06:40:27 -0500
commitdafea8fb584132837b56fb343e444ab65e2905c4 (patch)
treec96a36d963c293f0d9f70adbadd2f81f2abdc699 /drivers/video/fbdev/omap2/dss/dss_features.h
parentc84c3a5bb78ff271787a1fec9218768aed555e8d (diff)
OMAPDSS: features: remove unused DSI PLL features
Now that the DSS has the common DSS PLL, we no longer use the DSI PLL feature flags from dss_features.c. Remove all the unused feature flags. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/fbdev/omap2/dss/dss_features.h')
-rw-r--r--drivers/video/fbdev/omap2/dss/dss_features.h11
1 files changed, 0 insertions, 11 deletions
diff --git a/drivers/video/fbdev/omap2/dss/dss_features.h b/drivers/video/fbdev/omap2/dss/dss_features.h
index 05e8127d36b0..100f7a2d0638 100644
--- a/drivers/video/fbdev/omap2/dss/dss_features.h
+++ b/drivers/video/fbdev/omap2/dss/dss_features.h
@@ -41,7 +41,6 @@ enum dss_feat_id {
41 FEAT_LCD_CLK_SRC, 41 FEAT_LCD_CLK_SRC,
42 /* DSI-PLL power command 0x3 is not working */ 42 /* DSI-PLL power command 0x3 is not working */
43 FEAT_DSI_PLL_PWR_BUG, 43 FEAT_DSI_PLL_PWR_BUG,
44 FEAT_DSI_PLL_FREQSEL,
45 FEAT_DSI_DCS_CMD_CONFIG_VC, 44 FEAT_DSI_DCS_CMD_CONFIG_VC,
46 FEAT_DSI_VC_OCP_WIDTH, 45 FEAT_DSI_VC_OCP_WIDTH,
47 FEAT_DSI_REVERSE_TXCLKESC, 46 FEAT_DSI_REVERSE_TXCLKESC,
@@ -61,8 +60,6 @@ enum dss_feat_id {
61 /* An unknown HW bug causing the normal FIFO thresholds not to work */ 60 /* An unknown HW bug causing the normal FIFO thresholds not to work */
62 FEAT_OMAP3_DSI_FIFO_BUG, 61 FEAT_OMAP3_DSI_FIFO_BUG,
63 FEAT_BURST_2D, 62 FEAT_BURST_2D,
64 FEAT_DSI_PLL_SELFREQDCO,
65 FEAT_DSI_PLL_REFSEL,
66 FEAT_DSI_PHY_DCC, 63 FEAT_DSI_PHY_DCC,
67 FEAT_MFLAG, 64 FEAT_MFLAG,
68}; 65};
@@ -77,19 +74,11 @@ enum dss_feat_reg_field {
77 FEAT_REG_HORIZONTALACCU, 74 FEAT_REG_HORIZONTALACCU,
78 FEAT_REG_VERTICALACCU, 75 FEAT_REG_VERTICALACCU,
79 FEAT_REG_DISPC_CLK_SWITCH, 76 FEAT_REG_DISPC_CLK_SWITCH,
80 FEAT_REG_DSIPLL_REGN,
81 FEAT_REG_DSIPLL_REGM,
82 FEAT_REG_DSIPLL_REGM_DISPC,
83 FEAT_REG_DSIPLL_REGM_DSI,
84}; 77};
85 78
86enum dss_range_param { 79enum dss_range_param {
87 FEAT_PARAM_DSS_FCK, 80 FEAT_PARAM_DSS_FCK,
88 FEAT_PARAM_DSS_PCD, 81 FEAT_PARAM_DSS_PCD,
89 FEAT_PARAM_DSIPLL_REGN,
90 FEAT_PARAM_DSIPLL_REGM,
91 FEAT_PARAM_DSIPLL_REGM_HSDIV,
92 FEAT_PARAM_DSIPLL_FINT,
93 FEAT_PARAM_DSIPLL_LPDIV, 82 FEAT_PARAM_DSIPLL_LPDIV,
94 FEAT_PARAM_DSI_FCK, 83 FEAT_PARAM_DSI_FCK,
95 FEAT_PARAM_DOWNSCALE, 84 FEAT_PARAM_DOWNSCALE,