diff options
author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-11-07 09:44:02 -0500 |
---|---|---|
committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-11-12 06:40:27 -0500 |
commit | dafea8fb584132837b56fb343e444ab65e2905c4 (patch) | |
tree | c96a36d963c293f0d9f70adbadd2f81f2abdc699 | |
parent | c84c3a5bb78ff271787a1fec9218768aed555e8d (diff) |
OMAPDSS: features: remove unused DSI PLL features
Now that the DSS has the common DSS PLL, we no longer use the DSI PLL
feature flags from dss_features.c.
Remove all the unused feature flags.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
-rw-r--r-- | drivers/video/fbdev/omap2/dss/dss_features.c | 38 | ||||
-rw-r--r-- | drivers/video/fbdev/omap2/dss/dss_features.h | 11 |
2 files changed, 0 insertions, 49 deletions
diff --git a/drivers/video/fbdev/omap2/dss/dss_features.c b/drivers/video/fbdev/omap2/dss/dss_features.c index 7e7fcf450342..0e3da809473c 100644 --- a/drivers/video/fbdev/omap2/dss/dss_features.c +++ b/drivers/video/fbdev/omap2/dss/dss_features.c | |||
@@ -72,10 +72,6 @@ static const struct dss_reg_field omap2_dss_reg_fields[] = { | |||
72 | [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, | 72 | [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, |
73 | [FEAT_REG_VERTICALACCU] = { 25, 16 }, | 73 | [FEAT_REG_VERTICALACCU] = { 25, 16 }, |
74 | [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, | 74 | [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, |
75 | [FEAT_REG_DSIPLL_REGN] = { 0, 0 }, | ||
76 | [FEAT_REG_DSIPLL_REGM] = { 0, 0 }, | ||
77 | [FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 }, | ||
78 | [FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 }, | ||
79 | }; | 75 | }; |
80 | 76 | ||
81 | static const struct dss_reg_field omap3_dss_reg_fields[] = { | 77 | static const struct dss_reg_field omap3_dss_reg_fields[] = { |
@@ -87,10 +83,6 @@ static const struct dss_reg_field omap3_dss_reg_fields[] = { | |||
87 | [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, | 83 | [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, |
88 | [FEAT_REG_VERTICALACCU] = { 25, 16 }, | 84 | [FEAT_REG_VERTICALACCU] = { 25, 16 }, |
89 | [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, | 85 | [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, |
90 | [FEAT_REG_DSIPLL_REGN] = { 7, 1 }, | ||
91 | [FEAT_REG_DSIPLL_REGM] = { 18, 8 }, | ||
92 | [FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 }, | ||
93 | [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 }, | ||
94 | }; | 86 | }; |
95 | 87 | ||
96 | static const struct dss_reg_field am43xx_dss_reg_fields[] = { | 88 | static const struct dss_reg_field am43xx_dss_reg_fields[] = { |
@@ -113,10 +105,6 @@ static const struct dss_reg_field omap4_dss_reg_fields[] = { | |||
113 | [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, | 105 | [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, |
114 | [FEAT_REG_VERTICALACCU] = { 26, 16 }, | 106 | [FEAT_REG_VERTICALACCU] = { 26, 16 }, |
115 | [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 }, | 107 | [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 }, |
116 | [FEAT_REG_DSIPLL_REGN] = { 8, 1 }, | ||
117 | [FEAT_REG_DSIPLL_REGM] = { 20, 9 }, | ||
118 | [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 }, | ||
119 | [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 }, | ||
120 | }; | 108 | }; |
121 | 109 | ||
122 | static const struct dss_reg_field omap5_dss_reg_fields[] = { | 110 | static const struct dss_reg_field omap5_dss_reg_fields[] = { |
@@ -128,10 +116,6 @@ static const struct dss_reg_field omap5_dss_reg_fields[] = { | |||
128 | [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, | 116 | [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, |
129 | [FEAT_REG_VERTICALACCU] = { 26, 16 }, | 117 | [FEAT_REG_VERTICALACCU] = { 26, 16 }, |
130 | [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 }, | 118 | [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 }, |
131 | [FEAT_REG_DSIPLL_REGN] = { 8, 1 }, | ||
132 | [FEAT_REG_DSIPLL_REGM] = { 20, 9 }, | ||
133 | [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 }, | ||
134 | [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 }, | ||
135 | }; | 119 | }; |
136 | 120 | ||
137 | static const enum omap_display_type omap2_dss_supported_displays[] = { | 121 | static const enum omap_display_type omap2_dss_supported_displays[] = { |
@@ -437,11 +421,6 @@ static const char * const omap5_dss_clk_source_names[] = { | |||
437 | static const struct dss_param_range omap2_dss_param_range[] = { | 421 | static const struct dss_param_range omap2_dss_param_range[] = { |
438 | [FEAT_PARAM_DSS_FCK] = { 0, 133000000 }, | 422 | [FEAT_PARAM_DSS_FCK] = { 0, 133000000 }, |
439 | [FEAT_PARAM_DSS_PCD] = { 2, 255 }, | 423 | [FEAT_PARAM_DSS_PCD] = { 2, 255 }, |
440 | [FEAT_PARAM_DSIPLL_REGN] = { 0, 0 }, | ||
441 | [FEAT_PARAM_DSIPLL_REGM] = { 0, 0 }, | ||
442 | [FEAT_PARAM_DSIPLL_REGM_HSDIV] = { 0, 0 }, | ||
443 | [FEAT_PARAM_DSIPLL_FINT] = { 0, 0 }, | ||
444 | [FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 }, | ||
445 | [FEAT_PARAM_DOWNSCALE] = { 1, 2 }, | 424 | [FEAT_PARAM_DOWNSCALE] = { 1, 2 }, |
446 | /* | 425 | /* |
447 | * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC | 426 | * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC |
@@ -453,10 +432,6 @@ static const struct dss_param_range omap2_dss_param_range[] = { | |||
453 | static const struct dss_param_range omap3_dss_param_range[] = { | 432 | static const struct dss_param_range omap3_dss_param_range[] = { |
454 | [FEAT_PARAM_DSS_FCK] = { 0, 173000000 }, | 433 | [FEAT_PARAM_DSS_FCK] = { 0, 173000000 }, |
455 | [FEAT_PARAM_DSS_PCD] = { 1, 255 }, | 434 | [FEAT_PARAM_DSS_PCD] = { 1, 255 }, |
456 | [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 }, | ||
457 | [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 }, | ||
458 | [FEAT_PARAM_DSIPLL_REGM_HSDIV] = { 0, (1 << 4) - 1 }, | ||
459 | [FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 }, | ||
460 | [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1}, | 435 | [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1}, |
461 | [FEAT_PARAM_DSI_FCK] = { 0, 173000000 }, | 436 | [FEAT_PARAM_DSI_FCK] = { 0, 173000000 }, |
462 | [FEAT_PARAM_DOWNSCALE] = { 1, 4 }, | 437 | [FEAT_PARAM_DOWNSCALE] = { 1, 4 }, |
@@ -473,10 +448,6 @@ static const struct dss_param_range am43xx_dss_param_range[] = { | |||
473 | static const struct dss_param_range omap4_dss_param_range[] = { | 448 | static const struct dss_param_range omap4_dss_param_range[] = { |
474 | [FEAT_PARAM_DSS_FCK] = { 0, 186000000 }, | 449 | [FEAT_PARAM_DSS_FCK] = { 0, 186000000 }, |
475 | [FEAT_PARAM_DSS_PCD] = { 1, 255 }, | 450 | [FEAT_PARAM_DSS_PCD] = { 1, 255 }, |
476 | [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 }, | ||
477 | [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 }, | ||
478 | [FEAT_PARAM_DSIPLL_REGM_HSDIV] = { 0, (1 << 5) - 1 }, | ||
479 | [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 }, | ||
480 | [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 }, | 451 | [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 }, |
481 | [FEAT_PARAM_DSI_FCK] = { 0, 170000000 }, | 452 | [FEAT_PARAM_DSI_FCK] = { 0, 170000000 }, |
482 | [FEAT_PARAM_DOWNSCALE] = { 1, 4 }, | 453 | [FEAT_PARAM_DOWNSCALE] = { 1, 4 }, |
@@ -486,10 +457,6 @@ static const struct dss_param_range omap4_dss_param_range[] = { | |||
486 | static const struct dss_param_range omap5_dss_param_range[] = { | 457 | static const struct dss_param_range omap5_dss_param_range[] = { |
487 | [FEAT_PARAM_DSS_FCK] = { 0, 209250000 }, | 458 | [FEAT_PARAM_DSS_FCK] = { 0, 209250000 }, |
488 | [FEAT_PARAM_DSS_PCD] = { 1, 255 }, | 459 | [FEAT_PARAM_DSS_PCD] = { 1, 255 }, |
489 | [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 }, | ||
490 | [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 }, | ||
491 | [FEAT_PARAM_DSIPLL_REGM_HSDIV] = { 0, (1 << 5) - 1 }, | ||
492 | [FEAT_PARAM_DSIPLL_FINT] = { 150000, 52000000 }, | ||
493 | [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 }, | 460 | [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 }, |
494 | [FEAT_PARAM_DSI_FCK] = { 0, 209250000 }, | 461 | [FEAT_PARAM_DSI_FCK] = { 0, 209250000 }, |
495 | [FEAT_PARAM_DOWNSCALE] = { 1, 4 }, | 462 | [FEAT_PARAM_DOWNSCALE] = { 1, 4 }, |
@@ -513,7 +480,6 @@ static const enum dss_feat_id omap3430_dss_feat_list[] = { | |||
513 | FEAT_LINEBUFFERSPLIT, | 480 | FEAT_LINEBUFFERSPLIT, |
514 | FEAT_ROWREPEATENABLE, | 481 | FEAT_ROWREPEATENABLE, |
515 | FEAT_RESIZECONF, | 482 | FEAT_RESIZECONF, |
516 | FEAT_DSI_PLL_FREQSEL, | ||
517 | FEAT_DSI_REVERSE_TXCLKESC, | 483 | FEAT_DSI_REVERSE_TXCLKESC, |
518 | FEAT_VENC_REQUIRES_TV_DAC_CLK, | 484 | FEAT_VENC_REQUIRES_TV_DAC_CLK, |
519 | FEAT_CPR, | 485 | FEAT_CPR, |
@@ -533,7 +499,6 @@ static const enum dss_feat_id am35xx_dss_feat_list[] = { | |||
533 | FEAT_LINEBUFFERSPLIT, | 499 | FEAT_LINEBUFFERSPLIT, |
534 | FEAT_ROWREPEATENABLE, | 500 | FEAT_ROWREPEATENABLE, |
535 | FEAT_RESIZECONF, | 501 | FEAT_RESIZECONF, |
536 | FEAT_DSI_PLL_FREQSEL, | ||
537 | FEAT_DSI_REVERSE_TXCLKESC, | 502 | FEAT_DSI_REVERSE_TXCLKESC, |
538 | FEAT_VENC_REQUIRES_TV_DAC_CLK, | 503 | FEAT_VENC_REQUIRES_TV_DAC_CLK, |
539 | FEAT_CPR, | 504 | FEAT_CPR, |
@@ -568,7 +533,6 @@ static const enum dss_feat_id omap3630_dss_feat_list[] = { | |||
568 | FEAT_ROWREPEATENABLE, | 533 | FEAT_ROWREPEATENABLE, |
569 | FEAT_RESIZECONF, | 534 | FEAT_RESIZECONF, |
570 | FEAT_DSI_PLL_PWR_BUG, | 535 | FEAT_DSI_PLL_PWR_BUG, |
571 | FEAT_DSI_PLL_FREQSEL, | ||
572 | FEAT_CPR, | 536 | FEAT_CPR, |
573 | FEAT_PRELOAD, | 537 | FEAT_PRELOAD, |
574 | FEAT_FIR_COEF_V, | 538 | FEAT_FIR_COEF_V, |
@@ -650,8 +614,6 @@ static const enum dss_feat_id omap5_dss_feat_list[] = { | |||
650 | FEAT_ALPHA_FREE_ZORDER, | 614 | FEAT_ALPHA_FREE_ZORDER, |
651 | FEAT_FIFO_MERGE, | 615 | FEAT_FIFO_MERGE, |
652 | FEAT_BURST_2D, | 616 | FEAT_BURST_2D, |
653 | FEAT_DSI_PLL_SELFREQDCO, | ||
654 | FEAT_DSI_PLL_REFSEL, | ||
655 | FEAT_DSI_PHY_DCC, | 617 | FEAT_DSI_PHY_DCC, |
656 | FEAT_MFLAG, | 618 | FEAT_MFLAG, |
657 | }; | 619 | }; |
diff --git a/drivers/video/fbdev/omap2/dss/dss_features.h b/drivers/video/fbdev/omap2/dss/dss_features.h index 05e8127d36b0..100f7a2d0638 100644 --- a/drivers/video/fbdev/omap2/dss/dss_features.h +++ b/drivers/video/fbdev/omap2/dss/dss_features.h | |||
@@ -41,7 +41,6 @@ enum dss_feat_id { | |||
41 | FEAT_LCD_CLK_SRC, | 41 | FEAT_LCD_CLK_SRC, |
42 | /* DSI-PLL power command 0x3 is not working */ | 42 | /* DSI-PLL power command 0x3 is not working */ |
43 | FEAT_DSI_PLL_PWR_BUG, | 43 | FEAT_DSI_PLL_PWR_BUG, |
44 | FEAT_DSI_PLL_FREQSEL, | ||
45 | FEAT_DSI_DCS_CMD_CONFIG_VC, | 44 | FEAT_DSI_DCS_CMD_CONFIG_VC, |
46 | FEAT_DSI_VC_OCP_WIDTH, | 45 | FEAT_DSI_VC_OCP_WIDTH, |
47 | FEAT_DSI_REVERSE_TXCLKESC, | 46 | FEAT_DSI_REVERSE_TXCLKESC, |
@@ -61,8 +60,6 @@ enum dss_feat_id { | |||
61 | /* An unknown HW bug causing the normal FIFO thresholds not to work */ | 60 | /* An unknown HW bug causing the normal FIFO thresholds not to work */ |
62 | FEAT_OMAP3_DSI_FIFO_BUG, | 61 | FEAT_OMAP3_DSI_FIFO_BUG, |
63 | FEAT_BURST_2D, | 62 | FEAT_BURST_2D, |
64 | FEAT_DSI_PLL_SELFREQDCO, | ||
65 | FEAT_DSI_PLL_REFSEL, | ||
66 | FEAT_DSI_PHY_DCC, | 63 | FEAT_DSI_PHY_DCC, |
67 | FEAT_MFLAG, | 64 | FEAT_MFLAG, |
68 | }; | 65 | }; |
@@ -77,19 +74,11 @@ enum dss_feat_reg_field { | |||
77 | FEAT_REG_HORIZONTALACCU, | 74 | FEAT_REG_HORIZONTALACCU, |
78 | FEAT_REG_VERTICALACCU, | 75 | FEAT_REG_VERTICALACCU, |
79 | FEAT_REG_DISPC_CLK_SWITCH, | 76 | FEAT_REG_DISPC_CLK_SWITCH, |
80 | FEAT_REG_DSIPLL_REGN, | ||
81 | FEAT_REG_DSIPLL_REGM, | ||
82 | FEAT_REG_DSIPLL_REGM_DISPC, | ||
83 | FEAT_REG_DSIPLL_REGM_DSI, | ||
84 | }; | 77 | }; |
85 | 78 | ||
86 | enum dss_range_param { | 79 | enum dss_range_param { |
87 | FEAT_PARAM_DSS_FCK, | 80 | FEAT_PARAM_DSS_FCK, |
88 | FEAT_PARAM_DSS_PCD, | 81 | FEAT_PARAM_DSS_PCD, |
89 | FEAT_PARAM_DSIPLL_REGN, | ||
90 | FEAT_PARAM_DSIPLL_REGM, | ||
91 | FEAT_PARAM_DSIPLL_REGM_HSDIV, | ||
92 | FEAT_PARAM_DSIPLL_FINT, | ||
93 | FEAT_PARAM_DSIPLL_LPDIV, | 82 | FEAT_PARAM_DSIPLL_LPDIV, |
94 | FEAT_PARAM_DSI_FCK, | 83 | FEAT_PARAM_DSI_FCK, |
95 | FEAT_PARAM_DOWNSCALE, | 84 | FEAT_PARAM_DOWNSCALE, |