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authorKukjin Kim <kgene.kim@samsung.com>2014-05-30 13:36:49 -0400
committerKukjin Kim <kgene.kim@samsung.com>2014-05-30 13:36:49 -0400
commitfced6dee29f6fb143fe16ea90331176ff77e6120 (patch)
tree5b6e57e7a757adc2a6518ce291a4d2914397b917 /drivers/video/fbdev/mmp
parentbfed1074f213051e94648bfad0d0611a16d81366 (diff)
parentbe1f7c8d7e2bc8b8c76846aa6f276e8d2ef8975a (diff)
Merge branch 'v3.16-next/cleanup-samsung' into v3.16-next/platform-exynos
Diffstat (limited to 'drivers/video/fbdev/mmp')
-rw-r--r--drivers/video/fbdev/mmp/Kconfig11
-rw-r--r--drivers/video/fbdev/mmp/Makefile1
-rw-r--r--drivers/video/fbdev/mmp/core.c251
-rw-r--r--drivers/video/fbdev/mmp/fb/Kconfig13
-rw-r--r--drivers/video/fbdev/mmp/fb/Makefile1
-rw-r--r--drivers/video/fbdev/mmp/fb/mmpfb.c694
-rw-r--r--drivers/video/fbdev/mmp/fb/mmpfb.h54
-rw-r--r--drivers/video/fbdev/mmp/hw/Kconfig20
-rw-r--r--drivers/video/fbdev/mmp/hw/Makefile2
-rw-r--r--drivers/video/fbdev/mmp/hw/mmp_ctrl.c588
-rw-r--r--drivers/video/fbdev/mmp/hw/mmp_ctrl.h1502
-rw-r--r--drivers/video/fbdev/mmp/hw/mmp_spi.c180
-rw-r--r--drivers/video/fbdev/mmp/panel/Kconfig6
-rw-r--r--drivers/video/fbdev/mmp/panel/Makefile1
-rw-r--r--drivers/video/fbdev/mmp/panel/tpo_tj032md01bw.c186
15 files changed, 3510 insertions, 0 deletions
diff --git a/drivers/video/fbdev/mmp/Kconfig b/drivers/video/fbdev/mmp/Kconfig
new file mode 100644
index 000000000000..d4a4ffc24749
--- /dev/null
+++ b/drivers/video/fbdev/mmp/Kconfig
@@ -0,0 +1,11 @@
1menuconfig MMP_DISP
2 tristate "Marvell MMP Display Subsystem support"
3 depends on CPU_PXA910 || CPU_MMP2 || CPU_MMP3 || CPU_PXA988
4 help
5 Marvell Display Subsystem support.
6
7if MMP_DISP
8source "drivers/video/fbdev/mmp/hw/Kconfig"
9source "drivers/video/fbdev/mmp/panel/Kconfig"
10source "drivers/video/fbdev/mmp/fb/Kconfig"
11endif
diff --git a/drivers/video/fbdev/mmp/Makefile b/drivers/video/fbdev/mmp/Makefile
new file mode 100644
index 000000000000..a014cb358bf8
--- /dev/null
+++ b/drivers/video/fbdev/mmp/Makefile
@@ -0,0 +1 @@
obj-y += core.o hw/ panel/ fb/
diff --git a/drivers/video/fbdev/mmp/core.c b/drivers/video/fbdev/mmp/core.c
new file mode 100644
index 000000000000..b563b920f159
--- /dev/null
+++ b/drivers/video/fbdev/mmp/core.c
@@ -0,0 +1,251 @@
1/*
2 * linux/drivers/video/mmp/common.c
3 * This driver is a common framework for Marvell Display Controller
4 *
5 * Copyright (C) 2012 Marvell Technology Group Ltd.
6 * Authors: Zhou Zhu <zzhu3@marvell.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22
23#include <linux/slab.h>
24#include <linux/dma-mapping.h>
25#include <linux/export.h>
26#include <video/mmp_disp.h>
27
28static struct mmp_overlay *path_get_overlay(struct mmp_path *path,
29 int overlay_id)
30{
31 if (path && overlay_id < path->overlay_num)
32 return &path->overlays[overlay_id];
33 return NULL;
34}
35
36static int path_check_status(struct mmp_path *path)
37{
38 int i;
39 for (i = 0; i < path->overlay_num; i++)
40 if (path->overlays[i].status)
41 return 1;
42
43 return 0;
44}
45
46/*
47 * Get modelist write pointer of modelist.
48 * It also returns modelist number
49 * this function fetches modelist from phy/panel:
50 * for HDMI/parallel or dsi to hdmi cases, get from phy
51 * or get from panel
52 */
53static int path_get_modelist(struct mmp_path *path,
54 struct mmp_mode **modelist)
55{
56 BUG_ON(!path || !modelist);
57
58 if (path->panel && path->panel->get_modelist)
59 return path->panel->get_modelist(path->panel, modelist);
60
61 return 0;
62}
63
64/*
65 * panel list is used to pair panel/path when path/panel registered
66 * path list is used for both buffer driver and platdriver
67 * plat driver do path register/unregister
68 * panel driver do panel register/unregister
69 * buffer driver get registered path
70 */
71static LIST_HEAD(panel_list);
72static LIST_HEAD(path_list);
73static DEFINE_MUTEX(disp_lock);
74
75/*
76 * mmp_register_panel - register panel to panel_list and connect to path
77 * @p: panel to be registered
78 *
79 * this function provides interface for panel drivers to register panel
80 * to panel_list and connect to path which matchs panel->plat_path_name.
81 * no error returns when no matching path is found as path register after
82 * panel register is permitted.
83 */
84void mmp_register_panel(struct mmp_panel *panel)
85{
86 struct mmp_path *path;
87
88 mutex_lock(&disp_lock);
89
90 /* add */
91 list_add_tail(&panel->node, &panel_list);
92
93 /* try to register to path */
94 list_for_each_entry(path, &path_list, node) {
95 if (!strcmp(panel->plat_path_name, path->name)) {
96 dev_info(panel->dev, "connect to path %s\n",
97 path->name);
98 path->panel = panel;
99 break;
100 }
101 }
102
103 mutex_unlock(&disp_lock);
104}
105EXPORT_SYMBOL_GPL(mmp_register_panel);
106
107/*
108 * mmp_unregister_panel - unregister panel from panel_list and disconnect
109 * @p: panel to be unregistered
110 *
111 * this function provides interface for panel drivers to unregister panel
112 * from panel_list and disconnect from path.
113 */
114void mmp_unregister_panel(struct mmp_panel *panel)
115{
116 struct mmp_path *path;
117
118 mutex_lock(&disp_lock);
119 list_del(&panel->node);
120
121 list_for_each_entry(path, &path_list, node) {
122 if (path->panel && path->panel == panel) {
123 dev_info(panel->dev, "disconnect from path %s\n",
124 path->name);
125 path->panel = NULL;
126 break;
127 }
128 }
129 mutex_unlock(&disp_lock);
130}
131EXPORT_SYMBOL_GPL(mmp_unregister_panel);
132
133/*
134 * mmp_get_path - get path by name
135 * @p: path name
136 *
137 * this function checks path name in path_list and return matching path
138 * return NULL if no matching path
139 */
140struct mmp_path *mmp_get_path(const char *name)
141{
142 struct mmp_path *path;
143 int found = 0;
144
145 mutex_lock(&disp_lock);
146 list_for_each_entry(path, &path_list, node) {
147 if (!strcmp(name, path->name)) {
148 found = 1;
149 break;
150 }
151 }
152 mutex_unlock(&disp_lock);
153
154 return found ? path : NULL;
155}
156EXPORT_SYMBOL_GPL(mmp_get_path);
157
158/*
159 * mmp_register_path - init and register path by path_info
160 * @p: path info provided by display controller
161 *
162 * this function init by path info and register path to path_list
163 * this function also try to connect path with panel by name
164 */
165struct mmp_path *mmp_register_path(struct mmp_path_info *info)
166{
167 int i;
168 size_t size;
169 struct mmp_path *path = NULL;
170 struct mmp_panel *panel;
171
172 size = sizeof(struct mmp_path)
173 + sizeof(struct mmp_overlay) * info->overlay_num;
174 path = kzalloc(size, GFP_KERNEL);
175 if (!path)
176 return NULL;
177
178 /* path set */
179 mutex_init(&path->access_ok);
180 path->dev = info->dev;
181 path->id = info->id;
182 path->name = info->name;
183 path->output_type = info->output_type;
184 path->overlay_num = info->overlay_num;
185 path->plat_data = info->plat_data;
186 path->ops.set_mode = info->set_mode;
187
188 mutex_lock(&disp_lock);
189 /* get panel */
190 list_for_each_entry(panel, &panel_list, node) {
191 if (!strcmp(info->name, panel->plat_path_name)) {
192 dev_info(path->dev, "get panel %s\n", panel->name);
193 path->panel = panel;
194 break;
195 }
196 }
197
198 dev_info(path->dev, "register %s, overlay_num %d\n",
199 path->name, path->overlay_num);
200
201 /* default op set: if already set by driver, never cover it */
202 if (!path->ops.check_status)
203 path->ops.check_status = path_check_status;
204 if (!path->ops.get_overlay)
205 path->ops.get_overlay = path_get_overlay;
206 if (!path->ops.get_modelist)
207 path->ops.get_modelist = path_get_modelist;
208
209 /* step3: init overlays */
210 for (i = 0; i < path->overlay_num; i++) {
211 path->overlays[i].path = path;
212 path->overlays[i].id = i;
213 mutex_init(&path->overlays[i].access_ok);
214 path->overlays[i].ops = info->overlay_ops;
215 }
216
217 /* add to pathlist */
218 list_add_tail(&path->node, &path_list);
219
220 mutex_unlock(&disp_lock);
221 return path;
222}
223EXPORT_SYMBOL_GPL(mmp_register_path);
224
225/*
226 * mmp_unregister_path - unregister and destory path
227 * @p: path to be destoried.
228 *
229 * this function registers path and destorys it.
230 */
231void mmp_unregister_path(struct mmp_path *path)
232{
233 int i;
234
235 if (!path)
236 return;
237
238 mutex_lock(&disp_lock);
239 /* del from pathlist */
240 list_del(&path->node);
241
242 /* deinit overlays */
243 for (i = 0; i < path->overlay_num; i++)
244 mutex_destroy(&path->overlays[i].access_ok);
245
246 mutex_destroy(&path->access_ok);
247
248 kfree(path);
249 mutex_unlock(&disp_lock);
250}
251EXPORT_SYMBOL_GPL(mmp_unregister_path);
diff --git a/drivers/video/fbdev/mmp/fb/Kconfig b/drivers/video/fbdev/mmp/fb/Kconfig
new file mode 100644
index 000000000000..9b0141f105f5
--- /dev/null
+++ b/drivers/video/fbdev/mmp/fb/Kconfig
@@ -0,0 +1,13 @@
1if MMP_DISP
2
3config MMP_FB
4 bool "fb driver for Marvell MMP Display Subsystem"
5 depends on FB
6 select FB_CFB_FILLRECT
7 select FB_CFB_COPYAREA
8 select FB_CFB_IMAGEBLIT
9 default y
10 help
11 fb driver for Marvell MMP Display Subsystem
12
13endif
diff --git a/drivers/video/fbdev/mmp/fb/Makefile b/drivers/video/fbdev/mmp/fb/Makefile
new file mode 100644
index 000000000000..709fd1f76abe
--- /dev/null
+++ b/drivers/video/fbdev/mmp/fb/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_MMP_FB) += mmpfb.o
diff --git a/drivers/video/fbdev/mmp/fb/mmpfb.c b/drivers/video/fbdev/mmp/fb/mmpfb.c
new file mode 100644
index 000000000000..7ab31eb76a8c
--- /dev/null
+++ b/drivers/video/fbdev/mmp/fb/mmpfb.c
@@ -0,0 +1,694 @@
1/*
2 * linux/drivers/video/mmp/fb/mmpfb.c
3 * Framebuffer driver for Marvell Display controller.
4 *
5 * Copyright (C) 2012 Marvell Technology Group Ltd.
6 * Authors: Zhou Zhu <zzhu3@marvell.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22#include <linux/module.h>
23#include <linux/dma-mapping.h>
24#include <linux/platform_device.h>
25#include "mmpfb.h"
26
27static int var_to_pixfmt(struct fb_var_screeninfo *var)
28{
29 /*
30 * Pseudocolor mode?
31 */
32 if (var->bits_per_pixel == 8)
33 return PIXFMT_PSEUDOCOLOR;
34
35 /*
36 * Check for YUV422PLANAR.
37 */
38 if (var->bits_per_pixel == 16 && var->red.length == 8 &&
39 var->green.length == 4 && var->blue.length == 4) {
40 if (var->green.offset >= var->blue.offset)
41 return PIXFMT_YUV422P;
42 else
43 return PIXFMT_YVU422P;
44 }
45
46 /*
47 * Check for YUV420PLANAR.
48 */
49 if (var->bits_per_pixel == 12 && var->red.length == 8 &&
50 var->green.length == 2 && var->blue.length == 2) {
51 if (var->green.offset >= var->blue.offset)
52 return PIXFMT_YUV420P;
53 else
54 return PIXFMT_YVU420P;
55 }
56
57 /*
58 * Check for YUV422PACK.
59 */
60 if (var->bits_per_pixel == 16 && var->red.length == 16 &&
61 var->green.length == 16 && var->blue.length == 16) {
62 if (var->red.offset == 0)
63 return PIXFMT_YUYV;
64 else if (var->green.offset >= var->blue.offset)
65 return PIXFMT_UYVY;
66 else
67 return PIXFMT_VYUY;
68 }
69
70 /*
71 * Check for 565/1555.
72 */
73 if (var->bits_per_pixel == 16 && var->red.length <= 5 &&
74 var->green.length <= 6 && var->blue.length <= 5) {
75 if (var->transp.length == 0) {
76 if (var->red.offset >= var->blue.offset)
77 return PIXFMT_RGB565;
78 else
79 return PIXFMT_BGR565;
80 }
81 }
82
83 /*
84 * Check for 888/A888.
85 */
86 if (var->bits_per_pixel <= 32 && var->red.length <= 8 &&
87 var->green.length <= 8 && var->blue.length <= 8) {
88 if (var->bits_per_pixel == 24 && var->transp.length == 0) {
89 if (var->red.offset >= var->blue.offset)
90 return PIXFMT_RGB888PACK;
91 else
92 return PIXFMT_BGR888PACK;
93 }
94
95 if (var->bits_per_pixel == 32 && var->transp.offset == 24) {
96 if (var->red.offset >= var->blue.offset)
97 return PIXFMT_RGBA888;
98 else
99 return PIXFMT_BGRA888;
100 } else {
101 if (var->red.offset >= var->blue.offset)
102 return PIXFMT_RGB888UNPACK;
103 else
104 return PIXFMT_BGR888UNPACK;
105 }
106
107 /* fall through */
108 }
109
110 return -EINVAL;
111}
112
113static void pixfmt_to_var(struct fb_var_screeninfo *var, int pix_fmt)
114{
115 switch (pix_fmt) {
116 case PIXFMT_RGB565:
117 var->bits_per_pixel = 16;
118 var->red.offset = 11; var->red.length = 5;
119 var->green.offset = 5; var->green.length = 6;
120 var->blue.offset = 0; var->blue.length = 5;
121 var->transp.offset = 0; var->transp.length = 0;
122 break;
123 case PIXFMT_BGR565:
124 var->bits_per_pixel = 16;
125 var->red.offset = 0; var->red.length = 5;
126 var->green.offset = 5; var->green.length = 6;
127 var->blue.offset = 11; var->blue.length = 5;
128 var->transp.offset = 0; var->transp.length = 0;
129 break;
130 case PIXFMT_RGB888UNPACK:
131 var->bits_per_pixel = 32;
132 var->red.offset = 16; var->red.length = 8;
133 var->green.offset = 8; var->green.length = 8;
134 var->blue.offset = 0; var->blue.length = 8;
135 var->transp.offset = 0; var->transp.length = 0;
136 break;
137 case PIXFMT_BGR888UNPACK:
138 var->bits_per_pixel = 32;
139 var->red.offset = 0; var->red.length = 8;
140 var->green.offset = 8; var->green.length = 8;
141 var->blue.offset = 16; var->blue.length = 8;
142 var->transp.offset = 0; var->transp.length = 0;
143 break;
144 case PIXFMT_RGBA888:
145 var->bits_per_pixel = 32;
146 var->red.offset = 16; var->red.length = 8;
147 var->green.offset = 8; var->green.length = 8;
148 var->blue.offset = 0; var->blue.length = 8;
149 var->transp.offset = 24; var->transp.length = 8;
150 break;
151 case PIXFMT_BGRA888:
152 var->bits_per_pixel = 32;
153 var->red.offset = 0; var->red.length = 8;
154 var->green.offset = 8; var->green.length = 8;
155 var->blue.offset = 16; var->blue.length = 8;
156 var->transp.offset = 24; var->transp.length = 8;
157 break;
158 case PIXFMT_RGB888PACK:
159 var->bits_per_pixel = 24;
160 var->red.offset = 16; var->red.length = 8;
161 var->green.offset = 8; var->green.length = 8;
162 var->blue.offset = 0; var->blue.length = 8;
163 var->transp.offset = 0; var->transp.length = 0;
164 break;
165 case PIXFMT_BGR888PACK:
166 var->bits_per_pixel = 24;
167 var->red.offset = 0; var->red.length = 8;
168 var->green.offset = 8; var->green.length = 8;
169 var->blue.offset = 16; var->blue.length = 8;
170 var->transp.offset = 0; var->transp.length = 0;
171 break;
172 case PIXFMT_YUV420P:
173 var->bits_per_pixel = 12;
174 var->red.offset = 4; var->red.length = 8;
175 var->green.offset = 2; var->green.length = 2;
176 var->blue.offset = 0; var->blue.length = 2;
177 var->transp.offset = 0; var->transp.length = 0;
178 break;
179 case PIXFMT_YVU420P:
180 var->bits_per_pixel = 12;
181 var->red.offset = 4; var->red.length = 8;
182 var->green.offset = 0; var->green.length = 2;
183 var->blue.offset = 2; var->blue.length = 2;
184 var->transp.offset = 0; var->transp.length = 0;
185 break;
186 case PIXFMT_YUV422P:
187 var->bits_per_pixel = 16;
188 var->red.offset = 8; var->red.length = 8;
189 var->green.offset = 4; var->green.length = 4;
190 var->blue.offset = 0; var->blue.length = 4;
191 var->transp.offset = 0; var->transp.length = 0;
192 break;
193 case PIXFMT_YVU422P:
194 var->bits_per_pixel = 16;
195 var->red.offset = 8; var->red.length = 8;
196 var->green.offset = 0; var->green.length = 4;
197 var->blue.offset = 4; var->blue.length = 4;
198 var->transp.offset = 0; var->transp.length = 0;
199 break;
200 case PIXFMT_UYVY:
201 var->bits_per_pixel = 16;
202 var->red.offset = 8; var->red.length = 16;
203 var->green.offset = 4; var->green.length = 16;
204 var->blue.offset = 0; var->blue.length = 16;
205 var->transp.offset = 0; var->transp.length = 0;
206 break;
207 case PIXFMT_VYUY:
208 var->bits_per_pixel = 16;
209 var->red.offset = 8; var->red.length = 16;
210 var->green.offset = 0; var->green.length = 16;
211 var->blue.offset = 4; var->blue.length = 16;
212 var->transp.offset = 0; var->transp.length = 0;
213 break;
214 case PIXFMT_YUYV:
215 var->bits_per_pixel = 16;
216 var->red.offset = 0; var->red.length = 16;
217 var->green.offset = 4; var->green.length = 16;
218 var->blue.offset = 8; var->blue.length = 16;
219 var->transp.offset = 0; var->transp.length = 0;
220 break;
221 case PIXFMT_PSEUDOCOLOR:
222 var->bits_per_pixel = 8;
223 var->red.offset = 0; var->red.length = 8;
224 var->green.offset = 0; var->green.length = 8;
225 var->blue.offset = 0; var->blue.length = 8;
226 var->transp.offset = 0; var->transp.length = 0;
227 break;
228 }
229}
230
231/*
232 * fb framework has its limitation:
233 * 1. input color/output color is not seprated
234 * 2. fb_videomode not include output color
235 * so for fb usage, we keep a output format which is not changed
236 * then it's added for mmpmode
237 */
238static void fbmode_to_mmpmode(struct mmp_mode *mode,
239 struct fb_videomode *videomode, int output_fmt)
240{
241 u64 div_result = 1000000000000ll;
242 mode->name = videomode->name;
243 mode->refresh = videomode->refresh;
244 mode->xres = videomode->xres;
245 mode->yres = videomode->yres;
246
247 do_div(div_result, videomode->pixclock);
248 mode->pixclock_freq = (u32)div_result;
249
250 mode->left_margin = videomode->left_margin;
251 mode->right_margin = videomode->right_margin;
252 mode->upper_margin = videomode->upper_margin;
253 mode->lower_margin = videomode->lower_margin;
254 mode->hsync_len = videomode->hsync_len;
255 mode->vsync_len = videomode->vsync_len;
256 mode->hsync_invert = !!(videomode->sync & FB_SYNC_HOR_HIGH_ACT);
257 mode->vsync_invert = !!(videomode->sync & FB_SYNC_VERT_HIGH_ACT);
258 /* no defined flag in fb, use vmode>>3*/
259 mode->invert_pixclock = !!(videomode->vmode & 8);
260 mode->pix_fmt_out = output_fmt;
261}
262
263static void mmpmode_to_fbmode(struct fb_videomode *videomode,
264 struct mmp_mode *mode)
265{
266 u64 div_result = 1000000000000ll;
267
268 videomode->name = mode->name;
269 videomode->refresh = mode->refresh;
270 videomode->xres = mode->xres;
271 videomode->yres = mode->yres;
272
273 do_div(div_result, mode->pixclock_freq);
274 videomode->pixclock = (u32)div_result;
275
276 videomode->left_margin = mode->left_margin;
277 videomode->right_margin = mode->right_margin;
278 videomode->upper_margin = mode->upper_margin;
279 videomode->lower_margin = mode->lower_margin;
280 videomode->hsync_len = mode->hsync_len;
281 videomode->vsync_len = mode->vsync_len;
282 videomode->sync = (mode->hsync_invert ? FB_SYNC_HOR_HIGH_ACT : 0)
283 | (mode->vsync_invert ? FB_SYNC_VERT_HIGH_ACT : 0);
284 videomode->vmode = mode->invert_pixclock ? 8 : 0;
285}
286
287static int mmpfb_check_var(struct fb_var_screeninfo *var,
288 struct fb_info *info)
289{
290 struct mmpfb_info *fbi = info->par;
291
292 if (var->bits_per_pixel == 8)
293 return -EINVAL;
294 /*
295 * Basic geometry sanity checks.
296 */
297 if (var->xoffset + var->xres > var->xres_virtual)
298 return -EINVAL;
299 if (var->yoffset + var->yres > var->yres_virtual)
300 return -EINVAL;
301
302 /*
303 * Check size of framebuffer.
304 */
305 if (var->xres_virtual * var->yres_virtual *
306 (var->bits_per_pixel >> 3) > fbi->fb_size)
307 return -EINVAL;
308
309 return 0;
310}
311
312static unsigned int chan_to_field(unsigned int chan, struct fb_bitfield *bf)
313{
314 return ((chan & 0xffff) >> (16 - bf->length)) << bf->offset;
315}
316
317static u32 to_rgb(u16 red, u16 green, u16 blue)
318{
319 red >>= 8;
320 green >>= 8;
321 blue >>= 8;
322
323 return (red << 16) | (green << 8) | blue;
324}
325
326static int mmpfb_setcolreg(unsigned int regno, unsigned int red,
327 unsigned int green, unsigned int blue,
328 unsigned int trans, struct fb_info *info)
329{
330 struct mmpfb_info *fbi = info->par;
331 u32 val;
332
333 if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16) {
334 val = chan_to_field(red, &info->var.red);
335 val |= chan_to_field(green, &info->var.green);
336 val |= chan_to_field(blue , &info->var.blue);
337 fbi->pseudo_palette[regno] = val;
338 }
339
340 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
341 val = to_rgb(red, green, blue);
342 /* TODO */
343 }
344
345 return 0;
346}
347
348static int mmpfb_pan_display(struct fb_var_screeninfo *var,
349 struct fb_info *info)
350{
351 struct mmpfb_info *fbi = info->par;
352 struct mmp_addr addr;
353
354 memset(&addr, 0, sizeof(addr));
355 addr.phys[0] = (var->yoffset * var->xres_virtual + var->xoffset)
356 * var->bits_per_pixel / 8 + fbi->fb_start_dma;
357 mmp_overlay_set_addr(fbi->overlay, &addr);
358
359 return 0;
360}
361
362static int var_update(struct fb_info *info)
363{
364 struct mmpfb_info *fbi = info->par;
365 struct fb_var_screeninfo *var = &info->var;
366 struct fb_videomode *m;
367 int pix_fmt;
368
369 /* set pix_fmt */
370 pix_fmt = var_to_pixfmt(var);
371 if (pix_fmt < 0)
372 return -EINVAL;
373 pixfmt_to_var(var, pix_fmt);
374 fbi->pix_fmt = pix_fmt;
375
376 /* set var according to best video mode*/
377 m = (struct fb_videomode *)fb_match_mode(var, &info->modelist);
378 if (!m) {
379 dev_err(fbi->dev, "set par: no match mode, use best mode\n");
380 m = (struct fb_videomode *)fb_find_best_mode(var,
381 &info->modelist);
382 fb_videomode_to_var(var, m);
383 }
384 memcpy(&fbi->mode, m, sizeof(struct fb_videomode));
385
386 /* fix to 2* yres */
387 var->yres_virtual = var->yres * 2;
388 info->fix.visual = (pix_fmt == PIXFMT_PSEUDOCOLOR) ?
389 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
390 info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
391 info->fix.ypanstep = var->yres;
392 return 0;
393}
394
395static void mmpfb_set_win(struct fb_info *info)
396{
397 struct mmpfb_info *fbi = info->par;
398 struct fb_var_screeninfo *var = &info->var;
399 struct mmp_win win;
400 u32 stride;
401
402 memset(&win, 0, sizeof(win));
403 win.xsrc = win.xdst = fbi->mode.xres;
404 win.ysrc = win.ydst = fbi->mode.yres;
405 win.pix_fmt = fbi->pix_fmt;
406 stride = pixfmt_to_stride(win.pix_fmt);
407 win.pitch[0] = var->xres_virtual * stride;
408 win.pitch[1] = win.pitch[2] =
409 (stride == 1) ? (var->xres_virtual >> 1) : 0;
410 mmp_overlay_set_win(fbi->overlay, &win);
411}
412
413static int mmpfb_set_par(struct fb_info *info)
414{
415 struct mmpfb_info *fbi = info->par;
416 struct fb_var_screeninfo *var = &info->var;
417 struct mmp_addr addr;
418 struct mmp_mode mode;
419 int ret;
420
421 ret = var_update(info);
422 if (ret != 0)
423 return ret;
424
425 /* set window/path according to new videomode */
426 fbmode_to_mmpmode(&mode, &fbi->mode, fbi->output_fmt);
427 mmp_path_set_mode(fbi->path, &mode);
428
429 /* set window related info */
430 mmpfb_set_win(info);
431
432 /* set address always */
433 memset(&addr, 0, sizeof(addr));
434 addr.phys[0] = (var->yoffset * var->xres_virtual + var->xoffset)
435 * var->bits_per_pixel / 8 + fbi->fb_start_dma;
436 mmp_overlay_set_addr(fbi->overlay, &addr);
437
438 return 0;
439}
440
441static void mmpfb_power(struct mmpfb_info *fbi, int power)
442{
443 struct mmp_addr addr;
444 struct fb_var_screeninfo *var = &fbi->fb_info->var;
445
446 /* for power on, always set address/window again */
447 if (power) {
448 /* set window related info */
449 mmpfb_set_win(fbi->fb_info);
450
451 /* set address always */
452 memset(&addr, 0, sizeof(addr));
453 addr.phys[0] = fbi->fb_start_dma +
454 (var->yoffset * var->xres_virtual + var->xoffset)
455 * var->bits_per_pixel / 8;
456 mmp_overlay_set_addr(fbi->overlay, &addr);
457 }
458 mmp_overlay_set_onoff(fbi->overlay, power);
459}
460
461static int mmpfb_blank(int blank, struct fb_info *info)
462{
463 struct mmpfb_info *fbi = info->par;
464
465 mmpfb_power(fbi, (blank == FB_BLANK_UNBLANK));
466
467 return 0;
468}
469
470static struct fb_ops mmpfb_ops = {
471 .owner = THIS_MODULE,
472 .fb_blank = mmpfb_blank,
473 .fb_check_var = mmpfb_check_var,
474 .fb_set_par = mmpfb_set_par,
475 .fb_setcolreg = mmpfb_setcolreg,
476 .fb_pan_display = mmpfb_pan_display,
477 .fb_fillrect = cfb_fillrect,
478 .fb_copyarea = cfb_copyarea,
479 .fb_imageblit = cfb_imageblit,
480};
481
482static int modes_setup(struct mmpfb_info *fbi)
483{
484 struct fb_videomode *videomodes;
485 struct mmp_mode *mmp_modes;
486 struct fb_info *info = fbi->fb_info;
487 int videomode_num, i;
488
489 /* get videomodes from path */
490 videomode_num = mmp_path_get_modelist(fbi->path, &mmp_modes);
491 if (!videomode_num) {
492 dev_warn(fbi->dev, "can't get videomode num\n");
493 return 0;
494 }
495 /* put videomode list to info structure */
496 videomodes = kzalloc(sizeof(struct fb_videomode) * videomode_num,
497 GFP_KERNEL);
498 if (!videomodes) {
499 dev_err(fbi->dev, "can't malloc video modes\n");
500 return -ENOMEM;
501 }
502 for (i = 0; i < videomode_num; i++)
503 mmpmode_to_fbmode(&videomodes[i], &mmp_modes[i]);
504 fb_videomode_to_modelist(videomodes, videomode_num, &info->modelist);
505
506 /* set videomode[0] as default mode */
507 memcpy(&fbi->mode, &videomodes[0], sizeof(struct fb_videomode));
508 fbi->output_fmt = mmp_modes[0].pix_fmt_out;
509 fb_videomode_to_var(&info->var, &fbi->mode);
510 mmp_path_set_mode(fbi->path, &mmp_modes[0]);
511
512 kfree(videomodes);
513 return videomode_num;
514}
515
516static int fb_info_setup(struct fb_info *info,
517 struct mmpfb_info *fbi)
518{
519 int ret = 0;
520 /* Initialise static fb parameters.*/
521 info->flags = FBINFO_DEFAULT | FBINFO_PARTIAL_PAN_OK |
522 FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
523 info->node = -1;
524 strcpy(info->fix.id, fbi->name);
525 info->fix.type = FB_TYPE_PACKED_PIXELS;
526 info->fix.type_aux = 0;
527 info->fix.xpanstep = 0;
528 info->fix.ypanstep = info->var.yres;
529 info->fix.ywrapstep = 0;
530 info->fix.accel = FB_ACCEL_NONE;
531 info->fix.smem_start = fbi->fb_start_dma;
532 info->fix.smem_len = fbi->fb_size;
533 info->fix.visual = (fbi->pix_fmt == PIXFMT_PSEUDOCOLOR) ?
534 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
535 info->fix.line_length = info->var.xres_virtual *
536 info->var.bits_per_pixel / 8;
537 info->fbops = &mmpfb_ops;
538 info->pseudo_palette = fbi->pseudo_palette;
539 info->screen_base = fbi->fb_start;
540 info->screen_size = fbi->fb_size;
541
542 /* For FB framework: Allocate color map and Register framebuffer*/
543 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
544 ret = -ENOMEM;
545
546 return ret;
547}
548
549static void fb_info_clear(struct fb_info *info)
550{
551 fb_dealloc_cmap(&info->cmap);
552}
553
554static int mmpfb_probe(struct platform_device *pdev)
555{
556 struct mmp_buffer_driver_mach_info *mi;
557 struct fb_info *info = 0;
558 struct mmpfb_info *fbi = 0;
559 int ret, modes_num;
560
561 mi = pdev->dev.platform_data;
562 if (mi == NULL) {
563 dev_err(&pdev->dev, "no platform data defined\n");
564 return -EINVAL;
565 }
566
567 /* initialize fb */
568 info = framebuffer_alloc(sizeof(struct mmpfb_info), &pdev->dev);
569 if (info == NULL)
570 return -ENOMEM;
571 fbi = info->par;
572 if (!fbi) {
573 ret = -EINVAL;
574 goto failed;
575 }
576
577 /* init fb */
578 fbi->fb_info = info;
579 platform_set_drvdata(pdev, fbi);
580 fbi->dev = &pdev->dev;
581 fbi->name = mi->name;
582 fbi->pix_fmt = mi->default_pixfmt;
583 pixfmt_to_var(&info->var, fbi->pix_fmt);
584 mutex_init(&fbi->access_ok);
585
586 /* get display path by name */
587 fbi->path = mmp_get_path(mi->path_name);
588 if (!fbi->path) {
589 dev_err(&pdev->dev, "can't get the path %s\n", mi->path_name);
590 ret = -EINVAL;
591 goto failed_destroy_mutex;
592 }
593
594 dev_info(fbi->dev, "path %s get\n", fbi->path->name);
595
596 /* get overlay */
597 fbi->overlay = mmp_path_get_overlay(fbi->path, mi->overlay_id);
598 if (!fbi->overlay) {
599 ret = -EINVAL;
600 goto failed_destroy_mutex;
601 }
602 /* set fetch used */
603 mmp_overlay_set_fetch(fbi->overlay, mi->dmafetch_id);
604
605 modes_num = modes_setup(fbi);
606 if (modes_num < 0) {
607 ret = modes_num;
608 goto failed_destroy_mutex;
609 }
610
611 /*
612 * if get modes success, means not hotplug panels, use caculated buffer
613 * or use default size
614 */
615 if (modes_num > 0) {
616 /* fix to 2* yres */
617 info->var.yres_virtual = info->var.yres * 2;
618
619 /* Allocate framebuffer memory: size = modes xy *4 */
620 fbi->fb_size = info->var.xres_virtual * info->var.yres_virtual
621 * info->var.bits_per_pixel / 8;
622 } else {
623 fbi->fb_size = MMPFB_DEFAULT_SIZE;
624 }
625
626 fbi->fb_start = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(fbi->fb_size),
627 &fbi->fb_start_dma, GFP_KERNEL);
628 if (fbi->fb_start == NULL) {
629 dev_err(&pdev->dev, "can't alloc framebuffer\n");
630 ret = -ENOMEM;
631 goto failed_destroy_mutex;
632 }
633 memset(fbi->fb_start, 0, fbi->fb_size);
634 dev_info(fbi->dev, "fb %dk allocated\n", fbi->fb_size/1024);
635
636 /* fb power on */
637 if (modes_num > 0)
638 mmpfb_power(fbi, 1);
639
640 ret = fb_info_setup(info, fbi);
641 if (ret < 0)
642 goto failed_free_buff;
643
644 ret = register_framebuffer(info);
645 if (ret < 0) {
646 dev_err(&pdev->dev, "Failed to register fb: %d\n", ret);
647 ret = -ENXIO;
648 goto failed_clear_info;
649 }
650
651 dev_info(fbi->dev, "loaded to /dev/fb%d <%s>.\n",
652 info->node, info->fix.id);
653
654#ifdef CONFIG_LOGO
655 if (fbi->fb_start) {
656 fb_prepare_logo(info, 0);
657 fb_show_logo(info, 0);
658 }
659#endif
660
661 return 0;
662
663failed_clear_info:
664 fb_info_clear(info);
665failed_free_buff:
666 dma_free_coherent(&pdev->dev, PAGE_ALIGN(fbi->fb_size), fbi->fb_start,
667 fbi->fb_start_dma);
668failed_destroy_mutex:
669 mutex_destroy(&fbi->access_ok);
670failed:
671 dev_err(fbi->dev, "mmp-fb: frame buffer device init failed\n");
672
673 framebuffer_release(info);
674
675 return ret;
676}
677
678static struct platform_driver mmpfb_driver = {
679 .driver = {
680 .name = "mmp-fb",
681 .owner = THIS_MODULE,
682 },
683 .probe = mmpfb_probe,
684};
685
686static int mmpfb_init(void)
687{
688 return platform_driver_register(&mmpfb_driver);
689}
690module_init(mmpfb_init);
691
692MODULE_AUTHOR("Zhou Zhu <zhou.zhu@marvell.com>");
693MODULE_DESCRIPTION("Framebuffer driver for Marvell displays");
694MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/mmp/fb/mmpfb.h b/drivers/video/fbdev/mmp/fb/mmpfb.h
new file mode 100644
index 000000000000..88c23c10a9ec
--- /dev/null
+++ b/drivers/video/fbdev/mmp/fb/mmpfb.h
@@ -0,0 +1,54 @@
1/*
2 * linux/drivers/video/mmp/fb/mmpfb.h
3 * Framebuffer driver for Marvell Display controller.
4 *
5 * Copyright (C) 2012 Marvell Technology Group Ltd.
6 * Authors: Zhou Zhu <zzhu3@marvell.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22
23#ifndef _MMP_FB_H_
24#define _MMP_FB_H_
25
26#include <video/mmp_disp.h>
27#include <linux/fb.h>
28
29/* LCD controller private state. */
30struct mmpfb_info {
31 struct device *dev;
32 int id;
33 const char *name;
34
35 struct fb_info *fb_info;
36 /* basicaly videomode is for output */
37 struct fb_videomode mode;
38 int pix_fmt;
39
40 void *fb_start;
41 int fb_size;
42 dma_addr_t fb_start_dma;
43
44 struct mmp_overlay *overlay;
45 struct mmp_path *path;
46
47 struct mutex access_ok;
48
49 unsigned int pseudo_palette[16];
50 int output_fmt;
51};
52
53#define MMPFB_DEFAULT_SIZE (PAGE_ALIGN(1920 * 1080 * 4 * 2))
54#endif /* _MMP_FB_H_ */
diff --git a/drivers/video/fbdev/mmp/hw/Kconfig b/drivers/video/fbdev/mmp/hw/Kconfig
new file mode 100644
index 000000000000..02f109a20cd0
--- /dev/null
+++ b/drivers/video/fbdev/mmp/hw/Kconfig
@@ -0,0 +1,20 @@
1if MMP_DISP
2
3config MMP_DISP_CONTROLLER
4 bool "mmp display controller hw support"
5 depends on CPU_PXA910 || CPU_MMP2 || CPU_MMP3 || CPU_PXA988
6 default n
7 help
8 Marvell MMP display hw controller support
9 this controller is used on Marvell PXA910,
10 MMP2, MMP3, PXA988 chips
11
12config MMP_DISP_SPI
13 bool "mmp display controller spi port"
14 depends on MMP_DISP_CONTROLLER && SPI_MASTER
15 default y
16 help
17 Marvell MMP display hw controller spi port support
18 will register as a spi master for panel usage
19
20endif
diff --git a/drivers/video/fbdev/mmp/hw/Makefile b/drivers/video/fbdev/mmp/hw/Makefile
new file mode 100644
index 000000000000..0000a714fedf
--- /dev/null
+++ b/drivers/video/fbdev/mmp/hw/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_MMP_DISP_CONTROLLER) += mmp_ctrl.o
2obj-$(CONFIG_MMP_DISP_SPI) += mmp_spi.o
diff --git a/drivers/video/fbdev/mmp/hw/mmp_ctrl.c b/drivers/video/fbdev/mmp/hw/mmp_ctrl.c
new file mode 100644
index 000000000000..8621a9f2bdcc
--- /dev/null
+++ b/drivers/video/fbdev/mmp/hw/mmp_ctrl.c
@@ -0,0 +1,588 @@
1/*
2 * linux/drivers/video/mmp/hw/mmp_ctrl.c
3 * Marvell MMP series Display Controller support
4 *
5 * Copyright (C) 2012 Marvell Technology Group Ltd.
6 * Authors: Guoqing Li <ligq@marvell.com>
7 * Lisa Du <cldu@marvell.com>
8 * Zhou Zhu <zzhu3@marvell.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
22 *
23 */
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/kernel.h>
27#include <linux/errno.h>
28#include <linux/string.h>
29#include <linux/interrupt.h>
30#include <linux/slab.h>
31#include <linux/delay.h>
32#include <linux/platform_device.h>
33#include <linux/dma-mapping.h>
34#include <linux/clk.h>
35#include <linux/err.h>
36#include <linux/vmalloc.h>
37#include <linux/uaccess.h>
38#include <linux/kthread.h>
39#include <linux/io.h>
40
41#include "mmp_ctrl.h"
42
43static irqreturn_t ctrl_handle_irq(int irq, void *dev_id)
44{
45 struct mmphw_ctrl *ctrl = (struct mmphw_ctrl *)dev_id;
46 u32 isr, imask, tmp;
47
48 isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
49 imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
50
51 do {
52 /* clear clock only */
53 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
54 if (tmp & isr)
55 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR);
56 } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask);
57
58 return IRQ_HANDLED;
59}
60
61static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt)
62{
63 u32 rbswap = 0, uvswap = 0, yuvswap = 0,
64 csc_en = 0, val = 0,
65 vid = overlay_is_vid(overlay);
66
67 switch (pix_fmt) {
68 case PIXFMT_RGB565:
69 case PIXFMT_RGB1555:
70 case PIXFMT_RGB888PACK:
71 case PIXFMT_RGB888UNPACK:
72 case PIXFMT_RGBA888:
73 rbswap = 1;
74 break;
75 case PIXFMT_VYUY:
76 case PIXFMT_YVU422P:
77 case PIXFMT_YVU420P:
78 uvswap = 1;
79 break;
80 case PIXFMT_YUYV:
81 yuvswap = 1;
82 break;
83 default:
84 break;
85 }
86
87 switch (pix_fmt) {
88 case PIXFMT_RGB565:
89 case PIXFMT_BGR565:
90 break;
91 case PIXFMT_RGB1555:
92 case PIXFMT_BGR1555:
93 val = 0x1;
94 break;
95 case PIXFMT_RGB888PACK:
96 case PIXFMT_BGR888PACK:
97 val = 0x2;
98 break;
99 case PIXFMT_RGB888UNPACK:
100 case PIXFMT_BGR888UNPACK:
101 val = 0x3;
102 break;
103 case PIXFMT_RGBA888:
104 case PIXFMT_BGRA888:
105 val = 0x4;
106 break;
107 case PIXFMT_UYVY:
108 case PIXFMT_VYUY:
109 case PIXFMT_YUYV:
110 val = 0x5;
111 csc_en = 1;
112 break;
113 case PIXFMT_YUV422P:
114 case PIXFMT_YVU422P:
115 val = 0x6;
116 csc_en = 1;
117 break;
118 case PIXFMT_YUV420P:
119 case PIXFMT_YVU420P:
120 val = 0x7;
121 csc_en = 1;
122 break;
123 default:
124 break;
125 }
126
127 return (dma_palette(0) | dma_fmt(vid, val) |
128 dma_swaprb(vid, rbswap) | dma_swapuv(vid, uvswap) |
129 dma_swapyuv(vid, yuvswap) | dma_csc(vid, csc_en));
130}
131
132static void dmafetch_set_fmt(struct mmp_overlay *overlay)
133{
134 u32 tmp;
135 struct mmp_path *path = overlay->path;
136 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
137 tmp &= ~dma_mask(overlay_is_vid(overlay));
138 tmp |= fmt_to_reg(overlay, overlay->win.pix_fmt);
139 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
140}
141
142static void overlay_set_win(struct mmp_overlay *overlay, struct mmp_win *win)
143{
144 struct lcd_regs *regs = path_regs(overlay->path);
145
146 /* assert win supported */
147 memcpy(&overlay->win, win, sizeof(struct mmp_win));
148
149 mutex_lock(&overlay->access_ok);
150
151 if (overlay_is_vid(overlay)) {
152 writel_relaxed(win->pitch[0], &regs->v_pitch_yc);
153 writel_relaxed(win->pitch[2] << 16 |
154 win->pitch[1], &regs->v_pitch_uv);
155
156 writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->v_size);
157 writel_relaxed((win->ydst << 16) | win->xdst, &regs->v_size_z);
158 writel_relaxed(win->ypos << 16 | win->xpos, &regs->v_start);
159 } else {
160 writel_relaxed(win->pitch[0], &regs->g_pitch);
161
162 writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->g_size);
163 writel_relaxed((win->ydst << 16) | win->xdst, &regs->g_size_z);
164 writel_relaxed(win->ypos << 16 | win->xpos, &regs->g_start);
165 }
166
167 dmafetch_set_fmt(overlay);
168 mutex_unlock(&overlay->access_ok);
169}
170
171static void dmafetch_onoff(struct mmp_overlay *overlay, int on)
172{
173 u32 mask = overlay_is_vid(overlay) ? CFG_DMA_ENA_MASK :
174 CFG_GRA_ENA_MASK;
175 u32 enable = overlay_is_vid(overlay) ? CFG_DMA_ENA(1) : CFG_GRA_ENA(1);
176 u32 tmp;
177 struct mmp_path *path = overlay->path;
178
179 mutex_lock(&overlay->access_ok);
180 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
181 tmp &= ~mask;
182 tmp |= (on ? enable : 0);
183 writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
184 mutex_unlock(&overlay->access_ok);
185}
186
187static void path_enabledisable(struct mmp_path *path, int on)
188{
189 u32 tmp;
190 mutex_lock(&path->access_ok);
191 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
192 if (on)
193 tmp &= ~SCLK_DISABLE;
194 else
195 tmp |= SCLK_DISABLE;
196 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
197 mutex_unlock(&path->access_ok);
198}
199
200static void path_onoff(struct mmp_path *path, int on)
201{
202 if (path->status == on) {
203 dev_info(path->dev, "path %s is already %s\n",
204 path->name, stat_name(path->status));
205 return;
206 }
207
208 if (on) {
209 path_enabledisable(path, 1);
210
211 if (path->panel && path->panel->set_onoff)
212 path->panel->set_onoff(path->panel, 1);
213 } else {
214 if (path->panel && path->panel->set_onoff)
215 path->panel->set_onoff(path->panel, 0);
216
217 path_enabledisable(path, 0);
218 }
219 path->status = on;
220}
221
222static void overlay_set_onoff(struct mmp_overlay *overlay, int on)
223{
224 if (overlay->status == on) {
225 dev_info(overlay_to_ctrl(overlay)->dev, "overlay %s is already %s\n",
226 overlay->path->name, stat_name(overlay->status));
227 return;
228 }
229 overlay->status = on;
230 dmafetch_onoff(overlay, on);
231 if (overlay->path->ops.check_status(overlay->path)
232 != overlay->path->status)
233 path_onoff(overlay->path, on);
234}
235
236static void overlay_set_fetch(struct mmp_overlay *overlay, int fetch_id)
237{
238 overlay->dmafetch_id = fetch_id;
239}
240
241static int overlay_set_addr(struct mmp_overlay *overlay, struct mmp_addr *addr)
242{
243 struct lcd_regs *regs = path_regs(overlay->path);
244
245 /* FIXME: assert addr supported */
246 memcpy(&overlay->addr, addr, sizeof(struct mmp_addr));
247
248 if (overlay_is_vid(overlay)) {
249 writel_relaxed(addr->phys[0], &regs->v_y0);
250 writel_relaxed(addr->phys[1], &regs->v_u0);
251 writel_relaxed(addr->phys[2], &regs->v_v0);
252 } else
253 writel_relaxed(addr->phys[0], &regs->g_0);
254
255 return overlay->addr.phys[0];
256}
257
258static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode)
259{
260 struct lcd_regs *regs = path_regs(path);
261 u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div,
262 link_config = path_to_path_plat(path)->link_config,
263 dsi_rbswap = path_to_path_plat(path)->link_config;
264
265 /* FIXME: assert videomode supported */
266 memcpy(&path->mode, mode, sizeof(struct mmp_mode));
267
268 mutex_lock(&path->access_ok);
269
270 /* polarity of timing signals */
271 tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1;
272 tmp |= mode->vsync_invert ? 0 : 0x8;
273 tmp |= mode->hsync_invert ? 0 : 0x4;
274 tmp |= link_config & CFG_DUMBMODE_MASK;
275 tmp |= CFG_DUMB_ENA(1);
276 writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));
277
278 /* interface rb_swap setting */
279 tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &
280 (~(CFG_INTFRBSWAP_MASK));
281 tmp |= dsi_rbswap & CFG_INTFRBSWAP_MASK;
282 writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));
283
284 writel_relaxed((mode->yres << 16) | mode->xres, &regs->screen_active);
285 writel_relaxed((mode->left_margin << 16) | mode->right_margin,
286 &regs->screen_h_porch);
287 writel_relaxed((mode->upper_margin << 16) | mode->lower_margin,
288 &regs->screen_v_porch);
289 total_x = mode->xres + mode->left_margin + mode->right_margin +
290 mode->hsync_len;
291 total_y = mode->yres + mode->upper_margin + mode->lower_margin +
292 mode->vsync_len;
293 writel_relaxed((total_y << 16) | total_x, &regs->screen_size);
294
295 /* vsync ctrl */
296 if (path->output_type == PATH_OUT_DSI)
297 vsync_ctrl = 0x01330133;
298 else
299 vsync_ctrl = ((mode->xres + mode->right_margin) << 16)
300 | (mode->xres + mode->right_margin);
301 writel_relaxed(vsync_ctrl, &regs->vsync_ctrl);
302
303 /* set pixclock div */
304 sclk_src = clk_get_rate(path_to_ctrl(path)->clk);
305 sclk_div = sclk_src / mode->pixclock_freq;
306 if (sclk_div * mode->pixclock_freq < sclk_src)
307 sclk_div++;
308
309 dev_info(path->dev, "%s sclk_src %d sclk_div 0x%x pclk %d\n",
310 __func__, sclk_src, sclk_div, mode->pixclock_freq);
311
312 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
313 tmp &= ~CLK_INT_DIV_MASK;
314 tmp |= sclk_div;
315 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
316
317 mutex_unlock(&path->access_ok);
318}
319
320static struct mmp_overlay_ops mmphw_overlay_ops = {
321 .set_fetch = overlay_set_fetch,
322 .set_onoff = overlay_set_onoff,
323 .set_win = overlay_set_win,
324 .set_addr = overlay_set_addr,
325};
326
327static void ctrl_set_default(struct mmphw_ctrl *ctrl)
328{
329 u32 tmp, irq_mask;
330
331 /*
332 * LCD Global control(LCD_TOP_CTRL) should be configed before
333 * any other LCD registers read/write, or there maybe issues.
334 */
335 tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL);
336 tmp |= 0xfff0;
337 writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);
338
339
340 /* disable all interrupts */
341 irq_mask = path_imasks(0) | err_imask(0) |
342 path_imasks(1) | err_imask(1);
343 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
344 tmp &= ~irq_mask;
345 tmp |= irq_mask;
346 writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);
347}
348
349static void path_set_default(struct mmp_path *path)
350{
351 struct lcd_regs *regs = path_regs(path);
352 u32 dma_ctrl1, mask, tmp, path_config;
353
354 path_config = path_to_path_plat(path)->path_config;
355
356 /* Configure IOPAD: should be parallel only */
357 if (PATH_OUT_PARALLEL == path->output_type) {
358 mask = CFG_IOPADMODE_MASK | CFG_BURST_MASK | CFG_BOUNDARY_MASK;
359 tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL);
360 tmp &= ~mask;
361 tmp |= path_config;
362 writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);
363 }
364
365 /* Select path clock source */
366 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
367 tmp &= ~SCLK_SRC_SEL_MASK;
368 tmp |= path_config;
369 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
370
371 /*
372 * Configure default bits: vsync triggers DMA,
373 * power save enable, configure alpha registers to
374 * display 100% graphics, and set pixel command.
375 */
376 dma_ctrl1 = 0x2032ff81;
377
378 dma_ctrl1 |= CFG_VSYNC_INV_MASK;
379 writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));
380
381 /* Configure default register values */
382 writel_relaxed(0x00000000, &regs->blank_color);
383 writel_relaxed(0x00000000, &regs->g_1);
384 writel_relaxed(0x00000000, &regs->g_start);
385
386 /*
387 * 1.enable multiple burst request in DMA AXI
388 * bus arbiter for faster read if not tv path;
389 * 2.enable horizontal smooth filter;
390 */
391 mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | CFG_ARBFAST_ENA(1);
392 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
393 tmp |= mask;
394 if (PATH_TV == path->id)
395 tmp &= ~CFG_ARBFAST_ENA(1);
396 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
397}
398
399static int path_init(struct mmphw_path_plat *path_plat,
400 struct mmp_mach_path_config *config)
401{
402 struct mmphw_ctrl *ctrl = path_plat->ctrl;
403 struct mmp_path_info *path_info;
404 struct mmp_path *path = NULL;
405
406 dev_info(ctrl->dev, "%s: %s\n", __func__, config->name);
407
408 /* init driver data */
409 path_info = kzalloc(sizeof(struct mmp_path_info), GFP_KERNEL);
410 if (!path_info) {
411 dev_err(ctrl->dev, "%s: unable to alloc path_info for %s\n",
412 __func__, config->name);
413 return 0;
414 }
415 path_info->name = config->name;
416 path_info->id = path_plat->id;
417 path_info->dev = ctrl->dev;
418 path_info->overlay_num = config->overlay_num;
419 path_info->overlay_ops = &mmphw_overlay_ops;
420 path_info->set_mode = path_set_mode;
421 path_info->plat_data = path_plat;
422
423 /* create/register platform device */
424 path = mmp_register_path(path_info);
425 if (!path) {
426 kfree(path_info);
427 return 0;
428 }
429 path_plat->path = path;
430 path_plat->path_config = config->path_config;
431 path_plat->link_config = config->link_config;
432 path_plat->dsi_rbswap = config->dsi_rbswap;
433 path_set_default(path);
434
435 kfree(path_info);
436 return 1;
437}
438
439static void path_deinit(struct mmphw_path_plat *path_plat)
440{
441 if (!path_plat)
442 return;
443
444 if (path_plat->path)
445 mmp_unregister_path(path_plat->path);
446}
447
448static int mmphw_probe(struct platform_device *pdev)
449{
450 struct mmp_mach_plat_info *mi;
451 struct resource *res;
452 int ret, i, size, irq;
453 struct mmphw_path_plat *path_plat;
454 struct mmphw_ctrl *ctrl = NULL;
455
456 /* get resources from platform data */
457 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
458 if (res == NULL) {
459 dev_err(&pdev->dev, "%s: no IO memory defined\n", __func__);
460 ret = -ENOENT;
461 goto failed;
462 }
463
464 irq = platform_get_irq(pdev, 0);
465 if (irq < 0) {
466 dev_err(&pdev->dev, "%s: no IRQ defined\n", __func__);
467 ret = -ENOENT;
468 goto failed;
469 }
470
471 /* get configs from platform data */
472 mi = pdev->dev.platform_data;
473 if (mi == NULL || !mi->path_num || !mi->paths) {
474 dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
475 ret = -EINVAL;
476 goto failed;
477 }
478
479 /* allocate */
480 size = sizeof(struct mmphw_ctrl) + sizeof(struct mmphw_path_plat) *
481 mi->path_num;
482 ctrl = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
483 if (!ctrl) {
484 ret = -ENOMEM;
485 goto failed;
486 }
487
488 ctrl->name = mi->name;
489 ctrl->path_num = mi->path_num;
490 ctrl->dev = &pdev->dev;
491 ctrl->irq = irq;
492 platform_set_drvdata(pdev, ctrl);
493 mutex_init(&ctrl->access_ok);
494
495 /* map registers.*/
496 if (!devm_request_mem_region(ctrl->dev, res->start,
497 resource_size(res), ctrl->name)) {
498 dev_err(ctrl->dev,
499 "can't request region for resource %pR\n", res);
500 ret = -EINVAL;
501 goto failed;
502 }
503
504 ctrl->reg_base = devm_ioremap_nocache(ctrl->dev,
505 res->start, resource_size(res));
506 if (ctrl->reg_base == NULL) {
507 dev_err(ctrl->dev, "%s: res %x - %x map failed\n", __func__,
508 res->start, res->end);
509 ret = -ENOMEM;
510 goto failed;
511 }
512
513 /* request irq */
514 ret = devm_request_irq(ctrl->dev, ctrl->irq, ctrl_handle_irq,
515 IRQF_SHARED, "lcd_controller", ctrl);
516 if (ret < 0) {
517 dev_err(ctrl->dev, "%s unable to request IRQ %d\n",
518 __func__, ctrl->irq);
519 ret = -ENXIO;
520 goto failed;
521 }
522
523 /* get clock */
524 ctrl->clk = devm_clk_get(ctrl->dev, mi->clk_name);
525 if (IS_ERR(ctrl->clk)) {
526 dev_err(ctrl->dev, "unable to get clk %s\n", mi->clk_name);
527 ret = -ENOENT;
528 goto failed;
529 }
530 clk_prepare_enable(ctrl->clk);
531
532 /* init global regs */
533 ctrl_set_default(ctrl);
534
535 /* init pathes from machine info and register them */
536 for (i = 0; i < ctrl->path_num; i++) {
537 /* get from config and machine info */
538 path_plat = &ctrl->path_plats[i];
539 path_plat->id = i;
540 path_plat->ctrl = ctrl;
541
542 /* path init */
543 if (!path_init(path_plat, &mi->paths[i])) {
544 ret = -EINVAL;
545 goto failed_path_init;
546 }
547 }
548
549#ifdef CONFIG_MMP_DISP_SPI
550 ret = lcd_spi_register(ctrl);
551 if (ret < 0)
552 goto failed_path_init;
553#endif
554
555 dev_info(ctrl->dev, "device init done\n");
556
557 return 0;
558
559failed_path_init:
560 for (i = 0; i < ctrl->path_num; i++) {
561 path_plat = &ctrl->path_plats[i];
562 path_deinit(path_plat);
563 }
564
565 clk_disable_unprepare(ctrl->clk);
566failed:
567 dev_err(&pdev->dev, "device init failed\n");
568
569 return ret;
570}
571
572static struct platform_driver mmphw_driver = {
573 .driver = {
574 .name = "mmp-disp",
575 .owner = THIS_MODULE,
576 },
577 .probe = mmphw_probe,
578};
579
580static int mmphw_init(void)
581{
582 return platform_driver_register(&mmphw_driver);
583}
584module_init(mmphw_init);
585
586MODULE_AUTHOR("Li Guoqing<ligq@marvell.com>");
587MODULE_DESCRIPTION("Framebuffer driver for mmp");
588MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/mmp/hw/mmp_ctrl.h b/drivers/video/fbdev/mmp/hw/mmp_ctrl.h
new file mode 100644
index 000000000000..53301cfdb1ae
--- /dev/null
+++ b/drivers/video/fbdev/mmp/hw/mmp_ctrl.h
@@ -0,0 +1,1502 @@
1/*
2 * drivers/video/mmp/hw/mmp_ctrl.h
3 *
4 *
5 * Copyright (C) 2012 Marvell Technology Group Ltd.
6 * Authors: Guoqing Li <ligq@marvell.com>
7 * Lisa Du <cldu@marvell.com>
8 * Zhou Zhu <zzhu3@marvell.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
22 *
23 */
24
25#ifndef _MMP_CTRL_H_
26#define _MMP_CTRL_H_
27
28#include <video/mmp_disp.h>
29
30/* ------------< LCD register >------------ */
31struct lcd_regs {
32/* TV patch register for MMP2 */
33/* 32 bit TV Video Frame0 Y Starting Address */
34#define LCD_TVD_START_ADDR_Y0 (0x0000)
35/* 32 bit TV Video Frame0 U Starting Address */
36#define LCD_TVD_START_ADDR_U0 (0x0004)
37/* 32 bit TV Video Frame0 V Starting Address */
38#define LCD_TVD_START_ADDR_V0 (0x0008)
39/* 32 bit TV Video Frame0 Command Starting Address */
40#define LCD_TVD_START_ADDR_C0 (0x000C)
41/* 32 bit TV Video Frame1 Y Starting Address Register*/
42#define LCD_TVD_START_ADDR_Y1 (0x0010)
43/* 32 bit TV Video Frame1 U Starting Address Register*/
44#define LCD_TVD_START_ADDR_U1 (0x0014)
45/* 32 bit TV Video Frame1 V Starting Address Register*/
46#define LCD_TVD_START_ADDR_V1 (0x0018)
47/* 32 bit TV Video Frame1 Command Starting Address Register*/
48#define LCD_TVD_START_ADDR_C1 (0x001C)
49/* 32 bit TV Video Y andC Line Length(Pitch)Register*/
50#define LCD_TVD_PITCH_YC (0x0020)
51/* 32 bit TV Video U andV Line Length(Pitch)Register*/
52#define LCD_TVD_PITCH_UV (0x0024)
53/* 32 bit TV Video Starting Point on Screen Register*/
54#define LCD_TVD_OVSA_HPXL_VLN (0x0028)
55/* 32 bit TV Video Source Size Register*/
56#define LCD_TVD_HPXL_VLN (0x002C)
57/* 32 bit TV Video Destination Size (After Zooming)Register*/
58#define LCD_TVDZM_HPXL_VLN (0x0030)
59 u32 v_y0;
60 u32 v_u0;
61 u32 v_v0;
62 u32 v_c0;
63 u32 v_y1;
64 u32 v_u1;
65 u32 v_v1;
66 u32 v_c1;
67 u32 v_pitch_yc; /* Video Y and C Line Length (Pitch) */
68 u32 v_pitch_uv; /* Video U and V Line Length (Pitch) */
69 u32 v_start; /* Video Starting Point on Screen */
70 u32 v_size; /* Video Source Size */
71 u32 v_size_z; /* Video Destination Size (After Zooming) */
72
73/* 32 bit TV Graphic Frame 0 Starting Address Register*/
74#define LCD_TVG_START_ADDR0 (0x0034)
75/* 32 bit TV Graphic Frame 1 Starting Address Register*/
76#define LCD_TVG_START_ADDR1 (0x0038)
77/* 32 bit TV Graphic Line Length(Pitch)Register*/
78#define LCD_TVG_PITCH (0x003C)
79/* 32 bit TV Graphic Starting Point on Screen Register*/
80#define LCD_TVG_OVSA_HPXL_VLN (0x0040)
81/* 32 bit TV Graphic Source Size Register*/
82#define LCD_TVG_HPXL_VLN (0x0044)
83/* 32 bit TV Graphic Destination size (after Zooming)Register*/
84#define LCD_TVGZM_HPXL_VLN (0x0048)
85 u32 g_0; /* Graphic Frame 0/1 Starting Address */
86 u32 g_1;
87 u32 g_pitch; /* Graphic Line Length (Pitch) */
88 u32 g_start; /* Graphic Starting Point on Screen */
89 u32 g_size; /* Graphic Source Size */
90 u32 g_size_z; /* Graphic Destination Size (After Zooming) */
91
92/* 32 bit TV Hardware Cursor Starting Point on screen Register*/
93#define LCD_TVC_OVSA_HPXL_VLN (0x004C)
94/* 32 bit TV Hardware Cursor Size Register */
95#define LCD_TVC_HPXL_VLN (0x0050)
96 u32 hc_start; /* Hardware Cursor */
97 u32 hc_size; /* Hardware Cursor */
98
99/* 32 bit TV Total Screen Size Register*/
100#define LCD_TV_V_H_TOTAL (0x0054)
101/* 32 bit TV Screen Active Size Register*/
102#define LCD_TV_V_H_ACTIVE (0x0058)
103/* 32 bit TV Screen Horizontal Porch Register*/
104#define LCD_TV_H_PORCH (0x005C)
105/* 32 bit TV Screen Vertical Porch Register*/
106#define LCD_TV_V_PORCH (0x0060)
107 u32 screen_size; /* Screen Total Size */
108 u32 screen_active; /* Screen Active Size */
109 u32 screen_h_porch; /* Screen Horizontal Porch */
110 u32 screen_v_porch; /* Screen Vertical Porch */
111
112/* 32 bit TV Screen Blank Color Register*/
113#define LCD_TV_BLANKCOLOR (0x0064)
114/* 32 bit TV Hardware Cursor Color1 Register*/
115#define LCD_TV_ALPHA_COLOR1 (0x0068)
116/* 32 bit TV Hardware Cursor Color2 Register*/
117#define LCD_TV_ALPHA_COLOR2 (0x006C)
118 u32 blank_color; /* Screen Blank Color */
119 u32 hc_Alpha_color1; /* Hardware Cursor Color1 */
120 u32 hc_Alpha_color2; /* Hardware Cursor Color2 */
121
122/* 32 bit TV Video Y Color Key Control*/
123#define LCD_TV_COLORKEY_Y (0x0070)
124/* 32 bit TV Video U Color Key Control*/
125#define LCD_TV_COLORKEY_U (0x0074)
126/* 32 bit TV Video V Color Key Control*/
127#define LCD_TV_COLORKEY_V (0x0078)
128 u32 v_colorkey_y; /* Video Y Color Key Control */
129 u32 v_colorkey_u; /* Video U Color Key Control */
130 u32 v_colorkey_v; /* Video V Color Key Control */
131
132/* 32 bit TV VSYNC PulsePixel Edge Control Register*/
133#define LCD_TV_SEPXLCNT (0x007C)
134 u32 vsync_ctrl; /* VSYNC PulsePixel Edge Control */
135};
136
137#define intf_ctrl(id) ((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \
138 LCD_DUMB2_CTRL) : LCD_SPU_DUMB_CTRL)
139#define dma_ctrl0(id) ((id) ? (((id) & 1) ? LCD_TV_CTRL0 : \
140 LCD_PN2_CTRL0) : LCD_SPU_DMA_CTRL0)
141#define dma_ctrl1(id) ((id) ? (((id) & 1) ? LCD_TV_CTRL1 : \
142 LCD_PN2_CTRL1) : LCD_SPU_DMA_CTRL1)
143#define dma_ctrl(ctrl1, id) (ctrl1 ? dma_ctrl1(id) : dma_ctrl0(id))
144
145/* 32 bit TV Path DMA Control 0*/
146#define LCD_TV_CTRL0 (0x0080)
147/* 32 bit TV Path DMA Control 1*/
148#define LCD_TV_CTRL1 (0x0084)
149/* 32 bit TV Path Video Contrast*/
150#define LCD_TV_CONTRAST (0x0088)
151/* 32 bit TV Path Video Saturation*/
152#define LCD_TV_SATURATION (0x008C)
153/* 32 bit TV Path Video Hue Adjust*/
154#define LCD_TV_CBSH_HUE (0x0090)
155/* 32 bit TV Path TVIF Control Register */
156#define LCD_TVIF_CTRL (0x0094)
157#define TV_VBLNK_VALID_EN (1 << 12)
158
159/* 32 bit TV Path I/O Pad Control*/
160#define LCD_TVIOPAD_CTRL (0x0098)
161/* 32 bit TV Path Cloc Divider */
162#define LCD_TCLK_DIV (0x009C)
163
164#define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
165 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
166#define intf_rbswap_ctrl(id) ((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \
167 PN2_IOPAD_CONTROL) : LCD_TOP_CTRL)
168
169/* dither configure */
170#ifdef CONFIG_CPU_PXA988
171#define LCD_DITHER_CTRL (0x01EC)
172#else
173#define LCD_DITHER_CTRL (0x00A0)
174#endif
175
176#define DITHER_TBL_INDEX_SEL(s) ((s) << 16)
177#define DITHER_MODE2(m) ((m) << 12)
178#define DITHER_MODE2_SHIFT (12)
179#define DITHER_4X8_EN2 (1 << 9)
180#define DITHER_4X8_EN2_SHIFT (9)
181#define DITHER_EN2 (1 << 8)
182#define DITHER_MODE1(m) ((m) << 4)
183#define DITHER_MODE1_SHIFT (4)
184#define DITHER_4X8_EN1 (1 << 1)
185#define DITHER_4X8_EN1_SHIFT (1)
186#define DITHER_EN1 (1)
187
188/* dither table data was fixed by video bpp of input and output*/
189#ifdef CONFIG_CPU_PXA988
190#define DITHER_TB_4X4_INDEX0 (0x6e4ca280)
191#define DITHER_TB_4X4_INDEX1 (0x5d7f91b3)
192#define DITHER_TB_4X8_INDEX0 (0xb391a280)
193#define DITHER_TB_4X8_INDEX1 (0x7f5d6e4c)
194#define DITHER_TB_4X8_INDEX2 (0x80a291b3)
195#define DITHER_TB_4X8_INDEX3 (0x4c6e5d7f)
196#define LCD_DITHER_TBL_DATA (0x01F0)
197#else
198#define DITHER_TB_4X4_INDEX0 (0x3b19f7d5)
199#define DITHER_TB_4X4_INDEX1 (0x082ac4e6)
200#define DITHER_TB_4X8_INDEX0 (0xf7d508e6)
201#define DITHER_TB_4X8_INDEX1 (0x3b194c2a)
202#define DITHER_TB_4X8_INDEX2 (0xc4e6d5f7)
203#define DITHER_TB_4X8_INDEX3 (0x082a193b)
204#define LCD_DITHER_TBL_DATA (0x00A4)
205#endif
206
207/* Video Frame 0&1 start address registers */
208#define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
209#define LCD_SPU_DMA_START_ADDR_U0 0x00C4
210#define LCD_SPU_DMA_START_ADDR_V0 0x00C8
211#define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
212#define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
213#define LCD_SPU_DMA_START_ADDR_U1 0x00D4
214#define LCD_SPU_DMA_START_ADDR_V1 0x00D8
215#define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
216
217/* YC & UV Pitch */
218#define LCD_SPU_DMA_PITCH_YC 0x00E0
219#define SPU_DMA_PITCH_C(c) ((c)<<16)
220#define SPU_DMA_PITCH_Y(y) (y)
221#define LCD_SPU_DMA_PITCH_UV 0x00E4
222#define SPU_DMA_PITCH_V(v) ((v)<<16)
223#define SPU_DMA_PITCH_U(u) (u)
224
225/* Video Starting Point on Screen Register */
226#define LCD_SPUT_DMA_OVSA_HPXL_VLN 0x00E8
227#define CFG_DMA_OVSA_VLN(y) ((y)<<16) /* 0~0xfff */
228#define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */
229
230/* Video Size Register */
231#define LCD_SPU_DMA_HPXL_VLN 0x00EC
232#define CFG_DMA_VLN(y) ((y)<<16)
233#define CFG_DMA_HPXL(x) (x)
234
235/* Video Size After zooming Register */
236#define LCD_SPU_DZM_HPXL_VLN 0x00F0
237#define CFG_DZM_VLN(y) ((y)<<16)
238#define CFG_DZM_HPXL(x) (x)
239
240/* Graphic Frame 0&1 Starting Address Register */
241#define LCD_CFG_GRA_START_ADDR0 0x00F4
242#define LCD_CFG_GRA_START_ADDR1 0x00F8
243
244/* Graphic Frame Pitch */
245#define LCD_CFG_GRA_PITCH 0x00FC
246
247/* Graphic Starting Point on Screen Register */
248#define LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
249#define CFG_GRA_OVSA_VLN(y) ((y)<<16)
250#define CFG_GRA_OVSA_HPXL(x) (x)
251
252/* Graphic Size Register */
253#define LCD_SPU_GRA_HPXL_VLN 0x0104
254#define CFG_GRA_VLN(y) ((y)<<16)
255#define CFG_GRA_HPXL(x) (x)
256
257/* Graphic Size after Zooming Register */
258#define LCD_SPU_GZM_HPXL_VLN 0x0108
259#define CFG_GZM_VLN(y) ((y)<<16)
260#define CFG_GZM_HPXL(x) (x)
261
262/* HW Cursor Starting Point on Screen Register */
263#define LCD_SPU_HWC_OVSA_HPXL_VLN 0x010C
264#define CFG_HWC_OVSA_VLN(y) ((y)<<16)
265#define CFG_HWC_OVSA_HPXL(x) (x)
266
267/* HW Cursor Size */
268#define LCD_SPU_HWC_HPXL_VLN 0x0110
269#define CFG_HWC_VLN(y) ((y)<<16)
270#define CFG_HWC_HPXL(x) (x)
271
272/* Total Screen Size Register */
273#define LCD_SPUT_V_H_TOTAL 0x0114
274#define CFG_V_TOTAL(y) ((y)<<16)
275#define CFG_H_TOTAL(x) (x)
276
277/* Total Screen Active Size Register */
278#define LCD_SPU_V_H_ACTIVE 0x0118
279#define CFG_V_ACTIVE(y) ((y)<<16)
280#define CFG_H_ACTIVE(x) (x)
281
282/* Screen H&V Porch Register */
283#define LCD_SPU_H_PORCH 0x011C
284#define CFG_H_BACK_PORCH(b) ((b)<<16)
285#define CFG_H_FRONT_PORCH(f) (f)
286#define LCD_SPU_V_PORCH 0x0120
287#define CFG_V_BACK_PORCH(b) ((b)<<16)
288#define CFG_V_FRONT_PORCH(f) (f)
289
290/* Screen Blank Color Register */
291#define LCD_SPU_BLANKCOLOR 0x0124
292#define CFG_BLANKCOLOR_MASK 0x00FFFFFF
293#define CFG_BLANKCOLOR_R_MASK 0x000000FF
294#define CFG_BLANKCOLOR_G_MASK 0x0000FF00
295#define CFG_BLANKCOLOR_B_MASK 0x00FF0000
296
297/* HW Cursor Color 1&2 Register */
298#define LCD_SPU_ALPHA_COLOR1 0x0128
299#define CFG_HWC_COLOR1 0x00FFFFFF
300#define CFG_HWC_COLOR1_R(red) ((red)<<16)
301#define CFG_HWC_COLOR1_G(green) ((green)<<8)
302#define CFG_HWC_COLOR1_B(blue) (blue)
303#define CFG_HWC_COLOR1_R_MASK 0x000000FF
304#define CFG_HWC_COLOR1_G_MASK 0x0000FF00
305#define CFG_HWC_COLOR1_B_MASK 0x00FF0000
306#define LCD_SPU_ALPHA_COLOR2 0x012C
307#define CFG_HWC_COLOR2 0x00FFFFFF
308#define CFG_HWC_COLOR2_R_MASK 0x000000FF
309#define CFG_HWC_COLOR2_G_MASK 0x0000FF00
310#define CFG_HWC_COLOR2_B_MASK 0x00FF0000
311
312/* Video YUV Color Key Control */
313#define LCD_SPU_COLORKEY_Y 0x0130
314#define CFG_CKEY_Y2(y2) ((y2)<<24)
315#define CFG_CKEY_Y2_MASK 0xFF000000
316#define CFG_CKEY_Y1(y1) ((y1)<<16)
317#define CFG_CKEY_Y1_MASK 0x00FF0000
318#define CFG_CKEY_Y(y) ((y)<<8)
319#define CFG_CKEY_Y_MASK 0x0000FF00
320#define CFG_ALPHA_Y(y) (y)
321#define CFG_ALPHA_Y_MASK 0x000000FF
322#define LCD_SPU_COLORKEY_U 0x0134
323#define CFG_CKEY_U2(u2) ((u2)<<24)
324#define CFG_CKEY_U2_MASK 0xFF000000
325#define CFG_CKEY_U1(u1) ((u1)<<16)
326#define CFG_CKEY_U1_MASK 0x00FF0000
327#define CFG_CKEY_U(u) ((u)<<8)
328#define CFG_CKEY_U_MASK 0x0000FF00
329#define CFG_ALPHA_U(u) (u)
330#define CFG_ALPHA_U_MASK 0x000000FF
331#define LCD_SPU_COLORKEY_V 0x0138
332#define CFG_CKEY_V2(v2) ((v2)<<24)
333#define CFG_CKEY_V2_MASK 0xFF000000
334#define CFG_CKEY_V1(v1) ((v1)<<16)
335#define CFG_CKEY_V1_MASK 0x00FF0000
336#define CFG_CKEY_V(v) ((v)<<8)
337#define CFG_CKEY_V_MASK 0x0000FF00
338#define CFG_ALPHA_V(v) (v)
339#define CFG_ALPHA_V_MASK 0x000000FF
340
341/* Graphics/Video DMA color key enable bits in LCD_TV_CTRL1 */
342#define CFG_CKEY_GRA 0x2
343#define CFG_CKEY_DMA 0x1
344
345/* Interlace mode enable bits in LCD_TV_CTRL1 */
346#define CFG_TV_INTERLACE_EN (1 << 22)
347#define CFG_TV_NIB (1 << 0)
348
349#define LCD_PN_SEPXLCNT 0x013c /* MMP2 */
350
351/* SPI Read Data Register */
352#define LCD_SPU_SPI_RXDATA 0x0140
353
354/* Smart Panel Read Data Register */
355#define LCD_SPU_ISA_RSDATA 0x0144
356#define ISA_RXDATA_16BIT_1_DATA_MASK 0x000000FF
357#define ISA_RXDATA_16BIT_2_DATA_MASK 0x0000FF00
358#define ISA_RXDATA_16BIT_3_DATA_MASK 0x00FF0000
359#define ISA_RXDATA_16BIT_4_DATA_MASK 0xFF000000
360#define ISA_RXDATA_32BIT_1_DATA_MASK 0x00FFFFFF
361
362#define LCD_SPU_DBG_ISA (0x0148) /* TTC */
363#define LCD_SPU_DMAVLD_YC (0x014C)
364#define LCD_SPU_DMAVLD_UV (0x0150)
365#define LCD_SPU_DMAVLD_UVSPU_GRAVLD (0x0154)
366
367#define LCD_READ_IOPAD (0x0148) /* MMP2*/
368#define LCD_DMAVLD_YC (0x014C)
369#define LCD_DMAVLD_UV (0x0150)
370#define LCD_TVGGRAVLD_HLEN (0x0154)
371
372/* HWC SRAM Read Data Register */
373#define LCD_SPU_HWC_RDDAT 0x0158
374
375/* Gamma Table SRAM Read Data Register */
376#define LCD_SPU_GAMMA_RDDAT 0x015c
377#define CFG_GAMMA_RDDAT_MASK 0x000000FF
378
379/* Palette Table SRAM Read Data Register */
380#define LCD_SPU_PALETTE_RDDAT 0x0160
381#define CFG_PALETTE_RDDAT_MASK 0x00FFFFFF
382
383#define LCD_SPU_DBG_DMATOP (0x0164) /* TTC */
384#define LCD_SPU_DBG_GRATOP (0x0168)
385#define LCD_SPU_DBG_TXCTRL (0x016C)
386#define LCD_SPU_DBG_SLVTOP (0x0170)
387#define LCD_SPU_DBG_MUXTOP (0x0174)
388
389#define LCD_SLV_DBG (0x0164) /* MMP2 */
390#define LCD_TVDVLD_YC (0x0168)
391#define LCD_TVDVLD_UV (0x016C)
392#define LCD_TVC_RDDAT (0x0170)
393#define LCD_TV_GAMMA_RDDAT (0x0174)
394
395/* I/O Pads Input Read Only Register */
396#define LCD_SPU_IOPAD_IN 0x0178
397#define CFG_IOPAD_IN_MASK 0x0FFFFFFF
398
399#define LCD_TV_PALETTE_RDDAT (0x0178) /* MMP2 */
400
401/* Reserved Read Only Registers */
402#define LCD_CFG_RDREG5F 0x017C
403#define IRE_FRAME_CNT_MASK 0x000000C0
404#define IPE_FRAME_CNT_MASK 0x00000030
405#define GRA_FRAME_CNT_MASK 0x0000000C /* Graphic */
406#define DMA_FRAME_CNT_MASK 0x00000003 /* Video */
407
408#define LCD_FRAME_CNT (0x017C) /* MMP2 */
409
410/* SPI Control Register. */
411#define LCD_SPU_SPI_CTRL 0x0180
412#define CFG_SCLKCNT(div) ((div)<<24) /* 0xFF~0x2 */
413#define CFG_SCLKCNT_MASK 0xFF000000
414#define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */
415#define CFG_RXBITS_MASK 0x00FF0000
416#define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */
417#define CFG_TXBITS_MASK 0x0000FF00
418#define CFG_CLKINV(clk) ((clk)<<7)
419#define CFG_CLKINV_MASK 0x00000080
420#define CFG_KEEPXFER(transfer) ((transfer)<<6)
421#define CFG_KEEPXFER_MASK 0x00000040
422#define CFG_RXBITSTO0(rx) ((rx)<<5)
423#define CFG_RXBITSTO0_MASK 0x00000020
424#define CFG_TXBITSTO0(tx) ((tx)<<4)
425#define CFG_TXBITSTO0_MASK 0x00000010
426#define CFG_SPI_ENA(spi) ((spi)<<3)
427#define CFG_SPI_ENA_MASK 0x00000008
428#define CFG_SPI_SEL(spi) ((spi)<<2)
429#define CFG_SPI_SEL_MASK 0x00000004
430#define CFG_SPI_3W4WB(wire) ((wire)<<1)
431#define CFG_SPI_3W4WB_MASK 0x00000002
432#define CFG_SPI_START(start) (start)
433#define CFG_SPI_START_MASK 0x00000001
434
435/* SPI Tx Data Register */
436#define LCD_SPU_SPI_TXDATA 0x0184
437
438/*
439 1. Smart Pannel 8-bit Bus Control Register.
440 2. AHB Slave Path Data Port Register
441*/
442#define LCD_SPU_SMPN_CTRL 0x0188
443
444/* DMA Control 0 Register */
445#define LCD_SPU_DMA_CTRL0 0x0190
446#define CFG_NOBLENDING(nb) ((nb)<<31)
447#define CFG_NOBLENDING_MASK 0x80000000
448#define CFG_GAMMA_ENA(gn) ((gn)<<30)
449#define CFG_GAMMA_ENA_MASK 0x40000000
450#define CFG_CBSH_ENA(cn) ((cn)<<29)
451#define CFG_CBSH_ENA_MASK 0x20000000
452#define CFG_PALETTE_ENA(pn) ((pn)<<28)
453#define CFG_PALETTE_ENA_MASK 0x10000000
454#define CFG_ARBFAST_ENA(an) ((an)<<27)
455#define CFG_ARBFAST_ENA_MASK 0x08000000
456#define CFG_HWC_1BITMOD(mode) ((mode)<<26)
457#define CFG_HWC_1BITMOD_MASK 0x04000000
458#define CFG_HWC_1BITENA(mn) ((mn)<<25)
459#define CFG_HWC_1BITENA_MASK 0x02000000
460#define CFG_HWC_ENA(cn) ((cn)<<24)
461#define CFG_HWC_ENA_MASK 0x01000000
462#define CFG_DMAFORMAT(dmaformat) ((dmaformat)<<20)
463#define CFG_DMAFORMAT_MASK 0x00F00000
464#define CFG_GRAFORMAT(graformat) ((graformat)<<16)
465#define CFG_GRAFORMAT_MASK 0x000F0000
466/* for graphic part */
467#define CFG_GRA_FTOGGLE(toggle) ((toggle)<<15)
468#define CFG_GRA_FTOGGLE_MASK 0x00008000
469#define CFG_GRA_HSMOOTH(smooth) ((smooth)<<14)
470#define CFG_GRA_HSMOOTH_MASK 0x00004000
471#define CFG_GRA_TSTMODE(test) ((test)<<13)
472#define CFG_GRA_TSTMODE_MASK 0x00002000
473#define CFG_GRA_SWAPRB(swap) ((swap)<<12)
474#define CFG_GRA_SWAPRB_MASK 0x00001000
475#define CFG_GRA_SWAPUV(swap) ((swap)<<11)
476#define CFG_GRA_SWAPUV_MASK 0x00000800
477#define CFG_GRA_SWAPYU(swap) ((swap)<<10)
478#define CFG_GRA_SWAPYU_MASK 0x00000400
479#define CFG_GRA_SWAP_MASK 0x00001C00
480#define CFG_YUV2RGB_GRA(cvrt) ((cvrt)<<9)
481#define CFG_YUV2RGB_GRA_MASK 0x00000200
482#define CFG_GRA_ENA(gra) ((gra)<<8)
483#define CFG_GRA_ENA_MASK 0x00000100
484#define dma0_gfx_masks (CFG_GRAFORMAT_MASK | CFG_GRA_FTOGGLE_MASK | \
485 CFG_GRA_HSMOOTH_MASK | CFG_GRA_TSTMODE_MASK | CFG_GRA_SWAP_MASK | \
486 CFG_YUV2RGB_GRA_MASK | CFG_GRA_ENA_MASK)
487/* for video part */
488#define CFG_DMA_FTOGGLE(toggle) ((toggle)<<7)
489#define CFG_DMA_FTOGGLE_MASK 0x00000080
490#define CFG_DMA_HSMOOTH(smooth) ((smooth)<<6)
491#define CFG_DMA_HSMOOTH_MASK 0x00000040
492#define CFG_DMA_TSTMODE(test) ((test)<<5)
493#define CFG_DMA_TSTMODE_MASK 0x00000020
494#define CFG_DMA_SWAPRB(swap) ((swap)<<4)
495#define CFG_DMA_SWAPRB_MASK 0x00000010
496#define CFG_DMA_SWAPUV(swap) ((swap)<<3)
497#define CFG_DMA_SWAPUV_MASK 0x00000008
498#define CFG_DMA_SWAPYU(swap) ((swap)<<2)
499#define CFG_DMA_SWAPYU_MASK 0x00000004
500#define CFG_DMA_SWAP_MASK 0x0000001C
501#define CFG_YUV2RGB_DMA(cvrt) ((cvrt)<<1)
502#define CFG_YUV2RGB_DMA_MASK 0x00000002
503#define CFG_DMA_ENA(video) (video)
504#define CFG_DMA_ENA_MASK 0x00000001
505#define dma0_vid_masks (CFG_DMAFORMAT_MASK | CFG_DMA_FTOGGLE_MASK | \
506 CFG_DMA_HSMOOTH_MASK | CFG_DMA_TSTMODE_MASK | CFG_DMA_SWAP_MASK | \
507 CFG_YUV2RGB_DMA_MASK | CFG_DMA_ENA_MASK)
508#define dma_palette(val) ((val ? 1 : 0) << 28)
509#define dma_fmt(vid, val) ((val & 0xf) << ((vid) ? 20 : 16))
510#define dma_swaprb(vid, val) ((val ? 1 : 0) << ((vid) ? 4 : 12))
511#define dma_swapuv(vid, val) ((val ? 1 : 0) << ((vid) ? 3 : 11))
512#define dma_swapyuv(vid, val) ((val ? 1 : 0) << ((vid) ? 2 : 10))
513#define dma_csc(vid, val) ((val ? 1 : 0) << ((vid) ? 1 : 9))
514#define dma_hsmooth(vid, val) ((val ? 1 : 0) << ((vid) ? 6 : 14))
515#define dma_mask(vid) (dma_palette(1) | dma_fmt(vid, 0xf) | dma_csc(vid, 1) \
516 | dma_swaprb(vid, 1) | dma_swapuv(vid, 1) | dma_swapyuv(vid, 1))
517
518/* DMA Control 1 Register */
519#define LCD_SPU_DMA_CTRL1 0x0194
520#define CFG_FRAME_TRIG(trig) ((trig)<<31)
521#define CFG_FRAME_TRIG_MASK 0x80000000
522#define CFG_VSYNC_TRIG(trig) ((trig)<<28)
523#define CFG_VSYNC_TRIG_MASK 0x70000000
524#define CFG_VSYNC_INV(inv) ((inv)<<27)
525#define CFG_VSYNC_INV_MASK 0x08000000
526#define CFG_COLOR_KEY_MODE(cmode) ((cmode)<<24)
527#define CFG_COLOR_KEY_MASK 0x07000000
528#define CFG_CARRY(carry) ((carry)<<23)
529#define CFG_CARRY_MASK 0x00800000
530#define CFG_LNBUF_ENA(lnbuf) ((lnbuf)<<22)
531#define CFG_LNBUF_ENA_MASK 0x00400000
532#define CFG_GATED_ENA(gated) ((gated)<<21)
533#define CFG_GATED_ENA_MASK 0x00200000
534#define CFG_PWRDN_ENA(power) ((power)<<20)
535#define CFG_PWRDN_ENA_MASK 0x00100000
536#define CFG_DSCALE(dscale) ((dscale)<<18)
537#define CFG_DSCALE_MASK 0x000C0000
538#define CFG_ALPHA_MODE(amode) ((amode)<<16)
539#define CFG_ALPHA_MODE_MASK 0x00030000
540#define CFG_ALPHA(alpha) ((alpha)<<8)
541#define CFG_ALPHA_MASK 0x0000FF00
542#define CFG_PXLCMD(pxlcmd) (pxlcmd)
543#define CFG_PXLCMD_MASK 0x000000FF
544
545/* SRAM Control Register */
546#define LCD_SPU_SRAM_CTRL 0x0198
547#define CFG_SRAM_INIT_WR_RD(mode) ((mode)<<14)
548#define CFG_SRAM_INIT_WR_RD_MASK 0x0000C000
549#define CFG_SRAM_ADDR_LCDID(id) ((id)<<8)
550#define CFG_SRAM_ADDR_LCDID_MASK 0x00000F00
551#define CFG_SRAM_ADDR(addr) (addr)
552#define CFG_SRAM_ADDR_MASK 0x000000FF
553
554/* SRAM Write Data Register */
555#define LCD_SPU_SRAM_WRDAT 0x019C
556
557/* SRAM RTC/WTC Control Register */
558#define LCD_SPU_SRAM_PARA0 0x01A0
559
560/* SRAM Power Down Control Register */
561#define LCD_SPU_SRAM_PARA1 0x01A4
562#define CFG_CSB_256x32(hwc) ((hwc)<<15) /* HWC */
563#define CFG_CSB_256x32_MASK 0x00008000
564#define CFG_CSB_256x24(palette) ((palette)<<14) /* Palette */
565#define CFG_CSB_256x24_MASK 0x00004000
566#define CFG_CSB_256x8(gamma) ((gamma)<<13) /* Gamma */
567#define CFG_CSB_256x8_MASK 0x00002000
568#define CFG_PDWN256x32(pdwn) ((pdwn)<<7) /* HWC */
569#define CFG_PDWN256x32_MASK 0x00000080
570#define CFG_PDWN256x24(pdwn) ((pdwn)<<6) /* Palette */
571#define CFG_PDWN256x24_MASK 0x00000040
572#define CFG_PDWN256x8(pdwn) ((pdwn)<<5) /* Gamma */
573#define CFG_PDWN256x8_MASK 0x00000020
574#define CFG_PDWN32x32(pdwn) ((pdwn)<<3)
575#define CFG_PDWN32x32_MASK 0x00000008
576#define CFG_PDWN16x66(pdwn) ((pdwn)<<2)
577#define CFG_PDWN16x66_MASK 0x00000004
578#define CFG_PDWN32x66(pdwn) ((pdwn)<<1)
579#define CFG_PDWN32x66_MASK 0x00000002
580#define CFG_PDWN64x66(pdwn) (pdwn)
581#define CFG_PDWN64x66_MASK 0x00000001
582
583/* Smart or Dumb Panel Clock Divider */
584#define LCD_CFG_SCLK_DIV 0x01A8
585#define SCLK_SRC_SEL(src) ((src)<<31)
586#define SCLK_SRC_SEL_MASK 0x80000000
587#define SCLK_DISABLE (1<<28)
588#define CLK_FRACDIV(frac) ((frac)<<16)
589#define CLK_FRACDIV_MASK 0x0FFF0000
590#define DSI1_BITCLK_DIV(div) (div<<8)
591#define DSI1_BITCLK_DIV_MASK 0x00000F00
592#define CLK_INT_DIV(div) (div)
593#define CLK_INT_DIV_MASK 0x000000FF
594
595/* Video Contrast Register */
596#define LCD_SPU_CONTRAST 0x01AC
597#define CFG_BRIGHTNESS(bright) ((bright)<<16)
598#define CFG_BRIGHTNESS_MASK 0xFFFF0000
599#define CFG_CONTRAST(contrast) (contrast)
600#define CFG_CONTRAST_MASK 0x0000FFFF
601
602/* Video Saturation Register */
603#define LCD_SPU_SATURATION 0x01B0
604#define CFG_C_MULTS(mult) ((mult)<<16)
605#define CFG_C_MULTS_MASK 0xFFFF0000
606#define CFG_SATURATION(sat) (sat)
607#define CFG_SATURATION_MASK 0x0000FFFF
608
609/* Video Hue Adjust Register */
610#define LCD_SPU_CBSH_HUE 0x01B4
611#define CFG_SIN0(sin0) ((sin0)<<16)
612#define CFG_SIN0_MASK 0xFFFF0000
613#define CFG_COS0(con0) (con0)
614#define CFG_COS0_MASK 0x0000FFFF
615
616/* Dump LCD Panel Control Register */
617#define LCD_SPU_DUMB_CTRL 0x01B8
618#define CFG_DUMBMODE(mode) ((mode)<<28)
619#define CFG_DUMBMODE_MASK 0xF0000000
620#define CFG_INTFRBSWAP(mode) ((mode)<<24)
621#define CFG_INTFRBSWAP_MASK 0x0F000000
622#define CFG_LCDGPIO_O(data) ((data)<<20)
623#define CFG_LCDGPIO_O_MASK 0x0FF00000
624#define CFG_LCDGPIO_ENA(gpio) ((gpio)<<12)
625#define CFG_LCDGPIO_ENA_MASK 0x000FF000
626#define CFG_BIAS_OUT(bias) ((bias)<<8)
627#define CFG_BIAS_OUT_MASK 0x00000100
628#define CFG_REVERSE_RGB(RGB) ((RGB)<<7)
629#define CFG_REVERSE_RGB_MASK 0x00000080
630#define CFG_INV_COMPBLANK(blank) ((blank)<<6)
631#define CFG_INV_COMPBLANK_MASK 0x00000040
632#define CFG_INV_COMPSYNC(sync) ((sync)<<5)
633#define CFG_INV_COMPSYNC_MASK 0x00000020
634#define CFG_INV_HENA(hena) ((hena)<<4)
635#define CFG_INV_HENA_MASK 0x00000010
636#define CFG_INV_VSYNC(vsync) ((vsync)<<3)
637#define CFG_INV_VSYNC_MASK 0x00000008
638#define CFG_INV_HSYNC(hsync) ((hsync)<<2)
639#define CFG_INV_HSYNC_MASK 0x00000004
640#define CFG_INV_PCLK(pclk) ((pclk)<<1)
641#define CFG_INV_PCLK_MASK 0x00000002
642#define CFG_DUMB_ENA(dumb) (dumb)
643#define CFG_DUMB_ENA_MASK 0x00000001
644
645/* LCD I/O Pads Control Register */
646#define SPU_IOPAD_CONTROL 0x01BC
647#define CFG_GRA_VM_ENA(vm) ((vm)<<15)
648#define CFG_GRA_VM_ENA_MASK 0x00008000
649#define CFG_DMA_VM_ENA(vm) ((vm)<<13)
650#define CFG_DMA_VM_ENA_MASK 0x00002000
651#define CFG_CMD_VM_ENA(vm) ((vm)<<12)
652#define CFG_CMD_VM_ENA_MASK 0x00001000
653#define CFG_CSC(csc) ((csc)<<8)
654#define CFG_CSC_MASK 0x00000300
655#define CFG_BOUNDARY(size) ((size)<<5)
656#define CFG_BOUNDARY_MASK 0x00000020
657#define CFG_BURST(len) ((len)<<4)
658#define CFG_BURST_MASK 0x00000010
659#define CFG_IOPADMODE(iopad) (iopad)
660#define CFG_IOPADMODE_MASK 0x0000000F
661
662/* LCD Interrupt Control Register */
663#define SPU_IRQ_ENA 0x01C0
664#define DMA_FRAME_IRQ0_ENA(irq) ((irq)<<31)
665#define DMA_FRAME_IRQ0_ENA_MASK 0x80000000
666#define DMA_FRAME_IRQ1_ENA(irq) ((irq)<<30)
667#define DMA_FRAME_IRQ1_ENA_MASK 0x40000000
668#define DMA_FF_UNDERFLOW_ENA(ff) ((ff)<<29)
669#define DMA_FF_UNDERFLOW_ENA_MASK 0x20000000
670#define AXI_BUS_ERROR_IRQ_ENA(irq) ((irq)<<28)
671#define AXI_BUS_ERROR_IRQ_ENA_MASK 0x10000000
672#define GRA_FRAME_IRQ0_ENA(irq) ((irq)<<27)
673#define GRA_FRAME_IRQ0_ENA_MASK 0x08000000
674#define GRA_FRAME_IRQ1_ENA(irq) ((irq)<<26)
675#define GRA_FRAME_IRQ1_ENA_MASK 0x04000000
676#define GRA_FF_UNDERFLOW_ENA(ff) ((ff)<<25)
677#define GRA_FF_UNDERFLOW_ENA_MASK 0x02000000
678#define VSYNC_IRQ_ENA(vsync_irq) ((vsync_irq)<<23)
679#define VSYNC_IRQ_ENA_MASK 0x00800000
680#define DUMB_FRAMEDONE_ENA(fdone) ((fdone)<<22)
681#define DUMB_FRAMEDONE_ENA_MASK 0x00400000
682#define TWC_FRAMEDONE_ENA(fdone) ((fdone)<<21)
683#define TWC_FRAMEDONE_ENA_MASK 0x00200000
684#define HWC_FRAMEDONE_ENA(fdone) ((fdone)<<20)
685#define HWC_FRAMEDONE_ENA_MASK 0x00100000
686#define SLV_IRQ_ENA(irq) ((irq)<<19)
687#define SLV_IRQ_ENA_MASK 0x00080000
688#define SPI_IRQ_ENA(irq) ((irq)<<18)
689#define SPI_IRQ_ENA_MASK 0x00040000
690#define PWRDN_IRQ_ENA(irq) ((irq)<<17)
691#define PWRDN_IRQ_ENA_MASK 0x00020000
692#define AXI_LATENCY_TOO_LONG_IRQ_ENA(irq) ((irq)<<16)
693#define AXI_LATENCY_TOO_LONG_IRQ_ENA_MASK 0x00010000
694#define CLEAN_SPU_IRQ_ISR(irq) (irq)
695#define CLEAN_SPU_IRQ_ISR_MASK 0x0000FFFF
696#define TV_DMA_FRAME_IRQ0_ENA(irq) ((irq)<<15)
697#define TV_DMA_FRAME_IRQ0_ENA_MASK 0x00008000
698#define TV_DMA_FRAME_IRQ1_ENA(irq) ((irq)<<14)
699#define TV_DMA_FRAME_IRQ1_ENA_MASK 0x00004000
700#define TV_DMA_FF_UNDERFLOW_ENA(unerrun) ((unerrun)<<13)
701#define TV_DMA_FF_UNDERFLOW_ENA_MASK 0x00002000
702#define TVSYNC_IRQ_ENA(irq) ((irq)<<12)
703#define TVSYNC_IRQ_ENA_MASK 0x00001000
704#define TV_FRAME_IRQ0_ENA(irq) ((irq)<<11)
705#define TV_FRAME_IRQ0_ENA_MASK 0x00000800
706#define TV_FRAME_IRQ1_ENA(irq) ((irq)<<10)
707#define TV_FRAME_IRQ1_ENA_MASK 0x00000400
708#define TV_GRA_FF_UNDERFLOW_ENA(unerrun) ((unerrun)<<9)
709#define TV_GRA_FF_UNDERFLOW_ENA_MASK 0x00000200
710#define TV_FRAMEDONE_ENA(irq) ((irq)<<8)
711#define TV_FRAMEDONE_ENA_MASK 0x00000100
712
713/* FIXME - JUST GUESS */
714#define PN2_DMA_FRAME_IRQ0_ENA(irq) ((irq)<<7)
715#define PN2_DMA_FRAME_IRQ0_ENA_MASK 0x00000080
716#define PN2_DMA_FRAME_IRQ1_ENA(irq) ((irq)<<6)
717#define PN2_DMA_FRAME_IRQ1_ENA_MASK 0x00000040
718#define PN2_DMA_FF_UNDERFLOW_ENA(ff) ((ff)<<5)
719#define PN2_DMA_FF_UNDERFLOW_ENA_MASK 0x00000020
720#define PN2_GRA_FRAME_IRQ0_ENA(irq) ((irq)<<3)
721#define PN2_GRA_FRAME_IRQ0_ENA_MASK 0x00000008
722#define PN2_GRA_FRAME_IRQ1_ENA(irq) ((irq)<<2)
723#define PN2_GRA_FRAME_IRQ1_ENA_MASK 0x04000004
724#define PN2_GRA_FF_UNDERFLOW_ENA(ff) ((ff)<<1)
725#define PN2_GRA_FF_UNDERFLOW_ENA_MASK 0x00000002
726#define PN2_VSYNC_IRQ_ENA(irq) ((irq)<<0)
727#define PN2_SYNC_IRQ_ENA_MASK 0x00000001
728
729#define gf0_imask(id) ((id) ? (((id) & 1) ? TV_FRAME_IRQ0_ENA_MASK \
730 : PN2_GRA_FRAME_IRQ0_ENA_MASK) : GRA_FRAME_IRQ0_ENA_MASK)
731#define gf1_imask(id) ((id) ? (((id) & 1) ? TV_FRAME_IRQ1_ENA_MASK \
732 : PN2_GRA_FRAME_IRQ1_ENA_MASK) : GRA_FRAME_IRQ1_ENA_MASK)
733#define vsync_imask(id) ((id) ? (((id) & 1) ? TVSYNC_IRQ_ENA_MASK \
734 : PN2_SYNC_IRQ_ENA_MASK) : VSYNC_IRQ_ENA_MASK)
735#define vsync_imasks (vsync_imask(0) | vsync_imask(1))
736
737#define display_done_imask(id) ((id) ? (((id) & 1) ? TV_FRAMEDONE_ENA_MASK\
738 : (PN2_DMA_FRAME_IRQ0_ENA_MASK | PN2_DMA_FRAME_IRQ1_ENA_MASK))\
739 : DUMB_FRAMEDONE_ENA_MASK)
740
741#define display_done_imasks (display_done_imask(0) | display_done_imask(1))
742
743#define vf0_imask(id) ((id) ? (((id) & 1) ? TV_DMA_FRAME_IRQ0_ENA_MASK \
744 : PN2_DMA_FRAME_IRQ0_ENA_MASK) : DMA_FRAME_IRQ0_ENA_MASK)
745#define vf1_imask(id) ((id) ? (((id) & 1) ? TV_DMA_FRAME_IRQ1_ENA_MASK \
746 : PN2_DMA_FRAME_IRQ1_ENA_MASK) : DMA_FRAME_IRQ1_ENA_MASK)
747
748#define gfx_imasks (gf0_imask(0) | gf1_imask(0) | gf0_imask(1) | \
749 gf1_imask(1))
750#define vid_imasks (vf0_imask(0) | vf1_imask(0) | vf0_imask(1) | \
751 vf1_imask(1))
752#define vid_imask(id) (display_done_imask(id))
753
754#define pn1_imasks (gf0_imask(0) | gf1_imask(0) | vsync_imask(0) | \
755 display_done_imask(0) | vf0_imask(0) | vf1_imask(0))
756#define tv_imasks (gf0_imask(1) | gf1_imask(1) | vsync_imask(1) | \
757 display_done_imask(1) | vf0_imask(1) | vf1_imask(1))
758#define path_imasks(id) ((id) ? (tv_imasks) : (pn1_imasks))
759
760/* error indications */
761#define vid_udflow_imask(id) ((id) ? (((id) & 1) ? \
762 (TV_DMA_FF_UNDERFLOW_ENA_MASK) : (PN2_DMA_FF_UNDERFLOW_ENA_MASK)) : \
763 (DMA_FF_UNDERFLOW_ENA_MASK))
764#define gfx_udflow_imask(id) ((id) ? (((id) & 1) ? \
765 (TV_GRA_FF_UNDERFLOW_ENA_MASK) : (PN2_GRA_FF_UNDERFLOW_ENA_MASK)) : \
766 (GRA_FF_UNDERFLOW_ENA_MASK))
767
768#define err_imask(id) (vid_udflow_imask(id) | gfx_udflow_imask(id) | \
769 AXI_BUS_ERROR_IRQ_ENA_MASK | AXI_LATENCY_TOO_LONG_IRQ_ENA_MASK)
770#define err_imasks (err_imask(0) | err_imask(1) | err_imask(2))
771/* LCD Interrupt Status Register */
772#define SPU_IRQ_ISR 0x01C4
773#define DMA_FRAME_IRQ0(irq) ((irq)<<31)
774#define DMA_FRAME_IRQ0_MASK 0x80000000
775#define DMA_FRAME_IRQ1(irq) ((irq)<<30)
776#define DMA_FRAME_IRQ1_MASK 0x40000000
777#define DMA_FF_UNDERFLOW(ff) ((ff)<<29)
778#define DMA_FF_UNDERFLOW_MASK 0x20000000
779#define AXI_BUS_ERROR_IRQ(irq) ((irq)<<28)
780#define AXI_BUS_ERROR_IRQ_MASK 0x10000000
781#define GRA_FRAME_IRQ0(irq) ((irq)<<27)
782#define GRA_FRAME_IRQ0_MASK 0x08000000
783#define GRA_FRAME_IRQ1(irq) ((irq)<<26)
784#define GRA_FRAME_IRQ1_MASK 0x04000000
785#define GRA_FF_UNDERFLOW(ff) ((ff)<<25)
786#define GRA_FF_UNDERFLOW_MASK 0x02000000
787#define VSYNC_IRQ(vsync_irq) ((vsync_irq)<<23)
788#define VSYNC_IRQ_MASK 0x00800000
789#define DUMB_FRAMEDONE(fdone) ((fdone)<<22)
790#define DUMB_FRAMEDONE_MASK 0x00400000
791#define TWC_FRAMEDONE(fdone) ((fdone)<<21)
792#define TWC_FRAMEDONE_MASK 0x00200000
793#define HWC_FRAMEDONE(fdone) ((fdone)<<20)
794#define HWC_FRAMEDONE_MASK 0x00100000
795#define SLV_IRQ(irq) ((irq)<<19)
796#define SLV_IRQ_MASK 0x00080000
797#define SPI_IRQ(irq) ((irq)<<18)
798#define SPI_IRQ_MASK 0x00040000
799#define PWRDN_IRQ(irq) ((irq)<<17)
800#define PWRDN_IRQ_MASK 0x00020000
801#define AXI_LATENCY_TOO_LONGR_IRQ(irq) ((irq)<<16)
802#define AXI_LATENCY_TOO_LONGR_IRQ_MASK 0x00010000
803#define TV_DMA_FRAME_IRQ0(irq) ((irq)<<15)
804#define TV_DMA_FRAME_IRQ0_MASK 0x00008000
805#define TV_DMA_FRAME_IRQ1(irq) ((irq)<<14)
806#define TV_DMA_FRAME_IRQ1_MASK 0x00004000
807#define TV_DMA_FF_UNDERFLOW(unerrun) ((unerrun)<<13)
808#define TV_DMA_FF_UNDERFLOW_MASK 0x00002000
809#define TVSYNC_IRQ(irq) ((irq)<<12)
810#define TVSYNC_IRQ_MASK 0x00001000
811#define TV_FRAME_IRQ0(irq) ((irq)<<11)
812#define TV_FRAME_IRQ0_MASK 0x00000800
813#define TV_FRAME_IRQ1(irq) ((irq)<<10)
814#define TV_FRAME_IRQ1_MASK 0x00000400
815#define TV_GRA_FF_UNDERFLOW(unerrun) ((unerrun)<<9)
816#define TV_GRA_FF_UNDERFLOW_MASK 0x00000200
817#define PN2_DMA_FRAME_IRQ0(irq) ((irq)<<7)
818#define PN2_DMA_FRAME_IRQ0_MASK 0x00000080
819#define PN2_DMA_FRAME_IRQ1(irq) ((irq)<<6)
820#define PN2_DMA_FRAME_IRQ1_MASK 0x00000040
821#define PN2_DMA_FF_UNDERFLOW(ff) ((ff)<<5)
822#define PN2_DMA_FF_UNDERFLOW_MASK 0x00000020
823#define PN2_GRA_FRAME_IRQ0(irq) ((irq)<<3)
824#define PN2_GRA_FRAME_IRQ0_MASK 0x00000008
825#define PN2_GRA_FRAME_IRQ1(irq) ((irq)<<2)
826#define PN2_GRA_FRAME_IRQ1_MASK 0x04000004
827#define PN2_GRA_FF_UNDERFLOW(ff) ((ff)<<1)
828#define PN2_GRA_FF_UNDERFLOW_MASK 0x00000002
829#define PN2_VSYNC_IRQ(irq) ((irq)<<0)
830#define PN2_SYNC_IRQ_MASK 0x00000001
831
832/* LCD FIFO Depth register */
833#define LCD_FIFO_DEPTH 0x01c8
834#define VIDEO_FIFO(fi) ((fi) << 0)
835#define VIDEO_FIFO_MASK 0x00000003
836#define GRAPHIC_FIFO(fi) ((fi) << 2)
837#define GRAPHIC_FIFO_MASK 0x0000000c
838
839/* read-only */
840#define DMA_FRAME_IRQ0_LEVEL_MASK 0x00008000
841#define DMA_FRAME_IRQ1_LEVEL_MASK 0x00004000
842#define DMA_FRAME_CNT_ISR_MASK 0x00003000
843#define GRA_FRAME_IRQ0_LEVEL_MASK 0x00000800
844#define GRA_FRAME_IRQ1_LEVEL_MASK 0x00000400
845#define GRA_FRAME_CNT_ISR_MASK 0x00000300
846#define VSYNC_IRQ_LEVEL_MASK 0x00000080
847#define DUMB_FRAMEDONE_LEVEL_MASK 0x00000040
848#define TWC_FRAMEDONE_LEVEL_MASK 0x00000020
849#define HWC_FRAMEDONE_LEVEL_MASK 0x00000010
850#define SLV_FF_EMPTY_MASK 0x00000008
851#define DMA_FF_ALLEMPTY_MASK 0x00000004
852#define GRA_FF_ALLEMPTY_MASK 0x00000002
853#define PWRDN_IRQ_LEVEL_MASK 0x00000001
854
855/* 32 bit LCD Interrupt Reset Status*/
856#define SPU_IRQ_RSR (0x01C8)
857/* 32 bit Panel Path Graphic Partial Display Horizontal Control Register*/
858#define LCD_GRA_CUTHPXL (0x01CC)
859/* 32 bit Panel Path Graphic Partial Display Vertical Control Register*/
860#define LCD_GRA_CUTVLN (0x01D0)
861/* 32 bit TV Path Graphic Partial Display Horizontal Control Register*/
862#define LCD_TVG_CUTHPXL (0x01D4)
863/* 32 bit TV Path Graphic Partial Display Vertical Control Register*/
864#define LCD_TVG_CUTVLN (0x01D8)
865/* 32 bit LCD Global Control Register*/
866#define LCD_TOP_CTRL (0x01DC)
867/* 32 bit LCD SQU Line Buffer Control Register 1*/
868#define LCD_SQULN1_CTRL (0x01E0)
869/* 32 bit LCD SQU Line Buffer Control Register 2*/
870#define LCD_SQULN2_CTRL (0x01E4)
871#define squln_ctrl(id) ((id) ? (((id) & 1) ? LCD_SQULN2_CTRL : \
872 LCD_PN2_SQULN1_CTRL) : LCD_SQULN1_CTRL)
873
874/* 32 bit LCD Mixed Overlay Control Register */
875#define LCD_AFA_ALL2ONE (0x01E8)
876
877#define LCD_PN2_SCLK_DIV (0x01EC)
878#define LCD_PN2_TCLK_DIV (0x01F0)
879#define LCD_LVDS_SCLK_DIV_WR (0x01F4)
880#define LCD_LVDS_SCLK_DIV_RD (0x01FC)
881#define PN2_LCD_DMA_START_ADDR_Y0 (0x0200)
882#define PN2_LCD_DMA_START_ADDR_U0 (0x0204)
883#define PN2_LCD_DMA_START_ADDR_V0 (0x0208)
884#define PN2_LCD_DMA_START_ADDR_C0 (0x020C)
885#define PN2_LCD_DMA_START_ADDR_Y1 (0x0210)
886#define PN2_LCD_DMA_START_ADDR_U1 (0x0214)
887#define PN2_LCD_DMA_START_ADDR_V1 (0x0218)
888#define PN2_LCD_DMA_START_ADDR_C1 (0x021C)
889#define PN2_LCD_DMA_PITCH_YC (0x0220)
890#define PN2_LCD_DMA_PITCH_UV (0x0224)
891#define PN2_LCD_DMA_OVSA_HPXL_VLN (0x0228)
892#define PN2_LCD_DMA_HPXL_VLN (0x022C)
893#define PN2_LCD_DMAZM_HPXL_VLN (0x0230)
894#define PN2_LCD_GRA_START_ADDR0 (0x0234)
895#define PN2_LCD_GRA_START_ADDR1 (0x0238)
896#define PN2_LCD_GRA_PITCH (0x023C)
897#define PN2_LCD_GRA_OVSA_HPXL_VLN (0x0240)
898#define PN2_LCD_GRA_HPXL_VLN (0x0244)
899#define PN2_LCD_GRAZM_HPXL_VLN (0x0248)
900#define PN2_LCD_HWC_OVSA_HPXL_VLN (0x024C)
901#define PN2_LCD_HWC_HPXL_VLN (0x0250)
902#define LCD_PN2_V_H_TOTAL (0x0254)
903#define LCD_PN2_V_H_ACTIVE (0x0258)
904#define LCD_PN2_H_PORCH (0x025C)
905#define LCD_PN2_V_PORCH (0x0260)
906#define LCD_PN2_BLANKCOLOR (0x0264)
907#define LCD_PN2_ALPHA_COLOR1 (0x0268)
908#define LCD_PN2_ALPHA_COLOR2 (0x026C)
909#define LCD_PN2_COLORKEY_Y (0x0270)
910#define LCD_PN2_COLORKEY_U (0x0274)
911#define LCD_PN2_COLORKEY_V (0x0278)
912#define LCD_PN2_SEPXLCNT (0x027C)
913#define LCD_TV_V_H_TOTAL_FLD (0x0280)
914#define LCD_TV_V_PORCH_FLD (0x0284)
915#define LCD_TV_SEPXLCNT_FLD (0x0288)
916
917#define LCD_2ND_ALPHA (0x0294)
918#define LCD_PN2_CONTRAST (0x0298)
919#define LCD_PN2_SATURATION (0x029c)
920#define LCD_PN2_CBSH_HUE (0x02a0)
921#define LCD_TIMING_EXT (0x02C0)
922#define LCD_PN2_LAYER_ALPHA_SEL1 (0x02c4)
923#define LCD_PN2_CTRL0 (0x02C8)
924#define TV_LAYER_ALPHA_SEL1 (0x02cc)
925#define LCD_SMPN2_CTRL (0x02D0)
926#define LCD_IO_OVERL_MAP_CTRL (0x02D4)
927#define LCD_DUMB2_CTRL (0x02d8)
928#define LCD_PN2_CTRL1 (0x02DC)
929#define PN2_IOPAD_CONTROL (0x02E0)
930#define LCD_PN2_SQULN1_CTRL (0x02E4)
931#define PN2_LCD_GRA_CUTHPXL (0x02e8)
932#define PN2_LCD_GRA_CUTVLN (0x02ec)
933#define LCD_PN2_SQULN2_CTRL (0x02F0)
934#define ALL_LAYER_ALPHA_SEL (0x02F4)
935
936/* pxa988 has different MASTER_CTRL from MMP3/MMP2 */
937#ifdef CONFIG_CPU_PXA988
938#define TIMING_MASTER_CONTROL (0x01F4)
939#define MASTER_ENH(id) (1 << ((id) + 5))
940#define MASTER_ENV(id) (1 << ((id) + 6))
941#else
942#define TIMING_MASTER_CONTROL (0x02F8)
943#define MASTER_ENH(id) (1 << (id))
944#define MASTER_ENV(id) (1 << ((id) + 4))
945#endif
946
947#define DSI_START_SEL_SHIFT(id) (((id) << 1) + 8)
948#define timing_master_config(path, dsi_id, lcd_id) \
949 (MASTER_ENH(path) | MASTER_ENV(path) | \
950 (((lcd_id) + ((dsi_id) << 1)) << DSI_START_SEL_SHIFT(path)))
951
952#define LCD_2ND_BLD_CTL (0x02Fc)
953#define LVDS_SRC_MASK (3 << 30)
954#define LVDS_SRC_SHIFT (30)
955#define LVDS_FMT_MASK (1 << 28)
956#define LVDS_FMT_SHIFT (28)
957
958#define CLK_SCLK (1 << 0)
959#define CLK_LVDS_RD (1 << 1)
960#define CLK_LVDS_WR (1 << 2)
961
962#define gra_partdisp_ctrl_hor(id) ((id) ? (((id) & 1) ? \
963 LCD_TVG_CUTHPXL : PN2_LCD_GRA_CUTHPXL) : LCD_GRA_CUTHPXL)
964#define gra_partdisp_ctrl_ver(id) ((id) ? (((id) & 1) ? \
965 LCD_TVG_CUTVLN : PN2_LCD_GRA_CUTVLN) : LCD_GRA_CUTVLN)
966
967/*
968 * defined for Configure Dumb Mode
969 * defined for Configure Dumb Mode
970 * DUMB LCD Panel bit[31:28]
971 */
972#define DUMB16_RGB565_0 0x0
973#define DUMB16_RGB565_1 0x1
974#define DUMB18_RGB666_0 0x2
975#define DUMB18_RGB666_1 0x3
976#define DUMB12_RGB444_0 0x4
977#define DUMB12_RGB444_1 0x5
978#define DUMB24_RGB888_0 0x6
979#define DUMB_BLANK 0x7
980
981/*
982 * defined for Configure I/O Pin Allocation Mode
983 * LCD LCD I/O Pads control register bit[3:0]
984 */
985#define IOPAD_DUMB24 0x0
986#define IOPAD_DUMB18SPI 0x1
987#define IOPAD_DUMB18GPIO 0x2
988#define IOPAD_DUMB16SPI 0x3
989#define IOPAD_DUMB16GPIO 0x4
990#define IOPAD_DUMB12 0x5
991#define IOPAD_SMART18SPI 0x6
992#define IOPAD_SMART16SPI 0x7
993#define IOPAD_SMART8BOTH 0x8
994#define IOPAD_DUMB18_SMART8 0x9
995#define IOPAD_DUMB16_SMART8SPI 0xa
996#define IOPAD_DUMB16_SMART8GPIO 0xb
997#define IOPAD_DUMB16_DUMB16 0xc
998#define IOPAD_SMART8_SMART8 0xc
999
1000/*
1001 *defined for indicating boundary and cycle burst length
1002 */
1003#define CFG_BOUNDARY_1KB (1<<5)
1004#define CFG_BOUNDARY_4KB (0<<5)
1005#define CFG_CYC_BURST_LEN16 (1<<4)
1006#define CFG_CYC_BURST_LEN8 (0<<4)
1007
1008/* SRAM ID */
1009#define SRAMID_GAMMA_YR 0x0
1010#define SRAMID_GAMMA_UG 0x1
1011#define SRAMID_GAMMA_VB 0x2
1012#define SRAMID_PALATTE 0x3
1013#define SRAMID_HWC 0xf
1014
1015/* SRAM INIT Read/Write */
1016#define SRAMID_INIT_READ 0x0
1017#define SRAMID_INIT_WRITE 0x2
1018#define SRAMID_INIT_DEFAULT 0x3
1019
1020/*
1021 * defined VSYNC selection mode for DMA control 1 register
1022 * DMA1 bit[30:28]
1023 */
1024#define VMODE_SMPN 0x0
1025#define VMODE_SMPNIRQ 0x1
1026#define VMODE_DUMB 0x2
1027#define VMODE_IPE 0x3
1028#define VMODE_IRE 0x4
1029
1030/*
1031 * defined Configure Alpha and Alpha mode for DMA control 1 register
1032 * DMA1 bit[15:08](alpha) / bit[17:16](alpha mode)
1033 */
1034/* ALPHA mode */
1035#define MODE_ALPHA_DMA 0x0
1036#define MODE_ALPHA_GRA 0x1
1037#define MODE_ALPHA_CFG 0x2
1038
1039/* alpha value */
1040#define ALPHA_NOGRAPHIC 0xFF /* all video, no graphic */
1041#define ALPHA_NOVIDEO 0x00 /* all graphic, no video */
1042#define ALPHA_GRAPHNVIDEO 0x0F /* Selects graphic & video */
1043
1044/*
1045 * defined Pixel Command for DMA control 1 register
1046 * DMA1 bit[07:00]
1047 */
1048#define PIXEL_CMD 0x81
1049
1050/* DSI */
1051/* DSI1 - 4 Lane Controller base */
1052#define DSI1_REGS_PHYSICAL_BASE 0xD420B800
1053/* DSI2 - 3 Lane Controller base */
1054#define DSI2_REGS_PHYSICAL_BASE 0xD420BA00
1055
1056/* DSI Controller Registers */
1057struct dsi_lcd_regs {
1058#define DSI_LCD1_CTRL_0 0x100 /* DSI Active Panel 1 Control register 0 */
1059#define DSI_LCD1_CTRL_1 0x104 /* DSI Active Panel 1 Control register 1 */
1060 u32 ctrl0;
1061 u32 ctrl1;
1062 u32 reserved1[2];
1063
1064#define DSI_LCD1_TIMING_0 0x110 /* Timing register 0 */
1065#define DSI_LCD1_TIMING_1 0x114 /* Timing register 1 */
1066#define DSI_LCD1_TIMING_2 0x118 /* Timing register 2 */
1067#define DSI_LCD1_TIMING_3 0x11C /* Timing register 3 */
1068#define DSI_LCD1_WC_0 0x120 /* Word Count register 0 */
1069#define DSI_LCD1_WC_1 0x124 /* Word Count register 1 */
1070#define DSI_LCD1_WC_2 0x128 /* Word Count register 2 */
1071 u32 timing0;
1072 u32 timing1;
1073 u32 timing2;
1074 u32 timing3;
1075 u32 wc0;
1076 u32 wc1;
1077 u32 wc2;
1078 u32 reserved2[1];
1079 u32 slot_cnt0;
1080 u32 slot_cnt1;
1081 u32 reserved3[2];
1082 u32 status_0;
1083 u32 status_1;
1084 u32 status_2;
1085 u32 status_3;
1086 u32 status_4;
1087};
1088
1089struct dsi_regs {
1090#define DSI_CTRL_0 0x000 /* DSI control register 0 */
1091#define DSI_CTRL_1 0x004 /* DSI control register 1 */
1092 u32 ctrl0;
1093 u32 ctrl1;
1094 u32 reserved1[2];
1095 u32 irq_status;
1096 u32 irq_mask;
1097 u32 reserved2[2];
1098
1099#define DSI_CPU_CMD_0 0x020 /* DSI CPU packet command register 0 */
1100#define DSI_CPU_CMD_1 0x024 /* DSU CPU Packet Command Register 1 */
1101#define DSI_CPU_CMD_3 0x02C /* DSU CPU Packet Command Register 3 */
1102#define DSI_CPU_WDAT_0 0x030 /* DSI CUP */
1103 u32 cmd0;
1104 u32 cmd1;
1105 u32 cmd2;
1106 u32 cmd3;
1107 u32 dat0;
1108 u32 status0;
1109 u32 status1;
1110 u32 status2;
1111 u32 status3;
1112 u32 status4;
1113 u32 reserved3[2];
1114
1115 u32 smt_cmd;
1116 u32 smt_ctrl0;
1117 u32 smt_ctrl1;
1118 u32 reserved4[1];
1119
1120 u32 rx0_status;
1121
1122/* Rx Packet Header - data from slave device */
1123#define DSI_RX_PKT_HDR_0 0x064
1124 u32 rx0_header;
1125 u32 rx1_status;
1126 u32 rx1_header;
1127 u32 rx_ctrl;
1128 u32 rx_ctrl1;
1129 u32 rx2_status;
1130 u32 rx2_header;
1131 u32 reserved5[1];
1132
1133 u32 phy_ctrl1;
1134#define DSI_PHY_CTRL_2 0x088 /* DSI DPHI Control Register 2 */
1135#define DSI_PHY_CTRL_3 0x08C /* DPHY Control Register 3 */
1136 u32 phy_ctrl2;
1137 u32 phy_ctrl3;
1138 u32 phy_status0;
1139 u32 phy_status1;
1140 u32 reserved6[5];
1141 u32 phy_status2;
1142
1143#define DSI_PHY_RCOMP_0 0x0B0 /* DPHY Rcomp Control Register */
1144 u32 phy_rcomp0;
1145 u32 reserved7[3];
1146#define DSI_PHY_TIME_0 0x0C0 /* DPHY Timing Control Register 0 */
1147#define DSI_PHY_TIME_1 0x0C4 /* DPHY Timing Control Register 1 */
1148#define DSI_PHY_TIME_2 0x0C8 /* DPHY Timing Control Register 2 */
1149#define DSI_PHY_TIME_3 0x0CC /* DPHY Timing Control Register 3 */
1150#define DSI_PHY_TIME_4 0x0D0 /* DPHY Timing Control Register 4 */
1151#define DSI_PHY_TIME_5 0x0D4 /* DPHY Timing Control Register 5 */
1152 u32 phy_timing0;
1153 u32 phy_timing1;
1154 u32 phy_timing2;
1155 u32 phy_timing3;
1156 u32 phy_code_0;
1157 u32 phy_code_1;
1158 u32 reserved8[2];
1159 u32 mem_ctrl;
1160 u32 tx_timer;
1161 u32 rx_timer;
1162 u32 turn_timer;
1163 u32 reserved9[4];
1164
1165#define DSI_LCD1_CTRL_0 0x100 /* DSI Active Panel 1 Control register 0 */
1166#define DSI_LCD1_CTRL_1 0x104 /* DSI Active Panel 1 Control register 1 */
1167#define DSI_LCD1_TIMING_0 0x110 /* Timing register 0 */
1168#define DSI_LCD1_TIMING_1 0x114 /* Timing register 1 */
1169#define DSI_LCD1_TIMING_2 0x118 /* Timing register 2 */
1170#define DSI_LCD1_TIMING_3 0x11C /* Timing register 3 */
1171#define DSI_LCD1_WC_0 0x120 /* Word Count register 0 */
1172#define DSI_LCD1_WC_1 0x124 /* Word Count register 1 */
1173#define DSI_LCD1_WC_2 0x128 /* Word Count register 2 */
1174 struct dsi_lcd_regs lcd1;
1175 u32 reserved10[11];
1176 struct dsi_lcd_regs lcd2;
1177};
1178
1179#define DSI_LCD2_CTRL_0 0x180 /* DSI Active Panel 2 Control register 0 */
1180#define DSI_LCD2_CTRL_1 0x184 /* DSI Active Panel 2 Control register 1 */
1181#define DSI_LCD2_TIMING_0 0x190 /* Timing register 0 */
1182#define DSI_LCD2_TIMING_1 0x194 /* Timing register 1 */
1183#define DSI_LCD2_TIMING_2 0x198 /* Timing register 2 */
1184#define DSI_LCD2_TIMING_3 0x19C /* Timing register 3 */
1185#define DSI_LCD2_WC_0 0x1A0 /* Word Count register 0 */
1186#define DSI_LCD2_WC_1 0x1A4 /* Word Count register 1 */
1187#define DSI_LCD2_WC_2 0x1A8 /* Word Count register 2 */
1188
1189/* DSI_CTRL_0 0x0000 DSI Control Register 0 */
1190#define DSI_CTRL_0_CFG_SOFT_RST (1<<31)
1191#define DSI_CTRL_0_CFG_SOFT_RST_REG (1<<30)
1192#define DSI_CTRL_0_CFG_LCD1_TX_EN (1<<8)
1193#define DSI_CTRL_0_CFG_LCD1_SLV (1<<4)
1194#define DSI_CTRL_0_CFG_LCD1_EN (1<<0)
1195
1196/* DSI_CTRL_1 0x0004 DSI Control Register 1 */
1197#define DSI_CTRL_1_CFG_EOTP (1<<8)
1198#define DSI_CTRL_1_CFG_RSVD (2<<4)
1199#define DSI_CTRL_1_CFG_LCD2_VCH_NO_MASK (3<<2)
1200#define DSI_CTRL_1_CFG_LCD2_VCH_NO_SHIFT 2
1201#define DSI_CTRL_1_CFG_LCD1_VCH_NO_MASK (3<<0)
1202#define DSI_CTRL_1_CFG_LCD1_VCH_NO_SHIFT 0
1203
1204/* DSI_LCD1_CTRL_1 0x0104 DSI Active Panel 1 Control Register 1 */
1205/* LCD 1 Vsync Reset Enable */
1206#define DSI_LCD1_CTRL_1_CFG_L1_VSYNC_RST_EN (1<<31)
1207/* LCD 1 2K Pixel Buffer Mode Enable */
1208#define DSI_LCD1_CTRL_1_CFG_L1_M2K_EN (1<<30)
1209/* Bit(s) DSI_LCD1_CTRL_1_RSRV_29_23 reserved */
1210/* Long Blanking Packet Enable */
1211#define DSI_LCD1_CTRL_1_CFG_L1_HLP_PKT_EN (1<<22)
1212/* Extra Long Blanking Packet Enable */
1213#define DSI_LCD1_CTRL_1_CFG_L1_HEX_PKT_EN (1<<21)
1214/* Front Porch Packet Enable */
1215#define DSI_LCD1_CTRL_1_CFG_L1_HFP_PKT_EN (1<<20)
1216/* hact Packet Enable */
1217#define DSI_LCD1_CTRL_1_CFG_L1_HACT_PKT_EN (1<<19)
1218/* Back Porch Packet Enable */
1219#define DSI_LCD1_CTRL_1_CFG_L1_HBP_PKT_EN (1<<18)
1220/* hse Packet Enable */
1221#define DSI_LCD1_CTRL_1_CFG_L1_HSE_PKT_EN (1<<17)
1222/* hsa Packet Enable */
1223#define DSI_LCD1_CTRL_1_CFG_L1_HSA_PKT_EN (1<<16)
1224/* All Item Enable after Pixel Data */
1225#define DSI_LCD1_CTRL_1_CFG_L1_ALL_SLOT_EN (1<<15)
1226/* Extra Long Packet Enable after Pixel Data */
1227#define DSI_LCD1_CTRL_1_CFG_L1_HEX_SLOT_EN (1<<14)
1228/* Bit(s) DSI_LCD1_CTRL_1_RSRV_13_11 reserved */
1229/* Turn Around Bus at Last h Line */
1230#define DSI_LCD1_CTRL_1_CFG_L1_LAST_LINE_TURN (1<<10)
1231/* Go to Low Power Every Frame */
1232#define DSI_LCD1_CTRL_1_CFG_L1_LPM_FRAME_EN (1<<9)
1233/* Go to Low Power Every Line */
1234#define DSI_LCD1_CTRL_1_CFG_L1_LPM_LINE_EN (1<<8)
1235/* Bit(s) DSI_LCD1_CTRL_1_RSRV_7_4 reserved */
1236/* DSI Transmission Mode for LCD 1 */
1237#define DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_SHIFT 2
1238#define DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_MASK (3<<2)
1239/* LCD 1 Input Data RGB Mode for LCD 1 */
1240#define DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_SHIFT 0
1241#define DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_MASK (3<<2)
1242
1243/* DSI_PHY_CTRL_2 0x0088 DPHY Control Register 2 */
1244/* Bit(s) DSI_PHY_CTRL_2_RSRV_31_12 reserved */
1245/* DPHY LP Receiver Enable */
1246#define DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_MASK (0xf<<8)
1247#define DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_SHIFT 8
1248/* DPHY Data Lane Enable */
1249#define DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_MASK (0xf<<4)
1250#define DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_SHIFT 4
1251/* DPHY Bus Turn Around */
1252#define DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_MASK (0xf)
1253#define DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_SHIFT 0
1254
1255/* DSI_CPU_CMD_1 0x0024 DSI CPU Packet Command Register 1 */
1256/* Bit(s) DSI_CPU_CMD_1_RSRV_31_24 reserved */
1257/* LPDT TX Enable */
1258#define DSI_CPU_CMD_1_CFG_TXLP_LPDT_MASK (0xf<<20)
1259#define DSI_CPU_CMD_1_CFG_TXLP_LPDT_SHIFT 20
1260/* ULPS TX Enable */
1261#define DSI_CPU_CMD_1_CFG_TXLP_ULPS_MASK (0xf<<16)
1262#define DSI_CPU_CMD_1_CFG_TXLP_ULPS_SHIFT 16
1263/* Low Power TX Trigger Code */
1264#define DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_MASK (0xffff)
1265#define DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_SHIFT 0
1266
1267/* DSI_PHY_TIME_0 0x00c0 DPHY Timing Control Register 0 */
1268/* Length of HS Exit Period in tx_clk_esc Cycles */
1269#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_MASK (0xff<<24)
1270#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_SHIFT 24
1271/* DPHY HS Trail Period Length */
1272#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_MASK (0xff<<16)
1273#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_SHIFT 16
1274/* DPHY HS Zero State Length */
1275#define DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_MASK (0xff<<8)
1276#define DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_SHIFT 8
1277/* DPHY HS Prepare State Length */
1278#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_MASK (0xff)
1279#define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_SHIFT 0
1280
1281/* DSI_PHY_TIME_1 0x00c4 DPHY Timing Control Register 1 */
1282/* Time to Drive LP-00 by New Transmitter */
1283#define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_MASK (0xff<<24)
1284#define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_SHIFT 24
1285/* Time to Drive LP-00 after Turn Request */
1286#define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_MASK (0xff<<16)
1287#define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_SHIFT 16
1288/* DPHY HS Wakeup Period Length */
1289#define DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_MASK (0xffff)
1290#define DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_SHIFT 0
1291
1292/* DSI_PHY_TIME_2 0x00c8 DPHY Timing Control Register 2 */
1293/* DPHY CLK Exit Period Length */
1294#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_MASK (0xff<<24)
1295#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_SHIFT 24
1296/* DPHY CLK Trail Period Length */
1297#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_MASK (0xff<<16)
1298#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_SHIFT 16
1299/* DPHY CLK Zero State Length */
1300#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_MASK (0xff<<8)
1301#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_SHIFT 8
1302/* DPHY CLK LP Length */
1303#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_MASK (0xff)
1304#define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_SHIFT 0
1305
1306/* DSI_PHY_TIME_3 0x00cc DPHY Timing Control Register 3 */
1307/* Bit(s) DSI_PHY_TIME_3_RSRV_31_16 reserved */
1308/* DPHY LP Length */
1309#define DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_MASK (0xff<<8)
1310#define DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_SHIFT 8
1311/* DPHY HS req to rdy Length */
1312#define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_MASK (0xff)
1313#define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_SHIFT 0
1314
1315/*
1316 * DSI timings
1317 * PXA988 has diffrent ESC CLK with MMP2/MMP3
1318 * it will be used in dsi_set_dphy() in pxa688_phy.c
1319 * as low power mode clock.
1320 */
1321#ifdef CONFIG_CPU_PXA988
1322#define DSI_ESC_CLK 52 /* Unit: Mhz */
1323#define DSI_ESC_CLK_T 19 /* Unit: ns */
1324#else
1325#define DSI_ESC_CLK 66 /* Unit: Mhz */
1326#define DSI_ESC_CLK_T 15 /* Unit: ns */
1327#endif
1328
1329/* LVDS */
1330/* LVDS_PHY_CTRL */
1331#define LVDS_PHY_CTL 0x2A4
1332#define LVDS_PLL_LOCK (1 << 31)
1333#define LVDS_PHY_EXT_MASK (7 << 28)
1334#define LVDS_PHY_EXT_SHIFT (28)
1335#define LVDS_CLK_PHASE_MASK (0x7f << 16)
1336#define LVDS_CLK_PHASE_SHIFT (16)
1337#define LVDS_SSC_RESET_EXT (1 << 13)
1338#define LVDS_SSC_MODE_DOWN_SPREAD (1 << 12)
1339#define LVDS_SSC_EN (1 << 11)
1340#define LVDS_PU_PLL (1 << 10)
1341#define LVDS_PU_TX (1 << 9)
1342#define LVDS_PU_IVREF (1 << 8)
1343#define LVDS_CLK_SEL (1 << 7)
1344#define LVDS_CLK_SEL_LVDS_PCLK (1 << 7)
1345#define LVDS_PD_CH_MASK (0x3f << 1)
1346#define LVDS_PD_CH(ch) ((ch) << 1)
1347#define LVDS_RST (1 << 0)
1348
1349#define LVDS_PHY_CTL_EXT 0x2A8
1350
1351/* LVDS_PHY_CTRL_EXT1 */
1352#define LVDS_SSC_RNGE_MASK (0x7ff << 16)
1353#define LVDS_SSC_RNGE_SHIFT (16)
1354#define LVDS_RESERVE_IN_MASK (0xf << 12)
1355#define LVDS_RESERVE_IN_SHIFT (12)
1356#define LVDS_TEST_MON_MASK (0x7 << 8)
1357#define LVDS_TEST_MON_SHIFT (8)
1358#define LVDS_POL_SWAP_MASK (0x3f << 0)
1359#define LVDS_POL_SWAP_SHIFT (0)
1360
1361/* LVDS_PHY_CTRL_EXT2 */
1362#define LVDS_TX_DIF_AMP_MASK (0xf << 24)
1363#define LVDS_TX_DIF_AMP_SHIFT (24)
1364#define LVDS_TX_DIF_CM_MASK (0x3 << 22)
1365#define LVDS_TX_DIF_CM_SHIFT (22)
1366#define LVDS_SELLV_TXCLK_MASK (0x1f << 16)
1367#define LVDS_SELLV_TXCLK_SHIFT (16)
1368#define LVDS_TX_CMFB_EN (0x1 << 15)
1369#define LVDS_TX_TERM_EN (0x1 << 14)
1370#define LVDS_SELLV_TXDATA_MASK (0x1f << 8)
1371#define LVDS_SELLV_TXDATA_SHIFT (8)
1372#define LVDS_SELLV_OP7_MASK (0x3 << 6)
1373#define LVDS_SELLV_OP7_SHIFT (6)
1374#define LVDS_SELLV_OP6_MASK (0x3 << 4)
1375#define LVDS_SELLV_OP6_SHIFT (4)
1376#define LVDS_SELLV_OP9_MASK (0x3 << 2)
1377#define LVDS_SELLV_OP9_SHIFT (2)
1378#define LVDS_STRESSTST_EN (0x1 << 0)
1379
1380/* LVDS_PHY_CTRL_EXT3 */
1381#define LVDS_KVCO_MASK (0xf << 28)
1382#define LVDS_KVCO_SHIFT (28)
1383#define LVDS_CTUNE_MASK (0x3 << 26)
1384#define LVDS_CTUNE_SHIFT (26)
1385#define LVDS_VREG_IVREF_MASK (0x3 << 24)
1386#define LVDS_VREG_IVREF_SHIFT (24)
1387#define LVDS_VDDL_MASK (0xf << 20)
1388#define LVDS_VDDL_SHIFT (20)
1389#define LVDS_VDDM_MASK (0x3 << 18)
1390#define LVDS_VDDM_SHIFT (18)
1391#define LVDS_FBDIV_MASK (0xf << 8)
1392#define LVDS_FBDIV_SHIFT (8)
1393#define LVDS_REFDIV_MASK (0x7f << 0)
1394#define LVDS_REFDIV_SHIFT (0)
1395
1396/* LVDS_PHY_CTRL_EXT4 */
1397#define LVDS_SSC_FREQ_DIV_MASK (0xffff << 16)
1398#define LVDS_SSC_FREQ_DIV_SHIFT (16)
1399#define LVDS_INTPI_MASK (0xf << 12)
1400#define LVDS_INTPI_SHIFT (12)
1401#define LVDS_VCODIV_SEL_SE_MASK (0xf << 8)
1402#define LVDS_VCODIV_SEL_SE_SHIFT (8)
1403#define LVDS_RESET_INTP_EXT (0x1 << 7)
1404#define LVDS_VCO_VRNG_MASK (0x7 << 4)
1405#define LVDS_VCO_VRNG_SHIFT (4)
1406#define LVDS_PI_EN (0x1 << 3)
1407#define LVDS_ICP_MASK (0x7 << 0)
1408#define LVDS_ICP_SHIFT (0)
1409
1410/* LVDS_PHY_CTRL_EXT5 */
1411#define LVDS_FREQ_OFFSET_MASK (0x1ffff << 15)
1412#define LVDS_FREQ_OFFSET_SHIFT (15)
1413#define LVDS_FREQ_OFFSET_VALID (0x1 << 2)
1414#define LVDS_FREQ_OFFSET_MODE_CK_DIV4_OUT (0x1 << 1)
1415#define LVDS_FREQ_OFFSET_MODE_EN (0x1 << 0)
1416
1417enum {
1418 PATH_PN = 0,
1419 PATH_TV,
1420 PATH_P2,
1421};
1422
1423/*
1424 * mmp path describes part of mmp path related info:
1425 * which is hiden in display driver and not exported to buffer driver
1426 */
1427struct mmphw_ctrl;
1428struct mmphw_path_plat {
1429 int id;
1430 struct mmphw_ctrl *ctrl;
1431 struct mmp_path *path;
1432 u32 path_config;
1433 u32 link_config;
1434 u32 dsi_rbswap;
1435};
1436
1437/* mmp ctrl describes mmp controller related info */
1438struct mmphw_ctrl {
1439 /* platform related, get from config */
1440 const char *name;
1441 int irq;
1442 void *reg_base;
1443 struct clk *clk;
1444
1445 /* sys info */
1446 struct device *dev;
1447
1448 /* state */
1449 int open_count;
1450 int status;
1451 struct mutex access_ok;
1452
1453 /*pathes*/
1454 int path_num;
1455 struct mmphw_path_plat path_plats[0];
1456};
1457
1458static inline int overlay_is_vid(struct mmp_overlay *overlay)
1459{
1460 return overlay->dmafetch_id & 1;
1461}
1462
1463static inline struct mmphw_path_plat *path_to_path_plat(struct mmp_path *path)
1464{
1465 return (struct mmphw_path_plat *)path->plat_data;
1466}
1467
1468static inline struct mmphw_ctrl *path_to_ctrl(struct mmp_path *path)
1469{
1470 return path_to_path_plat(path)->ctrl;
1471}
1472
1473static inline struct mmphw_ctrl *overlay_to_ctrl(struct mmp_overlay *overlay)
1474{
1475 return path_to_ctrl(overlay->path);
1476}
1477
1478static inline void *ctrl_regs(struct mmp_path *path)
1479{
1480 return path_to_ctrl(path)->reg_base;
1481}
1482
1483/* path regs, for regs symmetrical for both pathes */
1484static inline struct lcd_regs *path_regs(struct mmp_path *path)
1485{
1486 if (path->id == PATH_PN)
1487 return (struct lcd_regs *)(ctrl_regs(path) + 0xc0);
1488 else if (path->id == PATH_TV)
1489 return (struct lcd_regs *)ctrl_regs(path);
1490 else if (path->id == PATH_P2)
1491 return (struct lcd_regs *)(ctrl_regs(path) + 0x200);
1492 else {
1493 dev_err(path->dev, "path id %d invalid\n", path->id);
1494 BUG_ON(1);
1495 return NULL;
1496 }
1497}
1498
1499#ifdef CONFIG_MMP_DISP_SPI
1500extern int lcd_spi_register(struct mmphw_ctrl *ctrl);
1501#endif
1502#endif /* _MMP_CTRL_H_ */
diff --git a/drivers/video/fbdev/mmp/hw/mmp_spi.c b/drivers/video/fbdev/mmp/hw/mmp_spi.c
new file mode 100644
index 000000000000..e62ca7bf0d5e
--- /dev/null
+++ b/drivers/video/fbdev/mmp/hw/mmp_spi.c
@@ -0,0 +1,180 @@
1/*
2 * linux/drivers/video/mmp/hw/mmp_spi.c
3 * using the spi in LCD controler for commands send
4 *
5 * Copyright (C) 2012 Marvell Technology Group Ltd.
6 * Authors: Guoqing Li <ligq@marvell.com>
7 * Lisa Du <cldu@marvell.com>
8 * Zhou Zhu <zzhu3@marvell.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
22 *
23 */
24#include <linux/errno.h>
25#include <linux/delay.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/spi/spi.h>
29#include "mmp_ctrl.h"
30
31/**
32 * spi_write - write command to the SPI port
33 * @data: can be 8/16/32-bit, MSB justified data to write.
34 * @len: data length.
35 *
36 * Wait bus transfer complete IRQ.
37 * The caller is expected to perform the necessary locking.
38 *
39 * Returns:
40 * %-ETIMEDOUT timeout occurred
41 * 0 success
42 */
43static inline int lcd_spi_write(struct spi_device *spi, u32 data)
44{
45 int timeout = 100000, isr, ret = 0;
46 u32 tmp;
47 void *reg_base =
48 *(void **)spi_master_get_devdata(spi->master);
49
50 /* clear ISR */
51 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR);
52
53 switch (spi->bits_per_word) {
54 case 8:
55 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA);
56 break;
57 case 16:
58 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA);
59 break;
60 case 32:
61 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA);
62 break;
63 default:
64 dev_err(&spi->dev, "Wrong spi bit length\n");
65 }
66
67 /* SPI start to send command */
68 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL);
69 tmp &= ~CFG_SPI_START_MASK;
70 tmp |= CFG_SPI_START(1);
71 writel(tmp, reg_base + LCD_SPU_SPI_CTRL);
72
73 isr = readl_relaxed(reg_base + SPU_IRQ_ISR);
74 while (!(isr & SPI_IRQ_ENA_MASK)) {
75 udelay(100);
76 isr = readl_relaxed(reg_base + SPU_IRQ_ISR);
77 if (!--timeout) {
78 ret = -ETIMEDOUT;
79 dev_err(&spi->dev, "spi cmd send time out\n");
80 break;
81 }
82 }
83
84 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL);
85 tmp &= ~CFG_SPI_START_MASK;
86 tmp |= CFG_SPI_START(0);
87 writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL);
88
89 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR);
90
91 return ret;
92}
93
94static int lcd_spi_setup(struct spi_device *spi)
95{
96 void *reg_base =
97 *(void **)spi_master_get_devdata(spi->master);
98 u32 tmp;
99
100 tmp = CFG_SCLKCNT(16) |
101 CFG_TXBITS(spi->bits_per_word) |
102 CFG_SPI_SEL(1) | CFG_SPI_ENA(1) |
103 CFG_SPI_3W4WB(1);
104 writel(tmp, reg_base + LCD_SPU_SPI_CTRL);
105
106 /*
107 * After set mode it need a time to pull up the spi singals,
108 * or it would cause the wrong waveform when send spi command,
109 * especially on pxa910h
110 */
111 tmp = readl_relaxed(reg_base + SPU_IOPAD_CONTROL);
112 if ((tmp & CFG_IOPADMODE_MASK) != IOPAD_DUMB18SPI)
113 writel_relaxed(IOPAD_DUMB18SPI |
114 (tmp & ~CFG_IOPADMODE_MASK),
115 reg_base + SPU_IOPAD_CONTROL);
116 udelay(20);
117 return 0;
118}
119
120static int lcd_spi_one_transfer(struct spi_device *spi, struct spi_message *m)
121{
122 struct spi_transfer *t;
123 int i;
124
125 list_for_each_entry(t, &m->transfers, transfer_list) {
126 switch (spi->bits_per_word) {
127 case 8:
128 for (i = 0; i < t->len; i++)
129 lcd_spi_write(spi, ((u8 *)t->tx_buf)[i]);
130 break;
131 case 16:
132 for (i = 0; i < t->len/2; i++)
133 lcd_spi_write(spi, ((u16 *)t->tx_buf)[i]);
134 break;
135 case 32:
136 for (i = 0; i < t->len/4; i++)
137 lcd_spi_write(spi, ((u32 *)t->tx_buf)[i]);
138 break;
139 default:
140 dev_err(&spi->dev, "Wrong spi bit length\n");
141 }
142 }
143
144 m->status = 0;
145 if (m->complete)
146 m->complete(m->context);
147 return 0;
148}
149
150int lcd_spi_register(struct mmphw_ctrl *ctrl)
151{
152 struct spi_master *master;
153 void **p_regbase;
154 int err;
155
156 master = spi_alloc_master(ctrl->dev, sizeof(void *));
157 if (!master) {
158 dev_err(ctrl->dev, "unable to allocate SPI master\n");
159 return -ENOMEM;
160 }
161 p_regbase = spi_master_get_devdata(master);
162 *p_regbase = ctrl->reg_base;
163
164 /* set bus num to 5 to avoid conflict with other spi hosts */
165 master->bus_num = 5;
166 master->num_chipselect = 1;
167 master->setup = lcd_spi_setup;
168 master->transfer = lcd_spi_one_transfer;
169
170 err = spi_register_master(master);
171 if (err < 0) {
172 dev_err(ctrl->dev, "unable to register SPI master\n");
173 spi_master_put(master);
174 return err;
175 }
176
177 dev_info(&master->dev, "registered\n");
178
179 return 0;
180}
diff --git a/drivers/video/fbdev/mmp/panel/Kconfig b/drivers/video/fbdev/mmp/panel/Kconfig
new file mode 100644
index 000000000000..4b2c4f457b11
--- /dev/null
+++ b/drivers/video/fbdev/mmp/panel/Kconfig
@@ -0,0 +1,6 @@
1config MMP_PANEL_TPOHVGA
2 bool "tpohvga panel TJ032MD01BW support"
3 depends on SPI_MASTER
4 default n
5 help
6 tpohvga panel support
diff --git a/drivers/video/fbdev/mmp/panel/Makefile b/drivers/video/fbdev/mmp/panel/Makefile
new file mode 100644
index 000000000000..2f91611c7e5e
--- /dev/null
+++ b/drivers/video/fbdev/mmp/panel/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_MMP_PANEL_TPOHVGA) += tpo_tj032md01bw.o
diff --git a/drivers/video/fbdev/mmp/panel/tpo_tj032md01bw.c b/drivers/video/fbdev/mmp/panel/tpo_tj032md01bw.c
new file mode 100644
index 000000000000..998978b08f5e
--- /dev/null
+++ b/drivers/video/fbdev/mmp/panel/tpo_tj032md01bw.c
@@ -0,0 +1,186 @@
1/*
2 * linux/drivers/video/mmp/panel/tpo_tj032md01bw.c
3 * active panel using spi interface to do init
4 *
5 * Copyright (C) 2012 Marvell Technology Group Ltd.
6 * Authors: Guoqing Li <ligq@marvell.com>
7 * Lisa Du <cldu@marvell.com>
8 * Zhou Zhu <zzhu3@marvell.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
22 *
23 */
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/kernel.h>
28#include <linux/errno.h>
29#include <linux/string.h>
30#include <linux/delay.h>
31#include <linux/platform_device.h>
32#include <linux/err.h>
33#include <linux/spi/spi.h>
34#include <video/mmp_disp.h>
35
36static u16 init[] = {
37 0x0801,
38 0x0800,
39 0x0200,
40 0x0304,
41 0x040e,
42 0x0903,
43 0x0b18,
44 0x0c53,
45 0x0d01,
46 0x0ee0,
47 0x0f01,
48 0x1058,
49 0x201e,
50 0x210a,
51 0x220a,
52 0x231e,
53 0x2400,
54 0x2532,
55 0x2600,
56 0x27ac,
57 0x2904,
58 0x2aa2,
59 0x2b45,
60 0x2c45,
61 0x2d15,
62 0x2e5a,
63 0x2fff,
64 0x306b,
65 0x310d,
66 0x3248,
67 0x3382,
68 0x34bd,
69 0x35e7,
70 0x3618,
71 0x3794,
72 0x3801,
73 0x395d,
74 0x3aae,
75 0x3bff,
76 0x07c9,
77};
78
79static u16 poweroff[] = {
80 0x07d9,
81};
82
83struct tpohvga_plat_data {
84 void (*plat_onoff)(int status);
85 struct spi_device *spi;
86};
87
88static void tpohvga_onoff(struct mmp_panel *panel, int status)
89{
90 struct tpohvga_plat_data *plat = panel->plat_data;
91 int ret;
92
93 if (status) {
94 plat->plat_onoff(1);
95
96 ret = spi_write(plat->spi, init, sizeof(init));
97 if (ret < 0)
98 dev_warn(panel->dev, "init cmd failed(%d)\n", ret);
99 } else {
100 ret = spi_write(plat->spi, poweroff, sizeof(poweroff));
101 if (ret < 0)
102 dev_warn(panel->dev, "poweroff cmd failed(%d)\n", ret);
103
104 plat->plat_onoff(0);
105 }
106}
107
108static struct mmp_mode mmp_modes_tpohvga[] = {
109 [0] = {
110 .pixclock_freq = 10394400,
111 .refresh = 60,
112 .xres = 320,
113 .yres = 480,
114 .hsync_len = 10,
115 .left_margin = 15,
116 .right_margin = 10,
117 .vsync_len = 2,
118 .upper_margin = 4,
119 .lower_margin = 2,
120 .invert_pixclock = 1,
121 .pix_fmt_out = PIXFMT_RGB565,
122 },
123};
124
125static int tpohvga_get_modelist(struct mmp_panel *panel,
126 struct mmp_mode **modelist)
127{
128 *modelist = mmp_modes_tpohvga;
129 return 1;
130}
131
132static struct mmp_panel panel_tpohvga = {
133 .name = "tpohvga",
134 .panel_type = PANELTYPE_ACTIVE,
135 .get_modelist = tpohvga_get_modelist,
136 .set_onoff = tpohvga_onoff,
137};
138
139static int tpohvga_probe(struct spi_device *spi)
140{
141 struct mmp_mach_panel_info *mi;
142 int ret;
143 struct tpohvga_plat_data *plat_data;
144
145 /* get configs from platform data */
146 mi = spi->dev.platform_data;
147 if (mi == NULL) {
148 dev_err(&spi->dev, "%s: no platform data defined\n", __func__);
149 return -EINVAL;
150 }
151
152 /* setup spi related info */
153 spi->bits_per_word = 16;
154 ret = spi_setup(spi);
155 if (ret < 0) {
156 dev_err(&spi->dev, "spi setup failed %d", ret);
157 return ret;
158 }
159
160 plat_data = kzalloc(sizeof(*plat_data), GFP_KERNEL);
161 if (plat_data == NULL)
162 return -ENOMEM;
163
164 plat_data->spi = spi;
165 plat_data->plat_onoff = mi->plat_set_onoff;
166 panel_tpohvga.plat_data = plat_data;
167 panel_tpohvga.plat_path_name = mi->plat_path_name;
168 panel_tpohvga.dev = &spi->dev;
169
170 mmp_register_panel(&panel_tpohvga);
171
172 return 0;
173}
174
175static struct spi_driver panel_tpohvga_driver = {
176 .driver = {
177 .name = "tpo-hvga",
178 .owner = THIS_MODULE,
179 },
180 .probe = tpohvga_probe,
181};
182module_spi_driver(panel_tpohvga_driver);
183
184MODULE_AUTHOR("Lisa Du<cldu@marvell.com>");
185MODULE_DESCRIPTION("Panel driver for tpohvga");
186MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-10 06:45:16 -0500