diff options
Diffstat (limited to 'drivers/video/fbdev/mmp/hw/mmp_ctrl.h')
| -rw-r--r-- | drivers/video/fbdev/mmp/hw/mmp_ctrl.h | 1502 |
1 files changed, 1502 insertions, 0 deletions
diff --git a/drivers/video/fbdev/mmp/hw/mmp_ctrl.h b/drivers/video/fbdev/mmp/hw/mmp_ctrl.h new file mode 100644 index 000000000000..53301cfdb1ae --- /dev/null +++ b/drivers/video/fbdev/mmp/hw/mmp_ctrl.h | |||
| @@ -0,0 +1,1502 @@ | |||
| 1 | /* | ||
| 2 | * drivers/video/mmp/hw/mmp_ctrl.h | ||
| 3 | * | ||
| 4 | * | ||
| 5 | * Copyright (C) 2012 Marvell Technology Group Ltd. | ||
| 6 | * Authors: Guoqing Li <ligq@marvell.com> | ||
| 7 | * Lisa Du <cldu@marvell.com> | ||
| 8 | * Zhou Zhu <zzhu3@marvell.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 18 | * more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License along with | ||
| 21 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
| 22 | * | ||
| 23 | */ | ||
| 24 | |||
| 25 | #ifndef _MMP_CTRL_H_ | ||
| 26 | #define _MMP_CTRL_H_ | ||
| 27 | |||
| 28 | #include <video/mmp_disp.h> | ||
| 29 | |||
| 30 | /* ------------< LCD register >------------ */ | ||
| 31 | struct lcd_regs { | ||
| 32 | /* TV patch register for MMP2 */ | ||
| 33 | /* 32 bit TV Video Frame0 Y Starting Address */ | ||
| 34 | #define LCD_TVD_START_ADDR_Y0 (0x0000) | ||
| 35 | /* 32 bit TV Video Frame0 U Starting Address */ | ||
| 36 | #define LCD_TVD_START_ADDR_U0 (0x0004) | ||
| 37 | /* 32 bit TV Video Frame0 V Starting Address */ | ||
| 38 | #define LCD_TVD_START_ADDR_V0 (0x0008) | ||
| 39 | /* 32 bit TV Video Frame0 Command Starting Address */ | ||
| 40 | #define LCD_TVD_START_ADDR_C0 (0x000C) | ||
| 41 | /* 32 bit TV Video Frame1 Y Starting Address Register*/ | ||
| 42 | #define LCD_TVD_START_ADDR_Y1 (0x0010) | ||
| 43 | /* 32 bit TV Video Frame1 U Starting Address Register*/ | ||
| 44 | #define LCD_TVD_START_ADDR_U1 (0x0014) | ||
| 45 | /* 32 bit TV Video Frame1 V Starting Address Register*/ | ||
| 46 | #define LCD_TVD_START_ADDR_V1 (0x0018) | ||
| 47 | /* 32 bit TV Video Frame1 Command Starting Address Register*/ | ||
| 48 | #define LCD_TVD_START_ADDR_C1 (0x001C) | ||
| 49 | /* 32 bit TV Video Y andC Line Length(Pitch)Register*/ | ||
| 50 | #define LCD_TVD_PITCH_YC (0x0020) | ||
| 51 | /* 32 bit TV Video U andV Line Length(Pitch)Register*/ | ||
| 52 | #define LCD_TVD_PITCH_UV (0x0024) | ||
| 53 | /* 32 bit TV Video Starting Point on Screen Register*/ | ||
| 54 | #define LCD_TVD_OVSA_HPXL_VLN (0x0028) | ||
| 55 | /* 32 bit TV Video Source Size Register*/ | ||
| 56 | #define LCD_TVD_HPXL_VLN (0x002C) | ||
| 57 | /* 32 bit TV Video Destination Size (After Zooming)Register*/ | ||
| 58 | #define LCD_TVDZM_HPXL_VLN (0x0030) | ||
| 59 | u32 v_y0; | ||
| 60 | u32 v_u0; | ||
| 61 | u32 v_v0; | ||
| 62 | u32 v_c0; | ||
| 63 | u32 v_y1; | ||
| 64 | u32 v_u1; | ||
| 65 | u32 v_v1; | ||
| 66 | u32 v_c1; | ||
| 67 | u32 v_pitch_yc; /* Video Y and C Line Length (Pitch) */ | ||
| 68 | u32 v_pitch_uv; /* Video U and V Line Length (Pitch) */ | ||
| 69 | u32 v_start; /* Video Starting Point on Screen */ | ||
| 70 | u32 v_size; /* Video Source Size */ | ||
| 71 | u32 v_size_z; /* Video Destination Size (After Zooming) */ | ||
| 72 | |||
| 73 | /* 32 bit TV Graphic Frame 0 Starting Address Register*/ | ||
| 74 | #define LCD_TVG_START_ADDR0 (0x0034) | ||
| 75 | /* 32 bit TV Graphic Frame 1 Starting Address Register*/ | ||
| 76 | #define LCD_TVG_START_ADDR1 (0x0038) | ||
| 77 | /* 32 bit TV Graphic Line Length(Pitch)Register*/ | ||
| 78 | #define LCD_TVG_PITCH (0x003C) | ||
| 79 | /* 32 bit TV Graphic Starting Point on Screen Register*/ | ||
| 80 | #define LCD_TVG_OVSA_HPXL_VLN (0x0040) | ||
| 81 | /* 32 bit TV Graphic Source Size Register*/ | ||
| 82 | #define LCD_TVG_HPXL_VLN (0x0044) | ||
| 83 | /* 32 bit TV Graphic Destination size (after Zooming)Register*/ | ||
| 84 | #define LCD_TVGZM_HPXL_VLN (0x0048) | ||
| 85 | u32 g_0; /* Graphic Frame 0/1 Starting Address */ | ||
| 86 | u32 g_1; | ||
| 87 | u32 g_pitch; /* Graphic Line Length (Pitch) */ | ||
| 88 | u32 g_start; /* Graphic Starting Point on Screen */ | ||
| 89 | u32 g_size; /* Graphic Source Size */ | ||
| 90 | u32 g_size_z; /* Graphic Destination Size (After Zooming) */ | ||
| 91 | |||
| 92 | /* 32 bit TV Hardware Cursor Starting Point on screen Register*/ | ||
| 93 | #define LCD_TVC_OVSA_HPXL_VLN (0x004C) | ||
| 94 | /* 32 bit TV Hardware Cursor Size Register */ | ||
| 95 | #define LCD_TVC_HPXL_VLN (0x0050) | ||
| 96 | u32 hc_start; /* Hardware Cursor */ | ||
| 97 | u32 hc_size; /* Hardware Cursor */ | ||
| 98 | |||
| 99 | /* 32 bit TV Total Screen Size Register*/ | ||
| 100 | #define LCD_TV_V_H_TOTAL (0x0054) | ||
| 101 | /* 32 bit TV Screen Active Size Register*/ | ||
| 102 | #define LCD_TV_V_H_ACTIVE (0x0058) | ||
| 103 | /* 32 bit TV Screen Horizontal Porch Register*/ | ||
| 104 | #define LCD_TV_H_PORCH (0x005C) | ||
| 105 | /* 32 bit TV Screen Vertical Porch Register*/ | ||
| 106 | #define LCD_TV_V_PORCH (0x0060) | ||
| 107 | u32 screen_size; /* Screen Total Size */ | ||
| 108 | u32 screen_active; /* Screen Active Size */ | ||
| 109 | u32 screen_h_porch; /* Screen Horizontal Porch */ | ||
| 110 | u32 screen_v_porch; /* Screen Vertical Porch */ | ||
| 111 | |||
| 112 | /* 32 bit TV Screen Blank Color Register*/ | ||
| 113 | #define LCD_TV_BLANKCOLOR (0x0064) | ||
| 114 | /* 32 bit TV Hardware Cursor Color1 Register*/ | ||
| 115 | #define LCD_TV_ALPHA_COLOR1 (0x0068) | ||
| 116 | /* 32 bit TV Hardware Cursor Color2 Register*/ | ||
| 117 | #define LCD_TV_ALPHA_COLOR2 (0x006C) | ||
| 118 | u32 blank_color; /* Screen Blank Color */ | ||
| 119 | u32 hc_Alpha_color1; /* Hardware Cursor Color1 */ | ||
| 120 | u32 hc_Alpha_color2; /* Hardware Cursor Color2 */ | ||
| 121 | |||
| 122 | /* 32 bit TV Video Y Color Key Control*/ | ||
| 123 | #define LCD_TV_COLORKEY_Y (0x0070) | ||
| 124 | /* 32 bit TV Video U Color Key Control*/ | ||
| 125 | #define LCD_TV_COLORKEY_U (0x0074) | ||
| 126 | /* 32 bit TV Video V Color Key Control*/ | ||
| 127 | #define LCD_TV_COLORKEY_V (0x0078) | ||
| 128 | u32 v_colorkey_y; /* Video Y Color Key Control */ | ||
| 129 | u32 v_colorkey_u; /* Video U Color Key Control */ | ||
| 130 | u32 v_colorkey_v; /* Video V Color Key Control */ | ||
| 131 | |||
| 132 | /* 32 bit TV VSYNC PulsePixel Edge Control Register*/ | ||
| 133 | #define LCD_TV_SEPXLCNT (0x007C) | ||
| 134 | u32 vsync_ctrl; /* VSYNC PulsePixel Edge Control */ | ||
| 135 | }; | ||
| 136 | |||
| 137 | #define intf_ctrl(id) ((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \ | ||
| 138 | LCD_DUMB2_CTRL) : LCD_SPU_DUMB_CTRL) | ||
| 139 | #define dma_ctrl0(id) ((id) ? (((id) & 1) ? LCD_TV_CTRL0 : \ | ||
| 140 | LCD_PN2_CTRL0) : LCD_SPU_DMA_CTRL0) | ||
| 141 | #define dma_ctrl1(id) ((id) ? (((id) & 1) ? LCD_TV_CTRL1 : \ | ||
| 142 | LCD_PN2_CTRL1) : LCD_SPU_DMA_CTRL1) | ||
| 143 | #define dma_ctrl(ctrl1, id) (ctrl1 ? dma_ctrl1(id) : dma_ctrl0(id)) | ||
| 144 | |||
| 145 | /* 32 bit TV Path DMA Control 0*/ | ||
| 146 | #define LCD_TV_CTRL0 (0x0080) | ||
| 147 | /* 32 bit TV Path DMA Control 1*/ | ||
| 148 | #define LCD_TV_CTRL1 (0x0084) | ||
| 149 | /* 32 bit TV Path Video Contrast*/ | ||
| 150 | #define LCD_TV_CONTRAST (0x0088) | ||
| 151 | /* 32 bit TV Path Video Saturation*/ | ||
| 152 | #define LCD_TV_SATURATION (0x008C) | ||
| 153 | /* 32 bit TV Path Video Hue Adjust*/ | ||
| 154 | #define LCD_TV_CBSH_HUE (0x0090) | ||
| 155 | /* 32 bit TV Path TVIF Control Register */ | ||
| 156 | #define LCD_TVIF_CTRL (0x0094) | ||
| 157 | #define TV_VBLNK_VALID_EN (1 << 12) | ||
| 158 | |||
| 159 | /* 32 bit TV Path I/O Pad Control*/ | ||
| 160 | #define LCD_TVIOPAD_CTRL (0x0098) | ||
| 161 | /* 32 bit TV Path Cloc Divider */ | ||
| 162 | #define LCD_TCLK_DIV (0x009C) | ||
| 163 | |||
| 164 | #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\ | ||
| 165 | ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV)) | ||
| 166 | #define intf_rbswap_ctrl(id) ((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \ | ||
| 167 | PN2_IOPAD_CONTROL) : LCD_TOP_CTRL) | ||
| 168 | |||
| 169 | /* dither configure */ | ||
| 170 | #ifdef CONFIG_CPU_PXA988 | ||
| 171 | #define LCD_DITHER_CTRL (0x01EC) | ||
| 172 | #else | ||
| 173 | #define LCD_DITHER_CTRL (0x00A0) | ||
| 174 | #endif | ||
| 175 | |||
| 176 | #define DITHER_TBL_INDEX_SEL(s) ((s) << 16) | ||
| 177 | #define DITHER_MODE2(m) ((m) << 12) | ||
| 178 | #define DITHER_MODE2_SHIFT (12) | ||
| 179 | #define DITHER_4X8_EN2 (1 << 9) | ||
| 180 | #define DITHER_4X8_EN2_SHIFT (9) | ||
| 181 | #define DITHER_EN2 (1 << 8) | ||
| 182 | #define DITHER_MODE1(m) ((m) << 4) | ||
| 183 | #define DITHER_MODE1_SHIFT (4) | ||
| 184 | #define DITHER_4X8_EN1 (1 << 1) | ||
| 185 | #define DITHER_4X8_EN1_SHIFT (1) | ||
| 186 | #define DITHER_EN1 (1) | ||
| 187 | |||
| 188 | /* dither table data was fixed by video bpp of input and output*/ | ||
| 189 | #ifdef CONFIG_CPU_PXA988 | ||
| 190 | #define DITHER_TB_4X4_INDEX0 (0x6e4ca280) | ||
| 191 | #define DITHER_TB_4X4_INDEX1 (0x5d7f91b3) | ||
| 192 | #define DITHER_TB_4X8_INDEX0 (0xb391a280) | ||
| 193 | #define DITHER_TB_4X8_INDEX1 (0x7f5d6e4c) | ||
| 194 | #define DITHER_TB_4X8_INDEX2 (0x80a291b3) | ||
| 195 | #define DITHER_TB_4X8_INDEX3 (0x4c6e5d7f) | ||
| 196 | #define LCD_DITHER_TBL_DATA (0x01F0) | ||
| 197 | #else | ||
| 198 | #define DITHER_TB_4X4_INDEX0 (0x3b19f7d5) | ||
| 199 | #define DITHER_TB_4X4_INDEX1 (0x082ac4e6) | ||
| 200 | #define DITHER_TB_4X8_INDEX0 (0xf7d508e6) | ||
| 201 | #define DITHER_TB_4X8_INDEX1 (0x3b194c2a) | ||
| 202 | #define DITHER_TB_4X8_INDEX2 (0xc4e6d5f7) | ||
| 203 | #define DITHER_TB_4X8_INDEX3 (0x082a193b) | ||
| 204 | #define LCD_DITHER_TBL_DATA (0x00A4) | ||
| 205 | #endif | ||
| 206 | |||
| 207 | /* Video Frame 0&1 start address registers */ | ||
| 208 | #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0 | ||
| 209 | #define LCD_SPU_DMA_START_ADDR_U0 0x00C4 | ||
| 210 | #define LCD_SPU_DMA_START_ADDR_V0 0x00C8 | ||
| 211 | #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */ | ||
| 212 | #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0 | ||
| 213 | #define LCD_SPU_DMA_START_ADDR_U1 0x00D4 | ||
| 214 | #define LCD_SPU_DMA_START_ADDR_V1 0x00D8 | ||
| 215 | #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */ | ||
| 216 | |||
| 217 | /* YC & UV Pitch */ | ||
| 218 | #define LCD_SPU_DMA_PITCH_YC 0x00E0 | ||
| 219 | #define SPU_DMA_PITCH_C(c) ((c)<<16) | ||
| 220 | #define SPU_DMA_PITCH_Y(y) (y) | ||
| 221 | #define LCD_SPU_DMA_PITCH_UV 0x00E4 | ||
| 222 | #define SPU_DMA_PITCH_V(v) ((v)<<16) | ||
| 223 | #define SPU_DMA_PITCH_U(u) (u) | ||
| 224 | |||
| 225 | /* Video Starting Point on Screen Register */ | ||
| 226 | #define LCD_SPUT_DMA_OVSA_HPXL_VLN 0x00E8 | ||
| 227 | #define CFG_DMA_OVSA_VLN(y) ((y)<<16) /* 0~0xfff */ | ||
| 228 | #define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */ | ||
| 229 | |||
| 230 | /* Video Size Register */ | ||
| 231 | #define LCD_SPU_DMA_HPXL_VLN 0x00EC | ||
| 232 | #define CFG_DMA_VLN(y) ((y)<<16) | ||
| 233 | #define CFG_DMA_HPXL(x) (x) | ||
| 234 | |||
| 235 | /* Video Size After zooming Register */ | ||
| 236 | #define LCD_SPU_DZM_HPXL_VLN 0x00F0 | ||
| 237 | #define CFG_DZM_VLN(y) ((y)<<16) | ||
| 238 | #define CFG_DZM_HPXL(x) (x) | ||
| 239 | |||
| 240 | /* Graphic Frame 0&1 Starting Address Register */ | ||
| 241 | #define LCD_CFG_GRA_START_ADDR0 0x00F4 | ||
| 242 | #define LCD_CFG_GRA_START_ADDR1 0x00F8 | ||
| 243 | |||
| 244 | /* Graphic Frame Pitch */ | ||
| 245 | #define LCD_CFG_GRA_PITCH 0x00FC | ||
| 246 | |||
| 247 | /* Graphic Starting Point on Screen Register */ | ||
| 248 | #define LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100 | ||
| 249 | #define CFG_GRA_OVSA_VLN(y) ((y)<<16) | ||
| 250 | #define CFG_GRA_OVSA_HPXL(x) (x) | ||
| 251 | |||
| 252 | /* Graphic Size Register */ | ||
| 253 | #define LCD_SPU_GRA_HPXL_VLN 0x0104 | ||
| 254 | #define CFG_GRA_VLN(y) ((y)<<16) | ||
| 255 | #define CFG_GRA_HPXL(x) (x) | ||
| 256 | |||
| 257 | /* Graphic Size after Zooming Register */ | ||
| 258 | #define LCD_SPU_GZM_HPXL_VLN 0x0108 | ||
| 259 | #define CFG_GZM_VLN(y) ((y)<<16) | ||
| 260 | #define CFG_GZM_HPXL(x) (x) | ||
| 261 | |||
| 262 | /* HW Cursor Starting Point on Screen Register */ | ||
| 263 | #define LCD_SPU_HWC_OVSA_HPXL_VLN 0x010C | ||
| 264 | #define CFG_HWC_OVSA_VLN(y) ((y)<<16) | ||
| 265 | #define CFG_HWC_OVSA_HPXL(x) (x) | ||
| 266 | |||
| 267 | /* HW Cursor Size */ | ||
| 268 | #define LCD_SPU_HWC_HPXL_VLN 0x0110 | ||
| 269 | #define CFG_HWC_VLN(y) ((y)<<16) | ||
| 270 | #define CFG_HWC_HPXL(x) (x) | ||
| 271 | |||
| 272 | /* Total Screen Size Register */ | ||
| 273 | #define LCD_SPUT_V_H_TOTAL 0x0114 | ||
| 274 | #define CFG_V_TOTAL(y) ((y)<<16) | ||
| 275 | #define CFG_H_TOTAL(x) (x) | ||
| 276 | |||
| 277 | /* Total Screen Active Size Register */ | ||
| 278 | #define LCD_SPU_V_H_ACTIVE 0x0118 | ||
| 279 | #define CFG_V_ACTIVE(y) ((y)<<16) | ||
| 280 | #define CFG_H_ACTIVE(x) (x) | ||
| 281 | |||
| 282 | /* Screen H&V Porch Register */ | ||
| 283 | #define LCD_SPU_H_PORCH 0x011C | ||
| 284 | #define CFG_H_BACK_PORCH(b) ((b)<<16) | ||
| 285 | #define CFG_H_FRONT_PORCH(f) (f) | ||
| 286 | #define LCD_SPU_V_PORCH 0x0120 | ||
| 287 | #define CFG_V_BACK_PORCH(b) ((b)<<16) | ||
| 288 | #define CFG_V_FRONT_PORCH(f) (f) | ||
| 289 | |||
| 290 | /* Screen Blank Color Register */ | ||
| 291 | #define LCD_SPU_BLANKCOLOR 0x0124 | ||
| 292 | #define CFG_BLANKCOLOR_MASK 0x00FFFFFF | ||
| 293 | #define CFG_BLANKCOLOR_R_MASK 0x000000FF | ||
| 294 | #define CFG_BLANKCOLOR_G_MASK 0x0000FF00 | ||
| 295 | #define CFG_BLANKCOLOR_B_MASK 0x00FF0000 | ||
| 296 | |||
| 297 | /* HW Cursor Color 1&2 Register */ | ||
| 298 | #define LCD_SPU_ALPHA_COLOR1 0x0128 | ||
| 299 | #define CFG_HWC_COLOR1 0x00FFFFFF | ||
| 300 | #define CFG_HWC_COLOR1_R(red) ((red)<<16) | ||
| 301 | #define CFG_HWC_COLOR1_G(green) ((green)<<8) | ||
| 302 | #define CFG_HWC_COLOR1_B(blue) (blue) | ||
| 303 | #define CFG_HWC_COLOR1_R_MASK 0x000000FF | ||
| 304 | #define CFG_HWC_COLOR1_G_MASK 0x0000FF00 | ||
| 305 | #define CFG_HWC_COLOR1_B_MASK 0x00FF0000 | ||
| 306 | #define LCD_SPU_ALPHA_COLOR2 0x012C | ||
| 307 | #define CFG_HWC_COLOR2 0x00FFFFFF | ||
| 308 | #define CFG_HWC_COLOR2_R_MASK 0x000000FF | ||
| 309 | #define CFG_HWC_COLOR2_G_MASK 0x0000FF00 | ||
| 310 | #define CFG_HWC_COLOR2_B_MASK 0x00FF0000 | ||
| 311 | |||
| 312 | /* Video YUV Color Key Control */ | ||
| 313 | #define LCD_SPU_COLORKEY_Y 0x0130 | ||
| 314 | #define CFG_CKEY_Y2(y2) ((y2)<<24) | ||
| 315 | #define CFG_CKEY_Y2_MASK 0xFF000000 | ||
| 316 | #define CFG_CKEY_Y1(y1) ((y1)<<16) | ||
| 317 | #define CFG_CKEY_Y1_MASK 0x00FF0000 | ||
| 318 | #define CFG_CKEY_Y(y) ((y)<<8) | ||
| 319 | #define CFG_CKEY_Y_MASK 0x0000FF00 | ||
| 320 | #define CFG_ALPHA_Y(y) (y) | ||
| 321 | #define CFG_ALPHA_Y_MASK 0x000000FF | ||
| 322 | #define LCD_SPU_COLORKEY_U 0x0134 | ||
| 323 | #define CFG_CKEY_U2(u2) ((u2)<<24) | ||
| 324 | #define CFG_CKEY_U2_MASK 0xFF000000 | ||
| 325 | #define CFG_CKEY_U1(u1) ((u1)<<16) | ||
| 326 | #define CFG_CKEY_U1_MASK 0x00FF0000 | ||
| 327 | #define CFG_CKEY_U(u) ((u)<<8) | ||
| 328 | #define CFG_CKEY_U_MASK 0x0000FF00 | ||
| 329 | #define CFG_ALPHA_U(u) (u) | ||
| 330 | #define CFG_ALPHA_U_MASK 0x000000FF | ||
| 331 | #define LCD_SPU_COLORKEY_V 0x0138 | ||
| 332 | #define CFG_CKEY_V2(v2) ((v2)<<24) | ||
| 333 | #define CFG_CKEY_V2_MASK 0xFF000000 | ||
| 334 | #define CFG_CKEY_V1(v1) ((v1)<<16) | ||
| 335 | #define CFG_CKEY_V1_MASK 0x00FF0000 | ||
| 336 | #define CFG_CKEY_V(v) ((v)<<8) | ||
| 337 | #define CFG_CKEY_V_MASK 0x0000FF00 | ||
| 338 | #define CFG_ALPHA_V(v) (v) | ||
| 339 | #define CFG_ALPHA_V_MASK 0x000000FF | ||
| 340 | |||
| 341 | /* Graphics/Video DMA color key enable bits in LCD_TV_CTRL1 */ | ||
| 342 | #define CFG_CKEY_GRA 0x2 | ||
| 343 | #define CFG_CKEY_DMA 0x1 | ||
| 344 | |||
| 345 | /* Interlace mode enable bits in LCD_TV_CTRL1 */ | ||
| 346 | #define CFG_TV_INTERLACE_EN (1 << 22) | ||
| 347 | #define CFG_TV_NIB (1 << 0) | ||
| 348 | |||
| 349 | #define LCD_PN_SEPXLCNT 0x013c /* MMP2 */ | ||
| 350 | |||
| 351 | /* SPI Read Data Register */ | ||
| 352 | #define LCD_SPU_SPI_RXDATA 0x0140 | ||
| 353 | |||
| 354 | /* Smart Panel Read Data Register */ | ||
| 355 | #define LCD_SPU_ISA_RSDATA 0x0144 | ||
| 356 | #define ISA_RXDATA_16BIT_1_DATA_MASK 0x000000FF | ||
| 357 | #define ISA_RXDATA_16BIT_2_DATA_MASK 0x0000FF00 | ||
| 358 | #define ISA_RXDATA_16BIT_3_DATA_MASK 0x00FF0000 | ||
| 359 | #define ISA_RXDATA_16BIT_4_DATA_MASK 0xFF000000 | ||
| 360 | #define ISA_RXDATA_32BIT_1_DATA_MASK 0x00FFFFFF | ||
| 361 | |||
| 362 | #define LCD_SPU_DBG_ISA (0x0148) /* TTC */ | ||
| 363 | #define LCD_SPU_DMAVLD_YC (0x014C) | ||
| 364 | #define LCD_SPU_DMAVLD_UV (0x0150) | ||
| 365 | #define LCD_SPU_DMAVLD_UVSPU_GRAVLD (0x0154) | ||
| 366 | |||
| 367 | #define LCD_READ_IOPAD (0x0148) /* MMP2*/ | ||
| 368 | #define LCD_DMAVLD_YC (0x014C) | ||
| 369 | #define LCD_DMAVLD_UV (0x0150) | ||
| 370 | #define LCD_TVGGRAVLD_HLEN (0x0154) | ||
| 371 | |||
| 372 | /* HWC SRAM Read Data Register */ | ||
| 373 | #define LCD_SPU_HWC_RDDAT 0x0158 | ||
| 374 | |||
| 375 | /* Gamma Table SRAM Read Data Register */ | ||
| 376 | #define LCD_SPU_GAMMA_RDDAT 0x015c | ||
| 377 | #define CFG_GAMMA_RDDAT_MASK 0x000000FF | ||
| 378 | |||
| 379 | /* Palette Table SRAM Read Data Register */ | ||
| 380 | #define LCD_SPU_PALETTE_RDDAT 0x0160 | ||
| 381 | #define CFG_PALETTE_RDDAT_MASK 0x00FFFFFF | ||
| 382 | |||
| 383 | #define LCD_SPU_DBG_DMATOP (0x0164) /* TTC */ | ||
| 384 | #define LCD_SPU_DBG_GRATOP (0x0168) | ||
| 385 | #define LCD_SPU_DBG_TXCTRL (0x016C) | ||
| 386 | #define LCD_SPU_DBG_SLVTOP (0x0170) | ||
| 387 | #define LCD_SPU_DBG_MUXTOP (0x0174) | ||
| 388 | |||
| 389 | #define LCD_SLV_DBG (0x0164) /* MMP2 */ | ||
| 390 | #define LCD_TVDVLD_YC (0x0168) | ||
| 391 | #define LCD_TVDVLD_UV (0x016C) | ||
| 392 | #define LCD_TVC_RDDAT (0x0170) | ||
| 393 | #define LCD_TV_GAMMA_RDDAT (0x0174) | ||
| 394 | |||
| 395 | /* I/O Pads Input Read Only Register */ | ||
| 396 | #define LCD_SPU_IOPAD_IN 0x0178 | ||
| 397 | #define CFG_IOPAD_IN_MASK 0x0FFFFFFF | ||
| 398 | |||
| 399 | #define LCD_TV_PALETTE_RDDAT (0x0178) /* MMP2 */ | ||
| 400 | |||
| 401 | /* Reserved Read Only Registers */ | ||
| 402 | #define LCD_CFG_RDREG5F 0x017C | ||
| 403 | #define IRE_FRAME_CNT_MASK 0x000000C0 | ||
| 404 | #define IPE_FRAME_CNT_MASK 0x00000030 | ||
| 405 | #define GRA_FRAME_CNT_MASK 0x0000000C /* Graphic */ | ||
| 406 | #define DMA_FRAME_CNT_MASK 0x00000003 /* Video */ | ||
| 407 | |||
| 408 | #define LCD_FRAME_CNT (0x017C) /* MMP2 */ | ||
| 409 | |||
| 410 | /* SPI Control Register. */ | ||
| 411 | #define LCD_SPU_SPI_CTRL 0x0180 | ||
| 412 | #define CFG_SCLKCNT(div) ((div)<<24) /* 0xFF~0x2 */ | ||
| 413 | #define CFG_SCLKCNT_MASK 0xFF000000 | ||
| 414 | #define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */ | ||
| 415 | #define CFG_RXBITS_MASK 0x00FF0000 | ||
| 416 | #define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */ | ||
| 417 | #define CFG_TXBITS_MASK 0x0000FF00 | ||
| 418 | #define CFG_CLKINV(clk) ((clk)<<7) | ||
| 419 | #define CFG_CLKINV_MASK 0x00000080 | ||
| 420 | #define CFG_KEEPXFER(transfer) ((transfer)<<6) | ||
| 421 | #define CFG_KEEPXFER_MASK 0x00000040 | ||
| 422 | #define CFG_RXBITSTO0(rx) ((rx)<<5) | ||
| 423 | #define CFG_RXBITSTO0_MASK 0x00000020 | ||
| 424 | #define CFG_TXBITSTO0(tx) ((tx)<<4) | ||
| 425 | #define CFG_TXBITSTO0_MASK 0x00000010 | ||
| 426 | #define CFG_SPI_ENA(spi) ((spi)<<3) | ||
| 427 | #define CFG_SPI_ENA_MASK 0x00000008 | ||
| 428 | #define CFG_SPI_SEL(spi) ((spi)<<2) | ||
| 429 | #define CFG_SPI_SEL_MASK 0x00000004 | ||
| 430 | #define CFG_SPI_3W4WB(wire) ((wire)<<1) | ||
| 431 | #define CFG_SPI_3W4WB_MASK 0x00000002 | ||
| 432 | #define CFG_SPI_START(start) (start) | ||
| 433 | #define CFG_SPI_START_MASK 0x00000001 | ||
| 434 | |||
| 435 | /* SPI Tx Data Register */ | ||
| 436 | #define LCD_SPU_SPI_TXDATA 0x0184 | ||
| 437 | |||
| 438 | /* | ||
| 439 | 1. Smart Pannel 8-bit Bus Control Register. | ||
| 440 | 2. AHB Slave Path Data Port Register | ||
| 441 | */ | ||
| 442 | #define LCD_SPU_SMPN_CTRL 0x0188 | ||
| 443 | |||
| 444 | /* DMA Control 0 Register */ | ||
| 445 | #define LCD_SPU_DMA_CTRL0 0x0190 | ||
| 446 | #define CFG_NOBLENDING(nb) ((nb)<<31) | ||
| 447 | #define CFG_NOBLENDING_MASK 0x80000000 | ||
| 448 | #define CFG_GAMMA_ENA(gn) ((gn)<<30) | ||
| 449 | #define CFG_GAMMA_ENA_MASK 0x40000000 | ||
| 450 | #define CFG_CBSH_ENA(cn) ((cn)<<29) | ||
| 451 | #define CFG_CBSH_ENA_MASK 0x20000000 | ||
| 452 | #define CFG_PALETTE_ENA(pn) ((pn)<<28) | ||
| 453 | #define CFG_PALETTE_ENA_MASK 0x10000000 | ||
| 454 | #define CFG_ARBFAST_ENA(an) ((an)<<27) | ||
| 455 | #define CFG_ARBFAST_ENA_MASK 0x08000000 | ||
| 456 | #define CFG_HWC_1BITMOD(mode) ((mode)<<26) | ||
| 457 | #define CFG_HWC_1BITMOD_MASK 0x04000000 | ||
| 458 | #define CFG_HWC_1BITENA(mn) ((mn)<<25) | ||
| 459 | #define CFG_HWC_1BITENA_MASK 0x02000000 | ||
| 460 | #define CFG_HWC_ENA(cn) ((cn)<<24) | ||
| 461 | #define CFG_HWC_ENA_MASK 0x01000000 | ||
| 462 | #define CFG_DMAFORMAT(dmaformat) ((dmaformat)<<20) | ||
| 463 | #define CFG_DMAFORMAT_MASK 0x00F00000 | ||
| 464 | #define CFG_GRAFORMAT(graformat) ((graformat)<<16) | ||
| 465 | #define CFG_GRAFORMAT_MASK 0x000F0000 | ||
| 466 | /* for graphic part */ | ||
| 467 | #define CFG_GRA_FTOGGLE(toggle) ((toggle)<<15) | ||
| 468 | #define CFG_GRA_FTOGGLE_MASK 0x00008000 | ||
| 469 | #define CFG_GRA_HSMOOTH(smooth) ((smooth)<<14) | ||
| 470 | #define CFG_GRA_HSMOOTH_MASK 0x00004000 | ||
| 471 | #define CFG_GRA_TSTMODE(test) ((test)<<13) | ||
| 472 | #define CFG_GRA_TSTMODE_MASK 0x00002000 | ||
| 473 | #define CFG_GRA_SWAPRB(swap) ((swap)<<12) | ||
| 474 | #define CFG_GRA_SWAPRB_MASK 0x00001000 | ||
| 475 | #define CFG_GRA_SWAPUV(swap) ((swap)<<11) | ||
| 476 | #define CFG_GRA_SWAPUV_MASK 0x00000800 | ||
| 477 | #define CFG_GRA_SWAPYU(swap) ((swap)<<10) | ||
| 478 | #define CFG_GRA_SWAPYU_MASK 0x00000400 | ||
| 479 | #define CFG_GRA_SWAP_MASK 0x00001C00 | ||
| 480 | #define CFG_YUV2RGB_GRA(cvrt) ((cvrt)<<9) | ||
| 481 | #define CFG_YUV2RGB_GRA_MASK 0x00000200 | ||
| 482 | #define CFG_GRA_ENA(gra) ((gra)<<8) | ||
| 483 | #define CFG_GRA_ENA_MASK 0x00000100 | ||
| 484 | #define dma0_gfx_masks (CFG_GRAFORMAT_MASK | CFG_GRA_FTOGGLE_MASK | \ | ||
| 485 | CFG_GRA_HSMOOTH_MASK | CFG_GRA_TSTMODE_MASK | CFG_GRA_SWAP_MASK | \ | ||
| 486 | CFG_YUV2RGB_GRA_MASK | CFG_GRA_ENA_MASK) | ||
| 487 | /* for video part */ | ||
| 488 | #define CFG_DMA_FTOGGLE(toggle) ((toggle)<<7) | ||
| 489 | #define CFG_DMA_FTOGGLE_MASK 0x00000080 | ||
| 490 | #define CFG_DMA_HSMOOTH(smooth) ((smooth)<<6) | ||
| 491 | #define CFG_DMA_HSMOOTH_MASK 0x00000040 | ||
| 492 | #define CFG_DMA_TSTMODE(test) ((test)<<5) | ||
| 493 | #define CFG_DMA_TSTMODE_MASK 0x00000020 | ||
| 494 | #define CFG_DMA_SWAPRB(swap) ((swap)<<4) | ||
| 495 | #define CFG_DMA_SWAPRB_MASK 0x00000010 | ||
| 496 | #define CFG_DMA_SWAPUV(swap) ((swap)<<3) | ||
| 497 | #define CFG_DMA_SWAPUV_MASK 0x00000008 | ||
| 498 | #define CFG_DMA_SWAPYU(swap) ((swap)<<2) | ||
| 499 | #define CFG_DMA_SWAPYU_MASK 0x00000004 | ||
| 500 | #define CFG_DMA_SWAP_MASK 0x0000001C | ||
| 501 | #define CFG_YUV2RGB_DMA(cvrt) ((cvrt)<<1) | ||
| 502 | #define CFG_YUV2RGB_DMA_MASK 0x00000002 | ||
| 503 | #define CFG_DMA_ENA(video) (video) | ||
| 504 | #define CFG_DMA_ENA_MASK 0x00000001 | ||
| 505 | #define dma0_vid_masks (CFG_DMAFORMAT_MASK | CFG_DMA_FTOGGLE_MASK | \ | ||
| 506 | CFG_DMA_HSMOOTH_MASK | CFG_DMA_TSTMODE_MASK | CFG_DMA_SWAP_MASK | \ | ||
| 507 | CFG_YUV2RGB_DMA_MASK | CFG_DMA_ENA_MASK) | ||
| 508 | #define dma_palette(val) ((val ? 1 : 0) << 28) | ||
| 509 | #define dma_fmt(vid, val) ((val & 0xf) << ((vid) ? 20 : 16)) | ||
| 510 | #define dma_swaprb(vid, val) ((val ? 1 : 0) << ((vid) ? 4 : 12)) | ||
| 511 | #define dma_swapuv(vid, val) ((val ? 1 : 0) << ((vid) ? 3 : 11)) | ||
| 512 | #define dma_swapyuv(vid, val) ((val ? 1 : 0) << ((vid) ? 2 : 10)) | ||
| 513 | #define dma_csc(vid, val) ((val ? 1 : 0) << ((vid) ? 1 : 9)) | ||
| 514 | #define dma_hsmooth(vid, val) ((val ? 1 : 0) << ((vid) ? 6 : 14)) | ||
| 515 | #define dma_mask(vid) (dma_palette(1) | dma_fmt(vid, 0xf) | dma_csc(vid, 1) \ | ||
| 516 | | dma_swaprb(vid, 1) | dma_swapuv(vid, 1) | dma_swapyuv(vid, 1)) | ||
| 517 | |||
| 518 | /* DMA Control 1 Register */ | ||
| 519 | #define LCD_SPU_DMA_CTRL1 0x0194 | ||
| 520 | #define CFG_FRAME_TRIG(trig) ((trig)<<31) | ||
| 521 | #define CFG_FRAME_TRIG_MASK 0x80000000 | ||
| 522 | #define CFG_VSYNC_TRIG(trig) ((trig)<<28) | ||
| 523 | #define CFG_VSYNC_TRIG_MASK 0x70000000 | ||
| 524 | #define CFG_VSYNC_INV(inv) ((inv)<<27) | ||
| 525 | #define CFG_VSYNC_INV_MASK 0x08000000 | ||
| 526 | #define CFG_COLOR_KEY_MODE(cmode) ((cmode)<<24) | ||
| 527 | #define CFG_COLOR_KEY_MASK 0x07000000 | ||
| 528 | #define CFG_CARRY(carry) ((carry)<<23) | ||
| 529 | #define CFG_CARRY_MASK 0x00800000 | ||
| 530 | #define CFG_LNBUF_ENA(lnbuf) ((lnbuf)<<22) | ||
| 531 | #define CFG_LNBUF_ENA_MASK 0x00400000 | ||
| 532 | #define CFG_GATED_ENA(gated) ((gated)<<21) | ||
| 533 | #define CFG_GATED_ENA_MASK 0x00200000 | ||
| 534 | #define CFG_PWRDN_ENA(power) ((power)<<20) | ||
| 535 | #define CFG_PWRDN_ENA_MASK 0x00100000 | ||
| 536 | #define CFG_DSCALE(dscale) ((dscale)<<18) | ||
| 537 | #define CFG_DSCALE_MASK 0x000C0000 | ||
| 538 | #define CFG_ALPHA_MODE(amode) ((amode)<<16) | ||
| 539 | #define CFG_ALPHA_MODE_MASK 0x00030000 | ||
| 540 | #define CFG_ALPHA(alpha) ((alpha)<<8) | ||
| 541 | #define CFG_ALPHA_MASK 0x0000FF00 | ||
| 542 | #define CFG_PXLCMD(pxlcmd) (pxlcmd) | ||
| 543 | #define CFG_PXLCMD_MASK 0x000000FF | ||
| 544 | |||
| 545 | /* SRAM Control Register */ | ||
| 546 | #define LCD_SPU_SRAM_CTRL 0x0198 | ||
| 547 | #define CFG_SRAM_INIT_WR_RD(mode) ((mode)<<14) | ||
| 548 | #define CFG_SRAM_INIT_WR_RD_MASK 0x0000C000 | ||
| 549 | #define CFG_SRAM_ADDR_LCDID(id) ((id)<<8) | ||
| 550 | #define CFG_SRAM_ADDR_LCDID_MASK 0x00000F00 | ||
| 551 | #define CFG_SRAM_ADDR(addr) (addr) | ||
| 552 | #define CFG_SRAM_ADDR_MASK 0x000000FF | ||
| 553 | |||
| 554 | /* SRAM Write Data Register */ | ||
| 555 | #define LCD_SPU_SRAM_WRDAT 0x019C | ||
| 556 | |||
| 557 | /* SRAM RTC/WTC Control Register */ | ||
| 558 | #define LCD_SPU_SRAM_PARA0 0x01A0 | ||
| 559 | |||
| 560 | /* SRAM Power Down Control Register */ | ||
| 561 | #define LCD_SPU_SRAM_PARA1 0x01A4 | ||
| 562 | #define CFG_CSB_256x32(hwc) ((hwc)<<15) /* HWC */ | ||
| 563 | #define CFG_CSB_256x32_MASK 0x00008000 | ||
| 564 | #define CFG_CSB_256x24(palette) ((palette)<<14) /* Palette */ | ||
| 565 | #define CFG_CSB_256x24_MASK 0x00004000 | ||
| 566 | #define CFG_CSB_256x8(gamma) ((gamma)<<13) /* Gamma */ | ||
| 567 | #define CFG_CSB_256x8_MASK 0x00002000 | ||
| 568 | #define CFG_PDWN256x32(pdwn) ((pdwn)<<7) /* HWC */ | ||
| 569 | #define CFG_PDWN256x32_MASK 0x00000080 | ||
| 570 | #define CFG_PDWN256x24(pdwn) ((pdwn)<<6) /* Palette */ | ||
| 571 | #define CFG_PDWN256x24_MASK 0x00000040 | ||
| 572 | #define CFG_PDWN256x8(pdwn) ((pdwn)<<5) /* Gamma */ | ||
| 573 | #define CFG_PDWN256x8_MASK 0x00000020 | ||
| 574 | #define CFG_PDWN32x32(pdwn) ((pdwn)<<3) | ||
| 575 | #define CFG_PDWN32x32_MASK 0x00000008 | ||
| 576 | #define CFG_PDWN16x66(pdwn) ((pdwn)<<2) | ||
| 577 | #define CFG_PDWN16x66_MASK 0x00000004 | ||
| 578 | #define CFG_PDWN32x66(pdwn) ((pdwn)<<1) | ||
| 579 | #define CFG_PDWN32x66_MASK 0x00000002 | ||
| 580 | #define CFG_PDWN64x66(pdwn) (pdwn) | ||
| 581 | #define CFG_PDWN64x66_MASK 0x00000001 | ||
| 582 | |||
| 583 | /* Smart or Dumb Panel Clock Divider */ | ||
| 584 | #define LCD_CFG_SCLK_DIV 0x01A8 | ||
| 585 | #define SCLK_SRC_SEL(src) ((src)<<31) | ||
| 586 | #define SCLK_SRC_SEL_MASK 0x80000000 | ||
| 587 | #define SCLK_DISABLE (1<<28) | ||
| 588 | #define CLK_FRACDIV(frac) ((frac)<<16) | ||
| 589 | #define CLK_FRACDIV_MASK 0x0FFF0000 | ||
| 590 | #define DSI1_BITCLK_DIV(div) (div<<8) | ||
| 591 | #define DSI1_BITCLK_DIV_MASK 0x00000F00 | ||
| 592 | #define CLK_INT_DIV(div) (div) | ||
| 593 | #define CLK_INT_DIV_MASK 0x000000FF | ||
| 594 | |||
| 595 | /* Video Contrast Register */ | ||
| 596 | #define LCD_SPU_CONTRAST 0x01AC | ||
| 597 | #define CFG_BRIGHTNESS(bright) ((bright)<<16) | ||
| 598 | #define CFG_BRIGHTNESS_MASK 0xFFFF0000 | ||
| 599 | #define CFG_CONTRAST(contrast) (contrast) | ||
| 600 | #define CFG_CONTRAST_MASK 0x0000FFFF | ||
| 601 | |||
| 602 | /* Video Saturation Register */ | ||
| 603 | #define LCD_SPU_SATURATION 0x01B0 | ||
| 604 | #define CFG_C_MULTS(mult) ((mult)<<16) | ||
| 605 | #define CFG_C_MULTS_MASK 0xFFFF0000 | ||
| 606 | #define CFG_SATURATION(sat) (sat) | ||
| 607 | #define CFG_SATURATION_MASK 0x0000FFFF | ||
| 608 | |||
| 609 | /* Video Hue Adjust Register */ | ||
| 610 | #define LCD_SPU_CBSH_HUE 0x01B4 | ||
| 611 | #define CFG_SIN0(sin0) ((sin0)<<16) | ||
| 612 | #define CFG_SIN0_MASK 0xFFFF0000 | ||
| 613 | #define CFG_COS0(con0) (con0) | ||
| 614 | #define CFG_COS0_MASK 0x0000FFFF | ||
| 615 | |||
| 616 | /* Dump LCD Panel Control Register */ | ||
| 617 | #define LCD_SPU_DUMB_CTRL 0x01B8 | ||
| 618 | #define CFG_DUMBMODE(mode) ((mode)<<28) | ||
| 619 | #define CFG_DUMBMODE_MASK 0xF0000000 | ||
| 620 | #define CFG_INTFRBSWAP(mode) ((mode)<<24) | ||
| 621 | #define CFG_INTFRBSWAP_MASK 0x0F000000 | ||
| 622 | #define CFG_LCDGPIO_O(data) ((data)<<20) | ||
| 623 | #define CFG_LCDGPIO_O_MASK 0x0FF00000 | ||
| 624 | #define CFG_LCDGPIO_ENA(gpio) ((gpio)<<12) | ||
| 625 | #define CFG_LCDGPIO_ENA_MASK 0x000FF000 | ||
| 626 | #define CFG_BIAS_OUT(bias) ((bias)<<8) | ||
| 627 | #define CFG_BIAS_OUT_MASK 0x00000100 | ||
| 628 | #define CFG_REVERSE_RGB(RGB) ((RGB)<<7) | ||
| 629 | #define CFG_REVERSE_RGB_MASK 0x00000080 | ||
| 630 | #define CFG_INV_COMPBLANK(blank) ((blank)<<6) | ||
| 631 | #define CFG_INV_COMPBLANK_MASK 0x00000040 | ||
| 632 | #define CFG_INV_COMPSYNC(sync) ((sync)<<5) | ||
| 633 | #define CFG_INV_COMPSYNC_MASK 0x00000020 | ||
| 634 | #define CFG_INV_HENA(hena) ((hena)<<4) | ||
| 635 | #define CFG_INV_HENA_MASK 0x00000010 | ||
| 636 | #define CFG_INV_VSYNC(vsync) ((vsync)<<3) | ||
| 637 | #define CFG_INV_VSYNC_MASK 0x00000008 | ||
| 638 | #define CFG_INV_HSYNC(hsync) ((hsync)<<2) | ||
| 639 | #define CFG_INV_HSYNC_MASK 0x00000004 | ||
| 640 | #define CFG_INV_PCLK(pclk) ((pclk)<<1) | ||
| 641 | #define CFG_INV_PCLK_MASK 0x00000002 | ||
| 642 | #define CFG_DUMB_ENA(dumb) (dumb) | ||
| 643 | #define CFG_DUMB_ENA_MASK 0x00000001 | ||
| 644 | |||
| 645 | /* LCD I/O Pads Control Register */ | ||
| 646 | #define SPU_IOPAD_CONTROL 0x01BC | ||
| 647 | #define CFG_GRA_VM_ENA(vm) ((vm)<<15) | ||
| 648 | #define CFG_GRA_VM_ENA_MASK 0x00008000 | ||
| 649 | #define CFG_DMA_VM_ENA(vm) ((vm)<<13) | ||
| 650 | #define CFG_DMA_VM_ENA_MASK 0x00002000 | ||
| 651 | #define CFG_CMD_VM_ENA(vm) ((vm)<<12) | ||
| 652 | #define CFG_CMD_VM_ENA_MASK 0x00001000 | ||
| 653 | #define CFG_CSC(csc) ((csc)<<8) | ||
| 654 | #define CFG_CSC_MASK 0x00000300 | ||
| 655 | #define CFG_BOUNDARY(size) ((size)<<5) | ||
| 656 | #define CFG_BOUNDARY_MASK 0x00000020 | ||
| 657 | #define CFG_BURST(len) ((len)<<4) | ||
| 658 | #define CFG_BURST_MASK 0x00000010 | ||
| 659 | #define CFG_IOPADMODE(iopad) (iopad) | ||
| 660 | #define CFG_IOPADMODE_MASK 0x0000000F | ||
| 661 | |||
| 662 | /* LCD Interrupt Control Register */ | ||
| 663 | #define SPU_IRQ_ENA 0x01C0 | ||
| 664 | #define DMA_FRAME_IRQ0_ENA(irq) ((irq)<<31) | ||
| 665 | #define DMA_FRAME_IRQ0_ENA_MASK 0x80000000 | ||
| 666 | #define DMA_FRAME_IRQ1_ENA(irq) ((irq)<<30) | ||
| 667 | #define DMA_FRAME_IRQ1_ENA_MASK 0x40000000 | ||
| 668 | #define DMA_FF_UNDERFLOW_ENA(ff) ((ff)<<29) | ||
| 669 | #define DMA_FF_UNDERFLOW_ENA_MASK 0x20000000 | ||
| 670 | #define AXI_BUS_ERROR_IRQ_ENA(irq) ((irq)<<28) | ||
| 671 | #define AXI_BUS_ERROR_IRQ_ENA_MASK 0x10000000 | ||
| 672 | #define GRA_FRAME_IRQ0_ENA(irq) ((irq)<<27) | ||
| 673 | #define GRA_FRAME_IRQ0_ENA_MASK 0x08000000 | ||
| 674 | #define GRA_FRAME_IRQ1_ENA(irq) ((irq)<<26) | ||
| 675 | #define GRA_FRAME_IRQ1_ENA_MASK 0x04000000 | ||
| 676 | #define GRA_FF_UNDERFLOW_ENA(ff) ((ff)<<25) | ||
| 677 | #define GRA_FF_UNDERFLOW_ENA_MASK 0x02000000 | ||
| 678 | #define VSYNC_IRQ_ENA(vsync_irq) ((vsync_irq)<<23) | ||
| 679 | #define VSYNC_IRQ_ENA_MASK 0x00800000 | ||
| 680 | #define DUMB_FRAMEDONE_ENA(fdone) ((fdone)<<22) | ||
| 681 | #define DUMB_FRAMEDONE_ENA_MASK 0x00400000 | ||
| 682 | #define TWC_FRAMEDONE_ENA(fdone) ((fdone)<<21) | ||
| 683 | #define TWC_FRAMEDONE_ENA_MASK 0x00200000 | ||
| 684 | #define HWC_FRAMEDONE_ENA(fdone) ((fdone)<<20) | ||
| 685 | #define HWC_FRAMEDONE_ENA_MASK 0x00100000 | ||
| 686 | #define SLV_IRQ_ENA(irq) ((irq)<<19) | ||
| 687 | #define SLV_IRQ_ENA_MASK 0x00080000 | ||
| 688 | #define SPI_IRQ_ENA(irq) ((irq)<<18) | ||
| 689 | #define SPI_IRQ_ENA_MASK 0x00040000 | ||
| 690 | #define PWRDN_IRQ_ENA(irq) ((irq)<<17) | ||
| 691 | #define PWRDN_IRQ_ENA_MASK 0x00020000 | ||
| 692 | #define AXI_LATENCY_TOO_LONG_IRQ_ENA(irq) ((irq)<<16) | ||
| 693 | #define AXI_LATENCY_TOO_LONG_IRQ_ENA_MASK 0x00010000 | ||
| 694 | #define CLEAN_SPU_IRQ_ISR(irq) (irq) | ||
| 695 | #define CLEAN_SPU_IRQ_ISR_MASK 0x0000FFFF | ||
| 696 | #define TV_DMA_FRAME_IRQ0_ENA(irq) ((irq)<<15) | ||
| 697 | #define TV_DMA_FRAME_IRQ0_ENA_MASK 0x00008000 | ||
| 698 | #define TV_DMA_FRAME_IRQ1_ENA(irq) ((irq)<<14) | ||
| 699 | #define TV_DMA_FRAME_IRQ1_ENA_MASK 0x00004000 | ||
| 700 | #define TV_DMA_FF_UNDERFLOW_ENA(unerrun) ((unerrun)<<13) | ||
| 701 | #define TV_DMA_FF_UNDERFLOW_ENA_MASK 0x00002000 | ||
| 702 | #define TVSYNC_IRQ_ENA(irq) ((irq)<<12) | ||
| 703 | #define TVSYNC_IRQ_ENA_MASK 0x00001000 | ||
| 704 | #define TV_FRAME_IRQ0_ENA(irq) ((irq)<<11) | ||
| 705 | #define TV_FRAME_IRQ0_ENA_MASK 0x00000800 | ||
| 706 | #define TV_FRAME_IRQ1_ENA(irq) ((irq)<<10) | ||
| 707 | #define TV_FRAME_IRQ1_ENA_MASK 0x00000400 | ||
| 708 | #define TV_GRA_FF_UNDERFLOW_ENA(unerrun) ((unerrun)<<9) | ||
| 709 | #define TV_GRA_FF_UNDERFLOW_ENA_MASK 0x00000200 | ||
| 710 | #define TV_FRAMEDONE_ENA(irq) ((irq)<<8) | ||
| 711 | #define TV_FRAMEDONE_ENA_MASK 0x00000100 | ||
| 712 | |||
| 713 | /* FIXME - JUST GUESS */ | ||
| 714 | #define PN2_DMA_FRAME_IRQ0_ENA(irq) ((irq)<<7) | ||
| 715 | #define PN2_DMA_FRAME_IRQ0_ENA_MASK 0x00000080 | ||
| 716 | #define PN2_DMA_FRAME_IRQ1_ENA(irq) ((irq)<<6) | ||
| 717 | #define PN2_DMA_FRAME_IRQ1_ENA_MASK 0x00000040 | ||
| 718 | #define PN2_DMA_FF_UNDERFLOW_ENA(ff) ((ff)<<5) | ||
| 719 | #define PN2_DMA_FF_UNDERFLOW_ENA_MASK 0x00000020 | ||
| 720 | #define PN2_GRA_FRAME_IRQ0_ENA(irq) ((irq)<<3) | ||
| 721 | #define PN2_GRA_FRAME_IRQ0_ENA_MASK 0x00000008 | ||
| 722 | #define PN2_GRA_FRAME_IRQ1_ENA(irq) ((irq)<<2) | ||
| 723 | #define PN2_GRA_FRAME_IRQ1_ENA_MASK 0x04000004 | ||
| 724 | #define PN2_GRA_FF_UNDERFLOW_ENA(ff) ((ff)<<1) | ||
| 725 | #define PN2_GRA_FF_UNDERFLOW_ENA_MASK 0x00000002 | ||
| 726 | #define PN2_VSYNC_IRQ_ENA(irq) ((irq)<<0) | ||
| 727 | #define PN2_SYNC_IRQ_ENA_MASK 0x00000001 | ||
| 728 | |||
| 729 | #define gf0_imask(id) ((id) ? (((id) & 1) ? TV_FRAME_IRQ0_ENA_MASK \ | ||
| 730 | : PN2_GRA_FRAME_IRQ0_ENA_MASK) : GRA_FRAME_IRQ0_ENA_MASK) | ||
| 731 | #define gf1_imask(id) ((id) ? (((id) & 1) ? TV_FRAME_IRQ1_ENA_MASK \ | ||
| 732 | : PN2_GRA_FRAME_IRQ1_ENA_MASK) : GRA_FRAME_IRQ1_ENA_MASK) | ||
| 733 | #define vsync_imask(id) ((id) ? (((id) & 1) ? TVSYNC_IRQ_ENA_MASK \ | ||
| 734 | : PN2_SYNC_IRQ_ENA_MASK) : VSYNC_IRQ_ENA_MASK) | ||
| 735 | #define vsync_imasks (vsync_imask(0) | vsync_imask(1)) | ||
| 736 | |||
| 737 | #define display_done_imask(id) ((id) ? (((id) & 1) ? TV_FRAMEDONE_ENA_MASK\ | ||
| 738 | : (PN2_DMA_FRAME_IRQ0_ENA_MASK | PN2_DMA_FRAME_IRQ1_ENA_MASK))\ | ||
| 739 | : DUMB_FRAMEDONE_ENA_MASK) | ||
| 740 | |||
| 741 | #define display_done_imasks (display_done_imask(0) | display_done_imask(1)) | ||
| 742 | |||
| 743 | #define vf0_imask(id) ((id) ? (((id) & 1) ? TV_DMA_FRAME_IRQ0_ENA_MASK \ | ||
| 744 | : PN2_DMA_FRAME_IRQ0_ENA_MASK) : DMA_FRAME_IRQ0_ENA_MASK) | ||
| 745 | #define vf1_imask(id) ((id) ? (((id) & 1) ? TV_DMA_FRAME_IRQ1_ENA_MASK \ | ||
| 746 | : PN2_DMA_FRAME_IRQ1_ENA_MASK) : DMA_FRAME_IRQ1_ENA_MASK) | ||
| 747 | |||
| 748 | #define gfx_imasks (gf0_imask(0) | gf1_imask(0) | gf0_imask(1) | \ | ||
| 749 | gf1_imask(1)) | ||
| 750 | #define vid_imasks (vf0_imask(0) | vf1_imask(0) | vf0_imask(1) | \ | ||
| 751 | vf1_imask(1)) | ||
| 752 | #define vid_imask(id) (display_done_imask(id)) | ||
| 753 | |||
| 754 | #define pn1_imasks (gf0_imask(0) | gf1_imask(0) | vsync_imask(0) | \ | ||
| 755 | display_done_imask(0) | vf0_imask(0) | vf1_imask(0)) | ||
| 756 | #define tv_imasks (gf0_imask(1) | gf1_imask(1) | vsync_imask(1) | \ | ||
| 757 | display_done_imask(1) | vf0_imask(1) | vf1_imask(1)) | ||
| 758 | #define path_imasks(id) ((id) ? (tv_imasks) : (pn1_imasks)) | ||
| 759 | |||
| 760 | /* error indications */ | ||
| 761 | #define vid_udflow_imask(id) ((id) ? (((id) & 1) ? \ | ||
| 762 | (TV_DMA_FF_UNDERFLOW_ENA_MASK) : (PN2_DMA_FF_UNDERFLOW_ENA_MASK)) : \ | ||
| 763 | (DMA_FF_UNDERFLOW_ENA_MASK)) | ||
| 764 | #define gfx_udflow_imask(id) ((id) ? (((id) & 1) ? \ | ||
| 765 | (TV_GRA_FF_UNDERFLOW_ENA_MASK) : (PN2_GRA_FF_UNDERFLOW_ENA_MASK)) : \ | ||
| 766 | (GRA_FF_UNDERFLOW_ENA_MASK)) | ||
| 767 | |||
| 768 | #define err_imask(id) (vid_udflow_imask(id) | gfx_udflow_imask(id) | \ | ||
| 769 | AXI_BUS_ERROR_IRQ_ENA_MASK | AXI_LATENCY_TOO_LONG_IRQ_ENA_MASK) | ||
| 770 | #define err_imasks (err_imask(0) | err_imask(1) | err_imask(2)) | ||
| 771 | /* LCD Interrupt Status Register */ | ||
| 772 | #define SPU_IRQ_ISR 0x01C4 | ||
| 773 | #define DMA_FRAME_IRQ0(irq) ((irq)<<31) | ||
| 774 | #define DMA_FRAME_IRQ0_MASK 0x80000000 | ||
| 775 | #define DMA_FRAME_IRQ1(irq) ((irq)<<30) | ||
| 776 | #define DMA_FRAME_IRQ1_MASK 0x40000000 | ||
| 777 | #define DMA_FF_UNDERFLOW(ff) ((ff)<<29) | ||
| 778 | #define DMA_FF_UNDERFLOW_MASK 0x20000000 | ||
| 779 | #define AXI_BUS_ERROR_IRQ(irq) ((irq)<<28) | ||
| 780 | #define AXI_BUS_ERROR_IRQ_MASK 0x10000000 | ||
| 781 | #define GRA_FRAME_IRQ0(irq) ((irq)<<27) | ||
| 782 | #define GRA_FRAME_IRQ0_MASK 0x08000000 | ||
| 783 | #define GRA_FRAME_IRQ1(irq) ((irq)<<26) | ||
| 784 | #define GRA_FRAME_IRQ1_MASK 0x04000000 | ||
| 785 | #define GRA_FF_UNDERFLOW(ff) ((ff)<<25) | ||
| 786 | #define GRA_FF_UNDERFLOW_MASK 0x02000000 | ||
| 787 | #define VSYNC_IRQ(vsync_irq) ((vsync_irq)<<23) | ||
| 788 | #define VSYNC_IRQ_MASK 0x00800000 | ||
| 789 | #define DUMB_FRAMEDONE(fdone) ((fdone)<<22) | ||
| 790 | #define DUMB_FRAMEDONE_MASK 0x00400000 | ||
| 791 | #define TWC_FRAMEDONE(fdone) ((fdone)<<21) | ||
| 792 | #define TWC_FRAMEDONE_MASK 0x00200000 | ||
| 793 | #define HWC_FRAMEDONE(fdone) ((fdone)<<20) | ||
| 794 | #define HWC_FRAMEDONE_MASK 0x00100000 | ||
| 795 | #define SLV_IRQ(irq) ((irq)<<19) | ||
| 796 | #define SLV_IRQ_MASK 0x00080000 | ||
| 797 | #define SPI_IRQ(irq) ((irq)<<18) | ||
| 798 | #define SPI_IRQ_MASK 0x00040000 | ||
| 799 | #define PWRDN_IRQ(irq) ((irq)<<17) | ||
| 800 | #define PWRDN_IRQ_MASK 0x00020000 | ||
| 801 | #define AXI_LATENCY_TOO_LONGR_IRQ(irq) ((irq)<<16) | ||
| 802 | #define AXI_LATENCY_TOO_LONGR_IRQ_MASK 0x00010000 | ||
| 803 | #define TV_DMA_FRAME_IRQ0(irq) ((irq)<<15) | ||
| 804 | #define TV_DMA_FRAME_IRQ0_MASK 0x00008000 | ||
| 805 | #define TV_DMA_FRAME_IRQ1(irq) ((irq)<<14) | ||
| 806 | #define TV_DMA_FRAME_IRQ1_MASK 0x00004000 | ||
| 807 | #define TV_DMA_FF_UNDERFLOW(unerrun) ((unerrun)<<13) | ||
| 808 | #define TV_DMA_FF_UNDERFLOW_MASK 0x00002000 | ||
| 809 | #define TVSYNC_IRQ(irq) ((irq)<<12) | ||
| 810 | #define TVSYNC_IRQ_MASK 0x00001000 | ||
| 811 | #define TV_FRAME_IRQ0(irq) ((irq)<<11) | ||
| 812 | #define TV_FRAME_IRQ0_MASK 0x00000800 | ||
| 813 | #define TV_FRAME_IRQ1(irq) ((irq)<<10) | ||
| 814 | #define TV_FRAME_IRQ1_MASK 0x00000400 | ||
| 815 | #define TV_GRA_FF_UNDERFLOW(unerrun) ((unerrun)<<9) | ||
| 816 | #define TV_GRA_FF_UNDERFLOW_MASK 0x00000200 | ||
| 817 | #define PN2_DMA_FRAME_IRQ0(irq) ((irq)<<7) | ||
| 818 | #define PN2_DMA_FRAME_IRQ0_MASK 0x00000080 | ||
| 819 | #define PN2_DMA_FRAME_IRQ1(irq) ((irq)<<6) | ||
| 820 | #define PN2_DMA_FRAME_IRQ1_MASK 0x00000040 | ||
| 821 | #define PN2_DMA_FF_UNDERFLOW(ff) ((ff)<<5) | ||
| 822 | #define PN2_DMA_FF_UNDERFLOW_MASK 0x00000020 | ||
| 823 | #define PN2_GRA_FRAME_IRQ0(irq) ((irq)<<3) | ||
| 824 | #define PN2_GRA_FRAME_IRQ0_MASK 0x00000008 | ||
| 825 | #define PN2_GRA_FRAME_IRQ1(irq) ((irq)<<2) | ||
| 826 | #define PN2_GRA_FRAME_IRQ1_MASK 0x04000004 | ||
| 827 | #define PN2_GRA_FF_UNDERFLOW(ff) ((ff)<<1) | ||
| 828 | #define PN2_GRA_FF_UNDERFLOW_MASK 0x00000002 | ||
| 829 | #define PN2_VSYNC_IRQ(irq) ((irq)<<0) | ||
| 830 | #define PN2_SYNC_IRQ_MASK 0x00000001 | ||
| 831 | |||
| 832 | /* LCD FIFO Depth register */ | ||
| 833 | #define LCD_FIFO_DEPTH 0x01c8 | ||
| 834 | #define VIDEO_FIFO(fi) ((fi) << 0) | ||
| 835 | #define VIDEO_FIFO_MASK 0x00000003 | ||
| 836 | #define GRAPHIC_FIFO(fi) ((fi) << 2) | ||
| 837 | #define GRAPHIC_FIFO_MASK 0x0000000c | ||
| 838 | |||
| 839 | /* read-only */ | ||
| 840 | #define DMA_FRAME_IRQ0_LEVEL_MASK 0x00008000 | ||
| 841 | #define DMA_FRAME_IRQ1_LEVEL_MASK 0x00004000 | ||
| 842 | #define DMA_FRAME_CNT_ISR_MASK 0x00003000 | ||
| 843 | #define GRA_FRAME_IRQ0_LEVEL_MASK 0x00000800 | ||
| 844 | #define GRA_FRAME_IRQ1_LEVEL_MASK 0x00000400 | ||
| 845 | #define GRA_FRAME_CNT_ISR_MASK 0x00000300 | ||
| 846 | #define VSYNC_IRQ_LEVEL_MASK 0x00000080 | ||
| 847 | #define DUMB_FRAMEDONE_LEVEL_MASK 0x00000040 | ||
| 848 | #define TWC_FRAMEDONE_LEVEL_MASK 0x00000020 | ||
| 849 | #define HWC_FRAMEDONE_LEVEL_MASK 0x00000010 | ||
| 850 | #define SLV_FF_EMPTY_MASK 0x00000008 | ||
| 851 | #define DMA_FF_ALLEMPTY_MASK 0x00000004 | ||
| 852 | #define GRA_FF_ALLEMPTY_MASK 0x00000002 | ||
| 853 | #define PWRDN_IRQ_LEVEL_MASK 0x00000001 | ||
| 854 | |||
| 855 | /* 32 bit LCD Interrupt Reset Status*/ | ||
| 856 | #define SPU_IRQ_RSR (0x01C8) | ||
| 857 | /* 32 bit Panel Path Graphic Partial Display Horizontal Control Register*/ | ||
| 858 | #define LCD_GRA_CUTHPXL (0x01CC) | ||
| 859 | /* 32 bit Panel Path Graphic Partial Display Vertical Control Register*/ | ||
| 860 | #define LCD_GRA_CUTVLN (0x01D0) | ||
| 861 | /* 32 bit TV Path Graphic Partial Display Horizontal Control Register*/ | ||
| 862 | #define LCD_TVG_CUTHPXL (0x01D4) | ||
| 863 | /* 32 bit TV Path Graphic Partial Display Vertical Control Register*/ | ||
| 864 | #define LCD_TVG_CUTVLN (0x01D8) | ||
| 865 | /* 32 bit LCD Global Control Register*/ | ||
| 866 | #define LCD_TOP_CTRL (0x01DC) | ||
| 867 | /* 32 bit LCD SQU Line Buffer Control Register 1*/ | ||
| 868 | #define LCD_SQULN1_CTRL (0x01E0) | ||
| 869 | /* 32 bit LCD SQU Line Buffer Control Register 2*/ | ||
| 870 | #define LCD_SQULN2_CTRL (0x01E4) | ||
| 871 | #define squln_ctrl(id) ((id) ? (((id) & 1) ? LCD_SQULN2_CTRL : \ | ||
| 872 | LCD_PN2_SQULN1_CTRL) : LCD_SQULN1_CTRL) | ||
| 873 | |||
| 874 | /* 32 bit LCD Mixed Overlay Control Register */ | ||
| 875 | #define LCD_AFA_ALL2ONE (0x01E8) | ||
| 876 | |||
| 877 | #define LCD_PN2_SCLK_DIV (0x01EC) | ||
| 878 | #define LCD_PN2_TCLK_DIV (0x01F0) | ||
| 879 | #define LCD_LVDS_SCLK_DIV_WR (0x01F4) | ||
| 880 | #define LCD_LVDS_SCLK_DIV_RD (0x01FC) | ||
| 881 | #define PN2_LCD_DMA_START_ADDR_Y0 (0x0200) | ||
| 882 | #define PN2_LCD_DMA_START_ADDR_U0 (0x0204) | ||
| 883 | #define PN2_LCD_DMA_START_ADDR_V0 (0x0208) | ||
| 884 | #define PN2_LCD_DMA_START_ADDR_C0 (0x020C) | ||
| 885 | #define PN2_LCD_DMA_START_ADDR_Y1 (0x0210) | ||
| 886 | #define PN2_LCD_DMA_START_ADDR_U1 (0x0214) | ||
| 887 | #define PN2_LCD_DMA_START_ADDR_V1 (0x0218) | ||
| 888 | #define PN2_LCD_DMA_START_ADDR_C1 (0x021C) | ||
| 889 | #define PN2_LCD_DMA_PITCH_YC (0x0220) | ||
| 890 | #define PN2_LCD_DMA_PITCH_UV (0x0224) | ||
| 891 | #define PN2_LCD_DMA_OVSA_HPXL_VLN (0x0228) | ||
| 892 | #define PN2_LCD_DMA_HPXL_VLN (0x022C) | ||
| 893 | #define PN2_LCD_DMAZM_HPXL_VLN (0x0230) | ||
| 894 | #define PN2_LCD_GRA_START_ADDR0 (0x0234) | ||
| 895 | #define PN2_LCD_GRA_START_ADDR1 (0x0238) | ||
| 896 | #define PN2_LCD_GRA_PITCH (0x023C) | ||
| 897 | #define PN2_LCD_GRA_OVSA_HPXL_VLN (0x0240) | ||
| 898 | #define PN2_LCD_GRA_HPXL_VLN (0x0244) | ||
| 899 | #define PN2_LCD_GRAZM_HPXL_VLN (0x0248) | ||
| 900 | #define PN2_LCD_HWC_OVSA_HPXL_VLN (0x024C) | ||
| 901 | #define PN2_LCD_HWC_HPXL_VLN (0x0250) | ||
| 902 | #define LCD_PN2_V_H_TOTAL (0x0254) | ||
| 903 | #define LCD_PN2_V_H_ACTIVE (0x0258) | ||
| 904 | #define LCD_PN2_H_PORCH (0x025C) | ||
| 905 | #define LCD_PN2_V_PORCH (0x0260) | ||
| 906 | #define LCD_PN2_BLANKCOLOR (0x0264) | ||
| 907 | #define LCD_PN2_ALPHA_COLOR1 (0x0268) | ||
| 908 | #define LCD_PN2_ALPHA_COLOR2 (0x026C) | ||
| 909 | #define LCD_PN2_COLORKEY_Y (0x0270) | ||
| 910 | #define LCD_PN2_COLORKEY_U (0x0274) | ||
| 911 | #define LCD_PN2_COLORKEY_V (0x0278) | ||
| 912 | #define LCD_PN2_SEPXLCNT (0x027C) | ||
| 913 | #define LCD_TV_V_H_TOTAL_FLD (0x0280) | ||
| 914 | #define LCD_TV_V_PORCH_FLD (0x0284) | ||
| 915 | #define LCD_TV_SEPXLCNT_FLD (0x0288) | ||
| 916 | |||
| 917 | #define LCD_2ND_ALPHA (0x0294) | ||
| 918 | #define LCD_PN2_CONTRAST (0x0298) | ||
| 919 | #define LCD_PN2_SATURATION (0x029c) | ||
| 920 | #define LCD_PN2_CBSH_HUE (0x02a0) | ||
| 921 | #define LCD_TIMING_EXT (0x02C0) | ||
| 922 | #define LCD_PN2_LAYER_ALPHA_SEL1 (0x02c4) | ||
| 923 | #define LCD_PN2_CTRL0 (0x02C8) | ||
| 924 | #define TV_LAYER_ALPHA_SEL1 (0x02cc) | ||
| 925 | #define LCD_SMPN2_CTRL (0x02D0) | ||
| 926 | #define LCD_IO_OVERL_MAP_CTRL (0x02D4) | ||
| 927 | #define LCD_DUMB2_CTRL (0x02d8) | ||
| 928 | #define LCD_PN2_CTRL1 (0x02DC) | ||
| 929 | #define PN2_IOPAD_CONTROL (0x02E0) | ||
| 930 | #define LCD_PN2_SQULN1_CTRL (0x02E4) | ||
| 931 | #define PN2_LCD_GRA_CUTHPXL (0x02e8) | ||
| 932 | #define PN2_LCD_GRA_CUTVLN (0x02ec) | ||
| 933 | #define LCD_PN2_SQULN2_CTRL (0x02F0) | ||
| 934 | #define ALL_LAYER_ALPHA_SEL (0x02F4) | ||
| 935 | |||
| 936 | /* pxa988 has different MASTER_CTRL from MMP3/MMP2 */ | ||
| 937 | #ifdef CONFIG_CPU_PXA988 | ||
| 938 | #define TIMING_MASTER_CONTROL (0x01F4) | ||
| 939 | #define MASTER_ENH(id) (1 << ((id) + 5)) | ||
| 940 | #define MASTER_ENV(id) (1 << ((id) + 6)) | ||
| 941 | #else | ||
| 942 | #define TIMING_MASTER_CONTROL (0x02F8) | ||
| 943 | #define MASTER_ENH(id) (1 << (id)) | ||
| 944 | #define MASTER_ENV(id) (1 << ((id) + 4)) | ||
| 945 | #endif | ||
| 946 | |||
| 947 | #define DSI_START_SEL_SHIFT(id) (((id) << 1) + 8) | ||
| 948 | #define timing_master_config(path, dsi_id, lcd_id) \ | ||
| 949 | (MASTER_ENH(path) | MASTER_ENV(path) | \ | ||
| 950 | (((lcd_id) + ((dsi_id) << 1)) << DSI_START_SEL_SHIFT(path))) | ||
| 951 | |||
| 952 | #define LCD_2ND_BLD_CTL (0x02Fc) | ||
| 953 | #define LVDS_SRC_MASK (3 << 30) | ||
| 954 | #define LVDS_SRC_SHIFT (30) | ||
| 955 | #define LVDS_FMT_MASK (1 << 28) | ||
| 956 | #define LVDS_FMT_SHIFT (28) | ||
| 957 | |||
| 958 | #define CLK_SCLK (1 << 0) | ||
| 959 | #define CLK_LVDS_RD (1 << 1) | ||
| 960 | #define CLK_LVDS_WR (1 << 2) | ||
| 961 | |||
| 962 | #define gra_partdisp_ctrl_hor(id) ((id) ? (((id) & 1) ? \ | ||
| 963 | LCD_TVG_CUTHPXL : PN2_LCD_GRA_CUTHPXL) : LCD_GRA_CUTHPXL) | ||
| 964 | #define gra_partdisp_ctrl_ver(id) ((id) ? (((id) & 1) ? \ | ||
| 965 | LCD_TVG_CUTVLN : PN2_LCD_GRA_CUTVLN) : LCD_GRA_CUTVLN) | ||
| 966 | |||
| 967 | /* | ||
| 968 | * defined for Configure Dumb Mode | ||
| 969 | * defined for Configure Dumb Mode | ||
| 970 | * DUMB LCD Panel bit[31:28] | ||
| 971 | */ | ||
| 972 | #define DUMB16_RGB565_0 0x0 | ||
| 973 | #define DUMB16_RGB565_1 0x1 | ||
| 974 | #define DUMB18_RGB666_0 0x2 | ||
| 975 | #define DUMB18_RGB666_1 0x3 | ||
| 976 | #define DUMB12_RGB444_0 0x4 | ||
| 977 | #define DUMB12_RGB444_1 0x5 | ||
| 978 | #define DUMB24_RGB888_0 0x6 | ||
| 979 | #define DUMB_BLANK 0x7 | ||
| 980 | |||
| 981 | /* | ||
| 982 | * defined for Configure I/O Pin Allocation Mode | ||
| 983 | * LCD LCD I/O Pads control register bit[3:0] | ||
| 984 | */ | ||
| 985 | #define IOPAD_DUMB24 0x0 | ||
| 986 | #define IOPAD_DUMB18SPI 0x1 | ||
| 987 | #define IOPAD_DUMB18GPIO 0x2 | ||
| 988 | #define IOPAD_DUMB16SPI 0x3 | ||
| 989 | #define IOPAD_DUMB16GPIO 0x4 | ||
| 990 | #define IOPAD_DUMB12 0x5 | ||
| 991 | #define IOPAD_SMART18SPI 0x6 | ||
| 992 | #define IOPAD_SMART16SPI 0x7 | ||
| 993 | #define IOPAD_SMART8BOTH 0x8 | ||
| 994 | #define IOPAD_DUMB18_SMART8 0x9 | ||
| 995 | #define IOPAD_DUMB16_SMART8SPI 0xa | ||
| 996 | #define IOPAD_DUMB16_SMART8GPIO 0xb | ||
| 997 | #define IOPAD_DUMB16_DUMB16 0xc | ||
| 998 | #define IOPAD_SMART8_SMART8 0xc | ||
| 999 | |||
| 1000 | /* | ||
| 1001 | *defined for indicating boundary and cycle burst length | ||
| 1002 | */ | ||
| 1003 | #define CFG_BOUNDARY_1KB (1<<5) | ||
| 1004 | #define CFG_BOUNDARY_4KB (0<<5) | ||
| 1005 | #define CFG_CYC_BURST_LEN16 (1<<4) | ||
| 1006 | #define CFG_CYC_BURST_LEN8 (0<<4) | ||
| 1007 | |||
| 1008 | /* SRAM ID */ | ||
| 1009 | #define SRAMID_GAMMA_YR 0x0 | ||
| 1010 | #define SRAMID_GAMMA_UG 0x1 | ||
| 1011 | #define SRAMID_GAMMA_VB 0x2 | ||
| 1012 | #define SRAMID_PALATTE 0x3 | ||
| 1013 | #define SRAMID_HWC 0xf | ||
| 1014 | |||
| 1015 | /* SRAM INIT Read/Write */ | ||
| 1016 | #define SRAMID_INIT_READ 0x0 | ||
| 1017 | #define SRAMID_INIT_WRITE 0x2 | ||
| 1018 | #define SRAMID_INIT_DEFAULT 0x3 | ||
| 1019 | |||
| 1020 | /* | ||
| 1021 | * defined VSYNC selection mode for DMA control 1 register | ||
| 1022 | * DMA1 bit[30:28] | ||
| 1023 | */ | ||
| 1024 | #define VMODE_SMPN 0x0 | ||
| 1025 | #define VMODE_SMPNIRQ 0x1 | ||
| 1026 | #define VMODE_DUMB 0x2 | ||
| 1027 | #define VMODE_IPE 0x3 | ||
| 1028 | #define VMODE_IRE 0x4 | ||
| 1029 | |||
| 1030 | /* | ||
| 1031 | * defined Configure Alpha and Alpha mode for DMA control 1 register | ||
| 1032 | * DMA1 bit[15:08](alpha) / bit[17:16](alpha mode) | ||
| 1033 | */ | ||
| 1034 | /* ALPHA mode */ | ||
| 1035 | #define MODE_ALPHA_DMA 0x0 | ||
| 1036 | #define MODE_ALPHA_GRA 0x1 | ||
| 1037 | #define MODE_ALPHA_CFG 0x2 | ||
| 1038 | |||
| 1039 | /* alpha value */ | ||
| 1040 | #define ALPHA_NOGRAPHIC 0xFF /* all video, no graphic */ | ||
| 1041 | #define ALPHA_NOVIDEO 0x00 /* all graphic, no video */ | ||
| 1042 | #define ALPHA_GRAPHNVIDEO 0x0F /* Selects graphic & video */ | ||
| 1043 | |||
| 1044 | /* | ||
| 1045 | * defined Pixel Command for DMA control 1 register | ||
| 1046 | * DMA1 bit[07:00] | ||
| 1047 | */ | ||
| 1048 | #define PIXEL_CMD 0x81 | ||
| 1049 | |||
| 1050 | /* DSI */ | ||
| 1051 | /* DSI1 - 4 Lane Controller base */ | ||
| 1052 | #define DSI1_REGS_PHYSICAL_BASE 0xD420B800 | ||
| 1053 | /* DSI2 - 3 Lane Controller base */ | ||
| 1054 | #define DSI2_REGS_PHYSICAL_BASE 0xD420BA00 | ||
| 1055 | |||
| 1056 | /* DSI Controller Registers */ | ||
| 1057 | struct dsi_lcd_regs { | ||
| 1058 | #define DSI_LCD1_CTRL_0 0x100 /* DSI Active Panel 1 Control register 0 */ | ||
| 1059 | #define DSI_LCD1_CTRL_1 0x104 /* DSI Active Panel 1 Control register 1 */ | ||
| 1060 | u32 ctrl0; | ||
| 1061 | u32 ctrl1; | ||
| 1062 | u32 reserved1[2]; | ||
| 1063 | |||
| 1064 | #define DSI_LCD1_TIMING_0 0x110 /* Timing register 0 */ | ||
| 1065 | #define DSI_LCD1_TIMING_1 0x114 /* Timing register 1 */ | ||
| 1066 | #define DSI_LCD1_TIMING_2 0x118 /* Timing register 2 */ | ||
| 1067 | #define DSI_LCD1_TIMING_3 0x11C /* Timing register 3 */ | ||
| 1068 | #define DSI_LCD1_WC_0 0x120 /* Word Count register 0 */ | ||
| 1069 | #define DSI_LCD1_WC_1 0x124 /* Word Count register 1 */ | ||
| 1070 | #define DSI_LCD1_WC_2 0x128 /* Word Count register 2 */ | ||
| 1071 | u32 timing0; | ||
| 1072 | u32 timing1; | ||
| 1073 | u32 timing2; | ||
| 1074 | u32 timing3; | ||
| 1075 | u32 wc0; | ||
| 1076 | u32 wc1; | ||
| 1077 | u32 wc2; | ||
| 1078 | u32 reserved2[1]; | ||
| 1079 | u32 slot_cnt0; | ||
| 1080 | u32 slot_cnt1; | ||
| 1081 | u32 reserved3[2]; | ||
| 1082 | u32 status_0; | ||
| 1083 | u32 status_1; | ||
| 1084 | u32 status_2; | ||
| 1085 | u32 status_3; | ||
| 1086 | u32 status_4; | ||
| 1087 | }; | ||
| 1088 | |||
| 1089 | struct dsi_regs { | ||
| 1090 | #define DSI_CTRL_0 0x000 /* DSI control register 0 */ | ||
| 1091 | #define DSI_CTRL_1 0x004 /* DSI control register 1 */ | ||
| 1092 | u32 ctrl0; | ||
| 1093 | u32 ctrl1; | ||
| 1094 | u32 reserved1[2]; | ||
| 1095 | u32 irq_status; | ||
| 1096 | u32 irq_mask; | ||
| 1097 | u32 reserved2[2]; | ||
| 1098 | |||
| 1099 | #define DSI_CPU_CMD_0 0x020 /* DSI CPU packet command register 0 */ | ||
| 1100 | #define DSI_CPU_CMD_1 0x024 /* DSU CPU Packet Command Register 1 */ | ||
| 1101 | #define DSI_CPU_CMD_3 0x02C /* DSU CPU Packet Command Register 3 */ | ||
| 1102 | #define DSI_CPU_WDAT_0 0x030 /* DSI CUP */ | ||
| 1103 | u32 cmd0; | ||
| 1104 | u32 cmd1; | ||
| 1105 | u32 cmd2; | ||
| 1106 | u32 cmd3; | ||
| 1107 | u32 dat0; | ||
| 1108 | u32 status0; | ||
| 1109 | u32 status1; | ||
| 1110 | u32 status2; | ||
| 1111 | u32 status3; | ||
| 1112 | u32 status4; | ||
| 1113 | u32 reserved3[2]; | ||
| 1114 | |||
| 1115 | u32 smt_cmd; | ||
| 1116 | u32 smt_ctrl0; | ||
| 1117 | u32 smt_ctrl1; | ||
| 1118 | u32 reserved4[1]; | ||
| 1119 | |||
| 1120 | u32 rx0_status; | ||
| 1121 | |||
| 1122 | /* Rx Packet Header - data from slave device */ | ||
| 1123 | #define DSI_RX_PKT_HDR_0 0x064 | ||
| 1124 | u32 rx0_header; | ||
| 1125 | u32 rx1_status; | ||
| 1126 | u32 rx1_header; | ||
| 1127 | u32 rx_ctrl; | ||
| 1128 | u32 rx_ctrl1; | ||
| 1129 | u32 rx2_status; | ||
| 1130 | u32 rx2_header; | ||
| 1131 | u32 reserved5[1]; | ||
| 1132 | |||
| 1133 | u32 phy_ctrl1; | ||
| 1134 | #define DSI_PHY_CTRL_2 0x088 /* DSI DPHI Control Register 2 */ | ||
| 1135 | #define DSI_PHY_CTRL_3 0x08C /* DPHY Control Register 3 */ | ||
| 1136 | u32 phy_ctrl2; | ||
| 1137 | u32 phy_ctrl3; | ||
| 1138 | u32 phy_status0; | ||
| 1139 | u32 phy_status1; | ||
| 1140 | u32 reserved6[5]; | ||
| 1141 | u32 phy_status2; | ||
| 1142 | |||
| 1143 | #define DSI_PHY_RCOMP_0 0x0B0 /* DPHY Rcomp Control Register */ | ||
| 1144 | u32 phy_rcomp0; | ||
| 1145 | u32 reserved7[3]; | ||
| 1146 | #define DSI_PHY_TIME_0 0x0C0 /* DPHY Timing Control Register 0 */ | ||
| 1147 | #define DSI_PHY_TIME_1 0x0C4 /* DPHY Timing Control Register 1 */ | ||
| 1148 | #define DSI_PHY_TIME_2 0x0C8 /* DPHY Timing Control Register 2 */ | ||
| 1149 | #define DSI_PHY_TIME_3 0x0CC /* DPHY Timing Control Register 3 */ | ||
| 1150 | #define DSI_PHY_TIME_4 0x0D0 /* DPHY Timing Control Register 4 */ | ||
| 1151 | #define DSI_PHY_TIME_5 0x0D4 /* DPHY Timing Control Register 5 */ | ||
| 1152 | u32 phy_timing0; | ||
| 1153 | u32 phy_timing1; | ||
| 1154 | u32 phy_timing2; | ||
| 1155 | u32 phy_timing3; | ||
| 1156 | u32 phy_code_0; | ||
| 1157 | u32 phy_code_1; | ||
| 1158 | u32 reserved8[2]; | ||
| 1159 | u32 mem_ctrl; | ||
| 1160 | u32 tx_timer; | ||
| 1161 | u32 rx_timer; | ||
| 1162 | u32 turn_timer; | ||
| 1163 | u32 reserved9[4]; | ||
| 1164 | |||
| 1165 | #define DSI_LCD1_CTRL_0 0x100 /* DSI Active Panel 1 Control register 0 */ | ||
| 1166 | #define DSI_LCD1_CTRL_1 0x104 /* DSI Active Panel 1 Control register 1 */ | ||
| 1167 | #define DSI_LCD1_TIMING_0 0x110 /* Timing register 0 */ | ||
| 1168 | #define DSI_LCD1_TIMING_1 0x114 /* Timing register 1 */ | ||
| 1169 | #define DSI_LCD1_TIMING_2 0x118 /* Timing register 2 */ | ||
| 1170 | #define DSI_LCD1_TIMING_3 0x11C /* Timing register 3 */ | ||
| 1171 | #define DSI_LCD1_WC_0 0x120 /* Word Count register 0 */ | ||
| 1172 | #define DSI_LCD1_WC_1 0x124 /* Word Count register 1 */ | ||
| 1173 | #define DSI_LCD1_WC_2 0x128 /* Word Count register 2 */ | ||
| 1174 | struct dsi_lcd_regs lcd1; | ||
| 1175 | u32 reserved10[11]; | ||
| 1176 | struct dsi_lcd_regs lcd2; | ||
| 1177 | }; | ||
| 1178 | |||
| 1179 | #define DSI_LCD2_CTRL_0 0x180 /* DSI Active Panel 2 Control register 0 */ | ||
| 1180 | #define DSI_LCD2_CTRL_1 0x184 /* DSI Active Panel 2 Control register 1 */ | ||
| 1181 | #define DSI_LCD2_TIMING_0 0x190 /* Timing register 0 */ | ||
| 1182 | #define DSI_LCD2_TIMING_1 0x194 /* Timing register 1 */ | ||
| 1183 | #define DSI_LCD2_TIMING_2 0x198 /* Timing register 2 */ | ||
| 1184 | #define DSI_LCD2_TIMING_3 0x19C /* Timing register 3 */ | ||
| 1185 | #define DSI_LCD2_WC_0 0x1A0 /* Word Count register 0 */ | ||
| 1186 | #define DSI_LCD2_WC_1 0x1A4 /* Word Count register 1 */ | ||
| 1187 | #define DSI_LCD2_WC_2 0x1A8 /* Word Count register 2 */ | ||
| 1188 | |||
| 1189 | /* DSI_CTRL_0 0x0000 DSI Control Register 0 */ | ||
| 1190 | #define DSI_CTRL_0_CFG_SOFT_RST (1<<31) | ||
| 1191 | #define DSI_CTRL_0_CFG_SOFT_RST_REG (1<<30) | ||
| 1192 | #define DSI_CTRL_0_CFG_LCD1_TX_EN (1<<8) | ||
| 1193 | #define DSI_CTRL_0_CFG_LCD1_SLV (1<<4) | ||
| 1194 | #define DSI_CTRL_0_CFG_LCD1_EN (1<<0) | ||
| 1195 | |||
| 1196 | /* DSI_CTRL_1 0x0004 DSI Control Register 1 */ | ||
| 1197 | #define DSI_CTRL_1_CFG_EOTP (1<<8) | ||
| 1198 | #define DSI_CTRL_1_CFG_RSVD (2<<4) | ||
| 1199 | #define DSI_CTRL_1_CFG_LCD2_VCH_NO_MASK (3<<2) | ||
| 1200 | #define DSI_CTRL_1_CFG_LCD2_VCH_NO_SHIFT 2 | ||
| 1201 | #define DSI_CTRL_1_CFG_LCD1_VCH_NO_MASK (3<<0) | ||
| 1202 | #define DSI_CTRL_1_CFG_LCD1_VCH_NO_SHIFT 0 | ||
| 1203 | |||
| 1204 | /* DSI_LCD1_CTRL_1 0x0104 DSI Active Panel 1 Control Register 1 */ | ||
| 1205 | /* LCD 1 Vsync Reset Enable */ | ||
| 1206 | #define DSI_LCD1_CTRL_1_CFG_L1_VSYNC_RST_EN (1<<31) | ||
| 1207 | /* LCD 1 2K Pixel Buffer Mode Enable */ | ||
| 1208 | #define DSI_LCD1_CTRL_1_CFG_L1_M2K_EN (1<<30) | ||
| 1209 | /* Bit(s) DSI_LCD1_CTRL_1_RSRV_29_23 reserved */ | ||
| 1210 | /* Long Blanking Packet Enable */ | ||
| 1211 | #define DSI_LCD1_CTRL_1_CFG_L1_HLP_PKT_EN (1<<22) | ||
| 1212 | /* Extra Long Blanking Packet Enable */ | ||
| 1213 | #define DSI_LCD1_CTRL_1_CFG_L1_HEX_PKT_EN (1<<21) | ||
| 1214 | /* Front Porch Packet Enable */ | ||
| 1215 | #define DSI_LCD1_CTRL_1_CFG_L1_HFP_PKT_EN (1<<20) | ||
| 1216 | /* hact Packet Enable */ | ||
| 1217 | #define DSI_LCD1_CTRL_1_CFG_L1_HACT_PKT_EN (1<<19) | ||
| 1218 | /* Back Porch Packet Enable */ | ||
| 1219 | #define DSI_LCD1_CTRL_1_CFG_L1_HBP_PKT_EN (1<<18) | ||
| 1220 | /* hse Packet Enable */ | ||
| 1221 | #define DSI_LCD1_CTRL_1_CFG_L1_HSE_PKT_EN (1<<17) | ||
| 1222 | /* hsa Packet Enable */ | ||
| 1223 | #define DSI_LCD1_CTRL_1_CFG_L1_HSA_PKT_EN (1<<16) | ||
| 1224 | /* All Item Enable after Pixel Data */ | ||
| 1225 | #define DSI_LCD1_CTRL_1_CFG_L1_ALL_SLOT_EN (1<<15) | ||
| 1226 | /* Extra Long Packet Enable after Pixel Data */ | ||
| 1227 | #define DSI_LCD1_CTRL_1_CFG_L1_HEX_SLOT_EN (1<<14) | ||
| 1228 | /* Bit(s) DSI_LCD1_CTRL_1_RSRV_13_11 reserved */ | ||
| 1229 | /* Turn Around Bus at Last h Line */ | ||
| 1230 | #define DSI_LCD1_CTRL_1_CFG_L1_LAST_LINE_TURN (1<<10) | ||
| 1231 | /* Go to Low Power Every Frame */ | ||
| 1232 | #define DSI_LCD1_CTRL_1_CFG_L1_LPM_FRAME_EN (1<<9) | ||
| 1233 | /* Go to Low Power Every Line */ | ||
| 1234 | #define DSI_LCD1_CTRL_1_CFG_L1_LPM_LINE_EN (1<<8) | ||
| 1235 | /* Bit(s) DSI_LCD1_CTRL_1_RSRV_7_4 reserved */ | ||
| 1236 | /* DSI Transmission Mode for LCD 1 */ | ||
| 1237 | #define DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_SHIFT 2 | ||
| 1238 | #define DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_MASK (3<<2) | ||
| 1239 | /* LCD 1 Input Data RGB Mode for LCD 1 */ | ||
| 1240 | #define DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_SHIFT 0 | ||
| 1241 | #define DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_MASK (3<<2) | ||
| 1242 | |||
| 1243 | /* DSI_PHY_CTRL_2 0x0088 DPHY Control Register 2 */ | ||
| 1244 | /* Bit(s) DSI_PHY_CTRL_2_RSRV_31_12 reserved */ | ||
| 1245 | /* DPHY LP Receiver Enable */ | ||
| 1246 | #define DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_MASK (0xf<<8) | ||
| 1247 | #define DSI_PHY_CTRL_2_CFG_CSR_LANE_RESC_EN_SHIFT 8 | ||
| 1248 | /* DPHY Data Lane Enable */ | ||
| 1249 | #define DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_MASK (0xf<<4) | ||
| 1250 | #define DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_SHIFT 4 | ||
| 1251 | /* DPHY Bus Turn Around */ | ||
| 1252 | #define DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_MASK (0xf) | ||
| 1253 | #define DSI_PHY_CTRL_2_CFG_CSR_LANE_TURN_SHIFT 0 | ||
| 1254 | |||
| 1255 | /* DSI_CPU_CMD_1 0x0024 DSI CPU Packet Command Register 1 */ | ||
| 1256 | /* Bit(s) DSI_CPU_CMD_1_RSRV_31_24 reserved */ | ||
| 1257 | /* LPDT TX Enable */ | ||
| 1258 | #define DSI_CPU_CMD_1_CFG_TXLP_LPDT_MASK (0xf<<20) | ||
| 1259 | #define DSI_CPU_CMD_1_CFG_TXLP_LPDT_SHIFT 20 | ||
| 1260 | /* ULPS TX Enable */ | ||
| 1261 | #define DSI_CPU_CMD_1_CFG_TXLP_ULPS_MASK (0xf<<16) | ||
| 1262 | #define DSI_CPU_CMD_1_CFG_TXLP_ULPS_SHIFT 16 | ||
| 1263 | /* Low Power TX Trigger Code */ | ||
| 1264 | #define DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_MASK (0xffff) | ||
| 1265 | #define DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_SHIFT 0 | ||
| 1266 | |||
| 1267 | /* DSI_PHY_TIME_0 0x00c0 DPHY Timing Control Register 0 */ | ||
| 1268 | /* Length of HS Exit Period in tx_clk_esc Cycles */ | ||
| 1269 | #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_MASK (0xff<<24) | ||
| 1270 | #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_SHIFT 24 | ||
| 1271 | /* DPHY HS Trail Period Length */ | ||
| 1272 | #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_MASK (0xff<<16) | ||
| 1273 | #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_SHIFT 16 | ||
| 1274 | /* DPHY HS Zero State Length */ | ||
| 1275 | #define DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_MASK (0xff<<8) | ||
| 1276 | #define DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_SHIFT 8 | ||
| 1277 | /* DPHY HS Prepare State Length */ | ||
| 1278 | #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_MASK (0xff) | ||
| 1279 | #define DSI_PHY_TIME_0_CFG_CSR_TIME_HS_PREP_SHIFT 0 | ||
| 1280 | |||
| 1281 | /* DSI_PHY_TIME_1 0x00c4 DPHY Timing Control Register 1 */ | ||
| 1282 | /* Time to Drive LP-00 by New Transmitter */ | ||
| 1283 | #define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_MASK (0xff<<24) | ||
| 1284 | #define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_SHIFT 24 | ||
| 1285 | /* Time to Drive LP-00 after Turn Request */ | ||
| 1286 | #define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_MASK (0xff<<16) | ||
| 1287 | #define DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_SHIFT 16 | ||
| 1288 | /* DPHY HS Wakeup Period Length */ | ||
| 1289 | #define DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_MASK (0xffff) | ||
| 1290 | #define DSI_PHY_TIME_1_CFG_CSR_TIME_WAKEUP_SHIFT 0 | ||
| 1291 | |||
| 1292 | /* DSI_PHY_TIME_2 0x00c8 DPHY Timing Control Register 2 */ | ||
| 1293 | /* DPHY CLK Exit Period Length */ | ||
| 1294 | #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_MASK (0xff<<24) | ||
| 1295 | #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_SHIFT 24 | ||
| 1296 | /* DPHY CLK Trail Period Length */ | ||
| 1297 | #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_MASK (0xff<<16) | ||
| 1298 | #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_SHIFT 16 | ||
| 1299 | /* DPHY CLK Zero State Length */ | ||
| 1300 | #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_MASK (0xff<<8) | ||
| 1301 | #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_SHIFT 8 | ||
| 1302 | /* DPHY CLK LP Length */ | ||
| 1303 | #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_MASK (0xff) | ||
| 1304 | #define DSI_PHY_TIME_2_CFG_CSR_TIME_CK_LPX_SHIFT 0 | ||
| 1305 | |||
| 1306 | /* DSI_PHY_TIME_3 0x00cc DPHY Timing Control Register 3 */ | ||
| 1307 | /* Bit(s) DSI_PHY_TIME_3_RSRV_31_16 reserved */ | ||
| 1308 | /* DPHY LP Length */ | ||
| 1309 | #define DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_MASK (0xff<<8) | ||
| 1310 | #define DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_SHIFT 8 | ||
| 1311 | /* DPHY HS req to rdy Length */ | ||
| 1312 | #define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_MASK (0xff) | ||
| 1313 | #define DSI_PHY_TIME_3_CFG_CSR_TIME_REQRDY_SHIFT 0 | ||
| 1314 | |||
| 1315 | /* | ||
| 1316 | * DSI timings | ||
| 1317 | * PXA988 has diffrent ESC CLK with MMP2/MMP3 | ||
| 1318 | * it will be used in dsi_set_dphy() in pxa688_phy.c | ||
| 1319 | * as low power mode clock. | ||
| 1320 | */ | ||
| 1321 | #ifdef CONFIG_CPU_PXA988 | ||
| 1322 | #define DSI_ESC_CLK 52 /* Unit: Mhz */ | ||
| 1323 | #define DSI_ESC_CLK_T 19 /* Unit: ns */ | ||
| 1324 | #else | ||
| 1325 | #define DSI_ESC_CLK 66 /* Unit: Mhz */ | ||
| 1326 | #define DSI_ESC_CLK_T 15 /* Unit: ns */ | ||
| 1327 | #endif | ||
| 1328 | |||
| 1329 | /* LVDS */ | ||
| 1330 | /* LVDS_PHY_CTRL */ | ||
| 1331 | #define LVDS_PHY_CTL 0x2A4 | ||
| 1332 | #define LVDS_PLL_LOCK (1 << 31) | ||
| 1333 | #define LVDS_PHY_EXT_MASK (7 << 28) | ||
| 1334 | #define LVDS_PHY_EXT_SHIFT (28) | ||
| 1335 | #define LVDS_CLK_PHASE_MASK (0x7f << 16) | ||
| 1336 | #define LVDS_CLK_PHASE_SHIFT (16) | ||
| 1337 | #define LVDS_SSC_RESET_EXT (1 << 13) | ||
| 1338 | #define LVDS_SSC_MODE_DOWN_SPREAD (1 << 12) | ||
| 1339 | #define LVDS_SSC_EN (1 << 11) | ||
| 1340 | #define LVDS_PU_PLL (1 << 10) | ||
| 1341 | #define LVDS_PU_TX (1 << 9) | ||
| 1342 | #define LVDS_PU_IVREF (1 << 8) | ||
| 1343 | #define LVDS_CLK_SEL (1 << 7) | ||
| 1344 | #define LVDS_CLK_SEL_LVDS_PCLK (1 << 7) | ||
| 1345 | #define LVDS_PD_CH_MASK (0x3f << 1) | ||
| 1346 | #define LVDS_PD_CH(ch) ((ch) << 1) | ||
| 1347 | #define LVDS_RST (1 << 0) | ||
| 1348 | |||
| 1349 | #define LVDS_PHY_CTL_EXT 0x2A8 | ||
| 1350 | |||
| 1351 | /* LVDS_PHY_CTRL_EXT1 */ | ||
| 1352 | #define LVDS_SSC_RNGE_MASK (0x7ff << 16) | ||
| 1353 | #define LVDS_SSC_RNGE_SHIFT (16) | ||
| 1354 | #define LVDS_RESERVE_IN_MASK (0xf << 12) | ||
| 1355 | #define LVDS_RESERVE_IN_SHIFT (12) | ||
| 1356 | #define LVDS_TEST_MON_MASK (0x7 << 8) | ||
| 1357 | #define LVDS_TEST_MON_SHIFT (8) | ||
| 1358 | #define LVDS_POL_SWAP_MASK (0x3f << 0) | ||
| 1359 | #define LVDS_POL_SWAP_SHIFT (0) | ||
| 1360 | |||
| 1361 | /* LVDS_PHY_CTRL_EXT2 */ | ||
| 1362 | #define LVDS_TX_DIF_AMP_MASK (0xf << 24) | ||
| 1363 | #define LVDS_TX_DIF_AMP_SHIFT (24) | ||
| 1364 | #define LVDS_TX_DIF_CM_MASK (0x3 << 22) | ||
| 1365 | #define LVDS_TX_DIF_CM_SHIFT (22) | ||
| 1366 | #define LVDS_SELLV_TXCLK_MASK (0x1f << 16) | ||
| 1367 | #define LVDS_SELLV_TXCLK_SHIFT (16) | ||
| 1368 | #define LVDS_TX_CMFB_EN (0x1 << 15) | ||
| 1369 | #define LVDS_TX_TERM_EN (0x1 << 14) | ||
| 1370 | #define LVDS_SELLV_TXDATA_MASK (0x1f << 8) | ||
| 1371 | #define LVDS_SELLV_TXDATA_SHIFT (8) | ||
| 1372 | #define LVDS_SELLV_OP7_MASK (0x3 << 6) | ||
| 1373 | #define LVDS_SELLV_OP7_SHIFT (6) | ||
| 1374 | #define LVDS_SELLV_OP6_MASK (0x3 << 4) | ||
| 1375 | #define LVDS_SELLV_OP6_SHIFT (4) | ||
| 1376 | #define LVDS_SELLV_OP9_MASK (0x3 << 2) | ||
| 1377 | #define LVDS_SELLV_OP9_SHIFT (2) | ||
| 1378 | #define LVDS_STRESSTST_EN (0x1 << 0) | ||
| 1379 | |||
| 1380 | /* LVDS_PHY_CTRL_EXT3 */ | ||
| 1381 | #define LVDS_KVCO_MASK (0xf << 28) | ||
| 1382 | #define LVDS_KVCO_SHIFT (28) | ||
| 1383 | #define LVDS_CTUNE_MASK (0x3 << 26) | ||
| 1384 | #define LVDS_CTUNE_SHIFT (26) | ||
| 1385 | #define LVDS_VREG_IVREF_MASK (0x3 << 24) | ||
| 1386 | #define LVDS_VREG_IVREF_SHIFT (24) | ||
| 1387 | #define LVDS_VDDL_MASK (0xf << 20) | ||
| 1388 | #define LVDS_VDDL_SHIFT (20) | ||
| 1389 | #define LVDS_VDDM_MASK (0x3 << 18) | ||
| 1390 | #define LVDS_VDDM_SHIFT (18) | ||
| 1391 | #define LVDS_FBDIV_MASK (0xf << 8) | ||
| 1392 | #define LVDS_FBDIV_SHIFT (8) | ||
| 1393 | #define LVDS_REFDIV_MASK (0x7f << 0) | ||
| 1394 | #define LVDS_REFDIV_SHIFT (0) | ||
| 1395 | |||
| 1396 | /* LVDS_PHY_CTRL_EXT4 */ | ||
| 1397 | #define LVDS_SSC_FREQ_DIV_MASK (0xffff << 16) | ||
| 1398 | #define LVDS_SSC_FREQ_DIV_SHIFT (16) | ||
| 1399 | #define LVDS_INTPI_MASK (0xf << 12) | ||
| 1400 | #define LVDS_INTPI_SHIFT (12) | ||
| 1401 | #define LVDS_VCODIV_SEL_SE_MASK (0xf << 8) | ||
| 1402 | #define LVDS_VCODIV_SEL_SE_SHIFT (8) | ||
| 1403 | #define LVDS_RESET_INTP_EXT (0x1 << 7) | ||
| 1404 | #define LVDS_VCO_VRNG_MASK (0x7 << 4) | ||
| 1405 | #define LVDS_VCO_VRNG_SHIFT (4) | ||
| 1406 | #define LVDS_PI_EN (0x1 << 3) | ||
| 1407 | #define LVDS_ICP_MASK (0x7 << 0) | ||
| 1408 | #define LVDS_ICP_SHIFT (0) | ||
| 1409 | |||
| 1410 | /* LVDS_PHY_CTRL_EXT5 */ | ||
| 1411 | #define LVDS_FREQ_OFFSET_MASK (0x1ffff << 15) | ||
| 1412 | #define LVDS_FREQ_OFFSET_SHIFT (15) | ||
| 1413 | #define LVDS_FREQ_OFFSET_VALID (0x1 << 2) | ||
| 1414 | #define LVDS_FREQ_OFFSET_MODE_CK_DIV4_OUT (0x1 << 1) | ||
| 1415 | #define LVDS_FREQ_OFFSET_MODE_EN (0x1 << 0) | ||
| 1416 | |||
| 1417 | enum { | ||
| 1418 | PATH_PN = 0, | ||
| 1419 | PATH_TV, | ||
| 1420 | PATH_P2, | ||
| 1421 | }; | ||
| 1422 | |||
| 1423 | /* | ||
| 1424 | * mmp path describes part of mmp path related info: | ||
| 1425 | * which is hiden in display driver and not exported to buffer driver | ||
| 1426 | */ | ||
| 1427 | struct mmphw_ctrl; | ||
| 1428 | struct mmphw_path_plat { | ||
| 1429 | int id; | ||
| 1430 | struct mmphw_ctrl *ctrl; | ||
| 1431 | struct mmp_path *path; | ||
| 1432 | u32 path_config; | ||
| 1433 | u32 link_config; | ||
| 1434 | u32 dsi_rbswap; | ||
| 1435 | }; | ||
| 1436 | |||
| 1437 | /* mmp ctrl describes mmp controller related info */ | ||
| 1438 | struct mmphw_ctrl { | ||
| 1439 | /* platform related, get from config */ | ||
| 1440 | const char *name; | ||
| 1441 | int irq; | ||
| 1442 | void *reg_base; | ||
| 1443 | struct clk *clk; | ||
| 1444 | |||
| 1445 | /* sys info */ | ||
| 1446 | struct device *dev; | ||
| 1447 | |||
| 1448 | /* state */ | ||
| 1449 | int open_count; | ||
| 1450 | int status; | ||
| 1451 | struct mutex access_ok; | ||
| 1452 | |||
| 1453 | /*pathes*/ | ||
| 1454 | int path_num; | ||
| 1455 | struct mmphw_path_plat path_plats[0]; | ||
| 1456 | }; | ||
| 1457 | |||
| 1458 | static inline int overlay_is_vid(struct mmp_overlay *overlay) | ||
| 1459 | { | ||
| 1460 | return overlay->dmafetch_id & 1; | ||
| 1461 | } | ||
| 1462 | |||
| 1463 | static inline struct mmphw_path_plat *path_to_path_plat(struct mmp_path *path) | ||
| 1464 | { | ||
| 1465 | return (struct mmphw_path_plat *)path->plat_data; | ||
| 1466 | } | ||
| 1467 | |||
| 1468 | static inline struct mmphw_ctrl *path_to_ctrl(struct mmp_path *path) | ||
| 1469 | { | ||
| 1470 | return path_to_path_plat(path)->ctrl; | ||
| 1471 | } | ||
| 1472 | |||
| 1473 | static inline struct mmphw_ctrl *overlay_to_ctrl(struct mmp_overlay *overlay) | ||
| 1474 | { | ||
| 1475 | return path_to_ctrl(overlay->path); | ||
| 1476 | } | ||
| 1477 | |||
| 1478 | static inline void *ctrl_regs(struct mmp_path *path) | ||
| 1479 | { | ||
| 1480 | return path_to_ctrl(path)->reg_base; | ||
| 1481 | } | ||
| 1482 | |||
| 1483 | /* path regs, for regs symmetrical for both pathes */ | ||
| 1484 | static inline struct lcd_regs *path_regs(struct mmp_path *path) | ||
| 1485 | { | ||
| 1486 | if (path->id == PATH_PN) | ||
| 1487 | return (struct lcd_regs *)(ctrl_regs(path) + 0xc0); | ||
| 1488 | else if (path->id == PATH_TV) | ||
| 1489 | return (struct lcd_regs *)ctrl_regs(path); | ||
| 1490 | else if (path->id == PATH_P2) | ||
| 1491 | return (struct lcd_regs *)(ctrl_regs(path) + 0x200); | ||
| 1492 | else { | ||
| 1493 | dev_err(path->dev, "path id %d invalid\n", path->id); | ||
| 1494 | BUG_ON(1); | ||
| 1495 | return NULL; | ||
| 1496 | } | ||
| 1497 | } | ||
| 1498 | |||
| 1499 | #ifdef CONFIG_MMP_DISP_SPI | ||
| 1500 | extern int lcd_spi_register(struct mmphw_ctrl *ctrl); | ||
| 1501 | #endif | ||
| 1502 | #endif /* _MMP_CTRL_H_ */ | ||