aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/tty
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2011-08-01 12:10:16 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-08-01 12:10:16 -0400
commite10b87d2b5b4574cdf3a5a19b22ca88b91ba7151 (patch)
tree21c0714515e1fb1722b918b5e43ecbd7349e2202 /drivers/tty
parent3da3f872aa175f59e20766ed30aaea67fd4fa7d1 (diff)
parent536628d0983f1c6a7ccece28ded635661aa30319 (diff)
Merge branch 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x
* 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x: (39 commits) SH: static should be at beginning of declaration sh: move CLKDEV_xxx_ID macro to sh_clk.h sh: clock-shx3: add CLKDEV_ICK_ID for cleanup sh: clock-sh7786: add CLKDEV_ICK_ID for cleanup sh: clock-sh7785: add CLKDEV_ICK_ID for cleanup sh: clock-sh7757: add CLKDEV_ICK_ID for cleanup sh: clock-sh7366: add CLKDEV_ICK_ID for cleanup sh: clock-sh7343: add CLKDEV_ICK_ID for cleanup sh: clock-sh7722: add CLKDEV_ICK_ID for cleanup sh: clock-sh7724: add CLKDEV_ICK_ID for cleanup sh: clock-sh7366: modify I2C clock settings sh: clock-sh7343: modify I2C clock settings sh: clock-sh7723: modify I2C clock settings sh: clock-sh7722: modify I2C clock settings sh: clock-sh7724: modify I2C clock settings serial: sh-sci: Fix up pretty name printing for port IRQs. serial: sh-sci: Kill off per-port enable/disable callbacks. serial: sh-sci: Add missing module description/author bits. serial: sh-sci: Regtype probing doesn't need to be fatal. sh: Tidy up pre-clkdev clk_get() error handling. ...
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/Kconfig2
-rw-r--r--drivers/tty/serial/sh-sci.c757
-rw-r--r--drivers/tty/serial/sh-sci.h434
3 files changed, 466 insertions, 727 deletions
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index cb40b82daf36..4dcb37bbdf92 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -959,7 +959,7 @@ config SERIAL_IP22_ZILOG_CONSOLE
959 959
960config SERIAL_SH_SCI 960config SERIAL_SH_SCI
961 tristate "SuperH SCI(F) serial port support" 961 tristate "SuperH SCI(F) serial port support"
962 depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE) 962 depends on HAVE_CLK && (SUPERH || ARCH_SHMOBILE)
963 select SERIAL_CORE 963 select SERIAL_CORE
964 964
965config SERIAL_SH_SCI_NR_UARTS 965config SERIAL_SH_SCI_NR_UARTS
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index ebd8629c108d..d0a56235c50e 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -54,10 +54,6 @@
54#include <asm/sh_bios.h> 54#include <asm/sh_bios.h>
55#endif 55#endif
56 56
57#ifdef CONFIG_H8300
58#include <asm/gpio.h>
59#endif
60
61#include "sh-sci.h" 57#include "sh-sci.h"
62 58
63struct sci_port { 59struct sci_port {
@@ -66,12 +62,6 @@ struct sci_port {
66 /* Platform configuration */ 62 /* Platform configuration */
67 struct plat_sci_port *cfg; 63 struct plat_sci_port *cfg;
68 64
69 /* Port enable callback */
70 void (*enable)(struct uart_port *port);
71
72 /* Port disable callback */
73 void (*disable)(struct uart_port *port);
74
75 /* Break timer */ 65 /* Break timer */
76 struct timer_list break_timer; 66 struct timer_list break_timer;
77 int break_flag; 67 int break_flag;
@@ -81,6 +71,8 @@ struct sci_port {
81 /* Function clock */ 71 /* Function clock */
82 struct clk *fclk; 72 struct clk *fclk;
83 73
74 char *irqstr[SCIx_NR_IRQS];
75
84 struct dma_chan *chan_tx; 76 struct dma_chan *chan_tx;
85 struct dma_chan *chan_rx; 77 struct dma_chan *chan_rx;
86 78
@@ -121,6 +113,278 @@ to_sci_port(struct uart_port *uart)
121 return container_of(uart, struct sci_port, port); 113 return container_of(uart, struct sci_port, port);
122} 114}
123 115
116struct plat_sci_reg {
117 u8 offset, size;
118};
119
120/* Helper for invalidating specific entries of an inherited map. */
121#define sci_reg_invalid { .offset = 0, .size = 0 }
122
123static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
124 [SCIx_PROBE_REGTYPE] = {
125 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
126 },
127
128 /*
129 * Common SCI definitions, dependent on the port's regshift
130 * value.
131 */
132 [SCIx_SCI_REGTYPE] = {
133 [SCSMR] = { 0x00, 8 },
134 [SCBRR] = { 0x01, 8 },
135 [SCSCR] = { 0x02, 8 },
136 [SCxTDR] = { 0x03, 8 },
137 [SCxSR] = { 0x04, 8 },
138 [SCxRDR] = { 0x05, 8 },
139 [SCFCR] = sci_reg_invalid,
140 [SCFDR] = sci_reg_invalid,
141 [SCTFDR] = sci_reg_invalid,
142 [SCRFDR] = sci_reg_invalid,
143 [SCSPTR] = sci_reg_invalid,
144 [SCLSR] = sci_reg_invalid,
145 },
146
147 /*
148 * Common definitions for legacy IrDA ports, dependent on
149 * regshift value.
150 */
151 [SCIx_IRDA_REGTYPE] = {
152 [SCSMR] = { 0x00, 8 },
153 [SCBRR] = { 0x01, 8 },
154 [SCSCR] = { 0x02, 8 },
155 [SCxTDR] = { 0x03, 8 },
156 [SCxSR] = { 0x04, 8 },
157 [SCxRDR] = { 0x05, 8 },
158 [SCFCR] = { 0x06, 8 },
159 [SCFDR] = { 0x07, 16 },
160 [SCTFDR] = sci_reg_invalid,
161 [SCRFDR] = sci_reg_invalid,
162 [SCSPTR] = sci_reg_invalid,
163 [SCLSR] = sci_reg_invalid,
164 },
165
166 /*
167 * Common SCIFA definitions.
168 */
169 [SCIx_SCIFA_REGTYPE] = {
170 [SCSMR] = { 0x00, 16 },
171 [SCBRR] = { 0x04, 8 },
172 [SCSCR] = { 0x08, 16 },
173 [SCxTDR] = { 0x20, 8 },
174 [SCxSR] = { 0x14, 16 },
175 [SCxRDR] = { 0x24, 8 },
176 [SCFCR] = { 0x18, 16 },
177 [SCFDR] = { 0x1c, 16 },
178 [SCTFDR] = sci_reg_invalid,
179 [SCRFDR] = sci_reg_invalid,
180 [SCSPTR] = sci_reg_invalid,
181 [SCLSR] = sci_reg_invalid,
182 },
183
184 /*
185 * Common SCIFB definitions.
186 */
187 [SCIx_SCIFB_REGTYPE] = {
188 [SCSMR] = { 0x00, 16 },
189 [SCBRR] = { 0x04, 8 },
190 [SCSCR] = { 0x08, 16 },
191 [SCxTDR] = { 0x40, 8 },
192 [SCxSR] = { 0x14, 16 },
193 [SCxRDR] = { 0x60, 8 },
194 [SCFCR] = { 0x18, 16 },
195 [SCFDR] = { 0x1c, 16 },
196 [SCTFDR] = sci_reg_invalid,
197 [SCRFDR] = sci_reg_invalid,
198 [SCSPTR] = sci_reg_invalid,
199 [SCLSR] = sci_reg_invalid,
200 },
201
202 /*
203 * Common SH-3 SCIF definitions.
204 */
205 [SCIx_SH3_SCIF_REGTYPE] = {
206 [SCSMR] = { 0x00, 8 },
207 [SCBRR] = { 0x02, 8 },
208 [SCSCR] = { 0x04, 8 },
209 [SCxTDR] = { 0x06, 8 },
210 [SCxSR] = { 0x08, 16 },
211 [SCxRDR] = { 0x0a, 8 },
212 [SCFCR] = { 0x0c, 8 },
213 [SCFDR] = { 0x0e, 16 },
214 [SCTFDR] = sci_reg_invalid,
215 [SCRFDR] = sci_reg_invalid,
216 [SCSPTR] = sci_reg_invalid,
217 [SCLSR] = sci_reg_invalid,
218 },
219
220 /*
221 * Common SH-4(A) SCIF(B) definitions.
222 */
223 [SCIx_SH4_SCIF_REGTYPE] = {
224 [SCSMR] = { 0x00, 16 },
225 [SCBRR] = { 0x04, 8 },
226 [SCSCR] = { 0x08, 16 },
227 [SCxTDR] = { 0x0c, 8 },
228 [SCxSR] = { 0x10, 16 },
229 [SCxRDR] = { 0x14, 8 },
230 [SCFCR] = { 0x18, 16 },
231 [SCFDR] = { 0x1c, 16 },
232 [SCTFDR] = sci_reg_invalid,
233 [SCRFDR] = sci_reg_invalid,
234 [SCSPTR] = { 0x20, 16 },
235 [SCLSR] = { 0x24, 16 },
236 },
237
238 /*
239 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
240 * register.
241 */
242 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
243 [SCSMR] = { 0x00, 16 },
244 [SCBRR] = { 0x04, 8 },
245 [SCSCR] = { 0x08, 16 },
246 [SCxTDR] = { 0x0c, 8 },
247 [SCxSR] = { 0x10, 16 },
248 [SCxRDR] = { 0x14, 8 },
249 [SCFCR] = { 0x18, 16 },
250 [SCFDR] = { 0x1c, 16 },
251 [SCTFDR] = sci_reg_invalid,
252 [SCRFDR] = sci_reg_invalid,
253 [SCSPTR] = sci_reg_invalid,
254 [SCLSR] = { 0x24, 16 },
255 },
256
257 /*
258 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
259 * count registers.
260 */
261 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
262 [SCSMR] = { 0x00, 16 },
263 [SCBRR] = { 0x04, 8 },
264 [SCSCR] = { 0x08, 16 },
265 [SCxTDR] = { 0x0c, 8 },
266 [SCxSR] = { 0x10, 16 },
267 [SCxRDR] = { 0x14, 8 },
268 [SCFCR] = { 0x18, 16 },
269 [SCFDR] = { 0x1c, 16 },
270 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
271 [SCRFDR] = { 0x20, 16 },
272 [SCSPTR] = { 0x24, 16 },
273 [SCLSR] = { 0x28, 16 },
274 },
275
276 /*
277 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
278 * registers.
279 */
280 [SCIx_SH7705_SCIF_REGTYPE] = {
281 [SCSMR] = { 0x00, 16 },
282 [SCBRR] = { 0x04, 8 },
283 [SCSCR] = { 0x08, 16 },
284 [SCxTDR] = { 0x20, 8 },
285 [SCxSR] = { 0x14, 16 },
286 [SCxRDR] = { 0x24, 8 },
287 [SCFCR] = { 0x18, 16 },
288 [SCFDR] = { 0x1c, 16 },
289 [SCTFDR] = sci_reg_invalid,
290 [SCRFDR] = sci_reg_invalid,
291 [SCSPTR] = sci_reg_invalid,
292 [SCLSR] = sci_reg_invalid,
293 },
294};
295
296#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
297
298/*
299 * The "offset" here is rather misleading, in that it refers to an enum
300 * value relative to the port mapping rather than the fixed offset
301 * itself, which needs to be manually retrieved from the platform's
302 * register map for the given port.
303 */
304static unsigned int sci_serial_in(struct uart_port *p, int offset)
305{
306 struct plat_sci_reg *reg = sci_getreg(p, offset);
307
308 if (reg->size == 8)
309 return ioread8(p->membase + (reg->offset << p->regshift));
310 else if (reg->size == 16)
311 return ioread16(p->membase + (reg->offset << p->regshift));
312 else
313 WARN(1, "Invalid register access\n");
314
315 return 0;
316}
317
318static void sci_serial_out(struct uart_port *p, int offset, int value)
319{
320 struct plat_sci_reg *reg = sci_getreg(p, offset);
321
322 if (reg->size == 8)
323 iowrite8(value, p->membase + (reg->offset << p->regshift));
324 else if (reg->size == 16)
325 iowrite16(value, p->membase + (reg->offset << p->regshift));
326 else
327 WARN(1, "Invalid register access\n");
328}
329
330#define sci_in(up, offset) (up->serial_in(up, offset))
331#define sci_out(up, offset, value) (up->serial_out(up, offset, value))
332
333static int sci_probe_regmap(struct plat_sci_port *cfg)
334{
335 switch (cfg->type) {
336 case PORT_SCI:
337 cfg->regtype = SCIx_SCI_REGTYPE;
338 break;
339 case PORT_IRDA:
340 cfg->regtype = SCIx_IRDA_REGTYPE;
341 break;
342 case PORT_SCIFA:
343 cfg->regtype = SCIx_SCIFA_REGTYPE;
344 break;
345 case PORT_SCIFB:
346 cfg->regtype = SCIx_SCIFB_REGTYPE;
347 break;
348 case PORT_SCIF:
349 /*
350 * The SH-4 is a bit of a misnomer here, although that's
351 * where this particular port layout originated. This
352 * configuration (or some slight variation thereof)
353 * remains the dominant model for all SCIFs.
354 */
355 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
356 break;
357 default:
358 printk(KERN_ERR "Can't probe register map for given port\n");
359 return -EINVAL;
360 }
361
362 return 0;
363}
364
365static void sci_port_enable(struct sci_port *sci_port)
366{
367 if (!sci_port->port.dev)
368 return;
369
370 pm_runtime_get_sync(sci_port->port.dev);
371
372 clk_enable(sci_port->iclk);
373 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
374 clk_enable(sci_port->fclk);
375}
376
377static void sci_port_disable(struct sci_port *sci_port)
378{
379 if (!sci_port->port.dev)
380 return;
381
382 clk_disable(sci_port->fclk);
383 clk_disable(sci_port->iclk);
384
385 pm_runtime_put_sync(sci_port->port.dev);
386}
387
124#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 388#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
125 389
126#ifdef CONFIG_CONSOLE_POLL 390#ifdef CONFIG_CONSOLE_POLL
@@ -164,223 +428,76 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c)
164} 428}
165#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 429#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
166 430
167#if defined(__H8300H__) || defined(__H8300S__)
168static void sci_init_pins(struct uart_port *port, unsigned int cflag) 431static void sci_init_pins(struct uart_port *port, unsigned int cflag)
169{ 432{
170 int ch = (port->mapbase - SMR0) >> 3; 433 struct sci_port *s = to_sci_port(port);
171 434 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
172 /* set DDR regs */
173 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
174 h8300_sci_pins[ch].rx,
175 H8300_GPIO_INPUT);
176 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
177 h8300_sci_pins[ch].tx,
178 H8300_GPIO_OUTPUT);
179
180 /* tx mark output*/
181 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
182}
183#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
184static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
185{
186 if (port->mapbase == 0xA4400000) {
187 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
188 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
189 } else if (port->mapbase == 0xA4410000)
190 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
191}
192#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
193static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
194{
195 unsigned short data;
196
197 if (cflag & CRTSCTS) {
198 /* enable RTS/CTS */
199 if (port->mapbase == 0xa4430000) { /* SCIF0 */
200 /* Clear PTCR bit 9-2; enable all scif pins but sck */
201 data = __raw_readw(PORT_PTCR);
202 __raw_writew((data & 0xfc03), PORT_PTCR);
203 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
204 /* Clear PVCR bit 9-2 */
205 data = __raw_readw(PORT_PVCR);
206 __raw_writew((data & 0xfc03), PORT_PVCR);
207 }
208 } else {
209 if (port->mapbase == 0xa4430000) { /* SCIF0 */
210 /* Clear PTCR bit 5-2; enable only tx and rx */
211 data = __raw_readw(PORT_PTCR);
212 __raw_writew((data & 0xffc3), PORT_PTCR);
213 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
214 /* Clear PVCR bit 5-2 */
215 data = __raw_readw(PORT_PVCR);
216 __raw_writew((data & 0xffc3), PORT_PVCR);
217 }
218 }
219}
220#elif defined(CONFIG_CPU_SH3)
221/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
222static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
223{
224 unsigned short data;
225
226 /* We need to set SCPCR to enable RTS/CTS */
227 data = __raw_readw(SCPCR);
228 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
229 __raw_writew(data & 0x0fcf, SCPCR);
230
231 if (!(cflag & CRTSCTS)) {
232 /* We need to set SCPCR to enable RTS/CTS */
233 data = __raw_readw(SCPCR);
234 /* Clear out SCP7MD1,0, SCP4MD1,0,
235 Set SCP6MD1,0 = {01} (output) */
236 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
237 435
238 data = __raw_readb(SCPDR); 436 /*
239 /* Set /RTS2 (bit6) = 0 */ 437 * Use port-specific handler if provided.
240 __raw_writeb(data & 0xbf, SCPDR); 438 */
439 if (s->cfg->ops && s->cfg->ops->init_pins) {
440 s->cfg->ops->init_pins(port, cflag);
441 return;
241 } 442 }
242}
243#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
244static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
245{
246 unsigned short data;
247 443
248 if (port->mapbase == 0xffe00000) { 444 /*
249 data = __raw_readw(PSCR); 445 * For the generic path SCSPTR is necessary. Bail out if that's
250 data &= ~0x03cf; 446 * unavailable, too.
251 if (!(cflag & CRTSCTS)) 447 */
252 data |= 0x0340; 448 if (!reg->size)
449 return;
253 450
254 __raw_writew(data, PSCR);
255 }
256}
257#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
258 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
259 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
260 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
261 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
262 defined(CONFIG_CPU_SUBTYPE_SHX3)
263static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
264{
265 if (!(cflag & CRTSCTS))
266 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
267}
268#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
269static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
270{
271 if (!(cflag & CRTSCTS)) 451 if (!(cflag & CRTSCTS))
272 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */ 452 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */
273} 453}
274#else
275static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
276{
277 /* Nothing to do */
278}
279#endif
280 454
281#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ 455static int sci_txfill(struct uart_port *port)
282 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
283 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
284 defined(CONFIG_CPU_SUBTYPE_SH7786)
285static int scif_txfill(struct uart_port *port)
286{ 456{
287 return sci_in(port, SCTFDR) & 0xff; 457 struct plat_sci_reg *reg;
288}
289 458
290static int scif_txroom(struct uart_port *port) 459 reg = sci_getreg(port, SCTFDR);
291{ 460 if (reg->size)
292 return SCIF_TXROOM_MAX - scif_txfill(port);
293}
294
295static int scif_rxfill(struct uart_port *port)
296{
297 return sci_in(port, SCRFDR) & 0xff;
298}
299#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
300static int scif_txfill(struct uart_port *port)
301{
302 if (port->mapbase == 0xffe00000 ||
303 port->mapbase == 0xffe08000)
304 /* SCIF0/1*/
305 return sci_in(port, SCTFDR) & 0xff; 461 return sci_in(port, SCTFDR) & 0xff;
306 else 462
307 /* SCIF2 */ 463 reg = sci_getreg(port, SCFDR);
464 if (reg->size)
308 return sci_in(port, SCFDR) >> 8; 465 return sci_in(port, SCFDR) >> 8;
309}
310 466
311static int scif_txroom(struct uart_port *port) 467 return !(sci_in(port, SCxSR) & SCI_TDRE);
312{
313 if (port->mapbase == 0xffe00000 ||
314 port->mapbase == 0xffe08000)
315 /* SCIF0/1*/
316 return SCIF_TXROOM_MAX - scif_txfill(port);
317 else
318 /* SCIF2 */
319 return SCIF2_TXROOM_MAX - scif_txfill(port);
320} 468}
321 469
322static int scif_rxfill(struct uart_port *port) 470static int sci_txroom(struct uart_port *port)
323{
324 if ((port->mapbase == 0xffe00000) ||
325 (port->mapbase == 0xffe08000)) {
326 /* SCIF0/1*/
327 return sci_in(port, SCRFDR) & 0xff;
328 } else {
329 /* SCIF2 */
330 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
331 }
332}
333#elif defined(CONFIG_ARCH_SH7372)
334static int scif_txfill(struct uart_port *port)
335{ 471{
336 if (port->type == PORT_SCIFA) 472 return port->fifosize - sci_txfill(port);
337 return sci_in(port, SCFDR) >> 8;
338 else
339 return sci_in(port, SCTFDR);
340} 473}
341 474
342static int scif_txroom(struct uart_port *port) 475static int sci_rxfill(struct uart_port *port)
343{ 476{
344 return port->fifosize - scif_txfill(port); 477 struct plat_sci_reg *reg;
345}
346 478
347static int scif_rxfill(struct uart_port *port) 479 reg = sci_getreg(port, SCRFDR);
348{ 480 if (reg->size)
349 if (port->type == PORT_SCIFA) 481 return sci_in(port, SCRFDR) & 0xff;
350 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
351 else
352 return sci_in(port, SCRFDR);
353}
354#else
355static int scif_txfill(struct uart_port *port)
356{
357 return sci_in(port, SCFDR) >> 8;
358}
359 482
360static int scif_txroom(struct uart_port *port) 483 reg = sci_getreg(port, SCFDR);
361{ 484 if (reg->size)
362 return SCIF_TXROOM_MAX - scif_txfill(port); 485 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
363}
364 486
365static int scif_rxfill(struct uart_port *port) 487 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
366{
367 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
368} 488}
369#endif
370 489
371static int sci_txfill(struct uart_port *port) 490/*
491 * SCI helper for checking the state of the muxed port/RXD pins.
492 */
493static inline int sci_rxd_in(struct uart_port *port)
372{ 494{
373 return !(sci_in(port, SCxSR) & SCI_TDRE); 495 struct sci_port *s = to_sci_port(port);
374}
375 496
376static int sci_txroom(struct uart_port *port) 497 if (s->cfg->port_reg <= 0)
377{ 498 return 1;
378 return !sci_txfill(port);
379}
380 499
381static int sci_rxfill(struct uart_port *port) 500 return !!__raw_readb(s->cfg->port_reg);
382{
383 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
384} 501}
385 502
386/* ********************************************************************** * 503/* ********************************************************************** *
@@ -406,10 +523,7 @@ static void sci_transmit_chars(struct uart_port *port)
406 return; 523 return;
407 } 524 }
408 525
409 if (port->type == PORT_SCI) 526 count = sci_txroom(port);
410 count = sci_txroom(port);
411 else
412 count = scif_txroom(port);
413 527
414 do { 528 do {
415 unsigned char c; 529 unsigned char c;
@@ -464,13 +578,8 @@ static void sci_receive_chars(struct uart_port *port)
464 return; 578 return;
465 579
466 while (1) { 580 while (1) {
467 if (port->type == PORT_SCI)
468 count = sci_rxfill(port);
469 else
470 count = scif_rxfill(port);
471
472 /* Don't copy more bytes than there is room for in the buffer */ 581 /* Don't copy more bytes than there is room for in the buffer */
473 count = tty_buffer_request_room(tty, count); 582 count = tty_buffer_request_room(tty, sci_rxfill(port));
474 583
475 /* If for any reason we can't copy more data, we're done! */ 584 /* If for any reason we can't copy more data, we're done! */
476 if (count == 0) 585 if (count == 0)
@@ -561,8 +670,7 @@ static void sci_break_timer(unsigned long data)
561{ 670{
562 struct sci_port *port = (struct sci_port *)data; 671 struct sci_port *port = (struct sci_port *)data;
563 672
564 if (port->enable) 673 sci_port_enable(port);
565 port->enable(&port->port);
566 674
567 if (sci_rxd_in(&port->port) == 0) { 675 if (sci_rxd_in(&port->port) == 0) {
568 port->break_flag = 1; 676 port->break_flag = 1;
@@ -574,8 +682,7 @@ static void sci_break_timer(unsigned long data)
574 } else 682 } else
575 port->break_flag = 0; 683 port->break_flag = 0;
576 684
577 if (port->disable) 685 sci_port_disable(port);
578 port->disable(&port->port);
579} 686}
580 687
581static int sci_handle_errors(struct uart_port *port) 688static int sci_handle_errors(struct uart_port *port)
@@ -583,13 +690,19 @@ static int sci_handle_errors(struct uart_port *port)
583 int copied = 0; 690 int copied = 0;
584 unsigned short status = sci_in(port, SCxSR); 691 unsigned short status = sci_in(port, SCxSR);
585 struct tty_struct *tty = port->state->port.tty; 692 struct tty_struct *tty = port->state->port.tty;
693 struct sci_port *s = to_sci_port(port);
586 694
587 if (status & SCxSR_ORER(port)) { 695 /*
588 /* overrun error */ 696 * Handle overruns, if supported.
589 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 697 */
590 copied++; 698 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
699 if (status & (1 << s->cfg->overrun_bit)) {
700 /* overrun error */
701 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
702 copied++;
591 703
592 dev_notice(port->dev, "overrun error"); 704 dev_notice(port->dev, "overrun error");
705 }
593 } 706 }
594 707
595 if (status & SCxSR_FER(port)) { 708 if (status & SCxSR_FER(port)) {
@@ -637,12 +750,15 @@ static int sci_handle_errors(struct uart_port *port)
637static int sci_handle_fifo_overrun(struct uart_port *port) 750static int sci_handle_fifo_overrun(struct uart_port *port)
638{ 751{
639 struct tty_struct *tty = port->state->port.tty; 752 struct tty_struct *tty = port->state->port.tty;
753 struct sci_port *s = to_sci_port(port);
754 struct plat_sci_reg *reg;
640 int copied = 0; 755 int copied = 0;
641 756
642 if (port->type != PORT_SCIF) 757 reg = sci_getreg(port, SCLSR);
758 if (!reg->size)
643 return 0; 759 return 0;
644 760
645 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { 761 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
646 sci_out(port, SCLSR, 0); 762 sci_out(port, SCLSR, 0);
647 763
648 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 764 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
@@ -840,74 +956,102 @@ static int sci_notifier(struct notifier_block *self,
840 return NOTIFY_OK; 956 return NOTIFY_OK;
841} 957}
842 958
843static void sci_clk_enable(struct uart_port *port) 959static struct sci_irq_desc {
844{ 960 const char *desc;
845 struct sci_port *sci_port = to_sci_port(port); 961 irq_handler_t handler;
846 962} sci_irq_desc[] = {
847 pm_runtime_get_sync(port->dev); 963 /*
964 * Split out handlers, the default case.
965 */
966 [SCIx_ERI_IRQ] = {
967 .desc = "rx err",
968 .handler = sci_er_interrupt,
969 },
848 970
849 clk_enable(sci_port->iclk); 971 [SCIx_RXI_IRQ] = {
850 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 972 .desc = "rx full",
851 clk_enable(sci_port->fclk); 973 .handler = sci_rx_interrupt,
852} 974 },
853 975
854static void sci_clk_disable(struct uart_port *port) 976 [SCIx_TXI_IRQ] = {
855{ 977 .desc = "tx empty",
856 struct sci_port *sci_port = to_sci_port(port); 978 .handler = sci_tx_interrupt,
979 },
857 980
858 clk_disable(sci_port->fclk); 981 [SCIx_BRI_IRQ] = {
859 clk_disable(sci_port->iclk); 982 .desc = "break",
983 .handler = sci_br_interrupt,
984 },
860 985
861 pm_runtime_put_sync(port->dev); 986 /*
862} 987 * Special muxed handler.
988 */
989 [SCIx_MUX_IRQ] = {
990 .desc = "mux",
991 .handler = sci_mpxed_interrupt,
992 },
993};
863 994
864static int sci_request_irq(struct sci_port *port) 995static int sci_request_irq(struct sci_port *port)
865{ 996{
866 int i; 997 struct uart_port *up = &port->port;
867 irqreturn_t (*handlers[4])(int irq, void *ptr) = { 998 int i, j, ret = 0;
868 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, 999
869 sci_br_interrupt, 1000 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
870 }; 1001 struct sci_irq_desc *desc;
871 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", 1002 unsigned int irq;
872 "SCI Transmit Data Empty", "SCI Break" }; 1003
873 1004 if (SCIx_IRQ_IS_MUXED(port)) {
874 if (port->cfg->irqs[0] == port->cfg->irqs[1]) { 1005 i = SCIx_MUX_IRQ;
875 if (unlikely(!port->cfg->irqs[0])) 1006 irq = up->irq;
876 return -ENODEV; 1007 } else
877 1008 irq = port->cfg->irqs[i];
878 if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt, 1009
879 IRQF_DISABLED, "sci", port)) { 1010 desc = sci_irq_desc + i;
880 dev_err(port->port.dev, "Can't allocate IRQ\n"); 1011 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
881 return -ENODEV; 1012 dev_name(up->dev), desc->desc);
1013 if (!port->irqstr[j]) {
1014 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1015 desc->desc);
1016 goto out_nomem;
882 } 1017 }
883 } else { 1018
884 for (i = 0; i < ARRAY_SIZE(handlers); i++) { 1019 ret = request_irq(irq, desc->handler, up->irqflags,
885 if (unlikely(!port->cfg->irqs[i])) 1020 port->irqstr[j], port);
886 continue; 1021 if (unlikely(ret)) {
887 1022 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
888 if (request_irq(port->cfg->irqs[i], handlers[i], 1023 goto out_noirq;
889 IRQF_DISABLED, desc[i], port)) {
890 dev_err(port->port.dev, "Can't allocate IRQ\n");
891 return -ENODEV;
892 }
893 } 1024 }
894 } 1025 }
895 1026
896 return 0; 1027 return 0;
1028
1029out_noirq:
1030 while (--i >= 0)
1031 free_irq(port->cfg->irqs[i], port);
1032
1033out_nomem:
1034 while (--j >= 0)
1035 kfree(port->irqstr[j]);
1036
1037 return ret;
897} 1038}
898 1039
899static void sci_free_irq(struct sci_port *port) 1040static void sci_free_irq(struct sci_port *port)
900{ 1041{
901 int i; 1042 int i;
902 1043
903 if (port->cfg->irqs[0] == port->cfg->irqs[1]) 1044 /*
904 free_irq(port->cfg->irqs[0], port); 1045 * Intentionally in reverse order so we iterate over the muxed
905 else { 1046 * IRQ first.
906 for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) { 1047 */
907 if (!port->cfg->irqs[i]) 1048 for (i = 0; i < SCIx_NR_IRQS; i++) {
908 continue; 1049 free_irq(port->cfg->irqs[i], port);
1050 kfree(port->irqstr[i]);
909 1051
910 free_irq(port->cfg->irqs[i], port); 1052 if (SCIx_IRQ_IS_MUXED(port)) {
1053 /* If there's only one IRQ, we're done. */
1054 return;
911 } 1055 }
912 } 1056 }
913} 1057}
@@ -915,7 +1059,7 @@ static void sci_free_irq(struct sci_port *port)
915static unsigned int sci_tx_empty(struct uart_port *port) 1059static unsigned int sci_tx_empty(struct uart_port *port)
916{ 1060{
917 unsigned short status = sci_in(port, SCxSR); 1061 unsigned short status = sci_in(port, SCxSR);
918 unsigned short in_tx_fifo = scif_txfill(port); 1062 unsigned short in_tx_fifo = sci_txfill(port);
919 1063
920 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1064 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
921} 1065}
@@ -1438,8 +1582,7 @@ static int sci_startup(struct uart_port *port)
1438 1582
1439 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1583 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1440 1584
1441 if (s->enable) 1585 sci_port_enable(s);
1442 s->enable(port);
1443 1586
1444 ret = sci_request_irq(s); 1587 ret = sci_request_irq(s);
1445 if (unlikely(ret < 0)) 1588 if (unlikely(ret < 0))
@@ -1465,8 +1608,7 @@ static void sci_shutdown(struct uart_port *port)
1465 sci_free_dma(port); 1608 sci_free_dma(port);
1466 sci_free_irq(s); 1609 sci_free_irq(s);
1467 1610
1468 if (s->disable) 1611 sci_port_disable(s);
1469 s->disable(port);
1470} 1612}
1471 1613
1472static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, 1614static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
@@ -1513,8 +1655,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1513 if (likely(baud && port->uartclk)) 1655 if (likely(baud && port->uartclk))
1514 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); 1656 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
1515 1657
1516 if (s->enable) 1658 sci_port_enable(s);
1517 s->enable(port);
1518 1659
1519 do { 1660 do {
1520 status = sci_in(port, SCxSR); 1661 status = sci_in(port, SCxSR);
@@ -1584,8 +1725,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1584 if ((termios->c_cflag & CREAD) != 0) 1725 if ((termios->c_cflag & CREAD) != 0)
1585 sci_start_rx(port); 1726 sci_start_rx(port);
1586 1727
1587 if (s->disable) 1728 sci_port_disable(s);
1588 s->disable(port);
1589} 1729}
1590 1730
1591static const char *sci_type(struct uart_port *port) 1731static const char *sci_type(struct uart_port *port)
@@ -1726,6 +1866,7 @@ static int __devinit sci_init_single(struct platform_device *dev,
1726 struct plat_sci_port *p) 1866 struct plat_sci_port *p)
1727{ 1867{
1728 struct uart_port *port = &sci_port->port; 1868 struct uart_port *port = &sci_port->port;
1869 int ret;
1729 1870
1730 port->ops = &sci_uart_ops; 1871 port->ops = &sci_uart_ops;
1731 port->iotype = UPIO_MEM; 1872 port->iotype = UPIO_MEM;
@@ -1746,6 +1887,12 @@ static int __devinit sci_init_single(struct platform_device *dev,
1746 break; 1887 break;
1747 } 1888 }
1748 1889
1890 if (p->regtype == SCIx_PROBE_REGTYPE) {
1891 ret = sci_probe_regmap(p);
1892 if (unlikely(!ret))
1893 return ret;
1894 }
1895
1749 if (dev) { 1896 if (dev) {
1750 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 1897 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1751 if (IS_ERR(sci_port->iclk)) { 1898 if (IS_ERR(sci_port->iclk)) {
@@ -1764,8 +1911,6 @@ static int __devinit sci_init_single(struct platform_device *dev,
1764 if (IS_ERR(sci_port->fclk)) 1911 if (IS_ERR(sci_port->fclk))
1765 sci_port->fclk = NULL; 1912 sci_port->fclk = NULL;
1766 1913
1767 sci_port->enable = sci_clk_enable;
1768 sci_port->disable = sci_clk_disable;
1769 port->dev = &dev->dev; 1914 port->dev = &dev->dev;
1770 1915
1771 pm_runtime_enable(&dev->dev); 1916 pm_runtime_enable(&dev->dev);
@@ -1775,20 +1920,51 @@ static int __devinit sci_init_single(struct platform_device *dev,
1775 sci_port->break_timer.function = sci_break_timer; 1920 sci_port->break_timer.function = sci_break_timer;
1776 init_timer(&sci_port->break_timer); 1921 init_timer(&sci_port->break_timer);
1777 1922
1923 /*
1924 * Establish some sensible defaults for the error detection.
1925 */
1926 if (!p->error_mask)
1927 p->error_mask = (p->type == PORT_SCI) ?
1928 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
1929
1930 /*
1931 * Establish sensible defaults for the overrun detection, unless
1932 * the part has explicitly disabled support for it.
1933 */
1934 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
1935 if (p->type == PORT_SCI)
1936 p->overrun_bit = 5;
1937 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
1938 p->overrun_bit = 9;
1939 else
1940 p->overrun_bit = 0;
1941
1942 /*
1943 * Make the error mask inclusive of overrun detection, if
1944 * supported.
1945 */
1946 p->error_mask |= (1 << p->overrun_bit);
1947 }
1948
1778 sci_port->cfg = p; 1949 sci_port->cfg = p;
1779 1950
1780 port->mapbase = p->mapbase; 1951 port->mapbase = p->mapbase;
1781 port->type = p->type; 1952 port->type = p->type;
1782 port->flags = p->flags; 1953 port->flags = p->flags;
1954 port->regshift = p->regshift;
1783 1955
1784 /* 1956 /*
1785 * The UART port needs an IRQ value, so we peg this to the TX IRQ 1957 * The UART port needs an IRQ value, so we peg this to the RX IRQ
1786 * for the multi-IRQ ports, which is where we are primarily 1958 * for the multi-IRQ ports, which is where we are primarily
1787 * concerned with the shutdown path synchronization. 1959 * concerned with the shutdown path synchronization.
1788 * 1960 *
1789 * For the muxed case there's nothing more to do. 1961 * For the muxed case there's nothing more to do.
1790 */ 1962 */
1791 port->irq = p->irqs[SCIx_RXI_IRQ]; 1963 port->irq = p->irqs[SCIx_RXI_IRQ];
1964 port->irqflags = IRQF_DISABLED;
1965
1966 port->serial_in = sci_serial_in;
1967 port->serial_out = sci_serial_out;
1792 1968
1793 if (p->dma_dev) 1969 if (p->dma_dev)
1794 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n", 1970 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
@@ -1814,8 +1990,7 @@ static void serial_console_write(struct console *co, const char *s,
1814 struct uart_port *port = &sci_port->port; 1990 struct uart_port *port = &sci_port->port;
1815 unsigned short bits; 1991 unsigned short bits;
1816 1992
1817 if (sci_port->enable) 1993 sci_port_enable(sci_port);
1818 sci_port->enable(port);
1819 1994
1820 uart_console_write(port, s, count, serial_console_putchar); 1995 uart_console_write(port, s, count, serial_console_putchar);
1821 1996
@@ -1824,8 +1999,7 @@ static void serial_console_write(struct console *co, const char *s,
1824 while ((sci_in(port, SCxSR) & bits) != bits) 1999 while ((sci_in(port, SCxSR) & bits) != bits)
1825 cpu_relax(); 2000 cpu_relax();
1826 2001
1827 if (sci_port->disable) 2002 sci_port_disable(sci_port);
1828 sci_port->disable(port);
1829} 2003}
1830 2004
1831static int __devinit serial_console_setup(struct console *co, char *options) 2005static int __devinit serial_console_setup(struct console *co, char *options)
@@ -1857,20 +2031,13 @@ static int __devinit serial_console_setup(struct console *co, char *options)
1857 if (unlikely(ret != 0)) 2031 if (unlikely(ret != 0))
1858 return ret; 2032 return ret;
1859 2033
1860 if (sci_port->enable) 2034 sci_port_enable(sci_port);
1861 sci_port->enable(port);
1862 2035
1863 if (options) 2036 if (options)
1864 uart_parse_options(options, &baud, &parity, &bits, &flow); 2037 uart_parse_options(options, &baud, &parity, &bits, &flow);
1865 2038
1866 ret = uart_set_options(port, co, baud, parity, bits, flow);
1867#if defined(__H8300H__) || defined(__H8300S__)
1868 /* disable rx interrupt */
1869 if (ret == 0)
1870 sci_stop_rx(port);
1871#endif
1872 /* TODO: disable clock */ 2039 /* TODO: disable clock */
1873 return ret; 2040 return uart_set_options(port, co, baud, parity, bits, flow);
1874} 2041}
1875 2042
1876static struct console serial_console = { 2043static struct console serial_console = {
@@ -2081,3 +2248,5 @@ module_exit(sci_exit);
2081 2248
2082MODULE_LICENSE("GPL"); 2249MODULE_LICENSE("GPL");
2083MODULE_ALIAS("platform:sh-sci"); 2250MODULE_ALIAS("platform:sh-sci");
2251MODULE_AUTHOR("Paul Mundt");
2252MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index b04d937c9110..e9bed038aa1f 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -2,169 +2,14 @@
2#include <linux/io.h> 2#include <linux/io.h>
3#include <linux/gpio.h> 3#include <linux/gpio.h>
4 4
5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
11
12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
19# define SCIF0 0xA4400000
20# define SCIF2 0xA4410000
21# define SCPCR 0xA4000116
22# define SCPDR 0xA4000136
23#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
24 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
25 defined(CONFIG_ARCH_SH73A0) || \
26 defined(CONFIG_ARCH_SH7367) || \
27 defined(CONFIG_ARCH_SH7377) || \
28 defined(CONFIG_ARCH_SH7372)
29# define PORT_PTCR 0xA405011EUL
30# define PORT_PVCR 0xA4050122UL
31# define SCIF_ORER 0x0200 /* overrun error bit */
32#elif defined(CONFIG_SH_RTS7751R2D)
33# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
34# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
35# define SCIF_ORER 0x0001 /* overrun error bit */
36#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
38 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
39 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
40 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
41 defined(CONFIG_CPU_SUBTYPE_SH7751R)
42# define SCSPTR1 0xffe0001c /* 8 bit SCI */
43# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
44# define SCIF_ORER 0x0001 /* overrun error bit */
45#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
46# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
47# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
48# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
49# define SCIF_ORER 0x0001 /* overrun error bit */
50#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
51# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
52# define SCIF_ORER 0x0001 /* overrun error bit */
53# define PACR 0xa4050100
54# define PBCR 0xa4050102
55#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
56# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
57#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
58# define PADR 0xA4050120
59# define PSDR 0xA405013e
60# define PWDR 0xA4050166
61# define PSCR 0xA405011E
62# define SCIF_ORER 0x0001 /* overrun error bit */
63#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
64# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
65# define SCSPTR0 SCPDR0
66# define SCIF_ORER 0x0001 /* overrun error bit */
67#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
68# define SCSPTR0 0xa4050160
69# define SCIF_ORER 0x0001 /* overrun error bit */
70#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
71# define SCIF_ORER 0x0001 /* overrun error bit */
72#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
73# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
74# define SCIF_ORER 0x0001 /* overrun error bit */
75#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
76# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
77#elif defined(CONFIG_H8S2678)
78# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
79#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
80# define SCSPTR0 0xfe4b0020
81# define SCIF_ORER 0x0001
82#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
83# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
84# define SCIF_ORER 0x0001 /* overrun error bit */
85#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
86# define SCSPTR0 0xff923020 /* 16 bit SCIF */
87# define SCIF_ORER 0x0001 /* overrun error bit */
88#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
89# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
90# define SCIF_ORER 0x0001 /* Overrun error bit */
91#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
92 defined(CONFIG_CPU_SUBTYPE_SH7786)
93# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
94# define SCIF_ORER 0x0001 /* Overrun error bit */
95#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
96 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
97 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
98 defined(CONFIG_CPU_SUBTYPE_SH7263)
99# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
100#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
101# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
102# define SCIF_ORER 0x0001 /* overrun error bit */
103#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
104# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
105# define SCIF_ORER 0x0001 /* Overrun error bit */
106#else
107# error CPU subtype not defined
108#endif
109
110/* SCxSR SCI */
111#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
112#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
113#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
114#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
115#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
116#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
117/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
118/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
119
120#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
121
122/* SCxSR SCIF */
123#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
124#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
125#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
126#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
127#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
128#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
129#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
130#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
131
132#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
133 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
134 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
135 defined(CONFIG_ARCH_SH73A0) || \
136 defined(CONFIG_ARCH_SH7367) || \
137 defined(CONFIG_ARCH_SH7377) || \
138 defined(CONFIG_ARCH_SH7372)
139# define SCIF_ORER 0x0200
140# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
141# define SCIF_RFDC_MASK 0x007f
142# define SCIF_TXROOM_MAX 64
143#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
144# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
145# define SCIF_RFDC_MASK 0x007f
146# define SCIF_TXROOM_MAX 64
147/* SH7763 SCIF2 support */
148# define SCIF2_RFDC_MASK 0x001f
149# define SCIF2_TXROOM_MAX 16
150#else
151# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
152# define SCIF_RFDC_MASK 0x001f
153# define SCIF_TXROOM_MAX 16
154#endif
155
156#ifndef SCIF_ORER
157#define SCIF_ORER 0x0000
158#endif
159
160#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 5#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
161#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
162#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 6#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
163#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 7#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
164#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 8#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
165#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 9#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
166#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 10#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
167#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 11
12#define SCxSR_ERRORS(port) (to_sci_port(port)->cfg->error_mask)
168 13
169#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 14#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
170 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 15 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
@@ -191,278 +36,3 @@
191 36
192#define SCI_MAJOR 204 37#define SCI_MAJOR 204
193#define SCI_MINOR_START 8 38#define SCI_MINOR_START 8
194
195#define SCI_IN(size, offset) \
196 if ((size) == 8) { \
197 return ioread8(port->membase + (offset)); \
198 } else { \
199 return ioread16(port->membase + (offset)); \
200 }
201#define SCI_OUT(size, offset, value) \
202 if ((size) == 8) { \
203 iowrite8(value, port->membase + (offset)); \
204 } else if ((size) == 16) { \
205 iowrite16(value, port->membase + (offset)); \
206 }
207
208#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
209 static inline unsigned int sci_##name##_in(struct uart_port *port) \
210 { \
211 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
212 SCI_IN(scif_size, scif_offset) \
213 } else { /* PORT_SCI or PORT_SCIFA */ \
214 SCI_IN(sci_size, sci_offset); \
215 } \
216 } \
217 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
218 { \
219 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
220 SCI_OUT(scif_size, scif_offset, value) \
221 } else { /* PORT_SCI or PORT_SCIFA */ \
222 SCI_OUT(sci_size, sci_offset, value); \
223 } \
224 }
225
226#ifdef CONFIG_H8300
227/* h8300 don't have SCIF */
228#define CPU_SCIF_FNS(name) \
229 static inline unsigned int sci_##name##_in(struct uart_port *port) \
230 { \
231 return 0; \
232 } \
233 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
234 { \
235 }
236#else
237#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
238 static inline unsigned int sci_##name##_in(struct uart_port *port) \
239 { \
240 SCI_IN(scif_size, scif_offset); \
241 } \
242 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
243 { \
244 SCI_OUT(scif_size, scif_offset, value); \
245 }
246#endif
247
248#define CPU_SCI_FNS(name, sci_offset, sci_size) \
249 static inline unsigned int sci_##name##_in(struct uart_port* port) \
250 { \
251 SCI_IN(sci_size, sci_offset); \
252 } \
253 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
254 { \
255 SCI_OUT(sci_size, sci_offset, value); \
256 }
257
258#if defined(CONFIG_CPU_SH3) || \
259 defined(CONFIG_ARCH_SH73A0) || \
260 defined(CONFIG_ARCH_SH7367) || \
261 defined(CONFIG_ARCH_SH7377) || \
262 defined(CONFIG_ARCH_SH7372)
263#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
264#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
265 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
266 h8_sci_offset, h8_sci_size) \
267 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
268#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
269 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
270#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
271 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
272 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
273 defined(CONFIG_ARCH_SH7367)
274#define SCIF_FNS(name, scif_offset, scif_size) \
275 CPU_SCIF_FNS(name, scif_offset, scif_size)
276#elif defined(CONFIG_ARCH_SH7377) || \
277 defined(CONFIG_ARCH_SH7372) || \
278 defined(CONFIG_ARCH_SH73A0)
279#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
280 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
281#define SCIF_FNS(name, scif_offset, scif_size) \
282 CPU_SCIF_FNS(name, scif_offset, scif_size)
283#else
284#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
285 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
286 h8_sci_offset, h8_sci_size) \
287 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
288#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
289 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
290#endif
291#elif defined(__H8300H__) || defined(__H8300S__)
292#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
293 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
294 h8_sci_offset, h8_sci_size) \
295 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
296#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
297 CPU_SCIF_FNS(name)
298#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
299 defined(CONFIG_CPU_SUBTYPE_SH7724)
300 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
301 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
302 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
303 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
304#else
305#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
306 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
307 h8_sci_offset, h8_sci_size) \
308 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
309#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
310 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
311#endif
312
313#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
314 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
315 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
316 defined(CONFIG_ARCH_SH7367)
317
318SCIF_FNS(SCSMR, 0x00, 16)
319SCIF_FNS(SCBRR, 0x04, 8)
320SCIF_FNS(SCSCR, 0x08, 16)
321SCIF_FNS(SCxSR, 0x14, 16)
322SCIF_FNS(SCFCR, 0x18, 16)
323SCIF_FNS(SCFDR, 0x1c, 16)
324SCIF_FNS(SCxTDR, 0x20, 8)
325SCIF_FNS(SCxRDR, 0x24, 8)
326SCIF_FNS(SCLSR, 0x00, 0)
327#elif defined(CONFIG_ARCH_SH7377) || \
328 defined(CONFIG_ARCH_SH7372) || \
329 defined(CONFIG_ARCH_SH73A0)
330SCIF_FNS(SCSMR, 0x00, 16)
331SCIF_FNS(SCBRR, 0x04, 8)
332SCIF_FNS(SCSCR, 0x08, 16)
333SCIF_FNS(SCTDSR, 0x0c, 16)
334SCIF_FNS(SCFER, 0x10, 16)
335SCIF_FNS(SCxSR, 0x14, 16)
336SCIF_FNS(SCFCR, 0x18, 16)
337SCIF_FNS(SCFDR, 0x1c, 16)
338SCIF_FNS(SCTFDR, 0x38, 16)
339SCIF_FNS(SCRFDR, 0x3c, 16)
340SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
341SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
342SCIF_FNS(SCLSR, 0x00, 0)
343#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
344 defined(CONFIG_CPU_SUBTYPE_SH7724)
345SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
346SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
347SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
348SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
349SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
350SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
351SCIx_FNS(SCSPTR, 0, 0, 0, 0)
352SCIF_FNS(SCFCR, 0x18, 16)
353SCIF_FNS(SCFDR, 0x1c, 16)
354SCIF_FNS(SCLSR, 0x24, 16)
355#else
356/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
357/* name off sz off sz off sz off sz off sz*/
358SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
359SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
360SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
361SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
362SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
363SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
364SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
365#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
366 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
367 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
368 defined(CONFIG_CPU_SUBTYPE_SH7786)
369SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
370SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
371SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
372SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
373SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
374#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
375SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
376SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
377SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
378SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
379SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
380#else
381SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
382#if defined(CONFIG_CPU_SUBTYPE_SH7722)
383SCIF_FNS(SCSPTR, 0, 0, 0, 0)
384#else
385SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
386#endif
387SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
388#endif
389#endif
390#define sci_in(port, reg) sci_##reg##_in(port)
391#define sci_out(port, reg, value) sci_##reg##_out(port, value)
392
393/* H8/300 series SCI pins assignment */
394#if defined(__H8300H__) || defined(__H8300S__)
395static const struct __attribute__((packed)) {
396 int port; /* GPIO port no */
397 unsigned short rx,tx; /* GPIO bit no */
398} h8300_sci_pins[] = {
399#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
400 { /* SCI0 */
401 .port = H8300_GPIO_P9,
402 .rx = H8300_GPIO_B2,
403 .tx = H8300_GPIO_B0,
404 },
405 { /* SCI1 */
406 .port = H8300_GPIO_P9,
407 .rx = H8300_GPIO_B3,
408 .tx = H8300_GPIO_B1,
409 },
410 { /* SCI2 */
411 .port = H8300_GPIO_PB,
412 .rx = H8300_GPIO_B7,
413 .tx = H8300_GPIO_B6,
414 }
415#elif defined(CONFIG_H8S2678)
416 { /* SCI0 */
417 .port = H8300_GPIO_P3,
418 .rx = H8300_GPIO_B2,
419 .tx = H8300_GPIO_B0,
420 },
421 { /* SCI1 */
422 .port = H8300_GPIO_P3,
423 .rx = H8300_GPIO_B3,
424 .tx = H8300_GPIO_B1,
425 },
426 { /* SCI2 */
427 .port = H8300_GPIO_P5,
428 .rx = H8300_GPIO_B1,
429 .tx = H8300_GPIO_B0,
430 }
431#endif
432};
433#endif
434
435#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
436 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
437 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
438 defined(CONFIG_CPU_SUBTYPE_SH7709)
439static inline int sci_rxd_in(struct uart_port *port)
440{
441 if (port->mapbase == 0xfffffe80)
442 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
443 return 1;
444}
445#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
446 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
447 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
448 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
449 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
450 defined(CONFIG_CPU_SUBTYPE_SH7091)
451static inline int sci_rxd_in(struct uart_port *port)
452{
453 if (port->mapbase == 0xffe00000)
454 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
455 return 1;
456}
457#elif defined(__H8300H__) || defined(__H8300S__)
458static inline int sci_rxd_in(struct uart_port *port)
459{
460 int ch = (port->mapbase - SMR0) >> 3;
461 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
462}
463#else /* default case for non-SCI processors */
464static inline int sci_rxd_in(struct uart_port *port)
465{
466 return 1;
467}
468#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 18:36:51 -0500