aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-shmobile/clock-sh7367.c3
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c4
-rw-r--r--arch/arm/mach-shmobile/clock-sh7377.c3
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c4
-rw-r--r--arch/sh/Makefile1
-rw-r--r--arch/sh/boards/board-apsh4a3a.c2
-rw-r--r--arch/sh/boards/board-apsh4ad0a.c2
-rw-r--r--arch/sh/boards/board-sh7785lcr.c2
-rw-r--r--arch/sh/boards/board-urquell.c2
-rw-r--r--arch/sh/boards/mach-highlander/setup.c2
-rw-r--r--arch/sh/boards/mach-sdk7786/setup.c2
-rw-r--r--arch/sh/include/cpu-sh3/cpu/serial.h10
-rw-r--r--arch/sh/include/cpu-sh4a/cpu/serial.h7
-rw-r--r--arch/sh/kernel/cpu/clock-cpg.c2
-rw-r--r--arch/sh/kernel/cpu/sh3/Makefile18
-rw-r--r--arch/sh/kernel/cpu/sh3/serial-sh770x.c33
-rw-r--r--arch/sh/kernel/cpu/sh3/serial-sh7710.c20
-rw-r--r--arch/sh/kernel/cpu/sh3/serial-sh7720.c37
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c5
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c9
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c5
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4-202.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c4
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c4
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7343.c33
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c25
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c46
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c4
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c84
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c36
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7763.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7780.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c79
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c115
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-shx3.c67
-rw-r--r--arch/sh/kernel/cpu/sh4a/serial-sh7722.c23
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c1
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c7
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c9
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c9
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c3
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c3
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c8
-rw-r--r--drivers/dma/shdma.c88
-rw-r--r--drivers/dma/shdma.h4
-rw-r--r--drivers/sh/clk/core.c29
-rw-r--r--drivers/tty/serial/Kconfig2
-rw-r--r--drivers/tty/serial/sh-sci.c757
-rw-r--r--drivers/tty/serial/sh-sci.h434
-rw-r--r--include/linux/serial_sci.h75
-rw-r--r--include/linux/sh_clk.h4
-rw-r--r--include/linux/sh_dma.h8
54 files changed, 962 insertions, 1188 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index 6b186aefcbd6..5218c34a9cc6 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -259,9 +259,6 @@ static struct clk mstp_clks[MSTP_NR] = {
259 [CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */ 259 [CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
260}; 260};
261 261
262#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
263#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
264
265static struct clk_lookup lookups[] = { 262static struct clk_lookup lookups[] = {
266 /* main clocks */ 263 /* main clocks */
267 CLKDEV_CON_ID("r_clk", &r_clk), 264 CLKDEV_CON_ID("r_clk", &r_clk),
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 91f5779abdd3..6b1619a65dba 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -561,10 +561,6 @@ static struct clk mstp_clks[MSTP_NR] = {
561 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ 561 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
562}; 562};
563 563
564#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
565#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
566#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
567
568static struct clk_lookup lookups[] = { 564static struct clk_lookup lookups[] = {
569 /* main clocks */ 565 /* main clocks */
570 CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk), 566 CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
index 95942466e63f..8cee7b151ae3 100644
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -267,9 +267,6 @@ static struct clk mstp_clks[] = {
267 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ 267 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
268}; 268};
269 269
270#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
271#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
272
273static struct clk_lookup lookups[] = { 270static struct clk_lookup lookups[] = {
274 /* main clocks */ 271 /* main clocks */
275 CLKDEV_CON_ID("r_clk", &r_clk), 272 CLKDEV_CON_ID("r_clk", &r_clk),
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index bcacb1e8cf85..6db2ccabc2bf 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -306,10 +306,6 @@ static struct clk mstp_clks[MSTP_NR] = {
306 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ 306 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
307}; 307};
308 308
309#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
310#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
311#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
312
313static struct clk_lookup lookups[] = { 309static struct clk_lookup lookups[] = {
314 /* main clocks */ 310 /* main clocks */
315 CLKDEV_CON_ID("r_clk", &r_clk), 311 CLKDEV_CON_ID("r_clk", &r_clk),
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index e3d8170ad00b..99385d0b3f3b 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -173,6 +173,7 @@ core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/
173cpuincdir-$(CONFIG_CPU_SH2A) += cpu-sh2a 173cpuincdir-$(CONFIG_CPU_SH2A) += cpu-sh2a
174cpuincdir-$(CONFIG_CPU_SH2) += cpu-sh2 174cpuincdir-$(CONFIG_CPU_SH2) += cpu-sh2
175cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3 175cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3
176cpuincdir-$(CONFIG_CPU_SH4A) += cpu-sh4a
176cpuincdir-$(CONFIG_CPU_SH4) += cpu-sh4 177cpuincdir-$(CONFIG_CPU_SH4) += cpu-sh4
177cpuincdir-$(CONFIG_CPU_SH5) += cpu-sh5 178cpuincdir-$(CONFIG_CPU_SH5) += cpu-sh5
178cpuincdir-y += cpu-common # Must be last 179cpuincdir-y += cpu-common # Must be last
diff --git a/arch/sh/boards/board-apsh4a3a.c b/arch/sh/boards/board-apsh4a3a.c
index 8e2a27057bc9..2823619c6006 100644
--- a/arch/sh/boards/board-apsh4a3a.c
+++ b/arch/sh/boards/board-apsh4a3a.c
@@ -116,7 +116,7 @@ static int apsh4a3a_clk_init(void)
116 int ret; 116 int ret;
117 117
118 clk = clk_get(NULL, "extal"); 118 clk = clk_get(NULL, "extal");
119 if (!clk || IS_ERR(clk)) 119 if (IS_ERR(clk))
120 return PTR_ERR(clk); 120 return PTR_ERR(clk);
121 ret = clk_set_rate(clk, 33333000); 121 ret = clk_set_rate(clk, 33333000);
122 clk_put(clk); 122 clk_put(clk);
diff --git a/arch/sh/boards/board-apsh4ad0a.c b/arch/sh/boards/board-apsh4ad0a.c
index e2bd218a054e..b4d6292a9247 100644
--- a/arch/sh/boards/board-apsh4ad0a.c
+++ b/arch/sh/boards/board-apsh4ad0a.c
@@ -94,7 +94,7 @@ static int apsh4ad0a_clk_init(void)
94 int ret; 94 int ret;
95 95
96 clk = clk_get(NULL, "extal"); 96 clk = clk_get(NULL, "extal");
97 if (!clk || IS_ERR(clk)) 97 if (IS_ERR(clk))
98 return PTR_ERR(clk); 98 return PTR_ERR(clk);
99 ret = clk_set_rate(clk, 33333000); 99 ret = clk_set_rate(clk, 33333000);
100 clk_put(clk); 100 clk_put(clk);
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index ee65ff05c558..d879848f3cdd 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -299,7 +299,7 @@ static int sh7785lcr_clk_init(void)
299 int ret; 299 int ret;
300 300
301 clk = clk_get(NULL, "extal"); 301 clk = clk_get(NULL, "extal");
302 if (!clk || IS_ERR(clk)) 302 if (IS_ERR(clk))
303 return PTR_ERR(clk); 303 return PTR_ERR(clk);
304 ret = clk_set_rate(clk, 33333333); 304 ret = clk_set_rate(clk, 33333333);
305 clk_put(clk); 305 clk_put(clk);
diff --git a/arch/sh/boards/board-urquell.c b/arch/sh/boards/board-urquell.c
index d81c609decc7..24e3316c5c17 100644
--- a/arch/sh/boards/board-urquell.c
+++ b/arch/sh/boards/board-urquell.c
@@ -190,7 +190,7 @@ static int urquell_clk_init(void)
190 return -EINVAL; 190 return -EINVAL;
191 191
192 clk = clk_get(NULL, "extal"); 192 clk = clk_get(NULL, "extal");
193 if (!clk || IS_ERR(clk)) 193 if (IS_ERR(clk))
194 return PTR_ERR(clk); 194 return PTR_ERR(clk);
195 ret = clk_set_rate(clk, 33333333); 195 ret = clk_set_rate(clk, 33333333);
196 clk_put(clk); 196 clk_put(clk);
diff --git a/arch/sh/boards/mach-highlander/setup.c b/arch/sh/boards/mach-highlander/setup.c
index 87618c91d178..74b8db1b74a9 100644
--- a/arch/sh/boards/mach-highlander/setup.c
+++ b/arch/sh/boards/mach-highlander/setup.c
@@ -335,8 +335,6 @@ static struct clk *r7780rp_clocks[] = {
335 &ivdr_clk, 335 &ivdr_clk,
336}; 336};
337 337
338#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
339
340static struct clk_lookup lookups[] = { 338static struct clk_lookup lookups[] = {
341 /* main clocks */ 339 /* main clocks */
342 CLKDEV_CON_ID("ivdr_clk", &ivdr_clk), 340 CLKDEV_CON_ID("ivdr_clk", &ivdr_clk),
diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c
index 1521aa75ee3a..486d1ac3694c 100644
--- a/arch/sh/boards/mach-sdk7786/setup.c
+++ b/arch/sh/boards/mach-sdk7786/setup.c
@@ -194,7 +194,7 @@ static int sdk7786_clk_init(void)
194 return -EINVAL; 194 return -EINVAL;
195 195
196 clk = clk_get(NULL, "extal"); 196 clk = clk_get(NULL, "extal");
197 if (!clk || IS_ERR(clk)) 197 if (IS_ERR(clk))
198 return PTR_ERR(clk); 198 return PTR_ERR(clk);
199 ret = clk_set_rate(clk, 33333333); 199 ret = clk_set_rate(clk, 33333333);
200 clk_put(clk); 200 clk_put(clk);
diff --git a/arch/sh/include/cpu-sh3/cpu/serial.h b/arch/sh/include/cpu-sh3/cpu/serial.h
new file mode 100644
index 000000000000..7766329bc103
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/serial.h
@@ -0,0 +1,10 @@
1#ifndef __CPU_SH3_SERIAL_H
2#define __CPU_SH3_SERIAL_H
3
4#include <linux/serial_sci.h>
5
6extern struct plat_sci_port_ops sh770x_sci_port_ops;
7extern struct plat_sci_port_ops sh7710_sci_port_ops;
8extern struct plat_sci_port_ops sh7720_sci_port_ops;
9
10#endif /* __CPU_SH3_SERIAL_H */
diff --git a/arch/sh/include/cpu-sh4a/cpu/serial.h b/arch/sh/include/cpu-sh4a/cpu/serial.h
new file mode 100644
index 000000000000..ff1bc275d210
--- /dev/null
+++ b/arch/sh/include/cpu-sh4a/cpu/serial.h
@@ -0,0 +1,7 @@
1#ifndef __CPU_SH4A_SERIAL_H
2#define __CPU_SH4A_SERIAL_H
3
4/* arch/sh/kernel/cpu/sh4a/serial-sh7722.c */
5extern struct plat_sci_port_ops sh7722_sci_port_ops;
6
7#endif /* __CPU_SH4A_SERIAL_H */
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index 8f63a264a842..f59b1f30d44b 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -35,8 +35,6 @@ static struct clk *onchip_clocks[] = {
35 &cpu_clk, 35 &cpu_clk,
36}; 36};
37 37
38#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
39
40static struct clk_lookup lookups[] = { 38static struct clk_lookup lookups[] = {
41 /* main clocks */ 39 /* main clocks */
42 CLKDEV_CON_ID("master_clk", &master_clk), 40 CLKDEV_CON_ID("master_clk", &master_clk),
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index ecab274141a8..6f13f33a35ff 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -7,15 +7,15 @@ obj-y := ex.o probe.o entry.o setup-sh3.o
7obj-$(CONFIG_HIBERNATION) += swsusp.o 7obj-$(CONFIG_HIBERNATION) += swsusp.o
8 8
9# CPU subtype setup 9# CPU subtype setup
10obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o serial-sh770x.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh770x.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh770x.o serial-sh770x.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7707) += setup-sh770x.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7707) += setup-sh770x.o serial-sh770x.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh770x.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh770x.o serial-sh770x.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh770x.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh770x.o serial-sh770x.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o serial-sh7710.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o 16obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o serial-sh7710.o
17obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o 17obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o serial-sh7720.o
18obj-$(CONFIG_CPU_SUBTYPE_SH7721) += setup-sh7720.o 18obj-$(CONFIG_CPU_SUBTYPE_SH7721) += setup-sh7720.o serial-sh7720.o
19 19
20# Primary on-chip clocks (common) 20# Primary on-chip clocks (common)
21clock-$(CONFIG_CPU_SH3) := clock-sh3.o 21clock-$(CONFIG_CPU_SH3) := clock-sh3.o
diff --git a/arch/sh/kernel/cpu/sh3/serial-sh770x.c b/arch/sh/kernel/cpu/sh3/serial-sh770x.c
new file mode 100644
index 000000000000..4f7242c676b3
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/serial-sh770x.c
@@ -0,0 +1,33 @@
1#include <linux/serial_sci.h>
2#include <linux/serial_core.h>
3#include <linux/io.h>
4#include <cpu/serial.h>
5
6#define SCPCR 0xA4000116
7#define SCPDR 0xA4000136
8
9static void sh770x_sci_init_pins(struct uart_port *port, unsigned int cflag)
10{
11 unsigned short data;
12
13 /* We need to set SCPCR to enable RTS/CTS */
14 data = __raw_readw(SCPCR);
15 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
16 __raw_writew(data & 0x0fcf, SCPCR);
17
18 if (!(cflag & CRTSCTS)) {
19 /* We need to set SCPCR to enable RTS/CTS */
20 data = __raw_readw(SCPCR);
21 /* Clear out SCP7MD1,0, SCP4MD1,0,
22 Set SCP6MD1,0 = {01} (output) */
23 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
24
25 data = __raw_readb(SCPDR);
26 /* Set /RTS2 (bit6) = 0 */
27 __raw_writeb(data & 0xbf, SCPDR);
28 }
29}
30
31struct plat_sci_port_ops sh770x_sci_port_ops = {
32 .init_pins = sh770x_sci_init_pins,
33};
diff --git a/arch/sh/kernel/cpu/sh3/serial-sh7710.c b/arch/sh/kernel/cpu/sh3/serial-sh7710.c
new file mode 100644
index 000000000000..42190ef6aebf
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/serial-sh7710.c
@@ -0,0 +1,20 @@
1#include <linux/serial_sci.h>
2#include <linux/serial_core.h>
3#include <linux/io.h>
4#include <cpu/serial.h>
5
6#define PACR 0xa4050100
7#define PBCR 0xa4050102
8
9static void sh7710_sci_init_pins(struct uart_port *port, unsigned int cflag)
10{
11 if (port->mapbase == 0xA4400000) {
12 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
13 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
14 } else if (port->mapbase == 0xA4410000)
15 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
16}
17
18struct plat_sci_port_ops sh7710_sci_port_ops = {
19 .init_pins = sh7710_sci_init_pins,
20};
diff --git a/arch/sh/kernel/cpu/sh3/serial-sh7720.c b/arch/sh/kernel/cpu/sh3/serial-sh7720.c
new file mode 100644
index 000000000000..8832c526cdf9
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/serial-sh7720.c
@@ -0,0 +1,37 @@
1#include <linux/serial_sci.h>
2#include <linux/serial_core.h>
3#include <linux/io.h>
4#include <cpu/serial.h>
5#include <asm/gpio.h>
6
7static void sh7720_sci_init_pins(struct uart_port *port, unsigned int cflag)
8{
9 unsigned short data;
10
11 if (cflag & CRTSCTS) {
12 /* enable RTS/CTS */
13 if (port->mapbase == 0xa4430000) { /* SCIF0 */
14 /* Clear PTCR bit 9-2; enable all scif pins but sck */
15 data = __raw_readw(PORT_PTCR);
16 __raw_writew((data & 0xfc03), PORT_PTCR);
17 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
18 /* Clear PVCR bit 9-2 */
19 data = __raw_readw(PORT_PVCR);
20 __raw_writew((data & 0xfc03), PORT_PVCR);
21 }
22 } else {
23 if (port->mapbase == 0xa4430000) { /* SCIF0 */
24 /* Clear PTCR bit 5-2; enable only tx and rx */
25 data = __raw_readw(PORT_PTCR);
26 __raw_writew((data & 0xffc3), PORT_PTCR);
27 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
28 /* Clear PVCR bit 5-2 */
29 data = __raw_readw(PORT_PVCR);
30 __raw_writew((data & 0xffc3), PORT_PVCR);
31 }
32 }
33}
34
35struct plat_sci_port_ops sh7720_sci_port_ops = {
36 .init_pins = sh7720_sci_init_pins,
37};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index cd2e702feb7e..2309618c015d 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -15,6 +15,7 @@
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17#include <asm/rtc.h> 17#include <asm/rtc.h>
18#include <cpu/serial.h>
18 19
19enum { 20enum {
20 UNUSED = 0, 21 UNUSED = 0,
@@ -75,6 +76,8 @@ static struct plat_sci_port scif0_platform_data = {
75 .scbrr_algo_id = SCBRR_ALGO_4, 76 .scbrr_algo_id = SCBRR_ALGO_4,
76 .type = PORT_SCIF, 77 .type = PORT_SCIF,
77 .irqs = { 56, 56, 56 }, 78 .irqs = { 56, 56, 56 },
79 .ops = &sh770x_sci_port_ops,
80 .regtype = SCIx_SH7705_SCIF_REGTYPE,
78}; 81};
79 82
80static struct platform_device scif0_device = { 83static struct platform_device scif0_device = {
@@ -92,6 +95,8 @@ static struct plat_sci_port scif1_platform_data = {
92 .scbrr_algo_id = SCBRR_ALGO_4, 95 .scbrr_algo_id = SCBRR_ALGO_4,
93 .type = PORT_SCIF, 96 .type = PORT_SCIF,
94 .irqs = { 52, 52, 52 }, 97 .irqs = { 52, 52, 52 },
98 .ops = &sh770x_sci_port_ops,
99 .regtype = SCIx_SH7705_SCIF_REGTYPE,
95}; 100};
96 101
97static struct platform_device scif1_device = { 102static struct platform_device scif1_device = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 4551ad647c2c..3f3d5fe5892d 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -19,6 +19,7 @@
19#include <linux/serial.h> 19#include <linux/serial.h>
20#include <linux/serial_sci.h> 20#include <linux/serial_sci.h>
21#include <linux/sh_timer.h> 21#include <linux/sh_timer.h>
22#include <cpu/serial.h>
22 23
23enum { 24enum {
24 UNUSED = 0, 25 UNUSED = 0,
@@ -108,11 +109,14 @@ static struct platform_device rtc_device = {
108 109
109static struct plat_sci_port scif0_platform_data = { 110static struct plat_sci_port scif0_platform_data = {
110 .mapbase = 0xfffffe80, 111 .mapbase = 0xfffffe80,
112 .port_reg = 0xa4000136,
111 .flags = UPF_BOOT_AUTOCONF, 113 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_TE | SCSCR_RE, 114 .scscr = SCSCR_TE | SCSCR_RE,
113 .scbrr_algo_id = SCBRR_ALGO_2, 115 .scbrr_algo_id = SCBRR_ALGO_2,
114 .type = PORT_SCI, 116 .type = PORT_SCI,
115 .irqs = { 23, 23, 23, 0 }, 117 .irqs = { 23, 23, 23, 0 },
118 .ops = &sh770x_sci_port_ops,
119 .regshift = 1,
116}; 120};
117 121
118static struct platform_device scif0_device = { 122static struct platform_device scif0_device = {
@@ -132,6 +136,8 @@ static struct plat_sci_port scif1_platform_data = {
132 .scbrr_algo_id = SCBRR_ALGO_2, 136 .scbrr_algo_id = SCBRR_ALGO_2,
133 .type = PORT_SCIF, 137 .type = PORT_SCIF,
134 .irqs = { 56, 56, 56, 56 }, 138 .irqs = { 56, 56, 56, 56 },
139 .ops = &sh770x_sci_port_ops,
140 .regtype = SCIx_SH3_SCIF_REGTYPE,
135}; 141};
136 142
137static struct platform_device scif1_device = { 143static struct platform_device scif1_device = {
@@ -146,11 +152,14 @@ static struct platform_device scif1_device = {
146 defined(CONFIG_CPU_SUBTYPE_SH7709) 152 defined(CONFIG_CPU_SUBTYPE_SH7709)
147static struct plat_sci_port scif2_platform_data = { 153static struct plat_sci_port scif2_platform_data = {
148 .mapbase = 0xa4000140, 154 .mapbase = 0xa4000140,
155 .port_reg = SCIx_NOT_SUPPORTED,
149 .flags = UPF_BOOT_AUTOCONF, 156 .flags = UPF_BOOT_AUTOCONF,
150 .scscr = SCSCR_TE | SCSCR_RE, 157 .scscr = SCSCR_TE | SCSCR_RE,
151 .scbrr_algo_id = SCBRR_ALGO_2, 158 .scbrr_algo_id = SCBRR_ALGO_2,
152 .type = PORT_IRDA, 159 .type = PORT_IRDA,
153 .irqs = { 52, 52, 52, 52 }, 160 .irqs = { 52, 52, 52, 52 },
161 .ops = &sh770x_sci_port_ops,
162 .regshift = 1,
154}; 163};
155 164
156static struct platform_device scif2_device = { 165static struct platform_device scif2_device = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 365b94a6fcb7..94920345c14d 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -20,6 +20,7 @@
20#include <linux/serial_sci.h> 20#include <linux/serial_sci.h>
21#include <linux/sh_timer.h> 21#include <linux/sh_timer.h>
22#include <asm/rtc.h> 22#include <asm/rtc.h>
23#include <cpu/serial.h>
23 24
24static struct resource rtc_resources[] = { 25static struct resource rtc_resources[] = {
25 [0] = { 26 [0] = {
@@ -55,6 +56,8 @@ static struct plat_sci_port scif0_platform_data = {
55 .scbrr_algo_id = SCBRR_ALGO_4, 56 .scbrr_algo_id = SCBRR_ALGO_4,
56 .type = PORT_SCIF, 57 .type = PORT_SCIF,
57 .irqs = { 80, 80, 80, 80 }, 58 .irqs = { 80, 80, 80, 80 },
59 .ops = &sh7720_sci_port_ops,
60 .regtype = SCIx_SH7705_SCIF_REGTYPE,
58}; 61};
59 62
60static struct platform_device scif0_device = { 63static struct platform_device scif0_device = {
@@ -72,6 +75,8 @@ static struct plat_sci_port scif1_platform_data = {
72 .scbrr_algo_id = SCBRR_ALGO_4, 75 .scbrr_algo_id = SCBRR_ALGO_4,
73 .type = PORT_SCIF, 76 .type = PORT_SCIF,
74 .irqs = { 81, 81, 81, 81 }, 77 .irqs = { 81, 81, 81, 81 },
78 .ops = &sh7720_sci_port_ops,
79 .regtype = SCIx_SH7705_SCIF_REGTYPE,
75}; 80};
76 81
77static struct platform_device scif1_device = { 82static struct platform_device scif1_device = {
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index 3f6f8e98635c..f4e262adb39e 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -147,8 +147,6 @@ static struct clk *sh4202_onchip_clocks[] = {
147 &sh4202_shoc_clk, 147 &sh4202_shoc_clk,
148}; 148};
149 149
150#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
151
152static struct clk_lookup lookups[] = { 150static struct clk_lookup lookups[] = {
153 /* main clocks */ 151 /* main clocks */
154 CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk), 152 CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk),
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index e53b4b38bd11..98cc0c794c76 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * SH7750/SH7751 Setup 2 * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup
3 * 3 *
4 * Copyright (C) 2006 Paul Mundt 4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2006 Jamie Lenehan 5 * Copyright (C) 2006 Jamie Lenehan
@@ -38,11 +38,13 @@ static struct platform_device rtc_device = {
38 38
39static struct plat_sci_port sci_platform_data = { 39static struct plat_sci_port sci_platform_data = {
40 .mapbase = 0xffe00000, 40 .mapbase = 0xffe00000,
41 .port_reg = 0xffe0001C,
41 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
42 .scscr = SCSCR_TE | SCSCR_RE, 43 .scscr = SCSCR_TE | SCSCR_RE,
43 .scbrr_algo_id = SCBRR_ALGO_2, 44 .scbrr_algo_id = SCBRR_ALGO_2,
44 .type = PORT_SCI, 45 .type = PORT_SCI,
45 .irqs = { 23, 23, 23, 0 }, 46 .irqs = { 23, 23, 23, 0 },
47 .regshift = 2,
46}; 48};
47 49
48static struct platform_device sci_device = { 50static struct platform_device sci_device = {
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 78bbf232e391..c0b4c774700e 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -133,6 +133,7 @@ static struct plat_sci_port scif0_platform_data = {
133 .scbrr_algo_id = SCBRR_ALGO_2, 133 .scbrr_algo_id = SCBRR_ALGO_2,
134 .type = PORT_SCIF, 134 .type = PORT_SCIF,
135 .irqs = { 52, 53, 55, 54 }, 135 .irqs = { 52, 53, 55, 54 },
136 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
136}; 137};
137 138
138static struct platform_device scif0_device = { 139static struct platform_device scif0_device = {
@@ -150,6 +151,7 @@ static struct plat_sci_port scif1_platform_data = {
150 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 151 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
151 .scbrr_algo_id = SCBRR_ALGO_2, 152 .scbrr_algo_id = SCBRR_ALGO_2,
152 .irqs = { 72, 73, 75, 74 }, 153 .irqs = { 72, 73, 75, 74 },
154 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
153}; 155};
154 156
155static struct platform_device scif1_device = { 157static struct platform_device scif1_device = {
@@ -167,6 +169,7 @@ static struct plat_sci_port scif2_platform_data = {
167 .scbrr_algo_id = SCBRR_ALGO_2, 169 .scbrr_algo_id = SCBRR_ALGO_2,
168 .type = PORT_SCIF, 170 .type = PORT_SCIF,
169 .irqs = { 76, 77, 79, 78 }, 171 .irqs = { 76, 77, 79, 78 },
172 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
170}; 173};
171 174
172static struct platform_device scif2_device = { 175static struct platform_device scif2_device = {
@@ -184,6 +187,7 @@ static struct plat_sci_port scif3_platform_data = {
184 .scbrr_algo_id = SCBRR_ALGO_2, 187 .scbrr_algo_id = SCBRR_ALGO_2,
185 .type = PORT_SCI, 188 .type = PORT_SCI,
186 .irqs = { 80, 81, 82, 0 }, 189 .irqs = { 80, 81, 82, 0 },
190 .regshift = 2,
187}; 191};
188 192
189static struct platform_device scif3_device = { 193static struct platform_device scif3_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index cc122b1d3035..c57fb287011e 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o 16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 93c646072c1b..70e45bdaadc7 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -194,8 +194,6 @@ static struct clk mstp_clks[MSTP_NR] = {
194 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), 194 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
195}; 195};
196 196
197#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
198
199static struct clk_lookup lookups[] = { 197static struct clk_lookup lookups[] = {
200 /* main clocks */ 198 /* main clocks */
201 CLKDEV_CON_ID("rclk", &r_clk), 199 CLKDEV_CON_ID("rclk", &r_clk),
@@ -233,32 +231,17 @@ static struct clk_lookup lookups[] = {
233 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]), 231 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
234 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]), 232 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
235 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]), 233 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
236 { 234
237 /* SCIF0 */ 235 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP007]),
238 .dev_id = "sh-sci.0", 236 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP006]),
239 .con_id = "sci_fck", 237 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP005]),
240 .clk = &mstp_clks[MSTP007], 238 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP004]),
241 }, { 239
242 /* SCIF1 */
243 .dev_id = "sh-sci.1",
244 .con_id = "sci_fck",
245 .clk = &mstp_clks[MSTP006],
246 }, {
247 /* SCIF2 */
248 .dev_id = "sh-sci.2",
249 .con_id = "sci_fck",
250 .clk = &mstp_clks[MSTP005],
251 }, {
252 /* SCIF3 */
253 .dev_id = "sh-sci.3",
254 .con_id = "sci_fck",
255 .clk = &mstp_clks[MSTP004],
256 },
257 CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]), 240 CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
258 CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]), 241 CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
259 CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]), 242 CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
260 CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]), 243 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP109]),
261 CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]), 244 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP108]),
262 CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]), 245 CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
263 CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]), 246 CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
264 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]), 247 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 049dc0628ccc..3c3165000c52 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -192,8 +192,6 @@ static struct clk mstp_clks[MSTP_NR] = {
192 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), 192 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
193}; 193};
194 194
195#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
196
197static struct clk_lookup lookups[] = { 195static struct clk_lookup lookups[] = {
198 /* main clocks */ 196 /* main clocks */
199 CLKDEV_CON_ID("rclk", &r_clk), 197 CLKDEV_CON_ID("rclk", &r_clk),
@@ -231,25 +229,14 @@ static struct clk_lookup lookups[] = {
231 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]), 229 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
232 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]), 230 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
233 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]), 231 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
234 { 232
235 /* SCIF0 */ 233 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP007]),
236 .dev_id = "sh-sci.0", 234 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP006]),
237 .con_id = "sci_fck", 235 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP005]),
238 .clk = &mstp_clks[MSTP007], 236
239 }, {
240 /* SCIF1 */
241 .dev_id = "sh-sci.1",
242 .con_id = "sci_fck",
243 .clk = &mstp_clks[MSTP006],
244 }, {
245 /* SCIF2 */
246 .dev_id = "sh-sci.2",
247 .con_id = "sci_fck",
248 .clk = &mstp_clks[MSTP005],
249 },
250 CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]), 237 CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
251 CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]), 238 CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
252 CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]), 239 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP109]),
253 CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]), 240 CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
254 CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]), 241 CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
255 CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]), 242 CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 9d23a36f0647..c9a48088ad47 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -175,8 +175,6 @@ static struct clk mstp_clks[HWBLK_NR] = {
175 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0), 175 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
176}; 176};
177 177
178#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
179
180static struct clk_lookup lookups[] = { 178static struct clk_lookup lookups[] = {
181 /* main clocks */ 179 /* main clocks */
182 CLKDEV_CON_ID("rclk", &r_clk), 180 CLKDEV_CON_ID("rclk", &r_clk),
@@ -201,42 +199,20 @@ static struct clk_lookup lookups[] = {
201 /* MSTP clocks */ 199 /* MSTP clocks */
202 CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]), 200 CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
203 CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]), 201 CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
204 { 202
205 /* TMU0 */ 203 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU]),
206 .dev_id = "sh_tmu.0", 204 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU]),
207 .con_id = "tmu_fck", 205 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]),
208 .clk = &mstp_clks[HWBLK_TMU], 206
209 }, {
210 /* TMU1 */
211 .dev_id = "sh_tmu.1",
212 .con_id = "tmu_fck",
213 .clk = &mstp_clks[HWBLK_TMU],
214 }, {
215 /* TMU2 */
216 .dev_id = "sh_tmu.2",
217 .con_id = "tmu_fck",
218 .clk = &mstp_clks[HWBLK_TMU],
219 },
220 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 207 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
221 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 208 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
222 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), 209 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
223 { 210
224 /* SCIF0 */ 211 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
225 .dev_id = "sh-sci.0", 212 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
226 .con_id = "sci_fck", 213 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
227 .clk = &mstp_clks[HWBLK_SCIF0], 214
228 }, { 215 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
229 /* SCIF1 */
230 .dev_id = "sh-sci.1",
231 .con_id = "sci_fck",
232 .clk = &mstp_clks[HWBLK_SCIF1],
233 }, {
234 /* SCIF2 */
235 .dev_id = "sh-sci.2",
236 .con_id = "sci_fck",
237 .clk = &mstp_clks[HWBLK_SCIF2],
238 },
239 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
240 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 216 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
241 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]), 217 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
242 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 218 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 55493cd5bd8f..3cc3827380e3 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -200,8 +200,6 @@ static struct clk mstp_clks[] = {
200 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 200 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
201}; 201};
202 202
203#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
204
205static struct clk_lookup lookups[] = { 203static struct clk_lookup lookups[] = {
206 /* main clocks */ 204 /* main clocks */
207 CLKDEV_CON_ID("rclk", &r_clk), 205 CLKDEV_CON_ID("rclk", &r_clk),
@@ -305,7 +303,7 @@ static struct clk_lookup lookups[] = {
305 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]), 303 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
306 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]), 304 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
307 CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]), 305 CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
308 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]), 306 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
309 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 307 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
310 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 308 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
311 CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]), 309 CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index d08fa953c88b..8668f557e0ac 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -252,8 +252,6 @@ static struct clk mstp_clks[HWBLK_NR] = {
252 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 252 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
253}; 253};
254 254
255#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
256
257static struct clk_lookup lookups[] = { 255static struct clk_lookup lookups[] = {
258 /* main clocks */ 256 /* main clocks */
259 CLKDEV_CON_ID("rclk", &r_clk), 257 CLKDEV_CON_ID("rclk", &r_clk),
@@ -289,77 +287,31 @@ static struct clk_lookup lookups[] = {
289 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 287 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
290 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 288 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
291 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 289 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
292 { 290
293 /* TMU0 */ 291 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU0]),
294 .dev_id = "sh_tmu.0", 292 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU0]),
295 .con_id = "tmu_fck", 293 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU0]),
296 .clk = &mstp_clks[HWBLK_TMU0], 294 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
297 }, { 295
298 /* TMU1 */
299 .dev_id = "sh_tmu.1",
300 .con_id = "tmu_fck",
301 .clk = &mstp_clks[HWBLK_TMU0],
302 }, {
303 /* TMU2 */
304 .dev_id = "sh_tmu.2",
305 .con_id = "tmu_fck",
306 .clk = &mstp_clks[HWBLK_TMU0],
307 }, {
308 /* TMU3 */
309 .dev_id = "sh_tmu.3",
310 .con_id = "tmu_fck",
311 .clk = &mstp_clks[HWBLK_TMU1],
312 },
313 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 296 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
314 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 297 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
315 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 298 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
316 { 299
317 /* TMU4 */ 300 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
318 .dev_id = "sh_tmu.4", 301 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
319 .con_id = "tmu_fck", 302 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
320 .clk = &mstp_clks[HWBLK_TMU1], 303 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
321 }, { 304 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
322 /* TMU5 */ 305 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
323 .dev_id = "sh_tmu.5", 306 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
324 .con_id = "tmu_fck", 307 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
325 .clk = &mstp_clks[HWBLK_TMU1], 308
326 }, {
327 /* SCIF0 */
328 .dev_id = "sh-sci.0",
329 .con_id = "sci_fck",
330 .clk = &mstp_clks[HWBLK_SCIF0],
331 }, {
332 /* SCIF1 */
333 .dev_id = "sh-sci.1",
334 .con_id = "sci_fck",
335 .clk = &mstp_clks[HWBLK_SCIF1],
336 }, {
337 /* SCIF2 */
338 .dev_id = "sh-sci.2",
339 .con_id = "sci_fck",
340 .clk = &mstp_clks[HWBLK_SCIF2],
341 }, {
342 /* SCIF3 */
343 .dev_id = "sh-sci.3",
344 .con_id = "sci_fck",
345 .clk = &mstp_clks[HWBLK_SCIF3],
346 }, {
347 /* SCIF4 */
348 .dev_id = "sh-sci.4",
349 .con_id = "sci_fck",
350 .clk = &mstp_clks[HWBLK_SCIF4],
351 }, {
352 /* SCIF5 */
353 .dev_id = "sh-sci.5",
354 .con_id = "sci_fck",
355 .clk = &mstp_clks[HWBLK_SCIF5],
356 },
357 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]), 309 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
358 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]), 310 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
359 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 311 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
360 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 312 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
361 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC0]), 313 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]),
362 CLKDEV_CON_ID("i2c1", &mstp_clks[HWBLK_IIC1]), 314 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]),
363 CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]), 315 CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]),
364 CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]), 316 CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]),
365 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 317 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index eedddad13835..3b097b09a3ba 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -101,8 +101,6 @@ static struct clk mstp_clks[MSTP_NR] = {
101 [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0), 101 [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
102}; 102};
103 103
104#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
105
106static struct clk_lookup lookups[] = { 104static struct clk_lookup lookups[] = {
107 /* main clocks */ 105 /* main clocks */
108 CLKDEV_CON_ID("extal", &extal_clk), 106 CLKDEV_CON_ID("extal", &extal_clk),
@@ -116,33 +114,13 @@ static struct clk_lookup lookups[] = {
116 /* MSTP32 clocks */ 114 /* MSTP32 clocks */
117 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]), 115 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]),
118 CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]), 116 CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]),
119 { 117
120 /* TMU0 */ 118 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP113]),
121 .dev_id = "sh_tmu.0", 119 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP114]),
122 .con_id = "tmu_fck", 120 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP112]),
123 .clk = &mstp_clks[MSTP113], 121 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP111]),
124 }, { 122 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP110]),
125 /* TMU1 */ 123
126 .dev_id = "sh_tmu.1",
127 .con_id = "tmu_fck",
128 .clk = &mstp_clks[MSTP114],
129 },
130 {
131 /* SCIF4 (But, ID is 2) */
132 .dev_id = "sh-sci.2",
133 .con_id = "sci_fck",
134 .clk = &mstp_clks[MSTP112],
135 }, {
136 /* SCIF3 */
137 .dev_id = "sh-sci.1",
138 .con_id = "sci_fck",
139 .clk = &mstp_clks[MSTP111],
140 }, {
141 /* SCIF2 */
142 .dev_id = "sh-sci.0",
143 .con_id = "sci_fck",
144 .clk = &mstp_clks[MSTP110],
145 },
146 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]), 124 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]),
147 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]), 125 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
148}; 126};
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 599630fc4d3b..2d4c7fd79c02 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -91,8 +91,6 @@ static struct clk *sh7763_onchip_clocks[] = {
91 &sh7763_shyway_clk, 91 &sh7763_shyway_clk,
92}; 92};
93 93
94#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
95
96static struct clk_lookup lookups[] = { 94static struct clk_lookup lookups[] = {
97 /* main clocks */ 95 /* main clocks */
98 CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk), 96 CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 8894926479a6..3b53348fe2fc 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -97,8 +97,6 @@ static struct clk *sh7780_onchip_clocks[] = {
97 &sh7780_shyway_clk, 97 &sh7780_shyway_clk,
98}; 98};
99 99
100#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
101
102static struct clk_lookup lookups[] = { 100static struct clk_lookup lookups[] = {
103 /* main clocks */ 101 /* main clocks */
104 CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk), 102 CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 2d960247f3eb..e5b420cc1265 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -116,8 +116,6 @@ static struct clk mstp_clks[MSTP_NR] = {
116 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0), 116 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
117}; 117};
118 118
119#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
120
121static struct clk_lookup lookups[] = { 119static struct clk_lookup lookups[] = {
122 /* main clocks */ 120 /* main clocks */
123 CLKDEV_CON_ID("extal", &extal_clk), 121 CLKDEV_CON_ID("extal", &extal_clk),
@@ -134,74 +132,27 @@ static struct clk_lookup lookups[] = {
134 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 132 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
135 133
136 /* MSTP32 clocks */ 134 /* MSTP32 clocks */
137 { 135 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]),
138 /* SCIF5 */ 136 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]),
139 .dev_id = "sh-sci.5", 137 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
140 .con_id = "sci_fck", 138 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
141 .clk = &mstp_clks[MSTP029], 139 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
142 }, { 140 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
143 /* SCIF4 */ 141
144 .dev_id = "sh-sci.4",
145 .con_id = "sci_fck",
146 .clk = &mstp_clks[MSTP028],
147 }, {
148 /* SCIF3 */
149 .dev_id = "sh-sci.3",
150 .con_id = "sci_fck",
151 .clk = &mstp_clks[MSTP027],
152 }, {
153 /* SCIF2 */
154 .dev_id = "sh-sci.2",
155 .con_id = "sci_fck",
156 .clk = &mstp_clks[MSTP026],
157 }, {
158 /* SCIF1 */
159 .dev_id = "sh-sci.1",
160 .con_id = "sci_fck",
161 .clk = &mstp_clks[MSTP025],
162 }, {
163 /* SCIF0 */
164 .dev_id = "sh-sci.0",
165 .con_id = "sci_fck",
166 .clk = &mstp_clks[MSTP024],
167 },
168 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]), 142 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
169 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]), 143 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
170 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]), 144 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
171 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]), 145 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
172 CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]), 146 CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
173 CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]), 147 CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
174 { 148
175 /* TMU0 */ 149 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP008]),
176 .dev_id = "sh_tmu.0", 150 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP008]),
177 .con_id = "tmu_fck", 151 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[MSTP008]),
178 .clk = &mstp_clks[MSTP008], 152 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[MSTP009]),
179 }, { 153 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[MSTP009]),
180 /* TMU1 */ 154 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[MSTP009]),
181 .dev_id = "sh_tmu.1", 155
182 .con_id = "tmu_fck",
183 .clk = &mstp_clks[MSTP008],
184 }, {
185 /* TMU2 */
186 .dev_id = "sh_tmu.2",
187 .con_id = "tmu_fck",
188 .clk = &mstp_clks[MSTP008],
189 }, {
190 /* TMU3 */
191 .dev_id = "sh_tmu.3",
192 .con_id = "tmu_fck",
193 .clk = &mstp_clks[MSTP009],
194 }, {
195 /* TMU4 */
196 .dev_id = "sh_tmu.4",
197 .con_id = "tmu_fck",
198 .clk = &mstp_clks[MSTP009],
199 }, {
200 /* TMU5 */
201 .dev_id = "sh_tmu.5",
202 .con_id = "tmu_fck",
203 .clk = &mstp_clks[MSTP009],
204 },
205 CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]), 156 CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
206 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]), 157 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
207 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]), 158 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index 42e403be9076..f6c0c3d5599f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -125,8 +125,6 @@ static struct clk mstp_clks[MSTP_NR] = {
125 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0), 125 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
126}; 126};
127 127
128#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
129
130static struct clk_lookup lookups[] = { 128static struct clk_lookup lookups[] = {
131 /* main clocks */ 129 /* main clocks */
132 CLKDEV_CON_ID("extal", &extal_clk), 130 CLKDEV_CON_ID("extal", &extal_clk),
@@ -141,37 +139,13 @@ static struct clk_lookup lookups[] = {
141 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 139 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
142 140
143 /* MSTP32 clocks */ 141 /* MSTP32 clocks */
144 { 142 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]),
145 /* SCIF5 */ 143 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]),
146 .dev_id = "sh-sci.5", 144 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
147 .con_id = "sci_fck", 145 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
148 .clk = &mstp_clks[MSTP029], 146 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
149 }, { 147 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
150 /* SCIF4 */ 148
151 .dev_id = "sh-sci.4",
152 .con_id = "sci_fck",
153 .clk = &mstp_clks[MSTP028],
154 }, {
155 /* SCIF3 */
156 .dev_id = "sh-sci.3",
157 .con_id = "sci_fck",
158 .clk = &mstp_clks[MSTP027],
159 }, {
160 /* SCIF2 */
161 .dev_id = "sh-sci.2",
162 .con_id = "sci_fck",
163 .clk = &mstp_clks[MSTP026],
164 }, {
165 /* SCIF1 */
166 .dev_id = "sh-sci.1",
167 .con_id = "sci_fck",
168 .clk = &mstp_clks[MSTP025],
169 }, {
170 /* SCIF0 */
171 .dev_id = "sh-sci.0",
172 .con_id = "sci_fck",
173 .clk = &mstp_clks[MSTP024],
174 },
175 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]), 149 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
176 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]), 150 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
177 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]), 151 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
@@ -180,67 +154,20 @@ static struct clk_lookup lookups[] = {
180 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]), 154 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
181 CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]), 155 CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
182 CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]), 156 CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
183 { 157
184 /* TMU0 */ 158 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP008]),
185 .dev_id = "sh_tmu.0", 159 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP008]),
186 .con_id = "tmu_fck", 160 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[MSTP008]),
187 .clk = &mstp_clks[MSTP008], 161 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[MSTP009]),
188 }, { 162 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[MSTP009]),
189 /* TMU1 */ 163 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[MSTP009]),
190 .dev_id = "sh_tmu.1", 164 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.6", &mstp_clks[MSTP010]),
191 .con_id = "tmu_fck", 165 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.7", &mstp_clks[MSTP010]),
192 .clk = &mstp_clks[MSTP008], 166 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.8", &mstp_clks[MSTP010]),
193 }, { 167 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.9", &mstp_clks[MSTP011]),
194 /* TMU2 */ 168 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.10", &mstp_clks[MSTP011]),
195 .dev_id = "sh_tmu.2", 169 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.11", &mstp_clks[MSTP011]),
196 .con_id = "tmu_fck", 170
197 .clk = &mstp_clks[MSTP008],
198 }, {
199 /* TMU3 */
200 .dev_id = "sh_tmu.3",
201 .con_id = "tmu_fck",
202 .clk = &mstp_clks[MSTP009],
203 }, {
204 /* TMU4 */
205 .dev_id = "sh_tmu.4",
206 .con_id = "tmu_fck",
207 .clk = &mstp_clks[MSTP009],
208 }, {
209 /* TMU5 */
210 .dev_id = "sh_tmu.5",
211 .con_id = "tmu_fck",
212 .clk = &mstp_clks[MSTP009],
213 }, {
214 /* TMU6 */
215 .dev_id = "sh_tmu.6",
216 .con_id = "tmu_fck",
217 .clk = &mstp_clks[MSTP010],
218 }, {
219 /* TMU7 */
220 .dev_id = "sh_tmu.7",
221 .con_id = "tmu_fck",
222 .clk = &mstp_clks[MSTP010],
223 }, {
224 /* TMU8 */
225 .dev_id = "sh_tmu.8",
226 .con_id = "tmu_fck",
227 .clk = &mstp_clks[MSTP010],
228 }, {
229 /* TMU9 */
230 .dev_id = "sh_tmu.9",
231 .con_id = "tmu_fck",
232 .clk = &mstp_clks[MSTP011],
233 }, {
234 /* TMU10 */
235 .dev_id = "sh_tmu.10",
236 .con_id = "tmu_fck",
237 .clk = &mstp_clks[MSTP011],
238 }, {
239 /* TMU11 */
240 .dev_id = "sh_tmu.11",
241 .con_id = "tmu_fck",
242 .clk = &mstp_clks[MSTP011],
243 },
244 CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]), 171 CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
245 CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]), 172 CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
246 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]), 173 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index 1afdb93b8ccb..bf2d00b8b908 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -100,8 +100,6 @@ static struct clk mstp_clks[MSTP_NR] = {
100 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), 100 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
101}; 101};
102 102
103#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
104
105static struct clk_lookup lookups[] = { 103static struct clk_lookup lookups[] = {
106 /* main clocks */ 104 /* main clocks */
107 CLKDEV_CON_ID("extal", &extal_clk), 105 CLKDEV_CON_ID("extal", &extal_clk),
@@ -116,62 +114,23 @@ static struct clk_lookup lookups[] = {
116 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 114 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
117 115
118 /* MSTP32 clocks */ 116 /* MSTP32 clocks */
119 { 117 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
120 /* SCIF3 */ 118 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
121 .dev_id = "sh-sci.3", 119 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
122 .con_id = "sci_fck", 120 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
123 .clk = &mstp_clks[MSTP027], 121
124 }, {
125 /* SCIF2 */
126 .dev_id = "sh-sci.2",
127 .con_id = "sci_fck",
128 .clk = &mstp_clks[MSTP026],
129 }, {
130 /* SCIF1 */
131 .dev_id = "sh-sci.1",
132 .con_id = "sci_fck",
133 .clk = &mstp_clks[MSTP025],
134 }, {
135 /* SCIF0 */
136 .dev_id = "sh-sci.0",
137 .con_id = "sci_fck",
138 .clk = &mstp_clks[MSTP024],
139 },
140 CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]), 122 CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
141 CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]), 123 CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
142 CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]), 124 CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
143 CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]), 125 CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
144 { 126
145 /* TMU0 */ 127 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP008]),
146 .dev_id = "sh_tmu.0", 128 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP008]),
147 .con_id = "tmu_fck", 129 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[MSTP008]),
148 .clk = &mstp_clks[MSTP008], 130 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[MSTP009]),
149 }, { 131 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[MSTP009]),
150 /* TMU1 */ 132 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[MSTP009]),
151 .dev_id = "sh_tmu.1", 133
152 .con_id = "tmu_fck",
153 .clk = &mstp_clks[MSTP008],
154 }, {
155 /* TMU2 */
156 .dev_id = "sh_tmu.2",
157 .con_id = "tmu_fck",
158 .clk = &mstp_clks[MSTP008],
159 }, {
160 /* TMU3 */
161 .dev_id = "sh_tmu.3",
162 .con_id = "tmu_fck",
163 .clk = &mstp_clks[MSTP009],
164 }, {
165 /* TMU4 */
166 .dev_id = "sh_tmu.4",
167 .con_id = "tmu_fck",
168 .clk = &mstp_clks[MSTP009],
169 }, {
170 /* TMU5 */
171 .dev_id = "sh_tmu.5",
172 .con_id = "tmu_fck",
173 .clk = &mstp_clks[MSTP009],
174 },
175 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]), 134 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
176 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), 135 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
177 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), 136 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
diff --git a/arch/sh/kernel/cpu/sh4a/serial-sh7722.c b/arch/sh/kernel/cpu/sh4a/serial-sh7722.c
new file mode 100644
index 000000000000..59bc3a72702e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/serial-sh7722.c
@@ -0,0 +1,23 @@
1#include <linux/serial_sci.h>
2#include <linux/serial_core.h>
3#include <linux/io.h>
4
5#define PSCR 0xA405011E
6
7static void sh7722_sci_init_pins(struct uart_port *port, unsigned int cflag)
8{
9 unsigned short data;
10
11 if (port->mapbase == 0xffe00000) {
12 data = __raw_readw(PSCR);
13 data &= ~0x03cf;
14 if (!(cflag & CRTSCTS))
15 data |= 0x0340;
16
17 __raw_writew(data, PSCR);
18 }
19}
20
21struct plat_sci_port_ops sh7722_sci_port_ops = {
22 .init_pins = sh7722_sci_init_pins,
23};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 82616af64d62..87773869a2f3 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -20,6 +20,7 @@
20 20
21static struct plat_sci_port scif0_platform_data = { 21static struct plat_sci_port scif0_platform_data = {
22 .mapbase = 0xffe00000, 22 .mapbase = 0xffe00000,
23 .port_reg = 0xa405013e,
23 .flags = UPF_BOOT_AUTOCONF, 24 .flags = UPF_BOOT_AUTOCONF,
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
25 .scbrr_algo_id = SCBRR_ALGO_2, 26 .scbrr_algo_id = SCBRR_ALGO_2,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 5813d8023619..278a0e572158 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -22,6 +22,7 @@
22 22
23#include <cpu/dma-register.h> 23#include <cpu/dma-register.h>
24#include <cpu/sh7722.h> 24#include <cpu/sh7722.h>
25#include <cpu/serial.h>
25 26
26static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = { 27static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
27 { 28 {
@@ -185,6 +186,8 @@ static struct plat_sci_port scif0_platform_data = {
185 .scbrr_algo_id = SCBRR_ALGO_2, 186 .scbrr_algo_id = SCBRR_ALGO_2,
186 .type = PORT_SCIF, 187 .type = PORT_SCIF,
187 .irqs = { 80, 80, 80, 80 }, 188 .irqs = { 80, 80, 80, 80 },
189 .ops = &sh7722_sci_port_ops,
190 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
188}; 191};
189 192
190static struct platform_device scif0_device = { 193static struct platform_device scif0_device = {
@@ -202,6 +205,8 @@ static struct plat_sci_port scif1_platform_data = {
202 .scbrr_algo_id = SCBRR_ALGO_2, 205 .scbrr_algo_id = SCBRR_ALGO_2,
203 .type = PORT_SCIF, 206 .type = PORT_SCIF,
204 .irqs = { 81, 81, 81, 81 }, 207 .irqs = { 81, 81, 81, 81 },
208 .ops = &sh7722_sci_port_ops,
209 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
205}; 210};
206 211
207static struct platform_device scif1_device = { 212static struct platform_device scif1_device = {
@@ -219,6 +224,8 @@ static struct plat_sci_port scif2_platform_data = {
219 .scbrr_algo_id = SCBRR_ALGO_2, 224 .scbrr_algo_id = SCBRR_ALGO_2,
220 .type = PORT_SCIF, 225 .type = PORT_SCIF,
221 .irqs = { 82, 82, 82, 82 }, 226 .irqs = { 82, 82, 82, 82 },
227 .ops = &sh7722_sci_port_ops,
228 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
222}; 229};
223 230
224static struct platform_device scif2_device = { 231static struct platform_device scif2_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 072382280f96..3c2810d8f72e 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -23,11 +23,13 @@
23/* Serial */ 23/* Serial */
24static struct plat_sci_port scif0_platform_data = { 24static struct plat_sci_port scif0_platform_data = {
25 .mapbase = 0xffe00000, 25 .mapbase = 0xffe00000,
26 .port_reg = 0xa4050160,
26 .flags = UPF_BOOT_AUTOCONF, 27 .flags = UPF_BOOT_AUTOCONF,
27 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
28 .scbrr_algo_id = SCBRR_ALGO_2, 29 .scbrr_algo_id = SCBRR_ALGO_2,
29 .type = PORT_SCIF, 30 .type = PORT_SCIF,
30 .irqs = { 80, 80, 80, 80 }, 31 .irqs = { 80, 80, 80, 80 },
32 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
31}; 33};
32 34
33static struct platform_device scif0_device = { 35static struct platform_device scif0_device = {
@@ -40,11 +42,13 @@ static struct platform_device scif0_device = {
40 42
41static struct plat_sci_port scif1_platform_data = { 43static struct plat_sci_port scif1_platform_data = {
42 .mapbase = 0xffe10000, 44 .mapbase = 0xffe10000,
45 .port_reg = SCIx_NOT_SUPPORTED,
43 .flags = UPF_BOOT_AUTOCONF, 46 .flags = UPF_BOOT_AUTOCONF,
44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 47 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
45 .scbrr_algo_id = SCBRR_ALGO_2, 48 .scbrr_algo_id = SCBRR_ALGO_2,
46 .type = PORT_SCIF, 49 .type = PORT_SCIF,
47 .irqs = { 81, 81, 81, 81 }, 50 .irqs = { 81, 81, 81, 81 },
51 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
48}; 52};
49 53
50static struct platform_device scif1_device = { 54static struct platform_device scif1_device = {
@@ -57,11 +61,13 @@ static struct platform_device scif1_device = {
57 61
58static struct plat_sci_port scif2_platform_data = { 62static struct plat_sci_port scif2_platform_data = {
59 .mapbase = 0xffe20000, 63 .mapbase = 0xffe20000,
64 .port_reg = SCIx_NOT_SUPPORTED,
60 .flags = UPF_BOOT_AUTOCONF, 65 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
62 .scbrr_algo_id = SCBRR_ALGO_2, 67 .scbrr_algo_id = SCBRR_ALGO_2,
63 .type = PORT_SCIF, 68 .type = PORT_SCIF,
64 .irqs = { 82, 82, 82, 82 }, 69 .irqs = { 82, 82, 82, 82 },
70 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
65}; 71};
66 72
67static struct platform_device scif2_device = { 73static struct platform_device scif2_device = {
@@ -75,6 +81,7 @@ static struct platform_device scif2_device = {
75static struct plat_sci_port scif3_platform_data = { 81static struct plat_sci_port scif3_platform_data = {
76 .mapbase = 0xa4e30000, 82 .mapbase = 0xa4e30000,
77 .flags = UPF_BOOT_AUTOCONF, 83 .flags = UPF_BOOT_AUTOCONF,
84 .port_reg = SCIx_NOT_SUPPORTED,
78 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 85 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
79 .scbrr_algo_id = SCBRR_ALGO_3, 86 .scbrr_algo_id = SCBRR_ALGO_3,
80 .type = PORT_SCIFA, 87 .type = PORT_SCIFA,
@@ -91,6 +98,7 @@ static struct platform_device scif3_device = {
91 98
92static struct plat_sci_port scif4_platform_data = { 99static struct plat_sci_port scif4_platform_data = {
93 .mapbase = 0xa4e40000, 100 .mapbase = 0xa4e40000,
101 .port_reg = SCIx_NOT_SUPPORTED,
94 .flags = UPF_BOOT_AUTOCONF, 102 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 103 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
96 .scbrr_algo_id = SCBRR_ALGO_3, 104 .scbrr_algo_id = SCBRR_ALGO_3,
@@ -108,6 +116,7 @@ static struct platform_device scif4_device = {
108 116
109static struct plat_sci_port scif5_platform_data = { 117static struct plat_sci_port scif5_platform_data = {
110 .mapbase = 0xa4e50000, 118 .mapbase = 0xa4e50000,
119 .port_reg = SCIx_NOT_SUPPORTED,
111 .flags = UPF_BOOT_AUTOCONF, 120 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 121 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
113 .scbrr_algo_id = SCBRR_ALGO_3, 122 .scbrr_algo_id = SCBRR_ALGO_3,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 134a397b1918..a37dd72c3671 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -296,11 +296,13 @@ static struct platform_device dma1_device = {
296/* Serial */ 296/* Serial */
297static struct plat_sci_port scif0_platform_data = { 297static struct plat_sci_port scif0_platform_data = {
298 .mapbase = 0xffe00000, 298 .mapbase = 0xffe00000,
299 .port_reg = SCIx_NOT_SUPPORTED,
299 .flags = UPF_BOOT_AUTOCONF, 300 .flags = UPF_BOOT_AUTOCONF,
300 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 301 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
301 .scbrr_algo_id = SCBRR_ALGO_2, 302 .scbrr_algo_id = SCBRR_ALGO_2,
302 .type = PORT_SCIF, 303 .type = PORT_SCIF,
303 .irqs = { 80, 80, 80, 80 }, 304 .irqs = { 80, 80, 80, 80 },
305 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
304}; 306};
305 307
306static struct platform_device scif0_device = { 308static struct platform_device scif0_device = {
@@ -313,11 +315,13 @@ static struct platform_device scif0_device = {
313 315
314static struct plat_sci_port scif1_platform_data = { 316static struct plat_sci_port scif1_platform_data = {
315 .mapbase = 0xffe10000, 317 .mapbase = 0xffe10000,
318 .port_reg = SCIx_NOT_SUPPORTED,
316 .flags = UPF_BOOT_AUTOCONF, 319 .flags = UPF_BOOT_AUTOCONF,
317 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 320 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
318 .scbrr_algo_id = SCBRR_ALGO_2, 321 .scbrr_algo_id = SCBRR_ALGO_2,
319 .type = PORT_SCIF, 322 .type = PORT_SCIF,
320 .irqs = { 81, 81, 81, 81 }, 323 .irqs = { 81, 81, 81, 81 },
324 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
321}; 325};
322 326
323static struct platform_device scif1_device = { 327static struct platform_device scif1_device = {
@@ -330,11 +334,13 @@ static struct platform_device scif1_device = {
330 334
331static struct plat_sci_port scif2_platform_data = { 335static struct plat_sci_port scif2_platform_data = {
332 .mapbase = 0xffe20000, 336 .mapbase = 0xffe20000,
337 .port_reg = SCIx_NOT_SUPPORTED,
333 .flags = UPF_BOOT_AUTOCONF, 338 .flags = UPF_BOOT_AUTOCONF,
334 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 339 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
335 .scbrr_algo_id = SCBRR_ALGO_2, 340 .scbrr_algo_id = SCBRR_ALGO_2,
336 .type = PORT_SCIF, 341 .type = PORT_SCIF,
337 .irqs = { 82, 82, 82, 82 }, 342 .irqs = { 82, 82, 82, 82 },
343 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
338}; 344};
339 345
340static struct platform_device scif2_device = { 346static struct platform_device scif2_device = {
@@ -347,6 +353,7 @@ static struct platform_device scif2_device = {
347 353
348static struct plat_sci_port scif3_platform_data = { 354static struct plat_sci_port scif3_platform_data = {
349 .mapbase = 0xa4e30000, 355 .mapbase = 0xa4e30000,
356 .port_reg = SCIx_NOT_SUPPORTED,
350 .flags = UPF_BOOT_AUTOCONF, 357 .flags = UPF_BOOT_AUTOCONF,
351 .scscr = SCSCR_RE | SCSCR_TE, 358 .scscr = SCSCR_RE | SCSCR_TE,
352 .scbrr_algo_id = SCBRR_ALGO_3, 359 .scbrr_algo_id = SCBRR_ALGO_3,
@@ -364,6 +371,7 @@ static struct platform_device scif3_device = {
364 371
365static struct plat_sci_port scif4_platform_data = { 372static struct plat_sci_port scif4_platform_data = {
366 .mapbase = 0xa4e40000, 373 .mapbase = 0xa4e40000,
374 .port_reg = SCIx_NOT_SUPPORTED,
367 .flags = UPF_BOOT_AUTOCONF, 375 .flags = UPF_BOOT_AUTOCONF,
368 .scscr = SCSCR_RE | SCSCR_TE, 376 .scscr = SCSCR_RE | SCSCR_TE,
369 .scbrr_algo_id = SCBRR_ALGO_3, 377 .scbrr_algo_id = SCBRR_ALGO_3,
@@ -381,6 +389,7 @@ static struct platform_device scif4_device = {
381 389
382static struct plat_sci_port scif5_platform_data = { 390static struct plat_sci_port scif5_platform_data = {
383 .mapbase = 0xa4e50000, 391 .mapbase = 0xa4e50000,
392 .port_reg = SCIx_NOT_SUPPORTED,
384 .flags = UPF_BOOT_AUTOCONF, 393 .flags = UPF_BOOT_AUTOCONF,
385 .scscr = SCSCR_RE | SCSCR_TE, 394 .scscr = SCSCR_RE | SCSCR_TE,
386 .scbrr_algo_id = SCBRR_ALGO_3, 395 .scbrr_algo_id = SCBRR_ALGO_3,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 593eca6509b5..00113515f233 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -23,6 +23,7 @@ static struct plat_sci_port scif0_platform_data = {
23 .scbrr_algo_id = SCBRR_ALGO_2, 23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 24 .type = PORT_SCIF,
25 .irqs = { 40, 40, 40, 40 }, 25 .irqs = { 40, 40, 40, 40 },
26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
26}; 27};
27 28
28static struct platform_device scif0_device = { 29static struct platform_device scif0_device = {
@@ -40,6 +41,7 @@ static struct plat_sci_port scif1_platform_data = {
40 .scbrr_algo_id = SCBRR_ALGO_2, 41 .scbrr_algo_id = SCBRR_ALGO_2,
41 .type = PORT_SCIF, 42 .type = PORT_SCIF,
42 .irqs = { 76, 76, 76, 76 }, 43 .irqs = { 76, 76, 76, 76 },
44 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
43}; 45};
44 46
45static struct platform_device scif1_device = { 47static struct platform_device scif1_device = {
@@ -57,6 +59,7 @@ static struct plat_sci_port scif2_platform_data = {
57 .scbrr_algo_id = SCBRR_ALGO_2, 59 .scbrr_algo_id = SCBRR_ALGO_2,
58 .type = PORT_SCIF, 60 .type = PORT_SCIF,
59 .irqs = { 104, 104, 104, 104 }, 61 .irqs = { 104, 104, 104, 104 },
62 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
60}; 63};
61 64
62static struct platform_device scif2_device = { 65static struct platform_device scif2_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 08add7fa6849..3d4d2075c19a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -14,7 +14,6 @@
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_dma.h> 15#include <linux/sh_dma.h>
16#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17
18#include <cpu/dma-register.h> 17#include <cpu/dma-register.h>
19 18
20static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
@@ -24,6 +23,7 @@ static struct plat_sci_port scif0_platform_data = {
24 .scbrr_algo_id = SCBRR_ALGO_1, 23 .scbrr_algo_id = SCBRR_ALGO_1,
25 .type = PORT_SCIF, 24 .type = PORT_SCIF,
26 .irqs = { 40, 40, 40, 40 }, 25 .irqs = { 40, 40, 40, 40 },
26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
27}; 27};
28 28
29static struct platform_device scif0_device = { 29static struct platform_device scif0_device = {
@@ -41,6 +41,7 @@ static struct plat_sci_port scif1_platform_data = {
41 .scbrr_algo_id = SCBRR_ALGO_1, 41 .scbrr_algo_id = SCBRR_ALGO_1,
42 .type = PORT_SCIF, 42 .type = PORT_SCIF,
43 .irqs = { 76, 76, 76, 76 }, 43 .irqs = { 76, 76, 76, 76 },
44 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
44}; 45};
45 46
46static struct platform_device scif1_device = { 47static struct platform_device scif1_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 18d8fc136fb2..b29e6340414a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -15,9 +15,7 @@
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/sh_dma.h> 16#include <linux/sh_dma.h>
17#include <linux/sh_timer.h> 17#include <linux/sh_timer.h>
18
19#include <asm/mmzone.h> 18#include <asm/mmzone.h>
20
21#include <cpu/dma-register.h> 19#include <cpu/dma-register.h>
22 20
23static struct plat_sci_port scif0_platform_data = { 21static struct plat_sci_port scif0_platform_data = {
@@ -27,6 +25,7 @@ static struct plat_sci_port scif0_platform_data = {
27 .scbrr_algo_id = SCBRR_ALGO_1, 25 .scbrr_algo_id = SCBRR_ALGO_1,
28 .type = PORT_SCIF, 26 .type = PORT_SCIF,
29 .irqs = { 40, 40, 40, 40 }, 27 .irqs = { 40, 40, 40, 40 },
28 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
30}; 29};
31 30
32static struct platform_device scif0_device = { 31static struct platform_device scif0_device = {
@@ -44,6 +43,7 @@ static struct plat_sci_port scif1_platform_data = {
44 .scbrr_algo_id = SCBRR_ALGO_1, 43 .scbrr_algo_id = SCBRR_ALGO_1,
45 .type = PORT_SCIF, 44 .type = PORT_SCIF,
46 .irqs = { 44, 44, 44, 44 }, 45 .irqs = { 44, 44, 44, 44 },
46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
47}; 47};
48 48
49static struct platform_device scif1_device = { 49static struct platform_device scif1_device = {
@@ -61,6 +61,7 @@ static struct plat_sci_port scif2_platform_data = {
61 .scbrr_algo_id = SCBRR_ALGO_1, 61 .scbrr_algo_id = SCBRR_ALGO_1,
62 .type = PORT_SCIF, 62 .type = PORT_SCIF,
63 .irqs = { 60, 60, 60, 60 }, 63 .irqs = { 60, 60, 60, 60 },
64 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
64}; 65};
65 66
66static struct platform_device scif2_device = { 67static struct platform_device scif2_device = {
@@ -78,6 +79,7 @@ static struct plat_sci_port scif3_platform_data = {
78 .scbrr_algo_id = SCBRR_ALGO_1, 79 .scbrr_algo_id = SCBRR_ALGO_1,
79 .type = PORT_SCIF, 80 .type = PORT_SCIF,
80 .irqs = { 61, 61, 61, 61 }, 81 .irqs = { 61, 61, 61, 61 },
82 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
81}; 83};
82 84
83static struct platform_device scif3_device = { 85static struct platform_device scif3_device = {
@@ -95,6 +97,7 @@ static struct plat_sci_port scif4_platform_data = {
95 .scbrr_algo_id = SCBRR_ALGO_1, 97 .scbrr_algo_id = SCBRR_ALGO_1,
96 .type = PORT_SCIF, 98 .type = PORT_SCIF,
97 .irqs = { 62, 62, 62, 62 }, 99 .irqs = { 62, 62, 62, 62 },
100 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
98}; 101};
99 102
100static struct platform_device scif4_device = { 103static struct platform_device scif4_device = {
@@ -112,6 +115,7 @@ static struct plat_sci_port scif5_platform_data = {
112 .scbrr_algo_id = SCBRR_ALGO_1, 115 .scbrr_algo_id = SCBRR_ALGO_1,
113 .type = PORT_SCIF, 116 .type = PORT_SCIF,
114 .irqs = { 63, 63, 63, 63 }, 117 .irqs = { 63, 63, 63, 63 },
118 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
115}; 119};
116 120
117static struct platform_device scif5_device = { 121static struct platform_device scif5_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index beba32beb6d9..dd5e709f9821 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7786 Setup 2 * SH7786 Setup
3 * 3 *
4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp. 4 * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * Paul Mundt <paul.mundt@renesas.com> 6 * Paul Mundt <paul.mundt@renesas.com>
7 * 7 *
@@ -33,6 +33,7 @@ static struct plat_sci_port scif0_platform_data = {
33 .scbrr_algo_id = SCBRR_ALGO_1, 33 .scbrr_algo_id = SCBRR_ALGO_1,
34 .type = PORT_SCIF, 34 .type = PORT_SCIF,
35 .irqs = { 40, 41, 43, 42 }, 35 .irqs = { 40, 41, 43, 42 },
36 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
36}; 37};
37 38
38static struct platform_device scif0_device = { 39static struct platform_device scif0_device = {
@@ -53,6 +54,7 @@ static struct plat_sci_port scif1_platform_data = {
53 .scbrr_algo_id = SCBRR_ALGO_1, 54 .scbrr_algo_id = SCBRR_ALGO_1,
54 .type = PORT_SCIF, 55 .type = PORT_SCIF,
55 .irqs = { 44, 44, 44, 44 }, 56 .irqs = { 44, 44, 44, 44 },
57 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
56}; 58};
57 59
58static struct platform_device scif1_device = { 60static struct platform_device scif1_device = {
@@ -70,6 +72,7 @@ static struct plat_sci_port scif2_platform_data = {
70 .scbrr_algo_id = SCBRR_ALGO_1, 72 .scbrr_algo_id = SCBRR_ALGO_1,
71 .type = PORT_SCIF, 73 .type = PORT_SCIF,
72 .irqs = { 50, 50, 50, 50 }, 74 .irqs = { 50, 50, 50, 50 },
75 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
73}; 76};
74 77
75static struct platform_device scif2_device = { 78static struct platform_device scif2_device = {
@@ -87,6 +90,7 @@ static struct plat_sci_port scif3_platform_data = {
87 .scbrr_algo_id = SCBRR_ALGO_1, 90 .scbrr_algo_id = SCBRR_ALGO_1,
88 .type = PORT_SCIF, 91 .type = PORT_SCIF,
89 .irqs = { 51, 51, 51, 51 }, 92 .irqs = { 51, 51, 51, 51 },
93 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
90}; 94};
91 95
92static struct platform_device scif3_device = { 96static struct platform_device scif3_device = {
@@ -104,6 +108,7 @@ static struct plat_sci_port scif4_platform_data = {
104 .scbrr_algo_id = SCBRR_ALGO_1, 108 .scbrr_algo_id = SCBRR_ALGO_1,
105 .type = PORT_SCIF, 109 .type = PORT_SCIF,
106 .irqs = { 52, 52, 52, 52 }, 110 .irqs = { 52, 52, 52, 52 },
111 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
107}; 112};
108 113
109static struct platform_device scif4_device = { 114static struct platform_device scif4_device = {
@@ -121,6 +126,7 @@ static struct plat_sci_port scif5_platform_data = {
121 .scbrr_algo_id = SCBRR_ALGO_1, 126 .scbrr_algo_id = SCBRR_ALGO_1,
122 .type = PORT_SCIF, 127 .type = PORT_SCIF,
123 .irqs = { 53, 53, 53, 53 }, 128 .irqs = { 53, 53, 53, 53 },
129 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
124}; 130};
125 131
126static struct platform_device scif5_device = { 132static struct platform_device scif5_device = {
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index 028330044201..7f49235d14b9 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -70,12 +70,36 @@ static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
70 70
71static u16 dmaor_read(struct sh_dmae_device *shdev) 71static u16 dmaor_read(struct sh_dmae_device *shdev)
72{ 72{
73 return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32)); 73 u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
74
75 if (shdev->pdata->dmaor_is_32bit)
76 return __raw_readl(addr);
77 else
78 return __raw_readw(addr);
74} 79}
75 80
76static void dmaor_write(struct sh_dmae_device *shdev, u16 data) 81static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
77{ 82{
78 __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32)); 83 u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
84
85 if (shdev->pdata->dmaor_is_32bit)
86 __raw_writel(data, addr);
87 else
88 __raw_writew(data, addr);
89}
90
91static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
92{
93 struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
94
95 __raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32));
96}
97
98static u32 chcr_read(struct sh_dmae_chan *sh_dc)
99{
100 struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
101
102 return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32));
79} 103}
80 104
81/* 105/*
@@ -120,7 +144,7 @@ static int sh_dmae_rst(struct sh_dmae_device *shdev)
120 144
121static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) 145static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
122{ 146{
123 u32 chcr = sh_dmae_readl(sh_chan, CHCR); 147 u32 chcr = chcr_read(sh_chan);
124 148
125 if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE) 149 if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
126 return true; /* working */ 150 return true; /* working */
@@ -130,8 +154,7 @@ static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
130 154
131static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) 155static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
132{ 156{
133 struct sh_dmae_device *shdev = container_of(sh_chan->common.device, 157 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
134 struct sh_dmae_device, common);
135 struct sh_dmae_pdata *pdata = shdev->pdata; 158 struct sh_dmae_pdata *pdata = shdev->pdata;
136 int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) | 159 int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
137 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift); 160 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
@@ -144,8 +167,7 @@ static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
144 167
145static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) 168static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
146{ 169{
147 struct sh_dmae_device *shdev = container_of(sh_chan->common.device, 170 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
148 struct sh_dmae_device, common);
149 struct sh_dmae_pdata *pdata = shdev->pdata; 171 struct sh_dmae_pdata *pdata = shdev->pdata;
150 int i; 172 int i;
151 173
@@ -169,18 +191,23 @@ static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
169 191
170static void dmae_start(struct sh_dmae_chan *sh_chan) 192static void dmae_start(struct sh_dmae_chan *sh_chan)
171{ 193{
172 u32 chcr = sh_dmae_readl(sh_chan, CHCR); 194 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
195 u32 chcr = chcr_read(sh_chan);
196
197 if (shdev->pdata->needs_tend_set)
198 sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
173 199
174 chcr |= CHCR_DE | CHCR_IE; 200 chcr |= CHCR_DE | shdev->chcr_ie_bit;
175 sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR); 201 chcr_write(sh_chan, chcr & ~CHCR_TE);
176} 202}
177 203
178static void dmae_halt(struct sh_dmae_chan *sh_chan) 204static void dmae_halt(struct sh_dmae_chan *sh_chan)
179{ 205{
180 u32 chcr = sh_dmae_readl(sh_chan, CHCR); 206 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
207 u32 chcr = chcr_read(sh_chan);
181 208
182 chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); 209 chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
183 sh_dmae_writel(sh_chan, chcr, CHCR); 210 chcr_write(sh_chan, chcr);
184} 211}
185 212
186static void dmae_init(struct sh_dmae_chan *sh_chan) 213static void dmae_init(struct sh_dmae_chan *sh_chan)
@@ -192,7 +219,7 @@ static void dmae_init(struct sh_dmae_chan *sh_chan)
192 u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, 219 u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
193 LOG2_DEFAULT_XFER_SIZE); 220 LOG2_DEFAULT_XFER_SIZE);
194 sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); 221 sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
195 sh_dmae_writel(sh_chan, chcr, CHCR); 222 chcr_write(sh_chan, chcr);
196} 223}
197 224
198static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) 225static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
@@ -202,23 +229,25 @@ static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
202 return -EBUSY; 229 return -EBUSY;
203 230
204 sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); 231 sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
205 sh_dmae_writel(sh_chan, val, CHCR); 232 chcr_write(sh_chan, val);
206 233
207 return 0; 234 return 0;
208} 235}
209 236
210static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) 237static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
211{ 238{
212 struct sh_dmae_device *shdev = container_of(sh_chan->common.device, 239 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
213 struct sh_dmae_device, common);
214 struct sh_dmae_pdata *pdata = shdev->pdata; 240 struct sh_dmae_pdata *pdata = shdev->pdata;
215 const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id]; 241 const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
216 u16 __iomem *addr = shdev->dmars; 242 u16 __iomem *addr = shdev->dmars;
217 int shift = chan_pdata->dmars_bit; 243 unsigned int shift = chan_pdata->dmars_bit;
218 244
219 if (dmae_is_busy(sh_chan)) 245 if (dmae_is_busy(sh_chan))
220 return -EBUSY; 246 return -EBUSY;
221 247
248 if (pdata->no_dmars)
249 return 0;
250
222 /* in the case of a missing DMARS resource use first memory window */ 251 /* in the case of a missing DMARS resource use first memory window */
223 if (!addr) 252 if (!addr)
224 addr = (u16 __iomem *)shdev->chan_reg; 253 addr = (u16 __iomem *)shdev->chan_reg;
@@ -296,9 +325,7 @@ static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
296static const struct sh_dmae_slave_config *sh_dmae_find_slave( 325static const struct sh_dmae_slave_config *sh_dmae_find_slave(
297 struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param) 326 struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param)
298{ 327{
299 struct dma_device *dma_dev = sh_chan->common.device; 328 struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
300 struct sh_dmae_device *shdev = container_of(dma_dev,
301 struct sh_dmae_device, common);
302 struct sh_dmae_pdata *pdata = shdev->pdata; 329 struct sh_dmae_pdata *pdata = shdev->pdata;
303 int i; 330 int i;
304 331
@@ -771,10 +798,8 @@ static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
771 798
772 spin_lock_bh(&sh_chan->desc_lock); 799 spin_lock_bh(&sh_chan->desc_lock);
773 /* DMA work check */ 800 /* DMA work check */
774 if (dmae_is_busy(sh_chan)) { 801 if (dmae_is_busy(sh_chan))
775 spin_unlock_bh(&sh_chan->desc_lock); 802 goto sh_chan_xfer_ld_queue_end;
776 return;
777 }
778 803
779 /* Find the first not transferred descriptor */ 804 /* Find the first not transferred descriptor */
780 list_for_each_entry(desc, &sh_chan->ld_queue, node) 805 list_for_each_entry(desc, &sh_chan->ld_queue, node)
@@ -788,6 +813,7 @@ static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
788 break; 813 break;
789 } 814 }
790 815
816sh_chan_xfer_ld_queue_end:
791 spin_unlock_bh(&sh_chan->desc_lock); 817 spin_unlock_bh(&sh_chan->desc_lock);
792} 818}
793 819
@@ -846,7 +872,7 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data)
846 872
847 spin_lock(&sh_chan->desc_lock); 873 spin_lock(&sh_chan->desc_lock);
848 874
849 chcr = sh_dmae_readl(sh_chan, CHCR); 875 chcr = chcr_read(sh_chan);
850 876
851 if (chcr & CHCR_TE) { 877 if (chcr & CHCR_TE) {
852 /* DMA stop */ 878 /* DMA stop */
@@ -1144,6 +1170,16 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
1144 /* platform data */ 1170 /* platform data */
1145 shdev->pdata = pdata; 1171 shdev->pdata = pdata;
1146 1172
1173 if (pdata->chcr_offset)
1174 shdev->chcr_offset = pdata->chcr_offset;
1175 else
1176 shdev->chcr_offset = CHCR;
1177
1178 if (pdata->chcr_ie_bit)
1179 shdev->chcr_ie_bit = pdata->chcr_ie_bit;
1180 else
1181 shdev->chcr_ie_bit = CHCR_IE;
1182
1147 platform_set_drvdata(pdev, shdev); 1183 platform_set_drvdata(pdev, shdev);
1148 1184
1149 pm_runtime_enable(&pdev->dev); 1185 pm_runtime_enable(&pdev->dev);
diff --git a/drivers/dma/shdma.h b/drivers/dma/shdma.h
index 5ae9fc512180..dc56576f9fdb 100644
--- a/drivers/dma/shdma.h
+++ b/drivers/dma/shdma.h
@@ -47,10 +47,14 @@ struct sh_dmae_device {
47 struct list_head node; 47 struct list_head node;
48 u32 __iomem *chan_reg; 48 u32 __iomem *chan_reg;
49 u16 __iomem *dmars; 49 u16 __iomem *dmars;
50 unsigned int chcr_offset;
51 u32 chcr_ie_bit;
50}; 52};
51 53
52#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common) 54#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)
53#define to_sh_desc(lh) container_of(lh, struct sh_desc, node) 55#define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
54#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx) 56#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
57#define to_sh_dev(chan) container_of(chan->common.device,\
58 struct sh_dmae_device, common)
55 59
56#endif /* __DMA_SHDMA_H */ 60#endif /* __DMA_SHDMA_H */
diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c
index d6702e57d428..dc8d022c07a1 100644
--- a/drivers/sh/clk/core.c
+++ b/drivers/sh/clk/core.c
@@ -34,6 +34,9 @@ static LIST_HEAD(clock_list);
34static DEFINE_SPINLOCK(clock_lock); 34static DEFINE_SPINLOCK(clock_lock);
35static DEFINE_MUTEX(clock_list_sem); 35static DEFINE_MUTEX(clock_list_sem);
36 36
37/* clock disable operations are not passed on to hardware during boot */
38static int allow_disable;
39
37void clk_rate_table_build(struct clk *clk, 40void clk_rate_table_build(struct clk *clk,
38 struct cpufreq_frequency_table *freq_table, 41 struct cpufreq_frequency_table *freq_table,
39 int nr_freqs, 42 int nr_freqs,
@@ -228,7 +231,7 @@ static void __clk_disable(struct clk *clk)
228 return; 231 return;
229 232
230 if (!(--clk->usecount)) { 233 if (!(--clk->usecount)) {
231 if (likely(clk->ops && clk->ops->disable)) 234 if (likely(allow_disable && clk->ops && clk->ops->disable))
232 clk->ops->disable(clk); 235 clk->ops->disable(clk);
233 if (likely(clk->parent)) 236 if (likely(clk->parent))
234 __clk_disable(clk->parent); 237 __clk_disable(clk->parent);
@@ -393,7 +396,7 @@ int clk_register(struct clk *clk)
393{ 396{
394 int ret; 397 int ret;
395 398
396 if (clk == NULL || IS_ERR(clk)) 399 if (IS_ERR_OR_NULL(clk))
397 return -EINVAL; 400 return -EINVAL;
398 401
399 /* 402 /*
@@ -744,3 +747,25 @@ err_out:
744 return err; 747 return err;
745} 748}
746late_initcall(clk_debugfs_init); 749late_initcall(clk_debugfs_init);
750
751static int __init clk_late_init(void)
752{
753 unsigned long flags;
754 struct clk *clk;
755
756 /* disable all clocks with zero use count */
757 mutex_lock(&clock_list_sem);
758 spin_lock_irqsave(&clock_lock, flags);
759
760 list_for_each_entry(clk, &clock_list, node)
761 if (!clk->usecount && clk->ops && clk->ops->disable)
762 clk->ops->disable(clk);
763
764 /* from now on allow clock disable operations */
765 allow_disable = 1;
766
767 spin_unlock_irqrestore(&clock_lock, flags);
768 mutex_unlock(&clock_list_sem);
769 return 0;
770}
771late_initcall(clk_late_init);
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index cb40b82daf36..4dcb37bbdf92 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -959,7 +959,7 @@ config SERIAL_IP22_ZILOG_CONSOLE
959 959
960config SERIAL_SH_SCI 960config SERIAL_SH_SCI
961 tristate "SuperH SCI(F) serial port support" 961 tristate "SuperH SCI(F) serial port support"
962 depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE) 962 depends on HAVE_CLK && (SUPERH || ARCH_SHMOBILE)
963 select SERIAL_CORE 963 select SERIAL_CORE
964 964
965config SERIAL_SH_SCI_NR_UARTS 965config SERIAL_SH_SCI_NR_UARTS
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index ebd8629c108d..d0a56235c50e 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -54,10 +54,6 @@
54#include <asm/sh_bios.h> 54#include <asm/sh_bios.h>
55#endif 55#endif
56 56
57#ifdef CONFIG_H8300
58#include <asm/gpio.h>
59#endif
60
61#include "sh-sci.h" 57#include "sh-sci.h"
62 58
63struct sci_port { 59struct sci_port {
@@ -66,12 +62,6 @@ struct sci_port {
66 /* Platform configuration */ 62 /* Platform configuration */
67 struct plat_sci_port *cfg; 63 struct plat_sci_port *cfg;
68 64
69 /* Port enable callback */
70 void (*enable)(struct uart_port *port);
71
72 /* Port disable callback */
73 void (*disable)(struct uart_port *port);
74
75 /* Break timer */ 65 /* Break timer */
76 struct timer_list break_timer; 66 struct timer_list break_timer;
77 int break_flag; 67 int break_flag;
@@ -81,6 +71,8 @@ struct sci_port {
81 /* Function clock */ 71 /* Function clock */
82 struct clk *fclk; 72 struct clk *fclk;
83 73
74 char *irqstr[SCIx_NR_IRQS];
75
84 struct dma_chan *chan_tx; 76 struct dma_chan *chan_tx;
85 struct dma_chan *chan_rx; 77 struct dma_chan *chan_rx;
86 78
@@ -121,6 +113,278 @@ to_sci_port(struct uart_port *uart)
121 return container_of(uart, struct sci_port, port); 113 return container_of(uart, struct sci_port, port);
122} 114}
123 115
116struct plat_sci_reg {
117 u8 offset, size;
118};
119
120/* Helper for invalidating specific entries of an inherited map. */
121#define sci_reg_invalid { .offset = 0, .size = 0 }
122
123static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
124 [SCIx_PROBE_REGTYPE] = {
125 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
126 },
127
128 /*
129 * Common SCI definitions, dependent on the port's regshift
130 * value.
131 */
132 [SCIx_SCI_REGTYPE] = {
133 [SCSMR] = { 0x00, 8 },
134 [SCBRR] = { 0x01, 8 },
135 [SCSCR] = { 0x02, 8 },
136 [SCxTDR] = { 0x03, 8 },
137 [SCxSR] = { 0x04, 8 },
138 [SCxRDR] = { 0x05, 8 },
139 [SCFCR] = sci_reg_invalid,
140 [SCFDR] = sci_reg_invalid,
141 [SCTFDR] = sci_reg_invalid,
142 [SCRFDR] = sci_reg_invalid,
143 [SCSPTR] = sci_reg_invalid,
144 [SCLSR] = sci_reg_invalid,
145 },
146
147 /*
148 * Common definitions for legacy IrDA ports, dependent on
149 * regshift value.
150 */
151 [SCIx_IRDA_REGTYPE] = {
152 [SCSMR] = { 0x00, 8 },
153 [SCBRR] = { 0x01, 8 },
154 [SCSCR] = { 0x02, 8 },
155 [SCxTDR] = { 0x03, 8 },
156 [SCxSR] = { 0x04, 8 },
157 [SCxRDR] = { 0x05, 8 },
158 [SCFCR] = { 0x06, 8 },
159 [SCFDR] = { 0x07, 16 },
160 [SCTFDR] = sci_reg_invalid,
161 [SCRFDR] = sci_reg_invalid,
162 [SCSPTR] = sci_reg_invalid,
163 [SCLSR] = sci_reg_invalid,
164 },
165
166 /*
167 * Common SCIFA definitions.
168 */
169 [SCIx_SCIFA_REGTYPE] = {
170 [SCSMR] = { 0x00, 16 },
171 [SCBRR] = { 0x04, 8 },
172 [SCSCR] = { 0x08, 16 },
173 [SCxTDR] = { 0x20, 8 },
174 [SCxSR] = { 0x14, 16 },
175 [SCxRDR] = { 0x24, 8 },
176 [SCFCR] = { 0x18, 16 },
177 [SCFDR] = { 0x1c, 16 },
178 [SCTFDR] = sci_reg_invalid,
179 [SCRFDR] = sci_reg_invalid,
180 [SCSPTR] = sci_reg_invalid,
181 [SCLSR] = sci_reg_invalid,
182 },
183
184 /*
185 * Common SCIFB definitions.
186 */
187 [SCIx_SCIFB_REGTYPE] = {
188 [SCSMR] = { 0x00, 16 },
189 [SCBRR] = { 0x04, 8 },
190 [SCSCR] = { 0x08, 16 },
191 [SCxTDR] = { 0x40, 8 },
192 [SCxSR] = { 0x14, 16 },
193 [SCxRDR] = { 0x60, 8 },
194 [SCFCR] = { 0x18, 16 },
195 [SCFDR] = { 0x1c, 16 },
196 [SCTFDR] = sci_reg_invalid,
197 [SCRFDR] = sci_reg_invalid,
198 [SCSPTR] = sci_reg_invalid,
199 [SCLSR] = sci_reg_invalid,
200 },
201
202 /*
203 * Common SH-3 SCIF definitions.
204 */
205 [SCIx_SH3_SCIF_REGTYPE] = {
206 [SCSMR] = { 0x00, 8 },
207 [SCBRR] = { 0x02, 8 },
208 [SCSCR] = { 0x04, 8 },
209 [SCxTDR] = { 0x06, 8 },
210 [SCxSR] = { 0x08, 16 },
211 [SCxRDR] = { 0x0a, 8 },
212 [SCFCR] = { 0x0c, 8 },
213 [SCFDR] = { 0x0e, 16 },
214 [SCTFDR] = sci_reg_invalid,
215 [SCRFDR] = sci_reg_invalid,
216 [SCSPTR] = sci_reg_invalid,
217 [SCLSR] = sci_reg_invalid,
218 },
219
220 /*
221 * Common SH-4(A) SCIF(B) definitions.
222 */
223 [SCIx_SH4_SCIF_REGTYPE] = {
224 [SCSMR] = { 0x00, 16 },
225 [SCBRR] = { 0x04, 8 },
226 [SCSCR] = { 0x08, 16 },
227 [SCxTDR] = { 0x0c, 8 },
228 [SCxSR] = { 0x10, 16 },
229 [SCxRDR] = { 0x14, 8 },
230 [SCFCR] = { 0x18, 16 },
231 [SCFDR] = { 0x1c, 16 },
232 [SCTFDR] = sci_reg_invalid,
233 [SCRFDR] = sci_reg_invalid,
234 [SCSPTR] = { 0x20, 16 },
235 [SCLSR] = { 0x24, 16 },
236 },
237
238 /*
239 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
240 * register.
241 */
242 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
243 [SCSMR] = { 0x00, 16 },
244 [SCBRR] = { 0x04, 8 },
245 [SCSCR] = { 0x08, 16 },
246 [SCxTDR] = { 0x0c, 8 },
247 [SCxSR] = { 0x10, 16 },
248 [SCxRDR] = { 0x14, 8 },
249 [SCFCR] = { 0x18, 16 },
250 [SCFDR] = { 0x1c, 16 },
251 [SCTFDR] = sci_reg_invalid,
252 [SCRFDR] = sci_reg_invalid,
253 [SCSPTR] = sci_reg_invalid,
254 [SCLSR] = { 0x24, 16 },
255 },
256
257 /*
258 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
259 * count registers.
260 */
261 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
262 [SCSMR] = { 0x00, 16 },
263 [SCBRR] = { 0x04, 8 },
264 [SCSCR] = { 0x08, 16 },
265 [SCxTDR] = { 0x0c, 8 },
266 [SCxSR] = { 0x10, 16 },
267 [SCxRDR] = { 0x14, 8 },
268 [SCFCR] = { 0x18, 16 },
269 [SCFDR] = { 0x1c, 16 },
270 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
271 [SCRFDR] = { 0x20, 16 },
272 [SCSPTR] = { 0x24, 16 },
273 [SCLSR] = { 0x28, 16 },
274 },
275
276 /*
277 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
278 * registers.
279 */
280 [SCIx_SH7705_SCIF_REGTYPE] = {
281 [SCSMR] = { 0x00, 16 },
282 [SCBRR] = { 0x04, 8 },
283 [SCSCR] = { 0x08, 16 },
284 [SCxTDR] = { 0x20, 8 },
285 [SCxSR] = { 0x14, 16 },
286 [SCxRDR] = { 0x24, 8 },
287 [SCFCR] = { 0x18, 16 },
288 [SCFDR] = { 0x1c, 16 },
289 [SCTFDR] = sci_reg_invalid,
290 [SCRFDR] = sci_reg_invalid,
291 [SCSPTR] = sci_reg_invalid,
292 [SCLSR] = sci_reg_invalid,
293 },
294};
295
296#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
297
298/*
299 * The "offset" here is rather misleading, in that it refers to an enum
300 * value relative to the port mapping rather than the fixed offset
301 * itself, which needs to be manually retrieved from the platform's
302 * register map for the given port.
303 */
304static unsigned int sci_serial_in(struct uart_port *p, int offset)
305{
306 struct plat_sci_reg *reg = sci_getreg(p, offset);
307
308 if (reg->size == 8)
309 return ioread8(p->membase + (reg->offset << p->regshift));
310 else if (reg->size == 16)
311 return ioread16(p->membase + (reg->offset << p->regshift));
312 else
313 WARN(1, "Invalid register access\n");
314
315 return 0;
316}
317
318static void sci_serial_out(struct uart_port *p, int offset, int value)
319{
320 struct plat_sci_reg *reg = sci_getreg(p, offset);
321
322 if (reg->size == 8)
323 iowrite8(value, p->membase + (reg->offset << p->regshift));
324 else if (reg->size == 16)
325 iowrite16(value, p->membase + (reg->offset << p->regshift));
326 else
327 WARN(1, "Invalid register access\n");
328}
329
330#define sci_in(up, offset) (up->serial_in(up, offset))
331#define sci_out(up, offset, value) (up->serial_out(up, offset, value))
332
333static int sci_probe_regmap(struct plat_sci_port *cfg)
334{
335 switch (cfg->type) {
336 case PORT_SCI:
337 cfg->regtype = SCIx_SCI_REGTYPE;
338 break;
339 case PORT_IRDA:
340 cfg->regtype = SCIx_IRDA_REGTYPE;
341 break;
342 case PORT_SCIFA:
343 cfg->regtype = SCIx_SCIFA_REGTYPE;
344 break;
345 case PORT_SCIFB:
346 cfg->regtype = SCIx_SCIFB_REGTYPE;
347 break;
348 case PORT_SCIF:
349 /*
350 * The SH-4 is a bit of a misnomer here, although that's
351 * where this particular port layout originated. This
352 * configuration (or some slight variation thereof)
353 * remains the dominant model for all SCIFs.
354 */
355 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
356 break;
357 default:
358 printk(KERN_ERR "Can't probe register map for given port\n");
359 return -EINVAL;
360 }
361
362 return 0;
363}
364
365static void sci_port_enable(struct sci_port *sci_port)
366{
367 if (!sci_port->port.dev)
368 return;
369
370 pm_runtime_get_sync(sci_port->port.dev);
371
372 clk_enable(sci_port->iclk);
373 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
374 clk_enable(sci_port->fclk);
375}
376
377static void sci_port_disable(struct sci_port *sci_port)
378{
379 if (!sci_port->port.dev)
380 return;
381
382 clk_disable(sci_port->fclk);
383 clk_disable(sci_port->iclk);
384
385 pm_runtime_put_sync(sci_port->port.dev);
386}
387
124#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 388#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
125 389
126#ifdef CONFIG_CONSOLE_POLL 390#ifdef CONFIG_CONSOLE_POLL
@@ -164,223 +428,76 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c)
164} 428}
165#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 429#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
166 430
167#if defined(__H8300H__) || defined(__H8300S__)
168static void sci_init_pins(struct uart_port *port, unsigned int cflag) 431static void sci_init_pins(struct uart_port *port, unsigned int cflag)
169{ 432{
170 int ch = (port->mapbase - SMR0) >> 3; 433 struct sci_port *s = to_sci_port(port);
171 434 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
172 /* set DDR regs */
173 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
174 h8300_sci_pins[ch].rx,
175 H8300_GPIO_INPUT);
176 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
177 h8300_sci_pins[ch].tx,
178 H8300_GPIO_OUTPUT);
179
180 /* tx mark output*/
181 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
182}
183#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
184static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
185{
186 if (port->mapbase == 0xA4400000) {
187 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
188 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
189 } else if (port->mapbase == 0xA4410000)
190 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
191}
192#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
193static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
194{
195 unsigned short data;
196
197 if (cflag & CRTSCTS) {
198 /* enable RTS/CTS */
199 if (port->mapbase == 0xa4430000) { /* SCIF0 */
200 /* Clear PTCR bit 9-2; enable all scif pins but sck */
201 data = __raw_readw(PORT_PTCR);
202 __raw_writew((data & 0xfc03), PORT_PTCR);
203 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
204 /* Clear PVCR bit 9-2 */
205 data = __raw_readw(PORT_PVCR);
206 __raw_writew((data & 0xfc03), PORT_PVCR);
207 }
208 } else {
209 if (port->mapbase == 0xa4430000) { /* SCIF0 */
210 /* Clear PTCR bit 5-2; enable only tx and rx */
211 data = __raw_readw(PORT_PTCR);
212 __raw_writew((data & 0xffc3), PORT_PTCR);
213 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
214 /* Clear PVCR bit 5-2 */
215 data = __raw_readw(PORT_PVCR);
216 __raw_writew((data & 0xffc3), PORT_PVCR);
217 }
218 }
219}
220#elif defined(CONFIG_CPU_SH3)
221/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
222static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
223{
224 unsigned short data;
225
226 /* We need to set SCPCR to enable RTS/CTS */
227 data = __raw_readw(SCPCR);
228 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
229 __raw_writew(data & 0x0fcf, SCPCR);
230
231 if (!(cflag & CRTSCTS)) {
232 /* We need to set SCPCR to enable RTS/CTS */
233 data = __raw_readw(SCPCR);
234 /* Clear out SCP7MD1,0, SCP4MD1,0,
235 Set SCP6MD1,0 = {01} (output) */
236 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
237 435
238 data = __raw_readb(SCPDR); 436 /*
239 /* Set /RTS2 (bit6) = 0 */ 437 * Use port-specific handler if provided.
240 __raw_writeb(data & 0xbf, SCPDR); 438 */
439 if (s->cfg->ops && s->cfg->ops->init_pins) {
440 s->cfg->ops->init_pins(port, cflag);
441 return;
241 } 442 }
242}
243#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
244static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
245{
246 unsigned short data;
247 443
248 if (port->mapbase == 0xffe00000) { 444 /*
249 data = __raw_readw(PSCR); 445 * For the generic path SCSPTR is necessary. Bail out if that's
250 data &= ~0x03cf; 446 * unavailable, too.
251 if (!(cflag & CRTSCTS)) 447 */
252 data |= 0x0340; 448 if (!reg->size)
449 return;
253 450
254 __raw_writew(data, PSCR);
255 }
256}
257#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
258 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
259 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
260 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
261 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
262 defined(CONFIG_CPU_SUBTYPE_SHX3)
263static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
264{
265 if (!(cflag & CRTSCTS))
266 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
267}
268#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
269static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
270{
271 if (!(cflag & CRTSCTS)) 451 if (!(cflag & CRTSCTS))
272 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */ 452 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */
273} 453}
274#else
275static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
276{
277 /* Nothing to do */
278}
279#endif
280 454
281#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ 455static int sci_txfill(struct uart_port *port)
282 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
283 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
284 defined(CONFIG_CPU_SUBTYPE_SH7786)
285static int scif_txfill(struct uart_port *port)
286{ 456{
287 return sci_in(port, SCTFDR) & 0xff; 457 struct plat_sci_reg *reg;
288}
289 458
290static int scif_txroom(struct uart_port *port) 459 reg = sci_getreg(port, SCTFDR);
291{ 460 if (reg->size)
292 return SCIF_TXROOM_MAX - scif_txfill(port);
293}
294
295static int scif_rxfill(struct uart_port *port)
296{
297 return sci_in(port, SCRFDR) & 0xff;
298}
299#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
300static int scif_txfill(struct uart_port *port)
301{
302 if (port->mapbase == 0xffe00000 ||
303 port->mapbase == 0xffe08000)
304 /* SCIF0/1*/
305 return sci_in(port, SCTFDR) & 0xff; 461 return sci_in(port, SCTFDR) & 0xff;
306 else 462
307 /* SCIF2 */ 463 reg = sci_getreg(port, SCFDR);
464 if (reg->size)
308 return sci_in(port, SCFDR) >> 8; 465 return sci_in(port, SCFDR) >> 8;
309}
310 466
311static int scif_txroom(struct uart_port *port) 467 return !(sci_in(port, SCxSR) & SCI_TDRE);
312{
313 if (port->mapbase == 0xffe00000 ||
314 port->mapbase == 0xffe08000)
315 /* SCIF0/1*/
316 return SCIF_TXROOM_MAX - scif_txfill(port);
317 else
318 /* SCIF2 */
319 return SCIF2_TXROOM_MAX - scif_txfill(port);
320} 468}
321 469
322static int scif_rxfill(struct uart_port *port) 470static int sci_txroom(struct uart_port *port)
323{
324 if ((port->mapbase == 0xffe00000) ||
325 (port->mapbase == 0xffe08000)) {
326 /* SCIF0/1*/
327 return sci_in(port, SCRFDR) & 0xff;
328 } else {
329 /* SCIF2 */
330 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
331 }
332}
333#elif defined(CONFIG_ARCH_SH7372)
334static int scif_txfill(struct uart_port *port)
335{ 471{
336 if (port->type == PORT_SCIFA) 472 return port->fifosize - sci_txfill(port);
337 return sci_in(port, SCFDR) >> 8;
338 else
339 return sci_in(port, SCTFDR);
340} 473}
341 474
342static int scif_txroom(struct uart_port *port) 475static int sci_rxfill(struct uart_port *port)
343{ 476{
344 return port->fifosize - scif_txfill(port); 477 struct plat_sci_reg *reg;
345}
346 478
347static int scif_rxfill(struct uart_port *port) 479 reg = sci_getreg(port, SCRFDR);
348{ 480 if (reg->size)
349 if (port->type == PORT_SCIFA) 481 return sci_in(port, SCRFDR) & 0xff;
350 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
351 else
352 return sci_in(port, SCRFDR);
353}
354#else
355static int scif_txfill(struct uart_port *port)
356{
357 return sci_in(port, SCFDR) >> 8;
358}
359 482
360static int scif_txroom(struct uart_port *port) 483 reg = sci_getreg(port, SCFDR);
361{ 484 if (reg->size)
362 return SCIF_TXROOM_MAX - scif_txfill(port); 485 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
363}
364 486
365static int scif_rxfill(struct uart_port *port) 487 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
366{
367 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
368} 488}
369#endif
370 489
371static int sci_txfill(struct uart_port *port) 490/*
491 * SCI helper for checking the state of the muxed port/RXD pins.
492 */
493static inline int sci_rxd_in(struct uart_port *port)
372{ 494{
373 return !(sci_in(port, SCxSR) & SCI_TDRE); 495 struct sci_port *s = to_sci_port(port);
374}
375 496
376static int sci_txroom(struct uart_port *port) 497 if (s->cfg->port_reg <= 0)
377{ 498 return 1;
378 return !sci_txfill(port);
379}
380 499
381static int sci_rxfill(struct uart_port *port) 500 return !!__raw_readb(s->cfg->port_reg);
382{
383 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
384} 501}
385 502
386/* ********************************************************************** * 503/* ********************************************************************** *
@@ -406,10 +523,7 @@ static void sci_transmit_chars(struct uart_port *port)
406 return; 523 return;
407 } 524 }
408 525
409 if (port->type == PORT_SCI) 526 count = sci_txroom(port);
410 count = sci_txroom(port);
411 else
412 count = scif_txroom(port);
413 527
414 do { 528 do {
415 unsigned char c; 529 unsigned char c;
@@ -464,13 +578,8 @@ static void sci_receive_chars(struct uart_port *port)
464 return; 578 return;
465 579
466 while (1) { 580 while (1) {
467 if (port->type == PORT_SCI)
468 count = sci_rxfill(port);
469 else
470 count = scif_rxfill(port);
471
472 /* Don't copy more bytes than there is room for in the buffer */ 581 /* Don't copy more bytes than there is room for in the buffer */
473 count = tty_buffer_request_room(tty, count); 582 count = tty_buffer_request_room(tty, sci_rxfill(port));
474 583
475 /* If for any reason we can't copy more data, we're done! */ 584 /* If for any reason we can't copy more data, we're done! */
476 if (count == 0) 585 if (count == 0)
@@ -561,8 +670,7 @@ static void sci_break_timer(unsigned long data)
561{ 670{
562 struct sci_port *port = (struct sci_port *)data; 671 struct sci_port *port = (struct sci_port *)data;
563 672
564 if (port->enable) 673 sci_port_enable(port);
565 port->enable(&port->port);
566 674
567 if (sci_rxd_in(&port->port) == 0) { 675 if (sci_rxd_in(&port->port) == 0) {
568 port->break_flag = 1; 676 port->break_flag = 1;
@@ -574,8 +682,7 @@ static void sci_break_timer(unsigned long data)
574 } else 682 } else
575 port->break_flag = 0; 683 port->break_flag = 0;
576 684
577 if (port->disable) 685 sci_port_disable(port);
578 port->disable(&port->port);
579} 686}
580 687
581static int sci_handle_errors(struct uart_port *port) 688static int sci_handle_errors(struct uart_port *port)
@@ -583,13 +690,19 @@ static int sci_handle_errors(struct uart_port *port)
583 int copied = 0; 690 int copied = 0;
584 unsigned short status = sci_in(port, SCxSR); 691 unsigned short status = sci_in(port, SCxSR);
585 struct tty_struct *tty = port->state->port.tty; 692 struct tty_struct *tty = port->state->port.tty;
693 struct sci_port *s = to_sci_port(port);
586 694
587 if (status & SCxSR_ORER(port)) { 695 /*
588 /* overrun error */ 696 * Handle overruns, if supported.
589 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 697 */
590 copied++; 698 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
699 if (status & (1 << s->cfg->overrun_bit)) {
700 /* overrun error */
701 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
702 copied++;
591 703
592 dev_notice(port->dev, "overrun error"); 704 dev_notice(port->dev, "overrun error");
705 }
593 } 706 }
594 707
595 if (status & SCxSR_FER(port)) { 708 if (status & SCxSR_FER(port)) {
@@ -637,12 +750,15 @@ static int sci_handle_errors(struct uart_port *port)
637static int sci_handle_fifo_overrun(struct uart_port *port) 750static int sci_handle_fifo_overrun(struct uart_port *port)
638{ 751{
639 struct tty_struct *tty = port->state->port.tty; 752 struct tty_struct *tty = port->state->port.tty;
753 struct sci_port *s = to_sci_port(port);
754 struct plat_sci_reg *reg;
640 int copied = 0; 755 int copied = 0;
641 756
642 if (port->type != PORT_SCIF) 757 reg = sci_getreg(port, SCLSR);
758 if (!reg->size)
643 return 0; 759 return 0;
644 760
645 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { 761 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
646 sci_out(port, SCLSR, 0); 762 sci_out(port, SCLSR, 0);
647 763
648 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 764 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
@@ -840,74 +956,102 @@ static int sci_notifier(struct notifier_block *self,
840 return NOTIFY_OK; 956 return NOTIFY_OK;
841} 957}
842 958
843static void sci_clk_enable(struct uart_port *port) 959static struct sci_irq_desc {
844{ 960 const char *desc;
845 struct sci_port *sci_port = to_sci_port(port); 961 irq_handler_t handler;
846 962} sci_irq_desc[] = {
847 pm_runtime_get_sync(port->dev); 963 /*
964 * Split out handlers, the default case.
965 */
966 [SCIx_ERI_IRQ] = {
967 .desc = "rx err",
968 .handler = sci_er_interrupt,
969 },
848 970
849 clk_enable(sci_port->iclk); 971 [SCIx_RXI_IRQ] = {
850 sci_port->port.uartclk = clk_get_rate(sci_port->iclk); 972 .desc = "rx full",
851 clk_enable(sci_port->fclk); 973 .handler = sci_rx_interrupt,
852} 974 },
853 975
854static void sci_clk_disable(struct uart_port *port) 976 [SCIx_TXI_IRQ] = {
855{ 977 .desc = "tx empty",
856 struct sci_port *sci_port = to_sci_port(port); 978 .handler = sci_tx_interrupt,
979 },
857 980
858 clk_disable(sci_port->fclk); 981 [SCIx_BRI_IRQ] = {
859 clk_disable(sci_port->iclk); 982 .desc = "break",
983 .handler = sci_br_interrupt,
984 },
860 985
861 pm_runtime_put_sync(port->dev); 986 /*
862} 987 * Special muxed handler.
988 */
989 [SCIx_MUX_IRQ] = {
990 .desc = "mux",
991 .handler = sci_mpxed_interrupt,
992 },
993};
863 994
864static int sci_request_irq(struct sci_port *port) 995static int sci_request_irq(struct sci_port *port)
865{ 996{
866 int i; 997 struct uart_port *up = &port->port;
867 irqreturn_t (*handlers[4])(int irq, void *ptr) = { 998 int i, j, ret = 0;
868 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, 999
869 sci_br_interrupt, 1000 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
870 }; 1001 struct sci_irq_desc *desc;
871 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", 1002 unsigned int irq;
872 "SCI Transmit Data Empty", "SCI Break" }; 1003
873 1004 if (SCIx_IRQ_IS_MUXED(port)) {
874 if (port->cfg->irqs[0] == port->cfg->irqs[1]) { 1005 i = SCIx_MUX_IRQ;
875 if (unlikely(!port->cfg->irqs[0])) 1006 irq = up->irq;
876 return -ENODEV; 1007 } else
877 1008 irq = port->cfg->irqs[i];
878 if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt, 1009
879 IRQF_DISABLED, "sci", port)) { 1010 desc = sci_irq_desc + i;
880 dev_err(port->port.dev, "Can't allocate IRQ\n"); 1011 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
881 return -ENODEV; 1012 dev_name(up->dev), desc->desc);
1013 if (!port->irqstr[j]) {
1014 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1015 desc->desc);
1016 goto out_nomem;
882 } 1017 }
883 } else { 1018
884 for (i = 0; i < ARRAY_SIZE(handlers); i++) { 1019 ret = request_irq(irq, desc->handler, up->irqflags,
885 if (unlikely(!port->cfg->irqs[i])) 1020 port->irqstr[j], port);
886 continue; 1021 if (unlikely(ret)) {
887 1022 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
888 if (request_irq(port->cfg->irqs[i], handlers[i], 1023 goto out_noirq;
889 IRQF_DISABLED, desc[i], port)) {
890 dev_err(port->port.dev, "Can't allocate IRQ\n");
891 return -ENODEV;
892 }
893 } 1024 }
894 } 1025 }
895 1026
896 return 0; 1027 return 0;
1028
1029out_noirq:
1030 while (--i >= 0)
1031 free_irq(port->cfg->irqs[i], port);
1032
1033out_nomem:
1034 while (--j >= 0)
1035 kfree(port->irqstr[j]);
1036
1037 return ret;
897} 1038}
898 1039
899static void sci_free_irq(struct sci_port *port) 1040static void sci_free_irq(struct sci_port *port)
900{ 1041{
901 int i; 1042 int i;
902 1043
903 if (port->cfg->irqs[0] == port->cfg->irqs[1]) 1044 /*
904 free_irq(port->cfg->irqs[0], port); 1045 * Intentionally in reverse order so we iterate over the muxed
905 else { 1046 * IRQ first.
906 for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) { 1047 */
907 if (!port->cfg->irqs[i]) 1048 for (i = 0; i < SCIx_NR_IRQS; i++) {
908 continue; 1049 free_irq(port->cfg->irqs[i], port);
1050 kfree(port->irqstr[i]);
909 1051
910 free_irq(port->cfg->irqs[i], port); 1052 if (SCIx_IRQ_IS_MUXED(port)) {
1053 /* If there's only one IRQ, we're done. */
1054 return;
911 } 1055 }
912 } 1056 }
913} 1057}
@@ -915,7 +1059,7 @@ static void sci_free_irq(struct sci_port *port)
915static unsigned int sci_tx_empty(struct uart_port *port) 1059static unsigned int sci_tx_empty(struct uart_port *port)
916{ 1060{
917 unsigned short status = sci_in(port, SCxSR); 1061 unsigned short status = sci_in(port, SCxSR);
918 unsigned short in_tx_fifo = scif_txfill(port); 1062 unsigned short in_tx_fifo = sci_txfill(port);
919 1063
920 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1064 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
921} 1065}
@@ -1438,8 +1582,7 @@ static int sci_startup(struct uart_port *port)
1438 1582
1439 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1583 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1440 1584
1441 if (s->enable) 1585 sci_port_enable(s);
1442 s->enable(port);
1443 1586
1444 ret = sci_request_irq(s); 1587 ret = sci_request_irq(s);
1445 if (unlikely(ret < 0)) 1588 if (unlikely(ret < 0))
@@ -1465,8 +1608,7 @@ static void sci_shutdown(struct uart_port *port)
1465 sci_free_dma(port); 1608 sci_free_dma(port);
1466 sci_free_irq(s); 1609 sci_free_irq(s);
1467 1610
1468 if (s->disable) 1611 sci_port_disable(s);
1469 s->disable(port);
1470} 1612}
1471 1613
1472static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, 1614static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
@@ -1513,8 +1655,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1513 if (likely(baud && port->uartclk)) 1655 if (likely(baud && port->uartclk))
1514 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); 1656 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
1515 1657
1516 if (s->enable) 1658 sci_port_enable(s);
1517 s->enable(port);
1518 1659
1519 do { 1660 do {
1520 status = sci_in(port, SCxSR); 1661 status = sci_in(port, SCxSR);
@@ -1584,8 +1725,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1584 if ((termios->c_cflag & CREAD) != 0) 1725 if ((termios->c_cflag & CREAD) != 0)
1585 sci_start_rx(port); 1726 sci_start_rx(port);
1586 1727
1587 if (s->disable) 1728 sci_port_disable(s);
1588 s->disable(port);
1589} 1729}
1590 1730
1591static const char *sci_type(struct uart_port *port) 1731static const char *sci_type(struct uart_port *port)
@@ -1726,6 +1866,7 @@ static int __devinit sci_init_single(struct platform_device *dev,
1726 struct plat_sci_port *p) 1866 struct plat_sci_port *p)
1727{ 1867{
1728 struct uart_port *port = &sci_port->port; 1868 struct uart_port *port = &sci_port->port;
1869 int ret;
1729 1870
1730 port->ops = &sci_uart_ops; 1871 port->ops = &sci_uart_ops;
1731 port->iotype = UPIO_MEM; 1872 port->iotype = UPIO_MEM;
@@ -1746,6 +1887,12 @@ static int __devinit sci_init_single(struct platform_device *dev,
1746 break; 1887 break;
1747 } 1888 }
1748 1889
1890 if (p->regtype == SCIx_PROBE_REGTYPE) {
1891 ret = sci_probe_regmap(p);
1892 if (unlikely(!ret))
1893 return ret;
1894 }
1895
1749 if (dev) { 1896 if (dev) {
1750 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 1897 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1751 if (IS_ERR(sci_port->iclk)) { 1898 if (IS_ERR(sci_port->iclk)) {
@@ -1764,8 +1911,6 @@ static int __devinit sci_init_single(struct platform_device *dev,
1764 if (IS_ERR(sci_port->fclk)) 1911 if (IS_ERR(sci_port->fclk))
1765 sci_port->fclk = NULL; 1912 sci_port->fclk = NULL;
1766 1913
1767 sci_port->enable = sci_clk_enable;
1768 sci_port->disable = sci_clk_disable;
1769 port->dev = &dev->dev; 1914 port->dev = &dev->dev;
1770 1915
1771 pm_runtime_enable(&dev->dev); 1916 pm_runtime_enable(&dev->dev);
@@ -1775,20 +1920,51 @@ static int __devinit sci_init_single(struct platform_device *dev,
1775 sci_port->break_timer.function = sci_break_timer; 1920 sci_port->break_timer.function = sci_break_timer;
1776 init_timer(&sci_port->break_timer); 1921 init_timer(&sci_port->break_timer);
1777 1922
1923 /*
1924 * Establish some sensible defaults for the error detection.
1925 */
1926 if (!p->error_mask)
1927 p->error_mask = (p->type == PORT_SCI) ?
1928 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
1929
1930 /*
1931 * Establish sensible defaults for the overrun detection, unless
1932 * the part has explicitly disabled support for it.
1933 */
1934 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
1935 if (p->type == PORT_SCI)
1936 p->overrun_bit = 5;
1937 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
1938 p->overrun_bit = 9;
1939 else
1940 p->overrun_bit = 0;
1941
1942 /*
1943 * Make the error mask inclusive of overrun detection, if
1944 * supported.
1945 */
1946 p->error_mask |= (1 << p->overrun_bit);
1947 }
1948
1778 sci_port->cfg = p; 1949 sci_port->cfg = p;
1779 1950
1780 port->mapbase = p->mapbase; 1951 port->mapbase = p->mapbase;
1781 port->type = p->type; 1952 port->type = p->type;
1782 port->flags = p->flags; 1953 port->flags = p->flags;
1954 port->regshift = p->regshift;
1783 1955
1784 /* 1956 /*
1785 * The UART port needs an IRQ value, so we peg this to the TX IRQ 1957 * The UART port needs an IRQ value, so we peg this to the RX IRQ
1786 * for the multi-IRQ ports, which is where we are primarily 1958 * for the multi-IRQ ports, which is where we are primarily
1787 * concerned with the shutdown path synchronization. 1959 * concerned with the shutdown path synchronization.
1788 * 1960 *
1789 * For the muxed case there's nothing more to do. 1961 * For the muxed case there's nothing more to do.
1790 */ 1962 */
1791 port->irq = p->irqs[SCIx_RXI_IRQ]; 1963 port->irq = p->irqs[SCIx_RXI_IRQ];
1964 port->irqflags = IRQF_DISABLED;
1965
1966 port->serial_in = sci_serial_in;
1967 port->serial_out = sci_serial_out;
1792 1968
1793 if (p->dma_dev) 1969 if (p->dma_dev)
1794 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n", 1970 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
@@ -1814,8 +1990,7 @@ static void serial_console_write(struct console *co, const char *s,
1814 struct uart_port *port = &sci_port->port; 1990 struct uart_port *port = &sci_port->port;
1815 unsigned short bits; 1991 unsigned short bits;
1816 1992
1817 if (sci_port->enable) 1993 sci_port_enable(sci_port);
1818 sci_port->enable(port);
1819 1994
1820 uart_console_write(port, s, count, serial_console_putchar); 1995 uart_console_write(port, s, count, serial_console_putchar);
1821 1996
@@ -1824,8 +1999,7 @@ static void serial_console_write(struct console *co, const char *s,
1824 while ((sci_in(port, SCxSR) & bits) != bits) 1999 while ((sci_in(port, SCxSR) & bits) != bits)
1825 cpu_relax(); 2000 cpu_relax();
1826 2001
1827 if (sci_port->disable) 2002 sci_port_disable(sci_port);
1828 sci_port->disable(port);
1829} 2003}
1830 2004
1831static int __devinit serial_console_setup(struct console *co, char *options) 2005static int __devinit serial_console_setup(struct console *co, char *options)
@@ -1857,20 +2031,13 @@ static int __devinit serial_console_setup(struct console *co, char *options)
1857 if (unlikely(ret != 0)) 2031 if (unlikely(ret != 0))
1858 return ret; 2032 return ret;
1859 2033
1860 if (sci_port->enable) 2034 sci_port_enable(sci_port);
1861 sci_port->enable(port);
1862 2035
1863 if (options) 2036 if (options)
1864 uart_parse_options(options, &baud, &parity, &bits, &flow); 2037 uart_parse_options(options, &baud, &parity, &bits, &flow);
1865 2038
1866 ret = uart_set_options(port, co, baud, parity, bits, flow);
1867#if defined(__H8300H__) || defined(__H8300S__)
1868 /* disable rx interrupt */
1869 if (ret == 0)
1870 sci_stop_rx(port);
1871#endif
1872 /* TODO: disable clock */ 2039 /* TODO: disable clock */
1873 return ret; 2040 return uart_set_options(port, co, baud, parity, bits, flow);
1874} 2041}
1875 2042
1876static struct console serial_console = { 2043static struct console serial_console = {
@@ -2081,3 +2248,5 @@ module_exit(sci_exit);
2081 2248
2082MODULE_LICENSE("GPL"); 2249MODULE_LICENSE("GPL");
2083MODULE_ALIAS("platform:sh-sci"); 2250MODULE_ALIAS("platform:sh-sci");
2251MODULE_AUTHOR("Paul Mundt");
2252MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index b04d937c9110..e9bed038aa1f 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -2,169 +2,14 @@
2#include <linux/io.h> 2#include <linux/io.h>
3#include <linux/gpio.h> 3#include <linux/gpio.h>
4 4
5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
11
12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
19# define SCIF0 0xA4400000
20# define SCIF2 0xA4410000
21# define SCPCR 0xA4000116
22# define SCPDR 0xA4000136
23#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
24 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
25 defined(CONFIG_ARCH_SH73A0) || \
26 defined(CONFIG_ARCH_SH7367) || \
27 defined(CONFIG_ARCH_SH7377) || \
28 defined(CONFIG_ARCH_SH7372)
29# define PORT_PTCR 0xA405011EUL
30# define PORT_PVCR 0xA4050122UL
31# define SCIF_ORER 0x0200 /* overrun error bit */
32#elif defined(CONFIG_SH_RTS7751R2D)
33# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
34# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
35# define SCIF_ORER 0x0001 /* overrun error bit */
36#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
38 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
39 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
40 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
41 defined(CONFIG_CPU_SUBTYPE_SH7751R)
42# define SCSPTR1 0xffe0001c /* 8 bit SCI */
43# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
44# define SCIF_ORER 0x0001 /* overrun error bit */
45#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
46# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
47# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
48# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
49# define SCIF_ORER 0x0001 /* overrun error bit */
50#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
51# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
52# define SCIF_ORER 0x0001 /* overrun error bit */
53# define PACR 0xa4050100
54# define PBCR 0xa4050102
55#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
56# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
57#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
58# define PADR 0xA4050120
59# define PSDR 0xA405013e
60# define PWDR 0xA4050166
61# define PSCR 0xA405011E
62# define SCIF_ORER 0x0001 /* overrun error bit */
63#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
64# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
65# define SCSPTR0 SCPDR0
66# define SCIF_ORER 0x0001 /* overrun error bit */
67#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
68# define SCSPTR0 0xa4050160
69# define SCIF_ORER 0x0001 /* overrun error bit */
70#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
71# define SCIF_ORER 0x0001 /* overrun error bit */
72#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
73# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
74# define SCIF_ORER 0x0001 /* overrun error bit */
75#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
76# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
77#elif defined(CONFIG_H8S2678)
78# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
79#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
80# define SCSPTR0 0xfe4b0020
81# define SCIF_ORER 0x0001
82#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
83# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
84# define SCIF_ORER 0x0001 /* overrun error bit */
85#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
86# define SCSPTR0 0xff923020 /* 16 bit SCIF */
87# define SCIF_ORER 0x0001 /* overrun error bit */
88#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
89# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
90# define SCIF_ORER 0x0001 /* Overrun error bit */
91#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
92 defined(CONFIG_CPU_SUBTYPE_SH7786)
93# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
94# define SCIF_ORER 0x0001 /* Overrun error bit */
95#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
96 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
97 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
98 defined(CONFIG_CPU_SUBTYPE_SH7263)
99# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
100#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
101# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
102# define SCIF_ORER 0x0001 /* overrun error bit */
103#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
104# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
105# define SCIF_ORER 0x0001 /* Overrun error bit */
106#else
107# error CPU subtype not defined
108#endif
109
110/* SCxSR SCI */
111#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
112#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
113#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
114#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
115#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
116#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
117/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
118/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
119
120#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
121
122/* SCxSR SCIF */
123#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
124#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
125#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
126#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
127#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
128#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
129#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
130#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
131
132#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
133 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
134 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
135 defined(CONFIG_ARCH_SH73A0) || \
136 defined(CONFIG_ARCH_SH7367) || \
137 defined(CONFIG_ARCH_SH7377) || \
138 defined(CONFIG_ARCH_SH7372)
139# define SCIF_ORER 0x0200
140# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
141# define SCIF_RFDC_MASK 0x007f
142# define SCIF_TXROOM_MAX 64
143#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
144# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
145# define SCIF_RFDC_MASK 0x007f
146# define SCIF_TXROOM_MAX 64
147/* SH7763 SCIF2 support */
148# define SCIF2_RFDC_MASK 0x001f
149# define SCIF2_TXROOM_MAX 16
150#else
151# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
152# define SCIF_RFDC_MASK 0x001f
153# define SCIF_TXROOM_MAX 16
154#endif
155
156#ifndef SCIF_ORER
157#define SCIF_ORER 0x0000
158#endif
159
160#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 5#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
161#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
162#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 6#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
163#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 7#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
164#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 8#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
165#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 9#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
166#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 10#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
167#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 11
12#define SCxSR_ERRORS(port) (to_sci_port(port)->cfg->error_mask)
168 13
169#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 14#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
170 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 15 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
@@ -191,278 +36,3 @@
191 36
192#define SCI_MAJOR 204 37#define SCI_MAJOR 204
193#define SCI_MINOR_START 8 38#define SCI_MINOR_START 8
194
195#define SCI_IN(size, offset) \
196 if ((size) == 8) { \
197 return ioread8(port->membase + (offset)); \
198 } else { \
199 return ioread16(port->membase + (offset)); \
200 }
201#define SCI_OUT(size, offset, value) \
202 if ((size) == 8) { \
203 iowrite8(value, port->membase + (offset)); \
204 } else if ((size) == 16) { \
205 iowrite16(value, port->membase + (offset)); \
206 }
207
208#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
209 static inline unsigned int sci_##name##_in(struct uart_port *port) \
210 { \
211 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
212 SCI_IN(scif_size, scif_offset) \
213 } else { /* PORT_SCI or PORT_SCIFA */ \
214 SCI_IN(sci_size, sci_offset); \
215 } \
216 } \
217 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
218 { \
219 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
220 SCI_OUT(scif_size, scif_offset, value) \
221 } else { /* PORT_SCI or PORT_SCIFA */ \
222 SCI_OUT(sci_size, sci_offset, value); \
223 } \
224 }
225
226#ifdef CONFIG_H8300
227/* h8300 don't have SCIF */
228#define CPU_SCIF_FNS(name) \
229 static inline unsigned int sci_##name##_in(struct uart_port *port) \
230 { \
231 return 0; \
232 } \
233 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
234 { \
235 }
236#else
237#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
238 static inline unsigned int sci_##name##_in(struct uart_port *port) \
239 { \
240 SCI_IN(scif_size, scif_offset); \
241 } \
242 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
243 { \
244 SCI_OUT(scif_size, scif_offset, value); \
245 }
246#endif
247
248#define CPU_SCI_FNS(name, sci_offset, sci_size) \
249 static inline unsigned int sci_##name##_in(struct uart_port* port) \
250 { \
251 SCI_IN(sci_size, sci_offset); \
252 } \
253 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
254 { \
255 SCI_OUT(sci_size, sci_offset, value); \
256 }
257
258#if defined(CONFIG_CPU_SH3) || \
259 defined(CONFIG_ARCH_SH73A0) || \
260 defined(CONFIG_ARCH_SH7367) || \
261 defined(CONFIG_ARCH_SH7377) || \
262 defined(CONFIG_ARCH_SH7372)
263#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
264#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
265 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
266 h8_sci_offset, h8_sci_size) \
267 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
268#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
269 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
270#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
271 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
272 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
273 defined(CONFIG_ARCH_SH7367)
274#define SCIF_FNS(name, scif_offset, scif_size) \
275 CPU_SCIF_FNS(name, scif_offset, scif_size)
276#elif defined(CONFIG_ARCH_SH7377) || \
277 defined(CONFIG_ARCH_SH7372) || \
278 defined(CONFIG_ARCH_SH73A0)
279#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
280 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
281#define SCIF_FNS(name, scif_offset, scif_size) \
282 CPU_SCIF_FNS(name, scif_offset, scif_size)
283#else
284#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
285 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
286 h8_sci_offset, h8_sci_size) \
287 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
288#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
289 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
290#endif
291#elif defined(__H8300H__) || defined(__H8300S__)
292#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
293 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
294 h8_sci_offset, h8_sci_size) \
295 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
296#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
297 CPU_SCIF_FNS(name)
298#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
299 defined(CONFIG_CPU_SUBTYPE_SH7724)
300 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
301 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
302 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
303 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
304#else
305#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
306 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
307 h8_sci_offset, h8_sci_size) \
308 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
309#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
310 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
311#endif
312
313#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
314 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
315 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
316 defined(CONFIG_ARCH_SH7367)
317
318SCIF_FNS(SCSMR, 0x00, 16)
319SCIF_FNS(SCBRR, 0x04, 8)
320SCIF_FNS(SCSCR, 0x08, 16)
321SCIF_FNS(SCxSR, 0x14, 16)
322SCIF_FNS(SCFCR, 0x18, 16)
323SCIF_FNS(SCFDR, 0x1c, 16)
324SCIF_FNS(SCxTDR, 0x20, 8)
325SCIF_FNS(SCxRDR, 0x24, 8)
326SCIF_FNS(SCLSR, 0x00, 0)
327#elif defined(CONFIG_ARCH_SH7377) || \
328 defined(CONFIG_ARCH_SH7372) || \
329 defined(CONFIG_ARCH_SH73A0)
330SCIF_FNS(SCSMR, 0x00, 16)
331SCIF_FNS(SCBRR, 0x04, 8)
332SCIF_FNS(SCSCR, 0x08, 16)
333SCIF_FNS(SCTDSR, 0x0c, 16)
334SCIF_FNS(SCFER, 0x10, 16)
335SCIF_FNS(SCxSR, 0x14, 16)
336SCIF_FNS(SCFCR, 0x18, 16)
337SCIF_FNS(SCFDR, 0x1c, 16)
338SCIF_FNS(SCTFDR, 0x38, 16)
339SCIF_FNS(SCRFDR, 0x3c, 16)
340SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
341SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
342SCIF_FNS(SCLSR, 0x00, 0)
343#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
344 defined(CONFIG_CPU_SUBTYPE_SH7724)
345SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
346SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
347SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
348SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
349SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
350SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
351SCIx_FNS(SCSPTR, 0, 0, 0, 0)
352SCIF_FNS(SCFCR, 0x18, 16)
353SCIF_FNS(SCFDR, 0x1c, 16)
354SCIF_FNS(SCLSR, 0x24, 16)
355#else
356/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
357/* name off sz off sz off sz off sz off sz*/
358SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
359SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
360SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
361SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
362SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
363SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
364SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
365#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
366 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
367 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
368 defined(CONFIG_CPU_SUBTYPE_SH7786)
369SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
370SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
371SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
372SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
373SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
374#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
375SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
376SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
377SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
378SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
379SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
380#else
381SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
382#if defined(CONFIG_CPU_SUBTYPE_SH7722)
383SCIF_FNS(SCSPTR, 0, 0, 0, 0)
384#else
385SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
386#endif
387SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
388#endif
389#endif
390#define sci_in(port, reg) sci_##reg##_in(port)
391#define sci_out(port, reg, value) sci_##reg##_out(port, value)
392
393/* H8/300 series SCI pins assignment */
394#if defined(__H8300H__) || defined(__H8300S__)
395static const struct __attribute__((packed)) {
396 int port; /* GPIO port no */
397 unsigned short rx,tx; /* GPIO bit no */
398} h8300_sci_pins[] = {
399#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
400 { /* SCI0 */
401 .port = H8300_GPIO_P9,
402 .rx = H8300_GPIO_B2,
403 .tx = H8300_GPIO_B0,
404 },
405 { /* SCI1 */
406 .port = H8300_GPIO_P9,
407 .rx = H8300_GPIO_B3,
408 .tx = H8300_GPIO_B1,
409 },
410 { /* SCI2 */
411 .port = H8300_GPIO_PB,
412 .rx = H8300_GPIO_B7,
413 .tx = H8300_GPIO_B6,
414 }
415#elif defined(CONFIG_H8S2678)
416 { /* SCI0 */
417 .port = H8300_GPIO_P3,
418 .rx = H8300_GPIO_B2,
419 .tx = H8300_GPIO_B0,
420 },
421 { /* SCI1 */
422 .port = H8300_GPIO_P3,
423 .rx = H8300_GPIO_B3,
424 .tx = H8300_GPIO_B1,
425 },
426 { /* SCI2 */
427 .port = H8300_GPIO_P5,
428 .rx = H8300_GPIO_B1,
429 .tx = H8300_GPIO_B0,
430 }
431#endif
432};
433#endif
434
435#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
436 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
437 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
438 defined(CONFIG_CPU_SUBTYPE_SH7709)
439static inline int sci_rxd_in(struct uart_port *port)
440{
441 if (port->mapbase == 0xfffffe80)
442 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
443 return 1;
444}
445#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
446 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
447 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
448 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
449 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
450 defined(CONFIG_CPU_SUBTYPE_SH7091)
451static inline int sci_rxd_in(struct uart_port *port)
452{
453 if (port->mapbase == 0xffe00000)
454 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
455 return 1;
456}
457#elif defined(__H8300H__) || defined(__H8300S__)
458static inline int sci_rxd_in(struct uart_port *port)
459{
460 int ch = (port->mapbase - SMR0) >> 3;
461 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
462}
463#else /* default case for non-SCI processors */
464static inline int sci_rxd_in(struct uart_port *port)
465{
466 return 1;
467}
468#endif
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index a2afc9fbe186..8bffe9ae2ca0 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -8,6 +8,8 @@
8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts) 8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
9 */ 9 */
10 10
11#define SCIx_NOT_SUPPORTED (-1)
12
11enum { 13enum {
12 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */ 14 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
13 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */ 15 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
@@ -25,6 +27,28 @@ enum {
25#define SCSCR_CKE1 (1 << 1) 27#define SCSCR_CKE1 (1 << 1)
26#define SCSCR_CKE0 (1 << 0) 28#define SCSCR_CKE0 (1 << 0)
27 29
30/* SCxSR SCI */
31#define SCI_TDRE 0x80
32#define SCI_RDRF 0x40
33#define SCI_ORER 0x20
34#define SCI_FER 0x10
35#define SCI_PER 0x08
36#define SCI_TEND 0x04
37
38#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
39
40/* SCxSR SCIF */
41#define SCIF_ER 0x0080
42#define SCIF_TEND 0x0040
43#define SCIF_TDFE 0x0020
44#define SCIF_BRK 0x0010
45#define SCIF_FER 0x0008
46#define SCIF_PER 0x0004
47#define SCIF_RDF 0x0002
48#define SCIF_DR 0x0001
49
50#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
51
28/* Offsets into the sci_port->irqs array */ 52/* Offsets into the sci_port->irqs array */
29enum { 53enum {
30 SCIx_ERI_IRQ, 54 SCIx_ERI_IRQ,
@@ -32,6 +56,24 @@ enum {
32 SCIx_TXI_IRQ, 56 SCIx_TXI_IRQ,
33 SCIx_BRI_IRQ, 57 SCIx_BRI_IRQ,
34 SCIx_NR_IRQS, 58 SCIx_NR_IRQS,
59
60 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
61};
62
63enum {
64 SCIx_PROBE_REGTYPE,
65
66 SCIx_SCI_REGTYPE,
67 SCIx_IRDA_REGTYPE,
68 SCIx_SCIFA_REGTYPE,
69 SCIx_SCIFB_REGTYPE,
70 SCIx_SH3_SCIF_REGTYPE,
71 SCIx_SH4_SCIF_REGTYPE,
72 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
73 SCIx_SH4_SCIF_FIFODATA_REGTYPE,
74 SCIx_SH7705_SCIF_REGTYPE,
75
76 SCIx_NR_REGTYPES,
35}; 77};
36 78
37#define SCIx_IRQ_MUXED(irq) \ 79#define SCIx_IRQ_MUXED(irq) \
@@ -42,8 +84,29 @@ enum {
42 [SCIx_BRI_IRQ] = (irq), \ 84 [SCIx_BRI_IRQ] = (irq), \
43} 85}
44 86
87#define SCIx_IRQ_IS_MUXED(port) \
88 ((port)->cfg->irqs[SCIx_ERI_IRQ] == \
89 (port)->cfg->irqs[SCIx_RXI_IRQ]) || \
90 ((port)->cfg->irqs[SCIx_ERI_IRQ] && \
91 !(port)->cfg->irqs[SCIx_RXI_IRQ])
92/*
93 * SCI register subset common for all port types.
94 * Not all registers will exist on all parts.
95 */
96enum {
97 SCSMR, SCBRR, SCSCR, SCxSR,
98 SCFCR, SCFDR, SCxTDR, SCxRDR,
99 SCLSR, SCTFDR, SCRFDR, SCSPTR,
100
101 SCIx_NR_REGS,
102};
103
45struct device; 104struct device;
46 105
106struct plat_sci_port_ops {
107 void (*init_pins)(struct uart_port *, unsigned int cflag);
108};
109
47/* 110/*
48 * Platform device specific platform_data struct 111 * Platform device specific platform_data struct
49 */ 112 */
@@ -56,6 +119,18 @@ struct plat_sci_port {
56 unsigned int scbrr_algo_id; /* SCBRR calculation algo */ 119 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
57 unsigned int scscr; /* SCSCR initialization */ 120 unsigned int scscr; /* SCSCR initialization */
58 121
122 /*
123 * Platform overrides if necessary, defaults otherwise.
124 */
125 int overrun_bit;
126 unsigned int error_mask;
127
128 int port_reg;
129 unsigned char regshift;
130 unsigned char regtype;
131
132 struct plat_sci_port_ops *ops;
133
59 struct device *dma_dev; 134 struct device *dma_dev;
60 135
61 unsigned int dma_slave_tx; 136 unsigned int dma_slave_tx;
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
index 9a52f72527dc..3ccf18648d0a 100644
--- a/include/linux/sh_clk.h
+++ b/include/linux/sh_clk.h
@@ -147,4 +147,8 @@ int sh_clk_div4_reparent_register(struct clk *clks, int nr,
147int sh_clk_div6_register(struct clk *clks, int nr); 147int sh_clk_div6_register(struct clk *clks, int nr);
148int sh_clk_div6_reparent_register(struct clk *clks, int nr); 148int sh_clk_div6_reparent_register(struct clk *clks, int nr);
149 149
150#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
151#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
152#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
153
150#endif /* __SH_CLOCK_H */ 154#endif /* __SH_CLOCK_H */
diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
index b08cd4efa15c..cb2dd118cc0f 100644
--- a/include/linux/sh_dma.h
+++ b/include/linux/sh_dma.h
@@ -62,6 +62,12 @@ struct sh_dmae_pdata {
62 const unsigned int *ts_shift; 62 const unsigned int *ts_shift;
63 int ts_shift_num; 63 int ts_shift_num;
64 u16 dmaor_init; 64 u16 dmaor_init;
65 unsigned int chcr_offset;
66 u32 chcr_ie_bit;
67
68 unsigned int dmaor_is_32bit:1;
69 unsigned int needs_tend_set:1;
70 unsigned int no_dmars:1;
65}; 71};
66 72
67/* DMA register */ 73/* DMA register */
@@ -71,6 +77,8 @@ struct sh_dmae_pdata {
71#define CHCR 0x0C 77#define CHCR 0x0C
72#define DMAOR 0x40 78#define DMAOR 0x40
73 79
80#define TEND 0x18 /* USB-DMAC */
81
74/* DMAOR definitions */ 82/* DMAOR definitions */
75#define DMAOR_AE 0x00000004 83#define DMAOR_AE 0x00000004
76#define DMAOR_NMIF 0x00000002 84#define DMAOR_NMIF 0x00000002
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-12 02:12:40 -0400