aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/regulator/ab8500.c
diff options
context:
space:
mode:
authorLee Jones <lee.jones@linaro.org>2013-03-28 12:11:14 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-04-01 08:23:38 -0400
commit547f384f33dbd6171607f925ab246e25e315961e (patch)
tree95ce40b8ffd846948718b980b58a13ac66e09031 /drivers/regulator/ab8500.c
parenta6324709ab4e8a06cb61aa4f7aa3374679d5f426 (diff)
regulator: ab8500: add support for ab8505
To obtain full AB8505 regulator support, the AB8500 regulator driver first needs to know its register layout and their initialisation values for each. That information is provided via a couple of large data structures which we provide here. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'drivers/regulator/ab8500.c')
-rw-r--r--drivers/regulator/ab8500.c617
1 files changed, 617 insertions, 0 deletions
diff --git a/drivers/regulator/ab8500.c b/drivers/regulator/ab8500.c
index 9de3a211b0b4..1ab0f8a7c862 100644
--- a/drivers/regulator/ab8500.c
+++ b/drivers/regulator/ab8500.c
@@ -5,11 +5,15 @@
5 * 5 *
6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson 7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
8 * 9 *
9 * AB8500 peripheral regulators 10 * AB8500 peripheral regulators
10 * 11 *
11 * AB8500 supports the following regulators: 12 * AB8500 supports the following regulators:
12 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA 13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
14 *
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
13 */ 17 */
14#include <linux/init.h> 18#include <linux/init.h>
15#include <linux/kernel.h> 19#include <linux/kernel.h>
@@ -92,6 +96,17 @@ static const unsigned int ldo_vaux3_voltages[] = {
92 2910000, 96 2910000,
93}; 97};
94 98
99static const int ldo_vaux56_voltages[] = {
100 1800000,
101 1050000,
102 1100000,
103 1200000,
104 1500000,
105 2200000,
106 2500000,
107 2790000,
108};
109
95static const unsigned int ldo_vintcore_voltages[] = { 110static const unsigned int ldo_vintcore_voltages[] = {
96 1200000, 111 1200000,
97 1225000, 112 1225000,
@@ -589,6 +604,313 @@ static struct ab8500_regulator_info
589 }, 604 },
590}; 605};
591 606
607/* AB8505 regulator information */
608static struct ab8500_regulator_info
609 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
610 /*
611 * Variable Voltage Regulators
612 * name, min mV, max mV,
613 * update bank, reg, mask, enable val
614 * volt bank, reg, mask, table, table length
615 */
616 [AB8505_LDO_AUX1] = {
617 .desc = {
618 .name = "LDO-AUX1",
619 .ops = &ab8500_regulator_volt_mode_ops,
620 .type = REGULATOR_VOLTAGE,
621 .id = AB8500_LDO_AUX1,
622 .owner = THIS_MODULE,
623 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
624 },
625 .min_uV = 1100000,
626 .max_uV = 3300000,
627 .load_lp_uA = 5000,
628 .update_bank = 0x04,
629 .update_reg = 0x09,
630 .update_mask = 0x03,
631 .update_val = 0x01,
632 .update_val_idle = 0x03,
633 .update_val_normal = 0x01,
634 .voltage_bank = 0x04,
635 .voltage_reg = 0x1f,
636 .voltage_mask = 0x0f,
637 .voltages = ldo_vauxn_voltages,
638 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
639 },
640 [AB8505_LDO_AUX2] = {
641 .desc = {
642 .name = "LDO-AUX2",
643 .ops = &ab8500_regulator_volt_mode_ops,
644 .type = REGULATOR_VOLTAGE,
645 .id = AB8500_LDO_AUX2,
646 .owner = THIS_MODULE,
647 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
648 },
649 .min_uV = 1100000,
650 .max_uV = 3300000,
651 .load_lp_uA = 5000,
652 .update_bank = 0x04,
653 .update_reg = 0x09,
654 .update_mask = 0x0c,
655 .update_val = 0x04,
656 .update_val_idle = 0x0c,
657 .update_val_normal = 0x04,
658 .voltage_bank = 0x04,
659 .voltage_reg = 0x20,
660 .voltage_mask = 0x0f,
661 .voltages = ldo_vauxn_voltages,
662 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
663 },
664 [AB8505_LDO_AUX3] = {
665 .desc = {
666 .name = "LDO-AUX3",
667 .ops = &ab8500_regulator_volt_mode_ops,
668 .type = REGULATOR_VOLTAGE,
669 .id = AB8500_LDO_AUX3,
670 .owner = THIS_MODULE,
671 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
672 },
673 .min_uV = 1100000,
674 .max_uV = 3300000,
675 .load_lp_uA = 5000,
676 .update_bank = 0x04,
677 .update_reg = 0x0a,
678 .update_mask = 0x03,
679 .update_val = 0x01,
680 .update_val_idle = 0x03,
681 .update_val_normal = 0x01,
682 .voltage_bank = 0x04,
683 .voltage_reg = 0x21,
684 .voltage_mask = 0x07,
685 .voltages = ldo_vaux3_voltages,
686 .voltages_len = ARRAY_SIZE(ldo_vaux3_voltages),
687 },
688 [AB8505_LDO_AUX4] = {
689 .desc = {
690 .name = "LDO-AUX4",
691 .ops = &ab8500_regulator_volt_mode_ops,
692 .type = REGULATOR_VOLTAGE,
693 .id = AB9540_LDO_AUX4,
694 .owner = THIS_MODULE,
695 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
696 },
697 .min_uV = 1100000,
698 .max_uV = 3300000,
699 .load_lp_uA = 5000,
700 /* values for Vaux4Regu register */
701 .update_bank = 0x04,
702 .update_reg = 0x2e,
703 .update_mask = 0x03,
704 .update_val = 0x01,
705 .update_val_idle = 0x03,
706 .update_val_normal = 0x01,
707 /* values for Vaux4SEL register */
708 .voltage_bank = 0x04,
709 .voltage_reg = 0x2f,
710 .voltage_mask = 0x0f,
711 .voltages = ldo_vauxn_voltages,
712 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
713 },
714 [AB8505_LDO_AUX5] = {
715 .desc = {
716 .name = "LDO-AUX5",
717 .ops = &ab8500_regulator_volt_mode_ops,
718 .type = REGULATOR_VOLTAGE,
719 .id = AB8505_LDO_AUX5,
720 .owner = THIS_MODULE,
721 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
722 },
723 .min_uV = 1050000,
724 .max_uV = 2790000,
725 .load_lp_uA = 2000,
726 /* values for CtrlVaux5 register */
727 .update_bank = 0x01,
728 .update_reg = 0x55,
729 .update_mask = 0x08,
730 .update_val = 0x00,
731 .update_val_idle = 0x01,
732 .update_val_normal = 0x00,
733 .voltage_bank = 0x01,
734 .voltage_reg = 0x55,
735 .voltage_mask = 0x07,
736 .voltages = ldo_vaux56_voltages,
737 .voltages_len = ARRAY_SIZE(ldo_vaux56_voltages),
738 },
739 [AB8505_LDO_AUX6] = {
740 .desc = {
741 .name = "LDO-AUX6",
742 .ops = &ab8500_regulator_volt_mode_ops,
743 .type = REGULATOR_VOLTAGE,
744 .id = AB8505_LDO_AUX6,
745 .owner = THIS_MODULE,
746 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
747 },
748 .min_uV = 1050000,
749 .max_uV = 2790000,
750 .load_lp_uA = 2000,
751 /* values for CtrlVaux6 register */
752 .update_bank = 0x01,
753 .update_reg = 0x56,
754 .update_mask = 0x08,
755 .update_val = 0x00,
756 .update_val_idle = 0x01,
757 .update_val_normal = 0x00,
758 .voltage_bank = 0x01,
759 .voltage_reg = 0x56,
760 .voltage_mask = 0x07,
761 .voltages = ldo_vaux56_voltages,
762 .voltages_len = ARRAY_SIZE(ldo_vaux56_voltages),
763 },
764 [AB8505_LDO_INTCORE] = {
765 .desc = {
766 .name = "LDO-INTCORE",
767 .ops = &ab8500_regulator_volt_mode_ops,
768 .type = REGULATOR_VOLTAGE,
769 .id = AB8500_LDO_INTCORE,
770 .owner = THIS_MODULE,
771 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
772 },
773 .min_uV = 1100000,
774 .max_uV = 3300000,
775 .load_lp_uA = 5000,
776 .update_bank = 0x03,
777 .update_reg = 0x80,
778 .update_mask = 0x44,
779 .update_val = 0x04,
780 .update_val_idle = 0x44,
781 .update_val_normal = 0x04,
782 .voltage_bank = 0x03,
783 .voltage_reg = 0x80,
784 .voltage_mask = 0x38,
785 .voltages = ldo_vintcore_voltages,
786 .voltages_len = ARRAY_SIZE(ldo_vintcore_voltages),
787 .voltage_shift = 3,
788 },
789
790 /*
791 * Fixed Voltage Regulators
792 * name, fixed mV,
793 * update bank, reg, mask, enable val
794 */
795 [AB8505_LDO_ADC] = {
796 .desc = {
797 .name = "LDO-ADC",
798 .ops = &ab8500_regulator_mode_ops,
799 .type = REGULATOR_VOLTAGE,
800 .id = AB8505_LDO_ADC,
801 .owner = THIS_MODULE,
802 .n_voltages = 1,
803 },
804 .delay = 10000,
805 .fixed_uV = 2000000,
806 .load_lp_uA = 1000,
807 .update_bank = 0x03,
808 .update_reg = 0x80,
809 .update_mask = 0x82,
810 .update_val = 0x02,
811 .update_val_idle = 0x82,
812 .update_val_normal = 0x02,
813 },
814 [AB8505_LDO_USB] = {
815 .desc = {
816 .name = "LDO-USB",
817 .ops = &ab8500_regulator_mode_ops,
818 .type = REGULATOR_VOLTAGE,
819 .id = AB9540_LDO_USB,
820 .owner = THIS_MODULE,
821 .n_voltages = 1,
822 },
823 .fixed_uV = 3300000,
824 .update_bank = 0x03,
825 .update_reg = 0x82,
826 .update_mask = 0x03,
827 .update_val = 0x01,
828 .update_val_idle = 0x03,
829 .update_val_normal = 0x01,
830 },
831 [AB8505_LDO_AUDIO] = {
832 .desc = {
833 .name = "LDO-AUDIO",
834 .ops = &ab8500_regulator_ops,
835 .type = REGULATOR_VOLTAGE,
836 .id = AB8500_LDO_AUDIO,
837 .owner = THIS_MODULE,
838 .n_voltages = 1,
839 },
840 .fixed_uV = 2000000,
841 .update_bank = 0x03,
842 .update_reg = 0x83,
843 .update_mask = 0x02,
844 .update_val = 0x02,
845 },
846 [AB8505_LDO_ANAMIC1] = {
847 .desc = {
848 .name = "LDO-ANAMIC1",
849 .ops = &ab8500_regulator_ops,
850 .type = REGULATOR_VOLTAGE,
851 .id = AB8500_LDO_ANAMIC1,
852 .owner = THIS_MODULE,
853 .n_voltages = 1,
854 },
855 .fixed_uV = 2050000,
856 .update_bank = 0x03,
857 .update_reg = 0x83,
858 .update_mask = 0x08,
859 .update_val = 0x08,
860 },
861 [AB8505_LDO_ANAMIC2] = {
862 .desc = {
863 .name = "LDO-ANAMIC2",
864 .ops = &ab8500_regulator_ops,
865 .type = REGULATOR_VOLTAGE,
866 .id = AB8500_LDO_ANAMIC2,
867 .owner = THIS_MODULE,
868 .n_voltages = 1,
869 },
870 .fixed_uV = 2050000,
871 .update_bank = 0x03,
872 .update_reg = 0x83,
873 .update_mask = 0x10,
874 .update_val = 0x10,
875 },
876 [AB8505_LDO_AUX8] = {
877 .desc = {
878 .name = "LDO-AUX8",
879 .ops = &ab8500_regulator_ops,
880 .type = REGULATOR_VOLTAGE,
881 .id = AB8505_LDO_AUX8,
882 .owner = THIS_MODULE,
883 .n_voltages = 1,
884 },
885 .fixed_uV = 1800000,
886 .update_bank = 0x03,
887 .update_reg = 0x83,
888 .update_mask = 0x04,
889 .update_val = 0x04,
890 },
891 /*
892 * Regulators with fixed voltage and normal/idle modes
893 */
894 [AB8505_LDO_ANA] = {
895 .desc = {
896 .name = "LDO-ANA",
897 .ops = &ab8500_regulator_mode_ops,
898 .type = REGULATOR_VOLTAGE,
899 .id = AB8500_LDO_ANA,
900 .owner = THIS_MODULE,
901 .n_voltages = 1,
902 },
903 .fixed_uV = 1200000,
904 .load_lp_uA = 1000,
905 .update_bank = 0x04,
906 .update_reg = 0x06,
907 .update_mask = 0x0c,
908 .update_val = 0x04,
909 .update_val_idle = 0x0c,
910 .update_val_normal = 0x04,
911 },
912};
913
592/* AB9540 regulator information */ 914/* AB9540 regulator information */
593static struct ab8500_regulator_info 915static struct ab8500_regulator_info
594 ab9540_regulator_info[AB9540_NUM_REGULATORS] = { 916 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
@@ -1031,6 +1353,276 @@ static struct ab8500_reg_init ab8500_reg_init[] = {
1031 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16), 1353 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
1032}; 1354};
1033 1355
1356/* AB8505 register init */
1357static struct ab8500_reg_init ab8505_reg_init[] = {
1358 /*
1359 * 0x03, VarmRequestCtrl
1360 * 0x0c, VsmpsCRequestCtrl
1361 * 0x30, VsmpsARequestCtrl
1362 * 0xc0, VsmpsBRequestCtrl
1363 */
1364 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1365 /*
1366 * 0x03, VsafeRequestCtrl
1367 * 0x0c, VpllRequestCtrl
1368 * 0x30, VanaRequestCtrl
1369 */
1370 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
1371 /*
1372 * 0x30, Vaux1RequestCtrl
1373 * 0xc0, Vaux2RequestCtrl
1374 */
1375 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
1376 /*
1377 * 0x03, Vaux3RequestCtrl
1378 * 0x04, SwHPReq
1379 */
1380 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1381 /*
1382 * 0x01, VsmpsASysClkReq1HPValid
1383 * 0x02, VsmpsBSysClkReq1HPValid
1384 * 0x04, VsafeSysClkReq1HPValid
1385 * 0x08, VanaSysClkReq1HPValid
1386 * 0x10, VpllSysClkReq1HPValid
1387 * 0x20, Vaux1SysClkReq1HPValid
1388 * 0x40, Vaux2SysClkReq1HPValid
1389 * 0x80, Vaux3SysClkReq1HPValid
1390 */
1391 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
1392 /*
1393 * 0x01, VsmpsCSysClkReq1HPValid
1394 * 0x02, VarmSysClkReq1HPValid
1395 * 0x04, VbbSysClkReq1HPValid
1396 * 0x08, VsmpsMSysClkReq1HPValid
1397 */
1398 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
1399 /*
1400 * 0x01, VsmpsAHwHPReq1Valid
1401 * 0x02, VsmpsBHwHPReq1Valid
1402 * 0x04, VsafeHwHPReq1Valid
1403 * 0x08, VanaHwHPReq1Valid
1404 * 0x10, VpllHwHPReq1Valid
1405 * 0x20, Vaux1HwHPReq1Valid
1406 * 0x40, Vaux2HwHPReq1Valid
1407 * 0x80, Vaux3HwHPReq1Valid
1408 */
1409 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
1410 /*
1411 * 0x08, VsmpsMHwHPReq1Valid
1412 */
1413 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
1414 /*
1415 * 0x01, VsmpsAHwHPReq2Valid
1416 * 0x02, VsmpsBHwHPReq2Valid
1417 * 0x04, VsafeHwHPReq2Valid
1418 * 0x08, VanaHwHPReq2Valid
1419 * 0x10, VpllHwHPReq2Valid
1420 * 0x20, Vaux1HwHPReq2Valid
1421 * 0x40, Vaux2HwHPReq2Valid
1422 * 0x80, Vaux3HwHPReq2Valid
1423 */
1424 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
1425 /*
1426 * 0x08, VsmpsMHwHPReq2Valid
1427 */
1428 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
1429 /*
1430 * 0x01, VsmpsCSwHPReqValid
1431 * 0x02, VarmSwHPReqValid
1432 * 0x04, VsmpsASwHPReqValid
1433 * 0x08, VsmpsBSwHPReqValid
1434 * 0x10, VsafeSwHPReqValid
1435 * 0x20, VanaSwHPReqValid
1436 * 0x40, VpllSwHPReqValid
1437 * 0x80, Vaux1SwHPReqValid
1438 */
1439 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
1440 /*
1441 * 0x01, Vaux2SwHPReqValid
1442 * 0x02, Vaux3SwHPReqValid
1443 * 0x20, VsmpsMSwHPReqValid
1444 */
1445 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
1446 /*
1447 * 0x02, SysClkReq2Valid1
1448 * 0x04, SysClkReq3Valid1
1449 * 0x08, SysClkReq4Valid1
1450 */
1451 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
1452 /*
1453 * 0x02, SysClkReq2Valid2
1454 * 0x04, SysClkReq3Valid2
1455 * 0x08, SysClkReq4Valid2
1456 */
1457 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
1458 /*
1459 * 0x01, Vaux4SwHPReqValid
1460 * 0x02, Vaux4HwHPReq2Valid
1461 * 0x04, Vaux4HwHPReq1Valid
1462 * 0x08, Vaux4SysClkReq1HPValid
1463 */
1464 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
1465 /*
1466 * 0x02, VadcEna
1467 * 0x04, VintCore12Ena
1468 * 0x38, VintCore12Sel
1469 * 0x40, VintCore12LP
1470 * 0x80, VadcLP
1471 */
1472 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
1473 /*
1474 * 0x02, VaudioEna
1475 * 0x04, VdmicEna
1476 * 0x08, Vamic1Ena
1477 * 0x10, Vamic2Ena
1478 */
1479 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1480 /*
1481 * 0x01, Vamic1_dzout
1482 * 0x02, Vamic2_dzout
1483 */
1484 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
1485 /*
1486 * 0x03, VsmpsARegu
1487 * 0x0c, VsmpsASelCtrl
1488 * 0x10, VsmpsAAutoMode
1489 * 0x20, VsmpsAPWMMode
1490 */
1491 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
1492 /*
1493 * 0x03, VsmpsBRegu
1494 * 0x0c, VsmpsBSelCtrl
1495 * 0x10, VsmpsBAutoMode
1496 * 0x20, VsmpsBPWMMode
1497 */
1498 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
1499 /*
1500 * 0x03, VsafeRegu
1501 * 0x0c, VsafeSelCtrl
1502 * 0x10, VsafeAutoMode
1503 * 0x20, VsafePWMMode
1504 */
1505 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
1506 /*
1507 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1508 * 0x0c, VanaRegu
1509 */
1510 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1511 /*
1512 * 0x03, VextSupply1Regu
1513 * 0x0c, VextSupply2Regu
1514 * 0x30, VextSupply3Regu
1515 * 0x40, ExtSupply2Bypass
1516 * 0x80, ExtSupply3Bypass
1517 */
1518 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1519 /*
1520 * 0x03, Vaux1Regu
1521 * 0x0c, Vaux2Regu
1522 */
1523 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
1524 /*
1525 * 0x0f, Vaux3Regu
1526 */
1527 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
1528 /*
1529 * 0x3f, VsmpsASel1
1530 */
1531 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
1532 /*
1533 * 0x3f, VsmpsASel2
1534 */
1535 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
1536 /*
1537 * 0x3f, VsmpsASel3
1538 */
1539 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
1540 /*
1541 * 0x3f, VsmpsBSel1
1542 */
1543 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
1544 /*
1545 * 0x3f, VsmpsBSel2
1546 */
1547 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
1548 /*
1549 * 0x3f, VsmpsBSel3
1550 */
1551 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
1552 /*
1553 * 0x7f, VsafeSel1
1554 */
1555 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
1556 /*
1557 * 0x3f, VsafeSel2
1558 */
1559 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
1560 /*
1561 * 0x3f, VsafeSel3
1562 */
1563 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
1564 /*
1565 * 0x0f, Vaux1Sel
1566 */
1567 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
1568 /*
1569 * 0x0f, Vaux2Sel
1570 */
1571 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
1572 /*
1573 * 0x07, Vaux3Sel
1574 * 0x30, VRF1Sel
1575 */
1576 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
1577 /*
1578 * 0x03, Vaux4RequestCtrl
1579 */
1580 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
1581 /*
1582 * 0x03, Vaux4Regu
1583 */
1584 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
1585 /*
1586 * 0x0f, Vaux4Sel
1587 */
1588 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
1589 /*
1590 * 0x04, Vaux1Disch
1591 * 0x08, Vaux2Disch
1592 * 0x10, Vaux3Disch
1593 * 0x20, Vintcore12Disch
1594 * 0x40, VTVoutDisch
1595 * 0x80, VaudioDisch
1596 */
1597 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
1598 /*
1599 * 0x02, VanaDisch
1600 * 0x04, VdmicPullDownEna
1601 * 0x10, VdmicDisch
1602 */
1603 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
1604 /*
1605 * 0x01, Vaux4Disch
1606 */
1607 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
1608 /*
1609 * 0x07, Vaux5Sel
1610 * 0x08, Vaux5LP
1611 * 0x10, Vaux5Ena
1612 * 0x20, Vaux5Disch
1613 * 0x40, Vaux5DisSfst
1614 * 0x80, Vaux5DisPulld
1615 */
1616 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
1617 /*
1618 * 0x07, Vaux6Sel
1619 * 0x08, Vaux6LP
1620 * 0x10, Vaux6Ena
1621 * 0x80, Vaux6DisPulld
1622 */
1623 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
1624};
1625
1034/* AB9540 register init */ 1626/* AB9540 register init */
1035static struct ab8500_reg_init ab9540_reg_init[] = { 1627static struct ab8500_reg_init ab9540_reg_init[] = {
1036 /* 1628 /*
@@ -1396,6 +1988,22 @@ static struct of_regulator_match ab8500_regulator_match[] = {
1396 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, }, 1988 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
1397}; 1989};
1398 1990
1991static struct of_regulator_match ab8505_regulator_match[] = {
1992 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
1993 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
1994 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
1995 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
1996 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
1997 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
1998 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
1999 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2000 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2001 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2002 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2003 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2004 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2005};
2006
1399static struct of_regulator_match ab9540_regulator_match[] = { 2007static struct of_regulator_match ab9540_regulator_match[] = {
1400 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, }, 2008 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
1401 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, }, 2009 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
@@ -1450,6 +2058,11 @@ static int ab8500_regulator_probe(struct platform_device *pdev)
1450 reg_init_size = AB9540_NUM_REGULATOR_REGISTERS; 2058 reg_init_size = AB9540_NUM_REGULATOR_REGISTERS;
1451 match = ab9540_regulator_match; 2059 match = ab9540_regulator_match;
1452 match_size = ARRAY_SIZE(ab9540_regulator_match) 2060 match_size = ARRAY_SIZE(ab9540_regulator_match)
2061 } else if (is_ab8505(ab8500)) {
2062 regulator_info = ab8505_regulator_info;
2063 regulator_info_size = ARRAY_SIZE(ab8505_regulator_info);
2064 reg_init = ab8505_reg_init;
2065 reg_init_size = AB8505_NUM_REGULATOR_REGISTERS;
1453 } else { 2066 } else {
1454 regulator_info = ab8500_regulator_info; 2067 regulator_info = ab8500_regulator_info;
1455 regulator_info_size = ARRAY_SIZE(ab8500_regulator_info); 2068 regulator_info_size = ARRAY_SIZE(ab8500_regulator_info);
@@ -1543,6 +2156,9 @@ static int ab8500_regulator_remove(struct platform_device *pdev)
1543 if (is_ab9540(ab8500)) { 2156 if (is_ab9540(ab8500)) {
1544 regulator_info = ab9540_regulator_info; 2157 regulator_info = ab9540_regulator_info;
1545 regulator_info_size = ARRAY_SIZE(ab9540_regulator_info); 2158 regulator_info_size = ARRAY_SIZE(ab9540_regulator_info);
2159 } else if (is_ab8505(ab8500)) {
2160 regulator_info = ab8505_regulator_info;
2161 regulator_info_size = ARRAY_SIZE(ab8505_regulator_info);
1546 } else { 2162 } else {
1547 regulator_info = ab8500_regulator_info; 2163 regulator_info = ab8500_regulator_info;
1548 regulator_info_size = ARRAY_SIZE(ab8500_regulator_info); 2164 regulator_info_size = ARRAY_SIZE(ab8500_regulator_info);
@@ -1601,5 +2217,6 @@ module_exit(ab8500_regulator_exit);
1601MODULE_LICENSE("GPL v2"); 2217MODULE_LICENSE("GPL v2");
1602MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>"); 2218MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
1603MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>"); 2219MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
2220MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
1604MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC"); 2221MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
1605MODULE_ALIAS("platform:ab8500-regulator"); 2222MODULE_ALIAS("platform:ab8500-regulator");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 14:54:22 -0500