diff options
author | Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | 2015-02-04 04:02:55 -0500 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2015-02-24 01:24:12 -0500 |
commit | ecd06305c9a077ab5aa000cb8027e2c1c872f25f (patch) | |
tree | fc2b90e6c940cbe2f20b61b260ffaa49ea39cd92 /drivers/pci | |
parent | 2ea2a2734cd850d8d270022e9aaabc02a931c172 (diff) |
PCI: rcar: Change PCIEPARL and PCIEPARH to PCIEPALR and PCIEPAUR
PCIEPARL and PCIEPARH are macros that calculate register addresses.
However, the register names are incorrect. Change them to PCIEPALR and
PCIEPAUR.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/host/pcie-rcar.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c index a910f795bfee..c086210f2ffd 100644 --- a/drivers/pci/host/pcie-rcar.c +++ b/drivers/pci/host/pcie-rcar.c | |||
@@ -64,8 +64,8 @@ | |||
64 | #define LAR_ENABLE (1 << 1) | 64 | #define LAR_ENABLE (1 << 1) |
65 | 65 | ||
66 | /* PCIe address reg & mask */ | 66 | /* PCIe address reg & mask */ |
67 | #define PCIEPARL(x) (0x03400 + ((x) * 0x20)) | 67 | #define PCIEPALR(x) (0x03400 + ((x) * 0x20)) |
68 | #define PCIEPARH(x) (0x03404 + ((x) * 0x20)) | 68 | #define PCIEPAUR(x) (0x03404 + ((x) * 0x20)) |
69 | #define PCIEPAMR(x) (0x03408 + ((x) * 0x20)) | 69 | #define PCIEPAMR(x) (0x03408 + ((x) * 0x20)) |
70 | #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20)) | 70 | #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20)) |
71 | #define PAR_ENABLE (1 << 31) | 71 | #define PAR_ENABLE (1 << 31) |
@@ -341,9 +341,9 @@ static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie) | |||
341 | else | 341 | else |
342 | res_start = res->start; | 342 | res_start = res->start; |
343 | 343 | ||
344 | rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPARH(win)); | 344 | rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win)); |
345 | rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F, | 345 | rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F, |
346 | PCIEPARL(win)); | 346 | PCIEPALR(win)); |
347 | 347 | ||
348 | /* First resource is for IO */ | 348 | /* First resource is for IO */ |
349 | mask = PAR_ENABLE; | 349 | mask = PAR_ENABLE; |