Merge branch 'irq/for-gpio' into irq/core

Merge the request/release callbacks which are in a separate branch for
consumption by the gpio folks.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

1 files changed, 2 insertions, 9 deletions

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 13478ecd4113..0e79665afd44 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -60,14 +60,6 @@
 #define PCIE_DEBUG_CTRL         0x1a60
 #define  PCIE_DEBUG_SOFT_RESET          BIT(20)
 
-/*
- * This product ID is registered by Marvell, and used when the Marvell
- * SoC is not the root complex, but an endpoint on the PCIe bus. It is
- * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
- * bridge.
- */
-#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
-
 /* PCI configuration space of a PCI-to-PCI bridge */
 struct mvebu_sw_pci_bridge {
         u16 vendor;
@@ -388,7 +380,8 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
 
         bridge->class = PCI_CLASS_BRIDGE_PCI;
         bridge->vendor = PCI_VENDOR_ID_MARVELL;
-        bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
+        bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
+        bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
         bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
         bridge->cache_line_size = 0x10;