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path: root/drivers/pci/host/pci-mvebu.c
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Diffstat (limited to 'drivers/pci/host/pci-mvebu.c')
-rw-r--r--drivers/pci/host/pci-mvebu.c11
1 files changed, 2 insertions, 9 deletions
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 13478ecd4113..0e79665afd44 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -60,14 +60,6 @@
60#define PCIE_DEBUG_CTRL 0x1a60 60#define PCIE_DEBUG_CTRL 0x1a60
61#define PCIE_DEBUG_SOFT_RESET BIT(20) 61#define PCIE_DEBUG_SOFT_RESET BIT(20)
62 62
63/*
64 * This product ID is registered by Marvell, and used when the Marvell
65 * SoC is not the root complex, but an endpoint on the PCIe bus. It is
66 * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
67 * bridge.
68 */
69#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
70
71/* PCI configuration space of a PCI-to-PCI bridge */ 63/* PCI configuration space of a PCI-to-PCI bridge */
72struct mvebu_sw_pci_bridge { 64struct mvebu_sw_pci_bridge {
73 u16 vendor; 65 u16 vendor;
@@ -388,7 +380,8 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
388 380
389 bridge->class = PCI_CLASS_BRIDGE_PCI; 381 bridge->class = PCI_CLASS_BRIDGE_PCI;
390 bridge->vendor = PCI_VENDOR_ID_MARVELL; 382 bridge->vendor = PCI_VENDOR_ID_MARVELL;
391 bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID; 383 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
384 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
392 bridge->header_type = PCI_HEADER_TYPE_BRIDGE; 385 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
393 bridge->cache_line_size = 0x10; 386 bridge->cache_line_size = 0x10;
394 387