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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/net/wireless/rtlwifi/rtl8192ce
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8192ce')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/Makefile13
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/def.h374
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/dm.c115
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/dm.h198
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/hw.c2307
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/hw.h78
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/led.c151
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/led.h38
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/phy.c635
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/phy.h262
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/reg.h2090
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/rf.c523
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/rf.h44
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/sw.c394
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/sw.h41
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/table.c1224
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/table.h58
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/trx.c1012
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/trx.h739
19 files changed, 10296 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/Makefile b/drivers/net/wireless/rtlwifi/rtl8192ce/Makefile
new file mode 100644
index 000000000000..c0cb0cfe7d37
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/Makefile
@@ -0,0 +1,13 @@
1rtl8192ce-objs := \
2 dm.o \
3 hw.o \
4 led.o \
5 phy.o \
6 rf.o \
7 sw.o \
8 table.o \
9 trx.o
10
11obj-$(CONFIG_RTL8192CE) += rtl8192ce.o
12
13ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/def.h b/drivers/net/wireless/rtlwifi/rtl8192ce/def.h
new file mode 100644
index 000000000000..35ff7df41a1d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/def.h
@@ -0,0 +1,374 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_DEF_H__
31#define __RTL92C_DEF_H__
32
33#define HAL_RETRY_LIMIT_INFRA 48
34#define HAL_RETRY_LIMIT_AP_ADHOC 7
35
36#define PHY_RSSI_SLID_WIN_MAX 100
37#define PHY_LINKQUALITY_SLID_WIN_MAX 20
38#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
39
40#define RESET_DELAY_8185 20
41
42#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
43#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
44
45#define NUM_OF_FIRMWARE_QUEUE 10
46#define NUM_OF_PAGES_IN_FW 0x100
47#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
48#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
49#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
50#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
51#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
52#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
53#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
54#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
55#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
56#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
57
58#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
59#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
60#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
61#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
62#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
63
64#define MAX_LINES_HWCONFIG_TXT 1000
65#define MAX_BYTES_LINE_HWCONFIG_TXT 256
66
67#define SW_THREE_WIRE 0
68#define HW_THREE_WIRE 2
69
70#define BT_DEMO_BOARD 0
71#define BT_QA_BOARD 1
72#define BT_FPGA 2
73
74#define RX_SMOOTH_FACTOR 20
75
76#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
77#define HAL_PRIME_CHNL_OFFSET_LOWER 1
78#define HAL_PRIME_CHNL_OFFSET_UPPER 2
79
80#define MAX_H2C_QUEUE_NUM 10
81
82#define RX_MPDU_QUEUE 0
83#define RX_CMD_QUEUE 1
84#define RX_MAX_QUEUE 2
85#define AC2QUEUEID(_AC) (_AC)
86
87#define C2H_RX_CMD_HDR_LEN 8
88#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
89 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
90#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
91 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
92#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
93 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
94#define GET_C2H_CMD_CONTINUE(__prxhdr) \
95 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
96#define GET_C2H_CMD_CONTENT(__prxhdr) \
97 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
98
99#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
100 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
101#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
102 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
103#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
104 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
105#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
106 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
107#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
108 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
109#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
110 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
111#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
112 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
113#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
114 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
115#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
116 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
117
118#define CHIP_VER_B BIT(4)
119#define CHIP_92C_BITMASK BIT(0)
120#define CHIP_92C_1T2R 0x03
121#define CHIP_92C 0x01
122#define CHIP_88C 0x00
123
124enum version_8192c {
125 VERSION_A_CHIP_92C = 0x01,
126 VERSION_A_CHIP_88C = 0x00,
127 VERSION_B_CHIP_92C = 0x11,
128 VERSION_B_CHIP_88C = 0x10,
129 VERSION_TEST_CHIP_88C = 0x00,
130 VERSION_TEST_CHIP_92C = 0x01,
131 VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
132 VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
133 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
134 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
135 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
136 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
137 VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
138 VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
139 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
140 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
141 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
142 VERSION_UNKNOWN = 0x88,
143};
144
145#define IS_CHIP_VER_B(version) ((version & CHIP_VER_B) ? true : false)
146#define IS_92C_SERIAL(version) ((version & CHIP_92C_BITMASK) ? true : false)
147
148enum rtl819x_loopback_e {
149 RTL819X_NO_LOOPBACK = 0,
150 RTL819X_MAC_LOOPBACK = 1,
151 RTL819X_DMA_LOOPBACK = 2,
152 RTL819X_CCK_LOOPBACK = 3,
153};
154
155enum rf_optype {
156 RF_OP_BY_SW_3WIRE = 0,
157 RF_OP_BY_FW,
158 RF_OP_MAX
159};
160
161enum rf_power_state {
162 RF_ON,
163 RF_OFF,
164 RF_SLEEP,
165 RF_SHUT_DOWN,
166};
167
168enum power_save_mode {
169 POWER_SAVE_MODE_ACTIVE,
170 POWER_SAVE_MODE_SAVE,
171};
172
173enum power_polocy_config {
174 POWERCFG_MAX_POWER_SAVINGS,
175 POWERCFG_GLOBAL_POWER_SAVINGS,
176 POWERCFG_LOCAL_POWER_SAVINGS,
177 POWERCFG_LENOVO,
178};
179
180enum interface_select_pci {
181 INTF_SEL1_MINICARD = 0,
182 INTF_SEL0_PCIE = 1,
183 INTF_SEL2_RSV = 2,
184 INTF_SEL3_RSV = 3,
185};
186
187enum hal_fw_c2h_cmd_id {
188 HAL_FW_C2H_CMD_Read_MACREG = 0,
189 HAL_FW_C2H_CMD_Read_BBREG = 1,
190 HAL_FW_C2H_CMD_Read_RFREG = 2,
191 HAL_FW_C2H_CMD_Read_EEPROM = 3,
192 HAL_FW_C2H_CMD_Read_EFUSE = 4,
193 HAL_FW_C2H_CMD_Read_CAM = 5,
194 HAL_FW_C2H_CMD_Get_BasicRate = 6,
195 HAL_FW_C2H_CMD_Get_DataRate = 7,
196 HAL_FW_C2H_CMD_Survey = 8,
197 HAL_FW_C2H_CMD_SurveyDone = 9,
198 HAL_FW_C2H_CMD_JoinBss = 10,
199 HAL_FW_C2H_CMD_AddSTA = 11,
200 HAL_FW_C2H_CMD_DelSTA = 12,
201 HAL_FW_C2H_CMD_AtimDone = 13,
202 HAL_FW_C2H_CMD_TX_Report = 14,
203 HAL_FW_C2H_CMD_CCX_Report = 15,
204 HAL_FW_C2H_CMD_DTM_Report = 16,
205 HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
206 HAL_FW_C2H_CMD_C2HLBK = 18,
207 HAL_FW_C2H_CMD_C2HDBG = 19,
208 HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
209 HAL_FW_C2H_CMD_MAX
210};
211
212enum rtl_desc_qsel {
213 QSLT_BK = 0x2,
214 QSLT_BE = 0x0,
215 QSLT_VI = 0x5,
216 QSLT_VO = 0x7,
217 QSLT_BEACON = 0x10,
218 QSLT_HIGH = 0x11,
219 QSLT_MGNT = 0x12,
220 QSLT_CMD = 0x13,
221};
222
223enum rtl_desc92c_rate {
224 DESC92C_RATE1M = 0x00,
225 DESC92C_RATE2M = 0x01,
226 DESC92C_RATE5_5M = 0x02,
227 DESC92C_RATE11M = 0x03,
228
229 DESC92C_RATE6M = 0x04,
230 DESC92C_RATE9M = 0x05,
231 DESC92C_RATE12M = 0x06,
232 DESC92C_RATE18M = 0x07,
233 DESC92C_RATE24M = 0x08,
234 DESC92C_RATE36M = 0x09,
235 DESC92C_RATE48M = 0x0a,
236 DESC92C_RATE54M = 0x0b,
237
238 DESC92C_RATEMCS0 = 0x0c,
239 DESC92C_RATEMCS1 = 0x0d,
240 DESC92C_RATEMCS2 = 0x0e,
241 DESC92C_RATEMCS3 = 0x0f,
242 DESC92C_RATEMCS4 = 0x10,
243 DESC92C_RATEMCS5 = 0x11,
244 DESC92C_RATEMCS6 = 0x12,
245 DESC92C_RATEMCS7 = 0x13,
246 DESC92C_RATEMCS8 = 0x14,
247 DESC92C_RATEMCS9 = 0x15,
248 DESC92C_RATEMCS10 = 0x16,
249 DESC92C_RATEMCS11 = 0x17,
250 DESC92C_RATEMCS12 = 0x18,
251 DESC92C_RATEMCS13 = 0x19,
252 DESC92C_RATEMCS14 = 0x1a,
253 DESC92C_RATEMCS15 = 0x1b,
254 DESC92C_RATEMCS15_SG = 0x1c,
255 DESC92C_RATEMCS32 = 0x20,
256};
257
258struct phy_sts_cck_8192s_t {
259 u8 adc_pwdb_X[4];
260 u8 sq_rpt;
261 u8 cck_agc_rpt;
262};
263
264struct h2c_cmd_8192c {
265 u8 element_id;
266 u32 cmd_len;
267 u8 *p_cmdbuffer;
268};
269
270/* NOTE: reference to rtl8192c_rates struct */
271static inline int _rtl92c_rate_mapping(struct ieee80211_hw *hw, bool isHT,
272 u8 desc_rate, bool first_ampdu)
273{
274 struct rtl_priv *rtlpriv = rtl_priv(hw);
275 int rate_idx = 0;
276
277 if (first_ampdu) {
278 if (false == isHT) {
279 switch (desc_rate) {
280 case DESC92C_RATE1M:
281 rate_idx = 0;
282 break;
283 case DESC92C_RATE2M:
284 rate_idx = 1;
285 break;
286 case DESC92C_RATE5_5M:
287 rate_idx = 2;
288 break;
289 case DESC92C_RATE11M:
290 rate_idx = 3;
291 break;
292 case DESC92C_RATE6M:
293 rate_idx = 4;
294 break;
295 case DESC92C_RATE9M:
296 rate_idx = 5;
297 break;
298 case DESC92C_RATE12M:
299 rate_idx = 6;
300 break;
301 case DESC92C_RATE18M:
302 rate_idx = 7;
303 break;
304 case DESC92C_RATE24M:
305 rate_idx = 8;
306 break;
307 case DESC92C_RATE36M:
308 rate_idx = 9;
309 break;
310 case DESC92C_RATE48M:
311 rate_idx = 10;
312 break;
313 case DESC92C_RATE54M:
314 rate_idx = 11;
315 break;
316 default:
317 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
318 ("Rate %d is not support, set to "
319 "1M rate.\n", desc_rate));
320 rate_idx = 0;
321 break;
322 }
323 } else {
324 rate_idx = 11;
325 }
326 return rate_idx;
327 }
328 switch (desc_rate) {
329 case DESC92C_RATE1M:
330 rate_idx = 0;
331 break;
332 case DESC92C_RATE2M:
333 rate_idx = 1;
334 break;
335 case DESC92C_RATE5_5M:
336 rate_idx = 2;
337 break;
338 case DESC92C_RATE11M:
339 rate_idx = 3;
340 break;
341 case DESC92C_RATE6M:
342 rate_idx = 4;
343 break;
344 case DESC92C_RATE9M:
345 rate_idx = 5;
346 break;
347 case DESC92C_RATE12M:
348 rate_idx = 6;
349 break;
350 case DESC92C_RATE18M:
351 rate_idx = 7;
352 break;
353 case DESC92C_RATE24M:
354 rate_idx = 8;
355 break;
356 case DESC92C_RATE36M:
357 rate_idx = 9;
358 break;
359 case DESC92C_RATE48M:
360 rate_idx = 10;
361 break;
362 case DESC92C_RATE54M:
363 rate_idx = 11;
364 break;
365 /* TODO: How to mapping MCS rate? */
366 /* NOTE: referenc to __ieee80211_rx */
367 default:
368 rate_idx = 11;
369 break;
370 }
371 return rate_idx;
372}
373
374#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/dm.c b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.c
new file mode 100644
index 000000000000..2df33e53e15a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.c
@@ -0,0 +1,115 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../base.h"
32#include "../pci.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "dm.h"
37#include "../rtl8192c/fw_common.h"
38
39void rtl92ce_dm_dynamic_txpower(struct ieee80211_hw *hw)
40{
41 struct rtl_priv *rtlpriv = rtl_priv(hw);
42 struct rtl_phy *rtlphy = &(rtlpriv->phy);
43 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
44 long undecorated_smoothed_pwdb;
45
46 if (!rtlpriv->dm.dynamic_txpower_enable)
47 return;
48
49 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
50 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
51 return;
52 }
53
54 if ((mac->link_state < MAC80211_LINKED) &&
55 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
56 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
57 ("Not connected to any\n"));
58
59 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
60
61 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
62 return;
63 }
64
65 if (mac->link_state >= MAC80211_LINKED) {
66 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
67 undecorated_smoothed_pwdb =
68 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
69 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
70 ("AP Client PWDB = 0x%lx\n",
71 undecorated_smoothed_pwdb));
72 } else {
73 undecorated_smoothed_pwdb =
74 rtlpriv->dm.undecorated_smoothed_pwdb;
75 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
76 ("STA Default Port PWDB = 0x%lx\n",
77 undecorated_smoothed_pwdb));
78 }
79 } else {
80 undecorated_smoothed_pwdb =
81 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
82
83 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
84 ("AP Ext Port PWDB = 0x%lx\n",
85 undecorated_smoothed_pwdb));
86 }
87
88 if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
89 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
90 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
91 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"));
92 } else if ((undecorated_smoothed_pwdb <
93 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
94 (undecorated_smoothed_pwdb >=
95 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
96
97 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
98 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
99 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"));
100 } else if (undecorated_smoothed_pwdb <
101 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
102 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
103 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
104 ("TXHIGHPWRLEVEL_NORMAL\n"));
105 }
106
107 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
108 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
109 ("PHY_SetTxPowerLevel8192S() Channel = %d\n",
110 rtlphy->current_channel));
111 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
112 }
113
114 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
115}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/dm.h b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.h
new file mode 100644
index 000000000000..07dd9552e82f
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.h
@@ -0,0 +1,198 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_DM_H__
31#define __RTL92C_DM_H__
32
33#define HAL_DM_DIG_DISABLE BIT(0)
34#define HAL_DM_HIPWR_DISABLE BIT(1)
35
36#define OFDM_TABLE_LENGTH 37
37#define CCK_TABLE_LENGTH 33
38
39#define OFDM_TABLE_SIZE 37
40#define CCK_TABLE_SIZE 33
41
42#define BW_AUTO_SWITCH_HIGH_LOW 25
43#define BW_AUTO_SWITCH_LOW_HIGH 30
44
45#define DM_DIG_THRESH_HIGH 40
46#define DM_DIG_THRESH_LOW 35
47
48#define DM_FALSEALARM_THRESH_LOW 400
49#define DM_FALSEALARM_THRESH_HIGH 1000
50
51#define DM_DIG_MAX 0x3e
52#define DM_DIG_MIN 0x1e
53
54#define DM_DIG_FA_UPPER 0x32
55#define DM_DIG_FA_LOWER 0x20
56#define DM_DIG_FA_TH0 0x20
57#define DM_DIG_FA_TH1 0x100
58#define DM_DIG_FA_TH2 0x200
59
60#define DM_DIG_BACKOFF_MAX 12
61#define DM_DIG_BACKOFF_MIN -4
62#define DM_DIG_BACKOFF_DEFAULT 10
63
64#define RXPATHSELECTION_SS_TH_lOW 30
65#define RXPATHSELECTION_DIFF_TH 18
66
67#define DM_RATR_STA_INIT 0
68#define DM_RATR_STA_HIGH 1
69#define DM_RATR_STA_MIDDLE 2
70#define DM_RATR_STA_LOW 3
71
72#define CTS2SELF_THVAL 30
73#define REGC38_TH 20
74
75#define WAIOTTHVal 25
76
77#define TXHIGHPWRLEVEL_NORMAL 0
78#define TXHIGHPWRLEVEL_LEVEL1 1
79#define TXHIGHPWRLEVEL_LEVEL2 2
80#define TXHIGHPWRLEVEL_BT1 3
81#define TXHIGHPWRLEVEL_BT2 4
82
83#define DM_TYPE_BYFW 0
84#define DM_TYPE_BYDRIVER 1
85
86#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
87#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
88
89struct ps_t {
90 u8 pre_ccastate;
91 u8 cur_ccasate;
92 u8 pre_rfstate;
93 u8 cur_rfstate;
94 long rssi_val_min;
95};
96
97struct dig_t {
98 u8 dig_enable_flag;
99 u8 dig_ext_port_stage;
100 u32 rssi_lowthresh;
101 u32 rssi_highthresh;
102 u32 fa_lowthresh;
103 u32 fa_highthresh;
104 u8 cursta_connectctate;
105 u8 presta_connectstate;
106 u8 curmultista_connectstate;
107 u8 pre_igvalue;
108 u8 cur_igvalue;
109 char backoff_val;
110 char backoff_val_range_max;
111 char backoff_val_range_min;
112 u8 rx_gain_range_max;
113 u8 rx_gain_range_min;
114 u8 rssi_val_min;
115 u8 pre_cck_pd_state;
116 u8 cur_cck_pd_state;
117 u8 pre_cck_fa_state;
118 u8 cur_cck_fa_state;
119 u8 pre_ccastate;
120 u8 cur_ccasate;
121};
122
123struct swat_t {
124 u8 failure_cnt;
125 u8 try_flag;
126 u8 stop_trying;
127 long pre_rssi;
128 long trying_threshold;
129 u8 cur_antenna;
130 u8 pre_antenna;
131};
132
133enum tag_dynamic_init_gain_operation_type_definition {
134 DIG_TYPE_THRESH_HIGH = 0,
135 DIG_TYPE_THRESH_LOW = 1,
136 DIG_TYPE_BACKOFF = 2,
137 DIG_TYPE_RX_GAIN_MIN = 3,
138 DIG_TYPE_RX_GAIN_MAX = 4,
139 DIG_TYPE_ENABLE = 5,
140 DIG_TYPE_DISABLE = 6,
141 DIG_OP_TYPE_MAX
142};
143
144enum tag_cck_packet_detection_threshold_type_definition {
145 CCK_PD_STAGE_LowRssi = 0,
146 CCK_PD_STAGE_HighRssi = 1,
147 CCK_FA_STAGE_Low = 2,
148 CCK_FA_STAGE_High = 3,
149 CCK_PD_STAGE_MAX = 4,
150};
151
152enum dm_1r_cca_e {
153 CCA_1R = 0,
154 CCA_2R = 1,
155 CCA_MAX = 2,
156};
157
158enum dm_rf_e {
159 RF_SAVE = 0,
160 RF_NORMAL = 1,
161 RF_MAX = 2,
162};
163
164enum dm_sw_ant_switch_e {
165 ANS_ANTENNA_B = 1,
166 ANS_ANTENNA_A = 2,
167 ANS_ANTENNA_MAX = 3,
168};
169
170enum dm_dig_ext_port_alg_e {
171 DIG_EXT_PORT_STAGE_0 = 0,
172 DIG_EXT_PORT_STAGE_1 = 1,
173 DIG_EXT_PORT_STAGE_2 = 2,
174 DIG_EXT_PORT_STAGE_3 = 3,
175 DIG_EXT_PORT_STAGE_MAX = 4,
176};
177
178enum dm_dig_connect_e {
179 DIG_STA_DISCONNECT = 0,
180 DIG_STA_CONNECT = 1,
181 DIG_STA_BEFORE_CONNECT = 2,
182 DIG_MULTISTA_DISCONNECT = 3,
183 DIG_MULTISTA_CONNECT = 4,
184 DIG_CONNECT_MAX
185};
186
187extern struct dig_t dm_digtable;
188void rtl92c_dm_init(struct ieee80211_hw *hw);
189void rtl92c_dm_watchdog(struct ieee80211_hw *hw);
190void rtl92c_dm_write_dig(struct ieee80211_hw *hw);
191void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw);
192void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw);
193void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
194void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
195void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw);
196void rtl92ce_dm_dynamic_txpower(struct ieee80211_hw *hw);
197
198#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
new file mode 100644
index 000000000000..defb4370cf74
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
@@ -0,0 +1,2307 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../regd.h"
34#include "../cam.h"
35#include "../ps.h"
36#include "../pci.h"
37#include "reg.h"
38#include "def.h"
39#include "phy.h"
40#include "../rtl8192c/fw_common.h"
41#include "dm.h"
42#include "led.h"
43#include "hw.h"
44
45#define LLT_CONFIG 5
46
47static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
48 u8 set_bits, u8 clear_bits)
49{
50 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
51 struct rtl_priv *rtlpriv = rtl_priv(hw);
52
53 rtlpci->reg_bcn_ctrl_val |= set_bits;
54 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
55
56 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
57}
58
59static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
60{
61 struct rtl_priv *rtlpriv = rtl_priv(hw);
62 u8 tmp1byte;
63
64 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
65 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
66 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
67 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
68 tmp1byte &= ~(BIT(0));
69 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
70}
71
72static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
73{
74 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 u8 tmp1byte;
76
77 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
78 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
79 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
80 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
81 tmp1byte |= BIT(0);
82 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
83}
84
85static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
86{
87 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
88}
89
90static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
91{
92 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
93}
94
95void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
96{
97 struct rtl_priv *rtlpriv = rtl_priv(hw);
98 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
99 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
100
101 switch (variable) {
102 case HW_VAR_RCR:
103 *((u32 *) (val)) = rtlpci->receive_config;
104 break;
105 case HW_VAR_RF_STATE:
106 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
107 break;
108 case HW_VAR_FWLPS_RF_ON:{
109 enum rf_pwrstate rfState;
110 u32 val_rcr;
111
112 rtlpriv->cfg->ops->get_hw_reg(hw,
113 HW_VAR_RF_STATE,
114 (u8 *) (&rfState));
115 if (rfState == ERFOFF) {
116 *((bool *) (val)) = true;
117 } else {
118 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
119 val_rcr &= 0x00070000;
120 if (val_rcr)
121 *((bool *) (val)) = false;
122 else
123 *((bool *) (val)) = true;
124 }
125 break;
126 }
127 case HW_VAR_FW_PSMODE_STATUS:
128 *((bool *) (val)) = ppsc->fw_current_inpsmode;
129 break;
130 case HW_VAR_CORRECT_TSF:{
131 u64 tsf;
132 u32 *ptsf_low = (u32 *)&tsf;
133 u32 *ptsf_high = ((u32 *)&tsf) + 1;
134
135 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
136 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
137
138 *((u64 *) (val)) = tsf;
139
140 break;
141 }
142 default:
143 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
144 ("switch case not process\n"));
145 break;
146 }
147}
148
149void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
150{
151 struct rtl_priv *rtlpriv = rtl_priv(hw);
152 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
153 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
154 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
155 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
156 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
157 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
158 u8 idx;
159
160 switch (variable) {
161 case HW_VAR_ETHER_ADDR:{
162 for (idx = 0; idx < ETH_ALEN; idx++) {
163 rtl_write_byte(rtlpriv, (REG_MACID + idx),
164 val[idx]);
165 }
166 break;
167 }
168 case HW_VAR_BASIC_RATE:{
169 u16 rate_cfg = ((u16 *) val)[0];
170 u8 rate_index = 0;
171 rate_cfg &= 0x15f;
172 rate_cfg |= 0x01;
173 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
174 rtl_write_byte(rtlpriv, REG_RRSR + 1,
175 (rate_cfg >> 8) & 0xff);
176 while (rate_cfg > 0x1) {
177 rate_cfg = (rate_cfg >> 1);
178 rate_index++;
179 }
180 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
181 rate_index);
182 break;
183 }
184 case HW_VAR_BSSID:{
185 for (idx = 0; idx < ETH_ALEN; idx++) {
186 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
187 val[idx]);
188 }
189 break;
190 }
191 case HW_VAR_SIFS:{
192 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
193 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
194
195 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
196 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
197
198 if (!mac->ht_enable)
199 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
200 0x0e0e);
201 else
202 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
203 *((u16 *) val));
204 break;
205 }
206 case HW_VAR_SLOT_TIME:{
207 u8 e_aci;
208
209 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
210 ("HW_VAR_SLOT_TIME %x\n", val[0]));
211
212 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
213
214 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
215 rtlpriv->cfg->ops->set_hw_reg(hw,
216 HW_VAR_AC_PARAM,
217 (u8 *) (&e_aci));
218 }
219 break;
220 }
221 case HW_VAR_ACK_PREAMBLE:{
222 u8 reg_tmp;
223 u8 short_preamble = (bool) (*(u8 *) val);
224 reg_tmp = (mac->cur_40_prime_sc) << 5;
225 if (short_preamble)
226 reg_tmp |= 0x80;
227
228 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
229 break;
230 }
231 case HW_VAR_AMPDU_MIN_SPACE:{
232 u8 min_spacing_to_set;
233 u8 sec_min_space;
234
235 min_spacing_to_set = *((u8 *) val);
236 if (min_spacing_to_set <= 7) {
237 sec_min_space = 0;
238
239 if (min_spacing_to_set < sec_min_space)
240 min_spacing_to_set = sec_min_space;
241
242 mac->min_space_cfg = ((mac->min_space_cfg &
243 0xf8) |
244 min_spacing_to_set);
245
246 *val = min_spacing_to_set;
247
248 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
249 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
250 mac->min_space_cfg));
251
252 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
253 mac->min_space_cfg);
254 }
255 break;
256 }
257 case HW_VAR_SHORTGI_DENSITY:{
258 u8 density_to_set;
259
260 density_to_set = *((u8 *) val);
261 mac->min_space_cfg |= (density_to_set << 3);
262
263 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
264 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
265 mac->min_space_cfg));
266
267 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
268 mac->min_space_cfg);
269
270 break;
271 }
272 case HW_VAR_AMPDU_FACTOR:{
273 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
274 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
275
276 u8 factor_toset;
277 u8 *p_regtoset = NULL;
278 u8 index = 0;
279
280 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
281 (rtlpcipriv->bt_coexist.bt_coexist_type ==
282 BT_CSR_BC4))
283 p_regtoset = regtoset_bt;
284 else
285 p_regtoset = regtoset_normal;
286
287 factor_toset = *((u8 *) val);
288 if (factor_toset <= 3) {
289 factor_toset = (1 << (factor_toset + 2));
290 if (factor_toset > 0xf)
291 factor_toset = 0xf;
292
293 for (index = 0; index < 4; index++) {
294 if ((p_regtoset[index] & 0xf0) >
295 (factor_toset << 4))
296 p_regtoset[index] =
297 (p_regtoset[index] & 0x0f) |
298 (factor_toset << 4);
299
300 if ((p_regtoset[index] & 0x0f) >
301 factor_toset)
302 p_regtoset[index] =
303 (p_regtoset[index] & 0xf0) |
304 (factor_toset);
305
306 rtl_write_byte(rtlpriv,
307 (REG_AGGLEN_LMT + index),
308 p_regtoset[index]);
309
310 }
311
312 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
313 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
314 factor_toset));
315 }
316 break;
317 }
318 case HW_VAR_AC_PARAM:{
319 u8 e_aci = *((u8 *) val);
320 rtl92c_dm_init_edca_turbo(hw);
321
322 if (rtlpci->acm_method != eAcmWay2_SW)
323 rtlpriv->cfg->ops->set_hw_reg(hw,
324 HW_VAR_ACM_CTRL,
325 (u8 *) (&e_aci));
326 break;
327 }
328 case HW_VAR_ACM_CTRL:{
329 u8 e_aci = *((u8 *) val);
330 union aci_aifsn *p_aci_aifsn =
331 (union aci_aifsn *)(&(mac->ac[0].aifs));
332 u8 acm = p_aci_aifsn->f.acm;
333 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
334
335 acm_ctrl =
336 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
337
338 if (acm) {
339 switch (e_aci) {
340 case AC0_BE:
341 acm_ctrl |= AcmHw_BeqEn;
342 break;
343 case AC2_VI:
344 acm_ctrl |= AcmHw_ViqEn;
345 break;
346 case AC3_VO:
347 acm_ctrl |= AcmHw_VoqEn;
348 break;
349 default:
350 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
351 ("HW_VAR_ACM_CTRL acm set "
352 "failed: eACI is %d\n", acm));
353 break;
354 }
355 } else {
356 switch (e_aci) {
357 case AC0_BE:
358 acm_ctrl &= (~AcmHw_BeqEn);
359 break;
360 case AC2_VI:
361 acm_ctrl &= (~AcmHw_ViqEn);
362 break;
363 case AC3_VO:
364 acm_ctrl &= (~AcmHw_BeqEn);
365 break;
366 default:
367 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
368 ("switch case not process\n"));
369 break;
370 }
371 }
372
373 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
374 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
375 "Write 0x%X\n", acm_ctrl));
376 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
377 break;
378 }
379 case HW_VAR_RCR:{
380 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
381 rtlpci->receive_config = ((u32 *) (val))[0];
382 break;
383 }
384 case HW_VAR_RETRY_LIMIT:{
385 u8 retry_limit = ((u8 *) (val))[0];
386
387 rtl_write_word(rtlpriv, REG_RL,
388 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
389 retry_limit << RETRY_LIMIT_LONG_SHIFT);
390 break;
391 }
392 case HW_VAR_DUAL_TSF_RST:
393 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
394 break;
395 case HW_VAR_EFUSE_BYTES:
396 rtlefuse->efuse_usedbytes = *((u16 *) val);
397 break;
398 case HW_VAR_EFUSE_USAGE:
399 rtlefuse->efuse_usedpercentage = *((u8 *) val);
400 break;
401 case HW_VAR_IO_CMD:
402 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
403 break;
404 case HW_VAR_WPA_CONFIG:
405 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
406 break;
407 case HW_VAR_SET_RPWM:{
408 u8 rpwm_val;
409
410 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
411 udelay(1);
412
413 if (rpwm_val & BIT(7)) {
414 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
415 (*(u8 *) val));
416 } else {
417 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
418 ((*(u8 *) val) | BIT(7)));
419 }
420
421 break;
422 }
423 case HW_VAR_H2C_FW_PWRMODE:{
424 u8 psmode = (*(u8 *) val);
425
426 if ((psmode != FW_PS_ACTIVE_MODE) &&
427 (!IS_92C_SERIAL(rtlhal->version))) {
428 rtl92c_dm_rf_saving(hw, true);
429 }
430
431 rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
432 break;
433 }
434 case HW_VAR_FW_PSMODE_STATUS:
435 ppsc->fw_current_inpsmode = *((bool *) val);
436 break;
437 case HW_VAR_H2C_FW_JOINBSSRPT:{
438 u8 mstatus = (*(u8 *) val);
439 u8 tmp_regcr, tmp_reg422;
440 bool recover = false;
441
442 if (mstatus == RT_MEDIA_CONNECT) {
443 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
444 NULL);
445
446 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
447 rtl_write_byte(rtlpriv, REG_CR + 1,
448 (tmp_regcr | BIT(0)));
449
450 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
451 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
452
453 tmp_reg422 =
454 rtl_read_byte(rtlpriv,
455 REG_FWHW_TXQ_CTRL + 2);
456 if (tmp_reg422 & BIT(6))
457 recover = true;
458 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
459 tmp_reg422 & (~BIT(6)));
460
461 rtl92c_set_fw_rsvdpagepkt(hw, 0);
462
463 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
464 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
465
466 if (recover) {
467 rtl_write_byte(rtlpriv,
468 REG_FWHW_TXQ_CTRL + 2,
469 tmp_reg422);
470 }
471
472 rtl_write_byte(rtlpriv, REG_CR + 1,
473 (tmp_regcr & ~(BIT(0))));
474 }
475 rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
476
477 break;
478 }
479 case HW_VAR_AID:{
480 u16 u2btmp;
481 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
482 u2btmp &= 0xC000;
483 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
484 mac->assoc_id));
485
486 break;
487 }
488 case HW_VAR_CORRECT_TSF:{
489 u8 btype_ibss = ((u8 *) (val))[0];
490
491 if (btype_ibss == true)
492 _rtl92ce_stop_tx_beacon(hw);
493
494 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
495
496 rtl_write_dword(rtlpriv, REG_TSFTR,
497 (u32) (mac->tsf & 0xffffffff));
498 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
499 (u32) ((mac->tsf >> 32) & 0xffffffff));
500
501 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
502
503 if (btype_ibss == true)
504 _rtl92ce_resume_tx_beacon(hw);
505
506 break;
507
508 }
509 default:
510 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
511 "not process\n"));
512 break;
513 }
514}
515
516static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
517{
518 struct rtl_priv *rtlpriv = rtl_priv(hw);
519 bool status = true;
520 long count = 0;
521 u32 value = _LLT_INIT_ADDR(address) |
522 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
523
524 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
525
526 do {
527 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
528 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
529 break;
530
531 if (count > POLLING_LLT_THRESHOLD) {
532 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
533 ("Failed to polling write LLT done at "
534 "address %d!\n", address));
535 status = false;
536 break;
537 }
538 } while (++count);
539
540 return status;
541}
542
543static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
544{
545 struct rtl_priv *rtlpriv = rtl_priv(hw);
546 unsigned short i;
547 u8 txpktbuf_bndy;
548 u8 maxPage;
549 bool status;
550
551#if LLT_CONFIG == 1
552 maxPage = 255;
553 txpktbuf_bndy = 252;
554#elif LLT_CONFIG == 2
555 maxPage = 127;
556 txpktbuf_bndy = 124;
557#elif LLT_CONFIG == 3
558 maxPage = 255;
559 txpktbuf_bndy = 174;
560#elif LLT_CONFIG == 4
561 maxPage = 255;
562 txpktbuf_bndy = 246;
563#elif LLT_CONFIG == 5
564 maxPage = 255;
565 txpktbuf_bndy = 246;
566#endif
567
568#if LLT_CONFIG == 1
569 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
570 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
571#elif LLT_CONFIG == 2
572 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
573#elif LLT_CONFIG == 3
574 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
575#elif LLT_CONFIG == 4
576 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
577#elif LLT_CONFIG == 5
578 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
579
580 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
581#endif
582
583 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
584 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
585
586 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
587 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
588
589 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
590 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
591 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
592
593 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
594 status = _rtl92ce_llt_write(hw, i, i + 1);
595 if (true != status)
596 return status;
597 }
598
599 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
600 if (true != status)
601 return status;
602
603 for (i = txpktbuf_bndy; i < maxPage; i++) {
604 status = _rtl92ce_llt_write(hw, i, (i + 1));
605 if (true != status)
606 return status;
607 }
608
609 status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
610 if (true != status)
611 return status;
612
613 return true;
614}
615
616static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
617{
618 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
619 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
620 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
621 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
622
623 if (rtlpci->up_first_time)
624 return;
625
626 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
627 rtl92ce_sw_led_on(hw, pLed0);
628 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
629 rtl92ce_sw_led_on(hw, pLed0);
630 else
631 rtl92ce_sw_led_off(hw, pLed0);
632}
633
634static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
635{
636 struct rtl_priv *rtlpriv = rtl_priv(hw);
637 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
638 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
639 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
640
641 unsigned char bytetmp;
642 unsigned short wordtmp;
643 u16 retry;
644
645 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
646 if (rtlpcipriv->bt_coexist.bt_coexistence) {
647 u32 value32;
648 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
649 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
650 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
651 }
652 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
653 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
654
655 if (rtlpcipriv->bt_coexist.bt_coexistence) {
656 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
657
658 u4b_tmp &= (~0x00024800);
659 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
660 }
661
662 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
663 udelay(2);
664
665 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
666 udelay(2);
667
668 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
669 udelay(2);
670
671 retry = 0;
672 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
673 rtl_read_dword(rtlpriv, 0xEC),
674 bytetmp));
675
676 while ((bytetmp & BIT(0)) && retry < 1000) {
677 retry++;
678 udelay(50);
679 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
680 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
681 rtl_read_dword(rtlpriv,
682 0xEC),
683 bytetmp));
684 udelay(50);
685 }
686
687 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
688
689 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
690 udelay(2);
691
692 if (rtlpcipriv->bt_coexist.bt_coexistence) {
693 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
694 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
695 }
696
697 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
698
699 if (_rtl92ce_llt_table_init(hw) == false)
700 return false;
701
702 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
703 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
704
705 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
706
707 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
708 wordtmp &= 0xf;
709 wordtmp |= 0xF771;
710 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
711
712 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
713 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
714 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
715
716 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
717
718 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
719 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
720 DMA_BIT_MASK(32));
721 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
722 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
723 DMA_BIT_MASK(32));
724 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
725 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
726 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
727 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
728 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
729 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
730 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
731 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
732 rtl_write_dword(rtlpriv, REG_HQ_DESA,
733 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
734 DMA_BIT_MASK(32));
735 rtl_write_dword(rtlpriv, REG_RX_DESA,
736 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
737 DMA_BIT_MASK(32));
738
739 if (IS_92C_SERIAL(rtlhal->version))
740 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
741 else
742 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
743
744 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
745
746 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
747 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
748 do {
749 retry++;
750 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
751 } while ((retry < 200) && (bytetmp & BIT(7)));
752
753 _rtl92ce_gen_refresh_led_state(hw);
754
755 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
756
757 return true;
758}
759
760static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
761{
762 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
763 struct rtl_priv *rtlpriv = rtl_priv(hw);
764 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
765 u8 reg_bw_opmode;
766 u32 reg_ratr, reg_prsr;
767
768 reg_bw_opmode = BW_OPMODE_20MHZ;
769 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
770 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
771 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
772
773 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
774
775 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
776
777 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
778
779 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
780
781 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
782
783 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
784
785 rtl_write_word(rtlpriv, REG_RL, 0x0707);
786
787 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
788
789 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
790
791 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
792 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
793 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
794 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
795
796 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
797 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
798 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
799 else
800 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
801
802 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
803
804 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
805
806 rtlpci->reg_bcn_ctrl_val = 0x1f;
807 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
808
809 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
810
811 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
812
813 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
814 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
815
816 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
817 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
818 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
819 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
820 } else {
821 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
822 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
823 }
824
825 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
826 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
827 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
828 else
829 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
830
831 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
832
833 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
834 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
835
836 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
837
838 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
839
840 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
841 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
842
843}
844
845static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
846{
847 struct rtl_priv *rtlpriv = rtl_priv(hw);
848 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
849
850 rtl_write_byte(rtlpriv, 0x34b, 0x93);
851 rtl_write_word(rtlpriv, 0x350, 0x870c);
852 rtl_write_byte(rtlpriv, 0x352, 0x1);
853
854 if (ppsc->support_backdoor)
855 rtl_write_byte(rtlpriv, 0x349, 0x1b);
856 else
857 rtl_write_byte(rtlpriv, 0x349, 0x03);
858
859 rtl_write_word(rtlpriv, 0x350, 0x2718);
860 rtl_write_byte(rtlpriv, 0x352, 0x1);
861}
862
863void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
864{
865 struct rtl_priv *rtlpriv = rtl_priv(hw);
866 u8 sec_reg_value;
867
868 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
869 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
870 rtlpriv->sec.pairwise_enc_algorithm,
871 rtlpriv->sec.group_enc_algorithm));
872
873 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
874 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("not open "
875 "hw encryption\n"));
876 return;
877 }
878
879 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
880
881 if (rtlpriv->sec.use_defaultkey) {
882 sec_reg_value |= SCR_TxUseDK;
883 sec_reg_value |= SCR_RxUseDK;
884 }
885
886 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
887
888 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
889
890 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
891 ("The SECR-value %x\n", sec_reg_value));
892
893 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
894
895}
896
897int rtl92ce_hw_init(struct ieee80211_hw *hw)
898{
899 struct rtl_priv *rtlpriv = rtl_priv(hw);
900 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
901 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
902 struct rtl_phy *rtlphy = &(rtlpriv->phy);
903 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
904 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
905 static bool iqk_initialized; /* initialized to false */
906 bool rtstatus = true;
907 bool is92c;
908 int err;
909 u8 tmp_u1b;
910
911 rtlpci->being_init_adapter = true;
912 rtlpriv->intf_ops->disable_aspm(hw);
913 rtstatus = _rtl92ce_init_mac(hw);
914 if (rtstatus != true) {
915 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
916 err = 1;
917 return err;
918 }
919
920 err = rtl92c_download_fw(hw);
921 if (err) {
922 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
923 ("Failed to download FW. Init HW "
924 "without FW now..\n"));
925 err = 1;
926 rtlhal->fw_ready = false;
927 return err;
928 } else {
929 rtlhal->fw_ready = true;
930 }
931
932 rtlhal->last_hmeboxnum = 0;
933 rtl92c_phy_mac_config(hw);
934 rtl92c_phy_bb_config(hw);
935 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
936 rtl92c_phy_rf_config(hw);
937 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
938 RF_CHNLBW, RFREG_OFFSET_MASK);
939 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
940 RF_CHNLBW, RFREG_OFFSET_MASK);
941 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
942 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
943 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
944 _rtl92ce_hw_configure(hw);
945 rtl_cam_reset_all_entry(hw);
946 rtl92ce_enable_hw_security_config(hw);
947
948 ppsc->rfpwr_state = ERFON;
949
950 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
951 _rtl92ce_enable_aspm_back_door(hw);
952 rtlpriv->intf_ops->enable_aspm(hw);
953
954 rtl8192ce_bt_hw_init(hw);
955
956 if (ppsc->rfpwr_state == ERFON) {
957 rtl92c_phy_set_rfpath_switch(hw, 1);
958 if (iqk_initialized) {
959 rtl92c_phy_iq_calibrate(hw, true);
960 } else {
961 rtl92c_phy_iq_calibrate(hw, false);
962 iqk_initialized = true;
963 }
964
965 rtl92c_dm_check_txpower_tracking(hw);
966 rtl92c_phy_lc_calibrate(hw);
967 }
968
969 is92c = IS_92C_SERIAL(rtlhal->version);
970 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
971 if (!(tmp_u1b & BIT(0))) {
972 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
973 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path A\n"));
974 }
975
976 if (!(tmp_u1b & BIT(1)) && is92c) {
977 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
978 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path B\n"));
979 }
980
981 if (!(tmp_u1b & BIT(4))) {
982 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
983 tmp_u1b &= 0x0F;
984 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
985 udelay(10);
986 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
987 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("under 1.5V\n"));
988 }
989 rtl92c_dm_init(hw);
990 rtlpci->being_init_adapter = false;
991 return err;
992}
993
994static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
995{
996 struct rtl_priv *rtlpriv = rtl_priv(hw);
997 struct rtl_phy *rtlphy = &(rtlpriv->phy);
998 enum version_8192c version = VERSION_UNKNOWN;
999 u32 value32;
1000
1001 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1002 if (value32 & TRP_VAUX_EN) {
1003 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1004 VERSION_A_CHIP_88C;
1005 } else {
1006 version = (value32 & TYPE_ID) ? VERSION_B_CHIP_92C :
1007 VERSION_B_CHIP_88C;
1008 }
1009
1010 switch (version) {
1011 case VERSION_B_CHIP_92C:
1012 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1013 ("Chip Version ID: VERSION_B_CHIP_92C.\n"));
1014 break;
1015 case VERSION_B_CHIP_88C:
1016 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1017 ("Chip Version ID: VERSION_B_CHIP_88C.\n"));
1018 break;
1019 case VERSION_A_CHIP_92C:
1020 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1021 ("Chip Version ID: VERSION_A_CHIP_92C.\n"));
1022 break;
1023 case VERSION_A_CHIP_88C:
1024 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1025 ("Chip Version ID: VERSION_A_CHIP_88C.\n"));
1026 break;
1027 default:
1028 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1029 ("Chip Version ID: Unknown. Bug?\n"));
1030 break;
1031 }
1032
1033 switch (version & 0x3) {
1034 case CHIP_88C:
1035 rtlphy->rf_type = RF_1T1R;
1036 break;
1037 case CHIP_92C:
1038 rtlphy->rf_type = RF_2T2R;
1039 break;
1040 case CHIP_92C_1T2R:
1041 rtlphy->rf_type = RF_1T2R;
1042 break;
1043 default:
1044 rtlphy->rf_type = RF_1T1R;
1045 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1046 ("ERROR RF_Type is set!!"));
1047 break;
1048 }
1049
1050 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1051 ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1052 "RF_2T2R" : "RF_1T1R"));
1053
1054 return version;
1055}
1056
1057static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1058 enum nl80211_iftype type)
1059{
1060 struct rtl_priv *rtlpriv = rtl_priv(hw);
1061 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1062 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1063 bt_msr &= 0xfc;
1064
1065 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1066 type == NL80211_IFTYPE_STATION) {
1067 _rtl92ce_stop_tx_beacon(hw);
1068 _rtl92ce_enable_bcn_sub_func(hw);
1069 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1070 _rtl92ce_resume_tx_beacon(hw);
1071 _rtl92ce_disable_bcn_sub_func(hw);
1072 } else {
1073 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1074 ("Set HW_VAR_MEDIA_STATUS: "
1075 "No such media status(%x).\n", type));
1076 }
1077
1078 switch (type) {
1079 case NL80211_IFTYPE_UNSPECIFIED:
1080 bt_msr |= MSR_NOLINK;
1081 ledaction = LED_CTL_LINK;
1082 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1083 ("Set Network type to NO LINK!\n"));
1084 break;
1085 case NL80211_IFTYPE_ADHOC:
1086 bt_msr |= MSR_ADHOC;
1087 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1088 ("Set Network type to Ad Hoc!\n"));
1089 break;
1090 case NL80211_IFTYPE_STATION:
1091 bt_msr |= MSR_INFRA;
1092 ledaction = LED_CTL_LINK;
1093 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1094 ("Set Network type to STA!\n"));
1095 break;
1096 case NL80211_IFTYPE_AP:
1097 bt_msr |= MSR_AP;
1098 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1099 ("Set Network type to AP!\n"));
1100 break;
1101 default:
1102 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1103 ("Network type %d not support!\n", type));
1104 return 1;
1105 break;
1106
1107 }
1108
1109 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1110 rtlpriv->cfg->ops->led_control(hw, ledaction);
1111 if ((bt_msr & 0xfc) == MSR_AP)
1112 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1113 else
1114 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1115 return 0;
1116}
1117
1118void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1119{
1120 struct rtl_priv *rtlpriv = rtl_priv(hw);
1121 u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1122
1123 if (rtlpriv->psc.rfpwr_state != ERFON)
1124 return;
1125
1126 if (check_bssid == true) {
1127 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1128 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1129 (u8 *) (&reg_rcr));
1130 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1131 } else if (check_bssid == false) {
1132 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1133 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1134 rtlpriv->cfg->ops->set_hw_reg(hw,
1135 HW_VAR_RCR, (u8 *) (&reg_rcr));
1136 }
1137
1138}
1139
1140int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1141{
1142 struct rtl_priv *rtlpriv = rtl_priv(hw);
1143
1144 if (_rtl92ce_set_media_status(hw, type))
1145 return -EOPNOTSUPP;
1146
1147 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1148 if (type != NL80211_IFTYPE_AP)
1149 rtl92ce_set_check_bssid(hw, true);
1150 } else {
1151 rtl92ce_set_check_bssid(hw, false);
1152 }
1153
1154 return 0;
1155}
1156
1157/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1158void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1159{
1160 struct rtl_priv *rtlpriv = rtl_priv(hw);
1161 rtl92c_dm_init_edca_turbo(hw);
1162 switch (aci) {
1163 case AC1_BK:
1164 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1165 break;
1166 case AC0_BE:
1167 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1168 break;
1169 case AC2_VI:
1170 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1171 break;
1172 case AC3_VO:
1173 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1174 break;
1175 default:
1176 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1177 break;
1178 }
1179}
1180
1181void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1182{
1183 struct rtl_priv *rtlpriv = rtl_priv(hw);
1184 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1185
1186 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1187 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1188 rtlpci->irq_enabled = true;
1189}
1190
1191void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1192{
1193 struct rtl_priv *rtlpriv = rtl_priv(hw);
1194 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1195
1196 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1197 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1198 rtlpci->irq_enabled = false;
1199}
1200
1201static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1202{
1203 struct rtl_priv *rtlpriv = rtl_priv(hw);
1204 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1206 u8 u1b_tmp;
1207 u32 u4b_tmp;
1208
1209 rtlpriv->intf_ops->enable_aspm(hw);
1210 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1211 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1212 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1213 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1214 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1215 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1216 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1217 rtl92c_firmware_selfreset(hw);
1218 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1219 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1220 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1221 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1222 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1223 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1224 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1225 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1226 (u1b_tmp << 8));
1227 } else {
1228 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1229 (u1b_tmp << 8));
1230 }
1231 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1232 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1233 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1234 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1235 if (rtlpcipriv->bt_coexist.bt_coexistence) {
1236 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1237 u4b_tmp |= 0x03824800;
1238 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1239 } else {
1240 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1241 }
1242
1243 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1244 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1245}
1246
1247void rtl92ce_card_disable(struct ieee80211_hw *hw)
1248{
1249 struct rtl_priv *rtlpriv = rtl_priv(hw);
1250 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1251 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1252 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1253 enum nl80211_iftype opmode;
1254
1255 mac->link_state = MAC80211_NOLINK;
1256 opmode = NL80211_IFTYPE_UNSPECIFIED;
1257 _rtl92ce_set_media_status(hw, opmode);
1258 if (rtlpci->driver_is_goingto_unload ||
1259 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1260 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1261 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1262 _rtl92ce_poweroff_adapter(hw);
1263}
1264
1265void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1266 u32 *p_inta, u32 *p_intb)
1267{
1268 struct rtl_priv *rtlpriv = rtl_priv(hw);
1269 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1270
1271 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1272 rtl_write_dword(rtlpriv, ISR, *p_inta);
1273
1274 /*
1275 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1276 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1277 */
1278}
1279
1280void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1281{
1282
1283 struct rtl_priv *rtlpriv = rtl_priv(hw);
1284 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1285 u16 bcn_interval, atim_window;
1286
1287 bcn_interval = mac->beacon_interval;
1288 atim_window = 2; /*FIX MERGE */
1289 rtl92ce_disable_interrupt(hw);
1290 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1291 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1292 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1293 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1294 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1295 rtl_write_byte(rtlpriv, 0x606, 0x30);
1296 rtl92ce_enable_interrupt(hw);
1297}
1298
1299void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1300{
1301 struct rtl_priv *rtlpriv = rtl_priv(hw);
1302 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1303 u16 bcn_interval = mac->beacon_interval;
1304
1305 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1306 ("beacon_interval:%d\n", bcn_interval));
1307 rtl92ce_disable_interrupt(hw);
1308 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1309 rtl92ce_enable_interrupt(hw);
1310}
1311
1312void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1313 u32 add_msr, u32 rm_msr)
1314{
1315 struct rtl_priv *rtlpriv = rtl_priv(hw);
1316 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1317
1318 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1319 ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1320
1321 if (add_msr)
1322 rtlpci->irq_mask[0] |= add_msr;
1323 if (rm_msr)
1324 rtlpci->irq_mask[0] &= (~rm_msr);
1325 rtl92ce_disable_interrupt(hw);
1326 rtl92ce_enable_interrupt(hw);
1327}
1328
1329static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1330 bool autoload_fail,
1331 u8 *hwinfo)
1332{
1333 struct rtl_priv *rtlpriv = rtl_priv(hw);
1334 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1335 u8 rf_path, index, tempval;
1336 u16 i;
1337
1338 for (rf_path = 0; rf_path < 2; rf_path++) {
1339 for (i = 0; i < 3; i++) {
1340 if (!autoload_fail) {
1341 rtlefuse->
1342 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1343 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1344 rtlefuse->
1345 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1346 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1347 i];
1348 } else {
1349 rtlefuse->
1350 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1351 EEPROM_DEFAULT_TXPOWERLEVEL;
1352 rtlefuse->
1353 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1354 EEPROM_DEFAULT_TXPOWERLEVEL;
1355 }
1356 }
1357 }
1358
1359 for (i = 0; i < 3; i++) {
1360 if (!autoload_fail)
1361 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1362 else
1363 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1364 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
1365 (tempval & 0xf);
1366 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
1367 ((tempval & 0xf0) >> 4);
1368 }
1369
1370 for (rf_path = 0; rf_path < 2; rf_path++)
1371 for (i = 0; i < 3; i++)
1372 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1373 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1374 i,
1375 rtlefuse->
1376 eeprom_chnlarea_txpwr_cck[rf_path][i]));
1377 for (rf_path = 0; rf_path < 2; rf_path++)
1378 for (i = 0; i < 3; i++)
1379 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1380 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1381 rf_path, i,
1382 rtlefuse->
1383 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
1384 for (rf_path = 0; rf_path < 2; rf_path++)
1385 for (i = 0; i < 3; i++)
1386 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1387 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1388 rf_path, i,
1389 rtlefuse->
1390 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1391 [i]));
1392
1393 for (rf_path = 0; rf_path < 2; rf_path++) {
1394 for (i = 0; i < 14; i++) {
1395 index = _rtl92c_get_chnl_group((u8) i);
1396
1397 rtlefuse->txpwrlevel_cck[rf_path][i] =
1398 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1399 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1400 rtlefuse->
1401 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1402
1403 if ((rtlefuse->
1404 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1405 rtlefuse->
1406 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
1407 > 0) {
1408 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1409 rtlefuse->
1410 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1411 [index] -
1412 rtlefuse->
1413 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1414 [index];
1415 } else {
1416 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1417 }
1418 }
1419
1420 for (i = 0; i < 14; i++) {
1421 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1422 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1423 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1424 rtlefuse->txpwrlevel_cck[rf_path][i],
1425 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1426 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1427 }
1428 }
1429
1430 for (i = 0; i < 3; i++) {
1431 if (!autoload_fail) {
1432 rtlefuse->eeprom_pwrlimit_ht40[i] =
1433 hwinfo[EEPROM_TXPWR_GROUP + i];
1434 rtlefuse->eeprom_pwrlimit_ht20[i] =
1435 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1436 } else {
1437 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1438 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1439 }
1440 }
1441
1442 for (rf_path = 0; rf_path < 2; rf_path++) {
1443 for (i = 0; i < 14; i++) {
1444 index = _rtl92c_get_chnl_group((u8) i);
1445
1446 if (rf_path == RF90_PATH_A) {
1447 rtlefuse->pwrgroup_ht20[rf_path][i] =
1448 (rtlefuse->eeprom_pwrlimit_ht20[index]
1449 & 0xf);
1450 rtlefuse->pwrgroup_ht40[rf_path][i] =
1451 (rtlefuse->eeprom_pwrlimit_ht40[index]
1452 & 0xf);
1453 } else if (rf_path == RF90_PATH_B) {
1454 rtlefuse->pwrgroup_ht20[rf_path][i] =
1455 ((rtlefuse->eeprom_pwrlimit_ht20[index]
1456 & 0xf0) >> 4);
1457 rtlefuse->pwrgroup_ht40[rf_path][i] =
1458 ((rtlefuse->eeprom_pwrlimit_ht40[index]
1459 & 0xf0) >> 4);
1460 }
1461
1462 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1463 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1464 rf_path, i,
1465 rtlefuse->pwrgroup_ht20[rf_path][i]));
1466 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1467 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1468 rf_path, i,
1469 rtlefuse->pwrgroup_ht40[rf_path][i]));
1470 }
1471 }
1472
1473 for (i = 0; i < 14; i++) {
1474 index = _rtl92c_get_chnl_group((u8) i);
1475
1476 if (!autoload_fail)
1477 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1478 else
1479 tempval = EEPROM_DEFAULT_HT20_DIFF;
1480
1481 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1482 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1483 ((tempval >> 4) & 0xF);
1484
1485 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1486 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1487
1488 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1489 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1490
1491 index = _rtl92c_get_chnl_group((u8) i);
1492
1493 if (!autoload_fail)
1494 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1495 else
1496 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1497
1498 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1499 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1500 ((tempval >> 4) & 0xF);
1501 }
1502
1503 rtlefuse->legacy_ht_txpowerdiff =
1504 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1505
1506 for (i = 0; i < 14; i++)
1507 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1508 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1509 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1510 for (i = 0; i < 14; i++)
1511 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1512 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1513 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1514 for (i = 0; i < 14; i++)
1515 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1516 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1517 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1518 for (i = 0; i < 14; i++)
1519 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1520 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1521 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1522
1523 if (!autoload_fail)
1524 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1525 else
1526 rtlefuse->eeprom_regulatory = 0;
1527 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1528 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1529
1530 if (!autoload_fail) {
1531 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1532 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1533 } else {
1534 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1535 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1536 }
1537 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1538 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1539 rtlefuse->eeprom_tssi[RF90_PATH_A],
1540 rtlefuse->eeprom_tssi[RF90_PATH_B]));
1541
1542 if (!autoload_fail)
1543 tempval = hwinfo[EEPROM_THERMAL_METER];
1544 else
1545 tempval = EEPROM_DEFAULT_THERMALMETER;
1546 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1547
1548 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1549 rtlefuse->apk_thermalmeterignore = true;
1550
1551 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1552 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1553 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
1554}
1555
1556static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1557{
1558 struct rtl_priv *rtlpriv = rtl_priv(hw);
1559 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1560 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1561 u16 i, usvalue;
1562 u8 hwinfo[HWSET_MAX_SIZE];
1563 u16 eeprom_id;
1564
1565 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1566 rtl_efuse_shadow_map_update(hw);
1567
1568 memcpy((void *)hwinfo,
1569 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1570 HWSET_MAX_SIZE);
1571 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1572 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1573 ("RTL819X Not boot from eeprom, check it !!"));
1574 }
1575
1576 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1577 hwinfo, HWSET_MAX_SIZE);
1578
1579 eeprom_id = *((u16 *)&hwinfo[0]);
1580 if (eeprom_id != RTL8190_EEPROM_ID) {
1581 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1582 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1583 rtlefuse->autoload_failflag = true;
1584 } else {
1585 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1586 rtlefuse->autoload_failflag = false;
1587 }
1588
1589 if (rtlefuse->autoload_failflag == true)
1590 return;
1591
1592 for (i = 0; i < 6; i += 2) {
1593 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1594 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1595 }
1596
1597 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1598 (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
1599
1600 _rtl92ce_read_txpower_info_from_hwpg(hw,
1601 rtlefuse->autoload_failflag,
1602 hwinfo);
1603
1604 rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1605 rtlefuse->autoload_failflag,
1606 hwinfo);
1607
1608 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1609 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1610 rtlefuse->txpwr_fromeprom = true;
1611 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1612
1613 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1614 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
1615
1616 /* set channel paln to world wide 13 */
1617 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1618
1619 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1620 switch (rtlefuse->eeprom_oemid) {
1621 case EEPROM_CID_DEFAULT:
1622 if (rtlefuse->eeprom_did == 0x8176) {
1623 if ((rtlefuse->eeprom_svid == 0x103C &&
1624 rtlefuse->eeprom_smid == 0x1629))
1625 rtlhal->oem_id = RT_CID_819x_HP;
1626 else
1627 rtlhal->oem_id = RT_CID_DEFAULT;
1628 } else {
1629 rtlhal->oem_id = RT_CID_DEFAULT;
1630 }
1631 break;
1632 case EEPROM_CID_TOSHIBA:
1633 rtlhal->oem_id = RT_CID_TOSHIBA;
1634 break;
1635 case EEPROM_CID_QMI:
1636 rtlhal->oem_id = RT_CID_819x_QMI;
1637 break;
1638 case EEPROM_CID_WHQL:
1639 default:
1640 rtlhal->oem_id = RT_CID_DEFAULT;
1641 break;
1642
1643 }
1644 }
1645
1646}
1647
1648static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1649{
1650 struct rtl_priv *rtlpriv = rtl_priv(hw);
1651 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1652 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1653
1654 switch (rtlhal->oem_id) {
1655 case RT_CID_819x_HP:
1656 pcipriv->ledctl.led_opendrain = true;
1657 break;
1658 case RT_CID_819x_Lenovo:
1659 case RT_CID_DEFAULT:
1660 case RT_CID_TOSHIBA:
1661 case RT_CID_CCX:
1662 case RT_CID_819x_Acer:
1663 case RT_CID_WHQL:
1664 default:
1665 break;
1666 }
1667 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1668 ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
1669}
1670
1671void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1672{
1673 struct rtl_priv *rtlpriv = rtl_priv(hw);
1674 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1675 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1676 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1677 u8 tmp_u1b;
1678
1679 rtlhal->version = _rtl92ce_read_chip_version(hw);
1680 if (get_rf_type(rtlphy) == RF_1T1R)
1681 rtlpriv->dm.rfpath_rxenable[0] = true;
1682 else
1683 rtlpriv->dm.rfpath_rxenable[0] =
1684 rtlpriv->dm.rfpath_rxenable[1] = true;
1685 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
1686 rtlhal->version));
1687 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1688 if (tmp_u1b & BIT(4)) {
1689 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1690 rtlefuse->epromtype = EEPROM_93C46;
1691 } else {
1692 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1693 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1694 }
1695 if (tmp_u1b & BIT(5)) {
1696 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1697 rtlefuse->autoload_failflag = false;
1698 _rtl92ce_read_adapter_info(hw);
1699 } else {
1700 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1701 }
1702 _rtl92ce_hal_customized_behavior(hw);
1703}
1704
1705static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1706 struct ieee80211_sta *sta)
1707{
1708 struct rtl_priv *rtlpriv = rtl_priv(hw);
1709 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1710 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1711 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1712 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1713 u32 ratr_value;
1714 u8 ratr_index = 0;
1715 u8 nmode = mac->ht_enable;
1716 u8 mimo_ps = IEEE80211_SMPS_OFF;
1717 u16 shortgi_rate;
1718 u32 tmp_ratr_value;
1719 u8 curtxbw_40mhz = mac->bw_40;
1720 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1721 1 : 0;
1722 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1723 1 : 0;
1724 enum wireless_mode wirelessmode = mac->mode;
1725
1726 if (rtlhal->current_bandtype == BAND_ON_5G)
1727 ratr_value = sta->supp_rates[1] << 4;
1728 else
1729 ratr_value = sta->supp_rates[0];
1730 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1731 sta->ht_cap.mcs.rx_mask[0] << 12);
1732 switch (wirelessmode) {
1733 case WIRELESS_MODE_B:
1734 if (ratr_value & 0x0000000c)
1735 ratr_value &= 0x0000000d;
1736 else
1737 ratr_value &= 0x0000000f;
1738 break;
1739 case WIRELESS_MODE_G:
1740 ratr_value &= 0x00000FF5;
1741 break;
1742 case WIRELESS_MODE_N_24G:
1743 case WIRELESS_MODE_N_5G:
1744 nmode = 1;
1745 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1746 ratr_value &= 0x0007F005;
1747 } else {
1748 u32 ratr_mask;
1749
1750 if (get_rf_type(rtlphy) == RF_1T2R ||
1751 get_rf_type(rtlphy) == RF_1T1R)
1752 ratr_mask = 0x000ff005;
1753 else
1754 ratr_mask = 0x0f0ff005;
1755
1756 ratr_value &= ratr_mask;
1757 }
1758 break;
1759 default:
1760 if (rtlphy->rf_type == RF_1T2R)
1761 ratr_value &= 0x000ff0ff;
1762 else
1763 ratr_value &= 0x0f0ff0ff;
1764
1765 break;
1766 }
1767
1768 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1769 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1770 (rtlpcipriv->bt_coexist.bt_cur_state) &&
1771 (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1772 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1773 (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1774 ratr_value &= 0x0fffcfc0;
1775 else
1776 ratr_value &= 0x0FFFFFFF;
1777
1778 if (nmode && ((curtxbw_40mhz &&
1779 curshortgi_40mhz) || (!curtxbw_40mhz &&
1780 curshortgi_20mhz))) {
1781
1782 ratr_value |= 0x10000000;
1783 tmp_ratr_value = (ratr_value >> 12);
1784
1785 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1786 if ((1 << shortgi_rate) & tmp_ratr_value)
1787 break;
1788 }
1789
1790 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1791 (shortgi_rate << 4) | (shortgi_rate);
1792 }
1793
1794 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1795
1796 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1797 ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
1798}
1799
1800static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1801 struct ieee80211_sta *sta, u8 rssi_level)
1802{
1803 struct rtl_priv *rtlpriv = rtl_priv(hw);
1804 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1805 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1806 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1807 struct rtl_sta_info *sta_entry = NULL;
1808 u32 ratr_bitmap;
1809 u8 ratr_index;
1810 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1811 ? 1 : 0;
1812 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1813 1 : 0;
1814 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1815 1 : 0;
1816 enum wireless_mode wirelessmode = 0;
1817 bool shortgi = false;
1818 u8 rate_mask[5];
1819 u8 macid = 0;
1820 u8 mimo_ps = IEEE80211_SMPS_OFF;
1821
1822 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1823 wirelessmode = sta_entry->wireless_mode;
1824 if (mac->opmode == NL80211_IFTYPE_STATION)
1825 curtxbw_40mhz = mac->bw_40;
1826 else if (mac->opmode == NL80211_IFTYPE_AP ||
1827 mac->opmode == NL80211_IFTYPE_ADHOC)
1828 macid = sta->aid + 1;
1829
1830 if (rtlhal->current_bandtype == BAND_ON_5G)
1831 ratr_bitmap = sta->supp_rates[1] << 4;
1832 else
1833 ratr_bitmap = sta->supp_rates[0];
1834 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1835 sta->ht_cap.mcs.rx_mask[0] << 12);
1836 switch (wirelessmode) {
1837 case WIRELESS_MODE_B:
1838 ratr_index = RATR_INX_WIRELESS_B;
1839 if (ratr_bitmap & 0x0000000c)
1840 ratr_bitmap &= 0x0000000d;
1841 else
1842 ratr_bitmap &= 0x0000000f;
1843 break;
1844 case WIRELESS_MODE_G:
1845 ratr_index = RATR_INX_WIRELESS_GB;
1846
1847 if (rssi_level == 1)
1848 ratr_bitmap &= 0x00000f00;
1849 else if (rssi_level == 2)
1850 ratr_bitmap &= 0x00000ff0;
1851 else
1852 ratr_bitmap &= 0x00000ff5;
1853 break;
1854 case WIRELESS_MODE_A:
1855 ratr_index = RATR_INX_WIRELESS_A;
1856 ratr_bitmap &= 0x00000ff0;
1857 break;
1858 case WIRELESS_MODE_N_24G:
1859 case WIRELESS_MODE_N_5G:
1860 ratr_index = RATR_INX_WIRELESS_NGB;
1861
1862 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1863 if (rssi_level == 1)
1864 ratr_bitmap &= 0x00070000;
1865 else if (rssi_level == 2)
1866 ratr_bitmap &= 0x0007f000;
1867 else
1868 ratr_bitmap &= 0x0007f005;
1869 } else {
1870 if (rtlphy->rf_type == RF_1T2R ||
1871 rtlphy->rf_type == RF_1T1R) {
1872 if (curtxbw_40mhz) {
1873 if (rssi_level == 1)
1874 ratr_bitmap &= 0x000f0000;
1875 else if (rssi_level == 2)
1876 ratr_bitmap &= 0x000ff000;
1877 else
1878 ratr_bitmap &= 0x000ff015;
1879 } else {
1880 if (rssi_level == 1)
1881 ratr_bitmap &= 0x000f0000;
1882 else if (rssi_level == 2)
1883 ratr_bitmap &= 0x000ff000;
1884 else
1885 ratr_bitmap &= 0x000ff005;
1886 }
1887 } else {
1888 if (curtxbw_40mhz) {
1889 if (rssi_level == 1)
1890 ratr_bitmap &= 0x0f0f0000;
1891 else if (rssi_level == 2)
1892 ratr_bitmap &= 0x0f0ff000;
1893 else
1894 ratr_bitmap &= 0x0f0ff015;
1895 } else {
1896 if (rssi_level == 1)
1897 ratr_bitmap &= 0x0f0f0000;
1898 else if (rssi_level == 2)
1899 ratr_bitmap &= 0x0f0ff000;
1900 else
1901 ratr_bitmap &= 0x0f0ff005;
1902 }
1903 }
1904 }
1905
1906 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1907 (!curtxbw_40mhz && curshortgi_20mhz)) {
1908
1909 if (macid == 0)
1910 shortgi = true;
1911 else if (macid == 1)
1912 shortgi = false;
1913 }
1914 break;
1915 default:
1916 ratr_index = RATR_INX_WIRELESS_NGB;
1917
1918 if (rtlphy->rf_type == RF_1T2R)
1919 ratr_bitmap &= 0x000ff0ff;
1920 else
1921 ratr_bitmap &= 0x0f0ff0ff;
1922 break;
1923 }
1924 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1925 ("ratr_bitmap :%x\n", ratr_bitmap));
1926 *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
1927 (ratr_index << 28));
1928 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1929 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
1930 "ratr_val:%x, %x:%x:%x:%x:%x\n",
1931 ratr_index, ratr_bitmap,
1932 rate_mask[0], rate_mask[1],
1933 rate_mask[2], rate_mask[3],
1934 rate_mask[4]));
1935 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1936
1937 if (macid != 0)
1938 sta_entry->ratr_index = ratr_index;
1939}
1940
1941void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1942 struct ieee80211_sta *sta, u8 rssi_level)
1943{
1944 struct rtl_priv *rtlpriv = rtl_priv(hw);
1945
1946 if (rtlpriv->dm.useramask)
1947 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
1948 else
1949 rtl92ce_update_hal_rate_table(hw, sta);
1950}
1951
1952void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1953{
1954 struct rtl_priv *rtlpriv = rtl_priv(hw);
1955 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1956 u16 sifs_timer;
1957
1958 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1959 (u8 *)&mac->slot_time);
1960 if (!mac->ht_enable)
1961 sifs_timer = 0x0a0a;
1962 else
1963 sifs_timer = 0x1010;
1964 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1965}
1966
1967bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
1968{
1969 struct rtl_priv *rtlpriv = rtl_priv(hw);
1970 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1971 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1972 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
1973 u8 u1tmp;
1974 bool actuallyset = false;
1975 unsigned long flag;
1976
1977 if (rtlpci->being_init_adapter)
1978 return false;
1979
1980 if (ppsc->swrf_processing)
1981 return false;
1982
1983 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1984 if (ppsc->rfchange_inprogress) {
1985 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1986 return false;
1987 } else {
1988 ppsc->rfchange_inprogress = true;
1989 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1990 }
1991
1992 cur_rfstate = ppsc->rfpwr_state;
1993
1994 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
1995 REG_MAC_PINMUX_CFG)&~(BIT(3)));
1996
1997 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1998 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
1999
2000 if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
2001 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2002 ("GPIOChangeRF - HW Radio ON, RF ON\n"));
2003
2004 e_rfpowerstate_toset = ERFON;
2005 ppsc->hwradiooff = false;
2006 actuallyset = true;
2007 } else if ((ppsc->hwradiooff == false)
2008 && (e_rfpowerstate_toset == ERFOFF)) {
2009 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2010 ("GPIOChangeRF - HW Radio OFF, RF OFF\n"));
2011
2012 e_rfpowerstate_toset = ERFOFF;
2013 ppsc->hwradiooff = true;
2014 actuallyset = true;
2015 }
2016
2017 if (actuallyset) {
2018 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2019 ppsc->rfchange_inprogress = false;
2020 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2021 } else {
2022 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2023 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2024
2025 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2026 ppsc->rfchange_inprogress = false;
2027 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2028 }
2029
2030 *valid = 1;
2031 return !ppsc->hwradiooff;
2032
2033}
2034
2035void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2036 u8 *p_macaddr, bool is_group, u8 enc_algo,
2037 bool is_wepkey, bool clear_all)
2038{
2039 struct rtl_priv *rtlpriv = rtl_priv(hw);
2040 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2041 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2042 u8 *macaddr = p_macaddr;
2043 u32 entry_id = 0;
2044 bool is_pairwise = false;
2045
2046 static u8 cam_const_addr[4][6] = {
2047 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2048 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2049 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2050 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2051 };
2052 static u8 cam_const_broad[] = {
2053 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2054 };
2055
2056 if (clear_all) {
2057 u8 idx = 0;
2058 u8 cam_offset = 0;
2059 u8 clear_number = 5;
2060
2061 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2062
2063 for (idx = 0; idx < clear_number; idx++) {
2064 rtl_cam_mark_invalid(hw, cam_offset + idx);
2065 rtl_cam_empty_entry(hw, cam_offset + idx);
2066
2067 if (idx < 5) {
2068 memset(rtlpriv->sec.key_buf[idx], 0,
2069 MAX_KEY_LEN);
2070 rtlpriv->sec.key_len[idx] = 0;
2071 }
2072 }
2073
2074 } else {
2075 switch (enc_algo) {
2076 case WEP40_ENCRYPTION:
2077 enc_algo = CAM_WEP40;
2078 break;
2079 case WEP104_ENCRYPTION:
2080 enc_algo = CAM_WEP104;
2081 break;
2082 case TKIP_ENCRYPTION:
2083 enc_algo = CAM_TKIP;
2084 break;
2085 case AESCCMP_ENCRYPTION:
2086 enc_algo = CAM_AES;
2087 break;
2088 default:
2089 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2090 "not process\n"));
2091 enc_algo = CAM_TKIP;
2092 break;
2093 }
2094
2095 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2096 macaddr = cam_const_addr[key_index];
2097 entry_id = key_index;
2098 } else {
2099 if (is_group) {
2100 macaddr = cam_const_broad;
2101 entry_id = key_index;
2102 } else {
2103 if (mac->opmode == NL80211_IFTYPE_AP) {
2104 entry_id = rtl_cam_get_free_entry(hw,
2105 p_macaddr);
2106 if (entry_id >= TOTAL_CAM_ENTRY) {
2107 RT_TRACE(rtlpriv, COMP_SEC,
2108 DBG_EMERG,
2109 ("Can not find free hw"
2110 " security cam entry\n"));
2111 return;
2112 }
2113 } else {
2114 entry_id = CAM_PAIRWISE_KEY_POSITION;
2115 }
2116
2117 key_index = PAIRWISE_KEYIDX;
2118 is_pairwise = true;
2119 }
2120 }
2121
2122 if (rtlpriv->sec.key_len[key_index] == 0) {
2123 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2124 ("delete one entry, entry_id is %d\n",
2125 entry_id));
2126 if (mac->opmode == NL80211_IFTYPE_AP)
2127 rtl_cam_del_entry(hw, p_macaddr);
2128 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2129 } else {
2130 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2131 ("The insert KEY length is %d\n",
2132 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2133 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2134 ("The insert KEY is %x %x\n",
2135 rtlpriv->sec.key_buf[0][0],
2136 rtlpriv->sec.key_buf[0][1]));
2137
2138 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2139 ("add one entry\n"));
2140 if (is_pairwise) {
2141 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2142 "Pairwiase Key content :",
2143 rtlpriv->sec.pairwise_key,
2144 rtlpriv->sec.
2145 key_len[PAIRWISE_KEYIDX]);
2146
2147 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2148 ("set Pairwiase key\n"));
2149
2150 rtl_cam_add_one_entry(hw, macaddr, key_index,
2151 entry_id, enc_algo,
2152 CAM_CONFIG_NO_USEDK,
2153 rtlpriv->sec.
2154 key_buf[key_index]);
2155 } else {
2156 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2157 ("set group key\n"));
2158
2159 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2160 rtl_cam_add_one_entry(hw,
2161 rtlefuse->dev_addr,
2162 PAIRWISE_KEYIDX,
2163 CAM_PAIRWISE_KEY_POSITION,
2164 enc_algo,
2165 CAM_CONFIG_NO_USEDK,
2166 rtlpriv->sec.key_buf
2167 [entry_id]);
2168 }
2169
2170 rtl_cam_add_one_entry(hw, macaddr, key_index,
2171 entry_id, enc_algo,
2172 CAM_CONFIG_NO_USEDK,
2173 rtlpriv->sec.key_buf[entry_id]);
2174 }
2175
2176 }
2177 }
2178}
2179
2180static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2181{
2182 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2183
2184 rtlpcipriv->bt_coexist.bt_coexistence =
2185 rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2186 rtlpcipriv->bt_coexist.bt_ant_num =
2187 rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2188 rtlpcipriv->bt_coexist.bt_coexist_type =
2189 rtlpcipriv->bt_coexist.eeprom_bt_type;
2190
2191 if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2192 rtlpcipriv->bt_coexist.bt_ant_isolation =
2193 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation;
2194 else
2195 rtlpcipriv->bt_coexist.bt_ant_isolation =
2196 rtlpcipriv->bt_coexist.reg_bt_iso;
2197
2198 rtlpcipriv->bt_coexist.bt_radio_shared_type =
2199 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2200
2201 if (rtlpcipriv->bt_coexist.bt_coexistence) {
2202
2203 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2204 rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2205 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2206 rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2207 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2208 rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2209 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2210 rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2211 else
2212 rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2213
2214 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2215 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2216 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2217 }
2218}
2219
2220void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2221 bool auto_load_fail, u8 *hwinfo)
2222{
2223 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2224 u8 value;
2225
2226 if (!auto_load_fail) {
2227 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2228 ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2229 value = hwinfo[RF_OPTION4];
2230 rtlpcipriv->bt_coexist.eeprom_bt_type = ((value & 0xe) >> 1);
2231 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1);
2232 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation =
2233 ((value & 0x10) >> 4);
2234 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2235 ((value & 0x20) >> 5);
2236 } else {
2237 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2238 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2239 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2240 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation = 0;
2241 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2242 }
2243
2244 rtl8192ce_bt_var_init(hw);
2245}
2246
2247void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2248{
2249 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2250
2251 /* 0:Low, 1:High, 2:From Efuse. */
2252 rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2253 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2254 rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2255 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2256 rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2257}
2258
2259
2260void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2261{
2262 struct rtl_priv *rtlpriv = rtl_priv(hw);
2263 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2264 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2265
2266 u8 u1_tmp;
2267
2268 if (rtlpcipriv->bt_coexist.bt_coexistence &&
2269 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2270 rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2271
2272 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2273 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2274
2275 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2276 BIT_OFFSET_LEN_MASK_32(0, 1);
2277 u1_tmp = u1_tmp |
2278 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2279 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2280 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2281 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2282 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2283
2284 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2285 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2286 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2287
2288 /* Config to 1T1R. */
2289 if (rtlphy->rf_type == RF_1T1R) {
2290 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2291 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2292 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2293
2294 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2295 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2296 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2297 }
2298 }
2299}
2300
2301void rtl92ce_suspend(struct ieee80211_hw *hw)
2302{
2303}
2304
2305void rtl92ce_resume(struct ieee80211_hw *hw)
2306{
2307}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.h b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.h
new file mode 100644
index 000000000000..07dbe3e340a5
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.h
@@ -0,0 +1,78 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CE_HW_H__
31#define __RTL92CE_HW_H__
32
33static inline u8 _rtl92c_get_chnl_group(u8 chnl)
34{
35 u8 group;
36
37 if (chnl < 3)
38 group = 0;
39 else if (chnl < 9)
40 group = 1;
41 else
42 group = 2;
43 return group;
44}
45
46void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
47void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw);
48void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
49 u32 *p_inta, u32 *p_intb);
50int rtl92ce_hw_init(struct ieee80211_hw *hw);
51void rtl92ce_card_disable(struct ieee80211_hw *hw);
52void rtl92ce_enable_interrupt(struct ieee80211_hw *hw);
53void rtl92ce_disable_interrupt(struct ieee80211_hw *hw);
54int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
55void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
56void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci);
57void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw);
58void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw);
59void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
60 u32 add_msr, u32 rm_msr);
61void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
62void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
63 struct ieee80211_sta *sta, u8 rssi_level);
64void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw);
65bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
66void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw);
67void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
68 u8 *p_macaddr, bool is_group, u8 enc_algo,
69 bool is_wepkey, bool clear_all);
70
71void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
72 bool autoload_fail, u8 *hwinfo);
73void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw);
74void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw);
75void rtl92ce_suspend(struct ieee80211_hw *hw);
76void rtl92ce_resume(struct ieee80211_hw *hw);
77
78#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/led.c b/drivers/net/wireless/rtlwifi/rtl8192ce/led.c
new file mode 100644
index 000000000000..9dd1ed7b6422
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/led.c
@@ -0,0 +1,151 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "reg.h"
33#include "led.h"
34
35static void _rtl92ce_init_led(struct ieee80211_hw *hw,
36 struct rtl_led *pled, enum rtl_led_pin ledpin)
37{
38 pled->hw = hw;
39 pled->ledpin = ledpin;
40 pled->ledon = false;
41}
42
43void rtl92ce_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
44{
45 u8 ledcfg;
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47
48 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
49 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
50
51 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
52
53 switch (pled->ledpin) {
54 case LED_PIN_GPIO0:
55 break;
56 case LED_PIN_LED0:
57 rtl_write_byte(rtlpriv,
58 REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5) | BIT(6));
59 break;
60 case LED_PIN_LED1:
61 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5));
62 break;
63 default:
64 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
65 ("switch case not process\n"));
66 break;
67 }
68 pled->ledon = true;
69}
70
71void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
72{
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
75 u8 ledcfg;
76
77 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
78 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
79
80 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
81
82 switch (pled->ledpin) {
83 case LED_PIN_GPIO0:
84 break;
85 case LED_PIN_LED0:
86 ledcfg &= 0xf0;
87 if (pcipriv->ledctl.led_opendrain == true)
88 rtl_write_byte(rtlpriv, REG_LEDCFG2,
89 (ledcfg | BIT(1) | BIT(5) | BIT(6)));
90 else
91 rtl_write_byte(rtlpriv, REG_LEDCFG2,
92 (ledcfg | BIT(3) | BIT(5) | BIT(6)));
93 break;
94 case LED_PIN_LED1:
95 ledcfg &= 0x0f;
96 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3)));
97 break;
98 default:
99 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
100 ("switch case not process\n"));
101 break;
102 }
103 pled->ledon = false;
104}
105
106void rtl92ce_init_sw_leds(struct ieee80211_hw *hw)
107{
108 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
109 _rtl92ce_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0);
110 _rtl92ce_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1);
111}
112
113static void _rtl92ce_sw_led_control(struct ieee80211_hw *hw,
114 enum led_ctl_mode ledaction)
115{
116 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
117 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
118 switch (ledaction) {
119 case LED_CTL_POWER_ON:
120 case LED_CTL_LINK:
121 case LED_CTL_NO_LINK:
122 rtl92ce_sw_led_on(hw, pLed0);
123 break;
124 case LED_CTL_POWER_OFF:
125 rtl92ce_sw_led_off(hw, pLed0);
126 break;
127 default:
128 break;
129 }
130}
131
132void rtl92ce_led_control(struct ieee80211_hw *hw,
133 enum led_ctl_mode ledaction)
134{
135 struct rtl_priv *rtlpriv = rtl_priv(hw);
136 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
137
138 if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
139 (ledaction == LED_CTL_TX ||
140 ledaction == LED_CTL_RX ||
141 ledaction == LED_CTL_SITE_SURVEY ||
142 ledaction == LED_CTL_LINK ||
143 ledaction == LED_CTL_NO_LINK ||
144 ledaction == LED_CTL_START_TO_LINK ||
145 ledaction == LED_CTL_POWER_ON)) {
146 return;
147 }
148 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, ("ledaction %d.\n",
149 ledaction));
150 _rtl92ce_sw_led_control(hw, ledaction);
151}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/led.h b/drivers/net/wireless/rtlwifi/rtl8192ce/led.h
new file mode 100644
index 000000000000..7dfccea2095b
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/led.h
@@ -0,0 +1,38 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CE_LED_H__
31#define __RTL92CE_LED_H__
32
33void rtl92ce_init_sw_leds(struct ieee80211_hw *hw);
34void rtl92ce_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
35void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
36void rtl92ce_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
37
38#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
new file mode 100644
index 000000000000..abe0fcc75368
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
@@ -0,0 +1,635 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "hw.h"
36#include "phy.h"
37#include "rf.h"
38#include "dm.h"
39#include "table.h"
40
41static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
42
43u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
44 enum radio_path rfpath, u32 regaddr, u32 bitmask)
45{
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 u32 original_value, readback_value, bitshift;
48 struct rtl_phy *rtlphy = &(rtlpriv->phy);
49 unsigned long flags;
50
51 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
52 "rfpath(%#x), bitmask(%#x)\n",
53 regaddr, rfpath, bitmask));
54
55 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
56
57 if (rtlphy->rf_mode != RF_OP_BY_FW) {
58 original_value = _rtl92c_phy_rf_serial_read(hw,
59 rfpath, regaddr);
60 } else {
61 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
62 rfpath, regaddr);
63 }
64
65 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
66 readback_value = (original_value & bitmask) >> bitshift;
67
68 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
69
70 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
71 ("regaddr(%#x), rfpath(%#x), "
72 "bitmask(%#x), original_value(%#x)\n",
73 regaddr, rfpath, bitmask, original_value));
74
75 return readback_value;
76}
77
78bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
79{
80 struct rtl_priv *rtlpriv = rtl_priv(hw);
81 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
82 bool is92c = IS_92C_SERIAL(rtlhal->version);
83 bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
84
85 if (is92c)
86 rtl_write_byte(rtlpriv, 0x14, 0x71);
87 return rtstatus;
88}
89
90bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
91{
92 bool rtstatus = true;
93 struct rtl_priv *rtlpriv = rtl_priv(hw);
94 u16 regval;
95 u32 regvaldw;
96 u8 reg_hwparafile = 1;
97
98 _rtl92c_phy_init_bb_rf_register_definition(hw);
99 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
100 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
101 regval | BIT(13) | BIT(0) | BIT(1));
102 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
103 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
104 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
105 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
106 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
107 FEN_BB_GLB_RSTn | FEN_BBRSTB);
108 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
109 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
110 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
111 if (reg_hwparafile == 1)
112 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
113 return rtstatus;
114}
115
116void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
117 enum radio_path rfpath,
118 u32 regaddr, u32 bitmask, u32 data)
119{
120 struct rtl_priv *rtlpriv = rtl_priv(hw);
121 struct rtl_phy *rtlphy = &(rtlpriv->phy);
122 u32 original_value, bitshift;
123 unsigned long flags;
124
125 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
126 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
127 regaddr, bitmask, data, rfpath));
128
129 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
130
131 if (rtlphy->rf_mode != RF_OP_BY_FW) {
132 if (bitmask != RFREG_OFFSET_MASK) {
133 original_value = _rtl92c_phy_rf_serial_read(hw,
134 rfpath,
135 regaddr);
136 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
137 data =
138 ((original_value & (~bitmask)) |
139 (data << bitshift));
140 }
141
142 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
143 } else {
144 if (bitmask != RFREG_OFFSET_MASK) {
145 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
146 rfpath,
147 regaddr);
148 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
149 data =
150 ((original_value & (~bitmask)) |
151 (data << bitshift));
152 }
153 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
154 }
155
156 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
157
158 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
159 "bitmask(%#x), data(%#x), "
160 "rfpath(%#x)\n", regaddr,
161 bitmask, data, rfpath));
162}
163
164static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
165{
166 struct rtl_priv *rtlpriv = rtl_priv(hw);
167 u32 i;
168 u32 arraylength;
169 u32 *ptrarray;
170
171 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
172 arraylength = MAC_2T_ARRAYLENGTH;
173 ptrarray = RTL8192CEMAC_2T_ARRAY;
174 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
175 ("Img:RTL8192CEMAC_2T_ARRAY\n"));
176 for (i = 0; i < arraylength; i = i + 2)
177 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
178 return true;
179}
180
181bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
182 u8 configtype)
183{
184 int i;
185 u32 *phy_regarray_table;
186 u32 *agctab_array_table;
187 u16 phy_reg_arraylen, agctab_arraylen;
188 struct rtl_priv *rtlpriv = rtl_priv(hw);
189 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
190
191 if (IS_92C_SERIAL(rtlhal->version)) {
192 agctab_arraylen = AGCTAB_2TARRAYLENGTH;
193 agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
194 phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
195 phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
196 } else {
197 agctab_arraylen = AGCTAB_1TARRAYLENGTH;
198 agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
199 phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
200 phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
201 }
202 if (configtype == BASEBAND_CONFIG_PHY_REG) {
203 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
204 if (phy_regarray_table[i] == 0xfe)
205 mdelay(50);
206 else if (phy_regarray_table[i] == 0xfd)
207 mdelay(5);
208 else if (phy_regarray_table[i] == 0xfc)
209 mdelay(1);
210 else if (phy_regarray_table[i] == 0xfb)
211 udelay(50);
212 else if (phy_regarray_table[i] == 0xfa)
213 udelay(5);
214 else if (phy_regarray_table[i] == 0xf9)
215 udelay(1);
216 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
217 phy_regarray_table[i + 1]);
218 udelay(1);
219 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
220 ("The phy_regarray_table[0] is %x"
221 " Rtl819XPHY_REGArray[1] is %x\n",
222 phy_regarray_table[i],
223 phy_regarray_table[i + 1]));
224 }
225 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
226 for (i = 0; i < agctab_arraylen; i = i + 2) {
227 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
228 agctab_array_table[i + 1]);
229 udelay(1);
230 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
231 ("The agctab_array_table[0] is "
232 "%x Rtl819XPHY_REGArray[1] is %x\n",
233 agctab_array_table[i],
234 agctab_array_table[i + 1]));
235 }
236 }
237 return true;
238}
239
240bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
241 u8 configtype)
242{
243 struct rtl_priv *rtlpriv = rtl_priv(hw);
244 int i;
245 u32 *phy_regarray_table_pg;
246 u16 phy_regarray_pg_len;
247
248 phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
249 phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
250
251 if (configtype == BASEBAND_CONFIG_PHY_REG) {
252 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
253 if (phy_regarray_table_pg[i] == 0xfe)
254 mdelay(50);
255 else if (phy_regarray_table_pg[i] == 0xfd)
256 mdelay(5);
257 else if (phy_regarray_table_pg[i] == 0xfc)
258 mdelay(1);
259 else if (phy_regarray_table_pg[i] == 0xfb)
260 udelay(50);
261 else if (phy_regarray_table_pg[i] == 0xfa)
262 udelay(5);
263 else if (phy_regarray_table_pg[i] == 0xf9)
264 udelay(1);
265
266 _rtl92c_store_pwrIndex_diffrate_offset(hw,
267 phy_regarray_table_pg[i],
268 phy_regarray_table_pg[i + 1],
269 phy_regarray_table_pg[i + 2]);
270 }
271 } else {
272
273 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
274 ("configtype != BaseBand_Config_PHY_REG\n"));
275 }
276 return true;
277}
278
279bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
280 enum radio_path rfpath)
281{
282
283 int i;
284 bool rtstatus = true;
285 u32 *radioa_array_table;
286 u32 *radiob_array_table;
287 u16 radioa_arraylen, radiob_arraylen;
288 struct rtl_priv *rtlpriv = rtl_priv(hw);
289 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
290
291 if (IS_92C_SERIAL(rtlhal->version)) {
292 radioa_arraylen = RADIOA_2TARRAYLENGTH;
293 radioa_array_table = RTL8192CERADIOA_2TARRAY;
294 radiob_arraylen = RADIOB_2TARRAYLENGTH;
295 radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
296 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
297 ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
298 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
299 ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
300 } else {
301 radioa_arraylen = RADIOA_1TARRAYLENGTH;
302 radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
303 radiob_arraylen = RADIOB_1TARRAYLENGTH;
304 radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
305 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
306 ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
307 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
308 ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
309 }
310 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
311 rtstatus = true;
312 switch (rfpath) {
313 case RF90_PATH_A:
314 for (i = 0; i < radioa_arraylen; i = i + 2) {
315 if (radioa_array_table[i] == 0xfe)
316 mdelay(50);
317 else if (radioa_array_table[i] == 0xfd)
318 mdelay(5);
319 else if (radioa_array_table[i] == 0xfc)
320 mdelay(1);
321 else if (radioa_array_table[i] == 0xfb)
322 udelay(50);
323 else if (radioa_array_table[i] == 0xfa)
324 udelay(5);
325 else if (radioa_array_table[i] == 0xf9)
326 udelay(1);
327 else {
328 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
329 RFREG_OFFSET_MASK,
330 radioa_array_table[i + 1]);
331 udelay(1);
332 }
333 }
334 break;
335 case RF90_PATH_B:
336 for (i = 0; i < radiob_arraylen; i = i + 2) {
337 if (radiob_array_table[i] == 0xfe) {
338 mdelay(50);
339 } else if (radiob_array_table[i] == 0xfd)
340 mdelay(5);
341 else if (radiob_array_table[i] == 0xfc)
342 mdelay(1);
343 else if (radiob_array_table[i] == 0xfb)
344 udelay(50);
345 else if (radiob_array_table[i] == 0xfa)
346 udelay(5);
347 else if (radiob_array_table[i] == 0xf9)
348 udelay(1);
349 else {
350 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
351 RFREG_OFFSET_MASK,
352 radiob_array_table[i + 1]);
353 udelay(1);
354 }
355 }
356 break;
357 case RF90_PATH_C:
358 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
359 ("switch case not process\n"));
360 break;
361 case RF90_PATH_D:
362 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
363 ("switch case not process\n"));
364 break;
365 }
366 return true;
367}
368
369void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
370{
371 struct rtl_priv *rtlpriv = rtl_priv(hw);
372 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
373 struct rtl_phy *rtlphy = &(rtlpriv->phy);
374 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
375 u8 reg_bw_opmode;
376 u8 reg_prsr_rsc;
377
378 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
379 ("Switch to %s bandwidth\n",
380 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
381 "20MHz" : "40MHz"))
382
383 if (is_hal_stop(rtlhal)) {
384 rtlphy->set_bwmode_inprogress = false;
385 return;
386 }
387
388 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
389 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
390
391 switch (rtlphy->current_chan_bw) {
392 case HT_CHANNEL_WIDTH_20:
393 reg_bw_opmode |= BW_OPMODE_20MHZ;
394 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
395 break;
396 case HT_CHANNEL_WIDTH_20_40:
397 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
398 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
399 reg_prsr_rsc =
400 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
401 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
402 break;
403 default:
404 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
405 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
406 break;
407 }
408
409 switch (rtlphy->current_chan_bw) {
410 case HT_CHANNEL_WIDTH_20:
411 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
412 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
413 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
414 break;
415 case HT_CHANNEL_WIDTH_20_40:
416 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
417 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
418
419 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
420 (mac->cur_40_prime_sc >> 1));
421 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
422 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
423
424 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
425 (mac->cur_40_prime_sc ==
426 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
427 break;
428 default:
429 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
430 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
431 break;
432 }
433 rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
434 rtlphy->set_bwmode_inprogress = false;
435 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
436}
437
438void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
439{
440 u8 tmpreg;
441 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
442 struct rtl_priv *rtlpriv = rtl_priv(hw);
443
444 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
445
446 if ((tmpreg & 0x70) != 0)
447 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
448 else
449 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
450
451 if ((tmpreg & 0x70) != 0) {
452 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
453
454 if (is2t)
455 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
456 MASK12BITS);
457
458 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
459 (rf_a_mode & 0x8FFFF) | 0x10000);
460
461 if (is2t)
462 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
463 (rf_b_mode & 0x8FFFF) | 0x10000);
464 }
465 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
466
467 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
468
469 mdelay(100);
470
471 if ((tmpreg & 0x70) != 0) {
472 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
473 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
474
475 if (is2t)
476 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
477 rf_b_mode);
478 } else {
479 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
480 }
481}
482
483static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
484{
485 u32 u4b_tmp;
486 u8 delay = 5;
487 struct rtl_priv *rtlpriv = rtl_priv(hw);
488
489 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
490 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
491 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
492 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
493 while (u4b_tmp != 0 && delay > 0) {
494 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
495 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
496 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
497 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
498 delay--;
499 }
500 if (delay == 0) {
501 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
502 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
503 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
504 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
505 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
506 ("Switch RF timeout !!!.\n"));
507 return;
508 }
509 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
510 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
511}
512
513static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
514 enum rf_pwrstate rfpwr_state)
515{
516 struct rtl_priv *rtlpriv = rtl_priv(hw);
517 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
518 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
519 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
520 bool bresult = true;
521 u8 i, queue_id;
522 struct rtl8192_tx_ring *ring = NULL;
523
524 ppsc->set_rfpowerstate_inprogress = true;
525 switch (rfpwr_state) {
526 case ERFON:{
527 if ((ppsc->rfpwr_state == ERFOFF) &&
528 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
529 bool rtstatus;
530 u32 InitializeCount = 0;
531 do {
532 InitializeCount++;
533 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
534 ("IPS Set eRf nic enable\n"));
535 rtstatus = rtl_ps_enable_nic(hw);
536 } while ((rtstatus != true)
537 && (InitializeCount < 10));
538 RT_CLEAR_PS_LEVEL(ppsc,
539 RT_RF_OFF_LEVL_HALT_NIC);
540 } else {
541 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
542 ("Set ERFON sleeped:%d ms\n",
543 jiffies_to_msecs(jiffies -
544 ppsc->
545 last_sleep_jiffies)));
546 ppsc->last_awake_jiffies = jiffies;
547 rtl92ce_phy_set_rf_on(hw);
548 }
549 if (mac->link_state == MAC80211_LINKED) {
550 rtlpriv->cfg->ops->led_control(hw,
551 LED_CTL_LINK);
552 } else {
553 rtlpriv->cfg->ops->led_control(hw,
554 LED_CTL_NO_LINK);
555 }
556 break;
557 }
558 case ERFOFF:{
559 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
560 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
561 ("IPS Set eRf nic disable\n"));
562 rtl_ps_disable_nic(hw);
563 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
564 } else {
565 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
566 rtlpriv->cfg->ops->led_control(hw,
567 LED_CTL_NO_LINK);
568 } else {
569 rtlpriv->cfg->ops->led_control(hw,
570 LED_CTL_POWER_OFF);
571 }
572 }
573 break;
574 }
575 case ERFSLEEP:{
576 if (ppsc->rfpwr_state == ERFOFF)
577 break;
578 for (queue_id = 0, i = 0;
579 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
580 ring = &pcipriv->dev.tx_ring[queue_id];
581 if (skb_queue_len(&ring->queue) == 0) {
582 queue_id++;
583 continue;
584 } else {
585 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
586 ("eRf Off/Sleep: %d times "
587 "TcbBusyQueue[%d] =%d before "
588 "doze!\n", (i + 1), queue_id,
589 skb_queue_len(&ring->queue)));
590
591 udelay(10);
592 i++;
593 }
594 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
595 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
596 ("\n ERFSLEEP: %d times "
597 "TcbBusyQueue[%d] = %d !\n",
598 MAX_DOZE_WAITING_TIMES_9x,
599 queue_id,
600 skb_queue_len(&ring->queue)));
601 break;
602 }
603 }
604 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
605 ("Set ERFSLEEP awaked:%d ms\n",
606 jiffies_to_msecs(jiffies -
607 ppsc->last_awake_jiffies)));
608 ppsc->last_sleep_jiffies = jiffies;
609 _rtl92ce_phy_set_rf_sleep(hw);
610 break;
611 }
612 default:
613 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
614 ("switch case not process\n"));
615 bresult = false;
616 break;
617 }
618 if (bresult)
619 ppsc->rfpwr_state = rfpwr_state;
620 ppsc->set_rfpowerstate_inprogress = false;
621 return bresult;
622}
623
624bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
625 enum rf_pwrstate rfpwr_state)
626{
627 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
628
629 bool bresult = false;
630
631 if (rfpwr_state == ppsc->rfpwr_state)
632 return bresult;
633 bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
634 return bresult;
635}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.h b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.h
new file mode 100644
index 000000000000..be2c92adef33
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.h
@@ -0,0 +1,262 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_PHY_H__
31#define __RTL92C_PHY_H__
32
33#define MAX_PRECMD_CNT 16
34#define MAX_RFDEPENDCMD_CNT 16
35#define MAX_POSTCMD_CNT 16
36
37#define MAX_DOZE_WAITING_TIMES_9x 64
38
39#define RT_CANNOT_IO(hw) false
40#define HIGHPOWER_RADIOA_ARRAYLEN 22
41
42#define IQK_ADDA_REG_NUM 16
43#define MAX_TOLERANCE 5
44#define IQK_DELAY_TIME 1
45
46#define APK_BB_REG_NUM 5
47#define APK_AFE_REG_NUM 16
48#define APK_CURVE_REG_NUM 4
49#define PATH_NUM 2
50
51#define LOOP_LIMIT 5
52#define MAX_STALL_TIME 50
53#define AntennaDiversityValue 0x80
54#define MAX_TXPWR_IDX_NMODE_92S 63
55#define Reset_Cnt_Limit 3
56
57#define IQK_ADDA_REG_NUM 16
58#define IQK_MAC_REG_NUM 4
59
60#define IQK_DELAY_TIME 1
61
62#define RF90_PATH_MAX 2
63
64#define CT_OFFSET_MAC_ADDR 0X16
65
66#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
67#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
68#define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66
69#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
70#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
71
72#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
73#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
74
75#define CT_OFFSET_CHANNEL_PLAH 0x75
76#define CT_OFFSET_THERMAL_METER 0x78
77#define CT_OFFSET_RF_OPTION 0x79
78#define CT_OFFSET_VERSION 0x7E
79#define CT_OFFSET_CUSTOMER_ID 0x7F
80
81#define RTL92C_MAX_PATH_NUM 2
82
83enum swchnlcmd_id {
84 CMDID_END,
85 CMDID_SET_TXPOWEROWER_LEVEL,
86 CMDID_BBREGWRITE10,
87 CMDID_WRITEPORT_ULONG,
88 CMDID_WRITEPORT_USHORT,
89 CMDID_WRITEPORT_UCHAR,
90 CMDID_RF_WRITEREG,
91};
92
93struct swchnlcmd {
94 enum swchnlcmd_id cmdid;
95 u32 para1;
96 u32 para2;
97 u32 msdelay;
98};
99
100enum hw90_block_e {
101 HW90_BLOCK_MAC = 0,
102 HW90_BLOCK_PHY0 = 1,
103 HW90_BLOCK_PHY1 = 2,
104 HW90_BLOCK_RF = 3,
105 HW90_BLOCK_MAXIMUM = 4,
106};
107
108enum baseband_config_type {
109 BASEBAND_CONFIG_PHY_REG = 0,
110 BASEBAND_CONFIG_AGC_TAB = 1,
111};
112
113enum ra_offset_area {
114 RA_OFFSET_LEGACY_OFDM1,
115 RA_OFFSET_LEGACY_OFDM2,
116 RA_OFFSET_HT_OFDM1,
117 RA_OFFSET_HT_OFDM2,
118 RA_OFFSET_HT_OFDM3,
119 RA_OFFSET_HT_OFDM4,
120 RA_OFFSET_HT_CCK,
121};
122
123enum antenna_path {
124 ANTENNA_NONE,
125 ANTENNA_D,
126 ANTENNA_C,
127 ANTENNA_CD,
128 ANTENNA_B,
129 ANTENNA_BD,
130 ANTENNA_BC,
131 ANTENNA_BCD,
132 ANTENNA_A,
133 ANTENNA_AD,
134 ANTENNA_AC,
135 ANTENNA_ACD,
136 ANTENNA_AB,
137 ANTENNA_ABD,
138 ANTENNA_ABC,
139 ANTENNA_ABCD
140};
141
142struct r_antenna_select_ofdm {
143 u32 r_tx_antenna:4;
144 u32 r_ant_l:4;
145 u32 r_ant_non_ht:4;
146 u32 r_ant_ht1:4;
147 u32 r_ant_ht2:4;
148 u32 r_ant_ht_s1:4;
149 u32 r_ant_non_ht_s1:4;
150 u32 ofdm_txsc:2;
151 u32 reserved:2;
152};
153
154struct r_antenna_select_cck {
155 u8 r_cckrx_enable_2:2;
156 u8 r_cckrx_enable:2;
157 u8 r_ccktx_enable:4;
158};
159
160struct efuse_contents {
161 u8 mac_addr[ETH_ALEN];
162 u8 cck_tx_power_idx[6];
163 u8 ht40_1s_tx_power_idx[6];
164 u8 ht40_2s_tx_power_idx_diff[3];
165 u8 ht20_tx_power_idx_diff[3];
166 u8 ofdm_tx_power_idx_diff[3];
167 u8 ht40_max_power_offset[3];
168 u8 ht20_max_power_offset[3];
169 u8 channel_plan;
170 u8 thermal_meter;
171 u8 rf_option[5];
172 u8 version;
173 u8 oem_id;
174 u8 regulatory;
175};
176
177struct tx_power_struct {
178 u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
179 u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
180 u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
181 u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
182 u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
183 u8 legacy_ht_txpowerdiff;
184 u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
185 u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
186 u8 pwrgroup_cnt;
187 u32 mcs_original_offset[4][16];
188};
189
190bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
191u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw,
192 u32 regaddr, u32 bitmask);
193void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
194 u32 regaddr, u32 bitmask, u32 data);
195u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
196 enum radio_path rfpath, u32 regaddr,
197 u32 bitmask);
198extern void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
199 enum radio_path rfpath, u32 regaddr,
200 u32 bitmask, u32 data);
201bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
202bool rtl92ce_phy_bb_config(struct ieee80211_hw *hw);
203bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
204bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
205 enum radio_path rfpath);
206void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
207void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw,
208 long *powerlevel);
209void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
210bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
211 long power_indbm);
212void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw,
213 u8 operation);
214void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
215 enum nl80211_channel_type ch_type);
216void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
217u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
218void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
219void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw,
220 u16 beaconinterval);
221void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
222void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
223void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t);
224void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
225bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
226 enum radio_path rfpath);
227bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
228 u32 rfpath);
229bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
230bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
231 enum rf_pwrstate rfpwr_state);
232void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
233bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
234void rtl92c_phy_set_io(struct ieee80211_hw *hw);
235void rtl92c_bb_block_on(struct ieee80211_hw *hw);
236u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
237 enum radio_path rfpath, u32 offset);
238u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
239 enum radio_path rfpath, u32 offset);
240u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
241void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
242 enum radio_path rfpath, u32 offset,
243 u32 data);
244void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
245 enum radio_path rfpath, u32 offset,
246 u32 data);
247void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
248 u32 regaddr, u32 bitmask,
249 u32 data);
250bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
251void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
252bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
253void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
254bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
255 enum rf_pwrstate rfpwr_state);
256bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
257 u8 configtype);
258bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
259 u8 configtype);
260void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
261
262#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
new file mode 100644
index 000000000000..598cecc63f41
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
@@ -0,0 +1,2090 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_REG_H__
31#define __RTL92C_REG_H__
32
33#define REG_SYS_ISO_CTRL 0x0000
34#define REG_SYS_FUNC_EN 0x0002
35#define REG_APS_FSMCO 0x0004
36#define REG_SYS_CLKR 0x0008
37#define REG_9346CR 0x000A
38#define REG_EE_VPD 0x000C
39#define REG_AFE_MISC 0x0010
40#define REG_SPS0_CTRL 0x0011
41#define REG_SPS_OCP_CFG 0x0018
42#define REG_RSV_CTRL 0x001C
43#define REG_RF_CTRL 0x001F
44#define REG_LDOA15_CTRL 0x0020
45#define REG_LDOV12D_CTRL 0x0021
46#define REG_LDOHCI12_CTRL 0x0022
47#define REG_LPLDO_CTRL 0x0023
48#define REG_AFE_XTAL_CTRL 0x0024
49#define REG_AFE_PLL_CTRL 0x0028
50#define REG_EFUSE_CTRL 0x0030
51#define REG_EFUSE_TEST 0x0034
52#define REG_PWR_DATA 0x0038
53#define REG_CAL_TIMER 0x003C
54#define REG_ACLK_MON 0x003E
55#define REG_GPIO_MUXCFG 0x0040
56#define REG_GPIO_IO_SEL 0x0042
57#define REG_MAC_PINMUX_CFG 0x0043
58#define REG_GPIO_PIN_CTRL 0x0044
59#define REG_GPIO_INTM 0x0048
60#define REG_LEDCFG0 0x004C
61#define REG_LEDCFG1 0x004D
62#define REG_LEDCFG2 0x004E
63#define REG_LEDCFG3 0x004F
64#define REG_FSIMR 0x0050
65#define REG_FSISR 0x0054
66#define REG_HSIMR 0x0058
67#define REG_HSISR 0x005c
68
69/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
70#define REG_GPIO_PIN_CTRL_2 0x0060
71/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
72#define REG_GPIO_IO_SEL_2 0x0062
73/* RTL8723 WIFI/BT/GPS Multi-Function control source. */
74#define REG_MULTI_FUNC_CTRL 0x0068
75
76#define REG_MCUFWDL 0x0080
77
78#define REG_HMEBOX_EXT_0 0x0088
79#define REG_HMEBOX_EXT_1 0x008A
80#define REG_HMEBOX_EXT_2 0x008C
81#define REG_HMEBOX_EXT_3 0x008E
82
83#define REG_BIST_SCAN 0x00D0
84#define REG_BIST_RPT 0x00D4
85#define REG_BIST_ROM_RPT 0x00D8
86#define REG_USB_SIE_INTF 0x00E0
87#define REG_PCIE_MIO_INTF 0x00E4
88#define REG_PCIE_MIO_INTD 0x00E8
89#define REG_HPON_FSM 0x00EC
90#define REG_SYS_CFG 0x00F0
91#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only.*/
92
93#define REG_CR 0x0100
94#define REG_PBP 0x0104
95#define REG_TRXDMA_CTRL 0x010C
96#define REG_TRXFF_BNDY 0x0114
97#define REG_TRXFF_STATUS 0x0118
98#define REG_RXFF_PTR 0x011C
99#define REG_HIMR 0x0120
100#define REG_HISR 0x0124
101#define REG_HIMRE 0x0128
102#define REG_HISRE 0x012C
103#define REG_CPWM 0x012F
104#define REG_FWIMR 0x0130
105#define REG_FWISR 0x0134
106#define REG_PKTBUF_DBG_CTRL 0x0140
107#define REG_PKTBUF_DBG_DATA_L 0x0144
108#define REG_PKTBUF_DBG_DATA_H 0x0148
109
110#define REG_TC0_CTRL 0x0150
111#define REG_TC1_CTRL 0x0154
112#define REG_TC2_CTRL 0x0158
113#define REG_TC3_CTRL 0x015C
114#define REG_TC4_CTRL 0x0160
115#define REG_TCUNIT_BASE 0x0164
116#define REG_MBIST_START 0x0174
117#define REG_MBIST_DONE 0x0178
118#define REG_MBIST_FAIL 0x017C
119#define REG_C2HEVT_MSG_NORMAL 0x01A0
120#define REG_C2HEVT_MSG_TEST 0x01B8
121#define REG_C2HEVT_CLEAR 0x01BF
122#define REG_MCUTST_1 0x01c0
123#define REG_FMETHR 0x01C8
124#define REG_HMETFR 0x01CC
125#define REG_HMEBOX_0 0x01D0
126#define REG_HMEBOX_1 0x01D4
127#define REG_HMEBOX_2 0x01D8
128#define REG_HMEBOX_3 0x01DC
129
130#define REG_LLT_INIT 0x01E0
131#define REG_BB_ACCEESS_CTRL 0x01E8
132#define REG_BB_ACCESS_DATA 0x01EC
133
134#define REG_RQPN 0x0200
135#define REG_FIFOPAGE 0x0204
136#define REG_TDECTRL 0x0208
137#define REG_TXDMA_OFFSET_CHK 0x020C
138#define REG_TXDMA_STATUS 0x0210
139#define REG_RQPN_NPQ 0x0214
140
141#define REG_RXDMA_AGG_PG_TH 0x0280
142#define REG_RXPKT_NUM 0x0284
143#define REG_RXDMA_STATUS 0x0288
144
145#define REG_PCIE_CTRL_REG 0x0300
146#define REG_INT_MIG 0x0304
147#define REG_BCNQ_DESA 0x0308
148#define REG_HQ_DESA 0x0310
149#define REG_MGQ_DESA 0x0318
150#define REG_VOQ_DESA 0x0320
151#define REG_VIQ_DESA 0x0328
152#define REG_BEQ_DESA 0x0330
153#define REG_BKQ_DESA 0x0338
154#define REG_RX_DESA 0x0340
155#define REG_DBI 0x0348
156#define REG_MDIO 0x0354
157#define REG_DBG_SEL 0x0360
158#define REG_PCIE_HRPWM 0x0361
159#define REG_PCIE_HCPWM 0x0363
160#define REG_UART_CTRL 0x0364
161#define REG_UART_TX_DESA 0x0370
162#define REG_UART_RX_DESA 0x0378
163
164#define REG_HDAQ_DESA_NODEF 0x0000
165#define REG_CMDQ_DESA_NODEF 0x0000
166
167#define REG_VOQ_INFORMATION 0x0400
168#define REG_VIQ_INFORMATION 0x0404
169#define REG_BEQ_INFORMATION 0x0408
170#define REG_BKQ_INFORMATION 0x040C
171#define REG_MGQ_INFORMATION 0x0410
172#define REG_HGQ_INFORMATION 0x0414
173#define REG_BCNQ_INFORMATION 0x0418
174
175#define REG_CPU_MGQ_INFORMATION 0x041C
176#define REG_FWHW_TXQ_CTRL 0x0420
177#define REG_HWSEQ_CTRL 0x0423
178#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
179#define REG_TXPKTBUF_MGQ_BDNY 0x0425
180#define REG_MULTI_BCNQ_EN 0x0426
181#define REG_MULTI_BCNQ_OFFSET 0x0427
182#define REG_SPEC_SIFS 0x0428
183#define REG_RL 0x042A
184#define REG_DARFRC 0x0430
185#define REG_RARFRC 0x0438
186#define REG_RRSR 0x0440
187#define REG_ARFR0 0x0444
188#define REG_ARFR1 0x0448
189#define REG_ARFR2 0x044C
190#define REG_ARFR3 0x0450
191#define REG_AGGLEN_LMT 0x0458
192#define REG_AMPDU_MIN_SPACE 0x045C
193#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
194#define REG_FAST_EDCA_CTRL 0x0460
195#define REG_RD_RESP_PKT_TH 0x0463
196#define REG_INIRTS_RATE_SEL 0x0480
197#define REG_INIDATA_RATE_SEL 0x0484
198#define REG_POWER_STATUS 0x04A4
199#define REG_POWER_STAGE1 0x04B4
200#define REG_POWER_STAGE2 0x04B8
201#define REG_PKT_LIFE_TIME 0x04C0
202#define REG_STBC_SETTING 0x04C4
203#define REG_PROT_MODE_CTRL 0x04C8
204#define REG_BAR_MODE_CTRL 0x04CC
205#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
206#define REG_NQOS_SEQ 0x04DC
207#define REG_QOS_SEQ 0x04DE
208#define REG_NEED_CPU_HANDLE 0x04E0
209#define REG_PKT_LOSE_RPT 0x04E1
210#define REG_PTCL_ERR_STATUS 0x04E2
211#define REG_DUMMY 0x04FC
212
213#define REG_EDCA_VO_PARAM 0x0500
214#define REG_EDCA_VI_PARAM 0x0504
215#define REG_EDCA_BE_PARAM 0x0508
216#define REG_EDCA_BK_PARAM 0x050C
217#define REG_BCNTCFG 0x0510
218#define REG_PIFS 0x0512
219#define REG_RDG_PIFS 0x0513
220#define REG_SIFS_CTX 0x0514
221#define REG_SIFS_TRX 0x0516
222#define REG_SIFS_CCK 0x0514
223#define REG_SIFS_OFDM 0x0516
224#define REG_AGGR_BREAK_TIME 0x051A
225#define REG_SLOT 0x051B
226#define REG_TX_PTCL_CTRL 0x0520
227#define REG_TXPAUSE 0x0522
228#define REG_DIS_TXREQ_CLR 0x0523
229#define REG_RD_CTRL 0x0524
230#define REG_TBTT_PROHIBIT 0x0540
231#define REG_RD_NAV_NXT 0x0544
232#define REG_NAV_PROT_LEN 0x0546
233#define REG_BCN_CTRL 0x0550
234#define REG_USTIME_TSF 0x0551
235#define REG_MBID_NUM 0x0552
236#define REG_DUAL_TSF_RST 0x0553
237#define REG_BCN_INTERVAL 0x0554
238#define REG_MBSSID_BCN_SPACE 0x0554
239#define REG_DRVERLYINT 0x0558
240#define REG_BCNDMATIM 0x0559
241#define REG_ATIMWND 0x055A
242#define REG_BCN_MAX_ERR 0x055D
243#define REG_RXTSF_OFFSET_CCK 0x055E
244#define REG_RXTSF_OFFSET_OFDM 0x055F
245#define REG_TSFTR 0x0560
246#define REG_INIT_TSFTR 0x0564
247#define REG_PSTIMER 0x0580
248#define REG_TIMER0 0x0584
249#define REG_TIMER1 0x0588
250#define REG_ACMHWCTRL 0x05C0
251#define REG_ACMRSTCTRL 0x05C1
252#define REG_ACMAVG 0x05C2
253#define REG_VO_ADMTIME 0x05C4
254#define REG_VI_ADMTIME 0x05C6
255#define REG_BE_ADMTIME 0x05C8
256#define REG_EDCA_RANDOM_GEN 0x05CC
257#define REG_SCH_TXCMD 0x05D0
258
259#define REG_APSD_CTRL 0x0600
260#define REG_BWOPMODE 0x0603
261#define REG_TCR 0x0604
262#define REG_RCR 0x0608
263#define REG_RX_PKT_LIMIT 0x060C
264#define REG_RX_DLK_TIME 0x060D
265#define REG_RX_DRVINFO_SZ 0x060F
266
267#define REG_MACID 0x0610
268#define REG_BSSID 0x0618
269#define REG_MAR 0x0620
270#define REG_MBIDCAMCFG 0x0628
271
272#define REG_USTIME_EDCA 0x0638
273#define REG_MAC_SPEC_SIFS 0x063A
274#define REG_RESP_SIFS_CCK 0x063C
275#define REG_RESP_SIFS_OFDM 0x063E
276/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
277#define REG_R2T_SIFS 0x063C
278/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
279#define REG_T2T_SIFS 0x063E
280#define REG_ACKTO 0x0640
281#define REG_CTS2TO 0x0641
282#define REG_EIFS 0x0642
283
284#define REG_NAV_CTRL 0x0650
285#define REG_BACAMCMD 0x0654
286#define REG_BACAMCONTENT 0x0658
287#define REG_LBDLY 0x0660
288#define REG_FWDLY 0x0661
289#define REG_RXERR_RPT 0x0664
290#define REG_WMAC_TRXPTCL_CTL 0x0668
291
292#define REG_CAMCMD 0x0670
293#define REG_CAMWRITE 0x0674
294#define REG_CAMREAD 0x0678
295#define REG_CAMDBG 0x067C
296#define REG_SECCFG 0x0680
297
298#define REG_WOW_CTRL 0x0690
299#define REG_PSSTATUS 0x0691
300#define REG_PS_RX_INFO 0x0692
301#define REG_LPNAV_CTRL 0x0694
302#define REG_WKFMCAM_CMD 0x0698
303#define REG_WKFMCAM_RWD 0x069C
304#define REG_RXFLTMAP0 0x06A0
305#define REG_RXFLTMAP1 0x06A2
306#define REG_RXFLTMAP2 0x06A4
307#define REG_BCN_PSR_RPT 0x06A8
308#define REG_CALB32K_CTRL 0x06AC
309#define REG_PKT_MON_CTRL 0x06B4
310#define REG_BT_COEX_TABLE 0x06C0
311#define REG_WMAC_RESP_TXINFO 0x06D8
312
313#define REG_USB_INFO 0xFE17
314#define REG_USB_SPECIAL_OPTION 0xFE55
315#define REG_USB_DMA_AGG_TO 0xFE5B
316#define REG_USB_AGG_TO 0xFE5C
317#define REG_USB_AGG_TH 0xFE5D
318
319#define REG_TEST_USB_TXQS 0xFE48
320#define REG_TEST_SIE_VID 0xFE60
321#define REG_TEST_SIE_PID 0xFE62
322#define REG_TEST_SIE_OPTIONAL 0xFE64
323#define REG_TEST_SIE_CHIRP_K 0xFE65
324#define REG_TEST_SIE_PHY 0xFE66
325#define REG_TEST_SIE_MAC_ADDR 0xFE70
326#define REG_TEST_SIE_STRING 0xFE80
327
328#define REG_NORMAL_SIE_VID 0xFE60
329#define REG_NORMAL_SIE_PID 0xFE62
330#define REG_NORMAL_SIE_OPTIONAL 0xFE64
331#define REG_NORMAL_SIE_EP 0xFE65
332#define REG_NORMAL_SIE_PHY 0xFE68
333#define REG_NORMAL_SIE_MAC_ADDR 0xFE70
334#define REG_NORMAL_SIE_STRING 0xFE80
335
336#define CR9346 REG_9346CR
337#define MSR (REG_CR + 2)
338#define ISR REG_HISR
339#define TSFR REG_TSFTR
340
341#define MACIDR0 REG_MACID
342#define MACIDR4 (REG_MACID + 4)
343
344#define PBP REG_PBP
345
346#define IDR0 MACIDR0
347#define IDR4 MACIDR4
348
349#define UNUSED_REGISTER 0x1BF
350#define DCAM UNUSED_REGISTER
351#define PSR UNUSED_REGISTER
352#define BBADDR UNUSED_REGISTER
353#define PHYDATAR UNUSED_REGISTER
354
355#define INVALID_BBRF_VALUE 0x12345678
356
357#define MAX_MSS_DENSITY_2T 0x13
358#define MAX_MSS_DENSITY_1T 0x0A
359
360#define CMDEEPROM_EN BIT(5)
361#define CMDEEPROM_SEL BIT(4)
362#define CMD9346CR_9356SEL BIT(4)
363#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL)
364#define AUTOLOAD_EFUSE CMDEEPROM_EN
365
366#define GPIOSEL_GPIO 0
367#define GPIOSEL_ENBT BIT(5)
368
369#define GPIO_IN REG_GPIO_PIN_CTRL
370#define GPIO_OUT (REG_GPIO_PIN_CTRL+1)
371#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)
372#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
373
374#define MSR_NOLINK 0x00
375#define MSR_ADHOC 0x01
376#define MSR_INFRA 0x02
377#define MSR_AP 0x03
378
379#define RRSR_RSC_OFFSET 21
380#define RRSR_SHORT_OFFSET 23
381#define RRSR_RSC_BW_40M 0x600000
382#define RRSR_RSC_UPSUBCHNL 0x400000
383#define RRSR_RSC_LOWSUBCHNL 0x200000
384#define RRSR_SHORT 0x800000
385#define RRSR_1M BIT(0)
386#define RRSR_2M BIT(1)
387#define RRSR_5_5M BIT(2)
388#define RRSR_11M BIT(3)
389#define RRSR_6M BIT(4)
390#define RRSR_9M BIT(5)
391#define RRSR_12M BIT(6)
392#define RRSR_18M BIT(7)
393#define RRSR_24M BIT(8)
394#define RRSR_36M BIT(9)
395#define RRSR_48M BIT(10)
396#define RRSR_54M BIT(11)
397#define RRSR_MCS0 BIT(12)
398#define RRSR_MCS1 BIT(13)
399#define RRSR_MCS2 BIT(14)
400#define RRSR_MCS3 BIT(15)
401#define RRSR_MCS4 BIT(16)
402#define RRSR_MCS5 BIT(17)
403#define RRSR_MCS6 BIT(18)
404#define RRSR_MCS7 BIT(19)
405#define BRSR_ACKSHORTPMB BIT(23)
406
407#define RATR_1M 0x00000001
408#define RATR_2M 0x00000002
409#define RATR_55M 0x00000004
410#define RATR_11M 0x00000008
411#define RATR_6M 0x00000010
412#define RATR_9M 0x00000020
413#define RATR_12M 0x00000040
414#define RATR_18M 0x00000080
415#define RATR_24M 0x00000100
416#define RATR_36M 0x00000200
417#define RATR_48M 0x00000400
418#define RATR_54M 0x00000800
419#define RATR_MCS0 0x00001000
420#define RATR_MCS1 0x00002000
421#define RATR_MCS2 0x00004000
422#define RATR_MCS3 0x00008000
423#define RATR_MCS4 0x00010000
424#define RATR_MCS5 0x00020000
425#define RATR_MCS6 0x00040000
426#define RATR_MCS7 0x00080000
427#define RATR_MCS8 0x00100000
428#define RATR_MCS9 0x00200000
429#define RATR_MCS10 0x00400000
430#define RATR_MCS11 0x00800000
431#define RATR_MCS12 0x01000000
432#define RATR_MCS13 0x02000000
433#define RATR_MCS14 0x04000000
434#define RATR_MCS15 0x08000000
435
436#define RATE_1M BIT(0)
437#define RATE_2M BIT(1)
438#define RATE_5_5M BIT(2)
439#define RATE_11M BIT(3)
440#define RATE_6M BIT(4)
441#define RATE_9M BIT(5)
442#define RATE_12M BIT(6)
443#define RATE_18M BIT(7)
444#define RATE_24M BIT(8)
445#define RATE_36M BIT(9)
446#define RATE_48M BIT(10)
447#define RATE_54M BIT(11)
448#define RATE_MCS0 BIT(12)
449#define RATE_MCS1 BIT(13)
450#define RATE_MCS2 BIT(14)
451#define RATE_MCS3 BIT(15)
452#define RATE_MCS4 BIT(16)
453#define RATE_MCS5 BIT(17)
454#define RATE_MCS6 BIT(18)
455#define RATE_MCS7 BIT(19)
456#define RATE_MCS8 BIT(20)
457#define RATE_MCS9 BIT(21)
458#define RATE_MCS10 BIT(22)
459#define RATE_MCS11 BIT(23)
460#define RATE_MCS12 BIT(24)
461#define RATE_MCS13 BIT(25)
462#define RATE_MCS14 BIT(26)
463#define RATE_MCS15 BIT(27)
464
465#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
466#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M \
467 | RATR_24M | RATR_36M | RATR_48M | RATR_54M)
468#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
469 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
470 RATR_MCS6 | RATR_MCS7)
471#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
472 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
473 RATR_MCS14 | RATR_MCS15)
474
475#define BW_OPMODE_20MHZ BIT(2)
476#define BW_OPMODE_5G BIT(1)
477#define BW_OPMODE_11J BIT(0)
478
479#define CAM_VALID BIT(15)
480#define CAM_NOTVALID 0x0000
481#define CAM_USEDK BIT(5)
482
483#define CAM_NONE 0x0
484#define CAM_WEP40 0x01
485#define CAM_TKIP 0x02
486#define CAM_AES 0x04
487#define CAM_WEP104 0x05
488
489#define TOTAL_CAM_ENTRY 32
490#define HALF_CAM_ENTRY 16
491
492#define CAM_WRITE BIT(16)
493#define CAM_READ 0x00000000
494#define CAM_POLLINIG BIT(31)
495
496#define SCR_USEDK 0x01
497#define SCR_TXSEC_ENABLE 0x02
498#define SCR_RXSEC_ENABLE 0x04
499
500#define WOW_PMEN BIT(0)
501#define WOW_WOMEN BIT(1)
502#define WOW_MAGIC BIT(2)
503#define WOW_UWF BIT(3)
504
505#define IMR8190_DISABLED 0x0
506#define IMR_BCNDMAINT6 BIT(31)
507#define IMR_BCNDMAINT5 BIT(30)
508#define IMR_BCNDMAINT4 BIT(29)
509#define IMR_BCNDMAINT3 BIT(28)
510#define IMR_BCNDMAINT2 BIT(27)
511#define IMR_BCNDMAINT1 BIT(26)
512#define IMR_BCNDOK8 BIT(25)
513#define IMR_BCNDOK7 BIT(24)
514#define IMR_BCNDOK6 BIT(23)
515#define IMR_BCNDOK5 BIT(22)
516#define IMR_BCNDOK4 BIT(21)
517#define IMR_BCNDOK3 BIT(20)
518#define IMR_BCNDOK2 BIT(19)
519#define IMR_BCNDOK1 BIT(18)
520#define IMR_TIMEOUT2 BIT(17)
521#define IMR_TIMEOUT1 BIT(16)
522#define IMR_TXFOVW BIT(15)
523#define IMR_PSTIMEOUT BIT(14)
524#define IMR_BCNINT BIT(13)
525#define IMR_RXFOVW BIT(12)
526#define IMR_RDU BIT(11)
527#define IMR_ATIMEND BIT(10)
528#define IMR_BDOK BIT(9)
529#define IMR_HIGHDOK BIT(8)
530#define IMR_TBDOK BIT(7)
531#define IMR_MGNTDOK BIT(6)
532#define IMR_TBDER BIT(5)
533#define IMR_BKDOK BIT(4)
534#define IMR_BEDOK BIT(3)
535#define IMR_VIDOK BIT(2)
536#define IMR_VODOK BIT(1)
537#define IMR_ROK BIT(0)
538
539#define IMR_TXERR BIT(11)
540#define IMR_RXERR BIT(10)
541#define IMR_C2HCMD BIT(9)
542#define IMR_CPWM BIT(8)
543#define IMR_OCPINT BIT(1)
544#define IMR_WLANOFF BIT(0)
545
546#define EFUSE_REAL_CONTENT_LEN 512
547
548#define EEPROM_DEFAULT_TSSI 0x0
549#define EEPROM_DEFAULT_TXPOWERDIFF 0x0
550#define EEPROM_DEFAULT_CRYSTALCAP 0x5
551#define EEPROM_DEFAULT_BOARDTYPE 0x02
552#define EEPROM_DEFAULT_TXPOWER 0x1010
553#define EEPROM_DEFAULT_HT2T_TXPWR 0x10
554
555#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
556#define EEPROM_DEFAULT_THERMALMETER 0x12
557#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0
558#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5
559#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22
560#define EEPROM_DEFAULT_HT40_2SDIFF 0x0
561#define EEPROM_DEFAULT_HT20_DIFF 2
562#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
563#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
564#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
565
566#define RF_OPTION1 0x79
567#define RF_OPTION2 0x7A
568#define RF_OPTION3 0x7B
569#define RF_OPTION4 0x7C
570
571#define EEPROM_DEFAULT_PID 0x1234
572#define EEPROM_DEFAULT_VID 0x5678
573#define EEPROM_DEFAULT_CUSTOMERID 0xAB
574#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD
575#define EEPROM_DEFAULT_VERSION 0
576
577#define EEPROM_CHANNEL_PLAN_FCC 0x0
578#define EEPROM_CHANNEL_PLAN_IC 0x1
579#define EEPROM_CHANNEL_PLAN_ETSI 0x2
580#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
581#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
582#define EEPROM_CHANNEL_PLAN_MKK 0x5
583#define EEPROM_CHANNEL_PLAN_MKK1 0x6
584#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
585#define EEPROM_CHANNEL_PLAN_TELEC 0x8
586#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
587#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
588#define EEPROM_CHANNEL_PLAN_NCC 0xB
589#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
590
591#define EEPROM_CID_DEFAULT 0x0
592#define EEPROM_CID_TOSHIBA 0x4
593#define EEPROM_CID_CCX 0x10
594#define EEPROM_CID_QMI 0x0D
595#define EEPROM_CID_WHQL 0xFE
596
597#define RTL8192_EEPROM_ID 0x8129
598
599#define RTL8190_EEPROM_ID 0x8129
600#define EEPROM_HPON 0x02
601#define EEPROM_CLK 0x06
602#define EEPROM_TESTR 0x08
603
604#define EEPROM_VID 0x0A
605#define EEPROM_DID 0x0C
606#define EEPROM_SVID 0x0E
607#define EEPROM_SMID 0x10
608
609#define EEPROM_MAC_ADDR 0x16
610
611#define EEPROM_CCK_TX_PWR_INX 0x5A
612#define EEPROM_HT40_1S_TX_PWR_INX 0x60
613#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66
614#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69
615#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C
616#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F
617#define EEPROM_HT20_MAX_PWR_OFFSET 0x72
618
619#define EEPROM_TSSI_A 0x76
620#define EEPROM_TSSI_B 0x77
621#define EEPROM_THERMAL_METER 0x78
622#define EEPROM_XTAL_K 0x78
623#define EEPROM_RF_OPT1 0x79
624#define EEPROM_RF_OPT2 0x7A
625#define EEPROM_RF_OPT3 0x7B
626#define EEPROM_RF_OPT4 0x7C
627#define EEPROM_CHANNEL_PLAN 0x7D
628#define EEPROM_VERSION 0x7E
629#define EEPROM_CUSTOMER_ID 0x7F
630
631#define EEPROM_PWRDIFF 0x54
632
633#define EEPROM_TXPOWERCCK 0x5A
634#define EEPROM_TXPOWERHT40_1S 0x60
635#define EEPROM_TXPOWERHT40_2SDIFF 0x66
636#define EEPROM_TXPOWERHT20DIFF 0x69
637#define EEPROM_TXPOWER_OFDMDIFF 0x6C
638
639#define EEPROM_TXPWR_GROUP 0x6F
640
641#define EEPROM_TSSI_A 0x76
642#define EEPROM_TSSI_B 0x77
643#define EEPROM_THERMAL_METER 0x78
644
645#define EEPROM_CHANNELPLAN 0x75
646
647#define RF_OPTION1 0x79
648#define RF_OPTION2 0x7A
649#define RF_OPTION3 0x7B
650#define RF_OPTION4 0x7C
651
652#define STOPBECON BIT(6)
653#define STOPHIGHT BIT(5)
654#define STOPMGT BIT(4)
655#define STOPVO BIT(3)
656#define STOPVI BIT(2)
657#define STOPBE BIT(1)
658#define STOPBK BIT(0)
659
660#define RCR_APPFCS BIT(31)
661#define RCR_APP_FCS BIT(31)
662#define RCR_APP_MIC BIT(30)
663#define RCR_APP_ICV BIT(29)
664#define RCR_APP_PHYSTS BIT(28)
665#define RCR_APP_PHYST_RXFF BIT(28)
666#define RCR_APP_BA_SSN BIT(27)
667#define RCR_ENMBID BIT(24)
668#define RCR_LSIGEN BIT(23)
669#define RCR_MFBEN BIT(22)
670#define RCR_HTC_LOC_CTRL BIT(14)
671#define RCR_AMF BIT(13)
672#define RCR_ACF BIT(12)
673#define RCR_ADF BIT(11)
674#define RCR_AICV BIT(9)
675#define RCR_ACRC32 BIT(8)
676#define RCR_CBSSID_BCN BIT(7)
677#define RCR_CBSSID_DATA BIT(6)
678#define RCR_CBSSID RCR_CBSSID_DATA
679#define RCR_APWRMGT BIT(5)
680#define RCR_ADD3 BIT(4)
681#define RCR_AB BIT(3)
682#define RCR_AM BIT(2)
683#define RCR_APM BIT(1)
684#define RCR_AAP BIT(0)
685#define RCR_MXDMA_OFFSET 8
686#define RCR_FIFO_OFFSET 13
687
688#define RSV_CTRL 0x001C
689#define RD_CTRL 0x0524
690
691#define REG_USB_INFO 0xFE17
692#define REG_USB_SPECIAL_OPTION 0xFE55
693
694#define REG_USB_DMA_AGG_TO 0xFE5B
695#define REG_USB_AGG_TO 0xFE5C
696#define REG_USB_AGG_TH 0xFE5D
697
698#define REG_USB_VID 0xFE60
699#define REG_USB_PID 0xFE62
700#define REG_USB_OPTIONAL 0xFE64
701#define REG_USB_CHIRP_K 0xFE65
702#define REG_USB_PHY 0xFE66
703#define REG_USB_MAC_ADDR 0xFE70
704#define REG_USB_HRPWM 0xFE58
705#define REG_USB_HCPWM 0xFE57
706
707#define SW18_FPWM BIT(3)
708
709#define ISO_MD2PP BIT(0)
710#define ISO_UA2USB BIT(1)
711#define ISO_UD2CORE BIT(2)
712#define ISO_PA2PCIE BIT(3)
713#define ISO_PD2CORE BIT(4)
714#define ISO_IP2MAC BIT(5)
715#define ISO_DIOP BIT(6)
716#define ISO_DIOE BIT(7)
717#define ISO_EB2CORE BIT(8)
718#define ISO_DIOR BIT(9)
719
720#define PWC_EV25V BIT(14)
721#define PWC_EV12V BIT(15)
722
723#define FEN_BBRSTB BIT(0)
724#define FEN_BB_GLB_RSTn BIT(1)
725#define FEN_USBA BIT(2)
726#define FEN_UPLL BIT(3)
727#define FEN_USBD BIT(4)
728#define FEN_DIO_PCIE BIT(5)
729#define FEN_PCIEA BIT(6)
730#define FEN_PPLL BIT(7)
731#define FEN_PCIED BIT(8)
732#define FEN_DIOE BIT(9)
733#define FEN_CPUEN BIT(10)
734#define FEN_DCORE BIT(11)
735#define FEN_ELDR BIT(12)
736#define FEN_DIO_RF BIT(13)
737#define FEN_HWPDN BIT(14)
738#define FEN_MREGEN BIT(15)
739
740#define PFM_LDALL BIT(0)
741#define PFM_ALDN BIT(1)
742#define PFM_LDKP BIT(2)
743#define PFM_WOWL BIT(3)
744#define EnPDN BIT(4)
745#define PDN_PL BIT(5)
746#define APFM_ONMAC BIT(8)
747#define APFM_OFF BIT(9)
748#define APFM_RSM BIT(10)
749#define AFSM_HSUS BIT(11)
750#define AFSM_PCIE BIT(12)
751#define APDM_MAC BIT(13)
752#define APDM_HOST BIT(14)
753#define APDM_HPDN BIT(15)
754#define RDY_MACON BIT(16)
755#define SUS_HOST BIT(17)
756#define ROP_ALD BIT(20)
757#define ROP_PWR BIT(21)
758#define ROP_SPS BIT(22)
759#define SOP_MRST BIT(25)
760#define SOP_FUSE BIT(26)
761#define SOP_ABG BIT(27)
762#define SOP_AMB BIT(28)
763#define SOP_RCK BIT(29)
764#define SOP_A8M BIT(30)
765#define XOP_BTCK BIT(31)
766
767#define ANAD16V_EN BIT(0)
768#define ANA8M BIT(1)
769#define MACSLP BIT(4)
770#define LOADER_CLK_EN BIT(5)
771#define _80M_SSC_DIS BIT(7)
772#define _80M_SSC_EN_HO BIT(8)
773#define PHY_SSC_RSTB BIT(9)
774#define SEC_CLK_EN BIT(10)
775#define MAC_CLK_EN BIT(11)
776#define SYS_CLK_EN BIT(12)
777#define RING_CLK_EN BIT(13)
778
779#define BOOT_FROM_EEPROM BIT(4)
780#define EEPROM_EN BIT(5)
781
782#define AFE_BGEN BIT(0)
783#define AFE_MBEN BIT(1)
784#define MAC_ID_EN BIT(7)
785
786#define WLOCK_ALL BIT(0)
787#define WLOCK_00 BIT(1)
788#define WLOCK_04 BIT(2)
789#define WLOCK_08 BIT(3)
790#define WLOCK_40 BIT(4)
791#define R_DIS_PRST_0 BIT(5)
792#define R_DIS_PRST_1 BIT(6)
793#define LOCK_ALL_EN BIT(7)
794
795#define RF_EN BIT(0)
796#define RF_RSTB BIT(1)
797#define RF_SDMRSTB BIT(2)
798
799#define LDA15_EN BIT(0)
800#define LDA15_STBY BIT(1)
801#define LDA15_OBUF BIT(2)
802#define LDA15_REG_VOS BIT(3)
803#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
804
805#define LDV12_EN BIT(0)
806#define LDV12_SDBY BIT(1)
807#define LPLDO_HSM BIT(2)
808#define LPLDO_LSM_DIS BIT(3)
809#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
810
811#define XTAL_EN BIT(0)
812#define XTAL_BSEL BIT(1)
813#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
814#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
815#define XTAL_GATE_USB BIT(8)
816#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
817#define XTAL_GATE_AFE BIT(11)
818#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
819#define XTAL_RF_GATE BIT(14)
820#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
821#define XTAL_GATE_DIG BIT(17)
822#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
823#define XTAL_BT_GATE BIT(20)
824#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
825#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
826
827#define CKDLY_AFE BIT(26)
828#define CKDLY_USB BIT(27)
829#define CKDLY_DIG BIT(28)
830#define CKDLY_BT BIT(29)
831
832#define APLL_EN BIT(0)
833#define APLL_320_EN BIT(1)
834#define APLL_FREF_SEL BIT(2)
835#define APLL_EDGE_SEL BIT(3)
836#define APLL_WDOGB BIT(4)
837#define APLL_LPFEN BIT(5)
838
839#define APLL_REF_CLK_13MHZ 0x1
840#define APLL_REF_CLK_19_2MHZ 0x2
841#define APLL_REF_CLK_20MHZ 0x3
842#define APLL_REF_CLK_25MHZ 0x4
843#define APLL_REF_CLK_26MHZ 0x5
844#define APLL_REF_CLK_38_4MHZ 0x6
845#define APLL_REF_CLK_40MHZ 0x7
846
847#define APLL_320EN BIT(14)
848#define APLL_80EN BIT(15)
849#define APLL_1MEN BIT(24)
850
851#define ALD_EN BIT(18)
852#define EF_PD BIT(19)
853#define EF_FLAG BIT(31)
854
855#define EF_TRPT BIT(7)
856#define LDOE25_EN BIT(31)
857
858#define RSM_EN BIT(0)
859#define Timer_EN BIT(4)
860
861#define TRSW0EN BIT(2)
862#define TRSW1EN BIT(3)
863#define EROM_EN BIT(4)
864#define EnBT BIT(5)
865#define EnUart BIT(8)
866#define Uart_910 BIT(9)
867#define EnPMAC BIT(10)
868#define SIC_SWRST BIT(11)
869#define EnSIC BIT(12)
870#define SIC_23 BIT(13)
871#define EnHDP BIT(14)
872#define SIC_LBK BIT(15)
873
874#define LED0PL BIT(4)
875#define LED1PL BIT(12)
876#define LED0DIS BIT(7)
877
878#define MCUFWDL_EN BIT(0)
879#define MCUFWDL_RDY BIT(1)
880#define FWDL_ChkSum_rpt BIT(2)
881#define MACINI_RDY BIT(3)
882#define BBINI_RDY BIT(4)
883#define RFINI_RDY BIT(5)
884#define WINTINI_RDY BIT(6)
885#define CPRST BIT(23)
886
887#define XCLK_VLD BIT(0)
888#define ACLK_VLD BIT(1)
889#define UCLK_VLD BIT(2)
890#define PCLK_VLD BIT(3)
891#define PCIRSTB BIT(4)
892#define V15_VLD BIT(5)
893#define TRP_B15V_EN BIT(7)
894#define SIC_IDLE BIT(8)
895#define BD_MAC2 BIT(9)
896#define BD_MAC1 BIT(10)
897#define IC_MACPHY_MODE BIT(11)
898#define BT_FUNC BIT(16)
899#define VENDOR_ID BIT(19)
900#define PAD_HWPD_IDN BIT(22)
901#define TRP_VAUX_EN BIT(23)
902#define TRP_BT_EN BIT(24)
903#define BD_PKG_SEL BIT(25)
904#define BD_HCI_SEL BIT(26)
905#define TYPE_ID BIT(27)
906#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
907
908#define CHIP_VER_RTL_MASK 0xF000
909#define CHIP_VER_RTL_SHIFT 12
910
911#define REG_LBMODE (REG_CR + 3)
912
913#define HCI_TXDMA_EN BIT(0)
914#define HCI_RXDMA_EN BIT(1)
915#define TXDMA_EN BIT(2)
916#define RXDMA_EN BIT(3)
917#define PROTOCOL_EN BIT(4)
918#define SCHEDULE_EN BIT(5)
919#define MACTXEN BIT(6)
920#define MACRXEN BIT(7)
921#define ENSWBCN BIT(8)
922#define ENSEC BIT(9)
923
924#define _NETTYPE(x) (((x) & 0x3) << 16)
925#define MASK_NETTYPE 0x30000
926#define NT_NO_LINK 0x0
927#define NT_LINK_AD_HOC 0x1
928#define NT_LINK_AP 0x2
929#define NT_AS_AP 0x3
930
931#define _LBMODE(x) (((x) & 0xF) << 24)
932#define MASK_LBMODE 0xF000000
933#define LOOPBACK_NORMAL 0x0
934#define LOOPBACK_IMMEDIATELY 0xB
935#define LOOPBACK_MAC_DELAY 0x3
936#define LOOPBACK_PHY 0x1
937#define LOOPBACK_DMA 0x7
938
939#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
940#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
941#define _PSRX_MASK 0xF
942#define _PSTX_MASK 0xF0
943#define _PSRX(x) (x)
944#define _PSTX(x) ((x) << 4)
945
946#define PBP_64 0x0
947#define PBP_128 0x1
948#define PBP_256 0x2
949#define PBP_512 0x3
950#define PBP_1024 0x4
951
952#define RXDMA_ARBBW_EN BIT(0)
953#define RXSHFT_EN BIT(1)
954#define RXDMA_AGG_EN BIT(2)
955#define QS_VO_QUEUE BIT(8)
956#define QS_VI_QUEUE BIT(9)
957#define QS_BE_QUEUE BIT(10)
958#define QS_BK_QUEUE BIT(11)
959#define QS_MANAGER_QUEUE BIT(12)
960#define QS_HIGH_QUEUE BIT(13)
961
962#define HQSEL_VOQ BIT(0)
963#define HQSEL_VIQ BIT(1)
964#define HQSEL_BEQ BIT(2)
965#define HQSEL_BKQ BIT(3)
966#define HQSEL_MGTQ BIT(4)
967#define HQSEL_HIQ BIT(5)
968
969#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
970#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
971#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
972#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)
973#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)
974#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)
975
976#define QUEUE_LOW 1
977#define QUEUE_NORMAL 2
978#define QUEUE_HIGH 3
979
980#define _LLT_NO_ACTIVE 0x0
981#define _LLT_WRITE_ACCESS 0x1
982#define _LLT_READ_ACCESS 0x2
983
984#define _LLT_INIT_DATA(x) ((x) & 0xFF)
985#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
986#define _LLT_OP(x) (((x) & 0x3) << 30)
987#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
988
989#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
990#define BB_WRITE_EN BIT(30)
991#define BB_READ_EN BIT(31)
992
993#define _HPQ(x) ((x) & 0xFF)
994#define _LPQ(x) (((x) & 0xFF) << 8)
995#define _PUBQ(x) (((x) & 0xFF) << 16)
996#define _NPQ(x) ((x) & 0xFF)
997
998#define HPQ_PUBLIC_DIS BIT(24)
999#define LPQ_PUBLIC_DIS BIT(25)
1000#define LD_RQPN BIT(31)
1001
1002#define BCN_VALID BIT(16)
1003#define BCN_HEAD(x) (((x) & 0xFF) << 8)
1004#define BCN_HEAD_MASK 0xFF00
1005
1006#define BLK_DESC_NUM_SHIFT 4
1007#define BLK_DESC_NUM_MASK 0xF
1008
1009#define DROP_DATA_EN BIT(9)
1010
1011#define EN_AMPDU_RTY_NEW BIT(7)
1012
1013#define _INIRTSMCS_SEL(x) ((x) & 0x3F)
1014
1015#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
1016#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
1017
1018#define RATE_REG_BITMAP_ALL 0xFFFFF
1019
1020#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
1021
1022#define _RRSR_RSC(x) (((x) & 0x3) << 21)
1023#define RRSR_RSC_RESERVED 0x0
1024#define RRSR_RSC_UPPER_SUBCHANNEL 0x1
1025#define RRSR_RSC_LOWER_SUBCHANNEL 0x2
1026#define RRSR_RSC_DUPLICATE_MODE 0x3
1027
1028#define USE_SHORT_G1 BIT(20)
1029
1030#define _AGGLMT_MCS0(x) ((x) & 0xF)
1031#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
1032#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
1033#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
1034#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
1035#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
1036#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
1037#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
1038
1039#define RETRY_LIMIT_SHORT_SHIFT 8
1040#define RETRY_LIMIT_LONG_SHIFT 0
1041
1042#define _DARF_RC1(x) ((x) & 0x1F)
1043#define _DARF_RC2(x) (((x) & 0x1F) << 8)
1044#define _DARF_RC3(x) (((x) & 0x1F) << 16)
1045#define _DARF_RC4(x) (((x) & 0x1F) << 24)
1046#define _DARF_RC5(x) ((x) & 0x1F)
1047#define _DARF_RC6(x) (((x) & 0x1F) << 8)
1048#define _DARF_RC7(x) (((x) & 0x1F) << 16)
1049#define _DARF_RC8(x) (((x) & 0x1F) << 24)
1050
1051#define _RARF_RC1(x) ((x) & 0x1F)
1052#define _RARF_RC2(x) (((x) & 0x1F) << 8)
1053#define _RARF_RC3(x) (((x) & 0x1F) << 16)
1054#define _RARF_RC4(x) (((x) & 0x1F) << 24)
1055#define _RARF_RC5(x) ((x) & 0x1F)
1056#define _RARF_RC6(x) (((x) & 0x1F) << 8)
1057#define _RARF_RC7(x) (((x) & 0x1F) << 16)
1058#define _RARF_RC8(x) (((x) & 0x1F) << 24)
1059
1060#define AC_PARAM_TXOP_OFFSET 16
1061#define AC_PARAM_TXOP_LIMIT_OFFSET 16
1062#define AC_PARAM_ECW_MAX_OFFSET 12
1063#define AC_PARAM_ECW_MIN_OFFSET 8
1064#define AC_PARAM_AIFS_OFFSET 0
1065
1066#define _AIFS(x) (x)
1067#define _ECW_MAX_MIN(x) ((x) << 8)
1068#define _TXOP_LIMIT(x) ((x) << 16)
1069
1070#define _BCNIFS(x) ((x) & 0xFF)
1071#define _BCNECW(x) ((((x) & 0xF)) << 8)
1072
1073#define _LRL(x) ((x) & 0x3F)
1074#define _SRL(x) (((x) & 0x3F) << 8)
1075
1076#define _SIFS_CCK_CTX(x) ((x) & 0xFF)
1077#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8);
1078
1079#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
1080#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8);
1081
1082#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
1083
1084#define DIS_EDCA_CNT_DWN BIT(11)
1085
1086#define EN_MBSSID BIT(1)
1087#define EN_TXBCN_RPT BIT(2)
1088#define EN_BCN_FUNCTION BIT(3)
1089
1090#define TSFTR_RST BIT(0)
1091#define TSFTR1_RST BIT(1)
1092
1093#define STOP_BCNQ BIT(6)
1094
1095#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
1096#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
1097
1098#define AcmHw_HwEn BIT(0)
1099#define AcmHw_BeqEn BIT(1)
1100#define AcmHw_ViqEn BIT(2)
1101#define AcmHw_VoqEn BIT(3)
1102#define AcmHw_BeqStatus BIT(4)
1103#define AcmHw_ViqStatus BIT(5)
1104#define AcmHw_VoqStatus BIT(6)
1105
1106#define APSDOFF BIT(6)
1107#define APSDOFF_STATUS BIT(7)
1108
1109#define BW_20MHZ BIT(2)
1110
1111#define RATE_BITMAP_ALL 0xFFFFF
1112
1113#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
1114
1115#define TSFRST BIT(0)
1116#define DIS_GCLK BIT(1)
1117#define PAD_SEL BIT(2)
1118#define PWR_ST BIT(6)
1119#define PWRBIT_OW_EN BIT(7)
1120#define ACRC BIT(8)
1121#define CFENDFORM BIT(9)
1122#define ICV BIT(10)
1123
1124#define AAP BIT(0)
1125#define APM BIT(1)
1126#define AM BIT(2)
1127#define AB BIT(3)
1128#define ADD3 BIT(4)
1129#define APWRMGT BIT(5)
1130#define CBSSID BIT(6)
1131#define CBSSID_DATA BIT(6)
1132#define CBSSID_BCN BIT(7)
1133#define ACRC32 BIT(8)
1134#define AICV BIT(9)
1135#define ADF BIT(11)
1136#define ACF BIT(12)
1137#define AMF BIT(13)
1138#define HTC_LOC_CTRL BIT(14)
1139#define UC_DATA_EN BIT(16)
1140#define BM_DATA_EN BIT(17)
1141#define MFBEN BIT(22)
1142#define LSIGEN BIT(23)
1143#define EnMBID BIT(24)
1144#define APP_BASSN BIT(27)
1145#define APP_PHYSTS BIT(28)
1146#define APP_ICV BIT(29)
1147#define APP_MIC BIT(30)
1148#define APP_FCS BIT(31)
1149
1150#define _MIN_SPACE(x) ((x) & 0x7)
1151#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
1152
1153#define RXERR_TYPE_OFDM_PPDU 0
1154#define RXERR_TYPE_OFDM_FALSE_ALARM 1
1155#define RXERR_TYPE_OFDM_MPDU_OK 2
1156#define RXERR_TYPE_OFDM_MPDU_FAIL 3
1157#define RXERR_TYPE_CCK_PPDU 4
1158#define RXERR_TYPE_CCK_FALSE_ALARM 5
1159#define RXERR_TYPE_CCK_MPDU_OK 6
1160#define RXERR_TYPE_CCK_MPDU_FAIL 7
1161#define RXERR_TYPE_HT_PPDU 8
1162#define RXERR_TYPE_HT_FALSE_ALARM 9
1163#define RXERR_TYPE_HT_MPDU_TOTAL 10
1164#define RXERR_TYPE_HT_MPDU_OK 11
1165#define RXERR_TYPE_HT_MPDU_FAIL 12
1166#define RXERR_TYPE_RX_FULL_DROP 15
1167
1168#define RXERR_COUNTER_MASK 0xFFFFF
1169#define RXERR_RPT_RST BIT(27)
1170#define _RXERR_RPT_SEL(type) ((type) << 28)
1171
1172#define SCR_TxUseDK BIT(0)
1173#define SCR_RxUseDK BIT(1)
1174#define SCR_TxEncEnable BIT(2)
1175#define SCR_RxDecEnable BIT(3)
1176#define SCR_SKByA2 BIT(4)
1177#define SCR_NoSKMC BIT(5)
1178#define SCR_TXBCUSEDK BIT(6)
1179#define SCR_RXBCUSEDK BIT(7)
1180
1181#define USB_IS_HIGH_SPEED 0
1182#define USB_IS_FULL_SPEED 1
1183#define USB_SPEED_MASK BIT(5)
1184
1185#define USB_NORMAL_SIE_EP_MASK 0xF
1186#define USB_NORMAL_SIE_EP_SHIFT 4
1187
1188#define USB_TEST_EP_MASK 0x30
1189#define USB_TEST_EP_SHIFT 4
1190
1191#define USB_AGG_EN BIT(3)
1192
1193#define MAC_ADDR_LEN 6
1194#define LAST_ENTRY_OF_TX_PKT_BUFFER 255
1195
1196#define POLLING_LLT_THRESHOLD 20
1197#define POLLING_READY_TIMEOUT_COUNT 1000
1198
1199#define MAX_MSS_DENSITY_2T 0x13
1200#define MAX_MSS_DENSITY_1T 0x0A
1201
1202#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
1203#define EPROM_CMD_CONFIG 0x3
1204#define EPROM_CMD_LOAD 1
1205
1206#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE
1207
1208#define WL_HWPDN_EN BIT(0)
1209
1210#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1211
1212#define RPMAC_RESET 0x100
1213#define RPMAC_TXSTART 0x104
1214#define RPMAC_TXLEGACYSIG 0x108
1215#define RPMAC_TXHTSIG1 0x10c
1216#define RPMAC_TXHTSIG2 0x110
1217#define RPMAC_PHYDEBUG 0x114
1218#define RPMAC_TXPACKETNUM 0x118
1219#define RPMAC_TXIDLE 0x11c
1220#define RPMAC_TXMACHEADER0 0x120
1221#define RPMAC_TXMACHEADER1 0x124
1222#define RPMAC_TXMACHEADER2 0x128
1223#define RPMAC_TXMACHEADER3 0x12c
1224#define RPMAC_TXMACHEADER4 0x130
1225#define RPMAC_TXMACHEADER5 0x134
1226#define RPMAC_TXDADATYPE 0x138
1227#define RPMAC_TXRANDOMSEED 0x13c
1228#define RPMAC_CCKPLCPPREAMBLE 0x140
1229#define RPMAC_CCKPLCPHEADER 0x144
1230#define RPMAC_CCKCRC16 0x148
1231#define RPMAC_OFDMRXCRC32OK 0x170
1232#define RPMAC_OFDMRXCRC32Er 0x174
1233#define RPMAC_OFDMRXPARITYER 0x178
1234#define RPMAC_OFDMRXCRC8ER 0x17c
1235#define RPMAC_CCKCRXRC16ER 0x180
1236#define RPMAC_CCKCRXRC32ER 0x184
1237#define RPMAC_CCKCRXRC32OK 0x188
1238#define RPMAC_TXSTATUS 0x18c
1239
1240#define RFPGA0_RFMOD 0x800
1241
1242#define RFPGA0_TXINFO 0x804
1243#define RFPGA0_PSDFUNCTION 0x808
1244
1245#define RFPGA0_TXGAINSTAGE 0x80c
1246
1247#define RFPGA0_RFTIMING1 0x810
1248#define RFPGA0_RFTIMING2 0x814
1249
1250#define RFPGA0_XA_HSSIPARAMETER1 0x820
1251#define RFPGA0_XA_HSSIPARAMETER2 0x824
1252#define RFPGA0_XB_HSSIPARAMETER1 0x828
1253#define RFPGA0_XB_HSSIPARAMETER2 0x82c
1254
1255#define RFPGA0_XA_LSSIPARAMETER 0x840
1256#define RFPGA0_XB_LSSIPARAMETER 0x844
1257
1258#define RFPGA0_RFWAKEUPPARAMETER 0x850
1259#define RFPGA0_RFSLEEPUPPARAMETER 0x854
1260
1261#define RFPGA0_XAB_SWITCHCONTROL 0x858
1262#define RFPGA0_XCD_SWITCHCONTROL 0x85c
1263
1264#define RFPGA0_XA_RFINTERFACEOE 0x860
1265#define RFPGA0_XB_RFINTERFACEOE 0x864
1266
1267#define RFPGA0_XAB_RFINTERFACESW 0x870
1268#define RFPGA0_XCD_RFINTERFACESW 0x874
1269
1270#define rFPGA0_XAB_RFPARAMETER 0x878
1271#define rFPGA0_XCD_RFPARAMETER 0x87c
1272
1273#define RFPGA0_ANALOGPARAMETER1 0x880
1274#define RFPGA0_ANALOGPARAMETER2 0x884
1275#define RFPGA0_ANALOGPARAMETER3 0x888
1276#define RFPGA0_ANALOGPARAMETER4 0x88c
1277
1278#define RFPGA0_XA_LSSIREADBACK 0x8a0
1279#define RFPGA0_XB_LSSIREADBACK 0x8a4
1280#define RFPGA0_XC_LSSIREADBACK 0x8a8
1281#define RFPGA0_XD_LSSIREADBACK 0x8ac
1282
1283#define RFPGA0_PSDREPORT 0x8b4
1284#define TRANSCEIVEA_HSPI_READBACK 0x8b8
1285#define TRANSCEIVEB_HSPI_READBACK 0x8bc
1286#define RFPGA0_XAB_RFINTERFACERB 0x8e0
1287#define RFPGA0_XCD_RFINTERFACERB 0x8e4
1288
1289#define RFPGA1_RFMOD 0x900
1290
1291#define RFPGA1_TXBLOCK 0x904
1292#define RFPGA1_DEBUGSELECT 0x908
1293#define RFPGA1_TXINFO 0x90c
1294
1295#define RCCK0_SYSTEM 0xa00
1296
1297#define RCCK0_AFESETTING 0xa04
1298#define RCCK0_CCA 0xa08
1299
1300#define RCCK0_RXAGC1 0xa0c
1301#define RCCK0_RXAGC2 0xa10
1302
1303#define RCCK0_RXHP 0xa14
1304
1305#define RCCK0_DSPPARAMETER1 0xa18
1306#define RCCK0_DSPPARAMETER2 0xa1c
1307
1308#define RCCK0_TXFILTER1 0xa20
1309#define RCCK0_TXFILTER2 0xa24
1310#define RCCK0_DEBUGPORT 0xa28
1311#define RCCK0_FALSEALARMREPORT 0xa2c
1312#define RCCK0_TRSSIREPORT 0xa50
1313#define RCCK0_RXREPORT 0xa54
1314#define RCCK0_FACOUNTERLOWER 0xa5c
1315#define RCCK0_FACOUNTERUPPER 0xa58
1316
1317#define ROFDM0_LSTF 0xc00
1318
1319#define ROFDM0_TRXPATHENABLE 0xc04
1320#define ROFDM0_TRMUXPAR 0xc08
1321#define ROFDM0_TRSWISOLATION 0xc0c
1322
1323#define ROFDM0_XARXAFE 0xc10
1324#define ROFDM0_XARXIQIMBALANCE 0xc14
1325#define ROFDM0_XBRXAFE 0xc18
1326#define ROFDM0_XBRXIQIMBALANCE 0xc1c
1327#define ROFDM0_XCRXAFE 0xc20
1328#define ROFDM0_XCRXIQIMBANLANCE 0xc24
1329#define ROFDM0_XDRXAFE 0xc28
1330#define ROFDM0_XDRXIQIMBALANCE 0xc2c
1331
1332#define ROFDM0_RXDETECTOR1 0xc30
1333#define ROFDM0_RXDETECTOR2 0xc34
1334#define ROFDM0_RXDETECTOR3 0xc38
1335#define ROFDM0_RXDETECTOR4 0xc3c
1336
1337#define ROFDM0_RXDSP 0xc40
1338#define ROFDM0_CFOANDDAGC 0xc44
1339#define ROFDM0_CCADROPTHRESHOLD 0xc48
1340#define ROFDM0_ECCATHRESHOLD 0xc4c
1341
1342#define ROFDM0_XAAGCCORE1 0xc50
1343#define ROFDM0_XAAGCCORE2 0xc54
1344#define ROFDM0_XBAGCCORE1 0xc58
1345#define ROFDM0_XBAGCCORE2 0xc5c
1346#define ROFDM0_XCAGCCORE1 0xc60
1347#define ROFDM0_XCAGCCORE2 0xc64
1348#define ROFDM0_XDAGCCORE1 0xc68
1349#define ROFDM0_XDAGCCORE2 0xc6c
1350
1351#define ROFDM0_AGCPARAMETER1 0xc70
1352#define ROFDM0_AGCPARAMETER2 0xc74
1353#define ROFDM0_AGCRSSITABLE 0xc78
1354#define ROFDM0_HTSTFAGC 0xc7c
1355
1356#define ROFDM0_XATXIQIMBALANCE 0xc80
1357#define ROFDM0_XATXAFE 0xc84
1358#define ROFDM0_XBTXIQIMBALANCE 0xc88
1359#define ROFDM0_XBTXAFE 0xc8c
1360#define ROFDM0_XCTXIQIMBALANCE 0xc90
1361#define ROFDM0_XCTXAFE 0xc94
1362#define ROFDM0_XDTXIQIMBALANCE 0xc98
1363#define ROFDM0_XDTXAFE 0xc9c
1364
1365#define ROFDM0_RXIQEXTANTA 0xca0
1366
1367#define ROFDM0_RXHPPARAMETER 0xce0
1368#define ROFDM0_TXPSEUDONOISEWGT 0xce4
1369#define ROFDM0_FRAMESYNC 0xcf0
1370#define ROFDM0_DFSREPORT 0xcf4
1371#define ROFDM0_TXCOEFF1 0xca4
1372#define ROFDM0_TXCOEFF2 0xca8
1373#define ROFDM0_TXCOEFF3 0xcac
1374#define ROFDM0_TXCOEFF4 0xcb0
1375#define ROFDM0_TXCOEFF5 0xcb4
1376#define ROFDM0_TXCOEFF6 0xcb8
1377
1378#define ROFDM1_LSTF 0xd00
1379#define ROFDM1_TRXPATHENABLE 0xd04
1380
1381#define ROFDM1_CF0 0xd08
1382#define ROFDM1_CSI1 0xd10
1383#define ROFDM1_SBD 0xd14
1384#define ROFDM1_CSI2 0xd18
1385#define ROFDM1_CFOTRACKING 0xd2c
1386#define ROFDM1_TRXMESAURE1 0xd34
1387#define ROFDM1_INTFDET 0xd3c
1388#define ROFDM1_PSEUDONOISESTATEAB 0xd50
1389#define ROFDM1_PSEUDONOISESTATECD 0xd54
1390#define ROFDM1_RXPSEUDONOISEWGT 0xd58
1391
1392#define ROFDM_PHYCOUNTER1 0xda0
1393#define ROFDM_PHYCOUNTER2 0xda4
1394#define ROFDM_PHYCOUNTER3 0xda8
1395
1396#define ROFDM_SHORTCFOAB 0xdac
1397#define ROFDM_SHORTCFOCD 0xdb0
1398#define ROFDM_LONGCFOAB 0xdb4
1399#define ROFDM_LONGCFOCD 0xdb8
1400#define ROFDM_TAILCF0AB 0xdbc
1401#define ROFDM_TAILCF0CD 0xdc0
1402#define ROFDM_PWMEASURE1 0xdc4
1403#define ROFDM_PWMEASURE2 0xdc8
1404#define ROFDM_BWREPORT 0xdcc
1405#define ROFDM_AGCREPORT 0xdd0
1406#define ROFDM_RXSNR 0xdd4
1407#define ROFDM_RXEVMCSI 0xdd8
1408#define ROFDM_SIGREPORT 0xddc
1409
1410#define RTXAGC_A_RATE18_06 0xe00
1411#define RTXAGC_A_RATE54_24 0xe04
1412#define RTXAGC_A_CCK1_MCS32 0xe08
1413#define RTXAGC_A_MCS03_MCS00 0xe10
1414#define RTXAGC_A_MCS07_MCS04 0xe14
1415#define RTXAGC_A_MCS11_MCS08 0xe18
1416#define RTXAGC_A_MCS15_MCS12 0xe1c
1417
1418#define RTXAGC_B_RATE18_06 0x830
1419#define RTXAGC_B_RATE54_24 0x834
1420#define RTXAGC_B_CCK1_55_MCS32 0x838
1421#define RTXAGC_B_MCS03_MCS00 0x83c
1422#define RTXAGC_B_MCS07_MCS04 0x848
1423#define RTXAGC_B_MCS11_MCS08 0x84c
1424#define RTXAGC_B_MCS15_MCS12 0x868
1425#define RTXAGC_B_CCK11_A_CCK2_11 0x86c
1426
1427#define RZEBRA1_HSSIENABLE 0x0
1428#define RZEBRA1_TRXENABLE1 0x1
1429#define RZEBRA1_TRXENABLE2 0x2
1430#define RZEBRA1_AGC 0x4
1431#define RZEBRA1_CHARGEPUMP 0x5
1432#define RZEBRA1_CHANNEL 0x7
1433
1434#define RZEBRA1_TXGAIN 0x8
1435#define RZEBRA1_TXLPF 0x9
1436#define RZEBRA1_RXLPF 0xb
1437#define RZEBRA1_RXHPFCORNER 0xc
1438
1439#define RGLOBALCTRL 0
1440#define RRTL8256_TXLPF 19
1441#define RRTL8256_RXLPF 11
1442#define RRTL8258_TXLPF 0x11
1443#define RRTL8258_RXLPF 0x13
1444#define RRTL8258_RSSILPF 0xa
1445
1446#define RF_AC 0x00
1447
1448#define RF_IQADJ_G1 0x01
1449#define RF_IQADJ_G2 0x02
1450#define RF_POW_TRSW 0x05
1451
1452#define RF_GAIN_RX 0x06
1453#define RF_GAIN_TX 0x07
1454
1455#define RF_TXM_IDAC 0x08
1456#define RF_BS_IQGEN 0x0F
1457
1458#define RF_MODE1 0x10
1459#define RF_MODE2 0x11
1460
1461#define RF_RX_AGC_HP 0x12
1462#define RF_TX_AGC 0x13
1463#define RF_BIAS 0x14
1464#define RF_IPA 0x15
1465#define RF_POW_ABILITY 0x17
1466#define RF_MODE_AG 0x18
1467#define RRFCHANNEL 0x18
1468#define RF_CHNLBW 0x18
1469#define RF_TOP 0x19
1470
1471#define RF_RX_G1 0x1A
1472#define RF_RX_G2 0x1B
1473
1474#define RF_RX_BB2 0x1C
1475#define RF_RX_BB1 0x1D
1476
1477#define RF_RCK1 0x1E
1478#define RF_RCK2 0x1F
1479
1480#define RF_TX_G1 0x20
1481#define RF_TX_G2 0x21
1482#define RF_TX_G3 0x22
1483
1484#define RF_TX_BB1 0x23
1485#define RF_T_METER 0x24
1486
1487#define RF_SYN_G1 0x25
1488#define RF_SYN_G2 0x26
1489#define RF_SYN_G3 0x27
1490#define RF_SYN_G4 0x28
1491#define RF_SYN_G5 0x29
1492#define RF_SYN_G6 0x2A
1493#define RF_SYN_G7 0x2B
1494#define RF_SYN_G8 0x2C
1495
1496#define RF_RCK_OS 0x30
1497#define RF_TXPA_G1 0x31
1498#define RF_TXPA_G2 0x32
1499#define RF_TXPA_G3 0x33
1500
1501#define BBBRESETB 0x100
1502#define BGLOBALRESETB 0x200
1503#define BOFDMTXSTART 0x4
1504#define BCCKTXSTART 0x8
1505#define BCRC32DEBUG 0x100
1506#define BPMACLOOPBACK 0x10
1507#define BTXLSIG 0xffffff
1508#define BOFDMTXRATE 0xf
1509#define BOFDMTXRESERVED 0x10
1510#define BOFDMTXLENGTH 0x1ffe0
1511#define BOFDMTXPARITY 0x20000
1512#define BTXHTSIG1 0xffffff
1513#define BTXHTMCSRATE 0x7f
1514#define BTXHTBW 0x80
1515#define BTXHTLENGTH 0xffff00
1516#define BTXHTSIG2 0xffffff
1517#define BTXHTSMOOTHING 0x1
1518#define BTXHTSOUNDING 0x2
1519#define BTXHTRESERVED 0x4
1520#define BTXHTAGGREATION 0x8
1521#define BTXHTSTBC 0x30
1522#define BTXHTADVANCECODING 0x40
1523#define BTXHTSHORTGI 0x80
1524#define BTXHTNUMBERHT_LTF 0x300
1525#define BTXHTCRC8 0x3fc00
1526#define BCOUNTERRESET 0x10000
1527#define BNUMOFOFDMTX 0xffff
1528#define BNUMOFCCKTX 0xffff0000
1529#define BTXIDLEINTERVAL 0xffff
1530#define BOFDMSERVICE 0xffff0000
1531#define BTXMACHEADER 0xffffffff
1532#define BTXDATAINIT 0xff
1533#define BTXHTMODE 0x100
1534#define BTXDATATYPE 0x30000
1535#define BTXRANDOMSEED 0xffffffff
1536#define BCCKTXPREAMBLE 0x1
1537#define BCCKTXSFD 0xffff0000
1538#define BCCKTXSIG 0xff
1539#define BCCKTXSERVICE 0xff00
1540#define BCCKLENGTHEXT 0x8000
1541#define BCCKTXLENGHT 0xffff0000
1542#define BCCKTXCRC16 0xffff
1543#define BCCKTXSTATUS 0x1
1544#define BOFDMTXSTATUS 0x2
1545#define IS_BB_REG_OFFSET_92S(_Offset) \
1546 ((_Offset >= 0x800) && (_Offset <= 0xfff))
1547
1548#define BRFMOD 0x1
1549#define BJAPANMODE 0x2
1550#define BCCKTXSC 0x30
1551#define BCCKEN 0x1000000
1552#define BOFDMEN 0x2000000
1553
1554#define BOFDMRXADCPHASE 0x10000
1555#define BOFDMTXDACPHASE 0x40000
1556#define BXATXAGC 0x3f
1557
1558#define BXBTXAGC 0xf00
1559#define BXCTXAGC 0xf000
1560#define BXDTXAGC 0xf0000
1561
1562#define BPASTART 0xf0000000
1563#define BTRSTART 0x00f00000
1564#define BRFSTART 0x0000f000
1565#define BBBSTART 0x000000f0
1566#define BBBCCKSTART 0x0000000f
1567#define BPAEND 0xf
1568#define BTREND 0x0f000000
1569#define BRFEND 0x000f0000
1570#define BCCAMASK 0x000000f0
1571#define BR2RCCAMASK 0x00000f00
1572#define BHSSI_R2TDELAY 0xf8000000
1573#define BHSSI_T2RDELAY 0xf80000
1574#define BCONTXHSSI 0x400
1575#define BIGFROMCCK 0x200
1576#define BAGCADDRESS 0x3f
1577#define BRXHPTX 0x7000
1578#define BRXHP2RX 0x38000
1579#define BRXHPCCKINI 0xc0000
1580#define BAGCTXCODE 0xc00000
1581#define BAGCRXCODE 0x300000
1582
1583#define B3WIREDATALENGTH 0x800
1584#define B3WIREADDREAALENGTH 0x400
1585
1586#define B3WIRERFPOWERDOWN 0x1
1587#define B5GPAPEPOLARITY 0x40000000
1588#define B2GPAPEPOLARITY 0x80000000
1589#define BRFSW_TXDEFAULTANT 0x3
1590#define BRFSW_TXOPTIONANT 0x30
1591#define BRFSW_RXDEFAULTANT 0x300
1592#define BRFSW_RXOPTIONANT 0x3000
1593#define BRFSI_3WIREDATA 0x1
1594#define BRFSI_3WIRECLOCK 0x2
1595#define BRFSI_3WIRELOAD 0x4
1596#define BRFSI_3WIRERW 0x8
1597#define BRFSI_3WIRE 0xf
1598
1599#define BRFSI_RFENV 0x10
1600
1601#define BRFSI_TRSW 0x20
1602#define BRFSI_TRSWB 0x40
1603#define BRFSI_ANTSW 0x100
1604#define BRFSI_ANTSWB 0x200
1605#define BRFSI_PAPE 0x400
1606#define BRFSI_PAPE5G 0x800
1607#define BBANDSELECT 0x1
1608#define BHTSIG2_GI 0x80
1609#define BHTSIG2_SMOOTHING 0x01
1610#define BHTSIG2_SOUNDING 0x02
1611#define BHTSIG2_AGGREATON 0x08
1612#define BHTSIG2_STBC 0x30
1613#define BHTSIG2_ADVCODING 0x40
1614#define BHTSIG2_NUMOFHTLTF 0x300
1615#define BHTSIG2_CRC8 0x3fc
1616#define BHTSIG1_MCS 0x7f
1617#define BHTSIG1_BANDWIDTH 0x80
1618#define BHTSIG1_HTLENGTH 0xffff
1619#define BLSIG_RATE 0xf
1620#define BLSIG_RESERVED 0x10
1621#define BLSIG_LENGTH 0x1fffe
1622#define BLSIG_PARITY 0x20
1623#define BCCKRXPHASE 0x4
1624
1625#define BLSSIREADADDRESS 0x7f800000
1626#define BLSSIREADEDGE 0x80000000
1627
1628#define BLSSIREADBACKDATA 0xfffff
1629
1630#define BLSSIREADOKFLAG 0x1000
1631#define BCCKSAMPLERATE 0x8
1632#define BREGULATOR0STANDBY 0x1
1633#define BREGULATORPLLSTANDBY 0x2
1634#define BREGULATOR1STANDBY 0x4
1635#define BPLLPOWERUP 0x8
1636#define BDPLLPOWERUP 0x10
1637#define BDA10POWERUP 0x20
1638#define BAD7POWERUP 0x200
1639#define BDA6POWERUP 0x2000
1640#define BXTALPOWERUP 0x4000
1641#define B40MDCLKPOWERUP 0x8000
1642#define BDA6DEBUGMODE 0x20000
1643#define BDA6SWING 0x380000
1644
1645#define BADCLKPHASE 0x4000000
1646#define B80MCLKDELAY 0x18000000
1647#define BAFEWATCHDOGENABLE 0x20000000
1648
1649#define BXTALCAP01 0xc0000000
1650#define BXTALCAP23 0x3
1651#define BXTALCAP92X 0x0f000000
1652#define BXTALCAP 0x0f000000
1653
1654#define BINTDIFCLKENABLE 0x400
1655#define BEXTSIGCLKENABLE 0x800
1656#define BBANDGAP_MBIAS_POWERUP 0x10000
1657#define BAD11SH_GAIN 0xc0000
1658#define BAD11NPUT_RANGE 0x700000
1659#define BAD110P_CURRENT 0x3800000
1660#define BLPATH_LOOPBACK 0x4000000
1661#define BQPATH_LOOPBACK 0x8000000
1662#define BAFE_LOOPBACK 0x10000000
1663#define BDA10_SWING 0x7e0
1664#define BDA10_REVERSE 0x800
1665#define BDA_CLK_SOURCE 0x1000
1666#define BDA7INPUT_RANGE 0x6000
1667#define BDA7_GAIN 0x38000
1668#define BDA7OUTPUT_CM_MODE 0x40000
1669#define BDA7INPUT_CM_MODE 0x380000
1670#define BDA7CURRENT 0xc00000
1671#define BREGULATOR_ADJUST 0x7000000
1672#define BAD11POWERUP_ATTX 0x1
1673#define BDA10PS_ATTX 0x10
1674#define BAD11POWERUP_ATRX 0x100
1675#define BDA10PS_ATRX 0x1000
1676#define BCCKRX_AGC_FORMAT 0x200
1677#define BPSDFFT_SAMPLE_POINT 0xc000
1678#define BPSD_AVERAGE_NUM 0x3000
1679#define BIQPATH_CONTROL 0xc00
1680#define BPSD_FREQ 0x3ff
1681#define BPSD_ANTENNA_PATH 0x30
1682#define BPSD_IQ_SWITCH 0x40
1683#define BPSD_RX_TRIGGER 0x400000
1684#define BPSD_TX_TRIGGER 0x80000000
1685#define BPSD_SINE_TONE_SCALE 0x7f000000
1686#define BPSD_REPORT 0xffff
1687
1688#define BOFDM_TXSC 0x30000000
1689#define BCCK_TXON 0x1
1690#define BOFDM_TXON 0x2
1691#define BDEBUG_PAGE 0xfff
1692#define BDEBUG_ITEM 0xff
1693#define BANTL 0x10
1694#define BANT_NONHT 0x100
1695#define BANT_HT1 0x1000
1696#define BANT_HT2 0x10000
1697#define BANT_HT1S1 0x100000
1698#define BANT_NONHTS1 0x1000000
1699
1700#define BCCK_BBMODE 0x3
1701#define BCCK_TXPOWERSAVING 0x80
1702#define BCCK_RXPOWERSAVING 0x40
1703
1704#define BCCK_SIDEBAND 0x10
1705
1706#define BCCK_SCRAMBLE 0x8
1707#define BCCK_ANTDIVERSITY 0x8000
1708#define BCCK_CARRIER_RECOVERY 0x4000
1709#define BCCK_TXRATE 0x3000
1710#define BCCK_DCCANCEL 0x0800
1711#define BCCK_ISICANCEL 0x0400
1712#define BCCK_MATCH_FILTER 0x0200
1713#define BCCK_EQUALIZER 0x0100
1714#define BCCK_PREAMBLE_DETECT 0x800000
1715#define BCCK_FAST_FALSECCA 0x400000
1716#define BCCK_CH_ESTSTART 0x300000
1717#define BCCK_CCA_COUNT 0x080000
1718#define BCCK_CS_LIM 0x070000
1719#define BCCK_BIST_MODE 0x80000000
1720#define BCCK_CCAMASK 0x40000000
1721#define BCCK_TX_DAC_PHASE 0x4
1722#define BCCK_RX_ADC_PHASE 0x20000000
1723#define BCCKR_CP_MODE 0x0100
1724#define BCCK_TXDC_OFFSET 0xf0
1725#define BCCK_RXDC_OFFSET 0xf
1726#define BCCK_CCA_MODE 0xc000
1727#define BCCK_FALSECS_LIM 0x3f00
1728#define BCCK_CS_RATIO 0xc00000
1729#define BCCK_CORGBIT_SEL 0x300000
1730#define BCCK_PD_LIM 0x0f0000
1731#define BCCK_NEWCCA 0x80000000
1732#define BCCK_RXHP_OF_IG 0x8000
1733#define BCCK_RXIG 0x7f00
1734#define BCCK_LNA_POLARITY 0x800000
1735#define BCCK_RX1ST_BAIN 0x7f0000
1736#define BCCK_RF_EXTEND 0x20000000
1737#define BCCK_RXAGC_SATLEVEL 0x1f000000
1738#define BCCK_RXAGC_SATCOUNT 0xe0
1739#define bCCKRxRFSettle 0x1f
1740#define BCCK_FIXED_RXAGC 0x8000
1741#define BCCK_ANTENNA_POLARITY 0x2000
1742#define BCCK_TXFILTER_TYPE 0x0c00
1743#define BCCK_RXAGC_REPORTTYPE 0x0300
1744#define BCCK_RXDAGC_EN 0x80000000
1745#define BCCK_RXDAGC_PERIOD 0x20000000
1746#define BCCK_RXDAGC_SATLEVEL 0x1f000000
1747#define BCCK_TIMING_RECOVERY 0x800000
1748#define BCCK_TXC0 0x3f0000
1749#define BCCK_TXC1 0x3f000000
1750#define BCCK_TXC2 0x3f
1751#define BCCK_TXC3 0x3f00
1752#define BCCK_TXC4 0x3f0000
1753#define BCCK_TXC5 0x3f000000
1754#define BCCK_TXC6 0x3f
1755#define BCCK_TXC7 0x3f00
1756#define BCCK_DEBUGPORT 0xff0000
1757#define BCCK_DAC_DEBUG 0x0f000000
1758#define BCCK_FALSEALARM_ENABLE 0x8000
1759#define BCCK_FALSEALARM_READ 0x4000
1760#define BCCK_TRSSI 0x7f
1761#define BCCK_RXAGC_REPORT 0xfe
1762#define BCCK_RXREPORT_ANTSEL 0x80000000
1763#define BCCK_RXREPORT_MFOFF 0x40000000
1764#define BCCK_RXREPORT_SQLOSS 0x20000000
1765#define BCCK_RXREPORT_PKTLOSS 0x10000000
1766#define BCCK_RXREPORT_LOCKEDBIT 0x08000000
1767#define BCCK_RXREPORT_RATEERROR 0x04000000
1768#define BCCK_RXREPORT_RXRATE 0x03000000
1769#define BCCK_RXFA_COUNTER_LOWER 0xff
1770#define BCCK_RXFA_COUNTER_UPPER 0xff000000
1771#define BCCK_RXHPAGC_START 0xe000
1772#define BCCK_RXHPAGC_FINAL 0x1c00
1773#define BCCK_RXFALSEALARM_ENABLE 0x8000
1774#define BCCK_FACOUNTER_FREEZE 0x4000
1775#define BCCK_TXPATH_SEL 0x10000000
1776#define BCCK_DEFAULT_RXPATH 0xc000000
1777#define BCCK_OPTION_RXPATH 0x3000000
1778
1779#define BNUM_OFSTF 0x3
1780#define BSHIFT_L 0xc0
1781#define BGI_TH 0xc
1782#define BRXPATH_A 0x1
1783#define BRXPATH_B 0x2
1784#define BRXPATH_C 0x4
1785#define BRXPATH_D 0x8
1786#define BTXPATH_A 0x1
1787#define BTXPATH_B 0x2
1788#define BTXPATH_C 0x4
1789#define BTXPATH_D 0x8
1790#define BTRSSI_FREQ 0x200
1791#define BADC_BACKOFF 0x3000
1792#define BDFIR_BACKOFF 0xc000
1793#define BTRSSI_LATCH_PHASE 0x10000
1794#define BRX_LDC_OFFSET 0xff
1795#define BRX_QDC_OFFSET 0xff00
1796#define BRX_DFIR_MODE 0x1800000
1797#define BRX_DCNF_TYPE 0xe000000
1798#define BRXIQIMB_A 0x3ff
1799#define BRXIQIMB_B 0xfc00
1800#define BRXIQIMB_C 0x3f0000
1801#define BRXIQIMB_D 0xffc00000
1802#define BDC_DC_NOTCH 0x60000
1803#define BRXNB_NOTCH 0x1f000000
1804#define BPD_TH 0xf
1805#define BPD_TH_OPT2 0xc000
1806#define BPWED_TH 0x700
1807#define BIFMF_WIN_L 0x800
1808#define BPD_OPTION 0x1000
1809#define BMF_WIN_L 0xe000
1810#define BBW_SEARCH_L 0x30000
1811#define BWIN_ENH_L 0xc0000
1812#define BBW_TH 0x700000
1813#define BED_TH2 0x3800000
1814#define BBW_OPTION 0x4000000
1815#define BRADIO_TH 0x18000000
1816#define BWINDOW_L 0xe0000000
1817#define BSBD_OPTION 0x1
1818#define BFRAME_TH 0x1c
1819#define BFS_OPTION 0x60
1820#define BDC_SLOPE_CHECK 0x80
1821#define BFGUARD_COUNTER_DC_L 0xe00
1822#define BFRAME_WEIGHT_SHORT 0x7000
1823#define BSUB_TUNE 0xe00000
1824#define BFRAME_DC_LENGTH 0xe000000
1825#define BSBD_START_OFFSET 0x30000000
1826#define BFRAME_TH_2 0x7
1827#define BFRAME_GI2_TH 0x38
1828#define BGI2_SYNC_EN 0x40
1829#define BSARCH_SHORT_EARLY 0x300
1830#define BSARCH_SHORT_LATE 0xc00
1831#define BSARCH_GI2_LATE 0x70000
1832#define BCFOANTSUM 0x1
1833#define BCFOACC 0x2
1834#define BCFOSTARTOFFSET 0xc
1835#define BCFOLOOPBACK 0x70
1836#define BCFOSUMWEIGHT 0x80
1837#define BDAGCENABLE 0x10000
1838#define BTXIQIMB_A 0x3ff
1839#define BTXIQIMB_b 0xfc00
1840#define BTXIQIMB_C 0x3f0000
1841#define BTXIQIMB_D 0xffc00000
1842#define BTXIDCOFFSET 0xff
1843#define BTXIQDCOFFSET 0xff00
1844#define BTXDFIRMODE 0x10000
1845#define BTXPESUDO_NOISEON 0x4000000
1846#define BTXPESUDO_NOISE_A 0xff
1847#define BTXPESUDO_NOISE_B 0xff00
1848#define BTXPESUDO_NOISE_C 0xff0000
1849#define BTXPESUDO_NOISE_D 0xff000000
1850#define BCCA_DROPOPTION 0x20000
1851#define BCCA_DROPTHRES 0xfff00000
1852#define BEDCCA_H 0xf
1853#define BEDCCA_L 0xf0
1854#define BLAMBDA_ED 0x300
1855#define BRX_INITIALGAIN 0x7f
1856#define BRX_ANTDIV_EN 0x80
1857#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
1858#define BRX_HIGHPOWER_FLOW 0x8000
1859#define BRX_AGC_FREEZE_THRES 0xc0000
1860#define BRX_FREEZESTEP_AGC1 0x300000
1861#define BRX_FREEZESTEP_AGC2 0xc00000
1862#define BRX_FREEZESTEP_AGC3 0x3000000
1863#define BRX_FREEZESTEP_AGC0 0xc000000
1864#define BRXRSSI_CMP_EN 0x10000000
1865#define BRXQUICK_AGCEN 0x20000000
1866#define BRXAGC_FREEZE_THRES_MODE 0x40000000
1867#define BRX_OVERFLOW_CHECKTYPE 0x80000000
1868#define BRX_AGCSHIFT 0x7f
1869#define BTRSW_TRI_ONLY 0x80
1870#define BPOWER_THRES 0x300
1871#define BRXAGC_EN 0x1
1872#define BRXAGC_TOGETHER_EN 0x2
1873#define BRXAGC_MIN 0x4
1874#define BRXHP_INI 0x7
1875#define BRXHP_TRLNA 0x70
1876#define BRXHP_RSSI 0x700
1877#define BRXHP_BBP1 0x7000
1878#define BRXHP_BBP2 0x70000
1879#define BRXHP_BBP3 0x700000
1880#define BRSSI_H 0x7f0000
1881#define BRSSI_GEN 0x7f000000
1882#define BRXSETTLE_TRSW 0x7
1883#define BRXSETTLE_LNA 0x38
1884#define BRXSETTLE_RSSI 0x1c0
1885#define BRXSETTLE_BBP 0xe00
1886#define BRXSETTLE_RXHP 0x7000
1887#define BRXSETTLE_ANTSW_RSSI 0x38000
1888#define BRXSETTLE_ANTSW 0xc0000
1889#define BRXPROCESS_TIME_DAGC 0x300000
1890#define BRXSETTLE_HSSI 0x400000
1891#define BRXPROCESS_TIME_BBPPW 0x800000
1892#define BRXANTENNA_POWER_SHIFT 0x3000000
1893#define BRSSI_TABLE_SELECT 0xc000000
1894#define BRXHP_FINAL 0x7000000
1895#define BRXHPSETTLE_BBP 0x7
1896#define BRXHTSETTLE_HSSI 0x8
1897#define BRXHTSETTLE_RXHP 0x70
1898#define BRXHTSETTLE_BBPPW 0x80
1899#define BRXHTSETTLE_IDLE 0x300
1900#define BRXHTSETTLE_RESERVED 0x1c00
1901#define BRXHT_RXHP_EN 0x8000
1902#define BRXAGC_FREEZE_THRES 0x30000
1903#define BRXAGC_TOGETHEREN 0x40000
1904#define BRXHTAGC_MIN 0x80000
1905#define BRXHTAGC_EN 0x100000
1906#define BRXHTDAGC_EN 0x200000
1907#define BRXHT_RXHP_BBP 0x1c00000
1908#define BRXHT_RXHP_FINAL 0xe0000000
1909#define BRXPW_RADIO_TH 0x3
1910#define BRXPW_RADIO_EN 0x4
1911#define BRXMF_HOLD 0x3800
1912#define BRXPD_DELAY_TH1 0x38
1913#define BRXPD_DELAY_TH2 0x1c0
1914#define BRXPD_DC_COUNT_MAX 0x600
1915#define BRXPD_DELAY_TH 0x8000
1916#define BRXPROCESS_DELAY 0xf0000
1917#define BRXSEARCHRANGE_GI2_EARLY 0x700000
1918#define BRXFRAME_FUARD_COUNTER_L 0x3800000
1919#define BRXSGI_GUARD_L 0xc000000
1920#define BRXSGI_SEARCH_L 0x30000000
1921#define BRXSGI_TH 0xc0000000
1922#define BDFSCNT0 0xff
1923#define BDFSCNT1 0xff00
1924#define BDFSFLAG 0xf0000
1925#define BMF_WEIGHT_SUM 0x300000
1926#define BMINIDX_TH 0x7f000000
1927#define BDAFORMAT 0x40000
1928#define BTXCH_EMU_ENABLE 0x01000000
1929#define BTRSW_ISOLATION_A 0x7f
1930#define BTRSW_ISOLATION_B 0x7f00
1931#define BTRSW_ISOLATION_C 0x7f0000
1932#define BTRSW_ISOLATION_D 0x7f000000
1933#define BEXT_LNA_GAIN 0x7c00
1934
1935#define BSTBC_EN 0x4
1936#define BANTENNA_MAPPING 0x10
1937#define BNSS 0x20
1938#define BCFO_ANTSUM_ID 0x200
1939#define BPHY_COUNTER_RESET 0x8000000
1940#define BCFO_REPORT_GET 0x4000000
1941#define BOFDM_CONTINUE_TX 0x10000000
1942#define BOFDM_SINGLE_CARRIER 0x20000000
1943#define BOFDM_SINGLE_TONE 0x40000000
1944#define BHT_DETECT 0x100
1945#define BCFOEN 0x10000
1946#define BCFOVALUE 0xfff00000
1947#define BSIGTONE_RE 0x3f
1948#define BSIGTONE_IM 0x7f00
1949#define BCOUNTER_CCA 0xffff
1950#define BCOUNTER_PARITYFAIL 0xffff0000
1951#define BCOUNTER_RATEILLEGAL 0xffff
1952#define BCOUNTER_CRC8FAIL 0xffff0000
1953#define BCOUNTER_MCSNOSUPPORT 0xffff
1954#define BCOUNTER_FASTSYNC 0xffff
1955#define BSHORTCFO 0xfff
1956#define BSHORTCFOT_LENGTH 12
1957#define BSHORTCFOF_LENGTH 11
1958#define BLONGCFO 0x7ff
1959#define BLONGCFOT_LENGTH 11
1960#define BLONGCFOF_LENGTH 11
1961#define BTAILCFO 0x1fff
1962#define BTAILCFOT_LENGTH 13
1963#define BTAILCFOF_LENGTH 12
1964#define BNOISE_EN_PWDB 0xffff
1965#define BCC_POWER_DB 0xffff0000
1966#define BMOISE_PWDB 0xffff
1967#define BPOWERMEAST_LENGTH 10
1968#define BPOWERMEASF_LENGTH 3
1969#define BRX_HT_BW 0x1
1970#define BRXSC 0x6
1971#define BRX_HT 0x8
1972#define BNB_INTF_DET_ON 0x1
1973#define BINTF_WIN_LEN_CFG 0x30
1974#define BNB_INTF_TH_CFG 0x1c0
1975#define BRFGAIN 0x3f
1976#define BTABLESEL 0x40
1977#define BTRSW 0x80
1978#define BRXSNR_A 0xff
1979#define BRXSNR_B 0xff00
1980#define BRXSNR_C 0xff0000
1981#define BRXSNR_D 0xff000000
1982#define BSNR_EVMT_LENGTH 8
1983#define BSNR_EVMF_LENGTH 1
1984#define BCSI1ST 0xff
1985#define BCSI2ND 0xff00
1986#define BRXEVM1ST 0xff0000
1987#define BRXEVM2ND 0xff000000
1988#define BSIGEVM 0xff
1989#define BPWDB 0xff00
1990#define BSGIEN 0x10000
1991
1992#define BSFACTOR_QMA1 0xf
1993#define BSFACTOR_QMA2 0xf0
1994#define BSFACTOR_QMA3 0xf00
1995#define BSFACTOR_QMA4 0xf000
1996#define BSFACTOR_QMA5 0xf0000
1997#define BSFACTOR_QMA6 0xf0000
1998#define BSFACTOR_QMA7 0xf00000
1999#define BSFACTOR_QMA8 0xf000000
2000#define BSFACTOR_QMA9 0xf0000000
2001#define BCSI_SCHEME 0x100000
2002
2003#define BNOISE_LVL_TOP_SET 0x3
2004#define BCHSMOOTH 0x4
2005#define BCHSMOOTH_CFG1 0x38
2006#define BCHSMOOTH_CFG2 0x1c0
2007#define BCHSMOOTH_CFG3 0xe00
2008#define BCHSMOOTH_CFG4 0x7000
2009#define BMRCMODE 0x800000
2010#define BTHEVMCFG 0x7000000
2011
2012#define BLOOP_FIT_TYPE 0x1
2013#define BUPD_CFO 0x40
2014#define BUPD_CFO_OFFDATA 0x80
2015#define BADV_UPD_CFO 0x100
2016#define BADV_TIME_CTRL 0x800
2017#define BUPD_CLKO 0x1000
2018#define BFC 0x6000
2019#define BTRACKING_MODE 0x8000
2020#define BPHCMP_ENABLE 0x10000
2021#define BUPD_CLKO_LTF 0x20000
2022#define BCOM_CH_CFO 0x40000
2023#define BCSI_ESTI_MODE 0x80000
2024#define BADV_UPD_EQZ 0x100000
2025#define BUCHCFG 0x7000000
2026#define BUPDEQZ 0x8000000
2027
2028#define BRX_PESUDO_NOISE_ON 0x20000000
2029#define BRX_PESUDO_NOISE_A 0xff
2030#define BRX_PESUDO_NOISE_B 0xff00
2031#define BRX_PESUDO_NOISE_C 0xff0000
2032#define BRX_PESUDO_NOISE_D 0xff000000
2033#define BRX_PESUDO_NOISESTATE_A 0xffff
2034#define BRX_PESUDO_NOISESTATE_B 0xffff0000
2035#define BRX_PESUDO_NOISESTATE_C 0xffff
2036#define BRX_PESUDO_NOISESTATE_D 0xffff0000
2037
2038#define BZEBRA1_HSSIENABLE 0x8
2039#define BZEBRA1_TRXCONTROL 0xc00
2040#define BZEBRA1_TRXGAINSETTING 0x07f
2041#define BZEBRA1_RXCOUNTER 0xc00
2042#define BZEBRA1_TXCHANGEPUMP 0x38
2043#define BZEBRA1_RXCHANGEPUMP 0x7
2044#define BZEBRA1_CHANNEL_NUM 0xf80
2045#define BZEBRA1_TXLPFBW 0x400
2046#define BZEBRA1_RXLPFBW 0x600
2047
2048#define BRTL8256REG_MODE_CTRL1 0x100
2049#define BRTL8256REG_MODE_CTRL0 0x40
2050#define BRTL8256REG_TXLPFBW 0x18
2051#define BRTL8256REG_RXLPFBW 0x600
2052
2053#define BRTL8258_TXLPFBW 0xc
2054#define BRTL8258_RXLPFBW 0xc00
2055#define BRTL8258_RSSILPFBW 0xc0
2056
2057#define BBYTE0 0x1
2058#define BBYTE1 0x2
2059#define BBYTE2 0x4
2060#define BBYTE3 0x8
2061#define BWORD0 0x3
2062#define BWORD1 0xc
2063#define BWORD 0xf
2064
2065#define MASKBYTE0 0xff
2066#define MASKBYTE1 0xff00
2067#define MASKBYTE2 0xff0000
2068#define MASKBYTE3 0xff000000
2069#define MASKHWORD 0xffff0000
2070#define MASKLWORD 0x0000ffff
2071#define MASKDWORD 0xffffffff
2072#define MASK12BITS 0xfff
2073#define MASKH4BITS 0xf0000000
2074#define MASKOFDM_D 0xffc00000
2075#define MASKCCK 0x3f3f3f3f
2076
2077#define MASK4BITS 0x0f
2078#define MASK20BITS 0xfffff
2079#define RFREG_OFFSET_MASK 0xfffff
2080
2081#define BENABLE 0x1
2082#define BDISABLE 0x0
2083
2084#define LEFT_ANTENNA 0x0
2085#define RIGHT_ANTENNA 0x1
2086
2087#define TCHECK_TXSTATUS 500
2088#define TUPDATE_RXCOUNTER 100
2089
2090#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
new file mode 100644
index 000000000000..90d0f2cf3b27
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
@@ -0,0 +1,523 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "reg.h"
32#include "def.h"
33#include "phy.h"
34#include "rf.h"
35#include "dm.h"
36
37static bool _rtl92ce_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
38
39void rtl92ce_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
40{
41 struct rtl_priv *rtlpriv = rtl_priv(hw);
42 struct rtl_phy *rtlphy = &(rtlpriv->phy);
43
44 switch (bandwidth) {
45 case HT_CHANNEL_WIDTH_20:
46 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
47 0xfffff3ff) | 0x0400);
48 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
49 rtlphy->rfreg_chnlval[0]);
50 break;
51 case HT_CHANNEL_WIDTH_20_40:
52 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
53 0xfffff3ff));
54 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
55 rtlphy->rfreg_chnlval[0]);
56 break;
57 default:
58 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
59 ("unknown bandwidth: %#X\n", bandwidth));
60 break;
61 }
62}
63
64void rtl92ce_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
65 u8 *ppowerlevel)
66{
67 struct rtl_priv *rtlpriv = rtl_priv(hw);
68 struct rtl_phy *rtlphy = &(rtlpriv->phy);
69 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
70 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
71 u32 tx_agc[2] = {0, 0}, tmpval;
72 bool turbo_scanoff = false;
73 u8 idx1, idx2;
74 u8 *ptr;
75
76 if (rtlefuse->eeprom_regulatory != 0)
77 turbo_scanoff = true;
78
79 if (mac->act_scanning == true) {
80 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
81 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
82
83 if (turbo_scanoff) {
84 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
85 tx_agc[idx1] = ppowerlevel[idx1] |
86 (ppowerlevel[idx1] << 8) |
87 (ppowerlevel[idx1] << 16) |
88 (ppowerlevel[idx1] << 24);
89 }
90 }
91 } else {
92 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
93 tx_agc[idx1] = ppowerlevel[idx1] |
94 (ppowerlevel[idx1] << 8) |
95 (ppowerlevel[idx1] << 16) |
96 (ppowerlevel[idx1] << 24);
97 }
98
99 if (rtlefuse->eeprom_regulatory == 0) {
100 tmpval =
101 (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
102 (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
103 8);
104 tx_agc[RF90_PATH_A] += tmpval;
105
106 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
107 (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
108 24);
109 tx_agc[RF90_PATH_B] += tmpval;
110 }
111 }
112
113 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
114 ptr = (u8 *) (&(tx_agc[idx1]));
115 for (idx2 = 0; idx2 < 4; idx2++) {
116 if (*ptr > RF6052_MAX_TX_PWR)
117 *ptr = RF6052_MAX_TX_PWR;
118 ptr++;
119 }
120 }
121
122 tmpval = tx_agc[RF90_PATH_A] & 0xff;
123 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
124
125 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
126 ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
127 RTXAGC_A_CCK1_MCS32));
128
129 tmpval = tx_agc[RF90_PATH_A] >> 8;
130
131 tmpval = tmpval & 0xff00ffff;
132
133 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
134
135 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
136 ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
137 RTXAGC_B_CCK11_A_CCK2_11));
138
139 tmpval = tx_agc[RF90_PATH_B] >> 24;
140 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
141
142 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
143 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
144 RTXAGC_B_CCK11_A_CCK2_11));
145
146 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
147 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
148
149 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
150 ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
151 RTXAGC_B_CCK1_55_MCS32));
152}
153
154static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
155 u8 *ppowerlevel, u8 channel,
156 u32 *ofdmbase, u32 *mcsbase)
157{
158 struct rtl_priv *rtlpriv = rtl_priv(hw);
159 struct rtl_phy *rtlphy = &(rtlpriv->phy);
160 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
161 u32 powerBase0, powerBase1;
162 u8 legacy_pwrdiff, ht20_pwrdiff;
163 u8 i, powerlevel[2];
164
165 for (i = 0; i < 2; i++) {
166 powerlevel[i] = ppowerlevel[i];
167 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
168 powerBase0 = powerlevel[i] + legacy_pwrdiff;
169
170 powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
171 (powerBase0 << 8) | powerBase0;
172 *(ofdmbase + i) = powerBase0;
173 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
174 (" [OFDM power base index rf(%c) = 0x%x]\n",
175 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
176 }
177
178 for (i = 0; i < 2; i++) {
179 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
180 ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
181 powerlevel[i] += ht20_pwrdiff;
182 }
183 powerBase1 = powerlevel[i];
184 powerBase1 = (powerBase1 << 24) |
185 (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
186
187 *(mcsbase + i) = powerBase1;
188
189 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
190 (" [MCS power base index rf(%c) = 0x%x]\n",
191 ((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
192 }
193}
194
195static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
196 u8 channel, u8 index,
197 u32 *powerBase0,
198 u32 *powerBase1,
199 u32 *p_outwriteval)
200{
201 struct rtl_priv *rtlpriv = rtl_priv(hw);
202 struct rtl_phy *rtlphy = &(rtlpriv->phy);
203 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
204 u8 i, chnlgroup = 0, pwr_diff_limit[4];
205 u32 writeVal, customer_limit, rf;
206
207 for (rf = 0; rf < 2; rf++) {
208 switch (rtlefuse->eeprom_regulatory) {
209 case 0:
210 chnlgroup = 0;
211
212 writeVal =
213 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
214 (rf ? 8 : 0)]
215 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
216
217 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
218 ("RTK better performance, "
219 "writeVal(%c) = 0x%x\n",
220 ((rf == 0) ? 'A' : 'B'), writeVal));
221 break;
222 case 1:
223 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
224 writeVal = ((index < 2) ? powerBase0[rf] :
225 powerBase1[rf]);
226
227 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
228 ("Realtek regulatory, 40MHz, "
229 "writeVal(%c) = 0x%x\n",
230 ((rf == 0) ? 'A' : 'B'), writeVal));
231 } else {
232 if (rtlphy->pwrgroup_cnt == 1)
233 chnlgroup = 0;
234 if (rtlphy->pwrgroup_cnt >= 3) {
235 if (channel <= 3)
236 chnlgroup = 0;
237 else if (channel >= 4 && channel <= 9)
238 chnlgroup = 1;
239 else if (channel > 9)
240 chnlgroup = 2;
241 if (rtlphy->pwrgroup_cnt == 4)
242 chnlgroup++;
243 }
244
245 writeVal =
246 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
247 [index + (rf ? 8 : 0)] + ((index < 2) ?
248 powerBase0[rf] :
249 powerBase1[rf]);
250
251 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
252 ("Realtek regulatory, 20MHz, "
253 "writeVal(%c) = 0x%x\n",
254 ((rf == 0) ? 'A' : 'B'), writeVal));
255 }
256 break;
257 case 2:
258 writeVal =
259 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
260
261 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
262 ("Better regulatory, "
263 "writeVal(%c) = 0x%x\n",
264 ((rf == 0) ? 'A' : 'B'), writeVal));
265 break;
266 case 3:
267 chnlgroup = 0;
268
269 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
270 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
271 ("customer's limit, 40MHz "
272 "rf(%c) = 0x%x\n",
273 ((rf == 0) ? 'A' : 'B'),
274 rtlefuse->pwrgroup_ht40[rf][channel -
275 1]));
276 } else {
277 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
278 ("customer's limit, 20MHz "
279 "rf(%c) = 0x%x\n",
280 ((rf == 0) ? 'A' : 'B'),
281 rtlefuse->pwrgroup_ht20[rf][channel -
282 1]));
283 }
284 for (i = 0; i < 4; i++) {
285 pwr_diff_limit[i] =
286 (u8) ((rtlphy->mcs_txpwrlevel_origoffset
287 [chnlgroup][index +
288 (rf ? 8 : 0)] & (0x7f << (i * 8))) >>
289 (i * 8));
290
291 if (rtlphy->current_chan_bw ==
292 HT_CHANNEL_WIDTH_20_40) {
293 if (pwr_diff_limit[i] >
294 rtlefuse->
295 pwrgroup_ht40[rf][channel - 1])
296 pwr_diff_limit[i] =
297 rtlefuse->pwrgroup_ht40[rf]
298 [channel - 1];
299 } else {
300 if (pwr_diff_limit[i] >
301 rtlefuse->
302 pwrgroup_ht20[rf][channel - 1])
303 pwr_diff_limit[i] =
304 rtlefuse->pwrgroup_ht20[rf]
305 [channel - 1];
306 }
307 }
308
309 customer_limit = (pwr_diff_limit[3] << 24) |
310 (pwr_diff_limit[2] << 16) |
311 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
312
313 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
314 ("Customer's limit rf(%c) = 0x%x\n",
315 ((rf == 0) ? 'A' : 'B'), customer_limit));
316
317 writeVal = customer_limit +
318 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
319
320 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
321 ("Customer, writeVal rf(%c)= 0x%x\n",
322 ((rf == 0) ? 'A' : 'B'), writeVal));
323 break;
324 default:
325 chnlgroup = 0;
326 writeVal =
327 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
328 [index + (rf ? 8 : 0)]
329 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
330
331 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
332 ("RTK better performance, writeVal "
333 "rf(%c) = 0x%x\n",
334 ((rf == 0) ? 'A' : 'B'), writeVal));
335 break;
336 }
337
338 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
339 writeVal = writeVal - 0x06060606;
340 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
341 TXHIGHPWRLEVEL_BT2)
342 writeVal = writeVal - 0x0c0c0c0c;
343 *(p_outwriteval + rf) = writeVal;
344 }
345}
346
347static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw,
348 u8 index, u32 *pValue)
349{
350 struct rtl_priv *rtlpriv = rtl_priv(hw);
351 struct rtl_phy *rtlphy = &(rtlpriv->phy);
352
353 u16 regoffset_a[6] = {
354 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
355 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
356 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
357 };
358 u16 regoffset_b[6] = {
359 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
360 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
361 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
362 };
363 u8 i, rf, pwr_val[4];
364 u32 writeVal;
365 u16 regoffset;
366
367 for (rf = 0; rf < 2; rf++) {
368 writeVal = pValue[rf];
369 for (i = 0; i < 4; i++) {
370 pwr_val[i] = (u8) ((writeVal & (0x7f <<
371 (i * 8))) >> (i * 8));
372
373 if (pwr_val[i] > RF6052_MAX_TX_PWR)
374 pwr_val[i] = RF6052_MAX_TX_PWR;
375 }
376 writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
377 (pwr_val[1] << 8) | pwr_val[0];
378
379 if (rf == 0)
380 regoffset = regoffset_a[index];
381 else
382 regoffset = regoffset_b[index];
383 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
384
385 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
386 ("Set 0x%x = %08x\n", regoffset, writeVal));
387
388 if (((get_rf_type(rtlphy) == RF_2T2R) &&
389 (regoffset == RTXAGC_A_MCS15_MCS12 ||
390 regoffset == RTXAGC_B_MCS15_MCS12)) ||
391 ((get_rf_type(rtlphy) != RF_2T2R) &&
392 (regoffset == RTXAGC_A_MCS07_MCS04 ||
393 regoffset == RTXAGC_B_MCS07_MCS04))) {
394
395 writeVal = pwr_val[3];
396 if (regoffset == RTXAGC_A_MCS15_MCS12 ||
397 regoffset == RTXAGC_A_MCS07_MCS04)
398 regoffset = 0xc90;
399 if (regoffset == RTXAGC_B_MCS15_MCS12 ||
400 regoffset == RTXAGC_B_MCS07_MCS04)
401 regoffset = 0xc98;
402
403 for (i = 0; i < 3; i++) {
404 writeVal = (writeVal > 6) ? (writeVal - 6) : 0;
405 rtl_write_byte(rtlpriv, (u32) (regoffset + i),
406 (u8) writeVal);
407 }
408 }
409 }
410}
411
412void rtl92ce_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
413 u8 *ppowerlevel, u8 channel)
414{
415 u32 writeVal[2], powerBase0[2], powerBase1[2];
416 u8 index;
417
418 rtl92c_phy_get_power_base(hw, ppowerlevel,
419 channel, &powerBase0[0], &powerBase1[0]);
420
421 for (index = 0; index < 6; index++) {
422 _rtl92c_get_txpower_writeval_by_regulatory(hw,
423 channel, index,
424 &powerBase0[0],
425 &powerBase1[0],
426 &writeVal[0]);
427
428 _rtl92c_write_ofdm_power_reg(hw, index, &writeVal[0]);
429 }
430}
431
432bool rtl92ce_phy_rf6052_config(struct ieee80211_hw *hw)
433{
434 struct rtl_priv *rtlpriv = rtl_priv(hw);
435 struct rtl_phy *rtlphy = &(rtlpriv->phy);
436
437 if (rtlphy->rf_type == RF_1T1R)
438 rtlphy->num_total_rfpath = 1;
439 else
440 rtlphy->num_total_rfpath = 2;
441
442 return _rtl92ce_phy_rf6052_config_parafile(hw);
443
444}
445
446static bool _rtl92ce_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
447{
448 struct rtl_priv *rtlpriv = rtl_priv(hw);
449 struct rtl_phy *rtlphy = &(rtlpriv->phy);
450 u32 u4_regvalue = 0;
451 u8 rfpath;
452 bool rtstatus = true;
453 struct bb_reg_def *pphyreg;
454
455 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
456
457 pphyreg = &rtlphy->phyreg_def[rfpath];
458
459 switch (rfpath) {
460 case RF90_PATH_A:
461 case RF90_PATH_C:
462 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
463 BRFSI_RFENV);
464 break;
465 case RF90_PATH_B:
466 case RF90_PATH_D:
467 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
468 BRFSI_RFENV << 16);
469 break;
470 }
471
472 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
473 udelay(1);
474
475 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
476 udelay(1);
477
478 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
479 B3WIREADDREAALENGTH, 0x0);
480 udelay(1);
481
482 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
483 udelay(1);
484
485 switch (rfpath) {
486 case RF90_PATH_A:
487 rtstatus = rtl92c_phy_config_rf_with_headerfile(hw,
488 (enum radio_path)rfpath);
489 break;
490 case RF90_PATH_B:
491 rtstatus = rtl92c_phy_config_rf_with_headerfile(hw,
492 (enum radio_path)rfpath);
493 break;
494 case RF90_PATH_C:
495 break;
496 case RF90_PATH_D:
497 break;
498 }
499
500 switch (rfpath) {
501 case RF90_PATH_A:
502 case RF90_PATH_C:
503 rtl_set_bbreg(hw, pphyreg->rfintfs,
504 BRFSI_RFENV, u4_regvalue);
505 break;
506 case RF90_PATH_B:
507 case RF90_PATH_D:
508 rtl_set_bbreg(hw, pphyreg->rfintfs,
509 BRFSI_RFENV << 16, u4_regvalue);
510 break;
511 }
512
513 if (rtstatus != true) {
514 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
515 ("Radio[%d] Fail!!", rfpath));
516 return false;
517 }
518
519 }
520
521 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("<---\n"));
522 return rtstatus;
523}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.h b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.h
new file mode 100644
index 000000000000..39ff03685986
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.h
@@ -0,0 +1,44 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_RF_H__
31#define __RTL92C_RF_H__
32
33#define RF6052_MAX_TX_PWR 0x3F
34#define RF6052_MAX_REG 0x3F
35#define RF6052_MAX_PATH 2
36
37extern void rtl92ce_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
38 u8 bandwidth);
39extern void rtl92ce_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
40 u8 *ppowerlevel);
41extern void rtl92ce_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
42 u8 *ppowerlevel, u8 channel);
43extern bool rtl92ce_phy_rf6052_config(struct ieee80211_hw *hw);
44#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c
new file mode 100644
index 000000000000..373dc78af1dc
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c
@@ -0,0 +1,394 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include <linux/vmalloc.h>
31
32#include "../wifi.h"
33#include "../core.h"
34#include "../pci.h"
35#include "reg.h"
36#include "def.h"
37#include "phy.h"
38#include "dm.h"
39#include "hw.h"
40#include "rf.h"
41#include "sw.h"
42#include "trx.h"
43#include "led.h"
44
45static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw)
46{
47 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
48
49 /*close ASPM for AMD defaultly */
50 rtlpci->const_amdpci_aspm = 0;
51
52 /*
53 * ASPM PS mode.
54 * 0 - Disable ASPM,
55 * 1 - Enable ASPM without Clock Req,
56 * 2 - Enable ASPM with Clock Req,
57 * 3 - Alwyas Enable ASPM with Clock Req,
58 * 4 - Always Enable ASPM without Clock Req.
59 * set defult to RTL8192CE:3 RTL8192E:2
60 * */
61 rtlpci->const_pci_aspm = 3;
62
63 /*Setting for PCI-E device */
64 rtlpci->const_devicepci_aspm_setting = 0x03;
65
66 /*Setting for PCI-E bridge */
67 rtlpci->const_hostpci_aspm_setting = 0x02;
68
69 /*
70 * In Hw/Sw Radio Off situation.
71 * 0 - Default,
72 * 1 - From ASPM setting without low Mac Pwr,
73 * 2 - From ASPM setting with low Mac Pwr,
74 * 3 - Bus D3
75 * set default to RTL8192CE:0 RTL8192SE:2
76 */
77 rtlpci->const_hwsw_rfoff_d3 = 0;
78
79 /*
80 * This setting works for those device with
81 * backdoor ASPM setting such as EPHY setting.
82 * 0 - Not support ASPM,
83 * 1 - Support ASPM,
84 * 2 - According to chipset.
85 */
86 rtlpci->const_support_pciaspm = 1;
87}
88
89int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
90{
91 int err;
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
94 const struct firmware *firmware;
95
96 rtl8192ce_bt_reg_init(hw);
97
98 rtlpriv->dm.dm_initialgain_enable = 1;
99 rtlpriv->dm.dm_flag = 0;
100 rtlpriv->dm.disable_framebursting = 0;
101 rtlpriv->dm.thermalvalue = 0;
102 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
103
104 /* compatible 5G band 88ce just 2.4G band & smsp */
105 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
106 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
107 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
108
109 rtlpci->receive_config = (RCR_APPFCS |
110 RCR_AMF |
111 RCR_ADF |
112 RCR_APP_MIC |
113 RCR_APP_ICV |
114 RCR_AICV |
115 RCR_ACRC32 |
116 RCR_AB |
117 RCR_AM |
118 RCR_APM |
119 RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0);
120
121 rtlpci->irq_mask[0] =
122 (u32) (IMR_ROK |
123 IMR_VODOK |
124 IMR_VIDOK |
125 IMR_BEDOK |
126 IMR_BKDOK |
127 IMR_MGNTDOK |
128 IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0);
129
130 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0);
131
132 /* for LPS & IPS */
133 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
134 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
135 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
136 rtlpriv->psc.reg_fwctrl_lps = 3;
137 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
138 /* for ASPM, you can close aspm through
139 * set const_support_pciaspm = 0 */
140 rtl92c_init_aspm_vars(hw);
141
142 if (rtlpriv->psc.reg_fwctrl_lps == 1)
143 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
144 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
145 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
146 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
147 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
148
149 /* for firmware buf */
150 rtlpriv->rtlhal.pfirmware = vzalloc(0x4000);
151 if (!rtlpriv->rtlhal.pfirmware) {
152 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
153 ("Can't alloc buffer for fw.\n"));
154 return 1;
155 }
156
157 /* request fw */
158 err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
159 rtlpriv->io.dev);
160 if (err) {
161 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
162 ("Failed to request firmware!\n"));
163 return 1;
164 }
165 if (firmware->size > 0x4000) {
166 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
167 ("Firmware is too big!\n"));
168 release_firmware(firmware);
169 return 1;
170 }
171 memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
172 rtlpriv->rtlhal.fwsize = firmware->size;
173 release_firmware(firmware);
174
175 return 0;
176}
177
178void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw)
179{
180 struct rtl_priv *rtlpriv = rtl_priv(hw);
181
182 if (rtlpriv->rtlhal.pfirmware) {
183 vfree(rtlpriv->rtlhal.pfirmware);
184 rtlpriv->rtlhal.pfirmware = NULL;
185 }
186}
187
188static struct rtl_hal_ops rtl8192ce_hal_ops = {
189 .init_sw_vars = rtl92c_init_sw_vars,
190 .deinit_sw_vars = rtl92c_deinit_sw_vars,
191 .read_eeprom_info = rtl92ce_read_eeprom_info,
192 .interrupt_recognized = rtl92ce_interrupt_recognized,
193 .hw_init = rtl92ce_hw_init,
194 .hw_disable = rtl92ce_card_disable,
195 .hw_suspend = rtl92ce_suspend,
196 .hw_resume = rtl92ce_resume,
197 .enable_interrupt = rtl92ce_enable_interrupt,
198 .disable_interrupt = rtl92ce_disable_interrupt,
199 .set_network_type = rtl92ce_set_network_type,
200 .set_chk_bssid = rtl92ce_set_check_bssid,
201 .set_qos = rtl92ce_set_qos,
202 .set_bcn_reg = rtl92ce_set_beacon_related_registers,
203 .set_bcn_intv = rtl92ce_set_beacon_interval,
204 .update_interrupt_mask = rtl92ce_update_interrupt_mask,
205 .get_hw_reg = rtl92ce_get_hw_reg,
206 .set_hw_reg = rtl92ce_set_hw_reg,
207 .update_rate_tbl = rtl92ce_update_hal_rate_tbl,
208 .fill_tx_desc = rtl92ce_tx_fill_desc,
209 .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc,
210 .query_rx_desc = rtl92ce_rx_query_desc,
211 .set_channel_access = rtl92ce_update_channel_access_setting,
212 .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking,
213 .set_bw_mode = rtl92c_phy_set_bw_mode,
214 .switch_channel = rtl92c_phy_sw_chnl,
215 .dm_watchdog = rtl92c_dm_watchdog,
216 .scan_operation_backup = rtl92c_phy_scan_operation_backup,
217 .set_rf_power_state = rtl92c_phy_set_rf_power_state,
218 .led_control = rtl92ce_led_control,
219 .set_desc = rtl92ce_set_desc,
220 .get_desc = rtl92ce_get_desc,
221 .tx_polling = rtl92ce_tx_polling,
222 .enable_hw_sec = rtl92ce_enable_hw_security_config,
223 .set_key = rtl92ce_set_key,
224 .init_sw_leds = rtl92ce_init_sw_leds,
225 .get_bbreg = rtl92c_phy_query_bb_reg,
226 .set_bbreg = rtl92c_phy_set_bb_reg,
227 .set_rfreg = rtl92ce_phy_set_rf_reg,
228 .get_rfreg = rtl92c_phy_query_rf_reg,
229 .phy_rf6052_config = rtl92ce_phy_rf6052_config,
230 .phy_rf6052_set_cck_txpower = rtl92ce_phy_rf6052_set_cck_txpower,
231 .phy_rf6052_set_ofdm_txpower = rtl92ce_phy_rf6052_set_ofdm_txpower,
232 .config_bb_with_headerfile = _rtl92ce_phy_config_bb_with_headerfile,
233 .config_bb_with_pgheaderfile = _rtl92ce_phy_config_bb_with_pgheaderfile,
234 .phy_lc_calibrate = _rtl92ce_phy_lc_calibrate,
235 .phy_set_bw_mode_callback = rtl92ce_phy_set_bw_mode_callback,
236 .dm_dynamic_txpower = rtl92ce_dm_dynamic_txpower,
237};
238
239static struct rtl_mod_params rtl92ce_mod_params = {
240 .sw_crypto = false,
241 .inactiveps = true,
242 .swctrl_lps = false,
243 .fwctrl_lps = true,
244};
245
246static struct rtl_hal_cfg rtl92ce_hal_cfg = {
247 .bar_id = 2,
248 .write_readback = true,
249 .name = "rtl92c_pci",
250 .fw_name = "rtlwifi/rtl8192cfw.bin",
251 .ops = &rtl8192ce_hal_ops,
252 .mod_params = &rtl92ce_mod_params,
253
254 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
255 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
256 .maps[SYS_CLK] = REG_SYS_CLKR,
257 .maps[MAC_RCR_AM] = AM,
258 .maps[MAC_RCR_AB] = AB,
259 .maps[MAC_RCR_ACRC32] = ACRC32,
260 .maps[MAC_RCR_ACF] = ACF,
261 .maps[MAC_RCR_AAP] = AAP,
262
263 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
264 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
265 .maps[EFUSE_CLK] = 0,
266 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
267 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
268 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
269 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
270 .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
271 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
272 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
273 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
274
275 .maps[RWCAM] = REG_CAMCMD,
276 .maps[WCAMI] = REG_CAMWRITE,
277 .maps[RCAMO] = REG_CAMREAD,
278 .maps[CAMDBG] = REG_CAMDBG,
279 .maps[SECR] = REG_SECCFG,
280 .maps[SEC_CAM_NONE] = CAM_NONE,
281 .maps[SEC_CAM_WEP40] = CAM_WEP40,
282 .maps[SEC_CAM_TKIP] = CAM_TKIP,
283 .maps[SEC_CAM_AES] = CAM_AES,
284 .maps[SEC_CAM_WEP104] = CAM_WEP104,
285
286 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
287 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
288 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
289 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
290 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
291 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
292 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
293 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
294 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
295 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
296 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
297 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
298 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
299 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
300 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
301 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
302
303 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
304 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
305 .maps[RTL_IMR_BcnInt] = IMR_BCNINT,
306 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
307 .maps[RTL_IMR_RDU] = IMR_RDU,
308 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
309 .maps[RTL_IMR_BDOK] = IMR_BDOK,
310 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
311 .maps[RTL_IMR_TBDER] = IMR_TBDER,
312 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
313 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
314 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
315 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
316 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
317 .maps[RTL_IMR_VODOK] = IMR_VODOK,
318 .maps[RTL_IMR_ROK] = IMR_ROK,
319 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
320
321 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
322 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
323 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
324 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
325 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
326 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
327 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
328 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
329 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
330 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
331 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
332 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
333
334 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
335 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
336};
337
338DEFINE_PCI_DEVICE_TABLE(rtl92ce_pci_ids) = {
339 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)},
340 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)},
341 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)},
342 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)},
343 {},
344};
345
346MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids);
347
348MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
349MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
350MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
351MODULE_LICENSE("GPL");
352MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless");
353MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin");
354
355module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444);
356module_param_named(ips, rtl92ce_mod_params.inactiveps, bool, 0444);
357module_param_named(swlps, rtl92ce_mod_params.swctrl_lps, bool, 0444);
358module_param_named(fwlps, rtl92ce_mod_params.fwctrl_lps, bool, 0444);
359MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
360MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n");
361MODULE_PARM_DESC(fwlps, "using linked fw control power save "
362 "(default 1 is open)\n");
363
364static struct pci_driver rtl92ce_driver = {
365 .name = KBUILD_MODNAME,
366 .id_table = rtl92ce_pci_ids,
367 .probe = rtl_pci_probe,
368 .remove = rtl_pci_disconnect,
369
370#ifdef CONFIG_PM
371 .suspend = rtl_pci_suspend,
372 .resume = rtl_pci_resume,
373#endif
374
375};
376
377static int __init rtl92ce_module_init(void)
378{
379 int ret;
380
381 ret = pci_register_driver(&rtl92ce_driver);
382 if (ret)
383 RT_ASSERT(false, (": No device found\n"));
384
385 return ret;
386}
387
388static void __exit rtl92ce_module_exit(void)
389{
390 pci_unregister_driver(&rtl92ce_driver);
391}
392
393module_init(rtl92ce_module_init);
394module_exit(rtl92ce_module_exit);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/sw.h b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.h
new file mode 100644
index 000000000000..b7dc3263e433
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.h
@@ -0,0 +1,41 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CE_SW_H__
31#define __RTL92CE_SW_H__
32
33int rtl92c_init_sw_vars(struct ieee80211_hw *hw);
34void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw);
35void rtl92c_init_var_map(struct ieee80211_hw *hw);
36bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
37 u8 configtype);
38bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
39 u8 configtype);
40
41#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/table.c b/drivers/net/wireless/rtlwifi/rtl8192ce/table.c
new file mode 100644
index 000000000000..ba938b91aa6f
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/table.c
@@ -0,0 +1,1224 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Created on 2010/ 5/18, 1:41
27 *
28 * Larry Finger <Larry.Finger@lwfinger.net>
29 *
30 *****************************************************************************/
31
32#include "table.h"
33
34
35u32 RTL8192CEPHY_REG_2TARRAY[PHY_REG_2TARRAY_LENGTH] = {
36 0x024, 0x0011800f,
37 0x028, 0x00ffdb83,
38 0x800, 0x80040002,
39 0x804, 0x00000003,
40 0x808, 0x0000fc00,
41 0x80c, 0x0000000a,
42 0x810, 0x10005388,
43 0x814, 0x020c3d10,
44 0x818, 0x02200385,
45 0x81c, 0x00000000,
46 0x820, 0x01000100,
47 0x824, 0x00390004,
48 0x828, 0x01000100,
49 0x82c, 0x00390004,
50 0x830, 0x27272727,
51 0x834, 0x27272727,
52 0x838, 0x27272727,
53 0x83c, 0x27272727,
54 0x840, 0x00010000,
55 0x844, 0x00010000,
56 0x848, 0x27272727,
57 0x84c, 0x27272727,
58 0x850, 0x00000000,
59 0x854, 0x00000000,
60 0x858, 0x569a569a,
61 0x85c, 0x0c1b25a4,
62 0x860, 0x66e60230,
63 0x864, 0x061f0130,
64 0x868, 0x27272727,
65 0x86c, 0x2b2b2b27,
66 0x870, 0x07000700,
67 0x874, 0x22184000,
68 0x878, 0x08080808,
69 0x87c, 0x00000000,
70 0x880, 0xc0083070,
71 0x884, 0x000004d5,
72 0x888, 0x00000000,
73 0x88c, 0xcc0000c0,
74 0x890, 0x00000800,
75 0x894, 0xfffffffe,
76 0x898, 0x40302010,
77 0x89c, 0x00706050,
78 0x900, 0x00000000,
79 0x904, 0x00000023,
80 0x908, 0x00000000,
81 0x90c, 0x81121313,
82 0xa00, 0x00d047c8,
83 0xa04, 0x80ff000c,
84 0xa08, 0x8c838300,
85 0xa0c, 0x2e68120f,
86 0xa10, 0x9500bb78,
87 0xa14, 0x11144028,
88 0xa18, 0x00881117,
89 0xa1c, 0x89140f00,
90 0xa20, 0x1a1b0000,
91 0xa24, 0x090e1317,
92 0xa28, 0x00000204,
93 0xa2c, 0x00d30000,
94 0xa70, 0x101fbf00,
95 0xa74, 0x00000007,
96 0xc00, 0x48071d40,
97 0xc04, 0x03a05633,
98 0xc08, 0x000000e4,
99 0xc0c, 0x6c6c6c6c,
100 0xc10, 0x08800000,
101 0xc14, 0x40000100,
102 0xc18, 0x08800000,
103 0xc1c, 0x40000100,
104 0xc20, 0x00000000,
105 0xc24, 0x00000000,
106 0xc28, 0x00000000,
107 0xc2c, 0x00000000,
108 0xc30, 0x69e9ac44,
109 0xc34, 0x469652cf,
110 0xc38, 0x49795994,
111 0xc3c, 0x0a97971c,
112 0xc40, 0x1f7c403f,
113 0xc44, 0x000100b7,
114 0xc48, 0xec020107,
115 0xc4c, 0x007f037f,
116 0xc50, 0x69543420,
117 0xc54, 0x43bc0094,
118 0xc58, 0x69543420,
119 0xc5c, 0x433c0094,
120 0xc60, 0x00000000,
121 0xc64, 0x5116848b,
122 0xc68, 0x47c00bff,
123 0xc6c, 0x00000036,
124 0xc70, 0x2c7f000d,
125 0xc74, 0x018610db,
126 0xc78, 0x0000001f,
127 0xc7c, 0x00b91612,
128 0xc80, 0x40000100,
129 0xc84, 0x20f60000,
130 0xc88, 0x40000100,
131 0xc8c, 0x20200000,
132 0xc90, 0x00121820,
133 0xc94, 0x00000000,
134 0xc98, 0x00121820,
135 0xc9c, 0x00007f7f,
136 0xca0, 0x00000000,
137 0xca4, 0x00000080,
138 0xca8, 0x00000000,
139 0xcac, 0x00000000,
140 0xcb0, 0x00000000,
141 0xcb4, 0x00000000,
142 0xcb8, 0x00000000,
143 0xcbc, 0x28000000,
144 0xcc0, 0x00000000,
145 0xcc4, 0x00000000,
146 0xcc8, 0x00000000,
147 0xccc, 0x00000000,
148 0xcd0, 0x00000000,
149 0xcd4, 0x00000000,
150 0xcd8, 0x64b22427,
151 0xcdc, 0x00766932,
152 0xce0, 0x00222222,
153 0xce4, 0x00000000,
154 0xce8, 0x37644302,
155 0xcec, 0x2f97d40c,
156 0xd00, 0x00080740,
157 0xd04, 0x00020403,
158 0xd08, 0x0000907f,
159 0xd0c, 0x20010201,
160 0xd10, 0xa0633333,
161 0xd14, 0x3333bc43,
162 0xd18, 0x7a8f5b6b,
163 0xd2c, 0xcc979975,
164 0xd30, 0x00000000,
165 0xd34, 0x80608000,
166 0xd38, 0x00000000,
167 0xd3c, 0x00027293,
168 0xd40, 0x00000000,
169 0xd44, 0x00000000,
170 0xd48, 0x00000000,
171 0xd4c, 0x00000000,
172 0xd50, 0x6437140a,
173 0xd54, 0x00000000,
174 0xd58, 0x00000000,
175 0xd5c, 0x30032064,
176 0xd60, 0x4653de68,
177 0xd64, 0x04518a3c,
178 0xd68, 0x00002101,
179 0xd6c, 0x2a201c16,
180 0xd70, 0x1812362e,
181 0xd74, 0x322c2220,
182 0xd78, 0x000e3c24,
183 0xe00, 0x2a2a2a2a,
184 0xe04, 0x2a2a2a2a,
185 0xe08, 0x03902a2a,
186 0xe10, 0x2a2a2a2a,
187 0xe14, 0x2a2a2a2a,
188 0xe18, 0x2a2a2a2a,
189 0xe1c, 0x2a2a2a2a,
190 0xe28, 0x00000000,
191 0xe30, 0x1000dc1f,
192 0xe34, 0x10008c1f,
193 0xe38, 0x02140102,
194 0xe3c, 0x681604c2,
195 0xe40, 0x01007c00,
196 0xe44, 0x01004800,
197 0xe48, 0xfb000000,
198 0xe4c, 0x000028d1,
199 0xe50, 0x1000dc1f,
200 0xe54, 0x10008c1f,
201 0xe58, 0x02140102,
202 0xe5c, 0x28160d05,
203 0xe60, 0x00000010,
204 0xe68, 0x001b25a4,
205 0xe6c, 0x63db25a4,
206 0xe70, 0x63db25a4,
207 0xe74, 0x0c1b25a4,
208 0xe78, 0x0c1b25a4,
209 0xe7c, 0x0c1b25a4,
210 0xe80, 0x0c1b25a4,
211 0xe84, 0x63db25a4,
212 0xe88, 0x0c1b25a4,
213 0xe8c, 0x63db25a4,
214 0xed0, 0x63db25a4,
215 0xed4, 0x63db25a4,
216 0xed8, 0x63db25a4,
217 0xedc, 0x001b25a4,
218 0xee0, 0x001b25a4,
219 0xeec, 0x6fdb25a4,
220 0xf14, 0x00000003,
221 0xf4c, 0x00000000,
222 0xf00, 0x00000300,
223};
224
225u32 RTL8192CEPHY_REG_1TARRAY[PHY_REG_1TARRAY_LENGTH] = {
226 0x024, 0x0011800f,
227 0x028, 0x00ffdb83,
228 0x800, 0x80040000,
229 0x804, 0x00000001,
230 0x808, 0x0000fc00,
231 0x80c, 0x0000000a,
232 0x810, 0x10005388,
233 0x814, 0x020c3d10,
234 0x818, 0x02200385,
235 0x81c, 0x00000000,
236 0x820, 0x01000100,
237 0x824, 0x00390004,
238 0x828, 0x00000000,
239 0x82c, 0x00000000,
240 0x830, 0x00000000,
241 0x834, 0x00000000,
242 0x838, 0x00000000,
243 0x83c, 0x00000000,
244 0x840, 0x00010000,
245 0x844, 0x00000000,
246 0x848, 0x00000000,
247 0x84c, 0x00000000,
248 0x850, 0x00000000,
249 0x854, 0x00000000,
250 0x858, 0x569a569a,
251 0x85c, 0x001b25a4,
252 0x860, 0x66e60230,
253 0x864, 0x061f0130,
254 0x868, 0x00000000,
255 0x86c, 0x32323200,
256 0x870, 0x07000700,
257 0x874, 0x22004000,
258 0x878, 0x00000808,
259 0x87c, 0x00000000,
260 0x880, 0xc0083070,
261 0x884, 0x000004d5,
262 0x888, 0x00000000,
263 0x88c, 0xccc000c0,
264 0x890, 0x00000800,
265 0x894, 0xfffffffe,
266 0x898, 0x40302010,
267 0x89c, 0x00706050,
268 0x900, 0x00000000,
269 0x904, 0x00000023,
270 0x908, 0x00000000,
271 0x90c, 0x81121111,
272 0xa00, 0x00d047c8,
273 0xa04, 0x80ff000c,
274 0xa08, 0x8c838300,
275 0xa0c, 0x2e68120f,
276 0xa10, 0x9500bb78,
277 0xa14, 0x11144028,
278 0xa18, 0x00881117,
279 0xa1c, 0x89140f00,
280 0xa20, 0x1a1b0000,
281 0xa24, 0x090e1317,
282 0xa28, 0x00000204,
283 0xa2c, 0x00d30000,
284 0xa70, 0x101fbf00,
285 0xa74, 0x00000007,
286 0xc00, 0x48071d40,
287 0xc04, 0x03a05611,
288 0xc08, 0x000000e4,
289 0xc0c, 0x6c6c6c6c,
290 0xc10, 0x08800000,
291 0xc14, 0x40000100,
292 0xc18, 0x08800000,
293 0xc1c, 0x40000100,
294 0xc20, 0x00000000,
295 0xc24, 0x00000000,
296 0xc28, 0x00000000,
297 0xc2c, 0x00000000,
298 0xc30, 0x69e9ac44,
299 0xc34, 0x469652cf,
300 0xc38, 0x49795994,
301 0xc3c, 0x0a97971c,
302 0xc40, 0x1f7c403f,
303 0xc44, 0x000100b7,
304 0xc48, 0xec020107,
305 0xc4c, 0x007f037f,
306 0xc50, 0x69543420,
307 0xc54, 0x43bc0094,
308 0xc58, 0x69543420,
309 0xc5c, 0x433c0094,
310 0xc60, 0x00000000,
311 0xc64, 0x5116848b,
312 0xc68, 0x47c00bff,
313 0xc6c, 0x00000036,
314 0xc70, 0x2c7f000d,
315 0xc74, 0x018610db,
316 0xc78, 0x0000001f,
317 0xc7c, 0x00b91612,
318 0xc80, 0x40000100,
319 0xc84, 0x20f60000,
320 0xc88, 0x40000100,
321 0xc8c, 0x20200000,
322 0xc90, 0x00121820,
323 0xc94, 0x00000000,
324 0xc98, 0x00121820,
325 0xc9c, 0x00007f7f,
326 0xca0, 0x00000000,
327 0xca4, 0x00000080,
328 0xca8, 0x00000000,
329 0xcac, 0x00000000,
330 0xcb0, 0x00000000,
331 0xcb4, 0x00000000,
332 0xcb8, 0x00000000,
333 0xcbc, 0x28000000,
334 0xcc0, 0x00000000,
335 0xcc4, 0x00000000,
336 0xcc8, 0x00000000,
337 0xccc, 0x00000000,
338 0xcd0, 0x00000000,
339 0xcd4, 0x00000000,
340 0xcd8, 0x64b22427,
341 0xcdc, 0x00766932,
342 0xce0, 0x00222222,
343 0xce4, 0x00000000,
344 0xce8, 0x37644302,
345 0xcec, 0x2f97d40c,
346 0xd00, 0x00080740,
347 0xd04, 0x00020401,
348 0xd08, 0x0000907f,
349 0xd0c, 0x20010201,
350 0xd10, 0xa0633333,
351 0xd14, 0x3333bc43,
352 0xd18, 0x7a8f5b6b,
353 0xd2c, 0xcc979975,
354 0xd30, 0x00000000,
355 0xd34, 0x80608000,
356 0xd38, 0x00000000,
357 0xd3c, 0x00027293,
358 0xd40, 0x00000000,
359 0xd44, 0x00000000,
360 0xd48, 0x00000000,
361 0xd4c, 0x00000000,
362 0xd50, 0x6437140a,
363 0xd54, 0x00000000,
364 0xd58, 0x00000000,
365 0xd5c, 0x30032064,
366 0xd60, 0x4653de68,
367 0xd64, 0x04518a3c,
368 0xd68, 0x00002101,
369 0xd6c, 0x2a201c16,
370 0xd70, 0x1812362e,
371 0xd74, 0x322c2220,
372 0xd78, 0x000e3c24,
373 0xe00, 0x2a2a2a2a,
374 0xe04, 0x2a2a2a2a,
375 0xe08, 0x03902a2a,
376 0xe10, 0x2a2a2a2a,
377 0xe14, 0x2a2a2a2a,
378 0xe18, 0x2a2a2a2a,
379 0xe1c, 0x2a2a2a2a,
380 0xe28, 0x00000000,
381 0xe30, 0x1000dc1f,
382 0xe34, 0x10008c1f,
383 0xe38, 0x02140102,
384 0xe3c, 0x681604c2,
385 0xe40, 0x01007c00,
386 0xe44, 0x01004800,
387 0xe48, 0xfb000000,
388 0xe4c, 0x000028d1,
389 0xe50, 0x1000dc1f,
390 0xe54, 0x10008c1f,
391 0xe58, 0x02140102,
392 0xe5c, 0x28160d05,
393 0xe60, 0x00000010,
394 0xe68, 0x001b25a4,
395 0xe6c, 0x631b25a0,
396 0xe70, 0x631b25a0,
397 0xe74, 0x081b25a0,
398 0xe78, 0x081b25a0,
399 0xe7c, 0x081b25a0,
400 0xe80, 0x081b25a0,
401 0xe84, 0x631b25a0,
402 0xe88, 0x081b25a0,
403 0xe8c, 0x631b25a0,
404 0xed0, 0x631b25a0,
405 0xed4, 0x631b25a0,
406 0xed8, 0x631b25a0,
407 0xedc, 0x001b25a0,
408 0xee0, 0x001b25a0,
409 0xeec, 0x6b1b25a0,
410 0xf14, 0x00000003,
411 0xf4c, 0x00000000,
412 0xf00, 0x00000300,
413};
414
415u32 RTL8192CEPHY_REG_ARRAY_PG[PHY_REG_ARRAY_PGLENGTH] = {
416 0xe00, 0xffffffff, 0x0a0c0c0c,
417 0xe04, 0xffffffff, 0x02040608,
418 0xe08, 0x0000ff00, 0x00000000,
419 0x86c, 0xffffff00, 0x00000000,
420 0xe10, 0xffffffff, 0x0a0c0d0e,
421 0xe14, 0xffffffff, 0x02040608,
422 0xe18, 0xffffffff, 0x0a0c0d0e,
423 0xe1c, 0xffffffff, 0x02040608,
424 0x830, 0xffffffff, 0x0a0c0c0c,
425 0x834, 0xffffffff, 0x02040608,
426 0x838, 0xffffff00, 0x00000000,
427 0x86c, 0x000000ff, 0x00000000,
428 0x83c, 0xffffffff, 0x0a0c0d0e,
429 0x848, 0xffffffff, 0x02040608,
430 0x84c, 0xffffffff, 0x0a0c0d0e,
431 0x868, 0xffffffff, 0x02040608,
432 0xe00, 0xffffffff, 0x00000000,
433 0xe04, 0xffffffff, 0x00000000,
434 0xe08, 0x0000ff00, 0x00000000,
435 0x86c, 0xffffff00, 0x00000000,
436 0xe10, 0xffffffff, 0x00000000,
437 0xe14, 0xffffffff, 0x00000000,
438 0xe18, 0xffffffff, 0x00000000,
439 0xe1c, 0xffffffff, 0x00000000,
440 0x830, 0xffffffff, 0x00000000,
441 0x834, 0xffffffff, 0x00000000,
442 0x838, 0xffffff00, 0x00000000,
443 0x86c, 0x000000ff, 0x00000000,
444 0x83c, 0xffffffff, 0x00000000,
445 0x848, 0xffffffff, 0x00000000,
446 0x84c, 0xffffffff, 0x00000000,
447 0x868, 0xffffffff, 0x00000000,
448 0xe00, 0xffffffff, 0x04040404,
449 0xe04, 0xffffffff, 0x00020204,
450 0xe08, 0x0000ff00, 0x00000000,
451 0x86c, 0xffffff00, 0x00000000,
452 0xe10, 0xffffffff, 0x06060606,
453 0xe14, 0xffffffff, 0x00020406,
454 0xe18, 0xffffffff, 0x06060606,
455 0xe1c, 0xffffffff, 0x00020406,
456 0x830, 0xffffffff, 0x04040404,
457 0x834, 0xffffffff, 0x00020204,
458 0x838, 0xffffff00, 0x00000000,
459 0x86c, 0x000000ff, 0x00000000,
460 0x83c, 0xffffffff, 0x06060606,
461 0x848, 0xffffffff, 0x00020406,
462 0x84c, 0xffffffff, 0x06060606,
463 0x868, 0xffffffff, 0x00020406,
464 0xe00, 0xffffffff, 0x00000000,
465 0xe04, 0xffffffff, 0x00000000,
466 0xe08, 0x0000ff00, 0x00000000,
467 0x86c, 0xffffff00, 0x00000000,
468 0xe10, 0xffffffff, 0x00000000,
469 0xe14, 0xffffffff, 0x00000000,
470 0xe18, 0xffffffff, 0x00000000,
471 0xe1c, 0xffffffff, 0x00000000,
472 0x830, 0xffffffff, 0x00000000,
473 0x834, 0xffffffff, 0x00000000,
474 0x838, 0xffffff00, 0x00000000,
475 0x86c, 0x000000ff, 0x00000000,
476 0x83c, 0xffffffff, 0x00000000,
477 0x848, 0xffffffff, 0x00000000,
478 0x84c, 0xffffffff, 0x00000000,
479 0x868, 0xffffffff, 0x00000000,
480};
481
482u32 RTL8192CERADIOA_2TARRAY[RADIOA_2TARRAYLENGTH] = {
483 0x000, 0x00030159,
484 0x001, 0x00031284,
485 0x002, 0x00098000,
486 0x003, 0x00018c63,
487 0x004, 0x000210e7,
488 0x009, 0x0002044f,
489 0x00a, 0x0001adb0,
490 0x00b, 0x00054867,
491 0x00c, 0x0008992e,
492 0x00d, 0x0000e52c,
493 0x00e, 0x00039ce7,
494 0x00f, 0x00000451,
495 0x019, 0x00000000,
496 0x01a, 0x00010255,
497 0x01b, 0x00060a00,
498 0x01c, 0x000fc378,
499 0x01d, 0x000a1250,
500 0x01e, 0x0004445f,
501 0x01f, 0x00080001,
502 0x020, 0x0000b614,
503 0x021, 0x0006c000,
504 0x022, 0x00000000,
505 0x023, 0x00001558,
506 0x024, 0x00000060,
507 0x025, 0x00000483,
508 0x026, 0x0004f000,
509 0x027, 0x000ec7d9,
510 0x028, 0x000977c0,
511 0x029, 0x00004783,
512 0x02a, 0x00000001,
513 0x02b, 0x00021334,
514 0x02a, 0x00000000,
515 0x02b, 0x00000054,
516 0x02a, 0x00000001,
517 0x02b, 0x00000808,
518 0x02b, 0x00053333,
519 0x02c, 0x0000000c,
520 0x02a, 0x00000002,
521 0x02b, 0x00000808,
522 0x02b, 0x0005b333,
523 0x02c, 0x0000000d,
524 0x02a, 0x00000003,
525 0x02b, 0x00000808,
526 0x02b, 0x00063333,
527 0x02c, 0x0000000d,
528 0x02a, 0x00000004,
529 0x02b, 0x00000808,
530 0x02b, 0x0006b333,
531 0x02c, 0x0000000d,
532 0x02a, 0x00000005,
533 0x02b, 0x00000808,
534 0x02b, 0x00073333,
535 0x02c, 0x0000000d,
536 0x02a, 0x00000006,
537 0x02b, 0x00000709,
538 0x02b, 0x0005b333,
539 0x02c, 0x0000000d,
540 0x02a, 0x00000007,
541 0x02b, 0x00000709,
542 0x02b, 0x00063333,
543 0x02c, 0x0000000d,
544 0x02a, 0x00000008,
545 0x02b, 0x0000060a,
546 0x02b, 0x0004b333,
547 0x02c, 0x0000000d,
548 0x02a, 0x00000009,
549 0x02b, 0x0000060a,
550 0x02b, 0x00053333,
551 0x02c, 0x0000000d,
552 0x02a, 0x0000000a,
553 0x02b, 0x0000060a,
554 0x02b, 0x0005b333,
555 0x02c, 0x0000000d,
556 0x02a, 0x0000000b,
557 0x02b, 0x0000060a,
558 0x02b, 0x00063333,
559 0x02c, 0x0000000d,
560 0x02a, 0x0000000c,
561 0x02b, 0x0000060a,
562 0x02b, 0x0006b333,
563 0x02c, 0x0000000d,
564 0x02a, 0x0000000d,
565 0x02b, 0x0000060a,
566 0x02b, 0x00073333,
567 0x02c, 0x0000000d,
568 0x02a, 0x0000000e,
569 0x02b, 0x0000050b,
570 0x02b, 0x00066666,
571 0x02c, 0x0000001a,
572 0x02a, 0x000e0000,
573 0x010, 0x0004000f,
574 0x011, 0x000e31fc,
575 0x010, 0x0006000f,
576 0x011, 0x000ff9f8,
577 0x010, 0x0002000f,
578 0x011, 0x000203f9,
579 0x010, 0x0003000f,
580 0x011, 0x000ff500,
581 0x010, 0x00000000,
582 0x011, 0x00000000,
583 0x010, 0x0008000f,
584 0x011, 0x0003f100,
585 0x010, 0x0009000f,
586 0x011, 0x00023100,
587 0x012, 0x00032000,
588 0x012, 0x00071000,
589 0x012, 0x000b0000,
590 0x012, 0x000fc000,
591 0x013, 0x000287af,
592 0x013, 0x000244b7,
593 0x013, 0x000204ab,
594 0x013, 0x0001c49f,
595 0x013, 0x00018493,
596 0x013, 0x00014297,
597 0x013, 0x00010295,
598 0x013, 0x0000c298,
599 0x013, 0x0000819c,
600 0x013, 0x000040a8,
601 0x013, 0x0000001c,
602 0x014, 0x0001944c,
603 0x014, 0x00059444,
604 0x014, 0x0009944c,
605 0x014, 0x000d9444,
606 0x015, 0x0000f424,
607 0x015, 0x0004f424,
608 0x015, 0x0008f424,
609 0x015, 0x000cf424,
610 0x016, 0x000e0330,
611 0x016, 0x000a0330,
612 0x016, 0x00060330,
613 0x016, 0x00020330,
614 0x000, 0x00010159,
615 0x018, 0x0000f401,
616 0x0fe, 0x00000000,
617 0x0fe, 0x00000000,
618 0x01f, 0x00080003,
619 0x0fe, 0x00000000,
620 0x0fe, 0x00000000,
621 0x01e, 0x00044457,
622 0x01f, 0x00080000,
623 0x000, 0x00030159,
624};
625
626u32 RTL8192CE_RADIOB_2TARRAY[RADIOB_2TARRAYLENGTH] = {
627 0x000, 0x00030159,
628 0x001, 0x00031284,
629 0x002, 0x00098000,
630 0x003, 0x00018c63,
631 0x004, 0x000210e7,
632 0x009, 0x0002044f,
633 0x00a, 0x0001adb0,
634 0x00b, 0x00054867,
635 0x00c, 0x0008992e,
636 0x00d, 0x0000e52c,
637 0x00e, 0x00039ce7,
638 0x00f, 0x00000451,
639 0x012, 0x00032000,
640 0x012, 0x00071000,
641 0x012, 0x000b0000,
642 0x012, 0x000fc000,
643 0x013, 0x000287af,
644 0x013, 0x000244b7,
645 0x013, 0x000204ab,
646 0x013, 0x0001c49f,
647 0x013, 0x00018493,
648 0x013, 0x00014297,
649 0x013, 0x00010295,
650 0x013, 0x0000c298,
651 0x013, 0x0000819c,
652 0x013, 0x000040a8,
653 0x013, 0x0000001c,
654 0x014, 0x0001944c,
655 0x014, 0x00059444,
656 0x014, 0x0009944c,
657 0x014, 0x000d9444,
658 0x015, 0x0000f424,
659 0x015, 0x0004f424,
660 0x015, 0x0008f424,
661 0x015, 0x000cf424,
662 0x016, 0x000e0330,
663 0x016, 0x000a0330,
664 0x016, 0x00060330,
665 0x016, 0x00020330,
666};
667
668u32 RTL8192CE_RADIOA_1TARRAY[RADIOA_1TARRAYLENGTH] = {
669 0x000, 0x00030159,
670 0x001, 0x00031284,
671 0x002, 0x00098000,
672 0x003, 0x00018c63,
673 0x004, 0x000210e7,
674 0x009, 0x0002044f,
675 0x00a, 0x0001adb0,
676 0x00b, 0x00054867,
677 0x00c, 0x0008992e,
678 0x00d, 0x0000e52c,
679 0x00e, 0x00039ce7,
680 0x00f, 0x00000451,
681 0x019, 0x00000000,
682 0x01a, 0x00010255,
683 0x01b, 0x00060a00,
684 0x01c, 0x000fc378,
685 0x01d, 0x000a1250,
686 0x01e, 0x0004445f,
687 0x01f, 0x00080001,
688 0x020, 0x0000b614,
689 0x021, 0x0006c000,
690 0x022, 0x00000000,
691 0x023, 0x00001558,
692 0x024, 0x00000060,
693 0x025, 0x00000483,
694 0x026, 0x0004f000,
695 0x027, 0x000ec7d9,
696 0x028, 0x000977c0,
697 0x029, 0x00004783,
698 0x02a, 0x00000001,
699 0x02b, 0x00021334,
700 0x02a, 0x00000000,
701 0x02b, 0x00000054,
702 0x02a, 0x00000001,
703 0x02b, 0x00000808,
704 0x02b, 0x00053333,
705 0x02c, 0x0000000c,
706 0x02a, 0x00000002,
707 0x02b, 0x00000808,
708 0x02b, 0x0005b333,
709 0x02c, 0x0000000d,
710 0x02a, 0x00000003,
711 0x02b, 0x00000808,
712 0x02b, 0x00063333,
713 0x02c, 0x0000000d,
714 0x02a, 0x00000004,
715 0x02b, 0x00000808,
716 0x02b, 0x0006b333,
717 0x02c, 0x0000000d,
718 0x02a, 0x00000005,
719 0x02b, 0x00000808,
720 0x02b, 0x00073333,
721 0x02c, 0x0000000d,
722 0x02a, 0x00000006,
723 0x02b, 0x00000709,
724 0x02b, 0x0005b333,
725 0x02c, 0x0000000d,
726 0x02a, 0x00000007,
727 0x02b, 0x00000709,
728 0x02b, 0x00063333,
729 0x02c, 0x0000000d,
730 0x02a, 0x00000008,
731 0x02b, 0x0000060a,
732 0x02b, 0x0004b333,
733 0x02c, 0x0000000d,
734 0x02a, 0x00000009,
735 0x02b, 0x0000060a,
736 0x02b, 0x00053333,
737 0x02c, 0x0000000d,
738 0x02a, 0x0000000a,
739 0x02b, 0x0000060a,
740 0x02b, 0x0005b333,
741 0x02c, 0x0000000d,
742 0x02a, 0x0000000b,
743 0x02b, 0x0000060a,
744 0x02b, 0x00063333,
745 0x02c, 0x0000000d,
746 0x02a, 0x0000000c,
747 0x02b, 0x0000060a,
748 0x02b, 0x0006b333,
749 0x02c, 0x0000000d,
750 0x02a, 0x0000000d,
751 0x02b, 0x0000060a,
752 0x02b, 0x00073333,
753 0x02c, 0x0000000d,
754 0x02a, 0x0000000e,
755 0x02b, 0x0000050b,
756 0x02b, 0x00066666,
757 0x02c, 0x0000001a,
758 0x02a, 0x000e0000,
759 0x010, 0x0004000f,
760 0x011, 0x000e31fc,
761 0x010, 0x0006000f,
762 0x011, 0x000ff9f8,
763 0x010, 0x0002000f,
764 0x011, 0x000203f9,
765 0x010, 0x0003000f,
766 0x011, 0x000ff500,
767 0x010, 0x00000000,
768 0x011, 0x00000000,
769 0x010, 0x0008000f,
770 0x011, 0x0003f100,
771 0x010, 0x0009000f,
772 0x011, 0x00023100,
773 0x012, 0x00032000,
774 0x012, 0x00071000,
775 0x012, 0x000b0000,
776 0x012, 0x000fc000,
777 0x013, 0x000287af,
778 0x013, 0x000244b7,
779 0x013, 0x000204ab,
780 0x013, 0x0001c49f,
781 0x013, 0x00018493,
782 0x013, 0x00014297,
783 0x013, 0x00010295,
784 0x013, 0x0000c298,
785 0x013, 0x0000819c,
786 0x013, 0x000040a8,
787 0x013, 0x0000001c,
788 0x014, 0x0001944c,
789 0x014, 0x00059444,
790 0x014, 0x0009944c,
791 0x014, 0x000d9444,
792 0x015, 0x0000f424,
793 0x015, 0x0004f424,
794 0x015, 0x0008f424,
795 0x015, 0x000cf424,
796 0x016, 0x000e0330,
797 0x016, 0x000a0330,
798 0x016, 0x00060330,
799 0x016, 0x00020330,
800 0x000, 0x00010159,
801 0x018, 0x0000f401,
802 0x0fe, 0x00000000,
803 0x0fe, 0x00000000,
804 0x01f, 0x00080003,
805 0x0fe, 0x00000000,
806 0x0fe, 0x00000000,
807 0x01e, 0x00044457,
808 0x01f, 0x00080000,
809 0x000, 0x00030159,
810};
811
812u32 RTL8192CE_RADIOB_1TARRAY[RADIOB_1TARRAYLENGTH] = {
813 0x0,
814};
815
816u32 RTL8192CEMAC_2T_ARRAY[MAC_2T_ARRAYLENGTH] = {
817 0x420, 0x00000080,
818 0x423, 0x00000000,
819 0x430, 0x00000000,
820 0x431, 0x00000000,
821 0x432, 0x00000000,
822 0x433, 0x00000001,
823 0x434, 0x00000004,
824 0x435, 0x00000005,
825 0x436, 0x00000006,
826 0x437, 0x00000007,
827 0x438, 0x00000000,
828 0x439, 0x00000000,
829 0x43a, 0x00000000,
830 0x43b, 0x00000001,
831 0x43c, 0x00000004,
832 0x43d, 0x00000005,
833 0x43e, 0x00000006,
834 0x43f, 0x00000007,
835 0x440, 0x0000005d,
836 0x441, 0x00000001,
837 0x442, 0x00000000,
838 0x444, 0x00000015,
839 0x445, 0x000000f0,
840 0x446, 0x0000000f,
841 0x447, 0x00000000,
842 0x458, 0x00000041,
843 0x459, 0x000000a8,
844 0x45a, 0x00000072,
845 0x45b, 0x000000b9,
846 0x460, 0x00000088,
847 0x461, 0x00000088,
848 0x462, 0x00000006,
849 0x463, 0x00000003,
850 0x4c8, 0x00000004,
851 0x4c9, 0x00000008,
852 0x4cc, 0x00000002,
853 0x4cd, 0x00000028,
854 0x4ce, 0x00000001,
855 0x500, 0x00000026,
856 0x501, 0x000000a2,
857 0x502, 0x0000002f,
858 0x503, 0x00000000,
859 0x504, 0x00000028,
860 0x505, 0x000000a3,
861 0x506, 0x0000005e,
862 0x507, 0x00000000,
863 0x508, 0x0000002b,
864 0x509, 0x000000a4,
865 0x50a, 0x0000005e,
866 0x50b, 0x00000000,
867 0x50c, 0x0000004f,
868 0x50d, 0x000000a4,
869 0x50e, 0x00000000,
870 0x50f, 0x00000000,
871 0x512, 0x0000001c,
872 0x514, 0x0000000a,
873 0x515, 0x00000010,
874 0x516, 0x0000000a,
875 0x517, 0x00000010,
876 0x51a, 0x00000016,
877 0x524, 0x0000000f,
878 0x525, 0x0000004f,
879 0x546, 0x00000020,
880 0x547, 0x00000000,
881 0x559, 0x00000002,
882 0x55a, 0x00000002,
883 0x55d, 0x000000ff,
884 0x605, 0x00000030,
885 0x608, 0x0000000e,
886 0x609, 0x0000002a,
887 0x652, 0x00000020,
888 0x63c, 0x0000000a,
889 0x63d, 0x0000000a,
890 0x700, 0x00000021,
891 0x701, 0x00000043,
892 0x702, 0x00000065,
893 0x703, 0x00000087,
894 0x708, 0x00000021,
895 0x709, 0x00000043,
896 0x70a, 0x00000065,
897 0x70b, 0x00000087,
898};
899
900u32 RTL8192CEAGCTAB_2TARRAY[AGCTAB_2TARRAYLENGTH] = {
901 0xc78, 0x7b000001,
902 0xc78, 0x7b010001,
903 0xc78, 0x7b020001,
904 0xc78, 0x7b030001,
905 0xc78, 0x7b040001,
906 0xc78, 0x7b050001,
907 0xc78, 0x7a060001,
908 0xc78, 0x79070001,
909 0xc78, 0x78080001,
910 0xc78, 0x77090001,
911 0xc78, 0x760a0001,
912 0xc78, 0x750b0001,
913 0xc78, 0x740c0001,
914 0xc78, 0x730d0001,
915 0xc78, 0x720e0001,
916 0xc78, 0x710f0001,
917 0xc78, 0x70100001,
918 0xc78, 0x6f110001,
919 0xc78, 0x6e120001,
920 0xc78, 0x6d130001,
921 0xc78, 0x6c140001,
922 0xc78, 0x6b150001,
923 0xc78, 0x6a160001,
924 0xc78, 0x69170001,
925 0xc78, 0x68180001,
926 0xc78, 0x67190001,
927 0xc78, 0x661a0001,
928 0xc78, 0x651b0001,
929 0xc78, 0x641c0001,
930 0xc78, 0x631d0001,
931 0xc78, 0x621e0001,
932 0xc78, 0x611f0001,
933 0xc78, 0x60200001,
934 0xc78, 0x49210001,
935 0xc78, 0x48220001,
936 0xc78, 0x47230001,
937 0xc78, 0x46240001,
938 0xc78, 0x45250001,
939 0xc78, 0x44260001,
940 0xc78, 0x43270001,
941 0xc78, 0x42280001,
942 0xc78, 0x41290001,
943 0xc78, 0x402a0001,
944 0xc78, 0x262b0001,
945 0xc78, 0x252c0001,
946 0xc78, 0x242d0001,
947 0xc78, 0x232e0001,
948 0xc78, 0x222f0001,
949 0xc78, 0x21300001,
950 0xc78, 0x20310001,
951 0xc78, 0x06320001,
952 0xc78, 0x05330001,
953 0xc78, 0x04340001,
954 0xc78, 0x03350001,
955 0xc78, 0x02360001,
956 0xc78, 0x01370001,
957 0xc78, 0x00380001,
958 0xc78, 0x00390001,
959 0xc78, 0x003a0001,
960 0xc78, 0x003b0001,
961 0xc78, 0x003c0001,
962 0xc78, 0x003d0001,
963 0xc78, 0x003e0001,
964 0xc78, 0x003f0001,
965 0xc78, 0x7b400001,
966 0xc78, 0x7b410001,
967 0xc78, 0x7b420001,
968 0xc78, 0x7b430001,
969 0xc78, 0x7b440001,
970 0xc78, 0x7b450001,
971 0xc78, 0x7a460001,
972 0xc78, 0x79470001,
973 0xc78, 0x78480001,
974 0xc78, 0x77490001,
975 0xc78, 0x764a0001,
976 0xc78, 0x754b0001,
977 0xc78, 0x744c0001,
978 0xc78, 0x734d0001,
979 0xc78, 0x724e0001,
980 0xc78, 0x714f0001,
981 0xc78, 0x70500001,
982 0xc78, 0x6f510001,
983 0xc78, 0x6e520001,
984 0xc78, 0x6d530001,
985 0xc78, 0x6c540001,
986 0xc78, 0x6b550001,
987 0xc78, 0x6a560001,
988 0xc78, 0x69570001,
989 0xc78, 0x68580001,
990 0xc78, 0x67590001,
991 0xc78, 0x665a0001,
992 0xc78, 0x655b0001,
993 0xc78, 0x645c0001,
994 0xc78, 0x635d0001,
995 0xc78, 0x625e0001,
996 0xc78, 0x615f0001,
997 0xc78, 0x60600001,
998 0xc78, 0x49610001,
999 0xc78, 0x48620001,
1000 0xc78, 0x47630001,
1001 0xc78, 0x46640001,
1002 0xc78, 0x45650001,
1003 0xc78, 0x44660001,
1004 0xc78, 0x43670001,
1005 0xc78, 0x42680001,
1006 0xc78, 0x41690001,
1007 0xc78, 0x406a0001,
1008 0xc78, 0x266b0001,
1009 0xc78, 0x256c0001,
1010 0xc78, 0x246d0001,
1011 0xc78, 0x236e0001,
1012 0xc78, 0x226f0001,
1013 0xc78, 0x21700001,
1014 0xc78, 0x20710001,
1015 0xc78, 0x06720001,
1016 0xc78, 0x05730001,
1017 0xc78, 0x04740001,
1018 0xc78, 0x03750001,
1019 0xc78, 0x02760001,
1020 0xc78, 0x01770001,
1021 0xc78, 0x00780001,
1022 0xc78, 0x00790001,
1023 0xc78, 0x007a0001,
1024 0xc78, 0x007b0001,
1025 0xc78, 0x007c0001,
1026 0xc78, 0x007d0001,
1027 0xc78, 0x007e0001,
1028 0xc78, 0x007f0001,
1029 0xc78, 0x3800001e,
1030 0xc78, 0x3801001e,
1031 0xc78, 0x3802001e,
1032 0xc78, 0x3803001e,
1033 0xc78, 0x3804001e,
1034 0xc78, 0x3805001e,
1035 0xc78, 0x3806001e,
1036 0xc78, 0x3807001e,
1037 0xc78, 0x3808001e,
1038 0xc78, 0x3c09001e,
1039 0xc78, 0x3e0a001e,
1040 0xc78, 0x400b001e,
1041 0xc78, 0x440c001e,
1042 0xc78, 0x480d001e,
1043 0xc78, 0x4c0e001e,
1044 0xc78, 0x500f001e,
1045 0xc78, 0x5210001e,
1046 0xc78, 0x5611001e,
1047 0xc78, 0x5a12001e,
1048 0xc78, 0x5e13001e,
1049 0xc78, 0x6014001e,
1050 0xc78, 0x6015001e,
1051 0xc78, 0x6016001e,
1052 0xc78, 0x6217001e,
1053 0xc78, 0x6218001e,
1054 0xc78, 0x6219001e,
1055 0xc78, 0x621a001e,
1056 0xc78, 0x621b001e,
1057 0xc78, 0x621c001e,
1058 0xc78, 0x621d001e,
1059 0xc78, 0x621e001e,
1060 0xc78, 0x621f001e,
1061};
1062
1063u32 RTL8192CEAGCTAB_1TARRAY[AGCTAB_1TARRAYLENGTH] = {
1064 0xc78, 0x7b000001,
1065 0xc78, 0x7b010001,
1066 0xc78, 0x7b020001,
1067 0xc78, 0x7b030001,
1068 0xc78, 0x7b040001,
1069 0xc78, 0x7b050001,
1070 0xc78, 0x7a060001,
1071 0xc78, 0x79070001,
1072 0xc78, 0x78080001,
1073 0xc78, 0x77090001,
1074 0xc78, 0x760a0001,
1075 0xc78, 0x750b0001,
1076 0xc78, 0x740c0001,
1077 0xc78, 0x730d0001,
1078 0xc78, 0x720e0001,
1079 0xc78, 0x710f0001,
1080 0xc78, 0x70100001,
1081 0xc78, 0x6f110001,
1082 0xc78, 0x6e120001,
1083 0xc78, 0x6d130001,
1084 0xc78, 0x6c140001,
1085 0xc78, 0x6b150001,
1086 0xc78, 0x6a160001,
1087 0xc78, 0x69170001,
1088 0xc78, 0x68180001,
1089 0xc78, 0x67190001,
1090 0xc78, 0x661a0001,
1091 0xc78, 0x651b0001,
1092 0xc78, 0x641c0001,
1093 0xc78, 0x631d0001,
1094 0xc78, 0x621e0001,
1095 0xc78, 0x611f0001,
1096 0xc78, 0x60200001,
1097 0xc78, 0x49210001,
1098 0xc78, 0x48220001,
1099 0xc78, 0x47230001,
1100 0xc78, 0x46240001,
1101 0xc78, 0x45250001,
1102 0xc78, 0x44260001,
1103 0xc78, 0x43270001,
1104 0xc78, 0x42280001,
1105 0xc78, 0x41290001,
1106 0xc78, 0x402a0001,
1107 0xc78, 0x262b0001,
1108 0xc78, 0x252c0001,
1109 0xc78, 0x242d0001,
1110 0xc78, 0x232e0001,
1111 0xc78, 0x222f0001,
1112 0xc78, 0x21300001,
1113 0xc78, 0x20310001,
1114 0xc78, 0x06320001,
1115 0xc78, 0x05330001,
1116 0xc78, 0x04340001,
1117 0xc78, 0x03350001,
1118 0xc78, 0x02360001,
1119 0xc78, 0x01370001,
1120 0xc78, 0x00380001,
1121 0xc78, 0x00390001,
1122 0xc78, 0x003a0001,
1123 0xc78, 0x003b0001,
1124 0xc78, 0x003c0001,
1125 0xc78, 0x003d0001,
1126 0xc78, 0x003e0001,
1127 0xc78, 0x003f0001,
1128 0xc78, 0x7b400001,
1129 0xc78, 0x7b410001,
1130 0xc78, 0x7b420001,
1131 0xc78, 0x7b430001,
1132 0xc78, 0x7b440001,
1133 0xc78, 0x7b450001,
1134 0xc78, 0x7a460001,
1135 0xc78, 0x79470001,
1136 0xc78, 0x78480001,
1137 0xc78, 0x77490001,
1138 0xc78, 0x764a0001,
1139 0xc78, 0x754b0001,
1140 0xc78, 0x744c0001,
1141 0xc78, 0x734d0001,
1142 0xc78, 0x724e0001,
1143 0xc78, 0x714f0001,
1144 0xc78, 0x70500001,
1145 0xc78, 0x6f510001,
1146 0xc78, 0x6e520001,
1147 0xc78, 0x6d530001,
1148 0xc78, 0x6c540001,
1149 0xc78, 0x6b550001,
1150 0xc78, 0x6a560001,
1151 0xc78, 0x69570001,
1152 0xc78, 0x68580001,
1153 0xc78, 0x67590001,
1154 0xc78, 0x665a0001,
1155 0xc78, 0x655b0001,
1156 0xc78, 0x645c0001,
1157 0xc78, 0x635d0001,
1158 0xc78, 0x625e0001,
1159 0xc78, 0x615f0001,
1160 0xc78, 0x60600001,
1161 0xc78, 0x49610001,
1162 0xc78, 0x48620001,
1163 0xc78, 0x47630001,
1164 0xc78, 0x46640001,
1165 0xc78, 0x45650001,
1166 0xc78, 0x44660001,
1167 0xc78, 0x43670001,
1168 0xc78, 0x42680001,
1169 0xc78, 0x41690001,
1170 0xc78, 0x406a0001,
1171 0xc78, 0x266b0001,
1172 0xc78, 0x256c0001,
1173 0xc78, 0x246d0001,
1174 0xc78, 0x236e0001,
1175 0xc78, 0x226f0001,
1176 0xc78, 0x21700001,
1177 0xc78, 0x20710001,
1178 0xc78, 0x06720001,
1179 0xc78, 0x05730001,
1180 0xc78, 0x04740001,
1181 0xc78, 0x03750001,
1182 0xc78, 0x02760001,
1183 0xc78, 0x01770001,
1184 0xc78, 0x00780001,
1185 0xc78, 0x00790001,
1186 0xc78, 0x007a0001,
1187 0xc78, 0x007b0001,
1188 0xc78, 0x007c0001,
1189 0xc78, 0x007d0001,
1190 0xc78, 0x007e0001,
1191 0xc78, 0x007f0001,
1192 0xc78, 0x3800001e,
1193 0xc78, 0x3801001e,
1194 0xc78, 0x3802001e,
1195 0xc78, 0x3803001e,
1196 0xc78, 0x3804001e,
1197 0xc78, 0x3805001e,
1198 0xc78, 0x3806001e,
1199 0xc78, 0x3807001e,
1200 0xc78, 0x3808001e,
1201 0xc78, 0x3c09001e,
1202 0xc78, 0x3e0a001e,
1203 0xc78, 0x400b001e,
1204 0xc78, 0x440c001e,
1205 0xc78, 0x480d001e,
1206 0xc78, 0x4c0e001e,
1207 0xc78, 0x500f001e,
1208 0xc78, 0x5210001e,
1209 0xc78, 0x5611001e,
1210 0xc78, 0x5a12001e,
1211 0xc78, 0x5e13001e,
1212 0xc78, 0x6014001e,
1213 0xc78, 0x6015001e,
1214 0xc78, 0x6016001e,
1215 0xc78, 0x6217001e,
1216 0xc78, 0x6218001e,
1217 0xc78, 0x6219001e,
1218 0xc78, 0x621a001e,
1219 0xc78, 0x621b001e,
1220 0xc78, 0x621c001e,
1221 0xc78, 0x621d001e,
1222 0xc78, 0x621e001e,
1223 0xc78, 0x621f001e,
1224};
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/table.h b/drivers/net/wireless/rtlwifi/rtl8192ce/table.h
new file mode 100644
index 000000000000..3a6e8b6aeee0
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/table.h
@@ -0,0 +1,58 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Created on 2010/ 5/18, 1:41
27 *
28 * Larry Finger <Larry.Finger@lwfinger.net>
29 *
30 *****************************************************************************/
31
32#ifndef __RTL92CE_TABLE__H_
33#define __RTL92CE_TABLE__H_
34
35#include <linux/types.h>
36
37#define PHY_REG_2TARRAY_LENGTH 374
38extern u32 RTL8192CEPHY_REG_2TARRAY[PHY_REG_2TARRAY_LENGTH];
39#define PHY_REG_1TARRAY_LENGTH 374
40extern u32 RTL8192CEPHY_REG_1TARRAY[PHY_REG_1TARRAY_LENGTH];
41#define PHY_REG_ARRAY_PGLENGTH 192
42extern u32 RTL8192CEPHY_REG_ARRAY_PG[PHY_REG_ARRAY_PGLENGTH];
43#define RADIOA_2TARRAYLENGTH 282
44extern u32 RTL8192CERADIOA_2TARRAY[RADIOA_2TARRAYLENGTH];
45#define RADIOB_2TARRAYLENGTH 78
46extern u32 RTL8192CE_RADIOB_2TARRAY[RADIOB_2TARRAYLENGTH];
47#define RADIOA_1TARRAYLENGTH 282
48extern u32 RTL8192CE_RADIOA_1TARRAY[RADIOA_1TARRAYLENGTH];
49#define RADIOB_1TARRAYLENGTH 1
50extern u32 RTL8192CE_RADIOB_1TARRAY[RADIOB_1TARRAYLENGTH];
51#define MAC_2T_ARRAYLENGTH 162
52extern u32 RTL8192CEMAC_2T_ARRAY[MAC_2T_ARRAYLENGTH];
53#define AGCTAB_2TARRAYLENGTH 320
54extern u32 RTL8192CEAGCTAB_2TARRAY[AGCTAB_2TARRAYLENGTH];
55#define AGCTAB_1TARRAYLENGTH 320
56extern u32 RTL8192CEAGCTAB_1TARRAY[AGCTAB_1TARRAYLENGTH];
57
58#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
new file mode 100644
index 000000000000..54b2bd53d36a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
@@ -0,0 +1,1012 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../base.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "trx.h"
37#include "led.h"
38
39static u8 _rtl92ce_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
40{
41 __le16 fc = rtl_get_fc(skb);
42
43 if (unlikely(ieee80211_is_beacon(fc)))
44 return QSLT_BEACON;
45 if (ieee80211_is_mgmt(fc))
46 return QSLT_MGNT;
47
48 return skb->priority;
49}
50
51static int _rtl92ce_rate_mapping(bool isht, u8 desc_rate, bool first_ampdu)
52{
53 int rate_idx;
54
55 if (first_ampdu) {
56 if (false == isht) {
57 switch (desc_rate) {
58 case DESC92C_RATE1M:
59 rate_idx = 0;
60 break;
61 case DESC92C_RATE2M:
62 rate_idx = 1;
63 break;
64 case DESC92C_RATE5_5M:
65 rate_idx = 2;
66 break;
67 case DESC92C_RATE11M:
68 rate_idx = 3;
69 break;
70 case DESC92C_RATE6M:
71 rate_idx = 4;
72 break;
73 case DESC92C_RATE9M:
74 rate_idx = 5;
75 break;
76 case DESC92C_RATE12M:
77 rate_idx = 6;
78 break;
79 case DESC92C_RATE18M:
80 rate_idx = 7;
81 break;
82 case DESC92C_RATE24M:
83 rate_idx = 8;
84 break;
85 case DESC92C_RATE36M:
86 rate_idx = 9;
87 break;
88 case DESC92C_RATE48M:
89 rate_idx = 10;
90 break;
91 case DESC92C_RATE54M:
92 rate_idx = 11;
93 break;
94 default:
95 rate_idx = 0;
96 break;
97 }
98 } else {
99 rate_idx = 11;
100 }
101
102 return rate_idx;
103 }
104
105 switch (desc_rate) {
106 case DESC92C_RATE1M:
107 rate_idx = 0;
108 break;
109 case DESC92C_RATE2M:
110 rate_idx = 1;
111 break;
112 case DESC92C_RATE5_5M:
113 rate_idx = 2;
114 break;
115 case DESC92C_RATE11M:
116 rate_idx = 3;
117 break;
118 case DESC92C_RATE6M:
119 rate_idx = 4;
120 break;
121 case DESC92C_RATE9M:
122 rate_idx = 5;
123 break;
124 case DESC92C_RATE12M:
125 rate_idx = 6;
126 break;
127 case DESC92C_RATE18M:
128 rate_idx = 7;
129 break;
130 case DESC92C_RATE24M:
131 rate_idx = 8;
132 break;
133 case DESC92C_RATE36M:
134 rate_idx = 9;
135 break;
136 case DESC92C_RATE48M:
137 rate_idx = 10;
138 break;
139 case DESC92C_RATE54M:
140 rate_idx = 11;
141 break;
142 default:
143 rate_idx = 11;
144 break;
145 }
146 return rate_idx;
147}
148
149static u8 _rtl92c_query_rxpwrpercentage(char antpower)
150{
151 if ((antpower <= -100) || (antpower >= 20))
152 return 0;
153 else if (antpower >= 0)
154 return 100;
155 else
156 return 100 + antpower;
157}
158
159static u8 _rtl92c_evm_db_to_percentage(char value)
160{
161 char ret_val;
162 ret_val = value;
163
164 if (ret_val >= 0)
165 ret_val = 0;
166
167 if (ret_val <= -33)
168 ret_val = -33;
169
170 ret_val = 0 - ret_val;
171 ret_val *= 3;
172
173 if (ret_val == 99)
174 ret_val = 100;
175
176 return ret_val;
177}
178
179static long _rtl92ce_translate_todbm(struct ieee80211_hw *hw,
180 u8 signal_strength_index)
181{
182 long signal_power;
183
184 signal_power = (long)((signal_strength_index + 1) >> 1);
185 signal_power -= 95;
186 return signal_power;
187}
188
189static long _rtl92ce_signal_scale_mapping(struct ieee80211_hw *hw,
190 long currsig)
191{
192 long retsig;
193
194 if (currsig >= 61 && currsig <= 100)
195 retsig = 90 + ((currsig - 60) / 4);
196 else if (currsig >= 41 && currsig <= 60)
197 retsig = 78 + ((currsig - 40) / 2);
198 else if (currsig >= 31 && currsig <= 40)
199 retsig = 66 + (currsig - 30);
200 else if (currsig >= 21 && currsig <= 30)
201 retsig = 54 + (currsig - 20);
202 else if (currsig >= 5 && currsig <= 20)
203 retsig = 42 + (((currsig - 5) * 2) / 3);
204 else if (currsig == 4)
205 retsig = 36;
206 else if (currsig == 3)
207 retsig = 27;
208 else if (currsig == 2)
209 retsig = 18;
210 else if (currsig == 1)
211 retsig = 9;
212 else
213 retsig = currsig;
214
215 return retsig;
216}
217
218static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
219 struct rtl_stats *pstats,
220 struct rx_desc_92c *pdesc,
221 struct rx_fwinfo_92c *p_drvinfo,
222 bool packet_match_bssid,
223 bool packet_toself,
224 bool packet_beacon)
225{
226 struct rtl_priv *rtlpriv = rtl_priv(hw);
227 struct phy_sts_cck_8192s_t *cck_buf;
228 s8 rx_pwr_all, rx_pwr[4];
229 u8 evm, pwdb_all, rf_rx_num = 0;
230 u8 i, max_spatial_stream;
231 u32 rssi, total_rssi = 0;
232 bool in_powersavemode = false;
233 bool is_cck_rate;
234
235 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc);
236 pstats->packet_matchbssid = packet_match_bssid;
237 pstats->packet_toself = packet_toself;
238 pstats->is_cck = is_cck_rate;
239 pstats->packet_beacon = packet_beacon;
240 pstats->is_cck = is_cck_rate;
241 pstats->rx_mimo_signalquality[0] = -1;
242 pstats->rx_mimo_signalquality[1] = -1;
243
244 if (is_cck_rate) {
245 u8 report, cck_highpwr;
246 cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
247
248 if (!in_powersavemode)
249 cck_highpwr = (u8) rtl_get_bbreg(hw,
250 RFPGA0_XA_HSSIPARAMETER2,
251 BIT(9));
252 else
253 cck_highpwr = false;
254
255 if (!cck_highpwr) {
256 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
257 report = cck_buf->cck_agc_rpt & 0xc0;
258 report = report >> 6;
259 switch (report) {
260 case 0x3:
261 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
262 break;
263 case 0x2:
264 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
265 break;
266 case 0x1:
267 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
268 break;
269 case 0x0:
270 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
271 break;
272 }
273 } else {
274 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
275 report = p_drvinfo->cfosho[0] & 0x60;
276 report = report >> 5;
277 switch (report) {
278 case 0x3:
279 rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
280 break;
281 case 0x2:
282 rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
283 break;
284 case 0x1:
285 rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
286 break;
287 case 0x0:
288 rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
289 break;
290 }
291 }
292
293 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
294 pstats->rx_pwdb_all = pwdb_all;
295 pstats->recvsignalpower = rx_pwr_all;
296
297 if (packet_match_bssid) {
298 u8 sq;
299 if (pstats->rx_pwdb_all > 40)
300 sq = 100;
301 else {
302 sq = cck_buf->sq_rpt;
303 if (sq > 64)
304 sq = 0;
305 else if (sq < 20)
306 sq = 100;
307 else
308 sq = ((64 - sq) * 100) / 44;
309 }
310
311 pstats->signalquality = sq;
312 pstats->rx_mimo_signalquality[0] = sq;
313 pstats->rx_mimo_signalquality[1] = -1;
314 }
315 } else {
316 rtlpriv->dm.rfpath_rxenable[0] =
317 rtlpriv->dm.rfpath_rxenable[1] = true;
318 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
319 if (rtlpriv->dm.rfpath_rxenable[i])
320 rf_rx_num++;
321
322 rx_pwr[i] =
323 ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
324 rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]);
325 total_rssi += rssi;
326 rtlpriv->stats.rx_snr_db[i] =
327 (long)(p_drvinfo->rxsnr[i] / 2);
328
329 if (packet_match_bssid)
330 pstats->rx_mimo_signalstrength[i] = (u8) rssi;
331 }
332
333 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
334 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
335 pstats->rx_pwdb_all = pwdb_all;
336 pstats->rxpower = rx_pwr_all;
337 pstats->recvsignalpower = rx_pwr_all;
338
339 if (pdesc->rxht && pdesc->rxmcs >= DESC92C_RATEMCS8 &&
340 pdesc->rxmcs <= DESC92C_RATEMCS15)
341 max_spatial_stream = 2;
342 else
343 max_spatial_stream = 1;
344
345 for (i = 0; i < max_spatial_stream; i++) {
346 evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]);
347
348 if (packet_match_bssid) {
349 if (i == 0)
350 pstats->signalquality =
351 (u8) (evm & 0xff);
352 pstats->rx_mimo_signalquality[i] =
353 (u8) (evm & 0xff);
354 }
355 }
356 }
357
358 if (is_cck_rate)
359 pstats->signalstrength =
360 (u8) (_rtl92ce_signal_scale_mapping(hw, pwdb_all));
361 else if (rf_rx_num != 0)
362 pstats->signalstrength =
363 (u8) (_rtl92ce_signal_scale_mapping
364 (hw, total_rssi /= rf_rx_num));
365}
366
367static void _rtl92ce_process_ui_rssi(struct ieee80211_hw *hw,
368 struct rtl_stats *pstats)
369{
370 struct rtl_priv *rtlpriv = rtl_priv(hw);
371 struct rtl_phy *rtlphy = &(rtlpriv->phy);
372 u8 rfpath;
373 u32 last_rssi, tmpval;
374
375 if (pstats->packet_toself || pstats->packet_beacon) {
376 rtlpriv->stats.rssi_calculate_cnt++;
377
378 if (rtlpriv->stats.ui_rssi.total_num++ >=
379 PHY_RSSI_SLID_WIN_MAX) {
380
381 rtlpriv->stats.ui_rssi.total_num =
382 PHY_RSSI_SLID_WIN_MAX;
383 last_rssi =
384 rtlpriv->stats.ui_rssi.elements[rtlpriv->
385 stats.ui_rssi.index];
386 rtlpriv->stats.ui_rssi.total_val -= last_rssi;
387 }
388
389 rtlpriv->stats.ui_rssi.total_val += pstats->signalstrength;
390 rtlpriv->stats.ui_rssi.elements[rtlpriv->stats.ui_rssi.
391 index++] =
392 pstats->signalstrength;
393
394 if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
395 rtlpriv->stats.ui_rssi.index = 0;
396
397 tmpval = rtlpriv->stats.ui_rssi.total_val /
398 rtlpriv->stats.ui_rssi.total_num;
399 rtlpriv->stats.signal_strength =
400 _rtl92ce_translate_todbm(hw, (u8) tmpval);
401 pstats->rssi = rtlpriv->stats.signal_strength;
402 }
403
404 if (!pstats->is_cck && pstats->packet_toself) {
405 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
406 rfpath++) {
407 if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
408 rtlpriv->stats.rx_rssi_percentage[rfpath] =
409 pstats->rx_mimo_signalstrength[rfpath];
410
411 }
412
413 if (pstats->rx_mimo_signalstrength[rfpath] >
414 rtlpriv->stats.rx_rssi_percentage[rfpath]) {
415 rtlpriv->stats.rx_rssi_percentage[rfpath] =
416 ((rtlpriv->stats.
417 rx_rssi_percentage[rfpath] *
418 (RX_SMOOTH_FACTOR - 1)) +
419 (pstats->rx_mimo_signalstrength[rfpath])) /
420 (RX_SMOOTH_FACTOR);
421
422 rtlpriv->stats.rx_rssi_percentage[rfpath] =
423 rtlpriv->stats.rx_rssi_percentage[rfpath] +
424 1;
425 } else {
426 rtlpriv->stats.rx_rssi_percentage[rfpath] =
427 ((rtlpriv->stats.
428 rx_rssi_percentage[rfpath] *
429 (RX_SMOOTH_FACTOR - 1)) +
430 (pstats->rx_mimo_signalstrength[rfpath])) /
431 (RX_SMOOTH_FACTOR);
432 }
433
434 }
435 }
436}
437
438static void _rtl92ce_update_rxsignalstatistics(struct ieee80211_hw *hw,
439 struct rtl_stats *pstats)
440{
441 struct rtl_priv *rtlpriv = rtl_priv(hw);
442 int weighting = 0;
443
444 if (rtlpriv->stats.recv_signal_power == 0)
445 rtlpriv->stats.recv_signal_power = pstats->recvsignalpower;
446
447 if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power)
448 weighting = 5;
449
450 else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power)
451 weighting = (-5);
452
453 rtlpriv->stats.recv_signal_power =
454 (rtlpriv->stats.recv_signal_power * 5 +
455 pstats->recvsignalpower + weighting) / 6;
456}
457
458static void _rtl92ce_process_pwdb(struct ieee80211_hw *hw,
459 struct rtl_stats *pstats)
460{
461 struct rtl_priv *rtlpriv = rtl_priv(hw);
462 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
463 long undecorated_smoothed_pwdb;
464
465 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
466 return;
467 } else {
468 undecorated_smoothed_pwdb =
469 rtlpriv->dm.undecorated_smoothed_pwdb;
470 }
471
472 if (pstats->packet_toself || pstats->packet_beacon) {
473 if (undecorated_smoothed_pwdb < 0)
474 undecorated_smoothed_pwdb = pstats->rx_pwdb_all;
475
476 if (pstats->rx_pwdb_all > (u32) undecorated_smoothed_pwdb) {
477 undecorated_smoothed_pwdb =
478 (((undecorated_smoothed_pwdb) *
479 (RX_SMOOTH_FACTOR - 1)) +
480 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
481
482 undecorated_smoothed_pwdb = undecorated_smoothed_pwdb
483 + 1;
484 } else {
485 undecorated_smoothed_pwdb =
486 (((undecorated_smoothed_pwdb) *
487 (RX_SMOOTH_FACTOR - 1)) +
488 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
489 }
490
491 rtlpriv->dm.undecorated_smoothed_pwdb =
492 undecorated_smoothed_pwdb;
493 _rtl92ce_update_rxsignalstatistics(hw, pstats);
494 }
495}
496
497static void _rtl92ce_process_ui_link_quality(struct ieee80211_hw *hw,
498 struct rtl_stats *pstats)
499{
500 struct rtl_priv *rtlpriv = rtl_priv(hw);
501 u32 last_evm, n_spatialstream, tmpval;
502
503 if (pstats->signalquality != 0) {
504 if (pstats->packet_toself || pstats->packet_beacon) {
505
506 if (rtlpriv->stats.ui_link_quality.total_num++ >=
507 PHY_LINKQUALITY_SLID_WIN_MAX) {
508 rtlpriv->stats.ui_link_quality.total_num =
509 PHY_LINKQUALITY_SLID_WIN_MAX;
510 last_evm =
511 rtlpriv->stats.
512 ui_link_quality.elements[rtlpriv->
513 stats.ui_link_quality.
514 index];
515 rtlpriv->stats.ui_link_quality.total_val -=
516 last_evm;
517 }
518
519 rtlpriv->stats.ui_link_quality.total_val +=
520 pstats->signalquality;
521 rtlpriv->stats.ui_link_quality.elements[rtlpriv->stats.
522 ui_link_quality.
523 index++] =
524 pstats->signalquality;
525
526 if (rtlpriv->stats.ui_link_quality.index >=
527 PHY_LINKQUALITY_SLID_WIN_MAX)
528 rtlpriv->stats.ui_link_quality.index = 0;
529
530 tmpval = rtlpriv->stats.ui_link_quality.total_val /
531 rtlpriv->stats.ui_link_quality.total_num;
532 rtlpriv->stats.signal_quality = tmpval;
533
534 rtlpriv->stats.last_sigstrength_inpercent = tmpval;
535
536 for (n_spatialstream = 0; n_spatialstream < 2;
537 n_spatialstream++) {
538 if (pstats->
539 rx_mimo_signalquality[n_spatialstream] !=
540 -1) {
541 if (rtlpriv->stats.
542 rx_evm_percentage[n_spatialstream]
543 == 0) {
544 rtlpriv->stats.
545 rx_evm_percentage
546 [n_spatialstream] =
547 pstats->rx_mimo_signalquality
548 [n_spatialstream];
549 }
550
551 rtlpriv->stats.
552 rx_evm_percentage[n_spatialstream] =
553 ((rtlpriv->
554 stats.rx_evm_percentage
555 [n_spatialstream] *
556 (RX_SMOOTH_FACTOR - 1)) +
557 (pstats->
558 rx_mimo_signalquality
559 [n_spatialstream] * 1)) /
560 (RX_SMOOTH_FACTOR);
561 }
562 }
563 }
564 } else {
565 ;
566 }
567}
568
569static void _rtl92ce_process_phyinfo(struct ieee80211_hw *hw,
570 u8 *buffer,
571 struct rtl_stats *pcurrent_stats)
572{
573
574 if (!pcurrent_stats->packet_matchbssid &&
575 !pcurrent_stats->packet_beacon)
576 return;
577
578 _rtl92ce_process_ui_rssi(hw, pcurrent_stats);
579 _rtl92ce_process_pwdb(hw, pcurrent_stats);
580 _rtl92ce_process_ui_link_quality(hw, pcurrent_stats);
581}
582
583static void _rtl92ce_translate_rx_signal_stuff(struct ieee80211_hw *hw,
584 struct sk_buff *skb,
585 struct rtl_stats *pstats,
586 struct rx_desc_92c *pdesc,
587 struct rx_fwinfo_92c *p_drvinfo)
588{
589 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
590 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
591
592 struct ieee80211_hdr *hdr;
593 u8 *tmp_buf;
594 u8 *praddr;
595 u8 *psaddr;
596 __le16 fc;
597 u16 type, c_fc;
598 bool packet_matchbssid, packet_toself, packet_beacon;
599
600 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
601
602 hdr = (struct ieee80211_hdr *)tmp_buf;
603 fc = hdr->frame_control;
604 c_fc = le16_to_cpu(fc);
605 type = WLAN_FC_GET_TYPE(fc);
606 praddr = hdr->addr1;
607 psaddr = hdr->addr2;
608
609 packet_matchbssid =
610 ((IEEE80211_FTYPE_CTL != type) &&
611 (!compare_ether_addr(mac->bssid,
612 (c_fc & IEEE80211_FCTL_TODS) ?
613 hdr->addr1 : (c_fc & IEEE80211_FCTL_FROMDS) ?
614 hdr->addr2 : hdr->addr3)) &&
615 (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv));
616
617 packet_toself = packet_matchbssid &&
618 (!compare_ether_addr(praddr, rtlefuse->dev_addr));
619
620 if (ieee80211_is_beacon(fc))
621 packet_beacon = true;
622
623 _rtl92ce_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
624 packet_matchbssid, packet_toself,
625 packet_beacon);
626
627 _rtl92ce_process_phyinfo(hw, tmp_buf, pstats);
628}
629
630bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
631 struct rtl_stats *stats,
632 struct ieee80211_rx_status *rx_status,
633 u8 *p_desc, struct sk_buff *skb)
634{
635 struct rx_fwinfo_92c *p_drvinfo;
636 struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
637
638 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
639 stats->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
640 stats->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
641 RX_DRV_INFO_SIZE_UNIT;
642 stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
643 stats->icv = (u16) GET_RX_DESC_ICV(pdesc);
644 stats->crc = (u16) GET_RX_DESC_CRC32(pdesc);
645 stats->hwerror = (stats->crc | stats->icv);
646 stats->decrypted = !GET_RX_DESC_SWDEC(pdesc);
647 stats->rate = (u8) GET_RX_DESC_RXMCS(pdesc);
648 stats->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
649 stats->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
650 stats->isampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1)
651 && (GET_RX_DESC_FAGGR(pdesc) == 1));
652 stats->timestamp_low = GET_RX_DESC_TSFL(pdesc);
653 stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
654
655 rx_status->freq = hw->conf.channel->center_freq;
656 rx_status->band = hw->conf.channel->band;
657
658 if (GET_RX_DESC_CRC32(pdesc))
659 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
660
661 if (!GET_RX_DESC_SWDEC(pdesc))
662 rx_status->flag |= RX_FLAG_DECRYPTED;
663
664 if (GET_RX_DESC_BW(pdesc))
665 rx_status->flag |= RX_FLAG_40MHZ;
666
667 if (GET_RX_DESC_RXHT(pdesc))
668 rx_status->flag |= RX_FLAG_HT;
669
670 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
671
672 if (stats->decrypted)
673 rx_status->flag |= RX_FLAG_DECRYPTED;
674
675 rx_status->rate_idx = _rtl92ce_rate_mapping((bool)
676 GET_RX_DESC_RXHT(pdesc),
677 (u8)
678 GET_RX_DESC_RXMCS(pdesc),
679 (bool)
680 GET_RX_DESC_PAGGR(pdesc));
681
682 rx_status->mactime = GET_RX_DESC_TSFL(pdesc);
683 if (phystatus == true) {
684 p_drvinfo = (struct rx_fwinfo_92c *)(skb->data +
685 stats->rx_bufshift);
686
687 _rtl92ce_translate_rx_signal_stuff(hw,
688 skb, stats, pdesc,
689 p_drvinfo);
690 }
691
692 /*rx_status->qual = stats->signal; */
693 rx_status->signal = stats->rssi + 10;
694 /*rx_status->noise = -stats->noise; */
695
696 return true;
697}
698
699void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
700 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
701 struct ieee80211_tx_info *info, struct sk_buff *skb,
702 u8 hw_queue, struct rtl_tcb_desc *tcb_desc)
703{
704 struct rtl_priv *rtlpriv = rtl_priv(hw);
705 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
706 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
707 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
708 bool defaultadapter = true;
709 struct ieee80211_sta *sta;
710 u8 *pdesc = (u8 *) pdesc_tx;
711 u16 seq_number;
712 __le16 fc = hdr->frame_control;
713 u8 fw_qsel = _rtl92ce_map_hwqueue_to_fwqueue(skb, hw_queue);
714 bool firstseg = ((hdr->seq_ctrl &
715 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
716
717 bool lastseg = ((hdr->frame_control &
718 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
719
720 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
721 skb->data, skb->len,
722 PCI_DMA_TODEVICE);
723 u8 bw_40 = 0;
724
725 rcu_read_lock();
726 sta = get_sta(hw, mac->vif, mac->bssid);
727 if (mac->opmode == NL80211_IFTYPE_STATION) {
728 bw_40 = mac->bw_40;
729 } else if (mac->opmode == NL80211_IFTYPE_AP ||
730 mac->opmode == NL80211_IFTYPE_ADHOC) {
731 if (sta)
732 bw_40 = sta->ht_cap.cap &
733 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
734 }
735
736 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
737
738 rtl_get_tcb_desc(hw, info, sta, skb, tcb_desc);
739
740 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_92c));
741
742 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
743 firstseg = true;
744 lastseg = true;
745 }
746 if (firstseg) {
747 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
748
749 SET_TX_DESC_TX_RATE(pdesc, tcb_desc->hw_rate);
750
751 if (tcb_desc->use_shortgi || tcb_desc->use_shortpreamble)
752 SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
753
754 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
755 SET_TX_DESC_AGG_BREAK(pdesc, 1);
756 SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
757 }
758 SET_TX_DESC_SEQ(pdesc, seq_number);
759
760 SET_TX_DESC_RTS_ENABLE(pdesc, ((tcb_desc->rts_enable &&
761 !tcb_desc->
762 cts_enable) ? 1 : 0));
763 SET_TX_DESC_HW_RTS_ENABLE(pdesc,
764 ((tcb_desc->rts_enable
765 || tcb_desc->cts_enable) ? 1 : 0));
766 SET_TX_DESC_CTS2SELF(pdesc, ((tcb_desc->cts_enable) ? 1 : 0));
767 SET_TX_DESC_RTS_STBC(pdesc, ((tcb_desc->rts_stbc) ? 1 : 0));
768
769 SET_TX_DESC_RTS_RATE(pdesc, tcb_desc->rts_rate);
770 SET_TX_DESC_RTS_BW(pdesc, 0);
771 SET_TX_DESC_RTS_SC(pdesc, tcb_desc->rts_sc);
772 SET_TX_DESC_RTS_SHORT(pdesc,
773 ((tcb_desc->rts_rate <= DESC92C_RATE54M) ?
774 (tcb_desc->rts_use_shortpreamble ? 1 : 0)
775 : (tcb_desc->rts_use_shortgi ? 1 : 0)));
776
777 if (bw_40) {
778 if (tcb_desc->packet_bw) {
779 SET_TX_DESC_DATA_BW(pdesc, 1);
780 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
781 } else {
782 SET_TX_DESC_DATA_BW(pdesc, 0);
783 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
784 mac->cur_40_prime_sc);
785 }
786 } else {
787 SET_TX_DESC_DATA_BW(pdesc, 0);
788 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
789 }
790
791 SET_TX_DESC_LINIP(pdesc, 0);
792 SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb->len);
793
794 if (sta) {
795 u8 ampdu_density = sta->ht_cap.ampdu_density;
796 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
797 }
798
799 if (info->control.hw_key) {
800 struct ieee80211_key_conf *keyconf =
801 info->control.hw_key;
802
803 switch (keyconf->cipher) {
804 case WLAN_CIPHER_SUITE_WEP40:
805 case WLAN_CIPHER_SUITE_WEP104:
806 case WLAN_CIPHER_SUITE_TKIP:
807 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
808 break;
809 case WLAN_CIPHER_SUITE_CCMP:
810 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
811 break;
812 default:
813 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
814 break;
815
816 }
817 }
818
819 SET_TX_DESC_PKT_ID(pdesc, 0);
820 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
821
822 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
823 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
824 SET_TX_DESC_DISABLE_FB(pdesc, 0);
825 SET_TX_DESC_USE_RATE(pdesc, tcb_desc->use_driver_rate ? 1 : 0);
826
827 if (ieee80211_is_data_qos(fc)) {
828 if (mac->rdg_en) {
829 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
830 ("Enable RDG function.\n"));
831 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
832 SET_TX_DESC_HTC(pdesc, 1);
833 }
834 }
835 }
836 rcu_read_unlock();
837
838 SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
839 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
840
841 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) skb->len);
842
843 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
844
845 if (rtlpriv->dm.useramask) {
846 SET_TX_DESC_RATE_ID(pdesc, tcb_desc->ratr_index);
847 SET_TX_DESC_MACID(pdesc, tcb_desc->mac_id);
848 } else {
849 SET_TX_DESC_RATE_ID(pdesc, 0xC + tcb_desc->ratr_index);
850 SET_TX_DESC_MACID(pdesc, tcb_desc->ratr_index);
851 }
852
853 if ((!ieee80211_is_data_qos(fc)) && ppsc->fwctrl_lps) {
854 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
855 SET_TX_DESC_PKT_ID(pdesc, 8);
856
857 if (!defaultadapter)
858 SET_TX_DESC_QOS(pdesc, 1);
859 }
860
861 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
862
863 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
864 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
865 SET_TX_DESC_BMC(pdesc, 1);
866 }
867
868 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, ("\n"));
869}
870
871void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw,
872 u8 *pdesc, bool firstseg,
873 bool lastseg, struct sk_buff *skb)
874{
875 struct rtl_priv *rtlpriv = rtl_priv(hw);
876 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
877 u8 fw_queue = QSLT_BEACON;
878
879 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
880 skb->data, skb->len,
881 PCI_DMA_TODEVICE);
882
883 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
884 __le16 fc = hdr->frame_control;
885
886 CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
887
888 if (firstseg)
889 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
890
891 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
892
893 SET_TX_DESC_SEQ(pdesc, 0);
894
895 SET_TX_DESC_LINIP(pdesc, 0);
896
897 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
898
899 SET_TX_DESC_FIRST_SEG(pdesc, 1);
900 SET_TX_DESC_LAST_SEG(pdesc, 1);
901
902 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) (skb->len));
903
904 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
905
906 SET_TX_DESC_RATE_ID(pdesc, 7);
907 SET_TX_DESC_MACID(pdesc, 0);
908
909 SET_TX_DESC_OWN(pdesc, 1);
910
911 SET_TX_DESC_PKT_SIZE((u8 *) pdesc, (u16) (skb->len));
912
913 SET_TX_DESC_FIRST_SEG(pdesc, 1);
914 SET_TX_DESC_LAST_SEG(pdesc, 1);
915
916 SET_TX_DESC_OFFSET(pdesc, 0x20);
917
918 SET_TX_DESC_USE_RATE(pdesc, 1);
919
920 if (!ieee80211_is_data_qos(fc)) {
921 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
922 SET_TX_DESC_PKT_ID(pdesc, 8);
923 }
924
925 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
926 "H2C Tx Cmd Content\n",
927 pdesc, TX_DESC_SIZE);
928}
929
930void rtl92ce_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
931{
932 if (istx == true) {
933 switch (desc_name) {
934 case HW_DESC_OWN:
935 SET_TX_DESC_OWN(pdesc, 1);
936 break;
937 case HW_DESC_TX_NEXTDESC_ADDR:
938 SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val);
939 break;
940 default:
941 RT_ASSERT(false, ("ERR txdesc :%d"
942 " not process\n", desc_name));
943 break;
944 }
945 } else {
946 switch (desc_name) {
947 case HW_DESC_RXOWN:
948 SET_RX_DESC_OWN(pdesc, 1);
949 break;
950 case HW_DESC_RXBUFF_ADDR:
951 SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *) val);
952 break;
953 case HW_DESC_RXPKT_LEN:
954 SET_RX_DESC_PKT_LEN(pdesc, *(u32 *) val);
955 break;
956 case HW_DESC_RXERO:
957 SET_RX_DESC_EOR(pdesc, 1);
958 break;
959 default:
960 RT_ASSERT(false, ("ERR rxdesc :%d "
961 "not process\n", desc_name));
962 break;
963 }
964 }
965}
966
967u32 rtl92ce_get_desc(u8 *p_desc, bool istx, u8 desc_name)
968{
969 u32 ret = 0;
970
971 if (istx == true) {
972 switch (desc_name) {
973 case HW_DESC_OWN:
974 ret = GET_TX_DESC_OWN(p_desc);
975 break;
976 case HW_DESC_TXBUFF_ADDR:
977 ret = GET_TX_DESC_TX_BUFFER_ADDRESS(p_desc);
978 break;
979 default:
980 RT_ASSERT(false, ("ERR txdesc :%d "
981 "not process\n", desc_name));
982 break;
983 }
984 } else {
985 struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
986 switch (desc_name) {
987 case HW_DESC_OWN:
988 ret = GET_RX_DESC_OWN(pdesc);
989 break;
990 case HW_DESC_RXPKT_LEN:
991 ret = GET_RX_DESC_PKT_LEN(pdesc);
992 break;
993 default:
994 RT_ASSERT(false, ("ERR rxdesc :%d "
995 "not process\n", desc_name));
996 break;
997 }
998 }
999 return ret;
1000}
1001
1002void rtl92ce_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
1003{
1004 struct rtl_priv *rtlpriv = rtl_priv(hw);
1005 if (hw_queue == BEACON_QUEUE) {
1006 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4));
1007 } else {
1008 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG,
1009 BIT(0) << (hw_queue));
1010 }
1011}
1012
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h
new file mode 100644
index 000000000000..0f1177137501
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h
@@ -0,0 +1,739 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CE_TRX_H__
31#define __RTL92CE_TRX_H__
32
33#define TX_DESC_SIZE 64
34#define TX_DESC_AGGR_SUBFRAME_SIZE 32
35
36#define RX_DESC_SIZE 32
37#define RX_DRV_INFO_SIZE_UNIT 8
38
39#define TX_DESC_NEXT_DESC_OFFSET 40
40#define USB_HWDESC_HEADER_LEN 32
41#define CRCLENGTH 4
42
43/* Define a macro that takes a le32 word, converts it to host ordering,
44 * right shifts by a specified count, creates a mask of the specified
45 * bit count, and extracts that number of bits.
46 */
47
48#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
49 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
50 BIT_LEN_MASK_32(__mask))
51
52/* Define a macro that clears a bit field in an le32 word and
53 * sets the specified value into that bit field. The resulting
54 * value remains in le32 ordering; however, it is properly converted
55 * to host ordering for the clear and set operations before conversion
56 * back to le32.
57 */
58
59#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
60 (*(__le32 *)(__pdesc) = \
61 (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
62 (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
63 (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
64
65/* macros to read/write various fields in RX or TX descriptors */
66
67#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
68 SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
69#define SET_TX_DESC_OFFSET(__pdesc, __val) \
70 SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
71#define SET_TX_DESC_BMC(__pdesc, __val) \
72 SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
73#define SET_TX_DESC_HTC(__pdesc, __val) \
74 SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
75#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
76 SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
77#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
78 SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
79#define SET_TX_DESC_LINIP(__pdesc, __val) \
80 SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
81#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
82 SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
83#define SET_TX_DESC_GF(__pdesc, __val) \
84 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
85#define SET_TX_DESC_OWN(__pdesc, __val) \
86 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
87
88#define GET_TX_DESC_PKT_SIZE(__pdesc) \
89 SHIFT_AND_MASK_LE(__pdesc, 0, 16)
90#define GET_TX_DESC_OFFSET(__pdesc) \
91 SHIFT_AND_MASK_LE(__pdesc, 16, 8)
92#define GET_TX_DESC_BMC(__pdesc) \
93 SHIFT_AND_MASK_LE(__pdesc, 24, 1)
94#define GET_TX_DESC_HTC(__pdesc) \
95 SHIFT_AND_MASK_LE(__pdesc, 25, 1)
96#define GET_TX_DESC_LAST_SEG(__pdesc) \
97 SHIFT_AND_MASK_LE(__pdesc, 26, 1)
98#define GET_TX_DESC_FIRST_SEG(__pdesc) \
99 SHIFT_AND_MASK_LE(__pdesc, 27, 1)
100#define GET_TX_DESC_LINIP(__pdesc) \
101 SHIFT_AND_MASK_LE(__pdesc, 28, 1)
102#define GET_TX_DESC_NO_ACM(__pdesc) \
103 SHIFT_AND_MASK_LE(__pdesc, 29, 1)
104#define GET_TX_DESC_GF(__pdesc) \
105 SHIFT_AND_MASK_LE(__pdesc, 30, 1)
106#define GET_TX_DESC_OWN(__pdesc) \
107 SHIFT_AND_MASK_LE(__pdesc, 31, 1)
108
109#define SET_TX_DESC_MACID(__pdesc, __val) \
110 SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
111#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
112 SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
113#define SET_TX_DESC_BK(__pdesc, __val) \
114 SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val)
115#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
116 SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
117#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
118 SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
119#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
120 SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val)
121#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
122 SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val)
123#define SET_TX_DESC_PIFS(__pdesc, __val) \
124 SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val)
125#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
126 SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
127#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
128 SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val)
129#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
130 SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val)
131#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
132 SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
133#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
134 SET_BITS_OFFSET_LE(__pdesc+4, 24, 8, __val)
135
136#define GET_TX_DESC_MACID(__pdesc) \
137 SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
138#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
139 SHIFT_AND_MASK_LE(__pdesc+4, 5, 1)
140#define GET_TX_DESC_AGG_BREAK(__pdesc) \
141 SHIFT_AND_MASK_LE(__pdesc+4, 6, 1)
142#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
143 SHIFT_AND_MASK_LE(__pdesc+4, 7, 1)
144#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
145 SHIFT_AND_MASK_LE(__pdesc+4, 8, 5)
146#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
147 SHIFT_AND_MASK_LE(__pdesc+4, 13, 1)
148#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
149 SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
150#define GET_TX_DESC_PIFS(__pdesc) \
151 SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
152#define GET_TX_DESC_RATE_ID(__pdesc) \
153 SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
154#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
155 SHIFT_AND_MASK_LE(__pdesc+4, 20, 1)
156#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
157 SHIFT_AND_MASK_LE(__pdesc+4, 21, 1)
158#define GET_TX_DESC_SEC_TYPE(__pdesc) \
159 SHIFT_AND_MASK_LE(__pdesc+4, 22, 2)
160#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
161 SHIFT_AND_MASK_LE(__pdesc+4, 24, 8)
162
163#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
164 SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val)
165#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
166 SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val)
167#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
168 SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val)
169#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
170 SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
171#define SET_TX_DESC_RAW(__pdesc, __val) \
172 SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val)
173#define SET_TX_DESC_CCX(__pdesc, __val) \
174 SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val)
175#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
176 SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
177#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
178 SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val)
179#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
180 SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val)
181#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \
182 SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val)
183#define SET_TX_DESC_TX_ANTL(__pdesc, __val) \
184 SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val)
185#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
186 SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val)
187
188#define GET_TX_DESC_RTS_RC(__pdesc) \
189 SHIFT_AND_MASK_LE(__pdesc+8, 0, 6)
190#define GET_TX_DESC_DATA_RC(__pdesc) \
191 SHIFT_AND_MASK_LE(__pdesc+8, 6, 6)
192#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
193 SHIFT_AND_MASK_LE(__pdesc+8, 14, 2)
194#define GET_TX_DESC_MORE_FRAG(__pdesc) \
195 SHIFT_AND_MASK_LE(__pdesc+8, 17, 1)
196#define GET_TX_DESC_RAW(__pdesc) \
197 SHIFT_AND_MASK_LE(__pdesc+8, 18, 1)
198#define GET_TX_DESC_CCX(__pdesc) \
199 SHIFT_AND_MASK_LE(__pdesc+8, 19, 1)
200#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
201 SHIFT_AND_MASK_LE(__pdesc+8, 20, 3)
202#define GET_TX_DESC_ANTSEL_A(__pdesc) \
203 SHIFT_AND_MASK_LE(__pdesc+8, 24, 1)
204#define GET_TX_DESC_ANTSEL_B(__pdesc) \
205 SHIFT_AND_MASK_LE(__pdesc+8, 25, 1)
206#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
207 SHIFT_AND_MASK_LE(__pdesc+8, 26, 2)
208#define GET_TX_DESC_TX_ANTL(__pdesc) \
209 SHIFT_AND_MASK_LE(__pdesc+8, 28, 2)
210#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
211 SHIFT_AND_MASK_LE(__pdesc+8, 30, 2)
212
213#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
214 SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val)
215#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
216 SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val)
217#define SET_TX_DESC_SEQ(__pdesc, __val) \
218 SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
219#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
220 SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
221
222#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
223 SHIFT_AND_MASK_LE(__pdesc+12, 0, 8)
224#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
225 SHIFT_AND_MASK_LE(__pdesc+12, 8, 8)
226#define GET_TX_DESC_SEQ(__pdesc) \
227 SHIFT_AND_MASK_LE(__pdesc+12, 16, 12)
228#define GET_TX_DESC_PKT_ID(__pdesc) \
229 SHIFT_AND_MASK_LE(__pdesc+12, 28, 4)
230
231#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
232 SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
233#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
234 SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val)
235#define SET_TX_DESC_QOS(__pdesc, __val) \
236 SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
237#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
238 SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
239#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
240 SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
241#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
242 SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val)
243#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
244 SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
245#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
246 SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
247#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
248 SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
249#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
250 SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
251#define SET_TX_DESC_PORT_ID(__pdesc, __val) \
252 SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val)
253#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \
254 SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
255#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \
256 SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val)
257#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
258 SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
259#define SET_TX_DESC_TX_STBC(__pdesc, __val) \
260 SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val)
261#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
262 SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
263#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
264 SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
265#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
266 SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
267#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
268 SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
269#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
270 SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
271#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
272 SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
273
274#define GET_TX_DESC_RTS_RATE(__pdesc) \
275 SHIFT_AND_MASK_LE(__pdesc+16, 0, 5)
276#define GET_TX_DESC_AP_DCFE(__pdesc) \
277 SHIFT_AND_MASK_LE(__pdesc+16, 5, 1)
278#define GET_TX_DESC_QOS(__pdesc) \
279 SHIFT_AND_MASK_LE(__pdesc+16, 6, 1)
280#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
281 SHIFT_AND_MASK_LE(__pdesc+16, 7, 1)
282#define GET_TX_DESC_USE_RATE(__pdesc) \
283 SHIFT_AND_MASK_LE(__pdesc+16, 8, 1)
284#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
285 SHIFT_AND_MASK_LE(__pdesc+16, 9, 1)
286#define GET_TX_DESC_DISABLE_FB(__pdesc) \
287 SHIFT_AND_MASK_LE(__pdesc+16, 10, 1)
288#define GET_TX_DESC_CTS2SELF(__pdesc) \
289 SHIFT_AND_MASK_LE(__pdesc+16, 11, 1)
290#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
291 SHIFT_AND_MASK_LE(__pdesc+16, 12, 1)
292#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
293 SHIFT_AND_MASK_LE(__pdesc+16, 13, 1)
294#define GET_TX_DESC_PORT_ID(__pdesc) \
295 SHIFT_AND_MASK_LE(__pdesc+16, 14, 1)
296#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
297 SHIFT_AND_MASK_LE(__pdesc+16, 18, 1)
298#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
299 SHIFT_AND_MASK_LE(__pdesc+16, 19, 1)
300#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
301 SHIFT_AND_MASK_LE(__pdesc+16, 20, 2)
302#define GET_TX_DESC_TX_STBC(__pdesc) \
303 SHIFT_AND_MASK_LE(__pdesc+16, 22, 2)
304#define GET_TX_DESC_DATA_SHORT(__pdesc) \
305 SHIFT_AND_MASK_LE(__pdesc+16, 24, 1)
306#define GET_TX_DESC_DATA_BW(__pdesc) \
307 SHIFT_AND_MASK_LE(__pdesc+16, 25, 1)
308#define GET_TX_DESC_RTS_SHORT(__pdesc) \
309 SHIFT_AND_MASK_LE(__pdesc+16, 26, 1)
310#define GET_TX_DESC_RTS_BW(__pdesc) \
311 SHIFT_AND_MASK_LE(__pdesc+16, 27, 1)
312#define GET_TX_DESC_RTS_SC(__pdesc) \
313 SHIFT_AND_MASK_LE(__pdesc+16, 28, 2)
314#define GET_TX_DESC_RTS_STBC(__pdesc) \
315 SHIFT_AND_MASK_LE(__pdesc+16, 30, 2)
316
317#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
318 SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
319#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
320 SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
321#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
322 SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
323#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
324 SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
325#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
326 SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
327#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
328 SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val)
329#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
330 SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val)
331#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
332 SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val)
333
334#define GET_TX_DESC_TX_RATE(__pdesc) \
335 SHIFT_AND_MASK_LE(__pdesc+20, 0, 6)
336#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
337 SHIFT_AND_MASK_LE(__pdesc+20, 6, 1)
338#define GET_TX_DESC_CCX_TAG(__pdesc) \
339 SHIFT_AND_MASK_LE(__pdesc+20, 7, 1)
340#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
341 SHIFT_AND_MASK_LE(__pdesc+20, 8, 5)
342#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
343 SHIFT_AND_MASK_LE(__pdesc+20, 13, 4)
344#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
345 SHIFT_AND_MASK_LE(__pdesc+20, 17, 1)
346#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
347 SHIFT_AND_MASK_LE(__pdesc+20, 18, 6)
348#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \
349 SHIFT_AND_MASK_LE(__pdesc+20, 24, 8)
350
351#define SET_TX_DESC_TXAGC_A(__pdesc, __val) \
352 SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val)
353#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
354 SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val)
355#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
356 SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val)
357#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
358 SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
359#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
360 SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val)
361#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \
362 SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val)
363#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \
364 SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val)
365#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \
366 SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val)
367
368#define GET_TX_DESC_TXAGC_A(__pdesc) \
369 SHIFT_AND_MASK_LE(__pdesc+24, 0, 5)
370#define GET_TX_DESC_TXAGC_B(__pdesc) \
371 SHIFT_AND_MASK_LE(__pdesc+24, 5, 5)
372#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
373 SHIFT_AND_MASK_LE(__pdesc+24, 10, 1)
374#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
375 SHIFT_AND_MASK_LE(__pdesc+24, 11, 5)
376#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
377 SHIFT_AND_MASK_LE(__pdesc+24, 16, 4)
378#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
379 SHIFT_AND_MASK_LE(__pdesc+24, 20, 4)
380#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
381 SHIFT_AND_MASK_LE(__pdesc+24, 24, 4)
382#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
383 SHIFT_AND_MASK_LE(__pdesc+24, 28, 4)
384
385#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
386 SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
387#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \
388 SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val)
389#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \
390 SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val)
391#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \
392 SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val)
393#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \
394 SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val)
395
396#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
397 SHIFT_AND_MASK_LE(__pdesc+28, 0, 16)
398#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
399 SHIFT_AND_MASK_LE(__pdesc+28, 16, 4)
400#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
401 SHIFT_AND_MASK_LE(__pdesc+28, 20, 4)
402#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
403 SHIFT_AND_MASK_LE(__pdesc+28, 24, 4)
404#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \
405 SHIFT_AND_MASK_LE(__pdesc+28, 28, 4)
406
407#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
408 SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
409#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
410 SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
411
412#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
413 SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
414#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
415 SHIFT_AND_MASK_LE(__pdesc+36, 0, 32)
416
417#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
418 SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
419#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
420 SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val)
421
422#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
423 SHIFT_AND_MASK_LE(__pdesc+40, 0, 32)
424#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \
425 SHIFT_AND_MASK_LE(__pdesc+44, 0, 32)
426
427#define GET_RX_DESC_PKT_LEN(__pdesc) \
428 SHIFT_AND_MASK_LE(__pdesc, 0, 14)
429#define GET_RX_DESC_CRC32(__pdesc) \
430 SHIFT_AND_MASK_LE(__pdesc, 14, 1)
431#define GET_RX_DESC_ICV(__pdesc) \
432 SHIFT_AND_MASK_LE(__pdesc, 15, 1)
433#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
434 SHIFT_AND_MASK_LE(__pdesc, 16, 4)
435#define GET_RX_DESC_SECURITY(__pdesc) \
436 SHIFT_AND_MASK_LE(__pdesc, 20, 3)
437#define GET_RX_DESC_QOS(__pdesc) \
438 SHIFT_AND_MASK_LE(__pdesc, 23, 1)
439#define GET_RX_DESC_SHIFT(__pdesc) \
440 SHIFT_AND_MASK_LE(__pdesc, 24, 2)
441#define GET_RX_DESC_PHYST(__pdesc) \
442 SHIFT_AND_MASK_LE(__pdesc, 26, 1)
443#define GET_RX_DESC_SWDEC(__pdesc) \
444 SHIFT_AND_MASK_LE(__pdesc, 27, 1)
445#define GET_RX_DESC_LS(__pdesc) \
446 SHIFT_AND_MASK_LE(__pdesc, 28, 1)
447#define GET_RX_DESC_FS(__pdesc) \
448 SHIFT_AND_MASK_LE(__pdesc, 29, 1)
449#define GET_RX_DESC_EOR(__pdesc) \
450 SHIFT_AND_MASK_LE(__pdesc, 30, 1)
451#define GET_RX_DESC_OWN(__pdesc) \
452 SHIFT_AND_MASK_LE(__pdesc, 31, 1)
453
454#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
455 SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
456#define SET_RX_DESC_EOR(__pdesc, __val) \
457 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
458#define SET_RX_DESC_OWN(__pdesc, __val) \
459 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
460
461#define GET_RX_DESC_MACID(__pdesc) \
462 SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
463#define GET_RX_DESC_TID(__pdesc) \
464 SHIFT_AND_MASK_LE(__pdesc+4, 5, 4)
465#define GET_RX_DESC_HWRSVD(__pdesc) \
466 SHIFT_AND_MASK_LE(__pdesc+4, 9, 5)
467#define GET_RX_DESC_PAGGR(__pdesc) \
468 SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
469#define GET_RX_DESC_FAGGR(__pdesc) \
470 SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
471#define GET_RX_DESC_A1_FIT(__pdesc) \
472 SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
473#define GET_RX_DESC_A2_FIT(__pdesc) \
474 SHIFT_AND_MASK_LE(__pdesc+4, 20, 4)
475#define GET_RX_DESC_PAM(__pdesc) \
476 SHIFT_AND_MASK_LE(__pdesc+4, 24, 1)
477#define GET_RX_DESC_PWR(__pdesc) \
478 SHIFT_AND_MASK_LE(__pdesc+4, 25, 1)
479#define GET_RX_DESC_MD(__pdesc) \
480 SHIFT_AND_MASK_LE(__pdesc+4, 26, 1)
481#define GET_RX_DESC_MF(__pdesc) \
482 SHIFT_AND_MASK_LE(__pdesc+4, 27, 1)
483#define GET_RX_DESC_TYPE(__pdesc) \
484 SHIFT_AND_MASK_LE(__pdesc+4, 28, 2)
485#define GET_RX_DESC_MC(__pdesc) \
486 SHIFT_AND_MASK_LE(__pdesc+4, 30, 1)
487#define GET_RX_DESC_BC(__pdesc) \
488 SHIFT_AND_MASK_LE(__pdesc+4, 31, 1)
489#define GET_RX_DESC_SEQ(__pdesc) \
490 SHIFT_AND_MASK_LE(__pdesc+8, 0, 12)
491#define GET_RX_DESC_FRAG(__pdesc) \
492 SHIFT_AND_MASK_LE(__pdesc+8, 12, 4)
493#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \
494 SHIFT_AND_MASK_LE(__pdesc+8, 16, 14)
495#define GET_RX_DESC_NEXT_IND(__pdesc) \
496 SHIFT_AND_MASK_LE(__pdesc+8, 30, 1)
497#define GET_RX_DESC_RSVD(__pdesc) \
498 SHIFT_AND_MASK_LE(__pdesc+8, 31, 1)
499
500#define GET_RX_DESC_RXMCS(__pdesc) \
501 SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
502#define GET_RX_DESC_RXHT(__pdesc) \
503 SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
504#define GET_RX_DESC_SPLCP(__pdesc) \
505 SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
506#define GET_RX_DESC_BW(__pdesc) \
507 SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
508#define GET_RX_DESC_HTC(__pdesc) \
509 SHIFT_AND_MASK_LE(__pdesc+12, 10, 1)
510#define GET_RX_DESC_HWPC_ERR(__pdesc) \
511 SHIFT_AND_MASK_LE(__pdesc+12, 14, 1)
512#define GET_RX_DESC_HWPC_IND(__pdesc) \
513 SHIFT_AND_MASK_LE(__pdesc+12, 15, 1)
514#define GET_RX_DESC_IV0(__pdesc) \
515 SHIFT_AND_MASK_LE(__pdesc+12, 16, 16)
516
517#define GET_RX_DESC_IV1(__pdesc) \
518 SHIFT_AND_MASK_LE(__pdesc+16, 0, 32)
519#define GET_RX_DESC_TSFL(__pdesc) \
520 SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
521
522#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
523 SHIFT_AND_MASK_LE(__pdesc+24, 0, 32)
524#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
525 SHIFT_AND_MASK_LE(__pdesc+28, 0, 32)
526
527#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
528 SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
529#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
530 SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
531
532#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
533do { \
534 if (_size > TX_DESC_NEXT_DESC_OFFSET) \
535 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
536 else \
537 memset(__pdesc, 0, _size); \
538} while (0);
539
540#define RX_HAL_IS_CCK_RATE(_pdesc)\
541 (_pdesc->rxmcs == DESC92C_RATE1M || \
542 _pdesc->rxmcs == DESC92C_RATE2M || \
543 _pdesc->rxmcs == DESC92C_RATE5_5M || \
544 _pdesc->rxmcs == DESC92C_RATE11M)
545
546struct rx_fwinfo_92c {
547 u8 gain_trsw[4];
548 u8 pwdb_all;
549 u8 cfosho[4];
550 u8 cfotail[4];
551 char rxevm[2];
552 char rxsnr[4];
553 u8 pdsnr[2];
554 u8 csi_current[2];
555 u8 csi_target[2];
556 u8 sigevm;
557 u8 max_ex_pwr;
558 u8 ex_intf_flag:1;
559 u8 sgi_en:1;
560 u8 rxsc:2;
561 u8 reserve:4;
562} __packed;
563
564struct tx_desc_92c {
565 u32 pktsize:16;
566 u32 offset:8;
567 u32 bmc:1;
568 u32 htc:1;
569 u32 lastseg:1;
570 u32 firstseg:1;
571 u32 linip:1;
572 u32 noacm:1;
573 u32 gf:1;
574 u32 own:1;
575
576 u32 macid:5;
577 u32 agg_en:1;
578 u32 bk:1;
579 u32 rdg_en:1;
580 u32 queuesel:5;
581 u32 rd_nav_ext:1;
582 u32 lsig_txop_en:1;
583 u32 pifs:1;
584 u32 rateid:4;
585 u32 nav_usehdr:1;
586 u32 en_descid:1;
587 u32 sectype:2;
588 u32 pktoffset:8;
589
590 u32 rts_rc:6;
591 u32 data_rc:6;
592 u32 rsvd0:2;
593 u32 bar_retryht:2;
594 u32 rsvd1:1;
595 u32 morefrag:1;
596 u32 raw:1;
597 u32 ccx:1;
598 u32 ampdudensity:3;
599 u32 rsvd2:1;
600 u32 ant_sela:1;
601 u32 ant_selb:1;
602 u32 txant_cck:2;
603 u32 txant_l:2;
604 u32 txant_ht:2;
605
606 u32 nextheadpage:8;
607 u32 tailpage:8;
608 u32 seq:12;
609 u32 pktid:4;
610
611 u32 rtsrate:5;
612 u32 apdcfe:1;
613 u32 qos:1;
614 u32 hwseq_enable:1;
615 u32 userrate:1;
616 u32 dis_rtsfb:1;
617 u32 dis_datafb:1;
618 u32 cts2self:1;
619 u32 rts_en:1;
620 u32 hwrts_en:1;
621 u32 portid:1;
622 u32 rsvd3:3;
623 u32 waitdcts:1;
624 u32 cts2ap_en:1;
625 u32 txsc:2;
626 u32 stbc:2;
627 u32 txshort:1;
628 u32 txbw:1;
629 u32 rtsshort:1;
630 u32 rtsbw:1;
631 u32 rtssc:2;
632 u32 rtsstbc:2;
633
634 u32 txrate:6;
635 u32 shortgi:1;
636 u32 ccxt:1;
637 u32 txrate_fb_lmt:5;
638 u32 rtsrate_fb_lmt:4;
639 u32 retrylmt_en:1;
640 u32 txretrylmt:6;
641 u32 usb_txaggnum:8;
642
643 u32 txagca:5;
644 u32 txagcb:5;
645 u32 usemaxlen:1;
646 u32 maxaggnum:5;
647 u32 mcsg1maxlen:4;
648 u32 mcsg2maxlen:4;
649 u32 mcsg3maxlen:4;
650 u32 mcs7sgimaxlen:4;
651
652 u32 txbuffersize:16;
653 u32 mcsg4maxlen:4;
654 u32 mcsg5maxlen:4;
655 u32 mcsg6maxlen:4;
656 u32 mcsg15sgimaxlen:4;
657
658 u32 txbuffaddr;
659 u32 txbufferaddr64;
660 u32 nextdescaddress;
661 u32 nextdescaddress64;
662
663 u32 reserve_pass_pcie_mm_limit[4];
664} __packed;
665
666struct rx_desc_92c {
667 u32 length:14;
668 u32 crc32:1;
669 u32 icverror:1;
670 u32 drv_infosize:4;
671 u32 security:3;
672 u32 qos:1;
673 u32 shift:2;
674 u32 phystatus:1;
675 u32 swdec:1;
676 u32 lastseg:1;
677 u32 firstseg:1;
678 u32 eor:1;
679 u32 own:1;
680
681 u32 macid:5;
682 u32 tid:4;
683 u32 hwrsvd:5;
684 u32 paggr:1;
685 u32 faggr:1;
686 u32 a1_fit:4;
687 u32 a2_fit:4;
688 u32 pam:1;
689 u32 pwr:1;
690 u32 moredata:1;
691 u32 morefrag:1;
692 u32 type:2;
693 u32 mc:1;
694 u32 bc:1;
695
696 u32 seq:12;
697 u32 frag:4;
698 u32 nextpktlen:14;
699 u32 nextind:1;
700 u32 rsvd:1;
701
702 u32 rxmcs:6;
703 u32 rxht:1;
704 u32 amsdu:1;
705 u32 splcp:1;
706 u32 bandwidth:1;
707 u32 htc:1;
708 u32 tcpchk_rpt:1;
709 u32 ipcchk_rpt:1;
710 u32 tcpchk_valid:1;
711 u32 hwpcerr:1;
712 u32 hwpcind:1;
713 u32 iv0:16;
714
715 u32 iv1;
716
717 u32 tsfl;
718
719 u32 bufferaddress;
720 u32 bufferaddress64;
721
722} __packed;
723
724void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
725 struct ieee80211_hdr *hdr,
726 u8 *pdesc, struct ieee80211_tx_info *info,
727 struct sk_buff *skb, u8 hw_queue,
728 struct rtl_tcb_desc *ptcb_desc);
729bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
730 struct rtl_stats *stats,
731 struct ieee80211_rx_status *rx_status,
732 u8 *pdesc, struct sk_buff *skb);
733void rtl92ce_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val);
734u32 rtl92ce_get_desc(u8 *pdesc, bool istx, u8 desc_name);
735void rtl92ce_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
736void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
737 bool b_firstseg, bool b_lastseg,
738 struct sk_buff *skb);
739#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-12 19:56:51 -0400