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path: root/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
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Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8192ce/phy.c')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/phy.c635
1 files changed, 635 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
new file mode 100644
index 000000000000..abe0fcc75368
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
@@ -0,0 +1,635 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "hw.h"
36#include "phy.h"
37#include "rf.h"
38#include "dm.h"
39#include "table.h"
40
41static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
42
43u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
44 enum radio_path rfpath, u32 regaddr, u32 bitmask)
45{
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 u32 original_value, readback_value, bitshift;
48 struct rtl_phy *rtlphy = &(rtlpriv->phy);
49 unsigned long flags;
50
51 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
52 "rfpath(%#x), bitmask(%#x)\n",
53 regaddr, rfpath, bitmask));
54
55 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
56
57 if (rtlphy->rf_mode != RF_OP_BY_FW) {
58 original_value = _rtl92c_phy_rf_serial_read(hw,
59 rfpath, regaddr);
60 } else {
61 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
62 rfpath, regaddr);
63 }
64
65 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
66 readback_value = (original_value & bitmask) >> bitshift;
67
68 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
69
70 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
71 ("regaddr(%#x), rfpath(%#x), "
72 "bitmask(%#x), original_value(%#x)\n",
73 regaddr, rfpath, bitmask, original_value));
74
75 return readback_value;
76}
77
78bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
79{
80 struct rtl_priv *rtlpriv = rtl_priv(hw);
81 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
82 bool is92c = IS_92C_SERIAL(rtlhal->version);
83 bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
84
85 if (is92c)
86 rtl_write_byte(rtlpriv, 0x14, 0x71);
87 return rtstatus;
88}
89
90bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
91{
92 bool rtstatus = true;
93 struct rtl_priv *rtlpriv = rtl_priv(hw);
94 u16 regval;
95 u32 regvaldw;
96 u8 reg_hwparafile = 1;
97
98 _rtl92c_phy_init_bb_rf_register_definition(hw);
99 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
100 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
101 regval | BIT(13) | BIT(0) | BIT(1));
102 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
103 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
104 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
105 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
106 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
107 FEN_BB_GLB_RSTn | FEN_BBRSTB);
108 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
109 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
110 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
111 if (reg_hwparafile == 1)
112 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
113 return rtstatus;
114}
115
116void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
117 enum radio_path rfpath,
118 u32 regaddr, u32 bitmask, u32 data)
119{
120 struct rtl_priv *rtlpriv = rtl_priv(hw);
121 struct rtl_phy *rtlphy = &(rtlpriv->phy);
122 u32 original_value, bitshift;
123 unsigned long flags;
124
125 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
126 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
127 regaddr, bitmask, data, rfpath));
128
129 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
130
131 if (rtlphy->rf_mode != RF_OP_BY_FW) {
132 if (bitmask != RFREG_OFFSET_MASK) {
133 original_value = _rtl92c_phy_rf_serial_read(hw,
134 rfpath,
135 regaddr);
136 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
137 data =
138 ((original_value & (~bitmask)) |
139 (data << bitshift));
140 }
141
142 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
143 } else {
144 if (bitmask != RFREG_OFFSET_MASK) {
145 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
146 rfpath,
147 regaddr);
148 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
149 data =
150 ((original_value & (~bitmask)) |
151 (data << bitshift));
152 }
153 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
154 }
155
156 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
157
158 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
159 "bitmask(%#x), data(%#x), "
160 "rfpath(%#x)\n", regaddr,
161 bitmask, data, rfpath));
162}
163
164static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
165{
166 struct rtl_priv *rtlpriv = rtl_priv(hw);
167 u32 i;
168 u32 arraylength;
169 u32 *ptrarray;
170
171 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
172 arraylength = MAC_2T_ARRAYLENGTH;
173 ptrarray = RTL8192CEMAC_2T_ARRAY;
174 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
175 ("Img:RTL8192CEMAC_2T_ARRAY\n"));
176 for (i = 0; i < arraylength; i = i + 2)
177 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
178 return true;
179}
180
181bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
182 u8 configtype)
183{
184 int i;
185 u32 *phy_regarray_table;
186 u32 *agctab_array_table;
187 u16 phy_reg_arraylen, agctab_arraylen;
188 struct rtl_priv *rtlpriv = rtl_priv(hw);
189 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
190
191 if (IS_92C_SERIAL(rtlhal->version)) {
192 agctab_arraylen = AGCTAB_2TARRAYLENGTH;
193 agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
194 phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
195 phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
196 } else {
197 agctab_arraylen = AGCTAB_1TARRAYLENGTH;
198 agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
199 phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
200 phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
201 }
202 if (configtype == BASEBAND_CONFIG_PHY_REG) {
203 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
204 if (phy_regarray_table[i] == 0xfe)
205 mdelay(50);
206 else if (phy_regarray_table[i] == 0xfd)
207 mdelay(5);
208 else if (phy_regarray_table[i] == 0xfc)
209 mdelay(1);
210 else if (phy_regarray_table[i] == 0xfb)
211 udelay(50);
212 else if (phy_regarray_table[i] == 0xfa)
213 udelay(5);
214 else if (phy_regarray_table[i] == 0xf9)
215 udelay(1);
216 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
217 phy_regarray_table[i + 1]);
218 udelay(1);
219 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
220 ("The phy_regarray_table[0] is %x"
221 " Rtl819XPHY_REGArray[1] is %x\n",
222 phy_regarray_table[i],
223 phy_regarray_table[i + 1]));
224 }
225 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
226 for (i = 0; i < agctab_arraylen; i = i + 2) {
227 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
228 agctab_array_table[i + 1]);
229 udelay(1);
230 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
231 ("The agctab_array_table[0] is "
232 "%x Rtl819XPHY_REGArray[1] is %x\n",
233 agctab_array_table[i],
234 agctab_array_table[i + 1]));
235 }
236 }
237 return true;
238}
239
240bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
241 u8 configtype)
242{
243 struct rtl_priv *rtlpriv = rtl_priv(hw);
244 int i;
245 u32 *phy_regarray_table_pg;
246 u16 phy_regarray_pg_len;
247
248 phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
249 phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
250
251 if (configtype == BASEBAND_CONFIG_PHY_REG) {
252 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
253 if (phy_regarray_table_pg[i] == 0xfe)
254 mdelay(50);
255 else if (phy_regarray_table_pg[i] == 0xfd)
256 mdelay(5);
257 else if (phy_regarray_table_pg[i] == 0xfc)
258 mdelay(1);
259 else if (phy_regarray_table_pg[i] == 0xfb)
260 udelay(50);
261 else if (phy_regarray_table_pg[i] == 0xfa)
262 udelay(5);
263 else if (phy_regarray_table_pg[i] == 0xf9)
264 udelay(1);
265
266 _rtl92c_store_pwrIndex_diffrate_offset(hw,
267 phy_regarray_table_pg[i],
268 phy_regarray_table_pg[i + 1],
269 phy_regarray_table_pg[i + 2]);
270 }
271 } else {
272
273 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
274 ("configtype != BaseBand_Config_PHY_REG\n"));
275 }
276 return true;
277}
278
279bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
280 enum radio_path rfpath)
281{
282
283 int i;
284 bool rtstatus = true;
285 u32 *radioa_array_table;
286 u32 *radiob_array_table;
287 u16 radioa_arraylen, radiob_arraylen;
288 struct rtl_priv *rtlpriv = rtl_priv(hw);
289 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
290
291 if (IS_92C_SERIAL(rtlhal->version)) {
292 radioa_arraylen = RADIOA_2TARRAYLENGTH;
293 radioa_array_table = RTL8192CERADIOA_2TARRAY;
294 radiob_arraylen = RADIOB_2TARRAYLENGTH;
295 radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
296 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
297 ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
298 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
299 ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
300 } else {
301 radioa_arraylen = RADIOA_1TARRAYLENGTH;
302 radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
303 radiob_arraylen = RADIOB_1TARRAYLENGTH;
304 radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
305 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
306 ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
307 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
308 ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
309 }
310 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
311 rtstatus = true;
312 switch (rfpath) {
313 case RF90_PATH_A:
314 for (i = 0; i < radioa_arraylen; i = i + 2) {
315 if (radioa_array_table[i] == 0xfe)
316 mdelay(50);
317 else if (radioa_array_table[i] == 0xfd)
318 mdelay(5);
319 else if (radioa_array_table[i] == 0xfc)
320 mdelay(1);
321 else if (radioa_array_table[i] == 0xfb)
322 udelay(50);
323 else if (radioa_array_table[i] == 0xfa)
324 udelay(5);
325 else if (radioa_array_table[i] == 0xf9)
326 udelay(1);
327 else {
328 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
329 RFREG_OFFSET_MASK,
330 radioa_array_table[i + 1]);
331 udelay(1);
332 }
333 }
334 break;
335 case RF90_PATH_B:
336 for (i = 0; i < radiob_arraylen; i = i + 2) {
337 if (radiob_array_table[i] == 0xfe) {
338 mdelay(50);
339 } else if (radiob_array_table[i] == 0xfd)
340 mdelay(5);
341 else if (radiob_array_table[i] == 0xfc)
342 mdelay(1);
343 else if (radiob_array_table[i] == 0xfb)
344 udelay(50);
345 else if (radiob_array_table[i] == 0xfa)
346 udelay(5);
347 else if (radiob_array_table[i] == 0xf9)
348 udelay(1);
349 else {
350 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
351 RFREG_OFFSET_MASK,
352 radiob_array_table[i + 1]);
353 udelay(1);
354 }
355 }
356 break;
357 case RF90_PATH_C:
358 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
359 ("switch case not process\n"));
360 break;
361 case RF90_PATH_D:
362 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
363 ("switch case not process\n"));
364 break;
365 }
366 return true;
367}
368
369void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
370{
371 struct rtl_priv *rtlpriv = rtl_priv(hw);
372 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
373 struct rtl_phy *rtlphy = &(rtlpriv->phy);
374 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
375 u8 reg_bw_opmode;
376 u8 reg_prsr_rsc;
377
378 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
379 ("Switch to %s bandwidth\n",
380 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
381 "20MHz" : "40MHz"))
382
383 if (is_hal_stop(rtlhal)) {
384 rtlphy->set_bwmode_inprogress = false;
385 return;
386 }
387
388 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
389 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
390
391 switch (rtlphy->current_chan_bw) {
392 case HT_CHANNEL_WIDTH_20:
393 reg_bw_opmode |= BW_OPMODE_20MHZ;
394 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
395 break;
396 case HT_CHANNEL_WIDTH_20_40:
397 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
398 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
399 reg_prsr_rsc =
400 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
401 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
402 break;
403 default:
404 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
405 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
406 break;
407 }
408
409 switch (rtlphy->current_chan_bw) {
410 case HT_CHANNEL_WIDTH_20:
411 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
412 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
413 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
414 break;
415 case HT_CHANNEL_WIDTH_20_40:
416 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
417 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
418
419 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
420 (mac->cur_40_prime_sc >> 1));
421 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
422 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
423
424 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
425 (mac->cur_40_prime_sc ==
426 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
427 break;
428 default:
429 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
430 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
431 break;
432 }
433 rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
434 rtlphy->set_bwmode_inprogress = false;
435 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
436}
437
438void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
439{
440 u8 tmpreg;
441 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
442 struct rtl_priv *rtlpriv = rtl_priv(hw);
443
444 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
445
446 if ((tmpreg & 0x70) != 0)
447 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
448 else
449 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
450
451 if ((tmpreg & 0x70) != 0) {
452 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
453
454 if (is2t)
455 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
456 MASK12BITS);
457
458 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
459 (rf_a_mode & 0x8FFFF) | 0x10000);
460
461 if (is2t)
462 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
463 (rf_b_mode & 0x8FFFF) | 0x10000);
464 }
465 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
466
467 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
468
469 mdelay(100);
470
471 if ((tmpreg & 0x70) != 0) {
472 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
473 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
474
475 if (is2t)
476 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
477 rf_b_mode);
478 } else {
479 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
480 }
481}
482
483static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
484{
485 u32 u4b_tmp;
486 u8 delay = 5;
487 struct rtl_priv *rtlpriv = rtl_priv(hw);
488
489 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
490 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
491 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
492 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
493 while (u4b_tmp != 0 && delay > 0) {
494 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
495 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
496 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
497 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
498 delay--;
499 }
500 if (delay == 0) {
501 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
502 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
503 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
504 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
505 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
506 ("Switch RF timeout !!!.\n"));
507 return;
508 }
509 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
510 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
511}
512
513static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
514 enum rf_pwrstate rfpwr_state)
515{
516 struct rtl_priv *rtlpriv = rtl_priv(hw);
517 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
518 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
519 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
520 bool bresult = true;
521 u8 i, queue_id;
522 struct rtl8192_tx_ring *ring = NULL;
523
524 ppsc->set_rfpowerstate_inprogress = true;
525 switch (rfpwr_state) {
526 case ERFON:{
527 if ((ppsc->rfpwr_state == ERFOFF) &&
528 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
529 bool rtstatus;
530 u32 InitializeCount = 0;
531 do {
532 InitializeCount++;
533 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
534 ("IPS Set eRf nic enable\n"));
535 rtstatus = rtl_ps_enable_nic(hw);
536 } while ((rtstatus != true)
537 && (InitializeCount < 10));
538 RT_CLEAR_PS_LEVEL(ppsc,
539 RT_RF_OFF_LEVL_HALT_NIC);
540 } else {
541 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
542 ("Set ERFON sleeped:%d ms\n",
543 jiffies_to_msecs(jiffies -
544 ppsc->
545 last_sleep_jiffies)));
546 ppsc->last_awake_jiffies = jiffies;
547 rtl92ce_phy_set_rf_on(hw);
548 }
549 if (mac->link_state == MAC80211_LINKED) {
550 rtlpriv->cfg->ops->led_control(hw,
551 LED_CTL_LINK);
552 } else {
553 rtlpriv->cfg->ops->led_control(hw,
554 LED_CTL_NO_LINK);
555 }
556 break;
557 }
558 case ERFOFF:{
559 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
560 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
561 ("IPS Set eRf nic disable\n"));
562 rtl_ps_disable_nic(hw);
563 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
564 } else {
565 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
566 rtlpriv->cfg->ops->led_control(hw,
567 LED_CTL_NO_LINK);
568 } else {
569 rtlpriv->cfg->ops->led_control(hw,
570 LED_CTL_POWER_OFF);
571 }
572 }
573 break;
574 }
575 case ERFSLEEP:{
576 if (ppsc->rfpwr_state == ERFOFF)
577 break;
578 for (queue_id = 0, i = 0;
579 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
580 ring = &pcipriv->dev.tx_ring[queue_id];
581 if (skb_queue_len(&ring->queue) == 0) {
582 queue_id++;
583 continue;
584 } else {
585 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
586 ("eRf Off/Sleep: %d times "
587 "TcbBusyQueue[%d] =%d before "
588 "doze!\n", (i + 1), queue_id,
589 skb_queue_len(&ring->queue)));
590
591 udelay(10);
592 i++;
593 }
594 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
595 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
596 ("\n ERFSLEEP: %d times "
597 "TcbBusyQueue[%d] = %d !\n",
598 MAX_DOZE_WAITING_TIMES_9x,
599 queue_id,
600 skb_queue_len(&ring->queue)));
601 break;
602 }
603 }
604 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
605 ("Set ERFSLEEP awaked:%d ms\n",
606 jiffies_to_msecs(jiffies -
607 ppsc->last_awake_jiffies)));
608 ppsc->last_sleep_jiffies = jiffies;
609 _rtl92ce_phy_set_rf_sleep(hw);
610 break;
611 }
612 default:
613 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
614 ("switch case not process\n"));
615 bresult = false;
616 break;
617 }
618 if (bresult)
619 ppsc->rfpwr_state = rfpwr_state;
620 ppsc->set_rfpowerstate_inprogress = false;
621 return bresult;
622}
623
624bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
625 enum rf_pwrstate rfpwr_state)
626{
627 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
628
629 bool bresult = false;
630
631 if (rfpwr_state == ppsc->rfpwr_state)
632 return bresult;
633 bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
634 return bresult;
635}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-14 03:44:03 -0400