diff options
author | Larry Finger <Larry.Finger@lwfinger.net> | 2014-03-04 17:53:48 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2014-03-06 14:29:56 -0500 |
commit | 25b13dbc38a74b76da5746d75867e306b70035bd (patch) | |
tree | f577599d398ca0fa96b32ef515b3ad0f6a04bc8d /drivers/net/wireless/rtlwifi/ps.h | |
parent | f3355dd9f7c261d2a3e505ba5c62ffe3cd4df97a (diff) |
rtlwifi: Move common routines to core
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rtlwifi/ps.h')
-rw-r--r-- | drivers/net/wireless/rtlwifi/ps.h | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/ps.h b/drivers/net/wireless/rtlwifi/ps.h index 88bd76ea88f7..3bd41f958974 100644 --- a/drivers/net/wireless/rtlwifi/ps.h +++ b/drivers/net/wireless/rtlwifi/ps.h | |||
@@ -32,6 +32,66 @@ | |||
32 | 32 | ||
33 | #define MAX_SW_LPS_SLEEP_INTV 5 | 33 | #define MAX_SW_LPS_SLEEP_INTV 5 |
34 | 34 | ||
35 | /*--------------------------------------------- | ||
36 | * 3 The value of cmd: 4 bits | ||
37 | *--------------------------------------------- | ||
38 | */ | ||
39 | #define PWR_CMD_READ 0x00 | ||
40 | #define PWR_CMD_WRITE 0x01 | ||
41 | #define PWR_CMD_POLLING 0x02 | ||
42 | #define PWR_CMD_DELAY 0x03 | ||
43 | #define PWR_CMD_END 0x04 | ||
44 | |||
45 | /* define the base address of each block */ | ||
46 | #define PWR_BASEADDR_MAC 0x00 | ||
47 | #define PWR_BASEADDR_USB 0x01 | ||
48 | #define PWR_BASEADDR_PCIE 0x02 | ||
49 | #define PWR_BASEADDR_SDIO 0x03 | ||
50 | |||
51 | #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) | ||
52 | #define PWR_CUT_TESTCHIP_MSK BIT(0) | ||
53 | #define PWR_CUT_A_MSK BIT(1) | ||
54 | #define PWR_CUT_B_MSK BIT(2) | ||
55 | #define PWR_CUT_C_MSK BIT(3) | ||
56 | #define PWR_CUT_D_MSK BIT(4) | ||
57 | #define PWR_CUT_E_MSK BIT(5) | ||
58 | #define PWR_CUT_F_MSK BIT(6) | ||
59 | #define PWR_CUT_G_MSK BIT(7) | ||
60 | #define PWR_CUT_ALL_MSK 0xFF | ||
61 | #define PWR_INTF_SDIO_MSK BIT(0) | ||
62 | #define PWR_INTF_USB_MSK BIT(1) | ||
63 | #define PWR_INTF_PCI_MSK BIT(2) | ||
64 | #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) | ||
65 | |||
66 | enum pwrseq_delay_unit { | ||
67 | PWRSEQ_DELAY_US, | ||
68 | PWRSEQ_DELAY_MS, | ||
69 | }; | ||
70 | |||
71 | struct wlan_pwr_cfg { | ||
72 | u16 offset; | ||
73 | u8 cut_msk; | ||
74 | u8 fab_msk:4; | ||
75 | u8 interface_msk:4; | ||
76 | u8 base:4; | ||
77 | u8 cmd:4; | ||
78 | u8 msk; | ||
79 | u8 value; | ||
80 | }; | ||
81 | |||
82 | #define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset) | ||
83 | #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk) | ||
84 | #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk) | ||
85 | #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk) | ||
86 | #define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base) | ||
87 | #define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd) | ||
88 | #define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk) | ||
89 | #define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value) | ||
90 | |||
91 | bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, | ||
92 | u8 fab_version, u8 interface_type, | ||
93 | struct wlan_pwr_cfg pwrcfgcmd[]); | ||
94 | |||
35 | bool rtl_ps_set_rf_state(struct ieee80211_hw *hw, | 95 | bool rtl_ps_set_rf_state(struct ieee80211_hw *hw, |
36 | enum rf_pwrstate state_toset, u32 changesource); | 96 | enum rf_pwrstate state_toset, u32 changesource); |
37 | bool rtl_ps_enable_nic(struct ieee80211_hw *hw); | 97 | bool rtl_ps_enable_nic(struct ieee80211_hw *hw); |