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authorLarry Finger <Larry.Finger@lwfinger.net>2014-03-04 17:53:48 -0500
committerJohn W. Linville <linville@tuxdriver.com>2014-03-06 14:29:56 -0500
commit25b13dbc38a74b76da5746d75867e306b70035bd (patch)
treef577599d398ca0fa96b32ef515b3ad0f6a04bc8d
parentf3355dd9f7c261d2a3e505ba5c62ffe3cd4df97a (diff)
rtlwifi: Move common routines to core
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/rtlwifi/btcoexist/halbt_precomp.h12
-rw-r--r--drivers/net/wireless/rtlwifi/core.c60
-rw-r--r--drivers/net/wireless/rtlwifi/core.h4
-rw-r--r--drivers/net/wireless/rtlwifi/ps.c100
-rw-r--r--drivers/net/wireless/rtlwifi/ps.h60
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/Makefile1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/hw.c19
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/phy.c61
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8188ee/reg.h16
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/phy.c71
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/reg.h16
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/phy.c71
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/dm.c50
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/hw.c10
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/phy.c429
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/reg.h14
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/rf.c6
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/phy.c87
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/reg.h12
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/Makefile1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/hw.c1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/phy.c48
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/reg.h16
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/Makefile1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/hw.c15
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/phy.c29
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.h1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723be/reg.h16
-rw-r--r--drivers/net/wireless/rtlwifi/wifi.h16
31 files changed, 520 insertions, 725 deletions
diff --git a/drivers/net/wireless/rtlwifi/btcoexist/halbt_precomp.h b/drivers/net/wireless/rtlwifi/btcoexist/halbt_precomp.h
index 582532fc199a..d76684eb24d0 100644
--- a/drivers/net/wireless/rtlwifi/btcoexist/halbt_precomp.h
+++ b/drivers/net/wireless/rtlwifi/btcoexist/halbt_precomp.h
@@ -72,16 +72,4 @@
72#define BIT30 0x40000000 72#define BIT30 0x40000000
73#define BIT31 0x80000000 73#define BIT31 0x80000000
74 74
75#define MASKBYTE0 0xff
76#define MASKBYTE1 0xff00
77#define MASKBYTE2 0xff0000
78#define MASKBYTE3 0xff000000
79#define MASKHWORD 0xffff0000
80#define MASKLWORD 0x0000ffff
81#define MASKDWORD 0xffffffff
82#define MASK12BITS 0xfff
83#define MASKH4BITS 0xf0000000
84#define MASKOFDM_D 0xffc00000
85#define MASKCCK 0x3f3f3f3f
86
87#endif /* __HALBT_PRECOMP_H__ */ 75#endif /* __HALBT_PRECOMP_H__ */
diff --git a/drivers/net/wireless/rtlwifi/core.c b/drivers/net/wireless/rtlwifi/core.c
index 724b830fe429..ded691f76f2f 100644
--- a/drivers/net/wireless/rtlwifi/core.c
+++ b/drivers/net/wireless/rtlwifi/core.c
@@ -36,6 +36,66 @@
36 36
37#include <linux/export.h> 37#include <linux/export.h>
38 38
39void rtl_addr_delay(u32 addr)
40{
41 if (addr == 0xfe)
42 mdelay(50);
43 else if (addr == 0xfd)
44 mdelay(5);
45 else if (addr == 0xfc)
46 mdelay(1);
47 else if (addr == 0xfb)
48 udelay(50);
49 else if (addr == 0xfa)
50 udelay(5);
51 else if (addr == 0xf9)
52 udelay(1);
53}
54EXPORT_SYMBOL(rtl_addr_delay);
55
56void rtl_rfreg_delay(struct ieee80211_hw *hw, enum radio_path rfpath, u32 addr,
57 u32 mask, u32 data)
58{
59 if (addr == 0xfe) {
60 mdelay(50);
61 } else if (addr == 0xfd) {
62 mdelay(5);
63 } else if (addr == 0xfc) {
64 mdelay(1);
65 } else if (addr == 0xfb) {
66 udelay(50);
67 } else if (addr == 0xfa) {
68 udelay(5);
69 } else if (addr == 0xf9) {
70 udelay(1);
71 } else {
72 rtl_set_rfreg(hw, rfpath, addr, mask, data);
73 udelay(1);
74 }
75}
76EXPORT_SYMBOL(rtl_rfreg_delay);
77
78void rtl_bb_delay(struct ieee80211_hw *hw, u32 addr, u32 data)
79{
80 if (addr == 0xfe) {
81 mdelay(50);
82 } else if (addr == 0xfd) {
83 mdelay(5);
84 } else if (addr == 0xfc) {
85 mdelay(1);
86 } else if (addr == 0xfb) {
87 udelay(50);
88 } else if (addr == 0xfa) {
89 udelay(5);
90 } else if (addr == 0xf9) {
91 udelay(1);
92 } else {
93 rtl_set_bbreg(hw, addr, MASKDWORD, data);
94 udelay(1);
95 }
96}
97EXPORT_SYMBOL(rtl_bb_delay);
98
39void rtl_fw_cb(const struct firmware *firmware, void *context) 99void rtl_fw_cb(const struct firmware *firmware, void *context)
40{ 100{
41 struct ieee80211_hw *hw = context; 101 struct ieee80211_hw *hw = context;
diff --git a/drivers/net/wireless/rtlwifi/core.h b/drivers/net/wireless/rtlwifi/core.h
index 2fe46a1b4f1f..027e75374dcc 100644
--- a/drivers/net/wireless/rtlwifi/core.h
+++ b/drivers/net/wireless/rtlwifi/core.h
@@ -41,5 +41,9 @@
41 41
42extern const struct ieee80211_ops rtl_ops; 42extern const struct ieee80211_ops rtl_ops;
43void rtl_fw_cb(const struct firmware *firmware, void *context); 43void rtl_fw_cb(const struct firmware *firmware, void *context);
44void rtl_addr_delay(u32 addr);
45void rtl_rfreg_delay(struct ieee80211_hw *hw, enum radio_path rfpath, u32 addr,
46 u32 mask, u32 data);
47void rtl_bb_delay(struct ieee80211_hw *hw, u32 addr, u32 data);
44 48
45#endif 49#endif
diff --git a/drivers/net/wireless/rtlwifi/ps.c b/drivers/net/wireless/rtlwifi/ps.c
index d1c0191a195b..de7f05f848ef 100644
--- a/drivers/net/wireless/rtlwifi/ps.c
+++ b/drivers/net/wireless/rtlwifi/ps.c
@@ -32,6 +32,106 @@
32#include "base.h" 32#include "base.h"
33#include "ps.h" 33#include "ps.h"
34 34
35/* Description:
36 * This routine deals with the Power Configuration CMD
37 * parsing for RTL8723/RTL8188E Series IC.
38 * Assumption:
39 * We should follow specific format that was released from HW SD.
40 */
41bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
42 u8 faversion, u8 interface_type,
43 struct wlan_pwr_cfg pwrcfgcmd[])
44{
45 struct wlan_pwr_cfg cfg_cmd = {0};
46 bool polling_bit = false;
47 u32 ary_idx = 0;
48 u8 value = 0;
49 u32 offset = 0;
50 u32 polling_count = 0;
51 u32 max_polling_cnt = 5000;
52
53 do {
54 cfg_cmd = pwrcfgcmd[ary_idx];
55 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
56 "rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), famsk(%#x),"
57 "interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
58 GET_PWR_CFG_OFFSET(cfg_cmd),
59 GET_PWR_CFG_CUT_MASK(cfg_cmd),
60 GET_PWR_CFG_FAB_MASK(cfg_cmd),
61 GET_PWR_CFG_INTF_MASK(cfg_cmd),
62 GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd),
63 GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd));
64
65 if ((GET_PWR_CFG_FAB_MASK(cfg_cmd)&faversion) &&
66 (GET_PWR_CFG_CUT_MASK(cfg_cmd)&cut_version) &&
67 (GET_PWR_CFG_INTF_MASK(cfg_cmd)&interface_type)) {
68 switch (GET_PWR_CFG_CMD(cfg_cmd)) {
69 case PWR_CMD_READ:
70 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
71 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
72 break;
73 case PWR_CMD_WRITE:
74 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
75 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
76 offset = GET_PWR_CFG_OFFSET(cfg_cmd);
77
78 /*Read the value from system register*/
79 value = rtl_read_byte(rtlpriv, offset);
80 value &= (~(GET_PWR_CFG_MASK(cfg_cmd)));
81 value |= (GET_PWR_CFG_VALUE(cfg_cmd) &
82 GET_PWR_CFG_MASK(cfg_cmd));
83
84 /*Write the value back to sytem register*/
85 rtl_write_byte(rtlpriv, offset, value);
86 break;
87 case PWR_CMD_POLLING:
88 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
89 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
90 polling_bit = false;
91 offset = GET_PWR_CFG_OFFSET(cfg_cmd);
92
93 do {
94 value = rtl_read_byte(rtlpriv, offset);
95
96 value &= GET_PWR_CFG_MASK(cfg_cmd);
97 if (value ==
98 (GET_PWR_CFG_VALUE(cfg_cmd)
99 & GET_PWR_CFG_MASK(cfg_cmd)))
100 polling_bit = true;
101 else
102 udelay(10);
103
104 if (polling_count++ > max_polling_cnt)
105 return false;
106 } while (!polling_bit);
107 break;
108 case PWR_CMD_DELAY:
109 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
110 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
111 if (GET_PWR_CFG_VALUE(cfg_cmd) ==
112 PWRSEQ_DELAY_US)
113 udelay(GET_PWR_CFG_OFFSET(cfg_cmd));
114 else
115 mdelay(GET_PWR_CFG_OFFSET(cfg_cmd));
116 break;
117 case PWR_CMD_END:
118 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
119 "rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
120 return true;
121 default:
122 RT_ASSERT(false,
123 "rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
124 break;
125 }
126
127 }
128 ary_idx++;
129 } while (1);
130
131 return true;
132}
133EXPORT_SYMBOL(rtl_hal_pwrseqcmdparsing);
134
35bool rtl_ps_enable_nic(struct ieee80211_hw *hw) 135bool rtl_ps_enable_nic(struct ieee80211_hw *hw)
36{ 136{
37 struct rtl_priv *rtlpriv = rtl_priv(hw); 137 struct rtl_priv *rtlpriv = rtl_priv(hw);
diff --git a/drivers/net/wireless/rtlwifi/ps.h b/drivers/net/wireless/rtlwifi/ps.h
index 88bd76ea88f7..3bd41f958974 100644
--- a/drivers/net/wireless/rtlwifi/ps.h
+++ b/drivers/net/wireless/rtlwifi/ps.h
@@ -32,6 +32,66 @@
32 32
33#define MAX_SW_LPS_SLEEP_INTV 5 33#define MAX_SW_LPS_SLEEP_INTV 5
34 34
35/*---------------------------------------------
36 * 3 The value of cmd: 4 bits
37 *---------------------------------------------
38 */
39#define PWR_CMD_READ 0x00
40#define PWR_CMD_WRITE 0x01
41#define PWR_CMD_POLLING 0x02
42#define PWR_CMD_DELAY 0x03
43#define PWR_CMD_END 0x04
44
45/* define the base address of each block */
46#define PWR_BASEADDR_MAC 0x00
47#define PWR_BASEADDR_USB 0x01
48#define PWR_BASEADDR_PCIE 0x02
49#define PWR_BASEADDR_SDIO 0x03
50
51#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
52#define PWR_CUT_TESTCHIP_MSK BIT(0)
53#define PWR_CUT_A_MSK BIT(1)
54#define PWR_CUT_B_MSK BIT(2)
55#define PWR_CUT_C_MSK BIT(3)
56#define PWR_CUT_D_MSK BIT(4)
57#define PWR_CUT_E_MSK BIT(5)
58#define PWR_CUT_F_MSK BIT(6)
59#define PWR_CUT_G_MSK BIT(7)
60#define PWR_CUT_ALL_MSK 0xFF
61#define PWR_INTF_SDIO_MSK BIT(0)
62#define PWR_INTF_USB_MSK BIT(1)
63#define PWR_INTF_PCI_MSK BIT(2)
64#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
65
66enum pwrseq_delay_unit {
67 PWRSEQ_DELAY_US,
68 PWRSEQ_DELAY_MS,
69};
70
71struct wlan_pwr_cfg {
72 u16 offset;
73 u8 cut_msk;
74 u8 fab_msk:4;
75 u8 interface_msk:4;
76 u8 base:4;
77 u8 cmd:4;
78 u8 msk;
79 u8 value;
80};
81
82#define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset)
83#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk)
84#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk)
85#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk)
86#define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base)
87#define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd)
88#define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk)
89#define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value)
90
91bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
92 u8 fab_version, u8 interface_type,
93 struct wlan_pwr_cfg pwrcfgcmd[]);
94
35bool rtl_ps_set_rf_state(struct ieee80211_hw *hw, 95bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
36 enum rf_pwrstate state_toset, u32 changesource); 96 enum rf_pwrstate state_toset, u32 changesource);
37bool rtl_ps_enable_nic(struct ieee80211_hw *hw); 97bool rtl_ps_enable_nic(struct ieee80211_hw *hw);
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/Makefile b/drivers/net/wireless/rtlwifi/rtl8188ee/Makefile
index 5b194e97f4b3..a85419a37651 100644
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/Makefile
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/Makefile
@@ -5,7 +5,6 @@ rtl8188ee-objs := \
5 led.o \ 5 led.o \
6 phy.o \ 6 phy.o \
7 pwrseq.o \ 7 pwrseq.o \
8 pwrseqcmd.o \
9 rf.o \ 8 rf.o \
10 sw.o \ 9 sw.o \
11 table.o \ 10 table.o \
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/hw.c b/drivers/net/wireless/rtlwifi/rtl8188ee/hw.c
index d608d75ff6ff..6561805c3a88 100644
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/hw.c
@@ -41,7 +41,6 @@
41#include "fw.h" 41#include "fw.h"
42#include "led.h" 42#include "led.h"
43#include "hw.h" 43#include "hw.h"
44#include "pwrseqcmd.h"
45#include "pwrseq.h" 44#include "pwrseq.h"
46 45
47#define LLT_CONFIG 5 46#define LLT_CONFIG 5
@@ -815,11 +814,11 @@ static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
815 814
816 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 815 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
817 /* HW Power on sequence */ 816 /* HW Power on sequence */
818 if (!rtl88_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 817 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
819 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 818 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
820 Rtl8188E_NIC_ENABLE_FLOW)) { 819 Rtl8188E_NIC_ENABLE_FLOW)) {
821 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 820 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
822 "init MAC Fail as rtl88_hal_pwrseqcmdparsing\n"); 821 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
823 return false; 822 return false;
824 } 823 }
825 824
@@ -1346,9 +1345,9 @@ static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1346 } 1345 }
1347 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF); 1346 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1348 1347
1349 rtl88_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1348 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1350 PWR_INTF_PCI_MSK, 1349 PWR_INTF_PCI_MSK,
1351 Rtl8188E_NIC_LPS_ENTER_FLOW); 1350 Rtl8188E_NIC_LPS_ENTER_FLOW);
1352 1351
1353 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1352 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1354 1353
@@ -1362,8 +1361,8 @@ static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1362 u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL); 1361 u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1363 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0)))); 1362 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1364 1363
1365 rtl88_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1364 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1366 PWR_INTF_PCI_MSK, Rtl8188E_NIC_DISABLE_FLOW); 1365 PWR_INTF_PCI_MSK, Rtl8188E_NIC_DISABLE_FLOW);
1367 1366
1368 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1); 1367 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1369 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3)))); 1368 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/phy.c b/drivers/net/wireless/rtlwifi/rtl8188ee/phy.c
index 54d4ec2dc26b..1cd6c16d597e 100644
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/phy.c
@@ -29,6 +29,7 @@
29 29
30#include "../wifi.h" 30#include "../wifi.h"
31#include "../pci.h" 31#include "../pci.h"
32#include "../core.h"
32#include "../ps.h" 33#include "../ps.h"
33#include "reg.h" 34#include "reg.h"
34#include "def.h" 35#include "def.h"
@@ -151,18 +152,7 @@ static bool config_bb_with_pgheader(struct ieee80211_hw *hw,
151 v2 = table_pg[i + 1]; 152 v2 = table_pg[i + 1];
152 153
153 if (v1 < 0xcdcdcdcd) { 154 if (v1 < 0xcdcdcdcd) {
154 if (table_pg[i] == 0xfe) 155 rtl_addr_delay(table_pg[i]);
155 mdelay(50);
156 else if (table_pg[i] == 0xfd)
157 mdelay(5);
158 else if (table_pg[i] == 0xfc)
159 mdelay(1);
160 else if (table_pg[i] == 0xfb)
161 udelay(50);
162 else if (table_pg[i] == 0xfa)
163 udelay(5);
164 else if (table_pg[i] == 0xf9)
165 udelay(1);
166 156
167 store_pwrindex_offset(hw, table_pg[i], 157 store_pwrindex_offset(hw, table_pg[i],
168 table_pg[i + 1], 158 table_pg[i + 1],
@@ -672,24 +662,9 @@ static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw,
672 u32 addr, u32 data, enum radio_path rfpath, 662 u32 addr, u32 data, enum radio_path rfpath,
673 u32 regaddr) 663 u32 regaddr)
674{ 664{
675 if (addr == 0xffe) { 665 rtl_rfreg_delay(hw, rfpath, regaddr,
676 mdelay(50); 666 RFREG_OFFSET_MASK,
677 } else if (addr == 0xfd) { 667 data);
678 mdelay(5);
679 } else if (addr == 0xfc) {
680 mdelay(1);
681 } else if (addr == 0xfb) {
682 udelay(50);
683 } else if (addr == 0xfa) {
684 udelay(5);
685 } else if (addr == 0xf9) {
686 udelay(1);
687 } else {
688 rtl_set_rfreg(hw, rfpath, regaddr,
689 RFREG_OFFSET_MASK,
690 data);
691 udelay(1);
692 }
693} 668}
694 669
695static void rtl88_config_s(struct ieee80211_hw *hw, 670static void rtl88_config_s(struct ieee80211_hw *hw,
@@ -702,28 +677,6 @@ static void rtl88_config_s(struct ieee80211_hw *hw,
702 addr | maskforphyset); 677 addr | maskforphyset);
703} 678}
704 679
705static void _rtl8188e_config_bb_reg(struct ieee80211_hw *hw,
706 u32 addr, u32 data)
707{
708 if (addr == 0xfe) {
709 mdelay(50);
710 } else if (addr == 0xfd) {
711 mdelay(5);
712 } else if (addr == 0xfc) {
713 mdelay(1);
714 } else if (addr == 0xfb) {
715 udelay(50);
716 } else if (addr == 0xfa) {
717 udelay(5);
718 } else if (addr == 0xf9) {
719 udelay(1);
720 } else {
721 rtl_set_bbreg(hw, addr, MASKDWORD, data);
722 udelay(1);
723 }
724}
725
726
727#define NEXT_PAIR(v1, v2, i) \ 680#define NEXT_PAIR(v1, v2, i) \
728 do { \ 681 do { \
729 i += 2; v1 = array_table[i]; \ 682 i += 2; v1 = array_table[i]; \
@@ -795,7 +748,7 @@ static void set_baseband_phy_config(struct ieee80211_hw *hw)
795 v1 = array_table[i]; 748 v1 = array_table[i];
796 v2 = array_table[i + 1]; 749 v2 = array_table[i + 1];
797 if (v1 < 0xcdcdcdcd) { 750 if (v1 < 0xcdcdcdcd) {
798 _rtl8188e_config_bb_reg(hw, v1, v2); 751 rtl_bb_delay(hw, v1, v2);
799 } else {/*This line is the start line of branch.*/ 752 } else {/*This line is the start line of branch.*/
800 if (!check_cond(hw, array_table[i])) { 753 if (!check_cond(hw, array_table[i])) {
801 /*Discard the following (offset, data) pairs*/ 754 /*Discard the following (offset, data) pairs*/
@@ -811,7 +764,7 @@ static void set_baseband_phy_config(struct ieee80211_hw *hw)
811 while (v2 != 0xDEAD && 764 while (v2 != 0xDEAD &&
812 v2 != 0xCDEF && 765 v2 != 0xCDEF &&
813 v2 != 0xCDCD && i < arraylen - 2) { 766 v2 != 0xCDCD && i < arraylen - 2) {
814 _rtl8188e_config_bb_reg(hw, v1, v2); 767 rtl_bb_delay(hw, v1, v2);
815 NEXT_PAIR(v1, v2, i); 768 NEXT_PAIR(v1, v2, i);
816 } 769 }
817 770
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h
index 028ec6dd52b4..32e135ab9a63 100644
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h
@@ -30,7 +30,6 @@
30#ifndef __RTL8723E_PWRSEQ_H__ 30#ifndef __RTL8723E_PWRSEQ_H__
31#define __RTL8723E_PWRSEQ_H__ 31#define __RTL8723E_PWRSEQ_H__
32 32
33#include "pwrseqcmd.h"
34/* 33/*
35 Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd 34 Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
36 There are 6 HW Power States: 35 There are 6 HW Power States:
diff --git a/drivers/net/wireless/rtlwifi/rtl8188ee/reg.h b/drivers/net/wireless/rtlwifi/rtl8188ee/reg.h
index d849abf7d94a..7af85cfa8f87 100644
--- a/drivers/net/wireless/rtlwifi/rtl8188ee/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8188ee/reg.h
@@ -2215,22 +2215,6 @@
2215#define BWORD1 0xc 2215#define BWORD1 0xc
2216#define BWORD 0xf 2216#define BWORD 0xf
2217 2217
2218#define MASKBYTE0 0xff
2219#define MASKBYTE1 0xff00
2220#define MASKBYTE2 0xff0000
2221#define MASKBYTE3 0xff000000
2222#define MASKHWORD 0xffff0000
2223#define MASKLWORD 0x0000ffff
2224#define MASKDWORD 0xffffffff
2225#define MASK12BITS 0xfff
2226#define MASKH4BITS 0xf0000000
2227#define MASKOFDM_D 0xffc00000
2228#define MASKCCK 0x3f3f3f3f
2229
2230#define MASK4BITS 0x0f
2231#define MASK20BITS 0xfffff
2232#define RFREG_OFFSET_MASK 0xfffff
2233
2234#define BENABLE 0x1 2218#define BENABLE 0x1
2235#define BDISABLE 0x0 2219#define BDISABLE 0x0
2236 2220
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
index 73262ca3864b..98b22303c84d 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
@@ -30,6 +30,7 @@
30#include "../wifi.h" 30#include "../wifi.h"
31#include "../pci.h" 31#include "../pci.h"
32#include "../ps.h" 32#include "../ps.h"
33#include "../core.h"
33#include "reg.h" 34#include "reg.h"
34#include "def.h" 35#include "def.h"
35#include "hw.h" 36#include "hw.h"
@@ -198,18 +199,7 @@ bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
198 } 199 }
199 if (configtype == BASEBAND_CONFIG_PHY_REG) { 200 if (configtype == BASEBAND_CONFIG_PHY_REG) {
200 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 201 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
201 if (phy_regarray_table[i] == 0xfe) 202 rtl_addr_delay(phy_regarray_table[i]);
202 mdelay(50);
203 else if (phy_regarray_table[i] == 0xfd)
204 mdelay(5);
205 else if (phy_regarray_table[i] == 0xfc)
206 mdelay(1);
207 else if (phy_regarray_table[i] == 0xfb)
208 udelay(50);
209 else if (phy_regarray_table[i] == 0xfa)
210 udelay(5);
211 else if (phy_regarray_table[i] == 0xf9)
212 udelay(1);
213 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, 203 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
214 phy_regarray_table[i + 1]); 204 phy_regarray_table[i + 1]);
215 udelay(1); 205 udelay(1);
@@ -245,18 +235,7 @@ bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
245 235
246 if (configtype == BASEBAND_CONFIG_PHY_REG) { 236 if (configtype == BASEBAND_CONFIG_PHY_REG) {
247 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 237 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
248 if (phy_regarray_table_pg[i] == 0xfe) 238 rtl_addr_delay(phy_regarray_table_pg[i]);
249 mdelay(50);
250 else if (phy_regarray_table_pg[i] == 0xfd)
251 mdelay(5);
252 else if (phy_regarray_table_pg[i] == 0xfc)
253 mdelay(1);
254 else if (phy_regarray_table_pg[i] == 0xfb)
255 udelay(50);
256 else if (phy_regarray_table_pg[i] == 0xfa)
257 udelay(5);
258 else if (phy_regarray_table_pg[i] == 0xf9)
259 udelay(1);
260 239
261 _rtl92c_store_pwrIndex_diffrate_offset(hw, 240 _rtl92c_store_pwrIndex_diffrate_offset(hw,
262 phy_regarray_table_pg[i], 241 phy_regarray_table_pg[i],
@@ -305,46 +284,16 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
305 switch (rfpath) { 284 switch (rfpath) {
306 case RF90_PATH_A: 285 case RF90_PATH_A:
307 for (i = 0; i < radioa_arraylen; i = i + 2) { 286 for (i = 0; i < radioa_arraylen; i = i + 2) {
308 if (radioa_array_table[i] == 0xfe) 287 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
309 mdelay(50); 288 RFREG_OFFSET_MASK,
310 else if (radioa_array_table[i] == 0xfd) 289 radioa_array_table[i + 1]);
311 mdelay(5);
312 else if (radioa_array_table[i] == 0xfc)
313 mdelay(1);
314 else if (radioa_array_table[i] == 0xfb)
315 udelay(50);
316 else if (radioa_array_table[i] == 0xfa)
317 udelay(5);
318 else if (radioa_array_table[i] == 0xf9)
319 udelay(1);
320 else {
321 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
322 RFREG_OFFSET_MASK,
323 radioa_array_table[i + 1]);
324 udelay(1);
325 }
326 } 290 }
327 break; 291 break;
328 case RF90_PATH_B: 292 case RF90_PATH_B:
329 for (i = 0; i < radiob_arraylen; i = i + 2) { 293 for (i = 0; i < radiob_arraylen; i = i + 2) {
330 if (radiob_array_table[i] == 0xfe) { 294 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
331 mdelay(50); 295 RFREG_OFFSET_MASK,
332 } else if (radiob_array_table[i] == 0xfd) 296 radiob_array_table[i + 1]);
333 mdelay(5);
334 else if (radiob_array_table[i] == 0xfc)
335 mdelay(1);
336 else if (radiob_array_table[i] == 0xfb)
337 udelay(50);
338 else if (radiob_array_table[i] == 0xfa)
339 udelay(5);
340 else if (radiob_array_table[i] == 0xf9)
341 udelay(1);
342 else {
343 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
344 RFREG_OFFSET_MASK,
345 radiob_array_table[i + 1]);
346 udelay(1);
347 }
348 } 297 }
349 break; 298 break;
350 case RF90_PATH_C: 299 case RF90_PATH_C:
@@ -355,6 +304,8 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
355 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 304 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
356 "switch case not processed\n"); 305 "switch case not processed\n");
357 break; 306 break;
307 default:
308 break;
358 } 309 }
359 return true; 310 return true;
360} 311}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
index 8922ecb47ad2..ed703a1b3b7c 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
@@ -2044,22 +2044,6 @@
2044#define BWORD1 0xc 2044#define BWORD1 0xc
2045#define BWORD 0xf 2045#define BWORD 0xf
2046 2046
2047#define MASKBYTE0 0xff
2048#define MASKBYTE1 0xff00
2049#define MASKBYTE2 0xff0000
2050#define MASKBYTE3 0xff000000
2051#define MASKHWORD 0xffff0000
2052#define MASKLWORD 0x0000ffff
2053#define MASKDWORD 0xffffffff
2054#define MASK12BITS 0xfff
2055#define MASKH4BITS 0xf0000000
2056#define MASKOFDM_D 0xffc00000
2057#define MASKCCK 0x3f3f3f3f
2058
2059#define MASK4BITS 0x0f
2060#define MASK20BITS 0xfffff
2061#define RFREG_OFFSET_MASK 0xfffff
2062
2063#define BENABLE 0x1 2047#define BENABLE 0x1
2064#define BDISABLE 0x0 2048#define BDISABLE 0x0
2065 2049
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
index 0c09240eadcc..9831ff1128ca 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
@@ -30,6 +30,7 @@
30#include "../wifi.h" 30#include "../wifi.h"
31#include "../pci.h" 31#include "../pci.h"
32#include "../ps.h" 32#include "../ps.h"
33#include "../core.h"
33#include "reg.h" 34#include "reg.h"
34#include "def.h" 35#include "def.h"
35#include "phy.h" 36#include "phy.h"
@@ -188,18 +189,7 @@ bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
188 } 189 }
189 if (configtype == BASEBAND_CONFIG_PHY_REG) { 190 if (configtype == BASEBAND_CONFIG_PHY_REG) {
190 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 191 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
191 if (phy_regarray_table[i] == 0xfe) 192 rtl_addr_delay(phy_regarray_table[i]);
192 mdelay(50);
193 else if (phy_regarray_table[i] == 0xfd)
194 mdelay(5);
195 else if (phy_regarray_table[i] == 0xfc)
196 mdelay(1);
197 else if (phy_regarray_table[i] == 0xfb)
198 udelay(50);
199 else if (phy_regarray_table[i] == 0xfa)
200 udelay(5);
201 else if (phy_regarray_table[i] == 0xf9)
202 udelay(1);
203 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, 193 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
204 phy_regarray_table[i + 1]); 194 phy_regarray_table[i + 1]);
205 udelay(1); 195 udelay(1);
@@ -236,18 +226,7 @@ bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
236 phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata; 226 phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata;
237 if (configtype == BASEBAND_CONFIG_PHY_REG) { 227 if (configtype == BASEBAND_CONFIG_PHY_REG) {
238 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 228 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
239 if (phy_regarray_table_pg[i] == 0xfe) 229 rtl_addr_delay(phy_regarray_table_pg[i]);
240 mdelay(50);
241 else if (phy_regarray_table_pg[i] == 0xfd)
242 mdelay(5);
243 else if (phy_regarray_table_pg[i] == 0xfc)
244 mdelay(1);
245 else if (phy_regarray_table_pg[i] == 0xfb)
246 udelay(50);
247 else if (phy_regarray_table_pg[i] == 0xfa)
248 udelay(5);
249 else if (phy_regarray_table_pg[i] == 0xf9)
250 udelay(1);
251 _rtl92c_store_pwrIndex_diffrate_offset(hw, 230 _rtl92c_store_pwrIndex_diffrate_offset(hw,
252 phy_regarray_table_pg[i], 231 phy_regarray_table_pg[i],
253 phy_regarray_table_pg[i + 1], 232 phy_regarray_table_pg[i + 1],
@@ -294,46 +273,16 @@ bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
294 switch (rfpath) { 273 switch (rfpath) {
295 case RF90_PATH_A: 274 case RF90_PATH_A:
296 for (i = 0; i < radioa_arraylen; i = i + 2) { 275 for (i = 0; i < radioa_arraylen; i = i + 2) {
297 if (radioa_array_table[i] == 0xfe) 276 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
298 mdelay(50); 277 RFREG_OFFSET_MASK,
299 else if (radioa_array_table[i] == 0xfd) 278 radioa_array_table[i + 1]);
300 mdelay(5);
301 else if (radioa_array_table[i] == 0xfc)
302 mdelay(1);
303 else if (radioa_array_table[i] == 0xfb)
304 udelay(50);
305 else if (radioa_array_table[i] == 0xfa)
306 udelay(5);
307 else if (radioa_array_table[i] == 0xf9)
308 udelay(1);
309 else {
310 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
311 RFREG_OFFSET_MASK,
312 radioa_array_table[i + 1]);
313 udelay(1);
314 }
315 } 279 }
316 break; 280 break;
317 case RF90_PATH_B: 281 case RF90_PATH_B:
318 for (i = 0; i < radiob_arraylen; i = i + 2) { 282 for (i = 0; i < radiob_arraylen; i = i + 2) {
319 if (radiob_array_table[i] == 0xfe) { 283 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
320 mdelay(50); 284 RFREG_OFFSET_MASK,
321 } else if (radiob_array_table[i] == 0xfd) 285 radiob_array_table[i + 1]);
322 mdelay(5);
323 else if (radiob_array_table[i] == 0xfc)
324 mdelay(1);
325 else if (radiob_array_table[i] == 0xfb)
326 udelay(50);
327 else if (radiob_array_table[i] == 0xfa)
328 udelay(5);
329 else if (radiob_array_table[i] == 0xf9)
330 udelay(1);
331 else {
332 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
333 RFREG_OFFSET_MASK,
334 radiob_array_table[i + 1]);
335 udelay(1);
336 }
337 } 286 }
338 break; 287 break;
339 case RF90_PATH_C: 288 case RF90_PATH_C:
@@ -344,6 +293,8 @@ bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
344 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 293 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
345 "switch case not processed\n"); 294 "switch case not processed\n");
346 break; 295 break;
296 default:
297 break;
347 } 298 }
348 return true; 299 return true;
349} 300}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/dm.c b/drivers/net/wireless/rtlwifi/rtl8192de/dm.c
index 7908e1c85819..304c443b89b2 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/dm.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/dm.c
@@ -194,15 +194,15 @@ static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
194 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */ 194 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */
195 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */ 195 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */
196 196
197 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, BMASKDWORD); 197 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD);
198 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); 198 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
199 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); 199 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
200 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, BMASKDWORD); 200 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
201 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); 201 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
202 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, BMASKDWORD); 202 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
203 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); 203 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
204 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); 204 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
205 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, BMASKDWORD); 205 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
206 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); 206 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
207 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + 207 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
208 falsealm_cnt->cnt_rate_illegal + 208 falsealm_cnt->cnt_rate_illegal +
@@ -214,9 +214,9 @@ static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
214 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { 214 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
215 /* hold cck counter */ 215 /* hold cck counter */
216 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 216 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
217 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, BMASKBYTE0); 217 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
218 falsealm_cnt->cnt_cck_fail = ret_value; 218 falsealm_cnt->cnt_cck_fail = ret_value;
219 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, BMASKBYTE3); 219 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
220 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; 220 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
221 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 221 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
222 } else { 222 } else {
@@ -331,11 +331,11 @@ static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
331 if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) { 331 if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) {
332 if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { 332 if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
333 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 333 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
334 rtl_set_bbreg(hw, RCCK0_CCA, BMASKBYTE2, 0x83); 334 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83);
335 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 335 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
336 } else { 336 } else {
337 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 337 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
338 rtl_set_bbreg(hw, RCCK0_CCA, BMASKBYTE2, 0xcd); 338 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
339 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 339 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
340 } 340 }
341 de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state; 341 de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state;
@@ -722,7 +722,7 @@ static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw)
722 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 722 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
723 "===> Rx Gain %x\n", u4tmp); 723 "===> Rx Gain %x\n", u4tmp);
724 for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++) 724 for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++)
725 rtl_set_rfreg(hw, i, 0x3C, BRFREGOFFSETMASK, 725 rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK,
726 (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp); 726 (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp);
727} 727}
728 728
@@ -737,7 +737,7 @@ static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg,
737 /* Query CCK default setting From 0xa24 */ 737 /* Query CCK default setting From 0xa24 */
738 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 738 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
739 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, 739 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2,
740 BMASKDWORD) & BMASKCCK; 740 MASKDWORD) & MASKCCK;
741 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 741 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
742 for (i = 0; i < CCK_TABLE_LENGTH; i++) { 742 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
743 if (rtlpriv->dm.cck_inch14) { 743 if (rtlpriv->dm.cck_inch14) {
@@ -896,9 +896,9 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
896 rf = 1; 896 rf = 1;
897 if (thermalvalue) { 897 if (thermalvalue) {
898 ele_d = rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 898 ele_d = rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
899 BMASKDWORD) & BMASKOFDM_D; 899 MASKDWORD) & MASKOFDM_D;
900 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { 900 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
901 if (ele_d == (ofdmswing_table[i] & BMASKOFDM_D)) { 901 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
902 ofdm_index_old[0] = (u8) i; 902 ofdm_index_old[0] = (u8) i;
903 903
904 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 904 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
@@ -910,10 +910,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
910 } 910 }
911 if (is2t) { 911 if (is2t) {
912 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 912 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
913 BMASKDWORD) & BMASKOFDM_D; 913 MASKDWORD) & MASKOFDM_D;
914 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { 914 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
915 if (ele_d == 915 if (ele_d ==
916 (ofdmswing_table[i] & BMASKOFDM_D)) { 916 (ofdmswing_table[i] & MASKOFDM_D)) {
917 ofdm_index_old[1] = (u8) i; 917 ofdm_index_old[1] = (u8) i;
918 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, 918 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
919 DBG_LOUD, 919 DBG_LOUD,
@@ -1091,10 +1091,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
1091 value32 = (ele_d << 22) | ((ele_c & 0x3F) << 1091 value32 = (ele_d << 22) | ((ele_c & 0x3F) <<
1092 16) | ele_a; 1092 16) | ele_a;
1093 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 1093 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
1094 BMASKDWORD, value32); 1094 MASKDWORD, value32);
1095 1095
1096 value32 = (ele_c & 0x000003C0) >> 6; 1096 value32 = (ele_c & 0x000003C0) >> 6;
1097 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, BMASKH4BITS, 1097 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, MASKH4BITS,
1098 value32); 1098 value32);
1099 1099
1100 value32 = ((val_x * ele_d) >> 7) & 0x01; 1100 value32 = ((val_x * ele_d) >> 7) & 0x01;
@@ -1103,10 +1103,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
1103 1103
1104 } else { 1104 } else {
1105 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 1105 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
1106 BMASKDWORD, 1106 MASKDWORD,
1107 ofdmswing_table 1107 ofdmswing_table
1108 [(u8)ofdm_index[0]]); 1108 [(u8)ofdm_index[0]]);
1109 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, BMASKH4BITS, 1109 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, MASKH4BITS,
1110 0x00); 1110 0x00);
1111 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1111 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1112 BIT(24), 0x00); 1112 BIT(24), 0x00);
@@ -1204,21 +1204,21 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
1204 ele_a; 1204 ele_a;
1205 rtl_set_bbreg(hw, 1205 rtl_set_bbreg(hw,
1206 ROFDM0_XBTxIQIMBALANCE, 1206 ROFDM0_XBTxIQIMBALANCE,
1207 BMASKDWORD, value32); 1207 MASKDWORD, value32);
1208 value32 = (ele_c & 0x000003C0) >> 6; 1208 value32 = (ele_c & 0x000003C0) >> 6;
1209 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 1209 rtl_set_bbreg(hw, ROFDM0_XDTxAFE,
1210 BMASKH4BITS, value32); 1210 MASKH4BITS, value32);
1211 value32 = ((val_x * ele_d) >> 7) & 0x01; 1211 value32 = ((val_x * ele_d) >> 7) & 0x01;
1212 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1212 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1213 BIT(28), value32); 1213 BIT(28), value32);
1214 } else { 1214 } else {
1215 rtl_set_bbreg(hw, 1215 rtl_set_bbreg(hw,
1216 ROFDM0_XBTxIQIMBALANCE, 1216 ROFDM0_XBTxIQIMBALANCE,
1217 BMASKDWORD, 1217 MASKDWORD,
1218 ofdmswing_table 1218 ofdmswing_table
1219 [(u8) ofdm_index[1]]); 1219 [(u8) ofdm_index[1]]);
1220 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 1220 rtl_set_bbreg(hw, ROFDM0_XDTxAFE,
1221 BMASKH4BITS, 0x00); 1221 MASKH4BITS, 0x00);
1222 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 1222 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1223 BIT(28), 0x00); 1223 BIT(28), 0x00);
1224 } 1224 }
@@ -1229,10 +1229,10 @@ static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
1229 } 1229 }
1230 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1230 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1231 "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", 1231 "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n",
1232 rtl_get_bbreg(hw, 0xc80, BMASKDWORD), 1232 rtl_get_bbreg(hw, 0xc80, MASKDWORD),
1233 rtl_get_bbreg(hw, 0xc94, BMASKDWORD), 1233 rtl_get_bbreg(hw, 0xc94, MASKDWORD),
1234 rtl_get_rfreg(hw, RF90_PATH_A, 0x24, 1234 rtl_get_rfreg(hw, RF90_PATH_A, 0x24,
1235 BRFREGOFFSETMASK)); 1235 RFREG_OFFSET_MASK));
1236 } 1236 }
1237 if ((delta_iqk > rtlefuse->delta_iqk) && 1237 if ((delta_iqk > rtlefuse->delta_iqk) &&
1238 (rtlefuse->delta_iqk != 0)) { 1238 (rtlefuse->delta_iqk != 0)) {
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/rtlwifi/rtl8192de/hw.c
index c9f6ee7e1765..2b08671004a0 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/hw.c
@@ -985,9 +985,9 @@ int rtl92de_hw_init(struct ieee80211_hw *hw)
985 /* set default value after initialize RF, */ 985 /* set default value after initialize RF, */
986 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); 986 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
987 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 987 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
988 RF_CHNLBW, BRFREGOFFSETMASK); 988 RF_CHNLBW, RFREG_OFFSET_MASK);
989 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 989 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
990 RF_CHNLBW, BRFREGOFFSETMASK); 990 RF_CHNLBW, RFREG_OFFSET_MASK);
991 991
992 /*---- Set CCK and OFDM Block "ON"----*/ 992 /*---- Set CCK and OFDM Block "ON"----*/
993 if (rtlhal->current_bandtype == BAND_ON_2_4G) 993 if (rtlhal->current_bandtype == BAND_ON_2_4G)
@@ -1035,7 +1035,7 @@ int rtl92de_hw_init(struct ieee80211_hw *hw)
1035 1035
1036 tmp_rega = rtl_get_rfreg(hw, 1036 tmp_rega = rtl_get_rfreg(hw,
1037 (enum radio_path)RF90_PATH_A, 1037 (enum radio_path)RF90_PATH_A,
1038 0x2a, BMASKDWORD); 1038 0x2a, MASKDWORD);
1039 1039
1040 if (((tmp_rega & BIT(11)) == BIT(11))) 1040 if (((tmp_rega & BIT(11)) == BIT(11)))
1041 break; 1041 break;
@@ -1334,13 +1334,13 @@ void rtl92de_card_disable(struct ieee80211_hw *hw)
1334 /* c. ========RF OFF sequence========== */ 1334 /* c. ========RF OFF sequence========== */
1335 /* 0x88c[23:20] = 0xf. */ 1335 /* 0x88c[23:20] = 0xf. */
1336 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); 1336 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1337 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00); 1337 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1338 1338
1339 /* APSD_CTRL 0x600[7:0] = 0x40 */ 1339 /* APSD_CTRL 0x600[7:0] = 0x40 */
1340 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 1340 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1341 1341
1342 /* Close antenna 0,0xc04,0xd04 */ 1342 /* Close antenna 0,0xc04,0xd04 */
1343 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0); 1343 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0);
1344 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0); 1344 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1345 1345
1346 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */ 1346 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
index 13196cc4b1d3..3d1f0dd4e52d 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
@@ -30,6 +30,7 @@
30#include "../wifi.h" 30#include "../wifi.h"
31#include "../pci.h" 31#include "../pci.h"
32#include "../ps.h" 32#include "../ps.h"
33#include "../core.h"
33#include "reg.h" 34#include "reg.h"
34#include "def.h" 35#include "def.h"
35#include "phy.h" 36#include "phy.h"
@@ -242,7 +243,7 @@ void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
242 else if (rtlhal->during_mac0init_radiob) 243 else if (rtlhal->during_mac0init_radiob)
243 /* mac0 use phy1 write radio_b. */ 244 /* mac0 use phy1 write radio_b. */
244 dbi_direct = BIT(3) | BIT(2); 245 dbi_direct = BIT(3) | BIT(2);
245 if (bitmask != BMASKDWORD) { 246 if (bitmask != MASKDWORD) {
246 if (rtlhal->during_mac1init_radioa || 247 if (rtlhal->during_mac1init_radioa ||
247 rtlhal->during_mac0init_radiob) 248 rtlhal->during_mac0init_radiob)
248 originalvalue = rtl92de_read_dword_dbi(hw, 249 originalvalue = rtl92de_read_dword_dbi(hw,
@@ -275,20 +276,20 @@ static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
275 u32 retvalue; 276 u32 retvalue;
276 277
277 newoffset = offset; 278 newoffset = offset;
278 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD); 279 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
279 if (rfpath == RF90_PATH_A) 280 if (rfpath == RF90_PATH_A)
280 tmplong2 = tmplong; 281 tmplong2 = tmplong;
281 else 282 else
282 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD); 283 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
283 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | 284 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
284 (newoffset << 23) | BLSSIREADEDGE; 285 (newoffset << 23) | BLSSIREADEDGE;
285 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD, 286 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
286 tmplong & (~BLSSIREADEDGE)); 287 tmplong & (~BLSSIREADEDGE));
287 udelay(10); 288 udelay(10);
288 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD, tmplong2); 289 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
289 udelay(50); 290 udelay(50);
290 udelay(50); 291 udelay(50);
291 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD, 292 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
292 tmplong | BLSSIREADEDGE); 293 tmplong | BLSSIREADEDGE);
293 udelay(10); 294 udelay(10);
294 if (rfpath == RF90_PATH_A) 295 if (rfpath == RF90_PATH_A)
@@ -321,7 +322,7 @@ static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
321 newoffset = offset; 322 newoffset = offset;
322 /* T65 RF */ 323 /* T65 RF */
323 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 324 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
324 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, BMASKDWORD, data_and_addr); 325 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
325 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", 326 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
326 rfpath, pphyreg->rf3wire_offset, data_and_addr); 327 rfpath, pphyreg->rf3wire_offset, data_and_addr);
327} 328}
@@ -362,7 +363,7 @@ void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
362 return; 363 return;
363 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 364 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
364 if (rtlphy->rf_mode != RF_OP_BY_FW) { 365 if (rtlphy->rf_mode != RF_OP_BY_FW) {
365 if (bitmask != BRFREGOFFSETMASK) { 366 if (bitmask != RFREG_OFFSET_MASK) {
366 original_value = _rtl92d_phy_rf_serial_read(hw, 367 original_value = _rtl92d_phy_rf_serial_read(hw,
367 rfpath, regaddr); 368 rfpath, regaddr);
368 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 369 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
@@ -567,19 +568,8 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
567 " ===> phy:Rtl819XPHY_REG_Array_PG\n"); 568 " ===> phy:Rtl819XPHY_REG_Array_PG\n");
568 if (configtype == BASEBAND_CONFIG_PHY_REG) { 569 if (configtype == BASEBAND_CONFIG_PHY_REG) {
569 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 570 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
570 if (phy_regarray_table[i] == 0xfe) 571 rtl_addr_delay(phy_regarray_table[i]);
571 mdelay(50); 572 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
572 else if (phy_regarray_table[i] == 0xfd)
573 mdelay(5);
574 else if (phy_regarray_table[i] == 0xfc)
575 mdelay(1);
576 else if (phy_regarray_table[i] == 0xfb)
577 udelay(50);
578 else if (phy_regarray_table[i] == 0xfa)
579 udelay(5);
580 else if (phy_regarray_table[i] == 0xf9)
581 udelay(1);
582 rtl_set_bbreg(hw, phy_regarray_table[i], BMASKDWORD,
583 phy_regarray_table[i + 1]); 573 phy_regarray_table[i + 1]);
584 udelay(1); 574 udelay(1);
585 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 575 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
@@ -591,7 +581,7 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
591 if (rtlhal->interfaceindex == 0) { 581 if (rtlhal->interfaceindex == 0) {
592 for (i = 0; i < agctab_arraylen; i = i + 2) { 582 for (i = 0; i < agctab_arraylen; i = i + 2) {
593 rtl_set_bbreg(hw, agctab_array_table[i], 583 rtl_set_bbreg(hw, agctab_array_table[i],
594 BMASKDWORD, 584 MASKDWORD,
595 agctab_array_table[i + 1]); 585 agctab_array_table[i + 1]);
596 /* Add 1us delay between BB/RF register 586 /* Add 1us delay between BB/RF register
597 * setting. */ 587 * setting. */
@@ -607,7 +597,7 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
607 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 597 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
608 for (i = 0; i < agctab_arraylen; i = i + 2) { 598 for (i = 0; i < agctab_arraylen; i = i + 2) {
609 rtl_set_bbreg(hw, agctab_array_table[i], 599 rtl_set_bbreg(hw, agctab_array_table[i],
610 BMASKDWORD, 600 MASKDWORD,
611 agctab_array_table[i + 1]); 601 agctab_array_table[i + 1]);
612 /* Add 1us delay between BB/RF register 602 /* Add 1us delay between BB/RF register
613 * setting. */ 603 * setting. */
@@ -623,7 +613,7 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
623 for (i = 0; i < agctab_5garraylen; i = i + 2) { 613 for (i = 0; i < agctab_5garraylen; i = i + 2) {
624 rtl_set_bbreg(hw, 614 rtl_set_bbreg(hw,
625 agctab_5garray_table[i], 615 agctab_5garray_table[i],
626 BMASKDWORD, 616 MASKDWORD,
627 agctab_5garray_table[i + 1]); 617 agctab_5garray_table[i + 1]);
628 /* Add 1us delay between BB/RF registeri 618 /* Add 1us delay between BB/RF registeri
629 * setting. */ 619 * setting. */
@@ -705,18 +695,7 @@ static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
705 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg; 695 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
706 if (configtype == BASEBAND_CONFIG_PHY_REG) { 696 if (configtype == BASEBAND_CONFIG_PHY_REG) {
707 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 697 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
708 if (phy_regarray_table_pg[i] == 0xfe) 698 rtl_addr_delay(phy_regarray_table_pg[i]);
709 mdelay(50);
710 else if (phy_regarray_table_pg[i] == 0xfd)
711 mdelay(5);
712 else if (phy_regarray_table_pg[i] == 0xfc)
713 mdelay(1);
714 else if (phy_regarray_table_pg[i] == 0xfb)
715 udelay(50);
716 else if (phy_regarray_table_pg[i] == 0xfa)
717 udelay(5);
718 else if (phy_regarray_table_pg[i] == 0xf9)
719 udelay(1);
720 _rtl92d_store_pwrindex_diffrate_offset(hw, 699 _rtl92d_store_pwrindex_diffrate_offset(hw,
721 phy_regarray_table_pg[i], 700 phy_regarray_table_pg[i],
722 phy_regarray_table_pg[i + 1], 701 phy_regarray_table_pg[i + 1],
@@ -843,54 +822,16 @@ bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
843 switch (rfpath) { 822 switch (rfpath) {
844 case RF90_PATH_A: 823 case RF90_PATH_A:
845 for (i = 0; i < radioa_arraylen; i = i + 2) { 824 for (i = 0; i < radioa_arraylen; i = i + 2) {
846 if (radioa_array_table[i] == 0xfe) { 825 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
847 mdelay(50); 826 RFREG_OFFSET_MASK,
848 } else if (radioa_array_table[i] == 0xfd) { 827 radioa_array_table[i + 1]);
849 /* delay_ms(5); */
850 mdelay(5);
851 } else if (radioa_array_table[i] == 0xfc) {
852 /* delay_ms(1); */
853 mdelay(1);
854 } else if (radioa_array_table[i] == 0xfb) {
855 udelay(50);
856 } else if (radioa_array_table[i] == 0xfa) {
857 udelay(5);
858 } else if (radioa_array_table[i] == 0xf9) {
859 udelay(1);
860 } else {
861 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
862 BRFREGOFFSETMASK,
863 radioa_array_table[i + 1]);
864 /* Add 1us delay between BB/RF register set. */
865 udelay(1);
866 }
867 } 828 }
868 break; 829 break;
869 case RF90_PATH_B: 830 case RF90_PATH_B:
870 for (i = 0; i < radiob_arraylen; i = i + 2) { 831 for (i = 0; i < radiob_arraylen; i = i + 2) {
871 if (radiob_array_table[i] == 0xfe) { 832 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
872 /* Delay specific ms. Only RF configuration 833 RFREG_OFFSET_MASK,
873 * requires delay. */ 834 radiob_array_table[i + 1]);
874 mdelay(50);
875 } else if (radiob_array_table[i] == 0xfd) {
876 /* delay_ms(5); */
877 mdelay(5);
878 } else if (radiob_array_table[i] == 0xfc) {
879 /* delay_ms(1); */
880 mdelay(1);
881 } else if (radiob_array_table[i] == 0xfb) {
882 udelay(50);
883 } else if (radiob_array_table[i] == 0xfa) {
884 udelay(5);
885 } else if (radiob_array_table[i] == 0xf9) {
886 udelay(1);
887 } else {
888 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
889 BRFREGOFFSETMASK,
890 radiob_array_table[i + 1]);
891 /* Add 1us delay between BB/RF register set. */
892 udelay(1);
893 }
894 } 835 }
895 break; 836 break;
896 case RF90_PATH_C: 837 case RF90_PATH_C:
@@ -911,13 +852,13 @@ void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
911 struct rtl_phy *rtlphy = &(rtlpriv->phy); 852 struct rtl_phy *rtlphy = &(rtlpriv->phy);
912 853
913 rtlphy->default_initialgain[0] = 854 rtlphy->default_initialgain[0] =
914 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, BMASKBYTE0); 855 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
915 rtlphy->default_initialgain[1] = 856 rtlphy->default_initialgain[1] =
916 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, BMASKBYTE0); 857 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
917 rtlphy->default_initialgain[2] = 858 rtlphy->default_initialgain[2] =
918 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, BMASKBYTE0); 859 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
919 rtlphy->default_initialgain[3] = 860 rtlphy->default_initialgain[3] =
920 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, BMASKBYTE0); 861 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
921 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 862 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
922 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 863 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
923 rtlphy->default_initialgain[0], 864 rtlphy->default_initialgain[0],
@@ -925,9 +866,9 @@ void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
925 rtlphy->default_initialgain[2], 866 rtlphy->default_initialgain[2],
926 rtlphy->default_initialgain[3]); 867 rtlphy->default_initialgain[3]);
927 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, 868 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
928 BMASKBYTE0); 869 MASKBYTE0);
929 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 870 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
930 BMASKDWORD); 871 MASKDWORD);
931 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 872 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
932 "Default framesync (0x%x) = 0x%x\n", 873 "Default framesync (0x%x) = 0x%x\n",
933 ROFDM0_RXDETECTOR3, rtlphy->framesync); 874 ROFDM0_RXDETECTOR3, rtlphy->framesync);
@@ -1106,7 +1047,7 @@ static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1106{ 1047{
1107 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); 1048 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1108 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); 1049 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1109 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x00); 1050 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
1110 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); 1051 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1111} 1052}
1112 1053
@@ -1168,7 +1109,7 @@ static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1168{ 1109{
1169 struct rtl_priv *rtlpriv = rtl_priv(hw); 1110 struct rtl_priv *rtlpriv = rtl_priv(hw);
1170 u32 imr_num = MAX_RF_IMR_INDEX; 1111 u32 imr_num = MAX_RF_IMR_INDEX;
1171 u32 rfmask = BRFREGOFFSETMASK; 1112 u32 rfmask = RFREG_OFFSET_MASK;
1172 u8 group, i; 1113 u8 group, i;
1173 unsigned long flag = 0; 1114 unsigned long flag = 0;
1174 1115
@@ -1211,7 +1152,7 @@ static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1211 for (i = 0; i < imr_num; i++) { 1152 for (i = 0; i < imr_num; i++) {
1212 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1153 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1213 rf_reg_for_5g_swchnl_normal[i], 1154 rf_reg_for_5g_swchnl_normal[i],
1214 BRFREGOFFSETMASK, 1155 RFREG_OFFSET_MASK,
1215 rf_imr_param_normal[0][0][i]); 1156 rf_imr_param_normal[0][0][i]);
1216 } 1157 }
1217 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 1158 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
@@ -1329,7 +1270,7 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1329 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { 1270 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1330 rtl_set_rfreg(hw, (enum radio_path)path, 1271 rtl_set_rfreg(hw, (enum radio_path)path,
1331 rf_reg_for_c_cut_5g[i], 1272 rf_reg_for_c_cut_5g[i],
1332 BRFREGOFFSETMASK, 0xE439D); 1273 RFREG_OFFSET_MASK, 0xE439D);
1333 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) { 1274 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1334 u4tmp2 = (rf_reg_pram_c_5g[index][i] & 1275 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1335 0x7FF) | (u4tmp << 11); 1276 0x7FF) | (u4tmp << 11);
@@ -1337,11 +1278,11 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1337 u4tmp2 &= ~(BIT(7) | BIT(6)); 1278 u4tmp2 &= ~(BIT(7) | BIT(6));
1338 rtl_set_rfreg(hw, (enum radio_path)path, 1279 rtl_set_rfreg(hw, (enum radio_path)path,
1339 rf_reg_for_c_cut_5g[i], 1280 rf_reg_for_c_cut_5g[i],
1340 BRFREGOFFSETMASK, u4tmp2); 1281 RFREG_OFFSET_MASK, u4tmp2);
1341 } else { 1282 } else {
1342 rtl_set_rfreg(hw, (enum radio_path)path, 1283 rtl_set_rfreg(hw, (enum radio_path)path,
1343 rf_reg_for_c_cut_5g[i], 1284 rf_reg_for_c_cut_5g[i],
1344 BRFREGOFFSETMASK, 1285 RFREG_OFFSET_MASK,
1345 rf_reg_pram_c_5g[index][i]); 1286 rf_reg_pram_c_5g[index][i]);
1346 } 1287 }
1347 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 1288 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
@@ -1351,7 +1292,7 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1351 path, index, 1292 path, index,
1352 rtl_get_rfreg(hw, (enum radio_path)path, 1293 rtl_get_rfreg(hw, (enum radio_path)path,
1353 rf_reg_for_c_cut_5g[i], 1294 rf_reg_for_c_cut_5g[i],
1354 BRFREGOFFSETMASK)); 1295 RFREG_OFFSET_MASK));
1355 } 1296 }
1356 if (need_pwr_down) 1297 if (need_pwr_down)
1357 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 1298 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
@@ -1381,7 +1322,7 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1381 i++) { 1322 i++) {
1382 rtl_set_rfreg(hw, rfpath, 1323 rtl_set_rfreg(hw, rfpath,
1383 rf_for_c_cut_5g_internal_pa[i], 1324 rf_for_c_cut_5g_internal_pa[i],
1384 BRFREGOFFSETMASK, 1325 RFREG_OFFSET_MASK,
1385 rf_pram_c_5g_int_pa[index][i]); 1326 rf_pram_c_5g_int_pa[index][i]);
1386 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, 1327 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1387 "offset 0x%x value 0x%x path %d index %d\n", 1328 "offset 0x%x value 0x%x path %d index %d\n",
@@ -1422,13 +1363,13 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1422 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7) 1363 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1423 rtl_set_rfreg(hw, (enum radio_path)path, 1364 rtl_set_rfreg(hw, (enum radio_path)path,
1424 rf_reg_for_c_cut_2g[i], 1365 rf_reg_for_c_cut_2g[i],
1425 BRFREGOFFSETMASK, 1366 RFREG_OFFSET_MASK,
1426 (rf_reg_param_for_c_cut_2g[index][i] | 1367 (rf_reg_param_for_c_cut_2g[index][i] |
1427 BIT(17))); 1368 BIT(17)));
1428 else 1369 else
1429 rtl_set_rfreg(hw, (enum radio_path)path, 1370 rtl_set_rfreg(hw, (enum radio_path)path,
1430 rf_reg_for_c_cut_2g[i], 1371 rf_reg_for_c_cut_2g[i],
1431 BRFREGOFFSETMASK, 1372 RFREG_OFFSET_MASK,
1432 rf_reg_param_for_c_cut_2g 1373 rf_reg_param_for_c_cut_2g
1433 [index][i]); 1374 [index][i]);
1434 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 1375 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
@@ -1438,14 +1379,14 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1438 rf_reg_mask_for_c_cut_2g[i], path, index, 1379 rf_reg_mask_for_c_cut_2g[i], path, index,
1439 rtl_get_rfreg(hw, (enum radio_path)path, 1380 rtl_get_rfreg(hw, (enum radio_path)path,
1440 rf_reg_for_c_cut_2g[i], 1381 rf_reg_for_c_cut_2g[i],
1441 BRFREGOFFSETMASK)); 1382 RFREG_OFFSET_MASK));
1442 } 1383 }
1443 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1384 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1444 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 1385 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1445 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 1386 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1446 1387
1447 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, 1388 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1448 BRFREGOFFSETMASK, 1389 RFREG_OFFSET_MASK,
1449 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 1390 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1450 if (need_pwr_down) 1391 if (need_pwr_down)
1451 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 1392 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
@@ -1493,41 +1434,41 @@ static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1493 /* path-A IQK setting */ 1434 /* path-A IQK setting */
1494 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1435 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1495 if (rtlhal->interfaceindex == 0) { 1436 if (rtlhal->interfaceindex == 0) {
1496 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c1f); 1437 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1497 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c1f); 1438 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1498 } else { 1439 } else {
1499 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c22); 1440 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22);
1500 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c22); 1441 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22);
1501 } 1442 }
1502 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140102); 1443 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1503 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x28160206); 1444 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206);
1504 /* path-B IQK setting */ 1445 /* path-B IQK setting */
1505 if (configpathb) { 1446 if (configpathb) {
1506 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x10008c22); 1447 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1507 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x10008c22); 1448 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1508 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140102); 1449 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1509 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x28160206); 1450 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206);
1510 } 1451 }
1511 /* LO calibration setting */ 1452 /* LO calibration setting */
1512 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1453 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1513 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911); 1454 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1514 /* One shot, path A LOK & IQK */ 1455 /* One shot, path A LOK & IQK */
1515 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 1456 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1516 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000); 1457 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1517 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000); 1458 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1518 /* delay x ms */ 1459 /* delay x ms */
1519 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1460 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1520 "Delay %d ms for One shot, path A LOK & IQK\n", 1461 "Delay %d ms for One shot, path A LOK & IQK\n",
1521 IQK_DELAY_TIME); 1462 IQK_DELAY_TIME);
1522 mdelay(IQK_DELAY_TIME); 1463 mdelay(IQK_DELAY_TIME);
1523 /* Check failed */ 1464 /* Check failed */
1524 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1465 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1525 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1466 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1526 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD); 1467 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1527 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1468 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1528 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD); 1469 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1529 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1470 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1530 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD); 1471 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1531 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1472 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1532 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && 1473 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1533 (((rege9c & 0x03FF0000) >> 16) != 0x42)) 1474 (((rege9c & 0x03FF0000) >> 16) != 0x42))
@@ -1563,42 +1504,42 @@ static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1563 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); 1504 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1564 /* path-A IQK setting */ 1505 /* path-A IQK setting */
1565 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1506 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1566 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f); 1507 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1567 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f); 1508 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1568 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140307); 1509 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1569 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68160960); 1510 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);
1570 /* path-B IQK setting */ 1511 /* path-B IQK setting */
1571 if (configpathb) { 1512 if (configpathb) {
1572 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f); 1513 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1573 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f); 1514 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1574 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82110000); 1515 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000);
1575 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68110000); 1516 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000);
1576 } 1517 }
1577 /* LO calibration setting */ 1518 /* LO calibration setting */
1578 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1519 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1579 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911); 1520 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1580 /* path-A PA on */ 1521 /* path-A PA on */
1581 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x07000f60); 1522 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1582 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD, 0x66e60e30); 1523 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1583 for (i = 0; i < retrycount; i++) { 1524 for (i = 0; i < retrycount; i++) {
1584 /* One shot, path A LOK & IQK */ 1525 /* One shot, path A LOK & IQK */
1585 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1526 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1586 "One shot, path A LOK & IQK!\n"); 1527 "One shot, path A LOK & IQK!\n");
1587 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000); 1528 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1588 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000); 1529 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1589 /* delay x ms */ 1530 /* delay x ms */
1590 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1531 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1591 "Delay %d ms for One shot, path A LOK & IQK.\n", 1532 "Delay %d ms for One shot, path A LOK & IQK.\n",
1592 IQK_DELAY_TIME); 1533 IQK_DELAY_TIME);
1593 mdelay(IQK_DELAY_TIME * 10); 1534 mdelay(IQK_DELAY_TIME * 10);
1594 /* Check failed */ 1535 /* Check failed */
1595 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1536 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1596 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1537 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1597 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD); 1538 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1598 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1539 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1599 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD); 1540 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1600 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1541 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1601 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD); 1542 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1602 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1543 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1603 if (!(regeac & TxOKBit) && 1544 if (!(regeac & TxOKBit) &&
1604 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { 1545 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
@@ -1620,9 +1561,9 @@ static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1620 } 1561 }
1621 } 1562 }
1622 /* path A PA off */ 1563 /* path A PA off */
1623 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 1564 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1624 rtlphy->iqk_bb_backup[0]); 1565 rtlphy->iqk_bb_backup[0]);
1625 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD, 1566 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
1626 rtlphy->iqk_bb_backup[1]); 1567 rtlphy->iqk_bb_backup[1]);
1627 return result; 1568 return result;
1628} 1569}
@@ -1637,22 +1578,22 @@ static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1637 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1578 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1638 /* One shot, path B LOK & IQK */ 1579 /* One shot, path B LOK & IQK */
1639 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 1580 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1640 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000002); 1581 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1641 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000000); 1582 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1642 /* delay x ms */ 1583 /* delay x ms */
1643 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1584 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1644 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME); 1585 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1645 mdelay(IQK_DELAY_TIME); 1586 mdelay(IQK_DELAY_TIME);
1646 /* Check failed */ 1587 /* Check failed */
1647 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1588 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1648 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1589 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1649 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD); 1590 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1650 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1591 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1651 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD); 1592 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1652 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1593 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1653 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD); 1594 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1654 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1595 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1655 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD); 1596 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1656 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1597 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1657 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && 1598 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1658 (((regebc & 0x03FF0000) >> 16) != 0x42)) 1599 (((regebc & 0x03FF0000) >> 16) != 0x42))
@@ -1680,31 +1621,31 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1680 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1621 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1681 /* path-A IQK setting */ 1622 /* path-A IQK setting */
1682 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1623 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1683 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f); 1624 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1684 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f); 1625 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1685 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82110000); 1626 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000);
1686 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68110000); 1627 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000);
1687 1628
1688 /* path-B IQK setting */ 1629 /* path-B IQK setting */
1689 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f); 1630 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1690 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f); 1631 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1691 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140307); 1632 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307);
1692 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68160960); 1633 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960);
1693 1634
1694 /* LO calibration setting */ 1635 /* LO calibration setting */
1695 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1636 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1696 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911); 1637 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1697 1638
1698 /* path-B PA on */ 1639 /* path-B PA on */
1699 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x0f600700); 1640 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1700 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD, 0x061f0d30); 1641 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1701 1642
1702 for (i = 0; i < retrycount; i++) { 1643 for (i = 0; i < retrycount; i++) {
1703 /* One shot, path B LOK & IQK */ 1644 /* One shot, path B LOK & IQK */
1704 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1645 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1705 "One shot, path A LOK & IQK!\n"); 1646 "One shot, path A LOK & IQK!\n");
1706 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xfa000000); 1647 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000);
1707 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000); 1648 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1708 1649
1709 /* delay x ms */ 1650 /* delay x ms */
1710 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1651 RTPRINT(rtlpriv, FINIT, INIT_IQK,
@@ -1712,15 +1653,15 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1712 mdelay(IQK_DELAY_TIME * 10); 1653 mdelay(IQK_DELAY_TIME * 10);
1713 1654
1714 /* Check failed */ 1655 /* Check failed */
1715 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1656 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1716 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1657 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1717 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD); 1658 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1718 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1659 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1719 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD); 1660 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1720 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1661 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1721 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD); 1662 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1722 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1663 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1723 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD); 1664 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1724 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1665 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1725 if (!(regeac & BIT(31)) && 1666 if (!(regeac & BIT(31)) &&
1726 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) 1667 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
@@ -1738,9 +1679,9 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1738 } 1679 }
1739 1680
1740 /* path B PA off */ 1681 /* path B PA off */
1741 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 1682 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1742 rtlphy->iqk_bb_backup[0]); 1683 rtlphy->iqk_bb_backup[0]);
1743 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD, 1684 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
1744 rtlphy->iqk_bb_backup[2]); 1685 rtlphy->iqk_bb_backup[2]);
1745 return result; 1686 return result;
1746} 1687}
@@ -1754,7 +1695,7 @@ static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1754 1695
1755 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n"); 1696 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n");
1756 for (i = 0; i < regnum; i++) 1697 for (i = 0; i < regnum; i++)
1757 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], BMASKDWORD); 1698 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);
1758} 1699}
1759 1700
1760static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, 1701static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
@@ -1779,7 +1720,7 @@ static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1779 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1720 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1780 "Reload ADDA power saving parameters !\n"); 1721 "Reload ADDA power saving parameters !\n");
1781 for (i = 0; i < regnum; i++) 1722 for (i = 0; i < regnum; i++)
1782 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, adda_backup[i]); 1723 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
1783} 1724}
1784 1725
1785static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw, 1726static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
@@ -1807,7 +1748,7 @@ static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1807 pathon = rtlpriv->rtlhal.interfaceindex == 0 ? 1748 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1808 0x04db25a4 : 0x0b1b25a4; 1749 0x04db25a4 : 0x0b1b25a4;
1809 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 1750 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1810 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, pathon); 1751 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);
1811} 1752}
1812 1753
1813static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, 1754static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
@@ -1830,9 +1771,9 @@ static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1830 struct rtl_priv *rtlpriv = rtl_priv(hw); 1771 struct rtl_priv *rtlpriv = rtl_priv(hw);
1831 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n"); 1772 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n");
1832 1773
1833 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x0); 1774 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1834 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 0x00010000); 1775 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1835 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000); 1776 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1836} 1777}
1837 1778
1838static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode) 1779static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
@@ -1843,8 +1784,8 @@ static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1843 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1784 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1844 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI"); 1785 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1845 mode = pi_mode ? 0x01000100 : 0x01000000; 1786 mode = pi_mode ? 0x01000100 : 0x01000000;
1846 rtl_set_bbreg(hw, 0x820, BMASKDWORD, mode); 1787 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1847 rtl_set_bbreg(hw, 0x828, BMASKDWORD, mode); 1788 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1848} 1789}
1849 1790
1850static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], 1791static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
@@ -1875,7 +1816,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1875 1816
1876 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n"); 1817 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n");
1877 if (t == 0) { 1818 if (t == 0) {
1878 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD); 1819 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1879 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1820 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
1880 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1821 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1881 is2t ? "2T2R" : "1T1R"); 1822 is2t ? "2T2R" : "1T1R");
@@ -1898,40 +1839,40 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1898 _rtl92d_phy_pimode_switch(hw, true); 1839 _rtl92d_phy_pimode_switch(hw, true);
1899 1840
1900 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 1841 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1901 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600); 1842 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1902 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4); 1843 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1903 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22204000); 1844 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1904 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 1845 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1905 if (is2t) { 1846 if (is2t) {
1906 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 1847 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
1907 0x00010000); 1848 0x00010000);
1908 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, BMASKDWORD, 1849 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
1909 0x00010000); 1850 0x00010000);
1910 } 1851 }
1911 /* MAC settings */ 1852 /* MAC settings */
1912 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 1853 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1913 rtlphy->iqk_mac_backup); 1854 rtlphy->iqk_mac_backup);
1914 /* Page B init */ 1855 /* Page B init */
1915 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000); 1856 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1916 if (is2t) 1857 if (is2t)
1917 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000); 1858 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1918 /* IQ calibration setting */ 1859 /* IQ calibration setting */
1919 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 1860 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
1920 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000); 1861 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1921 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x01007c00); 1862 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1922 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800); 1863 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1923 for (i = 0; i < retrycount; i++) { 1864 for (i = 0; i < retrycount; i++) {
1924 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t); 1865 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1925 if (patha_ok == 0x03) { 1866 if (patha_ok == 0x03) {
1926 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1867 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1927 "Path A IQK Success!!\n"); 1868 "Path A IQK Success!!\n");
1928 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 1869 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1929 0x3FF0000) >> 16; 1870 0x3FF0000) >> 16;
1930 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) & 1871 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1931 0x3FF0000) >> 16; 1872 0x3FF0000) >> 16;
1932 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) & 1873 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1933 0x3FF0000) >> 16; 1874 0x3FF0000) >> 16;
1934 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) & 1875 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1935 0x3FF0000) >> 16; 1876 0x3FF0000) >> 16;
1936 break; 1877 break;
1937 } else if (i == (retrycount - 1) && patha_ok == 0x01) { 1878 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
@@ -1939,9 +1880,9 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1939 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1880 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1940 "Path A IQK Only Tx Success!!\n"); 1881 "Path A IQK Only Tx Success!!\n");
1941 1882
1942 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 1883 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1943 0x3FF0000) >> 16; 1884 0x3FF0000) >> 16;
1944 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) & 1885 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1945 0x3FF0000) >> 16; 1886 0x3FF0000) >> 16;
1946 } 1887 }
1947 } 1888 }
@@ -1957,22 +1898,22 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1957 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1898 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1958 "Path B IQK Success!!\n"); 1899 "Path B IQK Success!!\n");
1959 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1900 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1960 BMASKDWORD) & 0x3FF0000) >> 16; 1901 MASKDWORD) & 0x3FF0000) >> 16;
1961 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1902 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1962 BMASKDWORD) & 0x3FF0000) >> 16; 1903 MASKDWORD) & 0x3FF0000) >> 16;
1963 result[t][6] = (rtl_get_bbreg(hw, 0xec4, 1904 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1964 BMASKDWORD) & 0x3FF0000) >> 16; 1905 MASKDWORD) & 0x3FF0000) >> 16;
1965 result[t][7] = (rtl_get_bbreg(hw, 0xecc, 1906 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1966 BMASKDWORD) & 0x3FF0000) >> 16; 1907 MASKDWORD) & 0x3FF0000) >> 16;
1967 break; 1908 break;
1968 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1909 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1969 /* Tx IQK OK */ 1910 /* Tx IQK OK */
1970 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1911 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1971 "Path B Only Tx IQK Success!!\n"); 1912 "Path B Only Tx IQK Success!!\n");
1972 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1913 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1973 BMASKDWORD) & 0x3FF0000) >> 16; 1914 MASKDWORD) & 0x3FF0000) >> 16;
1974 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1915 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1975 BMASKDWORD) & 0x3FF0000) >> 16; 1916 MASKDWORD) & 0x3FF0000) >> 16;
1976 } 1917 }
1977 } 1918 }
1978 if (0x00 == pathb_ok) 1919 if (0x00 == pathb_ok)
@@ -1984,7 +1925,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1984 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1925 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1985 "IQK:Back to BB mode, load original value!\n"); 1926 "IQK:Back to BB mode, load original value!\n");
1986 1927
1987 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0); 1928 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1988 if (t != 0) { 1929 if (t != 0) {
1989 /* Switch back BB to SI mode after finish IQ Calibration. */ 1930 /* Switch back BB to SI mode after finish IQ Calibration. */
1990 if (!rtlphy->rfpi_enable) 1931 if (!rtlphy->rfpi_enable)
@@ -2004,8 +1945,8 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2004 rtlphy->iqk_bb_backup, 1945 rtlphy->iqk_bb_backup,
2005 IQK_BB_REG_NUM - 1); 1946 IQK_BB_REG_NUM - 1);
2006 /* load 0xe30 IQC default value */ 1947 /* load 0xe30 IQC default value */
2007 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x01008c00); 1948 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
2008 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x01008c00); 1949 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
2009 } 1950 }
2010 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 1951 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
2011} 1952}
@@ -2042,7 +1983,7 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2042 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n"); 1983 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n");
2043 mdelay(IQK_DELAY_TIME * 20); 1984 mdelay(IQK_DELAY_TIME * 20);
2044 if (t == 0) { 1985 if (t == 0) {
2045 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD); 1986 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
2046 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1987 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
2047 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1988 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
2048 is2t ? "2T2R" : "1T1R"); 1989 is2t ? "2T2R" : "1T1R");
@@ -2072,38 +2013,38 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2072 if (!rtlphy->rfpi_enable) 2013 if (!rtlphy->rfpi_enable)
2073 _rtl92d_phy_pimode_switch(hw, true); 2014 _rtl92d_phy_pimode_switch(hw, true);
2074 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 2015 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2075 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600); 2016 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
2076 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4); 2017 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
2077 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22208000); 2018 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
2078 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 2019 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2079 2020
2080 /* Page B init */ 2021 /* Page B init */
2081 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000); 2022 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
2082 if (is2t) 2023 if (is2t)
2083 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000); 2024 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
2084 /* IQ calibration setting */ 2025 /* IQ calibration setting */
2085 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 2026 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
2086 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000); 2027 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
2087 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x10007c00); 2028 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00);
2088 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800); 2029 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
2089 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t); 2030 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2090 if (patha_ok == 0x03) { 2031 if (patha_ok == 0x03) {
2091 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n"); 2032 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n");
2092 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 2033 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2093 0x3FF0000) >> 16; 2034 0x3FF0000) >> 16;
2094 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) & 2035 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2095 0x3FF0000) >> 16; 2036 0x3FF0000) >> 16;
2096 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) & 2037 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
2097 0x3FF0000) >> 16; 2038 0x3FF0000) >> 16;
2098 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) & 2039 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
2099 0x3FF0000) >> 16; 2040 0x3FF0000) >> 16;
2100 } else if (patha_ok == 0x01) { /* Tx IQK OK */ 2041 } else if (patha_ok == 0x01) { /* Tx IQK OK */
2101 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2042 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2102 "Path A IQK Only Tx Success!!\n"); 2043 "Path A IQK Only Tx Success!!\n");
2103 2044
2104 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 2045 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2105 0x3FF0000) >> 16; 2046 0x3FF0000) >> 16;
2106 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) & 2047 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2107 0x3FF0000) >> 16; 2048 0x3FF0000) >> 16;
2108 } else { 2049 } else {
2109 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n"); 2050 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n");
@@ -2116,20 +2057,20 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2116 if (pathb_ok == 0x03) { 2057 if (pathb_ok == 0x03) {
2117 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2058 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2118 "Path B IQK Success!!\n"); 2059 "Path B IQK Success!!\n");
2119 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) & 2060 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2120 0x3FF0000) >> 16; 2061 0x3FF0000) >> 16;
2121 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) & 2062 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2122 0x3FF0000) >> 16; 2063 0x3FF0000) >> 16;
2123 result[t][6] = (rtl_get_bbreg(hw, 0xec4, BMASKDWORD) & 2064 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
2124 0x3FF0000) >> 16; 2065 0x3FF0000) >> 16;
2125 result[t][7] = (rtl_get_bbreg(hw, 0xecc, BMASKDWORD) & 2066 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
2126 0x3FF0000) >> 16; 2067 0x3FF0000) >> 16;
2127 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ 2068 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2128 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2069 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2129 "Path B Only Tx IQK Success!!\n"); 2070 "Path B Only Tx IQK Success!!\n");
2130 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) & 2071 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2131 0x3FF0000) >> 16; 2072 0x3FF0000) >> 16;
2132 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) & 2073 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2133 0x3FF0000) >> 16; 2074 0x3FF0000) >> 16;
2134 } else { 2075 } else {
2135 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2076 RTPRINT(rtlpriv, FINIT, INIT_IQK,
@@ -2140,7 +2081,7 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2140 /* Back to BB mode, load original value */ 2081 /* Back to BB mode, load original value */
2141 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2082 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2142 "IQK:Back to BB mode, load original value!\n"); 2083 "IQK:Back to BB mode, load original value!\n");
2143 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0); 2084 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
2144 if (t != 0) { 2085 if (t != 0) {
2145 if (is2t) 2086 if (is2t)
2146 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 2087 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
@@ -2240,7 +2181,7 @@ static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2240 return; 2181 return;
2241 } else if (iqk_ok) { 2182 } else if (iqk_ok) {
2242 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 2183 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2243 BMASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ 2184 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
2244 val_x = result[final_candidate][0]; 2185 val_x = result[final_candidate][0];
2245 if ((val_x & 0x00000200) != 0) 2186 if ((val_x & 0x00000200) != 0)
2246 val_x = val_x | 0xFFFFFC00; 2187 val_x = val_x | 0xFFFFFC00;
@@ -2271,7 +2212,7 @@ static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2271 ((val_y * oldval_0 >> 7) & 0x1)); 2212 ((val_y * oldval_0 >> 7) & 0x1));
2272 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", 2213 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2273 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 2214 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2274 BMASKDWORD)); 2215 MASKDWORD));
2275 if (txonly) { 2216 if (txonly) {
2276 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); 2217 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n");
2277 return; 2218 return;
@@ -2299,7 +2240,7 @@ static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2299 return; 2240 return;
2300 } else if (iqk_ok) { 2241 } else if (iqk_ok) {
2301 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 2242 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2302 BMASKDWORD) >> 22) & 0x3FF; 2243 MASKDWORD) >> 22) & 0x3FF;
2303 val_x = result[final_candidate][4]; 2244 val_x = result[final_candidate][4];
2304 if ((val_x & 0x00000200) != 0) 2245 if ((val_x & 0x00000200) != 0)
2305 val_x = val_x | 0xFFFFFC00; 2246 val_x = val_x | 0xFFFFFC00;
@@ -2657,7 +2598,7 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2657 rf_mode[index] = rtl_read_byte(rtlpriv, offset); 2598 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2658 /* 2. Set RF mode = standby mode */ 2599 /* 2. Set RF mode = standby mode */
2659 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC, 2600 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2660 BRFREGOFFSETMASK, 0x010000); 2601 RFREG_OFFSET_MASK, 0x010000);
2661 if (rtlpci->init_ready) { 2602 if (rtlpci->init_ready) {
2662 /* switch CV-curve control by LC-calibration */ 2603 /* switch CV-curve control by LC-calibration */
2663 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 2604 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
@@ -2667,16 +2608,16 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2667 0x08000, 0x01); 2608 0x08000, 0x01);
2668 } 2609 }
2669 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6, 2610 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2670 BRFREGOFFSETMASK); 2611 RFREG_OFFSET_MASK);
2671 while ((!(u4tmp & BIT(11))) && timecount <= timeout) { 2612 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2672 mdelay(50); 2613 mdelay(50);
2673 timecount += 50; 2614 timecount += 50;
2674 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, 2615 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2675 RF_SYN_G6, BRFREGOFFSETMASK); 2616 RF_SYN_G6, RFREG_OFFSET_MASK);
2676 } 2617 }
2677 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2618 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2678 "PHY_LCK finish delay for %d ms=2\n", timecount); 2619 "PHY_LCK finish delay for %d ms=2\n", timecount);
2679 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, BRFREGOFFSETMASK); 2620 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);
2680 if (index == 0 && rtlhal->interfaceindex == 0) { 2621 if (index == 0 && rtlhal->interfaceindex == 0) {
2681 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2622 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2682 "path-A / 5G LCK\n"); 2623 "path-A / 5G LCK\n");
@@ -2696,9 +2637,9 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2696 0x7f, i); 2637 0x7f, i);
2697 2638
2698 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, 2639 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2699 BRFREGOFFSETMASK, 0x0); 2640 RFREG_OFFSET_MASK, 0x0);
2700 readval = rtl_get_rfreg(hw, (enum radio_path)index, 2641 readval = rtl_get_rfreg(hw, (enum radio_path)index,
2701 0x4F, BRFREGOFFSETMASK); 2642 0x4F, RFREG_OFFSET_MASK);
2702 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; 2643 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2703 /* reg 0x4f [4:0] */ 2644 /* reg 0x4f [4:0] */
2704 /* reg 0x50 [19:10] */ 2645 /* reg 0x50 [19:10] */
@@ -2912,7 +2853,7 @@ static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2912 } 2853 }
2913 rtl_set_rfreg(hw, (enum radio_path)rfpath, 2854 rtl_set_rfreg(hw, (enum radio_path)rfpath,
2914 currentcmd->para1, 2855 currentcmd->para1,
2915 BRFREGOFFSETMASK, 2856 RFREG_OFFSET_MASK,
2916 rtlphy->rfreg_chnlval[rfpath]); 2857 rtlphy->rfreg_chnlval[rfpath]);
2917 _rtl92d_phy_reload_imr_setting(hw, channel, 2858 _rtl92d_phy_reload_imr_setting(hw, channel,
2918 rfpath); 2859 rfpath);
@@ -2960,7 +2901,7 @@ u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2960 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY && 2901 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2961 rtlhal->bandset == BAND_ON_BOTH) { 2902 rtlhal->bandset == BAND_ON_BOTH) {
2962 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 2903 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2963 BMASKDWORD); 2904 MASKDWORD);
2964 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) 2905 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2965 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G); 2906 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2966 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) 2907 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
@@ -3112,7 +3053,7 @@ static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3112 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ 3053 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
3113 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 3054 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3114 /* b. RF path 0 offset 0x00 = 0x00 disable RF */ 3055 /* b. RF path 0 offset 0x00 = 0x00 disable RF */
3115 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00); 3056 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3116 /* c. APSD_CTRL 0x600[7:0] = 0x40 */ 3057 /* c. APSD_CTRL 0x600[7:0] = 0x40 */
3117 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 3058 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3118 /* d. APSD_CTRL 0x600[7:0] = 0x00 3059 /* d. APSD_CTRL 0x600[7:0] = 0x00
@@ -3120,12 +3061,12 @@ static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3120 * RF path 0 offset 0x00 = 0x00 3061 * RF path 0 offset 0x00 = 0x00
3121 * APSD_CTRL 0x600[7:0] = 0x40 3062 * APSD_CTRL 0x600[7:0] = 0x40
3122 * */ 3063 * */
3123 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK); 3064 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3124 while (u4btmp != 0 && delay > 0) { 3065 while (u4btmp != 0 && delay > 0) {
3125 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); 3066 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3126 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00); 3067 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3127 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 3068 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3128 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK); 3069 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3129 delay--; 3070 delay--;
3130 } 3071 }
3131 if (delay == 0) { 3072 if (delay == 0) {
@@ -3468,9 +3409,9 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3468 /* 5G LAN ON */ 3409 /* 5G LAN ON */
3469 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); 3410 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3470 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */ 3411 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3471 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD, 3412 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3472 0x40000100); 3413 0x40000100);
3473 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD, 3414 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3474 0x40000100); 3415 0x40000100);
3475 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 3416 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3476 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3417 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
@@ -3524,16 +3465,16 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3524 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); 3465 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3525 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */ 3466 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3526 if (rtlefuse->internal_pa_5g[0]) 3467 if (rtlefuse->internal_pa_5g[0])
3527 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD, 3468 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3528 0x2d4000b5); 3469 0x2d4000b5);
3529 else 3470 else
3530 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD, 3471 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3531 0x20000080); 3472 0x20000080);
3532 if (rtlefuse->internal_pa_5g[1]) 3473 if (rtlefuse->internal_pa_5g[1])
3533 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD, 3474 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3534 0x2d4000b5); 3475 0x2d4000b5);
3535 else 3476 else
3536 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD, 3477 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3537 0x20000080); 3478 0x20000080);
3538 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 3479 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3539 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3480 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
@@ -3560,8 +3501,8 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3560 } 3501 }
3561 } 3502 }
3562 /* update IQK related settings */ 3503 /* update IQK related settings */
3563 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, BMASKDWORD, 0x40000100); 3504 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3564 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, BMASKDWORD, 0x40000100); 3505 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3565 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00); 3506 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3566 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | 3507 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3567 BIT(26) | BIT(24), 0x00); 3508 BIT(26) | BIT(24), 0x00);
@@ -3590,7 +3531,7 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3590 /* DMDP */ 3531 /* DMDP */
3591 if (rtlphy->rf_type == RF_1T1R) { 3532 if (rtlphy->rf_type == RF_1T1R) {
3592 /* Use antenna 0,0xc04,0xd04 */ 3533 /* Use antenna 0,0xc04,0xd04 */
3593 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x11); 3534 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
3594 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); 3535 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3595 3536
3596 /* enable ad/da clock1 for dual-phy reg0x888 */ 3537 /* enable ad/da clock1 for dual-phy reg0x888 */
@@ -3612,7 +3553,7 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3612 } else { 3553 } else {
3613 /* Single PHY */ 3554 /* Single PHY */
3614 /* Use antenna 0 & 1,0xc04,0xd04 */ 3555 /* Use antenna 0 & 1,0xc04,0xd04 */
3615 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x33); 3556 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
3616 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); 3557 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3617 /* disable ad/da clock1,0x888 */ 3558 /* disable ad/da clock1,0x888 */
3618 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); 3559 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
@@ -3620,9 +3561,9 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3620 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 3561 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3621 rfpath++) { 3562 rfpath++) {
3622 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, 3563 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3623 RF_CHNLBW, BRFREGOFFSETMASK); 3564 RF_CHNLBW, RFREG_OFFSET_MASK);
3624 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, 3565 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3625 BRFREGOFFSETMASK); 3566 RFREG_OFFSET_MASK);
3626 } 3567 }
3627 for (i = 0; i < 2; i++) 3568 for (i = 0; i < 2; i++)
3628 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", 3569 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/reg.h b/drivers/net/wireless/rtlwifi/rtl8192de/reg.h
index b7498c5bafc5..7f29b8d765b3 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/reg.h
@@ -1295,18 +1295,4 @@
1295#define BWORD1 0xc 1295#define BWORD1 0xc
1296#define BDWORD 0xf 1296#define BDWORD 0xf
1297 1297
1298#define BMASKBYTE0 0xff
1299#define BMASKBYTE1 0xff00
1300#define BMASKBYTE2 0xff0000
1301#define BMASKBYTE3 0xff000000
1302#define BMASKHWORD 0xffff0000
1303#define BMASKLWORD 0x0000ffff
1304#define BMASKDWORD 0xffffffff
1305#define BMASK12BITS 0xfff
1306#define BMASKH4BITS 0xf0000000
1307#define BMASKOFDM_D 0xffc00000
1308#define BMASKCCK 0x3f3f3f3f
1309
1310#define BRFREGOFFSETMASK 0xfffff
1311
1312#endif 1298#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/rf.c b/drivers/net/wireless/rtlwifi/rtl8192de/rf.c
index 20144e0b4142..6a6ac540d5b5 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/rf.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/rf.c
@@ -125,7 +125,7 @@ void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
125 } 125 }
126 126
127 tmpval = tx_agc[RF90_PATH_A] & 0xff; 127 tmpval = tx_agc[RF90_PATH_A] & 0xff;
128 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, BMASKBYTE1, tmpval); 128 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
129 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 129 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
130 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", 130 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n",
131 tmpval, RTXAGC_A_CCK1_MCS32); 131 tmpval, RTXAGC_A_CCK1_MCS32);
@@ -135,7 +135,7 @@ void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
135 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", 135 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n",
136 tmpval, RTXAGC_B_CCK11_A_CCK2_11); 136 tmpval, RTXAGC_B_CCK11_A_CCK2_11);
137 tmpval = tx_agc[RF90_PATH_B] >> 24; 137 tmpval = tx_agc[RF90_PATH_B] >> 24;
138 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, BMASKBYTE0, tmpval); 138 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
139 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 139 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
140 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", 140 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n",
141 tmpval, RTXAGC_B_CCK11_A_CCK2_11); 141 tmpval, RTXAGC_B_CCK11_A_CCK2_11);
@@ -360,7 +360,7 @@ static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw,
360 regoffset = regoffset_a[index]; 360 regoffset = regoffset_a[index];
361 else 361 else
362 regoffset = regoffset_b[index]; 362 regoffset = regoffset_b[index];
363 rtl_set_bbreg(hw, regoffset, BMASKDWORD, writeval); 363 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
364 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, 364 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
365 "Set 0x%x = %08x\n", regoffset, writeval); 365 "Set 0x%x = %08x\n", regoffset, writeval);
366 if (((get_rf_type(rtlphy) == RF_2T2R) && 366 if (((get_rf_type(rtlphy) == RF_2T2R) &&
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/phy.c b/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
index 9c092e6eb3fe..77c5b5f35244 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
@@ -30,6 +30,7 @@
30#include "../wifi.h" 30#include "../wifi.h"
31#include "../pci.h" 31#include "../pci.h"
32#include "../ps.h" 32#include "../ps.h"
33#include "../core.h"
33#include "reg.h" 34#include "reg.h"
34#include "def.h" 35#include "def.h"
35#include "phy.h" 36#include "phy.h"
@@ -833,18 +834,7 @@ static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
833 834
834 if (configtype == BASEBAND_CONFIG_PHY_REG) { 835 if (configtype == BASEBAND_CONFIG_PHY_REG) {
835 for (i = 0; i < phy_reg_len; i = i + 2) { 836 for (i = 0; i < phy_reg_len; i = i + 2) {
836 if (phy_reg_table[i] == 0xfe) 837 rtl_addr_delay(phy_reg_table[i]);
837 mdelay(50);
838 else if (phy_reg_table[i] == 0xfd)
839 mdelay(5);
840 else if (phy_reg_table[i] == 0xfc)
841 mdelay(1);
842 else if (phy_reg_table[i] == 0xfb)
843 udelay(50);
844 else if (phy_reg_table[i] == 0xfa)
845 udelay(5);
846 else if (phy_reg_table[i] == 0xf9)
847 udelay(1);
848 838
849 /* Add delay for ECS T20 & LG malow platform, */ 839 /* Add delay for ECS T20 & LG malow platform, */
850 udelay(1); 840 udelay(1);
@@ -886,18 +876,7 @@ static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
886 876
887 if (configtype == BASEBAND_CONFIG_PHY_REG) { 877 if (configtype == BASEBAND_CONFIG_PHY_REG) {
888 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) { 878 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
889 if (phy_regarray2xtxr_table[i] == 0xfe) 879 rtl_addr_delay(phy_regarray2xtxr_table[i]);
890 mdelay(50);
891 else if (phy_regarray2xtxr_table[i] == 0xfd)
892 mdelay(5);
893 else if (phy_regarray2xtxr_table[i] == 0xfc)
894 mdelay(1);
895 else if (phy_regarray2xtxr_table[i] == 0xfb)
896 udelay(50);
897 else if (phy_regarray2xtxr_table[i] == 0xfa)
898 udelay(5);
899 else if (phy_regarray2xtxr_table[i] == 0xf9)
900 udelay(1);
901 880
902 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i], 881 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
903 phy_regarray2xtxr_table[i + 1], 882 phy_regarray2xtxr_table[i + 1],
@@ -920,18 +899,7 @@ static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
920 899
921 if (configtype == BASEBAND_CONFIG_PHY_REG) { 900 if (configtype == BASEBAND_CONFIG_PHY_REG) {
922 for (i = 0; i < phy_pg_len; i = i + 3) { 901 for (i = 0; i < phy_pg_len; i = i + 3) {
923 if (phy_table_pg[i] == 0xfe) 902 rtl_addr_delay(phy_table_pg[i]);
924 mdelay(50);
925 else if (phy_table_pg[i] == 0xfd)
926 mdelay(5);
927 else if (phy_table_pg[i] == 0xfc)
928 mdelay(1);
929 else if (phy_table_pg[i] == 0xfb)
930 udelay(50);
931 else if (phy_table_pg[i] == 0xfa)
932 udelay(5);
933 else if (phy_table_pg[i] == 0xf9)
934 udelay(1);
935 903
936 _rtl92s_store_pwrindex_diffrate_offset(hw, 904 _rtl92s_store_pwrindex_diffrate_offset(hw,
937 phy_table_pg[i], 905 phy_table_pg[i],
@@ -1034,28 +1002,9 @@ u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
1034 switch (rfpath) { 1002 switch (rfpath) {
1035 case RF90_PATH_A: 1003 case RF90_PATH_A:
1036 for (i = 0; i < radio_a_tblen; i = i + 2) { 1004 for (i = 0; i < radio_a_tblen; i = i + 2) {
1037 if (radio_a_table[i] == 0xfe) 1005 rtl_rfreg_delay(hw, rfpath, radio_a_table[i],
1038 /* Delay specific ms. Only RF configuration 1006 MASK20BITS, radio_a_table[i + 1]);
1039 * requires delay. */
1040 mdelay(50);
1041 else if (radio_a_table[i] == 0xfd)
1042 mdelay(5);
1043 else if (radio_a_table[i] == 0xfc)
1044 mdelay(1);
1045 else if (radio_a_table[i] == 0xfb)
1046 udelay(50);
1047 else if (radio_a_table[i] == 0xfa)
1048 udelay(5);
1049 else if (radio_a_table[i] == 0xf9)
1050 udelay(1);
1051 else
1052 rtl92s_phy_set_rf_reg(hw, rfpath,
1053 radio_a_table[i],
1054 MASK20BITS,
1055 radio_a_table[i + 1]);
1056 1007
1057 /* Add delay for ECS T20 & LG malow platform */
1058 udelay(1);
1059 } 1008 }
1060 1009
1061 /* PA Bias current for inferiority IC */ 1010 /* PA Bias current for inferiority IC */
@@ -1063,28 +1012,8 @@ u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
1063 break; 1012 break;
1064 case RF90_PATH_B: 1013 case RF90_PATH_B:
1065 for (i = 0; i < radio_b_tblen; i = i + 2) { 1014 for (i = 0; i < radio_b_tblen; i = i + 2) {
1066 if (radio_b_table[i] == 0xfe) 1015 rtl_rfreg_delay(hw, rfpath, radio_b_table[i],
1067 /* Delay specific ms. Only RF configuration 1016 MASK20BITS, radio_b_table[i + 1]);
1068 * requires delay.*/
1069 mdelay(50);
1070 else if (radio_b_table[i] == 0xfd)
1071 mdelay(5);
1072 else if (radio_b_table[i] == 0xfc)
1073 mdelay(1);
1074 else if (radio_b_table[i] == 0xfb)
1075 udelay(50);
1076 else if (radio_b_table[i] == 0xfa)
1077 udelay(5);
1078 else if (radio_b_table[i] == 0xf9)
1079 udelay(1);
1080 else
1081 rtl92s_phy_set_rf_reg(hw, rfpath,
1082 radio_b_table[i],
1083 MASK20BITS,
1084 radio_b_table[i + 1]);
1085
1086 /* Add delay for ECS T20 & LG malow platform */
1087 udelay(1);
1088 } 1017 }
1089 break; 1018 break;
1090 case RF90_PATH_C: 1019 case RF90_PATH_C:
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/reg.h b/drivers/net/wireless/rtlwifi/rtl8192se/reg.h
index c81c83591940..e13043479b71 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/reg.h
@@ -1165,16 +1165,4 @@
1165 1165
1166#define BTX_AGCRATECCK 0x7f00 1166#define BTX_AGCRATECCK 0x7f00
1167 1167
1168#define MASKBYTE0 0xff
1169#define MASKBYTE1 0xff00
1170#define MASKBYTE2 0xff0000
1171#define MASKBYTE3 0xff000000
1172#define MASKHWORD 0xffff0000
1173#define MASKLWORD 0x0000ffff
1174#define MASKDWORD 0xffffffff
1175
1176#define MAKS12BITS 0xfffff
1177#define MASK20BITS 0xfffff
1178#define RFREG_OFFSET_MASK 0xfffff
1179
1180#endif 1168#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/Makefile b/drivers/net/wireless/rtlwifi/rtl8723ae/Makefile
index 4ed731f09b1f..9c34a85fdb89 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/Makefile
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/Makefile
@@ -10,7 +10,6 @@ rtl8723ae-objs := \
10 led.o \ 10 led.o \
11 phy.o \ 11 phy.o \
12 pwrseq.o \ 12 pwrseq.o \
13 pwrseqcmd.o \
14 rf.o \ 13 rf.o \
15 sw.o \ 14 sw.o \
16 table.o \ 15 table.o \
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
index 8a8577a1783b..b47167c96b58 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
@@ -43,7 +43,6 @@
43#include "../rtl8723com/fw_common.h" 43#include "../rtl8723com/fw_common.h"
44#include "led.h" 44#include "led.h"
45#include "hw.h" 45#include "hw.h"
46#include "pwrseqcmd.h"
47#include "pwrseq.h" 46#include "pwrseq.h"
48#include "btc.h" 47#include "btc.h"
49 48
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c b/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
index 4f8189d3bb44..3ea78afdec73 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
@@ -30,6 +30,7 @@
30#include "../wifi.h" 30#include "../wifi.h"
31#include "../pci.h" 31#include "../pci.h"
32#include "../ps.h" 32#include "../ps.h"
33#include "../core.h"
33#include "reg.h" 34#include "reg.h"
34#include "def.h" 35#include "def.h"
35#include "phy.h" 36#include "phy.h"
@@ -277,18 +278,7 @@ static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype)
277 phy_regarray_table = RTL8723EPHY_REG_1TARRAY; 278 phy_regarray_table = RTL8723EPHY_REG_1TARRAY;
278 if (configtype == BASEBAND_CONFIG_PHY_REG) { 279 if (configtype == BASEBAND_CONFIG_PHY_REG) {
279 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 280 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
280 if (phy_regarray_table[i] == 0xfe) 281 rtl_addr_delay(phy_regarray_table[i]);
281 mdelay(50);
282 else if (phy_regarray_table[i] == 0xfd)
283 mdelay(5);
284 else if (phy_regarray_table[i] == 0xfc)
285 mdelay(1);
286 else if (phy_regarray_table[i] == 0xfb)
287 udelay(50);
288 else if (phy_regarray_table[i] == 0xfa)
289 udelay(5);
290 else if (phy_regarray_table[i] == 0xf9)
291 udelay(1);
292 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, 282 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
293 phy_regarray_table[i + 1]); 283 phy_regarray_table[i + 1]);
294 udelay(1); 284 udelay(1);
@@ -450,18 +440,7 @@ static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype)
450 440
451 if (configtype == BASEBAND_CONFIG_PHY_REG) { 441 if (configtype == BASEBAND_CONFIG_PHY_REG) {
452 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 442 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
453 if (phy_regarray_table_pg[i] == 0xfe) 443 rtl_addr_delay(phy_regarray_table_pg[i]);
454 mdelay(50);
455 else if (phy_regarray_table_pg[i] == 0xfd)
456 mdelay(5);
457 else if (phy_regarray_table_pg[i] == 0xfc)
458 mdelay(1);
459 else if (phy_regarray_table_pg[i] == 0xfb)
460 udelay(50);
461 else if (phy_regarray_table_pg[i] == 0xfa)
462 udelay(5);
463 else if (phy_regarray_table_pg[i] == 0xf9)
464 udelay(1);
465 444
466 _st_pwrIdx_dfrate_off(hw, phy_regarray_table_pg[i], 445 _st_pwrIdx_dfrate_off(hw, phy_regarray_table_pg[i],
467 phy_regarray_table_pg[i + 1], 446 phy_regarray_table_pg[i + 1],
@@ -488,24 +467,9 @@ bool rtl8723ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
488 switch (rfpath) { 467 switch (rfpath) {
489 case RF90_PATH_A: 468 case RF90_PATH_A:
490 for (i = 0; i < radioa_arraylen; i = i + 2) { 469 for (i = 0; i < radioa_arraylen; i = i + 2) {
491 if (radioa_array_table[i] == 0xfe) 470 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
492 mdelay(50); 471 RFREG_OFFSET_MASK,
493 else if (radioa_array_table[i] == 0xfd) 472 radioa_array_table[i + 1]);
494 mdelay(5);
495 else if (radioa_array_table[i] == 0xfc)
496 mdelay(1);
497 else if (radioa_array_table[i] == 0xfb)
498 udelay(50);
499 else if (radioa_array_table[i] == 0xfa)
500 udelay(5);
501 else if (radioa_array_table[i] == 0xf9)
502 udelay(1);
503 else {
504 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
505 RFREG_OFFSET_MASK,
506 radioa_array_table[i + 1]);
507 udelay(1);
508 }
509 } 473 }
510 break; 474 break;
511 case RF90_PATH_B: 475 case RF90_PATH_B:
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h b/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h
index 7a46f9fdf558..a418acb4d0ca 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h
@@ -30,7 +30,6 @@
30#ifndef __RTL8723E_PWRSEQ_H__ 30#ifndef __RTL8723E_PWRSEQ_H__
31#define __RTL8723E_PWRSEQ_H__ 31#define __RTL8723E_PWRSEQ_H__
32 32
33#include "pwrseqcmd.h"
34/* 33/*
35 Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd 34 Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
36 There are 6 HW Power States: 35 There are 6 HW Power States:
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h b/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h
index 199da366c6da..64376b38708b 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/reg.h
@@ -2059,22 +2059,6 @@
2059#define BWORD1 0xc 2059#define BWORD1 0xc
2060#define BWORD 0xf 2060#define BWORD 0xf
2061 2061
2062#define MASKBYTE0 0xff
2063#define MASKBYTE1 0xff00
2064#define MASKBYTE2 0xff0000
2065#define MASKBYTE3 0xff000000
2066#define MASKHWORD 0xffff0000
2067#define MASKLWORD 0x0000ffff
2068#define MASKDWORD 0xffffffff
2069#define MASK12BITS 0xfff
2070#define MASKH4BITS 0xf0000000
2071#define MASKOFDM_D 0xffc00000
2072#define MASKCCK 0x3f3f3f3f
2073
2074#define MASK4BITS 0x0f
2075#define MASK20BITS 0xfffff
2076#define RFREG_OFFSET_MASK 0xfffff
2077
2078#define BENABLE 0x1 2062#define BENABLE 0x1
2079#define BDISABLE 0x0 2063#define BDISABLE 0x0
2080 2064
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/Makefile b/drivers/net/wireless/rtlwifi/rtl8723be/Makefile
index 4a75aab0539a..59e416abd93a 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/Makefile
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/Makefile
@@ -8,7 +8,6 @@ rtl8723be-objs := \
8 led.o \ 8 led.o \
9 phy.o \ 9 phy.o \
10 pwrseq.o \ 10 pwrseq.o \
11 pwrseqcmd.o \
12 rf.o \ 11 rf.o \
13 sw.o \ 12 sw.o \
14 table.o \ 13 table.o \
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/hw.c b/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
index a500d266fae5..fc2af714e9ec 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/hw.c
@@ -39,7 +39,6 @@
39#include "../rtl8723com/fw_common.h" 39#include "../rtl8723com/fw_common.h"
40#include "led.h" 40#include "led.h"
41#include "hw.h" 41#include "hw.h"
42#include "pwrseqcmd.h"
43#include "pwrseq.h" 42#include "pwrseq.h"
44#include "../btcoexist/rtl_btc.h" 43#include "../btcoexist/rtl_btc.h"
45 44
@@ -818,9 +817,9 @@ static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
818 mac_func_enable = false; 817 mac_func_enable = false;
819 818
820 /* HW Power on sequence */ 819 /* HW Power on sequence */
821 if (!rtlbe_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 820 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
822 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 821 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
823 RTL8723_NIC_ENABLE_FLOW)) { 822 RTL8723_NIC_ENABLE_FLOW)) {
824 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 823 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
825 "init MAC Fail as power on failure\n"); 824 "init MAC Fail as power on failure\n");
826 return false; 825 return false;
@@ -1309,8 +1308,8 @@ static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1309 1308
1310 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1309 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1311 /* 1. Run LPS WL RFOFF flow */ 1310 /* 1. Run LPS WL RFOFF flow */
1312 rtlbe_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1311 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1313 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW); 1312 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1314 1313
1315 /* 2. 0x1F[7:0] = 0 */ 1314 /* 2. 0x1F[7:0] = 0 */
1316 /* turn off RF */ 1315 /* turn off RF */
@@ -1328,8 +1327,8 @@ static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1328 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1327 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1329 1328
1330 /* HW card disable configuration. */ 1329 /* HW card disable configuration. */
1331 rtlbe_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1330 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1332 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW); 1331 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1333 1332
1334 /* Reset MCU IO Wrapper */ 1333 /* Reset MCU IO Wrapper */
1335 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1334 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/phy.c b/drivers/net/wireless/rtlwifi/rtl8723be/phy.c
index ebc1e2788fca..cadae9bc4e3f 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/phy.c
@@ -26,6 +26,7 @@
26#include "../wifi.h" 26#include "../wifi.h"
27#include "../pci.h" 27#include "../pci.h"
28#include "../ps.h" 28#include "../ps.h"
29#include "../core.h"
29#include "reg.h" 30#include "reg.h"
30#include "def.h" 31#include "def.h"
31#include "phy.h" 32#include "phy.h"
@@ -41,9 +42,6 @@ static bool _rtl8723be_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
41static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw, 42static bool rtl8723be_phy_sw_chn_step_by_step(struct ieee80211_hw *hw,
42 u8 channel, u8 *stage, 43 u8 channel, u8 *stage,
43 u8 *step, u32 *delay); 44 u8 *step, u32 *delay);
44static void _rtl8723be_config_bb_reg(struct ieee80211_hw *hw,
45 u32 addr, u32 data);
46
47static bool _rtl8723be_check_condition(struct ieee80211_hw *hw, 45static bool _rtl8723be_check_condition(struct ieee80211_hw *hw,
48 const u32 condition) 46 const u32 condition)
49{ 47{
@@ -114,7 +112,7 @@ static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
114 v1 = array_table[i]; 112 v1 = array_table[i];
115 v2 = array_table[i+1]; 113 v2 = array_table[i+1];
116 if (v1 < 0xcdcdcdcd) { 114 if (v1 < 0xcdcdcdcd) {
117 _rtl8723be_config_bb_reg(hw, v1, v2); 115 rtl_bb_delay(hw, v1, v2);
118 } else {/*This line is the start line of branch.*/ 116 } else {/*This line is the start line of branch.*/
119 if (!_rtl8723be_check_condition(hw, array_table[i])) { 117 if (!_rtl8723be_check_condition(hw, array_table[i])) {
120 /*Discard the following (offset, data) pairs*/ 118 /*Discard the following (offset, data) pairs*/
@@ -135,7 +133,7 @@ static bool _rtl8723be_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
135 v2 != 0xCDEF && 133 v2 != 0xCDEF &&
136 v2 != 0xCDCD && 134 v2 != 0xCDCD &&
137 i < arraylen - 2) { 135 i < arraylen - 2) {
138 _rtl8723be_config_bb_reg(hw, 136 rtl_bb_delay(hw,
139 v1, v2); 137 v1, v2);
140 READ_NEXT_PAIR(v1, v2, i); 138 READ_NEXT_PAIR(v1, v2, i);
141 } 139 }
@@ -389,27 +387,6 @@ static void _rtl8723be_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
389 [path][txnum][section] = 0; 387 [path][txnum][section] = 0;
390} 388}
391 389
392static void _rtl8723be_config_bb_reg(struct ieee80211_hw *hw,
393 u32 addr, u32 data)
394{
395 if (addr == 0xfe) {
396 mdelay(50);
397 } else if (addr == 0xfd) {
398 mdelay(5);
399 } else if (addr == 0xfc) {
400 mdelay(1);
401 } else if (addr == 0xfb) {
402 udelay(50);
403 } else if (addr == 0xfa) {
404 udelay(5);
405 } else if (addr == 0xf9) {
406 udelay(1);
407 } else {
408 rtl_set_bbreg(hw, addr, MASKDWORD, data);
409 udelay(1);
410 }
411}
412
413static void phy_set_txpwr_by_rate_base(struct ieee80211_hw *hw, u8 band, 390static void phy_set_txpwr_by_rate_base(struct ieee80211_hw *hw, u8 band,
414 u8 path, u8 rate_section, 391 u8 path, u8 rate_section,
415 u8 txnum, u8 value) 392 u8 txnum, u8 value)
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.h b/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.h
index 960b408216df..a62f43ed8d32 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/pwrseq.h
@@ -26,7 +26,6 @@
26#ifndef __RTL8723BE_PWRSEQ_H__ 26#ifndef __RTL8723BE_PWRSEQ_H__
27#define __RTL8723BE_PWRSEQ_H__ 27#define __RTL8723BE_PWRSEQ_H__
28 28
29#include "pwrseqcmd.h"
30/* Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd 29/* Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd
31 * There are 6 HW Power States: 30 * There are 6 HW Power States:
32 * 0: POFF--Power Off 31 * 0: POFF--Power Off
diff --git a/drivers/net/wireless/rtlwifi/rtl8723be/reg.h b/drivers/net/wireless/rtlwifi/rtl8723be/reg.h
index 65221e678230..4c653fab8795 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723be/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8723be/reg.h
@@ -2242,22 +2242,6 @@
2242#define BWORD1 0xc 2242#define BWORD1 0xc
2243#define BWORD 0xf 2243#define BWORD 0xf
2244 2244
2245#define MASKBYTE0 0xff
2246#define MASKBYTE1 0xff00
2247#define MASKBYTE2 0xff0000
2248#define MASKBYTE3 0xff000000
2249#define MASKHWORD 0xffff0000
2250#define MASKLWORD 0x0000ffff
2251#define MASKDWORD 0xffffffff
2252#define MASK12BITS 0xfff
2253#define MASKH4BITS 0xf0000000
2254#define MASKOFDM_D 0xffc00000
2255#define MASKCCK 0x3f3f3f3f
2256
2257#define MASK4BITS 0x0f
2258#define MASK20BITS 0xfffff
2259#define RFREG_OFFSET_MASK 0xfffff
2260
2261#define BENABLE 0x1 2245#define BENABLE 0x1
2262#define BDISABLE 0x0 2246#define BDISABLE 0x0
2263 2247
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
index 5cb799e6bd08..0b4d641bf715 100644
--- a/drivers/net/wireless/rtlwifi/wifi.h
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -57,6 +57,22 @@
57#define MASK20BITS 0xfffff 57#define MASK20BITS 0xfffff
58#define RFREG_OFFSET_MASK 0xfffff 58#define RFREG_OFFSET_MASK 0xfffff
59 59
60#define MASKBYTE0 0xff
61#define MASKBYTE1 0xff00
62#define MASKBYTE2 0xff0000
63#define MASKBYTE3 0xff000000
64#define MASKHWORD 0xffff0000
65#define MASKLWORD 0x0000ffff
66#define MASKDWORD 0xffffffff
67#define MASK12BITS 0xfff
68#define MASKH4BITS 0xf0000000
69#define MASKOFDM_D 0xffc00000
70#define MASKCCK 0x3f3f3f3f
71
72#define MASK4BITS 0x0f
73#define MASK20BITS 0xfffff
74#define RFREG_OFFSET_MASK 0xfffff
75
60#define RF_CHANGE_BY_INIT 0 76#define RF_CHANGE_BY_INIT 0
61#define RF_CHANGE_BY_IPS BIT(28) 77#define RF_CHANGE_BY_IPS BIT(28)
62#define RF_CHANGE_BY_PS BIT(29) 78#define RF_CHANGE_BY_PS BIT(29)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 00:21:41 -0500