Merge remote branch 'wireless-next/master' into ath6kl-next

Conflicts:
	drivers/net/wireless/ath/ath6kl/init.c

78 files changed, 6166 insertions, 1412 deletions

diff --git a/drivers/net/wireless/ath/Kconfig b/drivers/net/wireless/ath/Kconfig
index 073548836413..09602241901b 100644
--- a/drivers/net/wireless/ath/Kconfig
+++ b/drivers/net/wireless/ath/Kconfig
@@ -1,6 +1,6 @@
 menuconfig ATH_COMMON
         tristate "Atheros Wireless Cards"
-        depends on CFG80211
+        depends on CFG80211 && (!UML || BROKEN)
         ---help---
           This will enable the support for the Atheros wireless drivers.
           ath5k, ath9k, ath9k_htc and ar9170 drivers share some common code, this option
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
index fe4bf4da255f..c1d699fd5717 100644
--- a/drivers/net/wireless/ath/ath.h
+++ b/drivers/net/wireless/ath/ath.h
@@ -152,6 +152,7 @@ struct ath_common {
         struct ath_cycle_counters cc_survey;
 
         struct ath_regulatory regulatory;
+        struct ath_regulatory reg_world_copy;
         const struct ath_ops *ops;
         const struct ath_bus_ops *bus_ops;
 
@@ -173,8 +174,7 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry);
 void ath_hw_cycle_counters_update(struct ath_common *common);
 int32_t ath_hw_get_listen_time(struct ath_common *common);
 
-extern __attribute__((format (printf, 2, 3)))
-void ath_printk(const char *level, const char *fmt, ...);
+extern __printf(2, 3) void ath_printk(const char *level, const char *fmt, ...);
 
 #define _ath_printk(level, common, fmt, ...)                    \
 do {                                                            \
@@ -215,6 +215,10 @@ do {								\
  * @ATH_DBG_HWTIMER: hardware timer handling
  * @ATH_DBG_BTCOEX: bluetooth coexistance
  * @ATH_DBG_BSTUCK: stuck beacons
+ * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
+ *      used exclusively for WLAN-BT coexistence starting from
+ *      AR9462.
+ * @ATH_DBG_DFS: radar datection
  * @ATH_DBG_ANY: enable all debugging
  *
  * The debug level is used to control the amount and type of debugging output
@@ -241,6 +245,7 @@ enum ATH_DEBUG {
         ATH_DBG_WMI             = 0x00004000,
         ATH_DBG_BSTUCK          = 0x00008000,
         ATH_DBG_MCI             = 0x00010000,
+        ATH_DBG_DFS             = 0x00020000,
         ATH_DBG_ANY             = 0xffffffff
 };
 
@@ -259,7 +264,7 @@ do {									\
 
 #else
 
-static inline  __attribute__((format (printf, 3, 4)))
+static inline  __attribute__ ((format (printf, 3, 4)))
 void ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
              const char *fmt, ...)
 {
diff --git a/drivers/net/wireless/ath/ath5k/ahb.c b/drivers/net/wireless/ath/ath5k/ahb.c
index e5be7e701816..ee7ea572b065 100644
--- a/drivers/net/wireless/ath/ath5k/ahb.c
+++ b/drivers/net/wireless/ath/ath5k/ahb.c
@@ -166,7 +166,9 @@ static int ath_ahb_probe(struct platform_device *pdev)
                 if (to_platform_device(ah->dev)->id == 0 &&
                     (bcfg->config->flags & (BD_WLAN0 | BD_WLAN1)) ==
                      (BD_WLAN1 | BD_WLAN0))
-                        __set_bit(ATH_STAT_2G_DISABLED, ah->status);
+                        ah->ah_capabilities.cap_needs_2GHz_ovr = true;
+                else
+                        ah->ah_capabilities.cap_needs_2GHz_ovr = false;
         }
 
         ret = ath5k_init_ah(ah, &ath_ahb_bus_ops);
diff --git a/drivers/net/wireless/ath/ath5k/ani.c b/drivers/net/wireless/ath/ath5k/ani.c
index bea90e6be70e..bf674161a217 100644
--- a/drivers/net/wireless/ath/ath5k/ani.c
+++ b/drivers/net/wireless/ath/ath5k/ani.c
@@ -27,15 +27,21 @@
  * or reducing sensitivity as necessary.
  *
  * The parameters are:
+ *
  *   - "noise immunity"
+ *
  *   - "spur immunity"
+ *
  *   - "firstep level"
+ *
  *   - "OFDM weak signal detection"
+ *
  *   - "CCK weak signal detection"
  *
  * Basically we look at the amount of ODFM and CCK timing errors we get and then
  * raise or lower immunity accordingly by setting one or more of these
  * parameters.
+ *
  * Newer chipsets have PHY error counters in hardware which will generate a MIB
  * interrupt when they overflow. Older hardware has too enable PHY error frames
  * by setting a RX flag and then count every single PHY error. When a specified
@@ -45,11 +51,13 @@
  */
 
 
-/*** ANI parameter control ***/
+/***********************\
+* ANI parameter control *
+\***********************/
 
 /**
  * ath5k_ani_set_noise_immunity_level() - Set noise immunity level
- *
+ * @ah: The &struct ath5k_hw
  * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL
  */
 void
@@ -91,12 +99,11 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
         ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
 }
 
-
 /**
  * ath5k_ani_set_spur_immunity_level() - Set spur immunity level
- *
+ * @ah: The &struct ath5k_hw
  * @level: level between 0 and @max_spur_level (the maximum level is dependent
- *      on the chip revision).
+ * on the chip revision).
  */
 void
 ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
@@ -117,10 +124,9 @@ ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
         ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
 }
 
-
 /**
  * ath5k_ani_set_firstep_level() - Set "firstep" level
- *
+ * @ah: The &struct ath5k_hw
  * @level: level between 0 and @ATH5K_ANI_MAX_FIRSTEP_LVL
  */
 void
@@ -140,11 +146,9 @@ ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
         ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
 }
 
-
 /**
- * ath5k_ani_set_ofdm_weak_signal_detection() - Control OFDM weak signal
- *                                              detection
- *
+ * ath5k_ani_set_ofdm_weak_signal_detection() - Set OFDM weak signal detection
+ * @ah: The &struct ath5k_hw
  * @on: turn on or off
  */
 void
@@ -182,10 +186,9 @@ ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
                           on ? "on" : "off");
 }
 
-
 /**
- * ath5k_ani_set_cck_weak_signal_detection() - control CCK weak signal detection
- *
+ * ath5k_ani_set_cck_weak_signal_detection() - Set CCK weak signal detection
+ * @ah: The &struct ath5k_hw
  * @on: turn on or off
  */
 void
@@ -200,13 +203,16 @@ ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on)
 }
 
 
-/*** ANI algorithm ***/
+/***************\
+* ANI algorithm *
+\***************/
 
 /**
  * ath5k_ani_raise_immunity() - Increase noise immunity
- *
+ * @ah: The &struct ath5k_hw
+ * @as: The &struct ath5k_ani_state
  * @ofdm_trigger: If this is true we are called because of too many OFDM errors,
- *      the algorithm will tune more parameters then.
+ * the algorithm will tune more parameters then.
  *
  * Try to raise noise immunity (=decrease sensitivity) in several steps
  * depending on the average RSSI of the beacons we received.
@@ -290,9 +296,10 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
         */
 }
 
-
 /**
  * ath5k_ani_lower_immunity() - Decrease noise immunity
+ * @ah: The &struct ath5k_hw
+ * @as: The &struct ath5k_ani_state
  *
  * Try to lower noise immunity (=increase sensitivity) in several steps
  * depending on the average RSSI of the beacons we received.
@@ -352,9 +359,10 @@ ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
         }
 }
 
-
 /**
  * ath5k_hw_ani_get_listen_time() - Update counters and return listening time
+ * @ah: The &struct ath5k_hw
+ * @as: The &struct ath5k_ani_state
  *
  * Return an approximation of the time spent "listening" in milliseconds (ms)
  * since the last call of this function.
@@ -379,9 +387,10 @@ ath5k_hw_ani_get_listen_time(struct ath5k_hw *ah, struct ath5k_ani_state *as)
         return listen;
 }
 
-
 /**
  * ath5k_ani_save_and_clear_phy_errors() - Clear and save PHY error counters
+ * @ah: The &struct ath5k_hw
+ * @as: The &struct ath5k_ani_state
  *
  * Clear the PHY error counters as soon as possible, since this might be called
  * from a MIB interrupt and we want to make sure we don't get interrupted again.
@@ -429,14 +438,14 @@ ath5k_ani_save_and_clear_phy_errors(struct ath5k_hw *ah,
         return 1;
 }
 
-
 /**
  * ath5k_ani_period_restart() - Restart ANI period
+ * @as: The &struct ath5k_ani_state
  *
  * Just reset counters, so they are clear for the next "ani period".
  */
 static void
-ath5k_ani_period_restart(struct ath5k_hw *ah, struct ath5k_ani_state *as)
+ath5k_ani_period_restart(struct ath5k_ani_state *as)
 {
         /* keep last values for debugging */
         as->last_ofdm_errors = as->ofdm_errors;
@@ -448,9 +457,9 @@ ath5k_ani_period_restart(struct ath5k_hw *ah, struct ath5k_ani_state *as)
         as->listen_time = 0;
 }
 
-
 /**
  * ath5k_ani_calibration() - The main ANI calibration function
+ * @ah: The &struct ath5k_hw
  *
  * We count OFDM and CCK errors relative to the time where we did not send or
  * receive ("listen" time) and raise or lower immunity accordingly.
@@ -492,7 +501,7 @@ ath5k_ani_calibration(struct ath5k_hw *ah)
                 /* too many PHY errors - we have to raise immunity */
                 bool ofdm_flag = as->ofdm_errors > ofdm_high ? true : false;
                 ath5k_ani_raise_immunity(ah, as, ofdm_flag);
-                ath5k_ani_period_restart(ah, as);
+                ath5k_ani_period_restart(as);
 
         } else if (as->listen_time > 5 * ATH5K_ANI_LISTEN_PERIOD) {
                 /* If more than 5 (TODO: why 5?) periods have passed and we got
@@ -504,15 +513,18 @@ ath5k_ani_calibration(struct ath5k_hw *ah)
                 if (as->ofdm_errors <= ofdm_low && as->cck_errors <= cck_low)
                         ath5k_ani_lower_immunity(ah, as);
 
-                ath5k_ani_period_restart(ah, as);
+                ath5k_ani_period_restart(as);
         }
 }
 
 
-/*** INTERRUPT HANDLER ***/
+/*******************\
+* Interrupt handler *
+\*******************/
 
 /**
  * ath5k_ani_mib_intr() - Interrupt handler for ANI MIB counters
+ * @ah: The &struct ath5k_hw
  *
  * Just read & reset the registers quickly, so they don't generate more
  * interrupts, save the counters and schedule the tasklet to decide whether
@@ -549,9 +561,11 @@ ath5k_ani_mib_intr(struct ath5k_hw *ah)
                 tasklet_schedule(&ah->ani_tasklet);
 }
 
-
 /**
- * ath5k_ani_phy_error_report() - Used by older HW to report PHY errors
+ * ath5k_ani_phy_error_report - Used by older HW to report PHY errors
+ *
+ * @ah: The &struct ath5k_hw
+ * @phyerr: One of enum ath5k_phy_error_code
  *
  * This is used by hardware without PHY error counters to report PHY errors
  * on a frame-by-frame basis, instead of the interrupt.
@@ -574,10 +588,13 @@ ath5k_ani_phy_error_report(struct ath5k_hw *ah,
 }
 
 
-/*** INIT ***/
+/****************\
+* Initialization *
+\****************/
 
 /**
  * ath5k_enable_phy_err_counters() - Enable PHY error counters
+ * @ah: The &struct ath5k_hw
  *
  * Enable PHY error counters for OFDM and CCK timing errors.
  */
@@ -596,9 +613,9 @@ ath5k_enable_phy_err_counters(struct ath5k_hw *ah)
         ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
 }
 
-
 /**
  * ath5k_disable_phy_err_counters() - Disable PHY error counters
+ * @ah: The &struct ath5k_hw
  *
  * Disable PHY error counters for OFDM and CCK timing errors.
  */
@@ -615,10 +632,10 @@ ath5k_disable_phy_err_counters(struct ath5k_hw *ah)
         ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
 }
 
-
 /**
  * ath5k_ani_init() - Initialize ANI
- * @mode: Which mode to use (auto, manual high, manual low, off)
+ * @ah: The &struct ath5k_hw
+ * @mode: One of enum ath5k_ani_mode
  *
  * Initialize ANI according to mode.
  */
@@ -695,10 +712,18 @@ ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
 }
 
 
-/*** DEBUG ***/
+/**************\
+* Debug output *
+\**************/
 
 #ifdef CONFIG_ATH5K_DEBUG
 
+/**
+ * ath5k_ani_print_counters() - Print ANI counters
+ * @ah: The &struct ath5k_hw
+ *
+ * Used for debugging ANI
+ */
 void
 ath5k_ani_print_counters(struct ath5k_hw *ah)
 {
diff --git a/drivers/net/wireless/ath/ath5k/ani.h b/drivers/net/wireless/ath/ath5k/ani.h
index 7358b6c83c6c..21aa355460bb 100644
--- a/drivers/net/wireless/ath/ath5k/ani.h
+++ b/drivers/net/wireless/ath/ath5k/ani.h
@@ -40,13 +40,13 @@ enum ath5k_phy_error_code;
  * enum ath5k_ani_mode - mode for ANI / noise sensitivity
  *
  * @ATH5K_ANI_MODE_OFF: Turn ANI off. This can be useful to just stop the ANI
- *      algorithm after it has been on auto mode.
- * ATH5K_ANI_MODE_MANUAL_LOW: Manually set all immunity parameters to low,
- *      maximizing sensitivity. ANI will not run.
- * ATH5K_ANI_MODE_MANUAL_HIGH: Manually set all immunity parameters to high,
- *      minimizing sensitivity. ANI will not run.
- * ATH5K_ANI_MODE_AUTO: Automatically control immunity parameters based on the
- *      amount of OFDM and CCK frame errors (default).
+ *                      algorithm after it has been on auto mode.
+ * @ATH5K_ANI_MODE_MANUAL_LOW: Manually set all immunity parameters to low,
+ *                      maximizing sensitivity. ANI will not run.
+ * @ATH5K_ANI_MODE_MANUAL_HIGH: Manually set all immunity parameters to high,
+ *                      minimizing sensitivity. ANI will not run.
+ * @ATH5K_ANI_MODE_AUTO: Automatically control immunity parameters based on the
+ *                      amount of OFDM and CCK frame errors (default).
  */
 enum ath5k_ani_mode {
         ATH5K_ANI_MODE_OFF              = 0,
@@ -58,8 +58,22 @@ enum ath5k_ani_mode {
 
 /**
  * struct ath5k_ani_state - ANI state and associated counters
- *
- * @max_spur_level: the maximum spur level is chip dependent
+ * @ani_mode: One of enum ath5k_ani_mode
+ * @noise_imm_level: Noise immunity level
+ * @spur_level: Spur immunity level
+ * @firstep_level: FIRstep level
+ * @ofdm_weak_sig: OFDM weak signal detection state (on/off)
+ * @cck_weak_sig: CCK weak signal detection state (on/off)
+ * @max_spur_level: Max spur immunity level (chip specific)
+ * @listen_time: Listen time
+ * @ofdm_errors: OFDM timing error count
+ * @cck_errors: CCK timing error count
+ * @last_cc: The &struct ath_cycle_counters (for stats)
+ * @last_listen: Listen time from previous run (for stats)
+ * @last_ofdm_errors: OFDM timing error count from previous run (for tats)
+ * @last_cck_errors: CCK timing error count from previous run (for stats)
+ * @sum_ofdm_errors: Sum of OFDM timing errors (for stats)
+ * @sum_cck_errors: Sum of all CCK timing errors (for stats)
  */
 struct ath5k_ani_state {
         enum ath5k_ani_mode     ani_mode;
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h
index fecbcd9a4259..e564e585b221 100644
--- a/drivers/net/wireless/ath/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath/ath5k/ath5k.h
@@ -187,10 +187,9 @@
 #define AR5K_TUNE_MAX_TXPOWER                   63
 #define AR5K_TUNE_DEFAULT_TXPOWER               25
 #define AR5K_TUNE_TPC_TXPOWER                   false
-#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL    10000   /* 10 sec */
+#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL    60000   /* 60 sec */
+#define ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT   10000   /* 10 sec */
 #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI     1000    /* 1 sec */
-#define ATH5K_TUNE_CALIBRATION_INTERVAL_NF      60000   /* 60 sec */
-
 #define ATH5K_TX_COMPLETE_POLL_INT              3000    /* 3 sec */
 
 #define AR5K_INIT_CARR_SENSE_EN                 1
@@ -262,16 +261,34 @@
 #define AR5K_AGC_SETTLING_TURBO                 37
 
 
-/* GENERIC CHIPSET DEFINITIONS */
 
-/* MAC Chips */
+/*****************************\
+* GENERIC CHIPSET DEFINITIONS *
+\*****************************/
+
+/**
+ * enum ath5k_version - MAC Chips
+ * @AR5K_AR5210: AR5210 (Crete)
+ * @AR5K_AR5211: AR5211 (Oahu/Maui)
+ * @AR5K_AR5212: AR5212 (Venice) and newer
+ */
 enum ath5k_version {
         AR5K_AR5210     = 0,
         AR5K_AR5211     = 1,
         AR5K_AR5212     = 2,
 };
 
-/* PHY Chips */
+/**
+ * enum ath5k_radio - PHY Chips
+ * @AR5K_RF5110: RF5110 (Fez)
+ * @AR5K_RF5111: RF5111 (Sombrero)
+ * @AR5K_RF5112: RF2112/5112(A) (Derby/Derby2)
+ * @AR5K_RF2413: RF2413/2414 (Griffin/Griffin-Lite)
+ * @AR5K_RF5413: RF5413/5414/5424 (Eagle/Condor)
+ * @AR5K_RF2316: RF2315/2316 (Cobra SoC)
+ * @AR5K_RF2317: RF2317 (Spider SoC)
+ * @AR5K_RF2425: RF2425/2417 (Swan/Nalla)
+ */
 enum ath5k_radio {
         AR5K_RF5110     = 0,
         AR5K_RF5111     = 1,
@@ -303,11 +320,11 @@ enum ath5k_radio {
 #define AR5K_SREV_AR5213A       0x59 /* Hainan */
 #define AR5K_SREV_AR2413        0x78 /* Griffin lite */
 #define AR5K_SREV_AR2414        0x70 /* Griffin */
-#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
-#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
+#define AR5K_SREV_AR2315_R6     0x86 /* AP51-Light */
+#define AR5K_SREV_AR2315_R7     0x87 /* AP51-Full */
 #define AR5K_SREV_AR5424        0x90 /* Condor */
-#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
-#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
+#define AR5K_SREV_AR2317_R1     0x90 /* AP61-Light */
+#define AR5K_SREV_AR2317_R2     0x91 /* AP61-Full */
 #define AR5K_SREV_AR5413        0xa4 /* Eagle lite */
 #define AR5K_SREV_AR5414        0xa0 /* Eagle */
 #define AR5K_SREV_AR2415        0xb0 /* Talon */
@@ -344,32 +361,40 @@ enum ath5k_radio {
 
 /* TODO add support to mac80211 for vendor-specific rates and modes */
 
-/*
+/**
+ * DOC: Atheros XR
+ *
  * Some of this information is based on Documentation from:
  *
  * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
  *
- * Modulation for Atheros' eXtended Range - range enhancing extension that is
- * supposed to double the distance an Atheros client device can keep a
- * connection with an Atheros access point. This is achieved by increasing
- * the receiver sensitivity up to, -105dBm, which is about 20dB above what
- * the 802.11 specifications demand. In addition, new (proprietary) data rates
- * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
+ * Atheros' eXtended Range - range enhancing extension is a modulation scheme
+ * that is supposed to double the link distance between an Atheros XR-enabled
+ * client device with an Atheros XR-enabled access point. This is achieved
+ * by increasing the receiver sensitivity up to, -105dBm, which is about 20dB
+ * above what the 802.11 specifications demand. In addition, new (proprietary)
+ * data rates are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
  *
  * Please note that can you either use XR or TURBO but you cannot use both,
  * they are exclusive.
  *
+ * Also note that we do not plan to support XR mode at least for now. You can
+ * get a mode similar to XR by using 5MHz bwmode.
  */
-#define MODULATION_XR           0x00000200
-/*
- * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
- * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
- * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
- * channels. To use this feature your Access Point must also support it.
+
+
+/**
+ * DOC: Atheros SuperAG
+ *
+ * In addition to XR we have another modulation scheme called TURBO mode
+ * that is supposed to provide a throughput transmission speed up to 40Mbit/s
+ * -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two
+ * 54Mbit/s 802.11g channels. To use this feature both ends must support it.
  * There is also a distinction between "static" and "dynamic" turbo modes:
  *
  * - Static: is the dumb version: devices set to this mode stick to it until
  *     the mode is turned off.
+ *
  * - Dynamic: is the intelligent version, the network decides itself if it
  *     is ok to use turbo. As soon as traffic is detected on adjacent channels
  *     (which would get used in turbo mode), or when a non-turbo station joins
@@ -383,24 +408,39 @@ enum ath5k_radio {
  *
  * http://www.pcworld.com/article/id,113428-page,1/article.html
  *
- * The channel bonding seems to be driver specific though. In addition to
- * deciding what channels will be used, these "Turbo" modes are accomplished
- * by also enabling the following features:
+ * The channel bonding seems to be driver specific though.
+ *
+ * In addition to TURBO modes we also have the following features for even
+ * greater speed-up:
  *
  * - Bursting: allows multiple frames to be sent at once, rather than pausing
  *     after each frame. Bursting is a standards-compliant feature that can be
  *     used with any Access Point.
+ *
  * - Fast frames: increases the amount of information that can be sent per
  *     frame, also resulting in a reduction of transmission overhead. It is a
  *     proprietary feature that needs to be supported by the Access Point.
+ *
  * - Compression: data frames are compressed in real time using a Lempel Ziv
  *     algorithm. This is done transparently. Once this feature is enabled,
  *     compression and decompression takes place inside the chipset, without
  *     putting additional load on the host CPU.
  *
+ * As with XR we also don't plan to support SuperAG features for now. You can
+ * get a mode similar to TURBO by using 40MHz bwmode.
  */
-#define MODULATION_TURBO        0x00000080
 
+
+/**
+ * enum ath5k_driver_mode - PHY operation mode
+ * @AR5K_MODE_11A: 802.11a
+ * @AR5K_MODE_11B: 802.11b
+ * @AR5K_MODE_11G: 801.11g
+ * @AR5K_MODE_MAX: Used for boundary checks
+ *
+ * Do not change the order here, we use these as
+ * array indices and it also maps EEPROM structures.
+ */
 enum ath5k_driver_mode {
         AR5K_MODE_11A           =       0,
         AR5K_MODE_11B           =       1,
@@ -408,30 +448,64 @@ enum ath5k_driver_mode {
         AR5K_MODE_MAX           =       3
 };
 
+/**
+ * enum ath5k_ant_mode - Antenna operation mode
+ * @AR5K_ANTMODE_DEFAULT: Default antenna setup
+ * @AR5K_ANTMODE_FIXED_A: Only antenna A is present
+ * @AR5K_ANTMODE_FIXED_B: Only antenna B is present
+ * @AR5K_ANTMODE_SINGLE_AP: STA locked on a single ap
+ * @AR5K_ANTMODE_SECTOR_AP: AP with tx antenna set on tx desc
+ * @AR5K_ANTMODE_SECTOR_STA: STA with tx antenna set on tx desc
+ * @AR5K_ANTMODE_DEBUG: Debug mode -A -> Rx, B-> Tx-
+ * @AR5K_ANTMODE_MAX: Used for boundary checks
+ *
+ * For more infos on antenna control check out phy.c
+ */
 enum ath5k_ant_mode {
-        AR5K_ANTMODE_DEFAULT    = 0,    /* default antenna setup */
-        AR5K_ANTMODE_FIXED_A    = 1,    /* only antenna A is present */
-        AR5K_ANTMODE_FIXED_B    = 2,    /* only antenna B is present */
-        AR5K_ANTMODE_SINGLE_AP  = 3,    /* sta locked on a single ap */
-        AR5K_ANTMODE_SECTOR_AP  = 4,    /* AP with tx antenna set on tx desc */
-        AR5K_ANTMODE_SECTOR_STA = 5,    /* STA with tx antenna set on tx desc */
-        AR5K_ANTMODE_DEBUG      = 6,    /* Debug mode -A -> Rx, B-> Tx- */
+        AR5K_ANTMODE_DEFAULT    = 0,
+        AR5K_ANTMODE_FIXED_A    = 1,
+        AR5K_ANTMODE_FIXED_B    = 2,
+        AR5K_ANTMODE_SINGLE_AP  = 3,
+        AR5K_ANTMODE_SECTOR_AP  = 4,
+        AR5K_ANTMODE_SECTOR_STA = 5,
+        AR5K_ANTMODE_DEBUG      = 6,
         AR5K_ANTMODE_MAX,
 };
 
+/**
+ * enum ath5k_bw_mode - Bandwidth operation mode
+ * @AR5K_BWMODE_DEFAULT: 20MHz, default operation
+ * @AR5K_BWMODE_5MHZ: Quarter rate
+ * @AR5K_BWMODE_10MHZ: Half rate
+ * @AR5K_BWMODE_40MHZ: Turbo
+ */
 enum ath5k_bw_mode {
-        AR5K_BWMODE_DEFAULT     = 0,    /* 20MHz, default operation */
-        AR5K_BWMODE_5MHZ        = 1,    /* Quarter rate */
-        AR5K_BWMODE_10MHZ       = 2,    /* Half rate */
-        AR5K_BWMODE_40MHZ       = 3     /* Turbo */
+        AR5K_BWMODE_DEFAULT     = 0,
+        AR5K_BWMODE_5MHZ        = 1,
+        AR5K_BWMODE_10MHZ       = 2,
+        AR5K_BWMODE_40MHZ       = 3
 };
 
+
+
 /****************\
   TX DEFINITIONS
 \****************/
 
-/*
- * TX Status descriptor
+/**
+ * struct ath5k_tx_status - TX Status descriptor
+ * @ts_seqnum: Sequence number
+ * @ts_tstamp: Timestamp
+ * @ts_status: Status code
+ * @ts_final_idx: Final transmission series index
+ * @ts_final_retry: Final retry count
+ * @ts_rssi: RSSI for received ACK
+ * @ts_shortretry: Short retry count
+ * @ts_virtcol: Virtual collision count
+ * @ts_antenna: Antenna used
+ *
+ * TX status descriptor gets filled by the hw
+ * on each transmission attempt.
  */
 struct ath5k_tx_status {
         u16     ts_seqnum;
@@ -454,7 +528,6 @@ struct ath5k_tx_status {
  * enum ath5k_tx_queue - Queue types used to classify tx queues.
  * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
  * @AR5K_TX_QUEUE_DATA: A normal data queue
- * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
  * @AR5K_TX_QUEUE_BEACON: The beacon queue
  * @AR5K_TX_QUEUE_CAB: The after-beacon queue
  * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
@@ -462,7 +535,6 @@ struct ath5k_tx_status {
 enum ath5k_tx_queue {
         AR5K_TX_QUEUE_INACTIVE = 0,
         AR5K_TX_QUEUE_DATA,
-        AR5K_TX_QUEUE_XR_DATA,
         AR5K_TX_QUEUE_BEACON,
         AR5K_TX_QUEUE_CAB,
         AR5K_TX_QUEUE_UAPSD,
@@ -471,36 +543,46 @@ enum ath5k_tx_queue {
 #define AR5K_NUM_TX_QUEUES              10
 #define AR5K_NUM_TX_QUEUES_NOQCU        2
 
-/*
- * Queue syb-types to classify normal data queues.
+/**
+ * enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues
+ * @AR5K_WME_AC_BK: Background traffic
+ * @AR5K_WME_AC_BE: Best-effort (normal) traffic
+ * @AR5K_WME_AC_VI: Video traffic
+ * @AR5K_WME_AC_VO: Voice traffic
+ *
  * These are the 4 Access Categories as defined in
  * WME spec. 0 is the lowest priority and 4 is the
  * highest. Normal data that hasn't been classified
  * goes to the Best Effort AC.
  */
 enum ath5k_tx_queue_subtype {
-        AR5K_WME_AC_BK = 0,     /*Background traffic*/
-        AR5K_WME_AC_BE,         /*Best-effort (normal) traffic*/
-        AR5K_WME_AC_VI,         /*Video traffic*/
-        AR5K_WME_AC_VO,         /*Voice traffic*/
+        AR5K_WME_AC_BK = 0,
+        AR5K_WME_AC_BE,
+        AR5K_WME_AC_VI,
+        AR5K_WME_AC_VO,
 };
 
-/*
- * Queue ID numbers as returned by the hw functions, each number
- * represents a hw queue. If hw does not support hw queues
- * (eg 5210) all data goes in one queue. These match
- * d80211 definitions (net80211/MadWiFi don't use them).
+/**
+ * enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions
+ * @AR5K_TX_QUEUE_ID_NOQCU_DATA: Data queue on AR5210 (no QCU available)
+ * @AR5K_TX_QUEUE_ID_NOQCU_BEACON: Beacon queue on AR5210 (no QCU available)
+ * @AR5K_TX_QUEUE_ID_DATA_MIN: Data queue min index
+ * @AR5K_TX_QUEUE_ID_DATA_MAX: Data queue max index
+ * @AR5K_TX_QUEUE_ID_CAB: Content after beacon queue
+ * @AR5K_TX_QUEUE_ID_BEACON: Beacon queue
+ * @AR5K_TX_QUEUE_ID_UAPSD: Urgent Automatic Power Save Delivery,
+ *
+ * Each number represents a hw queue. If hw does not support hw queues
+ * (eg 5210) all data goes in one queue.
  */
 enum ath5k_tx_queue_id {
         AR5K_TX_QUEUE_ID_NOQCU_DATA     = 0,
         AR5K_TX_QUEUE_ID_NOQCU_BEACON   = 1,
-        AR5K_TX_QUEUE_ID_DATA_MIN       = 0, /*IEEE80211_TX_QUEUE_DATA0*/
-        AR5K_TX_QUEUE_ID_DATA_MAX       = 3, /*IEEE80211_TX_QUEUE_DATA3*/
-        AR5K_TX_QUEUE_ID_DATA_SVP       = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
-        AR5K_TX_QUEUE_ID_CAB            = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
-        AR5K_TX_QUEUE_ID_BEACON         = 7, /*IEEE80211_TX_QUEUE_BEACON*/
-        AR5K_TX_QUEUE_ID_UAPSD          = 8,
-        AR5K_TX_QUEUE_ID_XR_DATA        = 9,
+        AR5K_TX_QUEUE_ID_DATA_MIN       = 0,
+        AR5K_TX_QUEUE_ID_DATA_MAX       = 3,
+        AR5K_TX_QUEUE_ID_UAPSD          = 7,
+        AR5K_TX_QUEUE_ID_CAB            = 8,
+        AR5K_TX_QUEUE_ID_BEACON         = 9,
 };
 
 /*
@@ -521,46 +603,70 @@ enum ath5k_tx_queue_id {
 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS         0x1000  /* Disable backoff while bursting */
 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE        0x2000  /* Enable hw compression -not implemented-*/
 
-/*
- * Data transmit queue state.  One of these exists for each
- * hardware transmit queue.  Packets sent to us from above
- * are assigned to queues based on their priority.  Not all
- * devices support a complete set of hardware transmit queues.
- * For those devices the array sc_ac2q will map multiple
- * priorities to fewer hardware queues (typically all to one
- * hardware queue).
+/**
+ * struct ath5k_txq - Transmit queue state
+ * @qnum: Hardware q number
+ * @link: Link ptr in last TX desc
+ * @q: Transmit queue (&struct list_head)
+ * @lock: Lock on q and link
+ * @setup: Is the queue configured
+ * @txq_len:Number of queued buffers
+ * @txq_max: Max allowed num of queued buffers
+ * @txq_poll_mark: Used to check if queue got stuck
+ * @txq_stuck: Queue stuck counter
+ *
+ * One of these exists for each hardware transmit queue.
+ * Packets sent to us from above are assigned to queues based
+ * on their priority.  Not all devices support a complete set
+ * of hardware transmit queues. For those devices the array
+ * sc_ac2q will map multiple priorities to fewer hardware queues
+ * (typically all to one hardware queue).
  */
 struct ath5k_txq {
-        unsigned int            qnum;   /* hardware q number */
-        u32                     *link;  /* link ptr in last TX desc */
-        struct list_head        q;      /* transmit queue */
-        spinlock_t              lock;   /* lock on q and link */
+        unsigned int            qnum;
+        u32                     *link;
+        struct list_head        q;
+        spinlock_t              lock;
         bool                    setup;
-        int                     txq_len; /* number of queued buffers */
-        int                     txq_max; /* max allowed num of queued buffers */
+        int                     txq_len;
+        int                     txq_max;
         bool                    txq_poll_mark;
-        unsigned int            txq_stuck;      /* informational counter */
+        unsigned int            txq_stuck;
 };
 
-/*
- * A struct to hold tx queue's parameters
+/**
+ * struct ath5k_txq_info - A struct to hold TX queue's parameters
+ * @tqi_type: One of enum ath5k_tx_queue
+ * @tqi_subtype: One of enum ath5k_tx_queue_subtype
+ * @tqi_flags: TX queue flags (see above)
+ * @tqi_aifs: Arbitrated Inter-frame Space
+ * @tqi_cw_min: Minimum Contention Window
+ * @tqi_cw_max: Maximum Contention Window
+ * @tqi_cbr_period: Constant bit rate period
+ * @tqi_ready_time: Time queue waits after an event when RDYTIME is enabled
  */
 struct ath5k_txq_info {
         enum ath5k_tx_queue tqi_type;
         enum ath5k_tx_queue_subtype tqi_subtype;
-        u16     tqi_flags;      /* Tx queue flags (see above) */
-        u8      tqi_aifs;       /* Arbitrated Interframe Space */
-        u16     tqi_cw_min;     /* Minimum Contention Window */
-        u16     tqi_cw_max;     /* Maximum Contention Window */
-        u32     tqi_cbr_period; /* Constant bit rate period */
+        u16     tqi_flags;
+        u8      tqi_aifs;
+        u16     tqi_cw_min;
+        u16     tqi_cw_max;
+        u32     tqi_cbr_period;
         u32     tqi_cbr_overflow_limit;
         u32     tqi_burst_time;
-        u32     tqi_ready_time; /* Time queue waits after an event */
+        u32     tqi_ready_time;
 };
 
-/*
- * Transmit packet types.
- * used on tx control descriptor
+/**
+ * enum ath5k_pkt_type - Transmit packet types
+ * @AR5K_PKT_TYPE_NORMAL: Normal data
+ * @AR5K_PKT_TYPE_ATIM: ATIM
+ * @AR5K_PKT_TYPE_PSPOLL: PS-Poll
+ * @AR5K_PKT_TYPE_BEACON: Beacon
+ * @AR5K_PKT_TYPE_PROBE_RESP: Probe response
+ * @AR5K_PKT_TYPE_PIFS: PIFS
+ * Used on tx control descriptor
  */
 enum ath5k_pkt_type {
         AR5K_PKT_TYPE_NORMAL            = 0,
@@ -583,27 +689,23 @@ enum ath5k_pkt_type {
         (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v)     \
 )
 
-/*
- * DMA size definitions (2^(n+2))
- */
-enum ath5k_dmasize {
-        AR5K_DMASIZE_4B = 0,
-        AR5K_DMASIZE_8B,
-        AR5K_DMASIZE_16B,
-        AR5K_DMASIZE_32B,
-        AR5K_DMASIZE_64B,
-        AR5K_DMASIZE_128B,
-        AR5K_DMASIZE_256B,
-        AR5K_DMASIZE_512B
-};
 
 
 /****************\
   RX DEFINITIONS
 \****************/
 
-/*
- * RX Status descriptor
+/**
+ * struct ath5k_rx_status - RX Status descriptor
+ * @rs_datalen: Data length
+ * @rs_tstamp: Timestamp
+ * @rs_status: Status code
+ * @rs_phyerr: PHY error mask
+ * @rs_rssi: RSSI in 0.5dbm units
+ * @rs_keyix: Index to the key used for decrypting
+ * @rs_rate: Rate used to decode the frame
+ * @rs_antenna: Antenna used to receive the frame
+ * @rs_more: Indicates this is a frame fragment (Fast frames)
  */
 struct ath5k_rx_status {
         u16     rs_datalen;
@@ -645,10 +747,18 @@ struct ath5k_rx_status {
 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
 
 
+
 /*******************************\
   GAIN OPTIMIZATION DEFINITIONS
 \*******************************/
 
+/**
+ * enum ath5k_rfgain - RF Gain optimization engine state
+ * @AR5K_RFGAIN_INACTIVE: Engine disabled
+ * @AR5K_RFGAIN_ACTIVE: Probe active
+ * @AR5K_RFGAIN_READ_REQUESTED: Probe requested
+ * @AR5K_RFGAIN_NEED_CHANGE: Gain_F needs change
+ */
 enum ath5k_rfgain {
         AR5K_RFGAIN_INACTIVE = 0,
         AR5K_RFGAIN_ACTIVE,
@@ -656,6 +766,16 @@ enum ath5k_rfgain {
         AR5K_RFGAIN_NEED_CHANGE,
 };
 
+/**
+ * struct ath5k_gain - RF Gain optimization engine state data
+ * @g_step_idx: Current step index
+ * @g_current: Current gain
+ * @g_target: Target gain
+ * @g_low: Low gain boundary
+ * @g_high: High gain boundary
+ * @g_f_corr: Gain_F correction
+ * @g_state: One of enum ath5k_rfgain
+ */
 struct ath5k_gain {
         u8                      g_step_idx;
         u8                      g_current;
@@ -666,6 +786,8 @@ struct ath5k_gain {
         u8                      g_state;
 };
 
+
+
 /********************\
   COMMON DEFINITIONS
 \********************/
@@ -674,9 +796,14 @@ struct ath5k_gain {
 #define AR5K_SLOT_TIME_20       880
 #define AR5K_SLOT_TIME_MAX      0xffff
 
-/*
- * The following structure is used to map 2GHz channels to
- * 5GHz Atheros channels.
+/**
+ * struct ath5k_athchan_2ghz - 2GHz to 5GHZ map for RF5111
+ * @a2_flags: Channel flags (internal)
+ * @a2_athchan: HW channel number (internal)
+ *
+ * This structure is used to map 2GHz channels to
+ * 5GHz Atheros channels on 2111 frequency converter
+ * that comes together with RF5111
  * TODO: Clean up
  */
 struct ath5k_athchan_2ghz {
@@ -684,36 +811,80 @@ struct ath5k_athchan_2ghz {
         u16     a2_athchan;
 };
 
+/**
+ * enum ath5k_dmasize -  DMA size definitions (2^(n+2))
+ * @AR5K_DMASIZE_4B: 4Bytes
+ * @AR5K_DMASIZE_8B: 8Bytes
+ * @AR5K_DMASIZE_16B: 16Bytes
+ * @AR5K_DMASIZE_32B: 32Bytes
+ * @AR5K_DMASIZE_64B: 64Bytes (Default)
+ * @AR5K_DMASIZE_128B: 128Bytes
+ * @AR5K_DMASIZE_256B: 256Bytes
+ * @AR5K_DMASIZE_512B: 512Bytes
+ *
+ * These are used to set DMA burst size on hw
+ *
+ * Note: Some platforms can't handle more than 4Bytes
+ * be careful on embedded boards.
+ */
+enum ath5k_dmasize {
+        AR5K_DMASIZE_4B = 0,
+        AR5K_DMASIZE_8B,
+        AR5K_DMASIZE_16B,
+        AR5K_DMASIZE_32B,
+        AR5K_DMASIZE_64B,
+        AR5K_DMASIZE_128B,
+        AR5K_DMASIZE_256B,
+        AR5K_DMASIZE_512B
+};
+
+
 
 /******************\
   RATE DEFINITIONS
 \******************/
 
 /**
+ * DOC: Rate codes
+ *
  * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
  *
  * The rate code is used to get the RX rate or set the TX rate on the
  * hardware descriptors. It is also used for internal modulation control
  * and settings.
  *
- * This is the hardware rate map we are aware of:
- *
- * rate_code   0x01    0x02    0x03    0x04    0x05    0x06    0x07    0x08
- * rate_kbps   3000    1000    ?       ?       ?       2000    500     48000
- *
- * rate_code   0x09    0x0A    0x0B    0x0C    0x0D    0x0E    0x0F    0x10
- * rate_kbps   24000   12000   6000    54000   36000   18000   9000    ?
+ * This is the hardware rate map we are aware of (html unfriendly):
  *
- * rate_code   17      18      19      20      21      22      23      24
- * rate_kbps   ?       ?       ?       ?       ?       ?       ?       11000
+ * Rate code    Rate (Kbps)
+ * ---------    -----------
+ * 0x01          3000 (XR)
+ * 0x02          1000 (XR)
+ * 0x03           250 (XR)
+ * 0x04 - 05    -Reserved-
+ * 0x06          2000 (XR)
+ * 0x07           500 (XR)
+ * 0x08         48000 (OFDM)
+ * 0x09         24000 (OFDM)
+ * 0x0A         12000 (OFDM)
+ * 0x0B          6000 (OFDM)
+ * 0x0C         54000 (OFDM)
+ * 0x0D         36000 (OFDM)
+ * 0x0E         18000 (OFDM)
+ * 0x0F          9000 (OFDM)
+ * 0x10 - 17    -Reserved-
+ * 0x18         11000L (CCK)
+ * 0x19          5500L (CCK)
+ * 0x1A          2000L (CCK)
+ * 0x1B          1000L (CCK)
+ * 0x1C         11000S (CCK)
+ * 0x1D          5500S (CCK)
+ * 0x1E          2000S (CCK)
+ * 0x1F         -Reserved-
  *
- * rate_code   25      26      27      28      29      30      31      32
- * rate_kbps   5500    2000    1000    11000S  5500S   2000S   ?       ?
- *
- * "S" indicates CCK rates with short preamble.
+ * "S" indicates CCK rates with short preamble and "L" with long preamble.
  *
  * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
- * lowest 4 bits, so they are the same as below with a 0xF mask.
+ * lowest 4 bits, so they are the same as above with a 0xF mask.
  * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
  * We handle this in ath5k_setup_bands().
  */
@@ -733,13 +904,9 @@ struct ath5k_athchan_2ghz {
 #define ATH5K_RATE_CODE_36M     0x0D
 #define ATH5K_RATE_CODE_48M     0x08
 #define ATH5K_RATE_CODE_54M     0x0C
-/* XR */
-#define ATH5K_RATE_CODE_XR_500K 0x07
-#define ATH5K_RATE_CODE_XR_1M   0x02
-#define ATH5K_RATE_CODE_XR_2M   0x06
-#define ATH5K_RATE_CODE_XR_3M   0x01
 
-/* adding this flag to rate_code enables short preamble */
+/* Adding this flag to rate_code on B rates
+ * enables short preamble */
 #define AR5K_SET_SHORT_PREAMBLE 0x04
 
 /*
@@ -769,49 +936,65 @@ extern int ath5k_modparam_nohwcrypt;
 
 /**
  * enum ath5k_int - Hardware interrupt masks helpers
+ * @AR5K_INT_RXOK: Frame successfully received
+ * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor
+ * @AR5K_INT_RXERR: Frame reception failed
+ * @AR5K_INT_RXNOFRM: No frame received within a specified time period
+ * @AR5K_INT_RXEOL: Reached "End Of List", means we need more RX descriptors
+ * @AR5K_INT_RXORN: Indicates we got RX FIFO overrun. Note that Rx overrun is
+ *              not always fatal, on some chips we can continue operation
+ *              without resetting the card, that's why %AR5K_INT_FATAL is not
+ *              common for all chips.
+ * @AR5K_INT_RX_ALL: Mask to identify all RX related interrupts
+ *
+ * @AR5K_INT_TXOK: Frame transmission success
+ * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor
+ * @AR5K_INT_TXERR: Frame transmission failure
+ * @AR5K_INT_TXEOL: Received End Of List for VEOL (Virtual End Of List). The
+ *              Queue Control Unit (QCU) signals an EOL interrupt only if a
+ *              descriptor's LinkPtr is NULL. For more details, refer to:
+ *              "http://www.freepatentsonline.com/20030225739.html"
+ * @AR5K_INT_TXNOFRM: No frame was transmitted within a specified time period
+ * @AR5K_INT_TXURN: Indicates we got TX FIFO underrun. In such case we should
+ *              increase the TX trigger threshold.
+ * @AR5K_INT_TX_ALL: Mask to identify all TX related interrupts
  *
- * @AR5K_INT_RX: mask to identify received frame interrupts, of type
- *      AR5K_ISR_RXOK or AR5K_ISR_RXERR
- * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
- * @AR5K_INT_RXNOFRM: No frame received (?)
- * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
- *      Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
- *      LinkPtr is NULL. For more details, refer to:
- *      http://www.freepatentsonline.com/20030225739.html
- * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
- *      Note that Rx overrun is not always fatal, on some chips we can continue
- *      operation without resetting the card, that's why int_fatal is not
- *      common for all chips.
- * @AR5K_INT_TX: mask to identify received frame interrupts, of type
- *      AR5K_ISR_TXOK or AR5K_ISR_TXERR
- * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
- * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
- *      We currently do increments on interrupt by
- *      (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
  * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
- *      one of the PHY error counters reached the maximum value and should be
- *      read and cleared.
+ *              one of the PHY error counters reached the maximum value and
+ *              should be read and cleared.
+ * @AR5K_INT_SWI: Software triggered interrupt.
  * @AR5K_INT_RXPHY: RX PHY Error
  * @AR5K_INT_RXKCM: RX Key cache miss
  * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
- *      beacon that must be handled in software. The alternative is if you
- *      have VEOL support, in that case you let the hardware deal with things.
+ *              beacon that must be handled in software. The alternative is if
+ *              you have VEOL support, in that case you let the hardware deal
+ *              with things.
+ * @AR5K_INT_BRSSI: Beacon received with an RSSI value below our threshold
  * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
- *      beacons from the AP have associated with, we should probably try to
- *      reassociate. When in IBSS mode this might mean we have not received
- *      any beacons from any local stations. Note that every station in an
- *      IBSS schedules to send beacons at the Target Beacon Transmission Time
- *      (TBTT) with a random backoff.
- * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
- * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
- *      until properly handled
- * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
- *      errors. These types of errors we can enable seem to be of type
- *      AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
+ *              beacons from the AP have associated with, we should probably
+ *              try to reassociate. When in IBSS mode this might mean we have
+ *              not received any beacons from any local stations. Note that
+ *              every station in an IBSS schedules to send beacons at the
+ *              Target Beacon Transmission Time (TBTT) with a random backoff.
+ * @AR5K_INT_BNR: Beacon queue got triggered (DMA beacon alert) while empty.
+ * @AR5K_INT_TIM: Beacon with local station's TIM bit set
+ * @AR5K_INT_DTIM: Beacon with DTIM bit and zero DTIM count received
+ * @AR5K_INT_DTIM_SYNC: DTIM sync lost
+ * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill switches connected to
+ *              our GPIO pins.
+ * @AR5K_INT_BCN_TIMEOUT: Beacon timeout, we waited after TBTT but got noting
+ * @AR5K_INT_CAB_TIMEOUT: We waited for CAB traffic after the beacon but got
+ *              nothing or an incomplete CAB frame sequence.
+ * @AR5K_INT_QCBRORN: A queue got it's CBR counter expired
+ * @AR5K_INT_QCBRURN: A queue got triggered wile empty
+ * @AR5K_INT_QTRIG: A queue got triggered
+ *
+ * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by bus/DMA
+ *              errors. Indicates we need to reset the card.
  * @AR5K_INT_GLOBAL: Used to clear and set the IER
- * @AR5K_INT_NOCARD: signals the card has been removed
- * @AR5K_INT_COMMON: common interrupts shared among MACs with the same
- *      bit value
+ * @AR5K_INT_NOCARD: Signals the card has been removed
+ * @AR5K_INT_COMMON: Common interrupts shared among MACs with the same
+ *              bit value
  *
  * These are mapped to take advantage of some common bits
  * between the MACs, to be able to set intr properties
@@ -847,15 +1030,15 @@ enum ath5k_int {
         AR5K_INT_GPIO   =       0x01000000,
         AR5K_INT_BCN_TIMEOUT =  0x02000000, /* Non common */
         AR5K_INT_CAB_TIMEOUT =  0x04000000, /* Non common */
-        AR5K_INT_RX_DOPPLER =   0x08000000, /* Non common */
-        AR5K_INT_QCBRORN =      0x10000000, /* Non common */
-        AR5K_INT_QCBRURN =      0x20000000, /* Non common */
-        AR5K_INT_QTRIG  =       0x40000000, /* Non common */
+        AR5K_INT_QCBRORN =      0x08000000, /* Non common */
+        AR5K_INT_QCBRURN =      0x10000000, /* Non common */
+        AR5K_INT_QTRIG  =       0x20000000, /* Non common */
         AR5K_INT_GLOBAL =       0x80000000,
 
         AR5K_INT_TX_ALL = AR5K_INT_TXOK
                 | AR5K_INT_TXDESC
                 | AR5K_INT_TXERR
+                | AR5K_INT_TXNOFRM
                 | AR5K_INT_TXEOL
                 | AR5K_INT_TXURN,
 
@@ -891,15 +1074,32 @@ enum ath5k_int {
         AR5K_INT_NOCARD = 0xffffffff
 };
 
-/* mask which calibration is active at the moment */
+/**
+ * enum ath5k_calibration_mask - Mask which calibration is active at the moment
+ * @AR5K_CALIBRATION_FULL: Full calibration (AGC + SHORT)
+ * @AR5K_CALIBRATION_SHORT: Short calibration (NF + I/Q)
+ * @AR5K_CALIBRATION_NF: Noise Floor calibration
+ * @AR5K_CALIBRATION_ANI: Adaptive Noise Immunity
+ */
 enum ath5k_calibration_mask {
         AR5K_CALIBRATION_FULL = 0x01,
         AR5K_CALIBRATION_SHORT = 0x02,
-        AR5K_CALIBRATION_ANI = 0x04,
+        AR5K_CALIBRATION_NF = 0x04,
+        AR5K_CALIBRATION_ANI = 0x08,
 };
 
-/*
- * Power management
+/**
+ * enum ath5k_power_mode - Power management modes
+ * @AR5K_PM_UNDEFINED: Undefined
+ * @AR5K_PM_AUTO: Allow card to sleep if possible
+ * @AR5K_PM_AWAKE: Force card to wake up
+ * @AR5K_PM_FULL_SLEEP: Force card to full sleep (DANGEROUS)
+ * @AR5K_PM_NETWORK_SLEEP: Allow to sleep for a specified duration
+ *
+ * Currently only PM_AWAKE is used, FULL_SLEEP and NETWORK_SLEEP/AUTO
+ * are also known to have problems on some cards. This is not a big
+ * problem though because we can have almost the same effect as
+ * FULL_SLEEP by putting card on warm reset (it's almost powered down).
  */
 enum ath5k_power_mode {
         AR5K_PM_UNDEFINED = 0,
@@ -957,6 +1157,8 @@ struct ath5k_capabilities {
         } cap_queues;
 
         bool cap_has_phyerr_counters;
+        bool cap_has_mrr_support;
+        bool cap_needs_2GHz_ovr;
 };
 
 /* size of noise floor history (keep it a power of two) */
@@ -1072,13 +1274,11 @@ struct ath5k_hw {
         dma_addr_t              desc_daddr;     /* DMA (physical) address */
         size_t                  desc_len;       /* size of TX/RX descriptors */
 
-        DECLARE_BITMAP(status, 6);
+        DECLARE_BITMAP(status, 4);
 #define ATH_STAT_INVALID        0               /* disable hardware accesses */
-#define ATH_STAT_MRRETRY        1               /* multi-rate retry support */
-#define ATH_STAT_PROMISC        2
-#define ATH_STAT_LEDSOFT        3               /* enable LED gpio status */
-#define ATH_STAT_STARTED        4               /* opened & irqs enabled */
-#define ATH_STAT_2G_DISABLED    5               /* multiband radio without 2G */
+#define ATH_STAT_PROMISC        1
+#define ATH_STAT_LEDSOFT        2               /* enable LED gpio status */
+#define ATH_STAT_STARTED        3               /* opened & irqs enabled */
 
         unsigned int            filter_flags;   /* HW flags, AR5K_RX_FILTER_* */
         struct ieee80211_channel *curchan;      /* current h/w channel */
@@ -1097,6 +1297,7 @@ struct ath5k_hw {
                                 led_on;         /* pin setting for LED on */
 
         struct work_struct      reset_work;     /* deferred chip reset */
+        struct work_struct      calib_work;     /* deferred phy calibration */
 
         struct list_head        rxbuf;          /* receive buffer */
         spinlock_t              rxbuflock;
@@ -1113,8 +1314,6 @@ struct ath5k_hw {
 
         struct ath5k_rfkill     rf_kill;
 
-        struct tasklet_struct   calib;          /* calibration tasklet */
-
         spinlock_t              block;          /* protects beacon */
         struct tasklet_struct   beacontq;       /* beacon intr tasklet */
         struct list_head        bcbuf;          /* beacon buffer */
@@ -1144,7 +1343,7 @@ struct ath5k_hw {
         enum ath5k_int          ah_imr;
 
         struct ieee80211_channel *ah_current_channel;
-        bool                    ah_calibration;
+        bool                    ah_iq_cal_needed;
         bool                    ah_single_chip;
 
         enum ath5k_version      ah_version;
@@ -1187,7 +1386,13 @@ struct ath5k_hw {
         u32                     ah_txq_imr_cbrurn;
         u32                     ah_txq_imr_qtrig;
         u32                     ah_txq_imr_nofrm;
-        u32                     ah_txq_isr;
+
+        u32                     ah_txq_isr_txok_all;
+        u32                     ah_txq_isr_txurn;
+        u32                     ah_txq_isr_qcborn;
+        u32                     ah_txq_isr_qcburn;
+        u32                     ah_txq_isr_qtrig;
+
         u32                     *ah_rf_banks;
         size_t                  ah_rf_banks_size;
         size_t                  ah_rf_regs_count;
@@ -1228,8 +1433,8 @@ struct ath5k_hw {
 
         /* Calibration timestamp */
         unsigned long           ah_cal_next_full;
+        unsigned long           ah_cal_next_short;
         unsigned long           ah_cal_next_ani;
-        unsigned long           ah_cal_next_nf;
 
         /* Calibration mask */
         u8                      ah_cal_mask;
@@ -1338,11 +1543,11 @@ void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
 void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
-void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
+void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon,
+                                                        u32 interval);
 bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
 /* Init function */
-void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
-                                                                u8 mode);
+void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode);
 
 /* Queue Control Unit, DFS Control Unit Functions */
 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
diff --git a/drivers/net/wireless/ath/ath5k/attach.c b/drivers/net/wireless/ath/ath5k/attach.c
index 91627dd2c26a..d7114c75fe9b 100644
--- a/drivers/net/wireless/ath/ath5k/attach.c
+++ b/drivers/net/wireless/ath/ath5k/attach.c
@@ -27,8 +27,7 @@
 #include "debug.h"
 
 /**
- * ath5k_hw_post - Power On Self Test helper function
- *
+ * ath5k_hw_post() - Power On Self Test helper function
  * @ah: The &struct ath5k_hw
  */
 static int ath5k_hw_post(struct ath5k_hw *ah)
@@ -92,8 +91,7 @@ static int ath5k_hw_post(struct ath5k_hw *ah)
 }
 
 /**
- * ath5k_hw_init - Check if hw is supported and init the needed structs
- *
+ * ath5k_hw_init() - Check if hw is supported and init the needed structs
  * @ah: The &struct ath5k_hw associated with the device
  *
  * Check if the device is supported, perform a POST and initialize the needed
@@ -298,7 +296,7 @@ int ath5k_hw_init(struct ath5k_hw *ah)
 
                 /* Reset SERDES to load new settings */
                 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
-                mdelay(1);
+                usleep_range(1000, 1500);
         }
 
         /* Get misc capabilities */
@@ -308,11 +306,6 @@ int ath5k_hw_init(struct ath5k_hw *ah)
                 goto err;
         }
 
-        if (test_bit(ATH_STAT_2G_DISABLED, ah->status)) {
-                __clear_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode);
-                __clear_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode);
-        }
-
         /* Crypto settings */
         common->keymax = (ah->ah_version == AR5K_AR5210 ?
                           AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
@@ -349,8 +342,7 @@ err:
 }
 
 /**
- * ath5k_hw_deinit - Free the ath5k_hw struct
- *
+ * ath5k_hw_deinit() - Free the &struct ath5k_hw
  * @ah: The &struct ath5k_hw
  */
 void ath5k_hw_deinit(struct ath5k_hw *ah)
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index b346d0492001..178a4dd10316 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -80,6 +80,11 @@ static int modparam_fastchanswitch;
 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
 
+static int ath5k_modparam_no_hw_rfkill_switch;
+module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
+                                                                bool, S_IRUGO);
+MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
+
 
 /* Module info */
 MODULE_AUTHOR("Jiri Slaby");
@@ -183,7 +188,6 @@ static const struct ieee80211_rate ath5k_rates[] = {
         { .bitrate = 540,
           .hw_value = ATH5K_RATE_CODE_54M,
           .flags = 0 },
-        /* XR missing */
 };
 
 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
@@ -721,21 +725,24 @@ ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
         if (ret)
                 goto err_unmap;
 
-        memset(mrr_rate, 0, sizeof(mrr_rate));
-        memset(mrr_tries, 0, sizeof(mrr_tries));
-        for (i = 0; i < 3; i++) {
-                rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
-                if (!rate)
-                        break;
+        /* Set up MRR descriptor */
+        if (ah->ah_capabilities.cap_has_mrr_support) {
+                memset(mrr_rate, 0, sizeof(mrr_rate));
+                memset(mrr_tries, 0, sizeof(mrr_tries));
+                for (i = 0; i < 3; i++) {
+                        rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
+                        if (!rate)
+                                break;
 
-                mrr_rate[i] = rate->hw_value;
-                mrr_tries[i] = info->control.rates[i + 1].count;
-        }
+                        mrr_rate[i] = rate->hw_value;
+                        mrr_tries[i] = info->control.rates[i + 1].count;
+                }
 
-        ath5k_hw_setup_mrr_tx_desc(ah, ds,
-                mrr_rate[0], mrr_tries[0],
-                mrr_rate[1], mrr_tries[1],
-                mrr_rate[2], mrr_tries[2]);
+                ath5k_hw_setup_mrr_tx_desc(ah, ds,
+                        mrr_rate[0], mrr_tries[0],
+                        mrr_rate[1], mrr_tries[1],
+                        mrr_rate[2], mrr_tries[2]);
+        }
 
         ds->ds_link = 0;
         ds->ds_data = bf->skbaddr;
@@ -1689,7 +1696,7 @@ ath5k_tasklet_tx(unsigned long data)
         struct ath5k_hw *ah = (void *)data;
 
         for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
-                if (ah->txqs[i].setup && (ah->ah_txq_isr & BIT(i)))
+                if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
                         ath5k_tx_processq(ah, &ah->txqs[i]);
 
         ah->tx_pending = false;
@@ -2005,7 +2012,7 @@ ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
         ah->nexttbtt = nexttbtt;
 
         intval |= AR5K_BEACON_ENA;
-        ath5k_hw_init_beacon(ah, nexttbtt, intval);
+        ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
 
         /*
          * debugging output last in order to preserve the time critical aspect
@@ -2112,16 +2119,29 @@ static void
 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
 {
         if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
-            !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
-                /* run ANI only when full calibration is not active */
+           !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
+           !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
+
+                /* Run ANI only when calibration is not active */
+
                 ah->ah_cal_next_ani = jiffies +
                         msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
                 tasklet_schedule(&ah->ani_tasklet);
 
-        } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
-                ah->ah_cal_next_full = jiffies +
-                        msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
-                tasklet_schedule(&ah->calib);
+        } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
+                !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
+                !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
+
+                /* Run calibration only when another calibration
+                 * is not running.
+                 *
+                 * Note: This is for both full/short calibration,
+                 * if it's time for a full one, ath5k_calibrate_work will deal
+                 * with it. */
+
+                ah->ah_cal_next_short = jiffies +
+                        msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
+                ieee80211_queue_work(ah->hw, &ah->calib_work);
         }
         /* we could use SWI to generate enough interrupts to meet our
          * calibration interval requirements, if necessary:
@@ -2149,69 +2169,110 @@ ath5k_intr(int irq, void *dev_id)
         enum ath5k_int status;
         unsigned int counter = 1000;
 
+
+        /*
+         * If hw is not ready (or detached) and we get an
+         * interrupt, or if we have no interrupts pending
+         * (that means it's not for us) skip it.
+         *
+         * NOTE: Group 0/1 PCI interface registers are not
+         * supported on WiSOCs, so we can't check for pending
+         * interrupts (ISR belongs to another register group
+         * so we are ok).
+         */
         if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
-                ((ath5k_get_bus_type(ah) != ATH_AHB) &&
-                                !ath5k_hw_is_intr_pending(ah))))
+                        ((ath5k_get_bus_type(ah) != ATH_AHB) &&
+                        !ath5k_hw_is_intr_pending(ah))))
                 return IRQ_NONE;
 
+        /** Main loop **/
         do {
-                ath5k_hw_get_isr(ah, &status);          /* NB: clears IRQ too */
+                ath5k_hw_get_isr(ah, &status);  /* NB: clears IRQ too */
+
                 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
                                 status, ah->imask);
+
+                /*
+                 * Fatal hw error -> Log and reset
+                 *
+                 * Fatal errors are unrecoverable so we have to
+                 * reset the card. These errors include bus and
+                 * dma errors.
+                 */
                 if (unlikely(status & AR5K_INT_FATAL)) {
-                        /*
-                         * Fatal errors are unrecoverable.
-                         * Typically these are caused by DMA errors.
-                         */
+
                         ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
                                   "fatal int, resetting\n");
                         ieee80211_queue_work(ah->hw, &ah->reset_work);
+
+                /*
+                 * RX Overrun -> Count and reset if needed
+                 *
+                 * Receive buffers are full. Either the bus is busy or
+                 * the CPU is not fast enough to process all received
+                 * frames.
+                 */
                 } else if (unlikely(status & AR5K_INT_RXORN)) {
+
                         /*
-                         * Receive buffers are full. Either the bus is busy or
-                         * the CPU is not fast enough to process all received
-                         * frames.
                          * Older chipsets need a reset to come out of this
                          * condition, but we treat it as RX for newer chips.
-                         * We don't know exactly which versions need a reset -
+                         * We don't know exactly which versions need a reset
                          * this guess is copied from the HAL.
                          */
                         ah->stats.rxorn_intr++;
+
                         if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
                                 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
                                           "rx overrun, resetting\n");
                                 ieee80211_queue_work(ah->hw, &ah->reset_work);
                         } else
                                 ath5k_schedule_rx(ah);
+
                 } else {
+
+                        /* Software Beacon Alert -> Schedule beacon tasklet */
                         if (status & AR5K_INT_SWBA)
                                 tasklet_hi_schedule(&ah->beacontq);
 
-                        if (status & AR5K_INT_RXEOL) {
-                                /*
-                                * NB: the hardware should re-read the link when
-                                *     RXE bit is written, but it doesn't work at
-                                *     least on older hardware revs.
-                                */
+                        /*
+                         * No more RX descriptors -> Just count
+                         *
+                         * NB: the hardware should re-read the link when
+                         *     RXE bit is written, but it doesn't work at
+                         *     least on older hardware revs.
+                         */
+                        if (status & AR5K_INT_RXEOL)
                                 ah->stats.rxeol_intr++;
-                        }
-                        if (status & AR5K_INT_TXURN) {
-                                /* bump tx trigger level */
+
+
+                        /* TX Underrun -> Bump tx trigger level */
+                        if (status & AR5K_INT_TXURN)
                                 ath5k_hw_update_tx_triglevel(ah, true);
-                        }
+
+                        /* RX -> Schedule rx tasklet */
                         if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
                                 ath5k_schedule_rx(ah);
-                        if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
-                                        | AR5K_INT_TXERR | AR5K_INT_TXEOL))
+
+                        /* TX -> Schedule tx tasklet */
+                        if (status & (AR5K_INT_TXOK
+                                        | AR5K_INT_TXDESC
+                                        | AR5K_INT_TXERR
+                                        | AR5K_INT_TXEOL))
                                 ath5k_schedule_tx(ah);
-                        if (status & AR5K_INT_BMISS) {
-                                /* TODO */
-                        }
+
+                        /* Missed beacon -> TODO
+                        if (status & AR5K_INT_BMISS)
+                        */
+
+                        /* MIB event -> Update counters and notify ANI */
                         if (status & AR5K_INT_MIB) {
                                 ah->stats.mib_intr++;
                                 ath5k_hw_update_mib_counters(ah);
                                 ath5k_ani_mib_intr(ah);
                         }
+
+                        /* GPIO -> Notify RFKill layer */
                         if (status & AR5K_INT_GPIO)
                                 tasklet_schedule(&ah->rf_kill.toggleq);
 
@@ -2222,12 +2283,19 @@ ath5k_intr(int irq, void *dev_id)
 
         } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
 
+        /*
+         * Until we handle rx/tx interrupts mask them on IMR
+         *
+         * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
+         * and unset after we 've handled the interrupts.
+         */
         if (ah->rx_pending || ah->tx_pending)
                 ath5k_set_current_imask(ah);
 
         if (unlikely(!counter))
                 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
 
+        /* Fire up calibration poll */
         ath5k_intr_calibration_poll(ah);
 
         return IRQ_HANDLED;
@@ -2238,41 +2306,58 @@ ath5k_intr(int irq, void *dev_id)
  * for temperature/environment changes.
  */
 static void
-ath5k_tasklet_calibrate(unsigned long data)
+ath5k_calibrate_work(struct work_struct *work)
 {
-        struct ath5k_hw *ah = (void *)data;
+        struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
+                calib_work);
+
+        /* Should we run a full calibration ? */
+        if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
+
+                ah->ah_cal_next_full = jiffies +
+                        msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
+                ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
+
+                ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
+                                "running full calibration\n");
+
+                if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
+                        /*
+                         * Rfgain is out of bounds, reset the chip
+                         * to load new gain values.
+                         */
+                        ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
+                                        "got new rfgain, resetting\n");
+                        ieee80211_queue_work(ah->hw, &ah->reset_work);
+                }
+
+                /* TODO: On full calibration we should stop TX here,
+                 * so that it doesn't interfere (mostly due to gain_f
+                 * calibration that messes with tx packets -see phy.c).
+                 *
+                 * NOTE: Stopping the queues from above is not enough
+                 * to stop TX but saves us from disconecting (at least
+                 * we don't lose packets). */
+                ieee80211_stop_queues(ah->hw);
+        } else
+                ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
 
-        /* Only full calibration for now */
-        ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
 
         ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
                 ieee80211_frequency_to_channel(ah->curchan->center_freq),
                 ah->curchan->hw_value);
 
-        if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
-                /*
-                 * Rfgain is out of bounds, reset the chip
-                 * to load new gain values.
-                 */
-                ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "calibration, resetting\n");
-                ieee80211_queue_work(ah->hw, &ah->reset_work);
-        }
         if (ath5k_hw_phy_calibrate(ah, ah->curchan))
                 ATH5K_ERR(ah, "calibration of channel %u failed\n",
                         ieee80211_frequency_to_channel(
                                 ah->curchan->center_freq));
 
-        /* Noise floor calibration interrupts rx/tx path while I/Q calibration
-         * doesn't.
-         * TODO: We should stop TX here, so that it doesn't interfere.
-         * Note that stopping the queues is not enough to stop TX! */
-        if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
-                ah->ah_cal_next_nf = jiffies +
-                        msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
-                ath5k_hw_update_noise_floor(ah);
-        }
-
-        ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
+        /* Clear calibration flags */
+        if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) {
+                ieee80211_wake_queues(ah->hw);
+                ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
+        } else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
+                ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
 }
 
 
@@ -2407,8 +2492,8 @@ ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
         if (ret)
                 goto err_irq;
 
-        /* set up multi-rate retry capabilities */
-        if (ah->ah_version == AR5K_AR5212) {
+        /* Set up multi-rate retry capabilities */
+        if (ah->ah_capabilities.cap_has_mrr_support) {
                 hw->max_rates = 4;
                 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
                                          AR5K_INIT_RETRY_LONG);
@@ -2544,15 +2629,22 @@ int ath5k_start(struct ieee80211_hw *hw)
          * and then setup of the interrupt mask.
          */
         ah->curchan = ah->hw->conf.channel;
-        ah->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
-                AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
-                AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
+        ah->imask = AR5K_INT_RXOK
+                | AR5K_INT_RXERR
+                | AR5K_INT_RXEOL
+                | AR5K_INT_RXORN
+                | AR5K_INT_TXDESC
+                | AR5K_INT_TXEOL
+                | AR5K_INT_FATAL
+                | AR5K_INT_GLOBAL
+                | AR5K_INT_MIB;
 
         ret = ath5k_reset(ah, NULL, false);
         if (ret)
                 goto done;
 
-        ath5k_rfkill_hw_start(ah);
+        if (!ath5k_modparam_no_hw_rfkill_switch)
+                ath5k_rfkill_hw_start(ah);
 
         /*
          * Reset the key cache since some parts do not reset the
@@ -2585,7 +2677,6 @@ static void ath5k_stop_tasklets(struct ath5k_hw *ah)
         ah->tx_pending = false;
         tasklet_kill(&ah->rxtq);
         tasklet_kill(&ah->txtq);
-        tasklet_kill(&ah->calib);
         tasklet_kill(&ah->beacontq);
         tasklet_kill(&ah->ani_tasklet);
 }
@@ -2637,7 +2728,8 @@ void ath5k_stop(struct ieee80211_hw *hw)
 
         cancel_delayed_work_sync(&ah->tx_complete_work);
 
-        ath5k_rfkill_hw_stop(ah);
+        if (!ath5k_modparam_no_hw_rfkill_switch)
+                ath5k_rfkill_hw_stop(ah);
 }
 
 /*
@@ -2689,9 +2781,24 @@ ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
 
         ath5k_ani_init(ah, ani_mode);
 
-        ah->ah_cal_next_full = jiffies + msecs_to_jiffies(100);
-        ah->ah_cal_next_ani = jiffies;
-        ah->ah_cal_next_nf = jiffies;
+        /*
+         * Set calibration intervals
+         *
+         * Note: We don't need to run calibration imediately
+         * since some initial calibration is done on reset
+         * even for fast channel switching. Also on scanning
+         * this will get set again and again and it won't get
+         * executed unless we connect somewhere and spend some
+         * time on the channel (that's what calibration needs
+         * anyway to be accurate).
+         */
+        ah->ah_cal_next_full = jiffies +
+                msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
+        ah->ah_cal_next_ani = jiffies +
+                msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
+        ah->ah_cal_next_short = jiffies +
+                msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
+
         ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
 
         /* clear survey data and cycle counters */
@@ -2745,20 +2852,6 @@ ath5k_init(struct ieee80211_hw *hw)
 
 
         /*
-         * Check if the MAC has multi-rate retry support.
-         * We do this by trying to setup a fake extended
-         * descriptor.  MACs that don't have support will
-         * return false w/o doing anything.  MACs that do
-         * support it will return true w/o doing anything.
-         */
-        ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
-
-        if (ret < 0)
-                goto err;
-        if (ret > 0)
-                __set_bit(ATH_STAT_MRRETRY, ah->status);
-
-        /*
          * Collect the channel list.  The 802.11 layer
          * is responsible for filtering this list based
          * on settings like the phy mode and regulatory
@@ -2841,11 +2934,11 @@ ath5k_init(struct ieee80211_hw *hw)
 
         tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
         tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
-        tasklet_init(&ah->calib, ath5k_tasklet_calibrate, (unsigned long)ah);
         tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
         tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
 
         INIT_WORK(&ah->reset_work, ath5k_reset_work);
+        INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
         INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
 
         ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
diff --git a/drivers/net/wireless/ath/ath5k/caps.c b/drivers/net/wireless/ath/ath5k/caps.c
index 810fba96702b..994169ad39cb 100644
--- a/drivers/net/wireless/ath/ath5k/caps.c
+++ b/drivers/net/wireless/ath/ath5k/caps.c
@@ -85,12 +85,19 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
                         caps->cap_range.range_2ghz_min = 2412;
                         caps->cap_range.range_2ghz_max = 2732;
 
-                        if (AR5K_EEPROM_HDR_11B(ee_header))
-                                __set_bit(AR5K_MODE_11B, caps->cap_mode);
-
-                        if (AR5K_EEPROM_HDR_11G(ee_header) &&
-                            ah->ah_version != AR5K_AR5211)
-                                __set_bit(AR5K_MODE_11G, caps->cap_mode);
+                        /* Override 2GHz modes on SoCs that need it
+                         * NOTE: cap_needs_2GHz_ovr gets set from
+                         * ath_ahb_probe */
+                        if (!caps->cap_needs_2GHz_ovr) {
+                                if (AR5K_EEPROM_HDR_11B(ee_header))
+                                        __set_bit(AR5K_MODE_11B,
+                                                        caps->cap_mode);
+
+                                if (AR5K_EEPROM_HDR_11G(ee_header) &&
+                                ah->ah_version != AR5K_AR5211)
+                                        __set_bit(AR5K_MODE_11G,
+                                                        caps->cap_mode);
+                        }
                 }
         }
 
@@ -103,12 +110,18 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
         else
                 caps->cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
 
-        /* newer hardware has PHY error counters */
+        /* Newer hardware has PHY error counters */
         if (ah->ah_mac_srev >= AR5K_SREV_AR5213A)
                 caps->cap_has_phyerr_counters = true;
         else
                 caps->cap_has_phyerr_counters = false;
 
+        /* MACs since AR5212 have MRR support */
+        if (ah->ah_version == AR5K_AR5212)
+                caps->cap_has_mrr_support = true;
+        else
+                caps->cap_has_mrr_support = false;
+
         return 0;
 }
 
diff --git a/drivers/net/wireless/ath/ath5k/debug.c b/drivers/net/wireless/ath/ath5k/debug.c
index fce8c904eea9..8c5ce8b0c734 100644
--- a/drivers/net/wireless/ath/ath5k/debug.c
+++ b/drivers/net/wireless/ath/ath5k/debug.c
@@ -57,8 +57,9 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGES.
  */
+#include <linux/export.h>
+#include <linux/moduleparam.h>
 
-#include <linux/module.h>
 #include <linux/seq_file.h>
 #include <linux/list.h>
 #include "debug.h"
diff --git a/drivers/net/wireless/ath/ath5k/debug.h b/drivers/net/wireless/ath/ath5k/debug.h
index 7f37df3125fd..0a3f916a1ef3 100644
--- a/drivers/net/wireless/ath/ath5k/debug.h
+++ b/drivers/net/wireless/ath/ath5k/debug.h
@@ -141,10 +141,10 @@ ath5k_debug_printtxbuf(struct ath5k_hw *ah, struct ath5k_buf *bf);
 
 #include <linux/compiler.h>
 
-static inline void __attribute__ ((format (printf, 3, 4)))
+static inline __printf(3, 4) void
 ATH5K_DBG(struct ath5k_hw *ah, unsigned int m, const char *fmt, ...) {}
 
-static inline void __attribute__ ((format (printf, 3, 4)))
+static inline __printf(3, 4) void
 ATH5K_DBG_UNLIMIT(struct ath5k_hw *ah, unsigned int m, const char *fmt, ...)
 {}
 
diff --git a/drivers/net/wireless/ath/ath5k/desc.c b/drivers/net/wireless/ath/ath5k/desc.c
index 7e88dda82221..f8bfa3ac2af0 100644
--- a/drivers/net/wireless/ath/ath5k/desc.c
+++ b/drivers/net/wireless/ath/ath5k/desc.c
@@ -26,20 +26,61 @@
 #include "debug.h"
 
 
+/**
+ * DOC: Hardware descriptor functions
+ *
+ * Here we handle the processing of the low-level hw descriptors
+ * that hw reads and writes via DMA for each TX and RX attempt (that means
+ * we can also have descriptors for failed TX/RX tries). We have two kind of
+ * descriptors for RX and TX, control descriptors tell the hw how to send or
+ * receive a packet where to read/write it from/to etc and status descriptors
+ * that contain information about how the packet was sent or received (errors
+ * included).
+ *
+ * Descriptor format is not exactly the same for each MAC chip version so we
+ * have function pointers on &struct ath5k_hw we initialize at runtime based on
+ * the chip used.
+ */
+
+
 /************************\
 * TX Control descriptors *
 \************************/
 
-/*
- * Initialize the 2-word tx control descriptor on 5210/5211
+/**
+ * ath5k_hw_setup_2word_tx_desc() - Initialize a 2-word tx control descriptor
+ * @ah: The &struct ath5k_hw
+ * @desc: The &struct ath5k_desc
+ * @pkt_len: Frame length in bytes
+ * @hdr_len: Header length in bytes (only used on AR5210)
+ * @padsize: Any padding we've added to the frame length
+ * @type: One of enum ath5k_pkt_type
+ * @tx_power: Tx power in 0.5dB steps
+ * @tx_rate0: HW idx for transmission rate
+ * @tx_tries0: Max number of retransmissions
+ * @key_index: Index on key table to use for encryption
+ * @antenna_mode: Which antenna to use (0 for auto)
+ * @flags: One of AR5K_TXDESC_* flags (desc.h)
+ * @rtscts_rate: HW idx for RTS/CTS transmission rate
+ * @rtscts_duration: What to put on duration field on the header of RTS/CTS
+ *
+ * Internal function to initialize a 2-Word TX control descriptor
+ * found on AR5210 and AR5211 MACs chips.
+ *
+ * Returns 0 on success or -EINVAL on false input
  */
 static int
-ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
-        unsigned int pkt_len, unsigned int hdr_len, int padsize,
-        enum ath5k_pkt_type type,
-        unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
-        unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
-        unsigned int rtscts_rate, unsigned int rtscts_duration)
+ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah,
+                        struct ath5k_desc *desc,
+                        unsigned int pkt_len, unsigned int hdr_len,
+                        int padsize,
+                        enum ath5k_pkt_type type,
+                        unsigned int tx_power,
+                        unsigned int tx_rate0, unsigned int tx_tries0,
+                        unsigned int key_index,
+                        unsigned int antenna_mode,
+                        unsigned int flags,
+                        unsigned int rtscts_rate, unsigned int rtscts_duration)
 {
         u32 frame_type;
         struct ath5k_hw_2w_tx_ctl *tx_ctl;
@@ -172,17 +213,40 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
         return 0;
 }
 
-/*
- * Initialize the 4-word tx control descriptor on 5212
+/**
+ * ath5k_hw_setup_4word_tx_desc() - Initialize a 4-word tx control descriptor
+ * @ah: The &struct ath5k_hw
+ * @desc: The &struct ath5k_desc
+ * @pkt_len: Frame length in bytes
+ * @hdr_len: Header length in bytes (only used on AR5210)
+ * @padsize: Any padding we've added to the frame length
+ * @type: One of enum ath5k_pkt_type
+ * @tx_power: Tx power in 0.5dB steps
+ * @tx_rate0: HW idx for transmission rate
+ * @tx_tries0: Max number of retransmissions
+ * @key_index: Index on key table to use for encryption
+ * @antenna_mode: Which antenna to use (0 for auto)
+ * @flags: One of AR5K_TXDESC_* flags (desc.h)
+ * @rtscts_rate: HW idx for RTS/CTS transmission rate
+ * @rtscts_duration: What to put on duration field on the header of RTS/CTS
+ *
+ * Internal function to initialize a 4-Word TX control descriptor
+ * found on AR5212 and later MACs chips.
+ *
+ * Returns 0 on success or -EINVAL on false input
  */
-static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
-        struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
-        int padsize,
-        enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
-        unsigned int tx_tries0, unsigned int key_index,
-        unsigned int antenna_mode, unsigned int flags,
-        unsigned int rtscts_rate,
-        unsigned int rtscts_duration)
+static int
+ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
+                        struct ath5k_desc *desc,
+                        unsigned int pkt_len, unsigned int hdr_len,
+                        int padsize,
+                        enum ath5k_pkt_type type,
+                        unsigned int tx_power,
+                        unsigned int tx_rate0, unsigned int tx_tries0,
+                        unsigned int key_index,
+                        unsigned int antenna_mode,
+                        unsigned int flags,
+                        unsigned int rtscts_rate, unsigned int rtscts_duration)
 {
         struct ath5k_hw_4w_tx_ctl *tx_ctl;
         unsigned int frame_len;
@@ -292,13 +356,29 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
         return 0;
 }
 
-/*
- * Initialize a 4-word multi rate retry tx control descriptor on 5212
+/**
+ * ath5k_hw_setup_mrr_tx_desc() - Initialize an MRR tx control descriptor
+ * @ah: The &struct ath5k_hw
+ * @desc: The &struct ath5k_desc
+ * @tx_rate1: HW idx for rate used on transmission series 1
+ * @tx_tries1: Max number of retransmissions for transmission series 1
+ * @tx_rate2: HW idx for rate used on transmission series 2
+ * @tx_tries2: Max number of retransmissions for transmission series 2
+ * @tx_rate3: HW idx for rate used on transmission series 3
+ * @tx_tries3: Max number of retransmissions for transmission series 3
+ *
+ * Multi rate retry (MRR) tx control descriptors are available only on AR5212
+ * MACs, they are part of the normal 4-word tx control descriptor (see above)
+ * but we handle them through a separate function for better abstraction.
+ *
+ * Returns 0 on success or -EINVAL on invalid input
  */
 int
-ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
-        unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
-        u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)
+ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah,
+                        struct ath5k_desc *desc,
+                        u_int tx_rate1, u_int tx_tries1,
+                        u_int tx_rate2, u_int tx_tries2,
+                        u_int tx_rate3, u_int tx_tries3)
 {
         struct ath5k_hw_4w_tx_ctl *tx_ctl;
 
@@ -350,11 +430,16 @@ ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
 * TX Status descriptors *
 \***********************/
 
-/*
- * Process the tx status descriptor on 5210/5211
+/**
+ * ath5k_hw_proc_2word_tx_status() - Process a tx status descriptor on 5210/1
+ * @ah: The &struct ath5k_hw
+ * @desc: The &struct ath5k_desc
+ * @ts: The &struct ath5k_tx_status
  */
-static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
-                struct ath5k_desc *desc, struct ath5k_tx_status *ts)
+static int
+ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
+                                struct ath5k_desc *desc,
+                                struct ath5k_tx_status *ts)
 {
         struct ath5k_hw_2w_tx_ctl *tx_ctl;
         struct ath5k_hw_tx_status *tx_status;
@@ -399,11 +484,16 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
         return 0;
 }
 
-/*
- * Process a tx status descriptor on 5212
+/**
+ * ath5k_hw_proc_4word_tx_status() - Process a tx status descriptor on 5212
+ * @ah: The &struct ath5k_hw
+ * @desc: The &struct ath5k_desc
+ * @ts: The &struct ath5k_tx_status
  */
-static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
-                struct ath5k_desc *desc, struct ath5k_tx_status *ts)
+static int
+ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
+                                struct ath5k_desc *desc,
+                                struct ath5k_tx_status *ts)
 {
         struct ath5k_hw_4w_tx_ctl *tx_ctl;
         struct ath5k_hw_tx_status *tx_status;
@@ -460,11 +550,17 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
 * RX Descriptors *
 \****************/
 
-/*
- * Initialize an rx control descriptor
+/**
+ * ath5k_hw_setup_rx_desc() - Initialize an rx control descriptor
+ * @ah: The &struct ath5k_hw
+ * @desc: The &struct ath5k_desc
+ * @size: RX buffer length in bytes
+ * @flags: One of AR5K_RXDESC_* flags
  */
-int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
-                           u32 size, unsigned int flags)
+int
+ath5k_hw_setup_rx_desc(struct ath5k_hw *ah,
+                        struct ath5k_desc *desc,
+                        u32 size, unsigned int flags)
 {
         struct ath5k_hw_rx_ctl *rx_ctl;
 
@@ -491,11 +587,22 @@ int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
         return 0;
 }
 
-/*
- * Process the rx status descriptor on 5210/5211
+/**
+ * ath5k_hw_proc_5210_rx_status() - Process the rx status descriptor on 5210/1
+ * @ah: The &struct ath5k_hw
+ * @desc: The &struct ath5k_desc
+ * @rs: The &struct ath5k_rx_status
+ *
+ * Internal function used to process an RX status descriptor
+ * on AR5210/5211 MAC.
+ *
+ * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e
+ * frame yet.
  */
-static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
-                struct ath5k_desc *desc, struct ath5k_rx_status *rs)
+static int
+ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
+                                struct ath5k_desc *desc,
+                                struct ath5k_rx_status *rs)
 {
         struct ath5k_hw_rx_status *rx_status;
 
@@ -574,12 +681,22 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
         return 0;
 }
 
-/*
- * Process the rx status descriptor on 5212
+/**
+ * ath5k_hw_proc_5212_rx_status() - Process the rx status descriptor on 5212
+ * @ah: The &struct ath5k_hw
+ * @desc: The &struct ath5k_desc
+ * @rs: The &struct ath5k_rx_status
+ *
+ * Internal function used to process an RX status descriptor
+ * on AR5212 and later MAC.
+ *
+ * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e
+ * frame yet.
  */
-static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
-                                        struct ath5k_desc *desc,
-                                        struct ath5k_rx_status *rs)
+static int
+ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
+                                struct ath5k_desc *desc,
+                                struct ath5k_rx_status *rs)
 {
         struct ath5k_hw_rx_status *rx_status;
         u32 rxstat0, rxstat1;
@@ -646,10 +763,16 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
 * Attach *
 \********/
 
-/*
- * Init function pointers inside ath5k_hw struct
+/**
+ * ath5k_hw_init_desc_functions() - Init function pointers inside ah
+ * @ah: The &struct ath5k_hw
+ *
+ * Maps the internal descriptor functions to the function pointers on ah, used
+ * from above. This is used as an abstraction layer to handle the various chips
+ * the same way.
  */
-int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
+int
+ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
 {
         if (ah->ah_version == AR5K_AR5212) {
                 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
diff --git a/drivers/net/wireless/ath/ath5k/desc.h b/drivers/net/wireless/ath/ath5k/desc.h
index cfd529b548f3..8d6c01a49ea3 100644
--- a/drivers/net/wireless/ath/ath5k/desc.h
+++ b/drivers/net/wireless/ath/ath5k/desc.h
@@ -20,25 +20,30 @@
  * RX/TX descriptor structures
  */
 
-/*
- * Common hardware RX control descriptor
+/**
+ * struct ath5k_hw_rx_ctl - Common hardware RX control descriptor
+ * @rx_control_0: RX control word 0
+ * @rx_control_1: RX control word 1
  */
 struct ath5k_hw_rx_ctl {
-        u32     rx_control_0; /* RX control word 0 */
-        u32     rx_control_1; /* RX control word 1 */
+        u32     rx_control_0;
+        u32     rx_control_1;
 } __packed __aligned(4);
 
 /* RX control word 1 fields/flags */
 #define AR5K_DESC_RX_CTL1_BUF_LEN               0x00000fff /* data buffer length */
 #define AR5K_DESC_RX_CTL1_INTREQ                0x00002000 /* RX interrupt request */
 
-/*
- * Common hardware RX status descriptor
+/**
+ * struct ath5k_hw_rx_status - Common hardware RX status descriptor
+ * @rx_status_0: RX status word 0
+ * @rx_status_1: RX status word 1
+ *
  * 5210, 5211 and 5212 differ only in the fields and flags defined below
  */
 struct ath5k_hw_rx_status {
-        u32     rx_status_0; /* RX status word 0 */
-        u32     rx_status_1; /* RX status word 1 */
+        u32     rx_status_0;
+        u32     rx_status_1;
 } __packed __aligned(4);
 
 /* 5210/5211 */
@@ -98,17 +103,36 @@ struct ath5k_hw_rx_status {
 
 /**
  * enum ath5k_phy_error_code - PHY Error codes
+ * @AR5K_RX_PHY_ERROR_UNDERRUN: Transmit underrun, [5210] No error
+ * @AR5K_RX_PHY_ERROR_TIMING: Timing error
+ * @AR5K_RX_PHY_ERROR_PARITY: Illegal parity
+ * @AR5K_RX_PHY_ERROR_RATE: Illegal rate
+ * @AR5K_RX_PHY_ERROR_LENGTH: Illegal length
+ * @AR5K_RX_PHY_ERROR_RADAR: Radar detect, [5210] 64 QAM rate
+ * @AR5K_RX_PHY_ERROR_SERVICE: Illegal service
+ * @AR5K_RX_PHY_ERROR_TOR: Transmit override receive
+ * @AR5K_RX_PHY_ERROR_OFDM_TIMING: OFDM Timing error [5212+]
+ * @AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY: OFDM Signal parity error [5212+]
+ * @AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL: OFDM Illegal rate [5212+]
+ * @AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL: OFDM Illegal length [5212+]
+ * @AR5K_RX_PHY_ERROR_OFDM_POWER_DROP: OFDM Power drop [5212+]
+ * @AR5K_RX_PHY_ERROR_OFDM_SERVICE: OFDM Service (?) [5212+]
+ * @AR5K_RX_PHY_ERROR_OFDM_RESTART: OFDM Restart (?) [5212+]
+ * @AR5K_RX_PHY_ERROR_CCK_TIMING: CCK Timing error [5212+]
+ * @AR5K_RX_PHY_ERROR_CCK_HEADER_CRC: Header CRC error [5212+]
+ * @AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL: Illegal rate [5212+]
+ * @AR5K_RX_PHY_ERROR_CCK_SERVICE: CCK Service (?) [5212+]
+ * @AR5K_RX_PHY_ERROR_CCK_RESTART: CCK Restart (?) [5212+]
  */
 enum ath5k_phy_error_code {
-        AR5K_RX_PHY_ERROR_UNDERRUN              = 0,    /* Transmit underrun, [5210] No error */
-        AR5K_RX_PHY_ERROR_TIMING                = 1,    /* Timing error */
-        AR5K_RX_PHY_ERROR_PARITY                = 2,    /* Illegal parity */
-        AR5K_RX_PHY_ERROR_RATE                  = 3,    /* Illegal rate */
-        AR5K_RX_PHY_ERROR_LENGTH                = 4,    /* Illegal length */
-        AR5K_RX_PHY_ERROR_RADAR                 = 5,    /* Radar detect, [5210] 64 QAM rate */
-        AR5K_RX_PHY_ERROR_SERVICE               = 6,    /* Illegal service */
-        AR5K_RX_PHY_ERROR_TOR                   = 7,    /* Transmit override receive */
-        /* these are specific to the 5212 */
+        AR5K_RX_PHY_ERROR_UNDERRUN              = 0,
+        AR5K_RX_PHY_ERROR_TIMING                = 1,
+        AR5K_RX_PHY_ERROR_PARITY                = 2,
+        AR5K_RX_PHY_ERROR_RATE                  = 3,
+        AR5K_RX_PHY_ERROR_LENGTH                = 4,
+        AR5K_RX_PHY_ERROR_RADAR                 = 5,
+        AR5K_RX_PHY_ERROR_SERVICE               = 6,
+        AR5K_RX_PHY_ERROR_TOR                   = 7,
         AR5K_RX_PHY_ERROR_OFDM_TIMING           = 17,
         AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY    = 18,
         AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL     = 19,
@@ -123,12 +147,14 @@ enum ath5k_phy_error_code {
         AR5K_RX_PHY_ERROR_CCK_RESTART           = 31,
 };
 
-/*
- * 5210/5211 hardware 2-word TX control descriptor
+/**
+ * struct ath5k_hw_2w_tx_ctl  - 5210/5211 hardware 2-word TX control descriptor
+ * @tx_control_0: TX control word 0
+ * @tx_control_1: TX control word 1
  */
 struct ath5k_hw_2w_tx_ctl {
-        u32     tx_control_0; /* TX control word 0 */
-        u32     tx_control_1; /* TX control word 1 */
+        u32     tx_control_0;
+        u32     tx_control_1;
 } __packed __aligned(4);
 
 /* TX control word 0 fields/flags */
@@ -177,14 +203,18 @@ struct ath5k_hw_2w_tx_ctl {
 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS     4
 #define AR5K_AR5211_TX_DESC_FRAME_TYPE_PRESP    4
 
-/*
- * 5212 hardware 4-word TX control descriptor
+/**
+ * struct ath5k_hw_4w_tx_ctl - 5212 hardware 4-word TX control descriptor
+ * @tx_control_0: TX control word 0
+ * @tx_control_1: TX control word 1
+ * @tx_control_2: TX control word 2
+ * @tx_control_3: TX control word 3
  */
 struct ath5k_hw_4w_tx_ctl {
-        u32     tx_control_0; /* TX control word 0 */
-        u32     tx_control_1; /* TX control word 1 */
-        u32     tx_control_2; /* TX control word 2 */
-        u32     tx_control_3; /* TX control word 3 */
+        u32     tx_control_0;
+        u32     tx_control_1;
+        u32     tx_control_2;
+        u32     tx_control_3;
 } __packed __aligned(4);
 
 /* TX control word 0 fields/flags */
@@ -238,12 +268,14 @@ struct ath5k_hw_4w_tx_ctl {
 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE       0x01f00000 /* RTS or CTS rate */
 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S     20
 
-/*
- * Common TX status descriptor
+/**
+ * struct ath5k_hw_tx_status - Common TX status descriptor
+ * @tx_status_0: TX status word 0
+ * @tx_status_1: TX status word 1
  */
 struct ath5k_hw_tx_status {
-        u32     tx_status_0; /* TX status word 0 */
-        u32     tx_status_1; /* TX status word 1 */
+        u32     tx_status_0;
+        u32     tx_status_1;
 } __packed __aligned(4);
 
 /* TX status word 0 fields/flags */
@@ -276,37 +308,47 @@ struct ath5k_hw_tx_status {
 #define AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212  0x00800000 /* [5212] compression status */
 #define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212  0x01000000 /* [5212] transmit antenna */
 
-/*
- * 5210/5211 hardware TX descriptor
+/**
+ * struct ath5k_hw_5210_tx_desc - 5210/5211 hardware TX descriptor
+ * @tx_ctl: The &struct ath5k_hw_2w_tx_ctl
+ * @tx_stat: The &struct ath5k_hw_tx_status
  */
 struct ath5k_hw_5210_tx_desc {
         struct ath5k_hw_2w_tx_ctl       tx_ctl;
         struct ath5k_hw_tx_status       tx_stat;
 } __packed __aligned(4);
 
-/*
- * 5212 hardware TX descriptor
+/**
+ * struct ath5k_hw_5212_tx_desc - 5212 hardware TX descriptor
+ * @tx_ctl: The &struct ath5k_hw_4w_tx_ctl
+ * @tx_stat: The &struct ath5k_hw_tx_status
  */
 struct ath5k_hw_5212_tx_desc {
         struct ath5k_hw_4w_tx_ctl       tx_ctl;
         struct ath5k_hw_tx_status       tx_stat;
 } __packed __aligned(4);
 
-/*
- * Common hardware RX descriptor
+/**
+ * struct ath5k_hw_all_rx_desc - Common hardware RX descriptor
+ * @rx_ctl: The &struct ath5k_hw_rx_ctl
+ * @rx_stat: The &struct ath5k_hw_rx_status
  */
 struct ath5k_hw_all_rx_desc {
         struct ath5k_hw_rx_ctl          rx_ctl;
         struct ath5k_hw_rx_status       rx_stat;
 } __packed __aligned(4);
 
-/*
- * Atheros hardware DMA descriptor
+/**
+ * struct ath5k_desc - Atheros hardware DMA descriptor
+ * @ds_link: Physical address of the next descriptor
+ * @ds_data: Physical address of data buffer (skb)
+ * @ud: Union containing hw_5xxx_tx_desc structs and hw_all_rx_desc
+ *
  * This is read and written to by the hardware
  */
 struct ath5k_desc {
-        u32     ds_link;        /* physical address of the next descriptor */
-        u32     ds_data;        /* physical address of data buffer (skb) */
+        u32     ds_link;
+        u32     ds_data;
 
         union {
                 struct ath5k_hw_5210_tx_desc    ds_tx5210;
diff --git a/drivers/net/wireless/ath/ath5k/dma.c b/drivers/net/wireless/ath/ath5k/dma.c
index 2481f9c7f4b6..5cc9aa814697 100644
--- a/drivers/net/wireless/ath/ath5k/dma.c
+++ b/drivers/net/wireless/ath/ath5k/dma.c
@@ -20,16 +20,13 @@
 * DMA and interrupt masking functions *
 \*************************************/
 
-/*
- * dma.c - DMA and interrupt masking functions
+/**
+ * DOC: DMA and interrupt masking functions
  *
  * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and
  * handle queue setup for 5210 chipset (rest are handled on qcu.c).
  * Also we setup interrupt mask register (IMR) and read the various interrupt
  * status registers (ISR).
- *
- * TODO: Handle SISR on 5211+ and introduce a function to return the queue
- * number that resulted the interrupt.
  */
 
 #include "ath5k.h"
@@ -42,22 +39,22 @@
 \*********/
 
 /**
- * ath5k_hw_start_rx_dma - Start DMA receive
- *
+ * ath5k_hw_start_rx_dma() - Start DMA receive
  * @ah: The &struct ath5k_hw
  */
-void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
+void
+ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
 {
         ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
         ath5k_hw_reg_read(ah, AR5K_CR);
 }
 
 /**
- * ath5k_hw_stop_rx_dma - Stop DMA receive
- *
+ * ath5k_hw_stop_rx_dma() - Stop DMA receive
  * @ah: The &struct ath5k_hw
  */
-static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
+static int
+ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
 {
         unsigned int i;
 
@@ -79,24 +76,24 @@ static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
 }
 
 /**
- * ath5k_hw_get_rxdp - Get RX Descriptor's address
- *
+ * ath5k_hw_get_rxdp() - Get RX Descriptor's address
  * @ah: The &struct ath5k_hw
  */
-u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
+u32
+ath5k_hw_get_rxdp(struct ath5k_hw *ah)
 {
         return ath5k_hw_reg_read(ah, AR5K_RXDP);
 }
 
 /**
- * ath5k_hw_set_rxdp - Set RX Descriptor's address
- *
+ * ath5k_hw_set_rxdp() - Set RX Descriptor's address
  * @ah: The &struct ath5k_hw
  * @phys_addr: RX descriptor address
  *
  * Returns -EIO if rx is active
  */
-int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
+int
+ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
 {
         if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {
                 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
@@ -114,8 +111,7 @@ int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
 \**********/
 
 /**
- * ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
- *
+ * ath5k_hw_start_tx_dma() - Start DMA transmit for a specific queue
  * @ah: The &struct ath5k_hw
  * @queue: The hw queue number
  *
@@ -128,7 +124,8 @@ int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
  * NOTE: Must be called after setting up tx control descriptor for that
  * queue (see below).
  */
-int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
+int
+ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 {
         u32 tx_queue;
 
@@ -177,17 +174,16 @@ int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 }
 
 /**
- * ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
- *
+ * ath5k_hw_stop_tx_dma() - Stop DMA transmit on a specific queue
  * @ah: The &struct ath5k_hw
  * @queue: The hw queue number
  *
  * Stop DMA transmit on a specific hw queue and drain queue so we don't
  * have any pending frames. Returns -EBUSY if we still have pending frames,
  * -EINVAL if queue number is out of range or inactive.
- *
  */
-static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
+static int
+ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 {
         unsigned int i = 40;
         u32 tx_queue, pending;
@@ -320,14 +316,14 @@ static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 }
 
 /**
- * ath5k_hw_stop_beacon_queue - Stop beacon queue
- *
- * @ah The &struct ath5k_hw
- * @queue The queue number
+ * ath5k_hw_stop_beacon_queue() - Stop beacon queue
+ * @ah: The &struct ath5k_hw
+ * @queue: The queue number
  *
  * Returns -EIO if queue didn't stop
  */
-int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
+int
+ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
 {
         int ret;
         ret = ath5k_hw_stop_tx_dma(ah, queue);
@@ -340,8 +336,7 @@ int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
 }
 
 /**
- * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
- *
+ * ath5k_hw_get_txdp() - Get TX Descriptor's address for a specific queue
  * @ah: The &struct ath5k_hw
  * @queue: The hw queue number
  *
@@ -352,7 +347,8 @@ int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
  *
  * XXX: Is TXDP read and clear ?
  */
-u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
+u32
+ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
 {
         u16 tx_reg;
 
@@ -382,10 +378,10 @@ u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
 }
 
 /**
- * ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
- *
+ * ath5k_hw_set_txdp() - Set TX Descriptor's address for a specific queue
  * @ah: The &struct ath5k_hw
  * @queue: The hw queue number
+ * @phys_addr: The physical address
  *
  * Set TX descriptor's address for a specific queue. For 5210 we ignore
  * the queue number and we use tx queue type since we only have 2 queues
@@ -394,7 +390,8 @@ u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
  * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still
  * active.
  */
-int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
+int
+ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
 {
         u16 tx_reg;
 
@@ -435,8 +432,7 @@ int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
 }
 
 /**
- * ath5k_hw_update_tx_triglevel - Update tx trigger level
- *
+ * ath5k_hw_update_tx_triglevel() - Update tx trigger level
  * @ah: The &struct ath5k_hw
  * @increase: Flag to force increase of trigger level
  *
@@ -444,15 +440,15 @@ int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
  * buffer (aka FIFO threshold) that is used to indicate when PCU flushes
  * the buffer and transmits its data. Lowering this results sending small
  * frames more quickly but can lead to tx underruns, raising it a lot can
- * result other problems (i think bmiss is related). Right now we start with
- * the lowest possible (64Bytes) and if we get tx underrun we increase it using
- * the increase flag. Returns -EIO if we have reached maximum/minimum.
+ * result other problems. Right now we start with the lowest possible
+ * (64Bytes) and if we get tx underrun we increase it using the increase
+ * flag. Returns -EIO if we have reached maximum/minimum.
  *
  * XXX: Link this with tx DMA size ?
- * XXX: Use it to save interrupts ?
- * TODO: Needs testing, i think it's related to bmiss...
+ * XXX2: Use it to save interrupts ?
  */
-int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
+int
+ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
 {
         u32 trigger_level, imr;
         int ret = -EIO;
@@ -498,21 +494,20 @@ done:
 \*******************/
 
 /**
- * ath5k_hw_is_intr_pending - Check if we have pending interrupts
- *
+ * ath5k_hw_is_intr_pending() - Check if we have pending interrupts
  * @ah: The &struct ath5k_hw
  *
  * Check if we have pending interrupts to process. Returns 1 if we
  * have pending interrupts and 0 if we haven't.
  */
-bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
+bool
+ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
 {
         return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
 }
 
 /**
- * ath5k_hw_get_isr - Get interrupt status
- *
+ * ath5k_hw_get_isr() - Get interrupt status
  * @ah: The @struct ath5k_hw
  * @interrupt_mask: Driver's interrupt mask used to filter out
  * interrupts in sw.
@@ -523,62 +518,162 @@ bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
  * being mapped on some standard non hw-specific positions
  * (check out &ath5k_int).
  *
- * NOTE: We use read-and-clear register, so after this function is called ISR
- * is zeroed.
+ * NOTE: We do write-to-clear, so the active PISR/SISR bits at the time this
+ * function gets called are cleared on return.
  */
-int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
+int
+ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
 {
-        u32 data;
+        u32 data = 0;
 
         /*
-         * Read interrupt status from the Interrupt Status register
-         * on 5210
+         * Read interrupt status from Primary Interrupt
+         * Register.
+         *
+         * Note: PISR/SISR Not available on 5210
          */
         if (ah->ah_version == AR5K_AR5210) {
-                data = ath5k_hw_reg_read(ah, AR5K_ISR);
-                if (unlikely(data == AR5K_INT_NOCARD)) {
-                        *interrupt_mask = data;
+                u32 isr = 0;
+                isr = ath5k_hw_reg_read(ah, AR5K_ISR);
+                if (unlikely(isr == AR5K_INT_NOCARD)) {
+                        *interrupt_mask = isr;
                         return -ENODEV;
                 }
-        } else {
+
                 /*
-                 * Read interrupt status from Interrupt
-                 * Status Register shadow copy (Read And Clear)
-                 *
-                 * Note: PISR/SISR Not available on 5210
+                 * Filter out the non-common bits from the interrupt
+                 * status.
                  */
-                data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
-                if (unlikely(data == AR5K_INT_NOCARD)) {
-                        *interrupt_mask = data;
+                *interrupt_mask = (isr & AR5K_INT_COMMON) & ah->ah_imr;
+
+                /* Hanlde INT_FATAL */
+                if (unlikely(isr & (AR5K_ISR_SSERR | AR5K_ISR_MCABT
+                                                | AR5K_ISR_DPERR)))
+                        *interrupt_mask |= AR5K_INT_FATAL;
+
+                /*
+                 * XXX: BMISS interrupts may occur after association.
+                 * I found this on 5210 code but it needs testing. If this is
+                 * true we should disable them before assoc and re-enable them
+                 * after a successful assoc + some jiffies.
+                        interrupt_mask &= ~AR5K_INT_BMISS;
+                 */
+
+                data = isr;
+        } else {
+                u32 pisr = 0;
+                u32 pisr_clear = 0;
+                u32 sisr0 = 0;
+                u32 sisr1 = 0;
+                u32 sisr2 = 0;
+                u32 sisr3 = 0;
+                u32 sisr4 = 0;
+
+                /* Read PISR and SISRs... */
+                pisr = ath5k_hw_reg_read(ah, AR5K_PISR);
+                if (unlikely(pisr == AR5K_INT_NOCARD)) {
+                        *interrupt_mask = pisr;
                         return -ENODEV;
                 }
-        }
 
-        /*
-         * Get abstract interrupt mask (driver-compatible)
-         */
-        *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
+                sisr0 = ath5k_hw_reg_read(ah, AR5K_SISR0);
+                sisr1 = ath5k_hw_reg_read(ah, AR5K_SISR1);
+                sisr2 = ath5k_hw_reg_read(ah, AR5K_SISR2);
+                sisr3 = ath5k_hw_reg_read(ah, AR5K_SISR3);
+                sisr4 = ath5k_hw_reg_read(ah, AR5K_SISR4);
 
-        if (ah->ah_version != AR5K_AR5210) {
-                u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2);
+                /*
+                 * PISR holds the logical OR of interrupt bits
+                 * from SISR registers:
+                 *
+                 * TXOK and TXDESC  -> Logical OR of TXOK and TXDESC
+                 *                      per-queue bits on SISR0
+                 *
+                 * TXERR and TXEOL -> Logical OR of TXERR and TXEOL
+                 *                      per-queue bits on SISR1
+                 *
+                 * TXURN -> Logical OR of TXURN per-queue bits on SISR2
+                 *
+                 * HIUERR -> Logical OR of MCABT, SSERR and DPER bits on SISR2
+                 *
+                 * BCNMISC -> Logical OR of TIM, CAB_END, DTIM_SYNC
+                 *              BCN_TIMEOUT, CAB_TIMEOUT and DTIM
+                 *              (and TSFOOR ?) bits on SISR2
+                 *
+                 * QCBRORN and QCBRURN -> Logical OR of QCBRORN and
+                 *                      QCBRURN per-queue bits on SISR3
+                 * QTRIG -> Logical OR of QTRIG per-queue bits on SISR4
+                 *
+                 * If we clean these bits on PISR we 'll also clear all
+                 * related bits from SISRs, e.g. if we write the TXOK bit on
+                 * PISR we 'll clean all TXOK bits from SISR0 so if a new TXOK
+                 * interrupt got fired for another queue while we were reading
+                 * the interrupt registers and we write back the TXOK bit on
+                 * PISR we 'll lose it. So make sure that we don't write back
+                 * on PISR any bits that come from SISRs. Clearing them from
+                 * SISRs will also clear PISR so no need to worry here.
+                 */
 
-                /*HIU = Host Interface Unit (PCI etc)*/
-                if (unlikely(data & (AR5K_ISR_HIUERR)))
-                        *interrupt_mask |= AR5K_INT_FATAL;
+                pisr_clear = pisr & ~AR5K_ISR_BITS_FROM_SISRS;
 
-                /*Beacon Not Ready*/
-                if (unlikely(data & (AR5K_ISR_BNR)))
-                        *interrupt_mask |= AR5K_INT_BNR;
+                /*
+                 * Write to clear them...
+                 * Note: This means that each bit we write back
+                 * to the registers will get cleared, leaving the
+                 * rest unaffected. So this won't affect new interrupts
+                 * we didn't catch while reading/processing, we 'll get
+                 * them next time get_isr gets called.
+                 */
+                ath5k_hw_reg_write(ah, sisr0, AR5K_SISR0);
+                ath5k_hw_reg_write(ah, sisr1, AR5K_SISR1);
+                ath5k_hw_reg_write(ah, sisr2, AR5K_SISR2);
+                ath5k_hw_reg_write(ah, sisr3, AR5K_SISR3);
+                ath5k_hw_reg_write(ah, sisr4, AR5K_SISR4);
+                ath5k_hw_reg_write(ah, pisr_clear, AR5K_PISR);
+                /* Flush previous write */
+                ath5k_hw_reg_read(ah, AR5K_PISR);
 
-                if (unlikely(sisr2 & (AR5K_SISR2_SSERR |
-                                        AR5K_SISR2_DPERR |
-                                        AR5K_SISR2_MCABT)))
-                        *interrupt_mask |= AR5K_INT_FATAL;
+                /*
+                 * Filter out the non-common bits from the interrupt
+                 * status.
+                 */
+                *interrupt_mask = (pisr & AR5K_INT_COMMON) & ah->ah_imr;
+
+
+                /* We treat TXOK,TXDESC, TXERR and TXEOL
+                 * the same way (schedule the tx tasklet)
+                 * so we track them all together per queue */
+                if (pisr & AR5K_ISR_TXOK)
+                        ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0,
+                                                AR5K_SISR0_QCU_TXOK);
 
-                if (data & AR5K_ISR_TIM)
+                if (pisr & AR5K_ISR_TXDESC)
+                        ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0,
+                                                AR5K_SISR0_QCU_TXDESC);
+
+                if (pisr & AR5K_ISR_TXERR)
+                        ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1,
+                                                AR5K_SISR1_QCU_TXERR);
+
+                if (pisr & AR5K_ISR_TXEOL)
+                        ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1,
+                                                AR5K_SISR1_QCU_TXEOL);
+
+                /* Currently this is not much usefull since we treat
+                 * all queues the same way if we get a TXURN (update
+                 * tx trigger level) but we might need it later on*/
+                if (pisr & AR5K_ISR_TXURN)
+                        ah->ah_txq_isr_txurn |= AR5K_REG_MS(sisr2,
+                                                AR5K_SISR2_QCU_TXURN);
+
+                /* Misc Beacon related interrupts */
+
+                /* For AR5211 */
+                if (pisr & AR5K_ISR_TIM)
                         *interrupt_mask |= AR5K_INT_TIM;
 
-                if (data & AR5K_ISR_BCNMISC) {
+                /* For AR5212+ */
+                if (pisr & AR5K_ISR_BCNMISC) {
                         if (sisr2 & AR5K_SISR2_TIM)
                                 *interrupt_mask |= AR5K_INT_TIM;
                         if (sisr2 & AR5K_SISR2_DTIM)
@@ -591,63 +686,39 @@ int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
                                 *interrupt_mask |= AR5K_INT_CAB_TIMEOUT;
                 }
 
-                if (data & AR5K_ISR_RXDOPPLER)
-                        *interrupt_mask |= AR5K_INT_RX_DOPPLER;
-                if (data & AR5K_ISR_QCBRORN) {
+                /* Below interrupts are unlikely to happen */
+
+                /* HIU = Host Interface Unit (PCI etc)
+                 * Can be one of MCABT, SSERR, DPERR from SISR2 */
+                if (unlikely(pisr & (AR5K_ISR_HIUERR)))
+                        *interrupt_mask |= AR5K_INT_FATAL;
+
+                /*Beacon Not Ready*/
+                if (unlikely(pisr & (AR5K_ISR_BNR)))
+                        *interrupt_mask |= AR5K_INT_BNR;
+
+                /* A queue got CBR overrun */
+                if (unlikely(pisr & (AR5K_ISR_QCBRORN))) {
                         *interrupt_mask |= AR5K_INT_QCBRORN;
-                        ah->ah_txq_isr |= AR5K_REG_MS(
-                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
-                                        AR5K_SISR3_QCBRORN);
+                        ah->ah_txq_isr_qcborn |= AR5K_REG_MS(sisr3,
+                                                AR5K_SISR3_QCBRORN);
                 }
-                if (data & AR5K_ISR_QCBRURN) {
+
+                /* A queue got CBR underrun */
+                if (unlikely(pisr & (AR5K_ISR_QCBRURN))) {
                         *interrupt_mask |= AR5K_INT_QCBRURN;
-                        ah->ah_txq_isr |= AR5K_REG_MS(
-                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
-                                        AR5K_SISR3_QCBRURN);
+                        ah->ah_txq_isr_qcburn |= AR5K_REG_MS(sisr3,
+                                                AR5K_SISR3_QCBRURN);
                 }
-                if (data & AR5K_ISR_QTRIG) {
+
+                /* A queue got triggered */
+                if (unlikely(pisr & (AR5K_ISR_QTRIG))) {
                         *interrupt_mask |= AR5K_INT_QTRIG;
-                        ah->ah_txq_isr |= AR5K_REG_MS(
-                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR4),
-                                        AR5K_SISR4_QTRIG);
+                        ah->ah_txq_isr_qtrig |= AR5K_REG_MS(sisr4,
+                                                AR5K_SISR4_QTRIG);
                 }
 
-                if (data & AR5K_ISR_TXOK)
-                        ah->ah_txq_isr |= AR5K_REG_MS(
-                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
-                                        AR5K_SISR0_QCU_TXOK);
-
-                if (data & AR5K_ISR_TXDESC)
-                        ah->ah_txq_isr |= AR5K_REG_MS(
-                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
-                                        AR5K_SISR0_QCU_TXDESC);
-
-                if (data & AR5K_ISR_TXERR)
-                        ah->ah_txq_isr |= AR5K_REG_MS(
-                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
-                                        AR5K_SISR1_QCU_TXERR);
-
-                if (data & AR5K_ISR_TXEOL)
-                        ah->ah_txq_isr |= AR5K_REG_MS(
-                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
-                                        AR5K_SISR1_QCU_TXEOL);
-
-                if (data & AR5K_ISR_TXURN)
-                        ah->ah_txq_isr |= AR5K_REG_MS(
-                                        ath5k_hw_reg_read(ah, AR5K_RAC_SISR2),
-                                        AR5K_SISR2_QCU_TXURN);
-        } else {
-                if (unlikely(data & (AR5K_ISR_SSERR | AR5K_ISR_MCABT
-                                | AR5K_ISR_HIUERR | AR5K_ISR_DPERR)))
-                        *interrupt_mask |= AR5K_INT_FATAL;
-
-                /*
-                 * XXX: BMISS interrupts may occur after association.
-                 * I found this on 5210 code but it needs testing. If this is
-                 * true we should disable them before assoc and re-enable them
-                 * after a successful assoc + some jiffies.
-                        interrupt_mask &= ~AR5K_INT_BMISS;
-                 */
+                data = pisr;
         }
 
         /*
@@ -661,8 +732,7 @@ int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
 }
 
 /**
- * ath5k_hw_set_imr - Set interrupt mask
- *
+ * ath5k_hw_set_imr() - Set interrupt mask
  * @ah: The &struct ath5k_hw
  * @new_mask: The new interrupt mask to be set
  *
@@ -670,7 +740,8 @@ int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
  * ath5k_int bits to hw-specific bits to remove abstraction and writing
  * Interrupt Mask Register.
  */
-enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
+enum ath5k_int
+ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
 {
         enum ath5k_int old_mask, int_mask;
 
@@ -697,16 +768,14 @@ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
                 u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2)
                                 & AR5K_SIMR2_QCU_TXURN;
 
+                /* Fatal interrupt abstraction for 5211+ */
                 if (new_mask & AR5K_INT_FATAL) {
                         int_mask |= AR5K_IMR_HIUERR;
                         simr2 |= (AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR
                                 | AR5K_SIMR2_DPERR);
                 }
 
-                /*Beacon Not Ready*/
-                if (new_mask & AR5K_INT_BNR)
-                        int_mask |= AR5K_INT_BNR;
-
+                /* Misc beacon related interrupts */
                 if (new_mask & AR5K_INT_TIM)
                         int_mask |= AR5K_IMR_TIM;
 
@@ -721,8 +790,9 @@ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
                 if (new_mask & AR5K_INT_CAB_TIMEOUT)
                         simr2 |= AR5K_SISR2_CAB_TIMEOUT;
 
-                if (new_mask & AR5K_INT_RX_DOPPLER)
-                        int_mask |= AR5K_IMR_RXDOPPLER;
+                /*Beacon Not Ready*/
+                if (new_mask & AR5K_INT_BNR)
+                        int_mask |= AR5K_INT_BNR;
 
                 /* Note: Per queue interrupt masks
                  * are set via ath5k_hw_reset_tx_queue() (qcu.c) */
@@ -730,10 +800,12 @@ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
                 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);
 
         } else {
+                /* Fatal interrupt abstraction for 5210 */
                 if (new_mask & AR5K_INT_FATAL)
                         int_mask |= (AR5K_IMR_SSERR | AR5K_IMR_MCABT
                                 | AR5K_IMR_HIUERR | AR5K_IMR_DPERR);
 
+                /* Only common interrupts left for 5210 (no SIMRs) */
                 ath5k_hw_reg_write(ah, int_mask, AR5K_IMR);
         }
 
@@ -760,8 +832,7 @@ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
 \********************/
 
 /**
- * ath5k_hw_dma_init - Initialize DMA unit
- *
+ * ath5k_hw_dma_init() - Initialize DMA unit
  * @ah: The &struct ath5k_hw
  *
  * Set DMA size and pre-enable interrupts
@@ -770,7 +841,8 @@ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
  *
  * XXX: Save/restore RXDP/TXDP registers ?
  */
-void ath5k_hw_dma_init(struct ath5k_hw *ah)
+void
+ath5k_hw_dma_init(struct ath5k_hw *ah)
 {
         /*
          * Set Rx/Tx DMA Configuration
@@ -799,8 +871,7 @@ void ath5k_hw_dma_init(struct ath5k_hw *ah)
 }
 
 /**
- * ath5k_hw_dma_stop - stop DMA unit
- *
+ * ath5k_hw_dma_stop() - stop DMA unit
  * @ah: The &struct ath5k_hw
  *
  * Stop tx/rx DMA and interrupts. Returns
@@ -810,7 +881,8 @@ void ath5k_hw_dma_init(struct ath5k_hw *ah)
  * stuck frames on tx queues, only a reset
  * can fix that.
  */
-int ath5k_hw_dma_stop(struct ath5k_hw *ah)
+int
+ath5k_hw_dma_stop(struct ath5k_hw *ah)
 {
         int i, qmax, err;
         err = 0;
diff --git a/drivers/net/wireless/ath/ath5k/gpio.c b/drivers/net/wireless/ath/ath5k/gpio.c
index 859297811914..73d3dd8a306a 100644
--- a/drivers/net/wireless/ath/ath5k/gpio.c
+++ b/drivers/net/wireless/ath/ath5k/gpio.c
@@ -24,10 +24,33 @@
 #include "reg.h"
 #include "debug.h"
 
-/*
- * Set led state
+
+/**
+ * DOC: GPIO/LED functions
+ *
+ * Here we control the 6 bidirectional GPIO pins provided by the hw.
+ * We can set a GPIO pin to be an input or an output pin on GPIO control
+ * register and then read or set its status from GPIO data input/output
+ * registers.
+ *
+ * We also control the two LED pins provided by the hw, LED_0 is our
+ * "power" LED and LED_1 is our "network activity" LED but many scenarios
+ * are available from hw. Vendors might also provide LEDs connected to the
+ * GPIO pins, we handle them through the LED subsystem on led.c
+ */
+
+
+/**
+ * ath5k_hw_set_ledstate() - Set led state
+ * @ah: The &struct ath5k_hw
+ * @state: One of AR5K_LED_*
+ *
+ * Used to set the LED blinking state. This only
+ * works for the LED connected to the LED_0, LED_1 pins,
+ * not the GPIO based.
  */
-void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
+void
+ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
 {
         u32 led;
         /*5210 has different led mode handling*/
@@ -74,10 +97,13 @@ void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
                 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
 }
 
-/*
- * Set GPIO inputs
+/**
+ * ath5k_hw_set_gpio_input() - Set GPIO inputs
+ * @ah: The &struct ath5k_hw
+ * @gpio: GPIO pin to set as input
  */
-int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
+int
+ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
 {
         if (gpio >= AR5K_NUM_GPIO)
                 return -EINVAL;
@@ -89,10 +115,13 @@ int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
         return 0;
 }
 
-/*
- * Set GPIO outputs
+/**
+ * ath5k_hw_set_gpio_output() - Set GPIO outputs
+ * @ah: The &struct ath5k_hw
+ * @gpio: The GPIO pin to set as output
  */
-int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
+int
+ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
 {
         if (gpio >= AR5K_NUM_GPIO)
                 return -EINVAL;
@@ -104,10 +133,13 @@ int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
         return 0;
 }
 
-/*
- * Get GPIO state
+/**
+ * ath5k_hw_get_gpio() - Get GPIO state
+ * @ah: The &struct ath5k_hw
+ * @gpio: The GPIO pin to read
  */
-u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
+u32
+ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
 {
         if (gpio >= AR5K_NUM_GPIO)
                 return 0xffffffff;
@@ -117,10 +149,14 @@ u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
                 0x1;
 }
 
-/*
- * Set GPIO state
+/**
+ * ath5k_hw_set_gpio() - Set GPIO state
+ * @ah: The &struct ath5k_hw
+ * @gpio: The GPIO pin to set
+ * @val: Value to set (boolean)
  */
-int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
+int
+ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
 {
         u32 data;
 
@@ -138,10 +174,19 @@ int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
         return 0;
 }
 
-/*
- * Initialize the GPIO interrupt (RFKill switch)
+/**
+ * ath5k_hw_set_gpio_intr() - Initialize the GPIO interrupt (RFKill switch)
+ * @ah: The &struct ath5k_hw
+ * @gpio: The GPIO pin to use
+ * @interrupt_level: True to generate interrupt on active pin (high)
+ *
+ * This function is used to set up the GPIO interrupt for the hw RFKill switch.
+ * That switch is connected to a GPIO pin and it's number is stored on EEPROM.
+ * It can either open or close the circuit to indicate that we should disable
+ * RF/Wireless to save power (we also get that from EEPROM).
  */
-void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
+void
+ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
                 u32 interrupt_level)
 {
         u32 data;
diff --git a/drivers/net/wireless/ath/ath5k/initvals.c b/drivers/net/wireless/ath/ath5k/initvals.c
index 1ffecc0fd3ed..a1ea78e05b47 100644
--- a/drivers/net/wireless/ath/ath5k/initvals.c
+++ b/drivers/net/wireless/ath/ath5k/initvals.c
@@ -23,24 +23,27 @@
 #include "reg.h"
 #include "debug.h"
 
-/*
- * Mode-independent initial register writes
+/**
+ * struct ath5k_ini - Mode-independent initial register writes
+ * @ini_register: Register address
+ * @ini_value: Default value
+ * @ini_mode: 0 to write 1 to read (and clear)
  */
-
 struct ath5k_ini {
         u16     ini_register;
         u32     ini_value;
 
         enum {
                 AR5K_INI_WRITE = 0,     /* Default */
-                AR5K_INI_READ = 1,      /* Cleared on read */
+                AR5K_INI_READ = 1,
         } ini_mode;
 };
 
-/*
- * Mode specific initial register values
+/**
+ * struct ath5k_ini_mode - Mode specific initial register values
+ * @mode_register: Register address
+ * @mode_value: Set of values for each enum ath5k_driver_mode
  */
-
 struct ath5k_ini_mode {
         u16     mode_register;
         u32     mode_value[3];
@@ -386,11 +389,10 @@ static const struct ath5k_ini ar5211_ini[] = {
 
 /* Initial mode-specific settings for AR5211
  * 5211 supports OFDM-only g (draft g) but we
- * need to test it !
- */
+ * need to test it ! */
 static const struct ath5k_ini_mode ar5211_ini_mode[] = {
         { AR5K_TXCFG,
-        /*      A/XR          B           G       */
+        /*      A          B           G       */
            { 0x00000015, 0x0000001d, 0x00000015 } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
            { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
@@ -460,7 +462,7 @@ static const struct ath5k_ini_mode ar5211_ini_mode[] = {
            { 0x00000010, 0x00000010, 0x00000010 } },
 };
 
-/* Initial register settings for AR5212 */
+/* Initial register settings for AR5212 and newer chips */
 static const struct ath5k_ini ar5212_ini_common_start[] = {
         { AR5K_RXDP,            0x00000000 },
         { AR5K_RXCFG,           0x00000005 },
@@ -724,7 +726,8 @@ static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
            { 0x00000000, 0x00000000, 0x00000108 } },
 };
 
-/* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
+/* Initial mode-specific settings for AR5212 + RF5111
+ * (Written after ar5212_ini) */
 static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
         { AR5K_TXCFG,
         /*      A/XR          B           G       */
@@ -757,6 +760,7 @@ static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
            { 0x1883800a, 0x1873800a, 0x1883800a } },
 };
 
+/* Common for all modes */
 static const struct ath5k_ini rf5111_ini_common_end[] = {
         { AR5K_DCU_FP,          0x00000000 },
         { AR5K_PHY_AGC,         0x00000000 },
@@ -774,7 +778,9 @@ static const struct ath5k_ini rf5111_ini_common_end[] = {
         { 0xa23c,               0x13c889af },
 };
 
-/* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
+
+/* Initial mode-specific settings for AR5212 + RF5112
+ * (Written after ar5212_ini) */
 static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
         { AR5K_TXCFG,
         /*      A/XR          B           G       */
@@ -825,7 +831,9 @@ static const struct ath5k_ini rf5112_ini_common_end[] = {
         { 0xa23c,               0x13c889af },
 };
 
-/* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
+
+/* Initial mode-specific settings for RF5413/5414
+ * (Written after ar5212_ini) */
 static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
         { AR5K_TXCFG,
         /*      A/XR          B           G       */
@@ -963,7 +971,8 @@ static const struct ath5k_ini rf5413_ini_common_end[] = {
         { 0xa384, 0xf3307ff0 },
 };
 
-/* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */
+/* Initial mode-specific settings for RF2413/2414
+ * (Written after ar5212_ini) */
 /* XXX: a mode ? */
 static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
         { AR5K_TXCFG,
@@ -1085,7 +1094,8 @@ static const struct ath5k_ini rf2413_ini_common_end[] = {
         { 0xa384, 0xf3307ff0 },
 };
 
-/* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */
+/* Initial mode-specific settings for RF2425
+ * (Written after ar5212_ini) */
 /* XXX: a mode ? */
 static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
         { AR5K_TXCFG,
@@ -1357,10 +1367,15 @@ static const struct ath5k_ini rf5112_ini_bbgain[] = {
 };
 
 
-/*
- * Write initial register dump
+/**
+ * ath5k_hw_ini_registers() - Write initial register dump common for all modes
+ * @ah: The &struct ath5k_hw
+ * @size: Dump size
+ * @ini_regs: The array of &struct ath5k_ini
+ * @skip_pcu: Skip PCU registers
  */
-static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
+static void
+ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
                 const struct ath5k_ini *ini_regs, bool skip_pcu)
 {
         unsigned int i;
@@ -1388,7 +1403,15 @@ static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
         }
 }
 
-static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
+/**
+ * ath5k_hw_ini_mode_registers() - Write initial mode-specific register dump
+ * @ah: The &struct ath5k_hw
+ * @size: Dump size
+ * @ini_mode: The array of &struct ath5k_ini_mode
+ * @mode: One of enum ath5k_driver_mode
+ */
+static void
+ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
                 unsigned int size, const struct ath5k_ini_mode *ini_mode,
                 u8 mode)
 {
@@ -1402,7 +1425,17 @@ static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
 
 }
 
-int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
+/**
+ * ath5k_hw_write_initvals() - Write initial chip-specific register dump
+ * @ah: The &struct ath5k_hw
+ * @mode: One of enum ath5k_driver_mode
+ * @skip_pcu: Skip PCU registers
+ *
+ * Write initial chip-specific register dump, to get the chipset on a
+ * clean and ready-to-work state after warm reset.
+ */
+int
+ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
 {
         /*
          * Write initial register settings
diff --git a/drivers/net/wireless/ath/ath5k/pci.c b/drivers/net/wireless/ath/ath5k/pci.c
index c1dff2ced044..849fa060ebc4 100644
--- a/drivers/net/wireless/ath/ath5k/pci.c
+++ b/drivers/net/wireless/ath/ath5k/pci.c
@@ -18,6 +18,7 @@
 #include <linux/pci.h>
 #include <linux/pci-aspm.h>
 #include <linux/etherdevice.h>
+#include <linux/module.h>
 #include "../ath.h"
 #include "ath5k.h"
 #include "debug.h"
@@ -97,7 +98,7 @@ ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
                                         0xffff);
                         return true;
                 }
-                udelay(15);
+                usleep_range(15, 20);
         }
 
         return false;
diff --git a/drivers/net/wireless/ath/ath5k/pcu.c b/drivers/net/wireless/ath/ath5k/pcu.c
index a7eafa3edc21..cebfd6fd31d3 100644
--- a/drivers/net/wireless/ath/ath5k/pcu.c
+++ b/drivers/net/wireless/ath/ath5k/pcu.c
@@ -30,11 +30,47 @@
 #include "reg.h"
 #include "debug.h"
 
-/*
+/**
+ * DOC: Protocol Control Unit (PCU) functions
+ *
+ * Protocol control unit is responsible to maintain various protocol
+ * properties before a frame is send and after a frame is received to/from
+ * baseband. To be more specific, PCU handles:
+ *
+ * - Buffering of RX and TX frames (after QCU/DCUs)
+ *
+ * - Encrypting and decrypting (using the built-in engine)
+ *
+ * - Generating ACKs, RTS/CTS frames
+ *
+ * - Maintaining TSF
+ *
+ * - FCS
+ *
+ * - Updating beacon data (with TSF etc)
+ *
+ * - Generating virtual CCA
+ *
+ * - RX/Multicast filtering
+ *
+ * - BSSID filtering
+ *
+ * - Various statistics
+ *
+ * -Different operating modes: AP, STA, IBSS
+ *
+ * Note: Most of these functions can be tweaked/bypassed so you can do
+ * them on sw above for debugging or research. For more infos check out PCU
+ * registers on reg.h.
+ */
+
+/**
+ * DOC: ACK rates
+ *
  * AR5212+ can use higher rates for ack transmission
  * based on current tx rate instead of the base rate.
  * It does this to better utilize channel usage.
- * This is a mapping between G rates (that cover both
+ * There is a mapping between G rates (that cover both
  * CCK and OFDM) and ack rates that we use when setting
  * rate -> duration table. This mapping is hw-based so
  * don't change anything.
@@ -63,17 +99,18 @@ static const unsigned int ack_rates_high[] =
 \*******************/
 
 /**
- * ath5k_hw_get_frame_duration - Get tx time of a frame
- *
+ * ath5k_hw_get_frame_duration() - Get tx time of a frame
  * @ah: The &struct ath5k_hw
  * @len: Frame's length in bytes
  * @rate: The @struct ieee80211_rate
+ * @shortpre: Indicate short preample
  *
  * Calculate tx duration of a frame given it's rate and length
  * It extends ieee80211_generic_frame_duration for non standard
  * bwmodes.
  */
-int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
+int
+ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
                 int len, struct ieee80211_rate *rate, bool shortpre)
 {
         int sifs, preamble, plcp_bits, sym_time;
@@ -129,11 +166,11 @@ int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
 }
 
 /**
- * ath5k_hw_get_default_slottime - Get the default slot time for current mode
- *
+ * ath5k_hw_get_default_slottime() - Get the default slot time for current mode
  * @ah: The &struct ath5k_hw
  */
-unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
+unsigned int
+ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
 {
         struct ieee80211_channel *channel = ah->ah_current_channel;
         unsigned int slot_time;
@@ -160,11 +197,11 @@ unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
 }
 
 /**
- * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
- *
+ * ath5k_hw_get_default_sifs() - Get the default SIFS for current mode
  * @ah: The &struct ath5k_hw
  */
-unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
+unsigned int
+ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
 {
         struct ieee80211_channel *channel = ah->ah_current_channel;
         unsigned int sifs;
@@ -191,17 +228,17 @@ unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
 }
 
 /**
- * ath5k_hw_update_mib_counters - Update MIB counters (mac layer statistics)
- *
+ * ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics)
  * @ah: The &struct ath5k_hw
  *
  * Reads MIB counters from PCU and updates sw statistics. Is called after a
  * MIB interrupt, because one of these counters might have reached their maximum
  * and triggered the MIB interrupt, to let us read and clear the counter.
  *
- * Is called in interrupt context!
+ * NOTE: Is called in interrupt context!
  */
-void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
+void
+ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
 {
         struct ath5k_statistics *stats = &ah->stats;
 
@@ -219,10 +256,8 @@ void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
 \******************/
 
 /**
- * ath5k_hw_write_rate_duration - fill rate code to duration table
- *
- * @ah: the &struct ath5k_hw
- * @mode: one of enum ath5k_driver_mode
+ * ath5k_hw_write_rate_duration() - Fill rate code to duration table
+ * @ah: The &struct ath5k_hw
  *
  * Write the rate code to duration table upon hw reset. This is a helper for
  * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on
@@ -236,7 +271,8 @@ void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
  * that include all OFDM and CCK rates.
  *
  */
-static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
+static inline void
+ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
 {
         struct ieee80211_rate *rate;
         unsigned int i;
@@ -280,12 +316,12 @@ static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
 }
 
 /**
- * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
- *
+ * ath5k_hw_set_ack_timeout() - Set ACK timeout on PCU
  * @ah: The &struct ath5k_hw
  * @timeout: Timeout in usec
  */
-static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
+static int
+ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
 {
         if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
                         <= timeout)
@@ -298,12 +334,12 @@ static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
 }
 
 /**
- * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
- *
+ * ath5k_hw_set_cts_timeout() - Set CTS timeout on PCU
  * @ah: The &struct ath5k_hw
  * @timeout: Timeout in usec
  */
-static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
+static int
+ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
 {
         if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
                         <= timeout)
@@ -321,14 +357,14 @@ static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
 \*******************/
 
 /**
- * ath5k_hw_set_lladdr - Set station id
- *
+ * ath5k_hw_set_lladdr() - Set station id
  * @ah: The &struct ath5k_hw
- * @mac: The card's mac address
+ * @mac: The card's mac address (array of octets)
  *
  * Set station id on hw using the provided mac address
  */
-int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
+int
+ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
 {
         struct ath_common *common = ath5k_hw_common(ah);
         u32 low_id, high_id;
@@ -349,14 +385,14 @@ int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
 }
 
 /**
- * ath5k_hw_set_bssid - Set current BSSID on hw
- *
+ * ath5k_hw_set_bssid() - Set current BSSID on hw
  * @ah: The &struct ath5k_hw
  *
  * Sets the current BSSID and BSSID mask we have from the
  * common struct into the hardware
  */
-void ath5k_hw_set_bssid(struct ath5k_hw *ah)
+void
+ath5k_hw_set_bssid(struct ath5k_hw *ah)
 {
         struct ath_common *common = ath5k_hw_common(ah);
         u16 tim_offset = 0;
@@ -389,7 +425,23 @@ void ath5k_hw_set_bssid(struct ath5k_hw *ah)
         ath5k_hw_enable_pspoll(ah, NULL, 0);
 }
 
-void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
+/**
+ * ath5k_hw_set_bssid_mask() - Filter out bssids we listen
+ * @ah: The &struct ath5k_hw
+ * @mask: The BSSID mask to set (array of octets)
+ *
+ * BSSID masking is a method used by AR5212 and newer hardware to inform PCU
+ * which bits of the interface's MAC address should be looked at when trying
+ * to decide which packets to ACK. In station mode and AP mode with a single
+ * BSS every bit matters since we lock to only one BSS. In AP mode with
+ * multiple BSSes (virtual interfaces) not every bit matters because hw must
+ * accept frames for all BSSes and so we tweak some bits of our mac address
+ * in order to have multiple BSSes.
+ *
+ * For more information check out ../hw.c of the common ath module.
+ */
+void
+ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
 {
         struct ath_common *common = ath5k_hw_common(ah);
 
@@ -400,18 +452,21 @@ void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
                 ath_hw_setbssidmask(common);
 }
 
-/*
- * Set multicast filter
+/**
+ * ath5k_hw_set_mcast_filter() - Set multicast filter
+ * @ah: The &struct ath5k_hw
+ * @filter0: Lower 32bits of muticast filter
+ * @filter1: Higher 16bits of multicast filter
  */
-void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
+void
+ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
 {
         ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
         ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
 }
 
 /**
- * ath5k_hw_get_rx_filter - Get current rx filter
- *
+ * ath5k_hw_get_rx_filter() - Get current rx filter
  * @ah: The &struct ath5k_hw
  *
  * Returns the RX filter by reading rx filter and
@@ -420,7 +475,8 @@ void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
  * and pass to the driver. For a list of frame types
  * check out reg.h.
  */
-u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
+u32
+ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
 {
         u32 data, filter = 0;
 
@@ -440,8 +496,7 @@ u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
 }
 
 /**
- * ath5k_hw_set_rx_filter - Set rx filter
- *
+ * ath5k_hw_set_rx_filter() - Set rx filter
  * @ah: The &struct ath5k_hw
  * @filter: RX filter mask (see reg.h)
  *
@@ -449,7 +504,8 @@ u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
  * register on 5212 and newer chips so that we have proper PHY
  * error reporting.
  */
-void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
+void
+ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
 {
         u32 data = 0;
 
@@ -493,13 +549,13 @@ void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
 #define ATH5K_MAX_TSF_READ 10
 
 /**
- * ath5k_hw_get_tsf64 - Get the full 64bit TSF
- *
+ * ath5k_hw_get_tsf64() - Get the full 64bit TSF
  * @ah: The &struct ath5k_hw
  *
  * Returns the current TSF
  */
-u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
+u64
+ath5k_hw_get_tsf64(struct ath5k_hw *ah)
 {
         u32 tsf_lower, tsf_upper1, tsf_upper2;
         int i;
@@ -536,28 +592,30 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
         return ((u64)tsf_upper1 << 32) | tsf_lower;
 }
 
+#undef ATH5K_MAX_TSF_READ
+
 /**
- * ath5k_hw_set_tsf64 - Set a new 64bit TSF
- *
+ * ath5k_hw_set_tsf64() - Set a new 64bit TSF
  * @ah: The &struct ath5k_hw
  * @tsf64: The new 64bit TSF
  *
  * Sets the new TSF
  */
-void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
+void
+ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
 {
         ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
         ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
 }
 
 /**
- * ath5k_hw_reset_tsf - Force a TSF reset
- *
+ * ath5k_hw_reset_tsf() - Force a TSF reset
  * @ah: The &struct ath5k_hw
  *
  * Forces a TSF reset on PCU
  */
-void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
+void
+ath5k_hw_reset_tsf(struct ath5k_hw *ah)
 {
         u32 val;
 
@@ -573,10 +631,17 @@ void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
         ath5k_hw_reg_write(ah, val, AR5K_BEACON);
 }
 
-/*
- * Initialize beacon timers
+/**
+ * ath5k_hw_init_beacon_timers() - Initialize beacon timers
+ * @ah: The &struct ath5k_hw
+ * @next_beacon: Next TBTT
+ * @interval: Current beacon interval
+ *
+ * This function is used to initialize beacon timers based on current
+ * operation mode and settings.
  */
-void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
+void
+ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
 {
         u32 timer1, timer2, timer3;
 
@@ -655,8 +720,7 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
 }
 
 /**
- * ath5k_check_timer_win - Check if timer B is timer A + window
- *
+ * ath5k_check_timer_win() - Check if timer B is timer A + window
  * @a: timer a (before b)
  * @b: timer b (after a)
  * @window: difference between a and b
@@ -686,12 +750,11 @@ ath5k_check_timer_win(int a, int b, int window, int intval)
 }
 
 /**
- * ath5k_hw_check_beacon_timers - Check if the beacon timers are correct
- *
+ * ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct
  * @ah: The &struct ath5k_hw
  * @intval: beacon interval
  *
- * This is a workaround for IBSS mode:
+ * This is a workaround for IBSS mode
  *
  * The need for this function arises from the fact that we have 4 separate
  * HW timer registers (TIMER0 - TIMER3), which are closely related to the
@@ -746,14 +809,14 @@ ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)
 }
 
 /**
- * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class
- *
+ * ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class
  * @ah: The &struct ath5k_hw
  * @coverage_class: IEEE 802.11 coverage class number
  *
  * Sets IFS intervals and ACK/CTS timeouts for given coverage class.
  */
-void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
+void
+ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
 {
         /* As defined by IEEE 802.11-2007 17.3.8.6 */
         int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
@@ -772,8 +835,7 @@ void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
 \***************************/
 
 /**
- * ath5k_hw_start_rx_pcu - Start RX engine
- *
+ * ath5k_hw_start_rx_pcu() - Start RX engine
  * @ah: The &struct ath5k_hw
  *
  * Starts RX engine on PCU so that hw can process RXed frames
@@ -781,32 +843,33 @@ void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
  *
  * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
  */
-void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
+void
+ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
 {
         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
 }
 
 /**
- * at5k_hw_stop_rx_pcu - Stop RX engine
- *
+ * at5k_hw_stop_rx_pcu() - Stop RX engine
  * @ah: The &struct ath5k_hw
  *
  * Stops RX engine on PCU
  */
-void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
+void
+ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
 {
         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
 }
 
 /**
- * ath5k_hw_set_opmode - Set PCU operating mode
- *
+ * ath5k_hw_set_opmode() - Set PCU operating mode
  * @ah: The &struct ath5k_hw
- * @op_mode: &enum nl80211_iftype operating mode
+ * @op_mode: One of enum nl80211_iftype
  *
  * Configure PCU for the various operating modes (AP/STA etc)
  */
-int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
+int
+ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
 {
         struct ath_common *common = ath5k_hw_common(ah);
         u32 pcu_reg, beacon_reg, low_id, high_id;
@@ -873,8 +936,17 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
         return 0;
 }
 
-void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
-                                                                u8 mode)
+/**
+ * ath5k_hw_pcu_init() - Initialize PCU
+ * @ah: The &struct ath5k_hw
+ * @op_mode: One of enum nl80211_iftype
+ * @mode: One of enum ath5k_driver_mode
+ *
+ * This function is used to initialize PCU by setting current
+ * operation mode and various other settings.
+ */
+void
+ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
 {
         /* Set bssid and bssid mask */
         ath5k_hw_set_bssid(ah);
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index 01cb72de44cb..e1f8613426a9 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -1,6 +1,4 @@
 /*
- * PHY functions
- *
  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
@@ -20,6 +18,10 @@
  *
  */
 
+/***********************\
+* PHY related functions *
+\***********************/
+
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <asm/unaligned.h>
@@ -31,14 +33,53 @@
 #include "../regd.h"
 
 
+/**
+ * DOC: PHY related functions
+ *
+ * Here we handle the low-level functions related to baseband
+ * and analog frontend (RF) parts. This is by far the most complex
+ * part of the hw code so make sure you know what you are doing.
+ *
+ * Here is a list of what this is all about:
+ *
+ * - Channel setting/switching
+ *
+ * - Automatic Gain Control (AGC) calibration
+ *
+ * - Noise Floor calibration
+ *
+ * - I/Q imbalance calibration (QAM correction)
+ *
+ * - Calibration due to thermal changes (gain_F)
+ *
+ * - Spur noise mitigation
+ *
+ * - RF/PHY initialization for the various operating modes and bwmodes
+ *
+ * - Antenna control
+ *
+ * - TX power control per channel/rate/packet type
+ *
+ * Also have in mind we never got documentation for most of these
+ * functions, what we have comes mostly from Atheros's code, reverse
+ * engineering and patent docs/presentations etc.
+ */
+
+
 /******************\
 * Helper functions *
 \******************/
 
-/*
- * Get the PHY Chip revision
+/**
+ * ath5k_hw_radio_revision() - Get the PHY Chip revision
+ * @ah: The &struct ath5k_hw
+ * @band: One of enum ieee80211_band
+ *
+ * Returns the revision number of a 2GHz, 5GHz or single chip
+ * radio.
  */
-u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band)
+u16
+ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band)
 {
         unsigned int i;
         u32 srev;
@@ -58,7 +99,7 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band)
                 return 0;
         }
 
-        mdelay(2);
+        usleep_range(2000, 2500);
 
         /* ...wait until PHY is ready and read the selected radio revision */
         ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
@@ -81,10 +122,16 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band)
         return ret;
 }
 
-/*
- * Check if a channel is supported
+/**
+ * ath5k_channel_ok() - Check if a channel is supported by the hw
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ *
+ * Note: We don't do any regulatory domain checks here, it's just
+ * a sanity check.
  */
-bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel)
+bool
+ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel)
 {
         u16 freq = channel->center_freq;
 
@@ -101,7 +148,13 @@ bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel)
         return false;
 }
 
-bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
+/**
+ * ath5k_hw_chan_has_spur_noise() - Check if channel is sensitive to spur noise
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ */
+bool
+ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
                                 struct ieee80211_channel *channel)
 {
         u8 refclk_freq;
@@ -122,11 +175,20 @@ bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
                 return false;
 }
 
-/*
- * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
+/**
+ * ath5k_hw_rfb_op() - Perform an operation on the given RF Buffer
+ * @ah: The &struct ath5k_hw
+ * @rf_regs: The struct ath5k_rf_reg
+ * @val: New value
+ * @reg_id: RF register ID
+ * @set: Indicate we need to swap data
+ *
+ * This is an internal function used to modify RF Banks before
+ * writing them to AR5K_RF_BUFFER. Check out rfbuffer.h for more
+ * infos.
  */
-static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
-                                        const struct ath5k_rf_reg *rf_regs,
+static unsigned int
+ath5k_hw_rfb_op(struct ath5k_hw *ah, const struct ath5k_rf_reg *rf_regs,
                                         u32 val, u8 reg_id, bool set)
 {
         const struct ath5k_rf_reg *rfreg = NULL;
@@ -204,8 +266,7 @@ static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
 }
 
 /**
- * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
- *
+ * ath5k_hw_write_ofdm_timings() - set OFDM timings on AR5212
  * @ah: the &struct ath5k_hw
  * @channel: the currently set channel upon reset
  *
@@ -216,10 +277,11 @@ static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
  * mantissa and provide these values on hw.
  *
  * For more infos i think this patent is related
- * http://www.freepatentsonline.com/7184495.html
+ * "http://www.freepatentsonline.com/7184495.html"
  */
-static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
-        struct ieee80211_channel *channel)
+static inline int
+ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
+                                struct ieee80211_channel *channel)
 {
         /* Get exponent and mantissa and set it */
         u32 coef_scaled, coef_exp, coef_man,
@@ -278,6 +340,10 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
         return 0;
 }
 
+/**
+ * ath5k_hw_phy_disable() - Disable PHY
+ * @ah: The &struct ath5k_hw
+ */
 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
 {
         /*Just a try M.F.*/
@@ -286,10 +352,13 @@ int ath5k_hw_phy_disable(struct ath5k_hw *ah)
         return 0;
 }
 
-/*
- * Wait for synth to settle
+/**
+ * ath5k_hw_wait_for_synth() - Wait for synth to settle
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
  */
-static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
+static void
+ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
                         struct ieee80211_channel *channel)
 {
         /*
@@ -308,9 +377,9 @@ static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
                         delay = delay << 2;
                 /* XXX: /2 on turbo ? Let's be safe
                  * for now */
-                udelay(100 + delay);
+                usleep_range(100 + delay, 100 + (2 * delay));
         } else {
-                mdelay(1);
+                usleep_range(1000, 1500);
         }
 }
 
@@ -319,7 +388,9 @@ static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
 * RF Gain optimization *
 \**********************/
 
-/*
+/**
+ * DOC: RF Gain optimization
+ *
  * This code is used to optimize RF gain on different environments
  * (temperature mostly) based on feedback from a power detector.
  *
@@ -328,22 +399,22 @@ static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
  * no gain optimization ladder-.
  *
  * For more infos check out this patent doc
- * http://www.freepatentsonline.com/7400691.html
+ * "http://www.freepatentsonline.com/7400691.html"
  *
  * This paper describes power drops as seen on the receiver due to
  * probe packets
- * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
- * %20of%20Power%20Control.pdf
+ * "http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
+ * %20of%20Power%20Control.pdf"
  *
  * And this is the MadWiFi bug entry related to the above
- * http://madwifi-project.org/ticket/1659
+ * "http://madwifi-project.org/ticket/1659"
  * with various measurements and diagrams
- *
- * TODO: Deal with power drops due to probes by setting an appropriate
- * tx power on the probe packets ! Make this part of the calibration process.
  */
 
-/* Initialize ah_gain during attach */
+/**
+ * ath5k_hw_rfgain_opt_init() - Initialize ah_gain during attach
+ * @ah: The &struct ath5k_hw
+ */
 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
 {
         /* Initialize the gain optimization values */
@@ -367,17 +438,21 @@ int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
         return 0;
 }
 
-/* Schedule a gain probe check on the next transmitted packet.
+/**
+ * ath5k_hw_request_rfgain_probe() - Request a PAPD probe packet
+ * @ah: The &struct ath5k_hw
+ *
+ * Schedules a gain probe check on the next transmitted packet.
  * That means our next packet is going to be sent with lower
  * tx power and a Peak to Average Power Detector (PAPD) will try
  * to measure the gain.
  *
- * XXX:  How about forcing a tx packet (bypassing PCU arbitrator etc)
+ * TODO: Force a tx packet (bypassing PCU arbitrator etc)
  * just after we enable the probe so that we don't mess with
- * standard traffic ? Maybe it's time to use sw interrupts and
- * a probe tasklet !!!
+ * standard traffic.
  */
-static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
+static void
+ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
 {
 
         /* Skip if gain calibration is inactive or
@@ -395,9 +470,15 @@ static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
 
 }
 
-/* Calculate gain_F measurement correction
- * based on the current step for RF5112 rev. 2 */
-static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
+/**
+ * ath5k_hw_rf_gainf_corr() - Calculate Gain_F measurement correction
+ * @ah: The &struct ath5k_hw
+ *
+ * Calculate Gain_F measurement correction
+ * based on the current step for RF5112 rev. 2
+ */
+static u32
+ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
 {
         u32 mix, step;
         u32 *rf;
@@ -450,11 +531,19 @@ static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
         return ah->ah_gain.g_f_corr;
 }
 
-/* Check if current gain_F measurement is in the range of our
+/**
+ * ath5k_hw_rf_check_gainf_readback() - Validate Gain_F feedback from detector
+ * @ah: The &struct ath5k_hw
+ *
+ * Check if current gain_F measurement is in the range of our
  * power detector windows. If we get a measurement outside range
  * we know it's not accurate (detectors can't measure anything outside
- * their detection window) so we must ignore it */
-static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
+ * their detection window) so we must ignore it.
+ *
+ * Returns true if readback was O.K. or false on failure
+ */
+static bool
+ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
 {
         const struct ath5k_rf_reg *rf_regs;
         u32 step, mix_ovr, level[4];
@@ -506,9 +595,15 @@ static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
                         ah->ah_gain.g_current <= level[3]);
 }
 
-/* Perform gain_F adjustment by choosing the right set
- * of parameters from RF gain optimization ladder */
-static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
+/**
+ * ath5k_hw_rf_gainf_adjust() - Perform Gain_F adjustment
+ * @ah: The &struct ath5k_hw
+ *
+ * Choose the right target gain based on current gain
+ * and RF gain optimization ladder
+ */
+static s8
+ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
 {
         const struct ath5k_gain_opt *go;
         const struct ath5k_gain_opt_step *g_step;
@@ -572,13 +667,18 @@ done:
         return ret;
 }
 
-/* Main callback for thermal RF gain calibration engine
+/**
+ * ath5k_hw_gainf_calibrate() - Do a gain_F calibration
+ * @ah: The &struct ath5k_hw
+ *
+ * Main callback for thermal RF gain calibration engine
  * Check for a new gain reading and schedule an adjustment
  * if needed.
  *
- * TODO: Use sw interrupt to schedule reset if gain_F needs
- * adjustment */
-enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
+ * Returns one of enum ath5k_rfgain codes
+ */
+enum ath5k_rfgain
+ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
 {
         u32 data, type;
         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
@@ -638,10 +738,18 @@ done:
         return ah->ah_gain.g_state;
 }
 
-/* Write initial RF gain table to set the RF sensitivity
- * this one works on all RF chips and has nothing to do
- * with gain_F calibration */
-static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
+/**
+ * ath5k_hw_rfgain_init() - Write initial RF gain settings to hw
+ * @ah: The &struct ath5k_hw
+ * @band: One of enum ieee80211_band
+ *
+ * Write initial RF gain table to set the RF sensitivity.
+ *
+ * NOTE: This one works on all RF chips and has nothing to do
+ * with Gain_F calibration
+ */
+static int
+ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
 {
         const struct ath5k_ini_rfgain *ath5k_rfg;
         unsigned int i, size, index;
@@ -688,16 +796,23 @@ static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
 }
 
 
-
 /********************\
 * RF Registers setup *
 \********************/
 
-/*
- * Setup RF registers by writing RF buffer on hw
+/**
+ * ath5k_hw_rfregs_init() - Initialize RF register settings
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ * @mode: One of enum ath5k_driver_mode
+ *
+ * Setup RF registers by writing RF buffer on hw. For
+ * more infos on this, check out rfbuffer.h
  */
-static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
-        struct ieee80211_channel *channel, unsigned int mode)
+static int
+ath5k_hw_rfregs_init(struct ath5k_hw *ah,
+                        struct ieee80211_channel *channel,
+                        unsigned int mode)
 {
         const struct ath5k_rf_reg *rf_regs;
         const struct ath5k_ini_rfbuffer *ini_rfb;
@@ -1055,19 +1170,18 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
   PHY/RF channel functions
 \**************************/
 
-/*
- * Conversion needed for RF5110
+/**
+ * ath5k_hw_rf5110_chan2athchan() - Convert channel freq on RF5110
+ * @channel: The &struct ieee80211_channel
+ *
+ * Map channel frequency to IEEE channel number and convert it
+ * to an internal channel value used by the RF5110 chipset.
  */
-static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
+static u32
+ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
 {
         u32 athchan;
 
-        /*
-         * Convert IEEE channel/MHz to an internal channel value used
-         * by the AR5210 chipset. This has not been verified with
-         * newer chipsets like the AR5212A who have a completely
-         * different RF/PHY part.
-         */
         athchan = (ath5k_hw_bitswap(
                         (ieee80211_frequency_to_channel(
                                 channel->center_freq) - 24) / 2, 5)
@@ -1075,10 +1189,13 @@ static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
         return athchan;
 }
 
-/*
- * Set channel on RF5110
+/**
+ * ath5k_hw_rf5110_channel() - Set channel frequency on RF5110
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
  */
-static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
+static int
+ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
                 struct ieee80211_channel *channel)
 {
         u32 data;
@@ -1089,15 +1206,23 @@ static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
         data = ath5k_hw_rf5110_chan2athchan(channel);
         ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
         ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
-        mdelay(1);
+        usleep_range(1000, 1500);
 
         return 0;
 }
 
-/*
- * Conversion needed for 5111
+/**
+ * ath5k_hw_rf5111_chan2athchan() - Handle 2GHz channels on RF5111/2111
+ * @ieee: IEEE channel number
+ * @athchan: The &struct ath5k_athchan_2ghz
+ *
+ * In order to enable the RF2111 frequency converter on RF5111/2111 setups
+ * we need to add some offsets and extra flags to the data values we pass
+ * on to the PHY. So for every 2GHz channel this function gets called
+ * to do the conversion.
  */
-static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
+static int
+ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
                 struct ath5k_athchan_2ghz *athchan)
 {
         int channel;
@@ -1123,10 +1248,13 @@ static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
         return 0;
 }
 
-/*
- * Set channel on 5111
+/**
+ * ath5k_hw_rf5111_channel() - Set channel frequency on RF5111/2111
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
  */
-static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
+static int
+ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
                 struct ieee80211_channel *channel)
 {
         struct ath5k_athchan_2ghz ath5k_channel_2ghz;
@@ -1171,10 +1299,20 @@ static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
         return 0;
 }
 
-/*
- * Set channel on 5112 and newer
+/**
+ * ath5k_hw_rf5112_channel() - Set channel frequency on 5112 and newer
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ *
+ * On RF5112/2112 and newer we don't need to do any conversion.
+ * We pass the frequency value after a few modifications to the
+ * chip directly.
+ *
+ * NOTE: Make sure channel frequency given is within our range or else
+ * we might damage the chip ! Use ath5k_channel_ok before calling this one.
  */
-static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
+static int
+ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
                 struct ieee80211_channel *channel)
 {
         u32 data, data0, data1, data2;
@@ -1183,17 +1321,37 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
         data = data0 = data1 = data2 = 0;
         c = channel->center_freq;
 
+        /* My guess based on code:
+         * 2GHz RF has 2 synth modes, one with a Local Oscillator
+         * at 2224Hz and one with a LO at 2192Hz. IF is 1520Hz
+         * (3040/2). data0 is used to set the PLL divider and data1
+         * selects synth mode. */
         if (c < 4800) {
+                /* Channel 14 and all frequencies with 2Hz spacing
+                 * below/above (non-standard channels) */
                 if (!((c - 2224) % 5)) {
+                        /* Same as (c - 2224) / 5 */
                         data0 = ((2 * (c - 704)) - 3040) / 10;
                         data1 = 1;
+                /* Channel 1 and all frequencies with 5Hz spacing
+                 * below/above (standard channels without channel 14) */
                 } else if (!((c - 2192) % 5)) {
+                        /* Same as (c - 2192) / 5 */
                         data0 = ((2 * (c - 672)) - 3040) / 10;
                         data1 = 0;
                 } else
                         return -EINVAL;
 
                 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
+        /* This is more complex, we have a single synthesizer with
+         * 4 reference clock settings (?) based on frequency spacing
+         * and set using data2. LO is at 4800Hz and data0 is again used
+         * to set some divider.
+         *
+         * NOTE: There is an old atheros presentation at Stanford
+         * that mentions a method called dual direct conversion
+         * with 1GHz sliding IF for RF5110. Maybe that's what we
+         * have here, or an updated version. */
         } else if ((c % 5) != 2 || c > 5435) {
                 if (!(c % 20) && c >= 5120) {
                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
@@ -1219,10 +1377,16 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
         return 0;
 }
 
-/*
- * Set the channel on the RF2425
+/**
+ * ath5k_hw_rf2425_channel() - Set channel frequency on RF2425
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ *
+ * AR2425/2417 have a different 2GHz RF so code changes
+ * a little bit from RF5112.
  */
-static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
+static int
+ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
                 struct ieee80211_channel *channel)
 {
         u32 data, data0, data2;
@@ -1258,10 +1422,16 @@ static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
         return 0;
 }
 
-/*
- * Set a channel on the radio chip
+/**
+ * ath5k_hw_channel() - Set a channel on the radio chip
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ *
+ * This is the main function called to set a channel on the
+ * radio chip based on the radio chip version.
  */
-static int ath5k_hw_channel(struct ath5k_hw *ah,
+static int
+ath5k_hw_channel(struct ath5k_hw *ah,
                 struct ieee80211_channel *channel)
 {
         int ret;
@@ -1313,11 +1483,46 @@ static int ath5k_hw_channel(struct ath5k_hw *ah,
         return 0;
 }
 
+
 /*****************\
   PHY calibration
 \*****************/
 
-static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
+/**
+ * DOC: PHY Calibration routines
+ *
+ * Noise floor calibration: When we tell the hardware to
+ * perform a noise floor calibration by setting the
+ * AR5K_PHY_AGCCTL_NF bit on AR5K_PHY_AGCCTL, it will periodically
+ * sample-and-hold the minimum noise level seen at the antennas.
+ * This value is then stored in a ring buffer of recently measured
+ * noise floor values so we have a moving window of the last few
+ * samples. The median of the values in the history is then loaded
+ * into the hardware for its own use for RSSI and CCA measurements.
+ * This type of calibration doesn't interfere with traffic.
+ *
+ * AGC calibration: When we tell the hardware to perform
+ * an AGC (Automatic Gain Control) calibration by setting the
+ * AR5K_PHY_AGCCTL_CAL, hw disconnects the antennas and does
+ * a calibration on the DC offsets of ADCs. During this period
+ * rx/tx gets disabled so we have to deal with it on the driver
+ * part.
+ *
+ * I/Q calibration: When we tell the hardware to perform
+ * an I/Q calibration, it tries to correct I/Q imbalance and
+ * fix QAM constellation by sampling data from rxed frames.
+ * It doesn't interfere with traffic.
+ *
+ * For more infos on AGC and I/Q calibration check out patent doc
+ * #03/094463.
+ */
+
+/**
+ * ath5k_hw_read_measured_noise_floor() - Read measured NF from hw
+ * @ah: The &struct ath5k_hw
+ */
+static s32
+ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
 {
         s32 val;
 
@@ -1325,7 +1530,12 @@ static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
         return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
 }
 
-void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
+/**
+ * ath5k_hw_init_nfcal_hist() - Initialize NF calibration history buffer
+ * @ah: The &struct ath5k_hw
+ */
+void
+ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
 {
         int i;
 
@@ -1334,6 +1544,11 @@ void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
                 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
 }
 
+/**
+ * ath5k_hw_update_nfcal_hist() - Update NF calibration history buffer
+ * @ah: The &struct ath5k_hw
+ * @noise_floor: The NF we got from hw
+ */
 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
 {
         struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
@@ -1341,7 +1556,12 @@ static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
         hist->nfval[hist->index] = noise_floor;
 }
 
-static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
+/**
+ * ath5k_hw_get_median_noise_floor() - Get median NF from history buffer
+ * @ah: The &struct ath5k_hw
+ */
+static s16
+ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
 {
         s16 sort[ATH5K_NF_CAL_HIST_MAX];
         s16 tmp;
@@ -1364,18 +1584,16 @@ static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
         return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2];
 }
 
-/*
- * When we tell the hardware to perform a noise floor calibration
- * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
- * sample-and-hold the minimum noise level seen at the antennas.
- * This value is then stored in a ring buffer of recently measured
- * noise floor values so we have a moving window of the last few
- * samples.
+/**
+ * ath5k_hw_update_noise_floor() - Update NF on hardware
+ * @ah: The &struct ath5k_hw
  *
- * The median of the values in the history is then loaded into the
- * hardware for its own use for RSSI and CCA measurements.
+ * This is the main function we call to perform a NF calibration,
+ * it reads NF from hardware, calculates the median and updates
+ * NF on hw.
  */
-void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
+void
+ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
 {
         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
         u32 val;
@@ -1390,6 +1608,8 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
                 return;
         }
 
+        ah->ah_cal_mask |= AR5K_CALIBRATION_NF;
+
         ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel);
 
         /* completed NF calibration, test threshold */
@@ -1434,20 +1654,29 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
 
         ah->ah_noise_floor = nf;
 
+        ah->ah_cal_mask &= ~AR5K_CALIBRATION_NF;
+
         ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
                 "noise floor calibrated: %d\n", nf);
 }
 
-/*
- * Perform a PHY calibration on RF5110
- * -Fix BPSK/QAM Constellation (I/Q correction)
+/**
+ * ath5k_hw_rf5110_calibrate() - Perform a PHY calibration on RF5110
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ *
+ * Do a complete PHY calibration (AGC + NF + I/Q) on RF5110
  */
-static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
+static int
+ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
                 struct ieee80211_channel *channel)
 {
         u32 phy_sig, phy_agc, phy_sat, beacon;
         int ret;
 
+        if (!(ah->ah_cal_mask & AR5K_CALIBRATION_FULL))
+                return 0;
+
         /*
          * Disable beacons and RX/TX queues, wait
          */
@@ -1456,7 +1685,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
         beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
         ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
 
-        mdelay(2);
+        usleep_range(2000, 2500);
 
         /*
          * Set the channel (with AGC turned off)
@@ -1469,7 +1698,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
          * Activate PHY and wait
          */
         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
-        mdelay(1);
+        usleep_range(1000, 1500);
 
         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
 
@@ -1506,7 +1735,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
         ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
 
-        mdelay(1);
+        usleep_range(1000, 1500);
 
         /*
          * Enable calibration and wait until completion
@@ -1537,8 +1766,9 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
         return 0;
 }
 
-/*
- * Perform I/Q calibration on RF5111/5112 and newer chips
+/**
+ * ath5k_hw_rf511x_iq_calibrate() - Perform I/Q calibration on RF5111 and newer
+ * @ah: The &struct ath5k_hw
  */
 static int
 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
@@ -1547,12 +1777,19 @@ ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
         s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
         int i;
 
-        if (!ah->ah_calibration ||
-                ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
-                return 0;
+        /* Skip if I/Q calibration is not needed or if it's still running */
+        if (!ah->ah_iq_cal_needed)
+                return -EINVAL;
+        else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) {
+                ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
+                                "I/Q calibration still running");
+                return -EBUSY;
+        }
 
         /* Calibration has finished, get the results and re-run */
-        /* work around empty results which can apparently happen on 5212 */
+
+        /* Work around for empty results which can apparently happen on 5212:
+         * Read registers up to 10 times until we get both i_pr and q_pwr */
         for (i = 0; i <= 10; i++) {
                 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
                 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
@@ -1570,9 +1807,13 @@ ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
         else
                 q_coffd = q_pwr >> 7;
 
-        /* protect against divide by 0 and loss of sign bits */
+        /* In case i_coffd became zero, cancel calibration
+         * not only it's too small, it'll also result a divide
+         * by zero later on. */
         if (i_coffd == 0 || q_coffd < 2)
-                return 0;
+                return -ECANCELED;
+
+        /* Protect against loss of sign bits */
 
         i_coff = (-iq_corr) / i_coffd;
         i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
@@ -1601,10 +1842,17 @@ ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
         return 0;
 }
 
-/*
- * Perform a PHY calibration
+/**
+ * ath5k_hw_phy_calibrate() - Perform a PHY calibration
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ *
+ * The main function we call from above to perform
+ * a short or full PHY calibration based on RF chip
+ * and current channel
  */
-int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
+int
+ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
                 struct ieee80211_channel *channel)
 {
         int ret;
@@ -1613,10 +1861,43 @@ int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
                 return ath5k_hw_rf5110_calibrate(ah, channel);
 
         ret = ath5k_hw_rf511x_iq_calibrate(ah);
+        if (ret) {
+                ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
+                        "No I/Q correction performed (%uMHz)\n",
+                        channel->center_freq);
+
+                /* Happens all the time if there is not much
+                 * traffic, consider it normal behaviour. */
+                ret = 0;
+        }
+
+        /* On full calibration do an AGC calibration and
+         * request a PAPD probe for gainf calibration if
+         * needed */
+        if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) {
 
-        if ((ah->ah_radio == AR5K_RF5111 || ah->ah_radio == AR5K_RF5112) &&
-            (channel->hw_value != AR5K_MODE_11B))
-                ath5k_hw_request_rfgain_probe(ah);
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
+                                        AR5K_PHY_AGCCTL_CAL);
+
+                ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
+                        AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF,
+                        0, false);
+                if (ret) {
+                        ATH5K_ERR(ah,
+                                "gain calibration timeout (%uMHz)\n",
+                                channel->center_freq);
+                }
+
+                if ((ah->ah_radio == AR5K_RF5111 ||
+                        ah->ah_radio == AR5K_RF5112)
+                        && (channel->hw_value != AR5K_MODE_11B))
+                        ath5k_hw_request_rfgain_probe(ah);
+        }
+
+        /* Update noise floor
+         * XXX: Only do this after AGC calibration */
+        if (!(ah->ah_cal_mask & AR5K_CALIBRATION_NF))
+                ath5k_hw_update_noise_floor(ah);
 
         return ret;
 }
@@ -1626,6 +1907,16 @@ int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
 * Spur mitigation functions *
 \***************************/
 
+/**
+ * ath5k_hw_set_spur_mitigation_filter() - Configure SPUR filter
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ *
+ * This function gets called during PHY initialization to
+ * configure the spur filter for the given channel. Spur is noise
+ * generated due to "reflection" effects, for more information on this
+ * method check out patent US7643810
+ */
 static void
 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
                                 struct ieee80211_channel *channel)
@@ -1865,15 +2156,73 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
 * Antenna control *
 \*****************/
 
-static void /*TODO:Boundary check*/
+/**
+ * DOC: Antenna control
+ *
+ * Hw supports up to 14 antennas ! I haven't found any card that implements
+ * that. The maximum number of antennas I've seen is up to 4 (2 for 2GHz and 2
+ * for 5GHz). Antenna 1 (MAIN) should be omnidirectional, 2 (AUX)
+ * omnidirectional or sectorial and antennas 3-14 sectorial (or directional).
+ *
+ * We can have a single antenna for RX and multiple antennas for TX.
+ * RX antenna is our "default" antenna (usually antenna 1) set on
+ * DEFAULT_ANTENNA register and TX antenna is set on each TX control descriptor
+ * (0 for automatic selection, 1 - 14 antenna number).
+ *
+ * We can let hw do all the work doing fast antenna diversity for both
+ * tx and rx or we can do things manually. Here are the options we have
+ * (all are bits of STA_ID1 register):
+ *
+ * AR5K_STA_ID1_DEFAULT_ANTENNA -> When 0 is set as the TX antenna on TX
+ * control descriptor, use the default antenna to transmit or else use the last
+ * antenna on which we received an ACK.
+ *
+ * AR5K_STA_ID1_DESC_ANTENNA -> Update default antenna after each TX frame to
+ * the antenna on which we got the ACK for that frame.
+ *
+ * AR5K_STA_ID1_RTS_DEF_ANTENNA -> Use default antenna for RTS or else use the
+ * one on the TX descriptor.
+ *
+ * AR5K_STA_ID1_SELFGEN_DEF_ANT -> Use default antenna for self generated frames
+ * (ACKs etc), or else use current antenna (the one we just used for TX).
+ *
+ * Using the above we support the following scenarios:
+ *
+ * AR5K_ANTMODE_DEFAULT -> Hw handles antenna diversity etc automatically
+ *
+ * AR5K_ANTMODE_FIXED_A -> Only antenna A (MAIN) is present
+ *
+ * AR5K_ANTMODE_FIXED_B -> Only antenna B (AUX) is present
+ *
+ * AR5K_ANTMODE_SINGLE_AP -> Sta locked on a single ap
+ *
+ * AR5K_ANTMODE_SECTOR_AP -> AP with tx antenna set on tx desc
+ *
+ * AR5K_ANTMODE_SECTOR_STA -> STA with tx antenna set on tx desc
+ *
+ * AR5K_ANTMODE_DEBUG Debug mode -A -> Rx, B-> Tx-
+ *
+ * Also note that when setting antenna to F on tx descriptor card inverts
+ * current tx antenna.
+ */
+
+/**
+ * ath5k_hw_set_def_antenna() - Set default rx antenna on AR5211/5212 and newer
+ * @ah: The &struct ath5k_hw
+ * @ant: Antenna number
+ */
+static void
 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
 {
         if (ah->ah_version != AR5K_AR5210)
                 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
 }
 
-/*
- * Enable/disable fast rx antenna diversity
+/**
+ * ath5k_hw_set_fast_div() -  Enable/disable fast rx antenna diversity
+ * @ah: The &struct ath5k_hw
+ * @ee_mode: One of enum ath5k_driver_mode
+ * @enable: True to enable, false to disable
  */
 static void
 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
@@ -1913,6 +2262,14 @@ ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
         }
 }
 
+/**
+ * ath5k_hw_set_antenna_switch() - Set up antenna switch table
+ * @ah: The &struct ath5k_hw
+ * @ee_mode: One of enum ath5k_driver_mode
+ *
+ * Switch table comes from EEPROM and includes information on controlling
+ * the 2 antenna RX attenuators
+ */
 void
 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
 {
@@ -1944,8 +2301,10 @@ ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
                 AR5K_PHY_ANT_SWITCH_TABLE_1);
 }
 
-/*
- * Set antenna operating mode
+/**
+ * ath5k_hw_set_antenna_mode() -  Set antenna operating mode
+ * @ah: The &struct ath5k_hw
+ * @ant_mode: One of enum ath5k_ant_mode
  */
 void
 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
@@ -2068,8 +2427,13 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
  * Helper functions
  */
 
-/*
- * Do linear interpolation between two given (x, y) points
+/**
+ * ath5k_get_interpolated_value() - Get interpolated Y val between two points
+ * @target: X value of the middle point
+ * @x_left: X value of the left point
+ * @x_right: X value of the right point
+ * @y_left: Y value of the left point
+ * @y_right: Y value of the right point
  */
 static s16
 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
@@ -2096,13 +2460,18 @@ ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
         return result;
 }
 
-/*
- * Find vertical boundary (min pwr) for the linear PCDAC curve.
+/**
+ * ath5k_get_linear_pcdac_min() - Find vertical boundary (min pwr) for the
+ * linear PCDAC curve
+ * @stepL: Left array with y values (pcdac steps)
+ * @stepR: Right array with y values (pcdac steps)
+ * @pwrL: Left array with x values (power steps)
+ * @pwrR: Right array with x values (power steps)
  *
  * Since we have the top of the curve and we draw the line below
  * until we reach 1 (1 pcdac step) we need to know which point
- * (x value) that is so that we don't go below y axis and have negative
- * pcdac values when creating the curve, or fill the table with zeroes.
+ * (x value) that is so that we don't go below x axis and have negative
+ * pcdac values when creating the curve, or fill the table with zeros.
  */
 static s16
 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
@@ -2148,7 +2517,16 @@ ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
         return max(min_pwrL, min_pwrR);
 }
 
-/*
+/**
+ * ath5k_create_power_curve() - Create a Power to PDADC or PCDAC curve
+ * @pmin: Minimum power value (xmin)
+ * @pmax: Maximum power value (xmax)
+ * @pwr: Array of power steps (x values)
+ * @vpd: Array of matching PCDAC/PDADC steps (y values)
+ * @num_points: Number of provided points
+ * @vpd_table: Array to fill with the full PCDAC/PDADC values (y values)
+ * @type: One of enum ath5k_powertable_type (eeprom.h)
+ *
  * Interpolate (pwr,vpd) points to create a Power to PDADC or a
  * Power to PCDAC curve.
  *
@@ -2206,7 +2584,14 @@ ath5k_create_power_curve(s16 pmin, s16 pmax,
         }
 }
 
-/*
+/**
+ * ath5k_get_chan_pcal_surrounding_piers() - Get surrounding calibration piers
+ * for a given channel.
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ * @pcinfo_l: The &struct ath5k_chan_pcal_info to put the left cal. pier
+ * @pcinfo_r: The &struct ath5k_chan_pcal_info to put the right cal. pier
+ *
  * Get the surrounding per-channel power calibration piers
  * for a given frequency so that we can interpolate between
  * them and come up with an appropriate dataset for our current
@@ -2289,11 +2674,17 @@ done:
         *pcinfo_r = &pcinfo[idx_r];
 }
 
-/*
+/**
+ * ath5k_get_rate_pcal_data() - Get the interpolated per-rate power
+ * calibration data
+ * @ah: The &struct ath5k_hw *ah,
+ * @channel: The &struct ieee80211_channel
+ * @rates: The &struct ath5k_rate_pcal_info to fill
+ *
  * Get the surrounding per-rate power calibration data
  * for a given frequency and interpolate between power
  * values to set max target power supported by hw for
- * each rate.
+ * each rate on this frequency.
  */
 static void
 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
@@ -2381,7 +2772,11 @@ done:
                                         rpinfo[idx_r].target_power_54);
 }
 
-/*
+/**
+ * ath5k_get_max_ctl_power() - Get max edge power for a given frequency
+ * @ah: the &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ *
  * Get the max edge power for this channel if
  * we have such data from EEPROM's Conformance Test
  * Limits (CTL), and limit max power if needed.
@@ -2461,8 +2856,39 @@ ath5k_get_max_ctl_power(struct ath5k_hw *ah,
  * Power to PCDAC table functions
  */
 
-/*
- * Fill Power to PCDAC table on RF5111
+/**
+ * DOC: Power to PCDAC table functions
+ *
+ * For RF5111 we have an XPD -eXternal Power Detector- curve
+ * for each calibrated channel. Each curve has 0,5dB Power steps
+ * on x axis and PCDAC steps (offsets) on y axis and looks like an
+ * exponential function. To recreate the curve we read 11 points
+ * from eeprom (eeprom.c) and interpolate here.
+ *
+ * For RF5112 we have 4 XPD -eXternal Power Detector- curves
+ * for each calibrated channel on 0, -6, -12 and -18dBm but we only
+ * use the higher (3) and the lower (0) curves. Each curve again has 0.5dB
+ * power steps on x axis and PCDAC steps on y axis and looks like a
+ * linear function. To recreate the curve and pass the power values
+ * on hw, we get 4 points for xpd 0 (lower gain -> max power)
+ * and 3 points for xpd 3 (higher gain -> lower power) from eeprom (eeprom.c)
+ * and interpolate here.
+ *
+ * For a given channel we get the calibrated points (piers) for it or
+ * -if we don't have calibration data for this specific channel- from the
+ * available surrounding channels we have calibration data for, after we do a
+ * linear interpolation between them. Then since we have our calibrated points
+ * for this channel, we do again a linear interpolation between them to get the
+ * whole curve.
+ *
+ * We finally write the Y values of the curve(s) (the PCDAC values) on hw
+ */
+
+/**
+ * ath5k_fill_pwr_to_pcdac_table() - Fill Power to PCDAC table on RF5111
+ * @ah: The &struct ath5k_hw
+ * @table_min: Minimum power (x min)
+ * @table_max: Maximum power (x max)
  *
  * No further processing is needed for RF5111, the only thing we have to
  * do is fill the values below and above calibration range since eeprom data
@@ -2503,10 +2929,14 @@ ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
 
 }
 
-/*
- * Combine available XPD Curves and fill Linear Power to PCDAC table
- * on RF5112
+/**
+ * ath5k_combine_linear_pcdac_curves() - Combine available PCDAC Curves
+ * @ah: The &struct ath5k_hw
+ * @table_min: Minimum power (x min)
+ * @table_max: Maximum power (x max)
+ * @pdcurves: Number of pd curves
  *
+ * Combine available XPD Curves and fill Linear Power to PCDAC table on RF5112
  * RFX112 can have up to 2 curves (one for low txpower range and one for
  * higher txpower range). We need to put them both on pcdac_out and place
  * them in the correct location. In case we only have one curve available
@@ -2608,7 +3038,10 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
         }
 }
 
-/* Write PCDAC values on hw */
+/**
+ * ath5k_write_pcdac_table() - Write the PCDAC values on hw
+ * @ah: The &struct ath5k_hw
+ */
 static void
 ath5k_write_pcdac_table(struct ath5k_hw *ah)
 {
@@ -2631,9 +3064,32 @@ ath5k_write_pcdac_table(struct ath5k_hw *ah)
  * Power to PDADC table functions
  */
 
-/*
- * Set the gain boundaries and create final Power to PDADC table
+/**
+ * DOC: Power to PDADC table functions
+ *
+ * For RF2413 and later we have a Power to PDADC table (Power Detector)
+ * instead of a PCDAC (Power Control) and 4 pd gain curves for each
+ * calibrated channel. Each curve has power on x axis in 0.5 db steps and
+ * PDADC steps on y axis and looks like an exponential function like the
+ * RF5111 curve.
+ *
+ * To recreate the curves we read the points from eeprom (eeprom.c)
+ * and interpolate here. Note that in most cases only 2 (higher and lower)
+ * curves are used (like RF5112) but vendors have the opportunity to include
+ * all 4 curves on eeprom. The final curve (higher power) has an extra
+ * point for better accuracy like RF5112.
  *
+ * The process is similar to what we do above for RF5111/5112
+ */
+
+/**
+ * ath5k_combine_pwr_to_pdadc_curves() - Combine the various PDADC curves
+ * @ah: The &struct ath5k_hw
+ * @pwr_min: Minimum power (x min)
+ * @pwr_max: Maximum power (x max)
+ * @pdcurves: Number of available curves
+ *
+ * Combine the various pd curves and create the final Power to PDADC table
  * We can have up to 4 pd curves, we need to do a similar process
  * as we do for RF5112. This time we don't have an edge_flag but we
  * set the gain boundaries on a separate register.
@@ -2757,7 +3213,11 @@ ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
 
 }
 
-/* Write PDADC values on hw */
+/**
+ * ath5k_write_pwr_to_pdadc_table() - Write the PDADC values on hw
+ * @ah: The &struct ath5k_hw
+ * @ee_mode: One of enum ath5k_driver_mode
+ */
 static void
 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
 {
@@ -2814,7 +3274,13 @@ ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
  * Common code for PCDAC/PDADC tables
  */
 
-/*
+/**
+ * ath5k_setup_channel_powertable() - Set up power table for this channel
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ * @ee_mode: One of enum ath5k_driver_mode
+ * @type: One of enum ath5k_powertable_type (eeprom.h)
+ *
  * This is the main function that uses all of the above
  * to set PCDAC/PDADC table on hw for the current channel.
  * This table is used for tx power calibration on the baseband,
@@ -3012,7 +3478,12 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
         return 0;
 }
 
-/* Write power table for current channel to hw */
+/**
+ * ath5k_write_channel_powertable() - Set power table for current channel on hw
+ * @ah: The &struct ath5k_hw
+ * @ee_mode: One of enum ath5k_driver_mode
+ * @type: One of enum ath5k_powertable_type (eeprom.h)
+ */
 static void
 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
 {
@@ -3022,28 +3493,36 @@ ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
                 ath5k_write_pcdac_table(ah);
 }
 
-/*
- * Per-rate tx power setting
+
+/**
+ * DOC: Per-rate tx power setting
  *
- * This is the code that sets the desired tx power (below
+ * This is the code that sets the desired tx power limit (below
  * maximum) on hw for each rate (we also have TPC that sets
- * power per packet). We do that by providing an index on the
- * PCDAC/PDADC table we set up.
- */
-
-/*
- * Set rate power table
+ * power per packet type). We do that by providing an index on the
+ * PCDAC/PDADC table we set up above, for each rate.
  *
  * For now we only limit txpower based on maximum tx power
- * supported by hw (what's inside rate_info). We need to limit
- * this even more, based on regulatory domain etc.
+ * supported by hw (what's inside rate_info) + conformance test
+ * limits. We need to limit this even more, based on regulatory domain
+ * etc to be safe. Normally this is done from above so we don't care
+ * here, all we care is that the tx power we set will be O.K.
+ * for the hw (e.g. won't create noise on PA etc).
  *
- * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
- * and is indexed as follows:
+ * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps -
+ * x values) and is indexed as follows:
  * rates[0] - rates[7] -> OFDM rates
  * rates[8] - rates[14] -> CCK rates
  * rates[15] -> XR rates (they all have the same power)
  */
+
+/**
+ * ath5k_setup_rate_powertable() - Set up rate power table for a given tx power
+ * @ah: The &struct ath5k_hw
+ * @max_pwr: The maximum tx power requested in 0.5dB steps
+ * @rate_info: The &struct ath5k_rate_pcal_info to fill
+ * @ee_mode: One of enum ath5k_driver_mode
+ */
 static void
 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
                         struct ath5k_rate_pcal_info *rate_info,
@@ -3114,8 +3593,14 @@ ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
 }
 
 
-/*
- * Set transmission power
+/**
+ * ath5k_hw_txpower() - Set transmission power limit for a given channel
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ * @txpower: Requested tx power in 0.5dB steps
+ *
+ * Combines all of the above to set the requested tx power limit
+ * on hw.
  */
 static int
 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
@@ -3233,7 +3718,16 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
         return 0;
 }
 
-int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
+/**
+ * ath5k_hw_set_txpower_limit() - Set txpower limit for the current channel
+ * @ah: The &struct ath5k_hw
+ * @txpower: The requested tx power limit in 0.5dB steps
+ *
+ * This function provides access to ath5k_hw_txpower to the driver in
+ * case user or an application changes it while PHY is running.
+ */
+int
+ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
 {
         ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER,
                 "changing txpower to %d\n", txpower);
@@ -3241,11 +3735,26 @@ int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
         return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
 }
 
+
 /*************\
  Init function
 \*************/
 
-int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
+/**
+ * ath5k_hw_phy_init() - Initialize PHY
+ * @ah: The &struct ath5k_hw
+ * @channel: The @struct ieee80211_channel
+ * @mode: One of enum ath5k_driver_mode
+ * @fast: Try a fast channel switch instead
+ *
+ * This is the main function used during reset to initialize PHY
+ * or do a fast channel change if possible.
+ *
+ * NOTE: Do not call this one from the driver, it assumes PHY is in a
+ * warm reset state !
+ */
+int
+ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                       u8 mode, bool fast)
 {
         struct ieee80211_channel *curr_channel;
@@ -3355,7 +3864,7 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                 if (ret)
                         return ret;
 
-                mdelay(1);
+                usleep_range(1000, 1500);
 
                 /*
                  * Write RF buffer
@@ -3376,10 +3885,10 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                 }
 
         } else if (ah->ah_version == AR5K_AR5210) {
-                mdelay(1);
+                usleep_range(1000, 1500);
                 /* Disable phy and wait */
                 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
-                mdelay(1);
+                usleep_range(1000, 1500);
         }
 
         /* Set channel on PHY */
@@ -3405,7 +3914,7 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
         for (i = 0; i <= 20; i++) {
                 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
                         break;
-                udelay(200);
+                usleep_range(200, 250);
         }
         ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
 
@@ -3433,9 +3942,9 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 
         /* At the same time start I/Q calibration for QAM constellation
          * -no need for CCK- */
-        ah->ah_calibration = false;
+        ah->ah_iq_cal_needed = false;
         if (!(mode == AR5K_MODE_11B)) {
-                ah->ah_calibration = true;
+                ah->ah_iq_cal_needed = true;
                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
                                 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c
index 776654228eaa..30b50f934172 100644
--- a/drivers/net/wireless/ath/ath5k/qcu.c
+++ b/drivers/net/wireless/ath/ath5k/qcu.c
@@ -17,23 +17,48 @@
  */
 
 /********************************************\
-Queue Control Unit, DFS Control Unit Functions
+Queue Control Unit, DCF Control Unit Functions
 \********************************************/
 
 #include "ath5k.h"
 #include "reg.h"
 #include "debug.h"
+#include <linux/log2.h>
+
+/**
+ * DOC: Queue Control Unit (QCU)/DCF Control Unit (DCU) functions
+ *
+ * Here we setup parameters for the 12 available TX queues. Note that
+ * on the various registers we can usually only map the first 10 of them so
+ * basically we have 10 queues to play with. Each queue has a matching
+ * QCU that controls when the queue will get triggered and multiple QCUs
+ * can be mapped to a single DCU that controls the various DFS parameters
+ * for the various queues. In our setup we have a 1:1 mapping between QCUs
+ * and DCUs allowing us to have different DFS settings for each queue.
+ *
+ * When a frame goes into a TX queue, QCU decides when it'll trigger a
+ * transmission based on various criteria (such as how many data we have inside
+ * it's buffer or -if it's a beacon queue- if it's time to fire up the queue
+ * based on TSF etc), DCU adds backoff, IFSes etc and then a scheduler
+ * (arbitrator) decides the priority of each QCU based on it's configuration
+ * (e.g. beacons are always transmitted when they leave DCU bypassing all other
+ * frames from other queues waiting to be transmitted). After a frame leaves
+ * the DCU it goes to PCU for further processing and then to PHY for
+ * the actual transmission.
+ */
 
 
 /******************\
 * Helper functions *
 \******************/
 
-/*
- * Get number of pending frames
- * for a specific queue [5211+]
+/**
+ * ath5k_hw_num_tx_pending() - Get number of pending frames for a  given queue
+ * @ah: The &struct ath5k_hw
+ * @queue: One of enum ath5k_tx_queue_id
  */
-u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
+u32
+ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
 {
         u32 pending;
         AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
@@ -58,10 +83,13 @@ u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
         return pending;
 }
 
-/*
- * Set a transmit queue inactive
+/**
+ * ath5k_hw_release_tx_queue() - Set a transmit queue inactive
+ * @ah: The &struct ath5k_hw
+ * @queue: One of enum ath5k_tx_queue_id
  */
-void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
+void
+ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
 {
         if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
                 return;
@@ -72,34 +100,56 @@ void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
         AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
 }
 
-/*
+/**
+ * ath5k_cw_validate() - Make sure the given cw is valid
+ * @cw_req: The contention window value to check
+ *
  * Make sure cw is a power of 2 minus 1 and smaller than 1024
  */
-static u16 ath5k_cw_validate(u16 cw_req)
+static u16
+ath5k_cw_validate(u16 cw_req)
 {
-        u32 cw = 1;
         cw_req = min(cw_req, (u16)1023);
 
-        while (cw < cw_req)
-                cw = (cw << 1) | 1;
+        /* Check if cw_req + 1 a power of 2 */
+        if (is_power_of_2(cw_req + 1))
+                return cw_req;
 
-        return cw;
+        /* Check if cw_req is a power of 2 */
+        if (is_power_of_2(cw_req))
+                return cw_req - 1;
+
+        /* If none of the above is correct
+         * find the closest power of 2 */
+        cw_req = (u16) roundup_pow_of_two(cw_req) - 1;
+
+        return cw_req;
 }
 
-/*
- * Get properties for a transmit queue
+/**
+ * ath5k_hw_get_tx_queueprops() - Get properties for a transmit queue
+ * @ah: The &struct ath5k_hw
+ * @queue: One of enum ath5k_tx_queue_id
+ * @queue_info: The &struct ath5k_txq_info to fill
  */
-int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
+int
+ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
                 struct ath5k_txq_info *queue_info)
 {
         memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
         return 0;
 }
 
-/*
- * Set properties for a transmit queue
+/**
+ * ath5k_hw_set_tx_queueprops() - Set properties for a transmit queue
+ * @ah: The &struct ath5k_hw
+ * @queue: One of enum ath5k_tx_queue_id
+ * @qinfo: The &struct ath5k_txq_info to use
+ *
+ * Returns 0 on success or -EIO if queue is inactive
  */
-int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
+int
+ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
                                 const struct ath5k_txq_info *qinfo)
 {
         struct ath5k_txq_info *qi;
@@ -139,10 +189,16 @@ int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
         return 0;
 }
 
-/*
- * Initialize a transmit queue
+/**
+ * ath5k_hw_setup_tx_queue() - Initialize a transmit queue
+ * @ah: The &struct ath5k_hw
+ * @queue_type: One of enum ath5k_tx_queue
+ * @queue_info: The &struct ath5k_txq_info to use
+ *
+ * Returns 0 on success, -EINVAL on invalid arguments
  */
-int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
+int
+ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
                 struct ath5k_txq_info *queue_info)
 {
         unsigned int queue;
@@ -217,10 +273,16 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
 * Single QCU/DCU initialization *
 \*******************************/
 
-/*
- * Set tx retry limits on DCU
+/**
+ * ath5k_hw_set_tx_retry_limits() - Set tx retry limits on DCU
+ * @ah: The &struct ath5k_hw
+ * @queue: One of enum ath5k_tx_queue_id
+ *
+ * This function is used when initializing a queue, to set
+ * retry limits based on ah->ah_retry_* and the chipset used.
  */
-void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
+void
+ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
                                   unsigned int queue)
 {
         /* Single data queue on AR5210 */
@@ -255,15 +317,15 @@ void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
 }
 
 /**
- * ath5k_hw_reset_tx_queue - Initialize a single hw queue
+ * ath5k_hw_reset_tx_queue() - Initialize a single hw queue
+ * @ah: The &struct ath5k_hw
+ * @queue: One of enum ath5k_tx_queue_id
  *
- * @ah The &struct ath5k_hw
- * @queue The hw queue number
- *
- * Set DFS properties for the given transmit queue on DCU
+ * Set DCF properties for the given transmit queue on DCU
  * and configures all queue-specific parameters.
  */
-int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
+int
+ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
 {
         struct ath5k_txq_info *tq = &ah->ah_txq[queue];
 
@@ -491,10 +553,9 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
 \**************************/
 
 /**
- * ath5k_hw_set_ifs_intervals  - Set global inter-frame spaces on DCU
- *
- * @ah The &struct ath5k_hw
- * @slot_time Slot time in us
+ * ath5k_hw_set_ifs_intervals()  - Set global inter-frame spaces on DCU
+ * @ah: The &struct ath5k_hw
+ * @slot_time: Slot time in us
  *
  * Sets the global IFS intervals on DCU (also works on AR5210) for
  * the given slot time and the current bwmode.
@@ -597,7 +658,15 @@ int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time)
 }
 
 
-int ath5k_hw_init_queues(struct ath5k_hw *ah)
+/**
+ * ath5k_hw_init_queues() - Initialize tx queues
+ * @ah: The &struct ath5k_hw
+ *
+ * Initializes all tx queues based on information on
+ * ah->ah_txq* set by the driver
+ */
+int
+ath5k_hw_init_queues(struct ath5k_hw *ah)
 {
         int i, ret;
 
diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h
index f5c1000045d3..0ea1608b47fd 100644
--- a/drivers/net/wireless/ath/ath5k/reg.h
+++ b/drivers/net/wireless/ath/ath5k/reg.h
@@ -280,6 +280,10 @@
  * 5211/5212 we have one primary and 4 secondary registers.
  * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212.
  * Most of these bits are common for all chipsets.
+ *
+ * NOTE: On 5211+ TXOK, TXDESC, TXERR, TXEOL and TXURN contain
+ * the logical OR from per-queue interrupt bits found on SISR registers
+ * (see below).
  */
 #define AR5K_ISR                0x001c                  /* Register Address [5210] */
 #define AR5K_PISR               0x0080                  /* Register Address [5211+] */
@@ -292,7 +296,10 @@
 #define AR5K_ISR_TXOK           0x00000040      /* Frame successfully transmitted */
 #define AR5K_ISR_TXDESC         0x00000080      /* TX descriptor request */
 #define AR5K_ISR_TXERR          0x00000100      /* Transmit error */
-#define AR5K_ISR_TXNOFRM        0x00000200      /* No frame transmitted (transmit timeout) */
+#define AR5K_ISR_TXNOFRM        0x00000200      /* No frame transmitted (transmit timeout)
+                                                 * NOTE: We don't have per-queue info for this
+                                                 * one, but we can enable it per-queue through
+                                                 * TXNOFRM_QCU field on TXNOFRM register */
 #define AR5K_ISR_TXEOL          0x00000400      /* Empty TX descriptor */
 #define AR5K_ISR_TXURN          0x00000800      /* Transmit FIFO underrun */
 #define AR5K_ISR_MIB            0x00001000      /* Update MIB counters */
@@ -302,21 +309,29 @@
 #define AR5K_ISR_SWBA           0x00010000      /* Software beacon alert */
 #define AR5K_ISR_BRSSI          0x00020000      /* Beacon rssi below threshold (?) */
 #define AR5K_ISR_BMISS          0x00040000      /* Beacon missed */
-#define AR5K_ISR_HIUERR         0x00080000      /* Host Interface Unit error [5211+] */
+#define AR5K_ISR_HIUERR         0x00080000      /* Host Interface Unit error [5211+]
+                                                 * 'or' of MCABT, SSERR, DPERR from SISR2 */
 #define AR5K_ISR_BNR            0x00100000      /* Beacon not ready [5211+] */
 #define AR5K_ISR_MCABT          0x00100000      /* Master Cycle Abort [5210] */
 #define AR5K_ISR_RXCHIRP        0x00200000      /* CHIRP Received [5212+] */
 #define AR5K_ISR_SSERR          0x00200000      /* Signaled System Error [5210] */
-#define AR5K_ISR_DPERR          0x00400000      /* Det par Error (?) [5210] */
+#define AR5K_ISR_DPERR          0x00400000      /* Bus parity error [5210] */
 #define AR5K_ISR_RXDOPPLER      0x00400000      /* Doppler chirp received [5212+] */
 #define AR5K_ISR_TIM            0x00800000      /* [5211+] */
-#define AR5K_ISR_BCNMISC        0x00800000      /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
-                                                CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
+#define AR5K_ISR_BCNMISC        0x00800000      /* Misc beacon related interrupt
+                                                 * 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
+                                                 * CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
 #define AR5K_ISR_GPIO           0x01000000      /* GPIO (rf kill) */
 #define AR5K_ISR_QCBRORN        0x02000000      /* QCU CBR overrun [5211+] */
 #define AR5K_ISR_QCBRURN        0x04000000      /* QCU CBR underrun [5211+] */
 #define AR5K_ISR_QTRIG          0x08000000      /* QCU scheduling trigger [5211+] */
 
+#define AR5K_ISR_BITS_FROM_SISRS        (AR5K_ISR_TXOK | AR5K_ISR_TXDESC |\
+                                        AR5K_ISR_TXERR | AR5K_ISR_TXEOL |\
+                                        AR5K_ISR_TXURN | AR5K_ISR_HIUERR |\
+                                        AR5K_ISR_BCNMISC | AR5K_ISR_QCBRORN |\
+                                        AR5K_ISR_QCBRURN | AR5K_ISR_QTRIG)
+
 /*
  * Secondary status registers [5211+] (0 - 4)
  *
@@ -347,7 +362,7 @@
 #define AR5K_SISR2_BCN_TIMEOUT  0x08000000      /* Beacon Timeout [5212+] */
 #define AR5K_SISR2_CAB_TIMEOUT  0x10000000      /* CAB Timeout [5212+] */
 #define AR5K_SISR2_DTIM         0x20000000      /* [5212+] */
-#define AR5K_SISR2_TSFOOR       0x80000000      /* TSF OOR (?) */
+#define AR5K_SISR2_TSFOOR       0x80000000      /* TSF Out of range */
 
 #define AR5K_SISR3              0x0090                  /* Register Address [5211+] */
 #define AR5K_SISR3_QCBRORN      0x000003ff      /* Mask for QCBRORN */
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index 2abac257b4b4..4aed3a3ab109 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -19,9 +19,9 @@
  *
  */
 
-/*****************************\
-  Reset functions and helpers
-\*****************************/
+/****************************\
+  Reset function and helpers
+\****************************/
 
 #include <asm/unaligned.h>
 
@@ -33,14 +33,36 @@
 #include "debug.h"
 
 
+/**
+ * DOC: Reset function and helpers
+ *
+ * Here we implement the main reset routine, used to bring the card
+ * to a working state and ready to receive. We also handle routines
+ * that don't fit on other places such as clock, sleep and power control
+ */
+
+
 /******************\
 * Helper functions *
 \******************/
 
-/*
- * Check if a register write has been completed
+/**
+ * ath5k_hw_register_timeout() - Poll a register for a flag/field change
+ * @ah: The &struct ath5k_hw
+ * @reg: The register to read
+ * @flag: The flag/field to check on the register
+ * @val: The field value we expect (if we check a field)
+ * @is_set: Instead of checking if the flag got cleared, check if it got set
+ *
+ * Some registers contain flags that indicate that an operation is
+ * running. We use this function to poll these registers and check
+ * if these flags get cleared. We also use it to poll a register
+ * field (containing multiple flags) until it gets a specific value.
+ *
+ * Returns -EAGAIN if we exceeded AR5K_TUNE_REGISTER_TIMEOUT * 15us or 0
  */
-int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
+int
+ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
                               bool is_set)
 {
         int i;
@@ -64,35 +86,48 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
 \*************************/
 
 /**
- * ath5k_hw_htoclock - Translate usec to hw clock units
- *
+ * ath5k_hw_htoclock() - Translate usec to hw clock units
  * @ah: The &struct ath5k_hw
  * @usec: value in microseconds
+ *
+ * Translate usecs to hw clock units based on the current
+ * hw clock rate.
+ *
+ * Returns number of clock units
  */
-unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
+unsigned int
+ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
 {
         struct ath_common *common = ath5k_hw_common(ah);
         return usec * common->clockrate;
 }
 
 /**
- * ath5k_hw_clocktoh - Translate hw clock units to usec
+ * ath5k_hw_clocktoh() - Translate hw clock units to usec
+ * @ah: The &struct ath5k_hw
  * @clock: value in hw clock units
+ *
+ * Translate hw clock units to usecs based on the current
+ * hw clock rate.
+ *
+ * Returns number of usecs
  */
-unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
+unsigned int
+ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
 {
         struct ath_common *common = ath5k_hw_common(ah);
         return clock / common->clockrate;
 }
 
 /**
- * ath5k_hw_init_core_clock - Initialize core clock
- *
- * @ah The &struct ath5k_hw
+ * ath5k_hw_init_core_clock() - Initialize core clock
+ * @ah: The &struct ath5k_hw
  *
- * Initialize core clock parameters (usec, usec32, latencies etc).
+ * Initialize core clock parameters (usec, usec32, latencies etc),
+ * based on current bwmode and chipset properties.
  */
-static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
+static void
+ath5k_hw_init_core_clock(struct ath5k_hw *ah)
 {
         struct ieee80211_channel *channel = ah->ah_current_channel;
         struct ath_common *common = ath5k_hw_common(ah);
@@ -227,16 +262,21 @@ static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
         }
 }
 
-/*
+/**
+ * ath5k_hw_set_sleep_clock() - Setup sleep clock operation
+ * @ah: The &struct ath5k_hw
+ * @enable: Enable sleep clock operation (false to disable)
+ *
  * If there is an external 32KHz crystal available, use it
  * as ref. clock instead of 32/40MHz clock and baseband clocks
  * to save power during sleep or restore normal 32/40MHz
  * operation.
  *
- * XXX: When operating on 32KHz certain PHY registers (27 - 31,
- *      123 - 127) require delay on access.
+ * NOTE: When operating on 32KHz certain PHY registers (27 - 31,
+ * 123 - 127) require delay on access.
  */
-static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
+static void
+ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
 {
         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
         u32 scal, spending, sclock;
@@ -340,10 +380,19 @@ static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
 * Reset/Sleep control *
 \*********************/
 
-/*
- * Reset chipset
+/**
+ * ath5k_hw_nic_reset() - Reset the various chipset units
+ * @ah: The &struct ath5k_hw
+ * @val: Mask to indicate what units to reset
+ *
+ * To reset the various chipset units we need to write
+ * the mask to AR5K_RESET_CTL and poll the register until
+ * all flags are cleared.
+ *
+ * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
  */
-static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
+static int
+ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
 {
         int ret;
         u32 mask = val ? val : ~0U;
@@ -357,7 +406,7 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
         ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
 
         /* Wait at least 128 PCI clocks */
-        udelay(15);
+        usleep_range(15, 20);
 
         if (ah->ah_version == AR5K_AR5210) {
                 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
@@ -382,12 +431,17 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
         return ret;
 }
 
-/*
- * Reset AHB chipset
- * AR5K_RESET_CTL_PCU flag resets WMAC
- * AR5K_RESET_CTL_BASEBAND flag resets WBB
+/**
+ * ath5k_hw_wisoc_reset() -  Reset AHB chipset
+ * @ah: The &struct ath5k_hw
+ * @flags: Mask to indicate what units to reset
+ *
+ * Same as ath5k_hw_nic_reset but for AHB based devices
+ *
+ * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
  */
-static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
+static int
+ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
 {
         u32 mask = flags ? flags : ~0U;
         u32 __iomem *reg;
@@ -422,7 +476,7 @@ static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
         regval = __raw_readl(reg);
         __raw_writel(regval | val, reg);
         regval = __raw_readl(reg);
-        udelay(100);
+        usleep_range(100, 150);
 
         /* Bring BB/MAC out of reset */
         __raw_writel(regval & ~val, reg);
@@ -439,11 +493,23 @@ static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
         return 0;
 }
 
-
-/*
- * Sleep control
+/**
+ * ath5k_hw_set_power_mode() - Set power mode
+ * @ah: The &struct ath5k_hw
+ * @mode: One of enum ath5k_power_mode
+ * @set_chip: Set to true to write sleep control register
+ * @sleep_duration: How much time the device is allowed to sleep
+ * when sleep logic is enabled (in 128 microsecond increments).
+ *
+ * This function is used to configure sleep policy and allowed
+ * sleep modes. For more information check out the sleep control
+ * register on reg.h and STA_ID1.
+ *
+ * Returns 0 on success, -EIO if chip didn't wake up or -EINVAL if an invalid
+ * mode is requested.
  */
-static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
+static int
+ath5k_hw_set_power_mode(struct ath5k_hw *ah, enum ath5k_power_mode mode,
                               bool set_chip, u16 sleep_duration)
 {
         unsigned int i;
@@ -493,7 +559,7 @@ static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
 
                 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
                                                         AR5K_SLEEP_CTL);
-                udelay(15);
+                usleep_range(15, 20);
 
                 for (i = 200; i > 0; i--) {
                         /* Check if the chip did wake up */
@@ -502,7 +568,7 @@ static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
                                 break;
 
                         /* Wait a bit and retry */
-                        udelay(50);
+                        usleep_range(50, 75);
                         ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
                                                         AR5K_SLEEP_CTL);
                 }
@@ -523,17 +589,20 @@ commit:
         return 0;
 }
 
-/*
- * Put device on hold
+/**
+ * ath5k_hw_on_hold() - Put device on hold
+ * @ah: The &struct ath5k_hw
  *
- * Put MAC and Baseband on warm reset and
- * keep that state (don't clean sleep control
- * register). After this MAC and Baseband are
- * disabled and a full reset is needed to come
- * back. This way we save as much power as possible
+ * Put MAC and Baseband on warm reset and keep that state
+ * (don't clean sleep control register). After this MAC
+ * and Baseband are disabled and a full reset is needed
+ * to come back. This way we save as much power as possible
  * without putting the card on full sleep.
+ *
+ * Returns 0 on success or -EIO on error
  */
-int ath5k_hw_on_hold(struct ath5k_hw *ah)
+int
+ath5k_hw_on_hold(struct ath5k_hw *ah)
 {
         struct pci_dev *pdev = ah->pdev;
         u32 bus_flags;
@@ -543,7 +612,7 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
                 return 0;
 
         /* Make sure device is awake */
-        ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
+        ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
         if (ret) {
                 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
                 return ret;
@@ -563,7 +632,7 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
                         AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
                         AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
-                        mdelay(2);
+                        usleep_range(2000, 2500);
         } else {
                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
                         AR5K_RESET_CTL_BASEBAND | bus_flags);
@@ -575,7 +644,7 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
         }
 
         /* ...wakeup again!*/
-        ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
+        ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
         if (ret) {
                 ATH5K_ERR(ah, "failed to put device on hold\n");
                 return ret;
@@ -584,11 +653,18 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
         return ret;
 }
 
-/*
+/**
+ * ath5k_hw_nic_wakeup() - Force card out of sleep
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ *
  * Bring up MAC + PHY Chips and program PLL
- * Channel is NULL for the initial wakeup.
+ * NOTE: Channel is NULL for the initial wakeup.
+ *
+ * Returns 0 on success, -EIO on hw failure or -EINVAL for false channel infos
  */
-int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
+int
+ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
 {
         struct pci_dev *pdev = ah->pdev;
         u32 turbo, mode, clock, bus_flags;
@@ -600,7 +676,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
 
         if ((ath5k_get_bus_type(ah) != ATH_AHB) || channel) {
                 /* Wakeup the device */
-                ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
+                ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
                 if (ret) {
                         ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
                         return ret;
@@ -621,7 +697,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
                         AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
                         AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
-                        mdelay(2);
+                        usleep_range(2000, 2500);
         } else {
                 if (ath5k_get_bus_type(ah) == ATH_AHB)
                         ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
@@ -637,7 +713,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
         }
 
         /* ...wakeup again!...*/
-        ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
+        ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
         if (ret) {
                 ATH5K_ERR(ah, "failed to resume the MAC Chip\n");
                 return ret;
@@ -739,7 +815,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
                 /* ...update PLL if needed */
                 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
                         ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
-                        udelay(300);
+                        usleep_range(300, 350);
                 }
 
                 /* ...set the PHY operating mode */
@@ -755,8 +831,19 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
 * Post-initvals register modifications *
 \**************************************/
 
-/* TODO: Half/Quarter rate */
-static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
+/**
+ * ath5k_hw_tweak_initval_settings() - Tweak initial settings
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ *
+ * Some settings are not handled on initvals, e.g. bwmode
+ * settings, some phy settings, workarounds etc that in general
+ * don't fit anywhere else or are too small to introduce a separate
+ * function for each one. So we have this function to handle
+ * them all during reset and complete card's initialization.
+ */
+static void
+ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
                                 struct ieee80211_channel *channel)
 {
         if (ah->ah_version == AR5K_AR5212 &&
@@ -875,7 +962,16 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
         }
 }
 
-static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
+/**
+ * ath5k_hw_commit_eeprom_settings() - Commit settings from EEPROM
+ * @ah: The &struct ath5k_hw
+ * @channel: The &struct ieee80211_channel
+ *
+ * Use settings stored on EEPROM to properly initialize the card
+ * based on various infos and per-mode calibration data.
+ */
+static void
+ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
                 struct ieee80211_channel *channel)
 {
         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
@@ -1029,7 +1125,23 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
 * Main reset function *
 \*********************/
 
-int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
+/**
+ * ath5k_hw_reset() - The main reset function
+ * @ah: The &struct ath5k_hw
+ * @op_mode: One of enum nl80211_iftype
+ * @channel: The &struct ieee80211_channel
+ * @fast: Enable fast channel switching
+ * @skip_pcu: Skip pcu initialization
+ *
+ * This is the function we call each time we want to (re)initialize the
+ * card and pass new settings to hw. We also call it when hw runs into
+ * trouble to make it come back to a working state.
+ *
+ * Returns 0 on success, -EINVAL on false op_mode or channel infos, or -EIO
+ * on failure.
+ */
+int
+ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
                 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
 {
         u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
@@ -1242,7 +1354,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
         /*
          * Initialize PCU
          */
-        ath5k_hw_pcu_init(ah, op_mode, mode);
+        ath5k_hw_pcu_init(ah, op_mode);
 
         /*
          * Initialize PHY
diff --git a/drivers/net/wireless/ath/ath5k/rfbuffer.h b/drivers/net/wireless/ath/ath5k/rfbuffer.h
index 5d11c23b4297..aed34d9954c0 100644
--- a/drivers/net/wireless/ath/ath5k/rfbuffer.h
+++ b/drivers/net/wireless/ath/ath5k/rfbuffer.h
@@ -18,7 +18,9 @@
  */
 
 
-/*
+/**
+ * DOC: RF Buffer registers
+ *
  * There are some special registers on the RF chip
  * that control various operation settings related mostly to
  * the analog parts (channel, gain adjustment etc).
@@ -44,40 +46,63 @@
  */
 
 
-/*
+/**
+ * struct ath5k_ini_rfbuffer - Initial RF Buffer settings
+ * @rfb_bank: RF Bank number
+ * @rfb_ctrl_register: RF Buffer control register
+ * @rfb_mode_data: RF Buffer data for each mode
+ *
  * Struct to hold default mode specific RF
- * register values (RF Banks)
+ * register values (RF Banks) for each chip.
  */
 struct ath5k_ini_rfbuffer {
-        u8      rfb_bank;               /* RF Bank number */
-        u16     rfb_ctrl_register;      /* RF Buffer control register */
-        u32     rfb_mode_data[3];       /* RF Buffer data for each mode */
+        u8      rfb_bank;
+        u16     rfb_ctrl_register;
+        u32     rfb_mode_data[3];
 };
 
-/*
+/**
+ * struct ath5k_rfb_field - An RF Buffer field (register/value)
+ * @len: Field length
+ * @pos: Offset on the raw packet
+ * @col: Used for shifting
+ *
  * Struct to hold RF Buffer field
  * infos used to access certain RF
  * analog registers
  */
 struct ath5k_rfb_field {
-        u8      len;    /* Field length */
-        u16     pos;    /* Offset on the raw packet */
-        u8      col;    /* Column -used for shifting */
+        u8      len;
+        u16     pos;
+        u8      col;
 };
 
-/*
- * RF analog register definition
+/**
+ * struct ath5k_rf_reg - RF analog register definition
+ * @bank: RF Buffer Bank number
+ * @index: Register's index on ath5k_rf_regx_idx
+ * @field: The &struct ath5k_rfb_field
+ *
+ * We use this struct to define the set of RF registers
+ * on each chip that we want to tweak. Some RF registers
+ * are common between different chip versions so this saves
+ * us space and complexity because we can refer to an rf
+ * register by it's index no matter what chip we work with
+ * as long as it has that register.
  */
 struct ath5k_rf_reg {
-        u8                      bank;   /* RF Buffer Bank number */
-        u8                      index;  /* Register's index on rf_regs_idx */
-        struct ath5k_rfb_field  field;  /* RF Buffer field for this register */
+        u8                      bank;
+        u8                      index;
+        struct ath5k_rfb_field  field;
 };
 
-/* Map RF registers to indexes
+/**
+ * enum ath5k_rf_regs_idx - Map RF registers to indexes
+ *
  * We do this to handle common bits and make our
  * life easier by using an index for each register
- * instead of a full rfb_field */
+ * instead of a full rfb_field
+ */
 enum ath5k_rf_regs_idx {
         /* BANK 2 */
         AR5K_RF_TURBO = 0,
diff --git a/drivers/net/wireless/ath/ath5k/rfgain.h b/drivers/net/wireless/ath/ath5k/rfgain.h
index ebfae052d89e..4d21df0e5975 100644
--- a/drivers/net/wireless/ath/ath5k/rfgain.h
+++ b/drivers/net/wireless/ath/ath5k/rfgain.h
@@ -18,13 +18,17 @@
  *
  */
 
-/*
+/**
+ * struct ath5k_ini_rfgain - RF Gain table
+ * @rfg_register: RF Gain register address
+ * @rfg_value: Register value for 5 and 2GHz
+ *
  * Mode-specific RF Gain table (64bytes) for RF5111/5112
  * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
  * RF Gain values are included in AR5K_AR5210_INI)
  */
 struct ath5k_ini_rfgain {
-        u16     rfg_register;   /* RF Gain register address */
+        u16     rfg_register;
         u32     rfg_value[2];   /* [freq (see below)] */
 };
 
@@ -455,18 +459,31 @@ static const struct ath5k_ini_rfgain rfgain_2425[] = {
 #define AR5K_GAIN_CHECK_ADJUST(_g)              \
         ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
 
+/**
+ * struct ath5k_gain_opt_step - An RF gain optimization step
+ * @gos_param: Set of parameters
+ * @gos_gain: Gain
+ */
 struct ath5k_gain_opt_step {
         s8                              gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
         s8                              gos_gain;
 };
 
+/**
+ * struct ath5k_gain_opt - RF Gain optimization ladder
+ * @go_default: The default step
+ * @go_steps_count: How many optimization steps
+ * @go_step: Array of &struct ath5k_gain_opt_step
+ */
 struct ath5k_gain_opt {
         u8                              go_default;
         u8                              go_steps_count;
         const struct ath5k_gain_opt_step        go_step[AR5K_GAIN_STEP_COUNT];
 };
 
+
 /*
+ * RF5111
  * Parameters on gos_param:
  * 1) Tx clip PHY register
  * 2) PWD 90 RF register
@@ -490,6 +507,7 @@ static const struct ath5k_gain_opt rfgain_opt_5111 = {
 };
 
 /*
+ * RF5112
  * Parameters on gos_param:
  * 1) Mixgain ovr RF register
  * 2) PWD 138 RF register
diff --git a/drivers/net/wireless/ath/ath6kl/cfg80211.c b/drivers/net/wireless/ath/ath6kl/cfg80211.c
index abe3af3c6188..6c59a217b1a1 100644
--- a/drivers/net/wireless/ath/ath6kl/cfg80211.c
+++ b/drivers/net/wireless/ath/ath6kl/cfg80211.c
@@ -14,6 +14,8 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/moduleparam.h>
+
 #include "core.h"
 #include "cfg80211.h"
 #include "debug.h"
diff --git a/drivers/net/wireless/ath/ath6kl/debug.c b/drivers/net/wireless/ath/ath6kl/debug.c
index cf513a80b061..eb808b46f94c 100644
--- a/drivers/net/wireless/ath/ath6kl/debug.c
+++ b/drivers/net/wireless/ath/ath6kl/debug.c
@@ -19,6 +19,7 @@
 #include <linux/circ_buf.h>
 #include <linux/fs.h>
 #include <linux/vmalloc.h>
+#include <linux/export.h>
 
 #include "debug.h"
 #include "target.h"
diff --git a/drivers/net/wireless/ath/ath6kl/debug.h b/drivers/net/wireless/ath/ath6kl/debug.h
index 9b779aac83e7..e569c652e35c 100644
--- a/drivers/net/wireless/ath/ath6kl/debug.h
+++ b/drivers/net/wireless/ath/ath6kl/debug.h
@@ -46,8 +46,8 @@ enum ATH6K_DEBUG_MASK {
 };
 
 extern unsigned int debug_mask;
-extern int ath6kl_printk(const char *level, const char *fmt, ...)
-        __attribute__ ((format (printf, 2, 3)));
+extern __printf(2, 3)
+int ath6kl_printk(const char *level, const char *fmt, ...);
 
 #define ath6kl_info(fmt, ...)                           \
         ath6kl_printk(KERN_INFO, fmt, ##__VA_ARGS__)
diff --git a/drivers/net/wireless/ath/ath6kl/init.c b/drivers/net/wireless/ath/ath6kl/init.c
index c614049d7b2e..368ecbd172a3 100644
--- a/drivers/net/wireless/ath/ath6kl/init.c
+++ b/drivers/net/wireless/ath/ath6kl/init.c
@@ -1663,6 +1663,7 @@ int ath6kl_core_init(struct ath6kl *ar)
 
         ar->wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM |
                             WIPHY_FLAG_HAVE_AP_SME |
+                            WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL |
                             WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD;
 
         if (test_bit(ATH6KL_FW_CAPABILITY_SCHED_SCAN, ar->fw_capabilities))
diff --git a/drivers/net/wireless/ath/ath6kl/sdio.c b/drivers/net/wireless/ath/ath6kl/sdio.c
index 07903e6114d8..15c3f56caf4f 100644
--- a/drivers/net/wireless/ath/ath6kl/sdio.c
+++ b/drivers/net/wireless/ath/ath6kl/sdio.c
@@ -14,6 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/module.h>
 #include <linux/mmc/card.h>
 #include <linux/mmc/mmc.h>
 #include <linux/mmc/host.h>
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index 7b4c074e12fa..1b4786ae00ac 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -2,6 +2,9 @@ config ATH9K_HW
         tristate
 config ATH9K_COMMON
         tristate
+config ATH9K_DFS_DEBUGFS
+        def_bool y
+        depends on ATH9K_DEBUGFS && ATH9K_DFS_CERTIFIED
 
 config ATH9K
         tristate "Atheros 802.11n wireless cards support"
@@ -51,6 +54,25 @@ config ATH9K_DEBUGFS
 
           Also required for changing debug message flags at run time.
 
+config ATH9K_DFS_CERTIFIED
+        bool "Atheros DFS support for certified platforms"
+        depends on ATH9K && EXPERT
+        default n
+        ---help---
+          This option enables DFS support for initiating radiation on
+          ath9k. There is no way to dynamically detect if a card was DFS
+          certified and as such this is left as a build time option. This
+          option should only be enabled by system integrators that can
+          guarantee that all the platforms that their kernel will run on
+          have obtained appropriate regulatory body certification for a
+          respective Atheros card by using ath9k on the target shipping
+          platforms.
+
+          This is currently only a placeholder for future DFS support,
+          as DFS support requires more components that still need to be
+          developed. At this point enabling this option won't do anything
+          except increase code size.
+
 config ATH9K_RATE_CONTROL
         bool "Atheros ath9k rate control"
         depends on ATH9K
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 49d3f25f509d..da02242499af 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -10,6 +10,8 @@ ath9k-$(CONFIG_ATH9K_RATE_CONTROL) += rc.o
 ath9k-$(CONFIG_ATH9K_PCI) += pci.o
 ath9k-$(CONFIG_ATH9K_AHB) += ahb.o
 ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
+ath9k-$(CONFIG_ATH9K_DFS_DEBUGFS) += dfs_debug.o
+ath9k-$(CONFIG_ATH9K_DFS_CERTIFIED) += dfs.o
 
 obj-$(CONFIG_ATH9K) += ath9k.o
 
@@ -34,7 +36,8 @@ ath9k_hw-y:=	\
                 ar9002_mac.o \
                 ar9003_mac.o \
                 ar9003_eeprom.o \
-                ar9003_paprd.o
+                ar9003_paprd.o \
+                ar9003_mci.o
 
 obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
 
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 85a54cd2b083..5e47ca6d16a8 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -19,6 +19,7 @@
 #include <linux/nl80211.h>
 #include <linux/platform_device.h>
 #include <linux/ath9k_platform.h>
+#include <linux/module.h>
 #include "ath9k.h"
 
 static const struct platform_device_id ath9k_platform_id_table[] = {
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 2776c3c1f506..a639b94f7643 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -15,6 +15,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/export.h>
 #include "hw.h"
 #include "hw-ops.h"
 
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
index 88279e325dca..157337febc2b 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
@@ -203,7 +203,7 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         i);
 
                 ath_dbg(common, ATH_DBG_CALIBRATE,
-                        "Orignal: Chn %diq_corr_meas = 0x%08x\n",
+                        "Original: Chn %d iq_corr_meas = 0x%08x\n",
                         i, ah->totalIqCorrMeas[i]);
 
                 iqCorrNeg = 0;
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index 626d547d2f06..11f192a1ceb7 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -14,6 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/moduleparam.h>
 #include "hw.h"
 #include "ar5008_initvals.h"
 #include "ar9001_initvals.h"
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
index f7d8e516a2a9..b5920168606d 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
@@ -15,6 +15,7 @@
  */
 
 #include "hw.h"
+#include <linux/export.h>
 
 #define AR_BufLen           0x00000fff
 
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
index 12a730dcb500..23b3a6c57800 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -18,6 +18,7 @@
 #include "hw-ops.h"
 #include "ar9003_phy.h"
 #include "ar9003_rtt.h"
+#include "ar9003_mci.h"
 
 #define MAX_MEASUREMENT MAX_IQCAL_MEASUREMENT
 #define MAX_MAG_DELTA   11
@@ -225,7 +226,7 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         i);
 
                 ath_dbg(common, ATH_DBG_CALIBRATE,
-                        "Orignal: Chn %diq_corr_meas = 0x%08x\n",
+                        "Original: Chn %d iq_corr_meas = 0x%08x\n",
                         i, ah->totalIqCorrMeas[i]);
 
                 iqCorrNeg = 0;
@@ -824,7 +825,7 @@ static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah, bool is_reusable)
                                                 chan_info_tab[i] + offset);
 
                                 ath_dbg(common, ATH_DBG_CALIBRATE,
-                                        "IQ RES[%d]=0x%x"
+                                        "IQ_RES[%d]=0x%x "
                                         "IQ_RES[%d]=0x%x\n",
                                         idx, iq_res[idx], idx + 1,
                                         iq_res[idx + 1]);
@@ -934,10 +935,12 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
 {
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_hw_cal_data *caldata = ah->caldata;
+        struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
         bool txiqcal_done = false, txclcal_done = false;
         bool is_reusable = true, status = true;
         bool run_rtt_cal = false, run_agc_cal;
         bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
+        bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
         u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
                                           AR_PHY_AGC_CONTROL_FLTR_CAL   |
                                           AR_PHY_AGC_CONTROL_PKDET_CAL;
@@ -1005,6 +1008,31 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
         } else if (caldata && !caldata->done_txiqcal_once)
                 run_agc_cal = true;
 
+        if (mci && IS_CHAN_2GHZ(chan) &&
+            (mci_hw->bt_state  == MCI_BT_AWAKE) &&
+            run_agc_cal &&
+            !(mci_hw->config & ATH_MCI_CONFIG_DISABLE_MCI_CAL)) {
+
+                u32 pld[4] = {0, 0, 0, 0};
+
+                /* send CAL_REQ only when BT is AWAKE. */
+                ath_dbg(common, ATH_DBG_MCI, "MCI send WLAN_CAL_REQ 0x%x\n",
+                        mci_hw->wlan_cal_seq);
+                MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_REQ);
+                pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_seq++;
+                ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false);
+
+                /* Wait BT_CAL_GRANT for 50ms */
+                ath_dbg(common, ATH_DBG_MCI, "MCI wait for BT_CAL_GRANT");
+
+                if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_GRANT, 0, 50000))
+                        ath_dbg(common, ATH_DBG_MCI, "MCI got BT_CAL_GRANT");
+                else {
+                        is_reusable = false;
+                        ath_dbg(common, ATH_DBG_MCI, "\nMCI BT is not responding");
+                }
+        }
+
         txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
         udelay(5);
@@ -1022,6 +1050,21 @@ skip_tx_iqcal:
                                        AR_PHY_AGC_CONTROL_CAL,
                                        0, AH_WAIT_TIMEOUT);
         }
+
+        if (mci && IS_CHAN_2GHZ(chan) &&
+            (mci_hw->bt_state  == MCI_BT_AWAKE) &&
+            run_agc_cal &&
+            !(mci_hw->config & ATH_MCI_CONFIG_DISABLE_MCI_CAL)) {
+
+                u32 pld[4] = {0, 0, 0, 0};
+
+                ath_dbg(common, ATH_DBG_MCI, "MCI Send WLAN_CAL_DONE 0x%x\n",
+                        mci_hw->wlan_cal_done);
+                MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_DONE);
+                pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_done++;
+                ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false);
+        }
+
         if (rtt && !run_rtt_cal) {
                 agc_ctrl |= agc_supp_cals;
                 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index a93bd63ad23b..4ba6f52943a8 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -4779,7 +4779,7 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
 {
         struct ath_common *common = ath9k_hw_common(ah);
         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
-        u16 twiceMaxEdgePower = MAX_RATE_POWER;
+        u16 twiceMaxEdgePower;
         int i;
         u16 scaledPower = 0, minCtlPower;
         static const u16 ctlModesFor11a[] = {
@@ -4880,6 +4880,7 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
                         ctlNum = AR9300_NUM_CTLS_5G;
                 }
 
+                twiceMaxEdgePower = MAX_RATE_POWER;
                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
                         ath_dbg(common, ATH_DBG_REGULATORY,
                                 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index b363cc06cfd9..631fe4f2e495 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -13,6 +13,7 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
+#include <linux/export.h>
 #include "hw.h"
 #include "ar9003_mac.h"
 
@@ -174,20 +175,24 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
         u32 isr = 0;
         u32 mask2 = 0;
         struct ath9k_hw_capabilities *pCap = &ah->caps;
-        u32 sync_cause = 0;
         struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 sync_cause = 0, async_cause;
 
-        if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
+        async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
+
+        if (async_cause & (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_MASK_MCI)) {
                 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
                                 == AR_RTC_STATUS_ON)
                         isr = REG_READ(ah, AR_ISR);
         }
 
+
         sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
 
         *masked = 0;
 
-        if (!isr && !sync_cause)
+        if (!isr && !sync_cause && !async_cause)
                 return false;
 
         if (isr) {
@@ -293,6 +298,35 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
                         ar9003_hw_bb_watchdog_read(ah);
         }
 
+        if (async_cause & AR_INTR_ASYNC_MASK_MCI) {
+                u32 raw_intr, rx_msg_intr;
+
+                rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
+                raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);
+
+                if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef))
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI gets 0xdeadbeef during MCI int processing"
+                                "new raw_intr=0x%08x, new rx_msg_raw=0x%08x, "
+                                "raw_intr=0x%08x, rx_msg_raw=0x%08x\n",
+                                raw_intr, rx_msg_intr, mci->raw_intr,
+                                mci->rx_msg_intr);
+                else {
+                        mci->rx_msg_intr |= rx_msg_intr;
+                        mci->raw_intr |= raw_intr;
+                        *masked |= ATH9K_INT_MCI;
+
+                        if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO)
+                                mci->cont_status =
+                                        REG_READ(ah, AR_MCI_CONT_STATUS);
+
+                        REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);
+                        REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);
+                        ath_dbg(common, ATH_DBG_MCI, "AR_INTR_SYNC_MCI\n");
+
+                }
+        }
+
         if (sync_cause) {
                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mci.c b/drivers/net/wireless/ath/ath9k/ar9003_mci.c
new file mode 100644
index 000000000000..8599822dc83f
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mci.c
@@ -0,0 +1,1464 @@
+/*
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/export.h>
+#include "hw.h"
+#include "ar9003_phy.h"
+#include "ar9003_mci.h"
+
+static void ar9003_mci_reset_req_wakeup(struct ath_hw *ah)
+{
+        if (!AR_SREV_9462_20(ah))
+                return;
+
+        REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
+                      AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 1);
+        udelay(1);
+        REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
+                      AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 0);
+}
+
+static int ar9003_mci_wait_for_interrupt(struct ath_hw *ah, u32 address,
+                                        u32 bit_position, int time_out)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        while (time_out) {
+
+                if (REG_READ(ah, address) & bit_position) {
+
+                        REG_WRITE(ah, address, bit_position);
+
+                        if (address == AR_MCI_INTERRUPT_RX_MSG_RAW) {
+
+                                if (bit_position &
+                                    AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)
+                                        ar9003_mci_reset_req_wakeup(ah);
+
+                                if (bit_position &
+                                    (AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING |
+                                     AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING))
+                                        REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
+                                        AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE);
+
+                                REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
+                                          AR_MCI_INTERRUPT_RX_MSG);
+                        }
+                        break;
+                }
+
+                udelay(10);
+                time_out -= 10;
+
+                if (time_out < 0)
+                        break;
+        }
+
+        if (time_out <= 0) {
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Wait for Reg 0x%08x = 0x%08x timeout.\n",
+                        address, bit_position);
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI INT_RAW = 0x%08x, RX_MSG_RAW = 0x%08x",
+                        REG_READ(ah, AR_MCI_INTERRUPT_RAW),
+                        REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
+                time_out = 0;
+        }
+
+        return time_out;
+}
+
+void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done)
+{
+        u32 payload[4] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffff00};
+
+        ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, payload, 16,
+                                wait_done, false);
+        udelay(5);
+}
+
+void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done)
+{
+        u32 payload = 0x00000000;
+
+        ar9003_mci_send_message(ah, MCI_LNA_TRANS, 0, &payload, 1,
+                                wait_done, false);
+}
+
+static void ar9003_mci_send_req_wake(struct ath_hw *ah, bool wait_done)
+{
+        ar9003_mci_send_message(ah, MCI_REQ_WAKE, MCI_FLAG_DISABLE_TIMESTAMP,
+                                NULL, 0, wait_done, false);
+        udelay(5);
+}
+
+void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done)
+{
+        ar9003_mci_send_message(ah, MCI_SYS_WAKING, MCI_FLAG_DISABLE_TIMESTAMP,
+                                NULL, 0, wait_done, false);
+}
+
+static void ar9003_mci_send_lna_take(struct ath_hw *ah, bool wait_done)
+{
+        u32 payload = 0x70000000;
+
+        ar9003_mci_send_message(ah, MCI_LNA_TAKE, 0, &payload, 1,
+                                wait_done, false);
+}
+
+static void ar9003_mci_send_sys_sleeping(struct ath_hw *ah, bool wait_done)
+{
+        ar9003_mci_send_message(ah, MCI_SYS_SLEEPING,
+                                MCI_FLAG_DISABLE_TIMESTAMP,
+                                NULL, 0, wait_done, false);
+}
+
+static void ar9003_mci_send_coex_version_query(struct ath_hw *ah,
+                                               bool wait_done)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 payload[4] = {0, 0, 0, 0};
+
+        if (!mci->bt_version_known &&
+                        (mci->bt_state != MCI_BT_SLEEP)) {
+                ath_dbg(common, ATH_DBG_MCI, "MCI Send Coex version query\n");
+                MCI_GPM_SET_TYPE_OPCODE(payload,
+                                MCI_GPM_COEX_AGENT, MCI_GPM_COEX_VERSION_QUERY);
+                ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
+                                wait_done, true);
+        }
+}
+
+static void ar9003_mci_send_coex_version_response(struct ath_hw *ah,
+                                                     bool wait_done)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 payload[4] = {0, 0, 0, 0};
+
+        ath_dbg(common, ATH_DBG_MCI, "MCI Send Coex version response\n");
+        MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT,
+                        MCI_GPM_COEX_VERSION_RESPONSE);
+        *(((u8 *)payload) + MCI_GPM_COEX_B_MAJOR_VERSION) =
+                mci->wlan_ver_major;
+        *(((u8 *)payload) + MCI_GPM_COEX_B_MINOR_VERSION) =
+                mci->wlan_ver_minor;
+        ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
+}
+
+static void ar9003_mci_send_coex_wlan_channels(struct ath_hw *ah,
+                                                  bool wait_done)
+{
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 *payload = &mci->wlan_channels[0];
+
+        if ((mci->wlan_channels_update == true) &&
+                        (mci->bt_state != MCI_BT_SLEEP)) {
+                MCI_GPM_SET_TYPE_OPCODE(payload,
+                MCI_GPM_COEX_AGENT, MCI_GPM_COEX_WLAN_CHANNELS);
+                ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
+                                        wait_done, true);
+                MCI_GPM_SET_TYPE_OPCODE(payload, 0xff, 0xff);
+        }
+}
+
+static void ar9003_mci_send_coex_bt_status_query(struct ath_hw *ah,
+                                                bool wait_done, u8 query_type)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 payload[4] = {0, 0, 0, 0};
+        bool query_btinfo = !!(query_type & (MCI_GPM_COEX_QUERY_BT_ALL_INFO |
+                                             MCI_GPM_COEX_QUERY_BT_TOPOLOGY));
+
+        if (mci->bt_state != MCI_BT_SLEEP) {
+
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Send Coex BT Status Query 0x%02X\n", query_type);
+
+                MCI_GPM_SET_TYPE_OPCODE(payload,
+                                MCI_GPM_COEX_AGENT, MCI_GPM_COEX_STATUS_QUERY);
+
+                *(((u8 *)payload) + MCI_GPM_COEX_B_BT_BITMAP) = query_type;
+                /*
+                 * If bt_status_query message is  not sent successfully,
+                 * then need_flush_btinfo should be set again.
+                 */
+                if (!ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
+                                             wait_done, true)) {
+                        if (query_btinfo) {
+                                mci->need_flush_btinfo = true;
+
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI send bt_status_query fail, "
+                                        "set flush flag again\n");
+                        }
+                }
+
+                if (query_btinfo)
+                        mci->query_bt = false;
+        }
+}
+
+void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt,
+                                      bool wait_done)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 payload[4] = {0, 0, 0, 0};
+
+        ath_dbg(common, ATH_DBG_MCI, "MCI Send Coex %s BT GPM.\n",
+                (halt) ? "halt" : "unhalt");
+
+        MCI_GPM_SET_TYPE_OPCODE(payload,
+                                MCI_GPM_COEX_AGENT, MCI_GPM_COEX_HALT_BT_GPM);
+
+        if (halt) {
+                mci->query_bt = true;
+                /* Send next unhalt no matter halt sent or not */
+                mci->unhalt_bt_gpm = true;
+                mci->need_flush_btinfo = true;
+                *(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) =
+                        MCI_GPM_COEX_BT_GPM_HALT;
+        } else
+                *(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) =
+                        MCI_GPM_COEX_BT_GPM_UNHALT;
+
+        ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
+}
+
+
+static void ar9003_mci_prep_interface(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 saved_mci_int_en;
+        u32 mci_timeout = 150;
+
+        mci->bt_state = MCI_BT_SLEEP;
+        saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
+
+        REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
+        REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
+                  REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
+        REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
+                  REG_READ(ah, AR_MCI_INTERRUPT_RAW));
+
+        /* Remote Reset */
+        ath_dbg(common, ATH_DBG_MCI, "MCI Reset sequence start\n");
+        ath_dbg(common, ATH_DBG_MCI, "MCI send REMOTE_RESET\n");
+        ar9003_mci_remote_reset(ah, true);
+
+        /*
+         * This delay is required for the reset delay worst case value 255 in
+         * MCI_COMMAND2 register
+         */
+
+        if (AR_SREV_9462_10(ah))
+                udelay(252);
+
+        ath_dbg(common, ATH_DBG_MCI, "MCI Send REQ_WAKE to remoter(BT)\n");
+        ar9003_mci_send_req_wake(ah, true);
+
+        if (ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
+                                AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING, 500)) {
+
+                ath_dbg(common, ATH_DBG_MCI,
+                                "MCI SYS_WAKING from remote(BT)\n");
+                mci->bt_state = MCI_BT_AWAKE;
+
+                if (AR_SREV_9462_10(ah))
+                        udelay(10);
+                /*
+                 * we don't need to send more remote_reset at this moment.
+                 * If BT receive first remote_reset, then BT HW will
+                 * be cleaned up and will be able to receive req_wake
+                 * and BT HW will respond sys_waking.
+                 * In this case, WLAN will receive BT's HW sys_waking.
+                 * Otherwise, if BT SW missed initial remote_reset,
+                 * that remote_reset will still clean up BT MCI RX,
+                 * and the req_wake will wake BT up,
+                 * and BT SW will respond this req_wake with a remote_reset and
+                 * sys_waking. In this case, WLAN will receive BT's SW
+                 * sys_waking. In either case, BT's RX is cleaned up. So we
+                 * don't need to reply BT's remote_reset now, if any.
+                 * Similarly, if in any case, WLAN can receive BT's sys_waking,
+                 * that means WLAN's RX is also fine.
+                 */
+
+                /* Send SYS_WAKING to BT */
+
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI send SW SYS_WAKING to remote BT\n");
+
+                ar9003_mci_send_sys_waking(ah, true);
+                udelay(10);
+
+                /*
+                 * Set BT priority interrupt value to be 0xff to
+                 * avoid having too many BT PRIORITY interrupts.
+                 */
+
+                REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF);
+                REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF);
+                REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF);
+                REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF);
+                REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF);
+
+                /*
+                 * A contention reset will be received after send out
+                 * sys_waking. Also BT priority interrupt bits will be set.
+                 * Clear those bits before the next step.
+                 */
+
+                REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
+                          AR_MCI_INTERRUPT_RX_MSG_CONT_RST);
+                REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
+                          AR_MCI_INTERRUPT_BT_PRI);
+
+                if (AR_SREV_9462_10(ah) || mci->is_2g) {
+                        /* Send LNA_TRANS */
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI send LNA_TRANS to BT\n");
+                        ar9003_mci_send_lna_transfer(ah, true);
+                        udelay(5);
+                }
+
+                if (AR_SREV_9462_10(ah) || (mci->is_2g &&
+                                            !mci->update_2g5g)) {
+                        if (ar9003_mci_wait_for_interrupt(ah,
+                                AR_MCI_INTERRUPT_RX_MSG_RAW,
+                                AR_MCI_INTERRUPT_RX_MSG_LNA_INFO,
+                                mci_timeout))
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI WLAN has control over the LNA & "
+                                        "BT obeys it\n");
+                        else
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI BT didn't respond to"
+                                        "LNA_TRANS\n");
+                }
+
+                if (AR_SREV_9462_10(ah)) {
+                        /* Send another remote_reset to deassert BT clk_req. */
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI another remote_reset to "
+                                "deassert clk_req\n");
+                        ar9003_mci_remote_reset(ah, true);
+                        udelay(252);
+                }
+        }
+
+        /* Clear the extra redundant SYS_WAKING from BT */
+        if ((mci->bt_state == MCI_BT_AWAKE) &&
+                (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
+                                AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING)) &&
+                (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
+                                AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) == 0)) {
+
+                        REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
+                                  AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING);
+                        REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
+                                  AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE);
+        }
+
+        REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
+}
+
+void ar9003_mci_disable_interrupt(struct ath_hw *ah)
+{
+        REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
+        REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
+}
+
+void ar9003_mci_enable_interrupt(struct ath_hw *ah)
+{
+
+        REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT);
+        REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
+                  AR_MCI_INTERRUPT_RX_MSG_DEFAULT);
+}
+
+bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints)
+{
+        u32 intr;
+
+        intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
+        return ((intr & ints) == ints);
+}
+
+void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
+                              u32 *rx_msg_intr)
+{
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        *raw_intr = mci->raw_intr;
+        *rx_msg_intr = mci->rx_msg_intr;
+
+        /* Clean int bits after the values are read. */
+        mci->raw_intr = 0;
+        mci->rx_msg_intr = 0;
+}
+EXPORT_SYMBOL(ar9003_mci_get_interrupt);
+
+void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g)
+{
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+
+        if (!mci->update_2g5g &&
+            (mci->is_2g != is_2g))
+                mci->update_2g5g = true;
+
+        mci->is_2g = is_2g;
+}
+
+static bool ar9003_mci_is_gpm_valid(struct ath_hw *ah, u32 msg_index)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 *payload;
+        u32 recv_type, offset;
+
+        if (msg_index == MCI_GPM_INVALID)
+                return false;
+
+        offset = msg_index << 4;
+
+        payload = (u32 *)(mci->gpm_buf + offset);
+        recv_type = MCI_GPM_TYPE(payload);
+
+        if (recv_type == MCI_GPM_RSVD_PATTERN) {
+                ath_dbg(common, ATH_DBG_MCI, "MCI Skip RSVD GPM\n");
+                return false;
+        }
+
+        return true;
+}
+
+static void ar9003_mci_observation_set_up(struct ath_hw *ah)
+{
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        if (mci->config & ATH_MCI_CONFIG_MCI_OBS_MCI) {
+
+                ath9k_hw_cfg_output(ah, 3,
+                                        AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA);
+                ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK);
+                ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
+                ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
+
+        } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_TXRX) {
+
+                ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX);
+                ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX);
+                ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
+                ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
+                ath9k_hw_cfg_output(ah, 5, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+
+        } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_BT) {
+
+                ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
+                ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
+                ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
+                ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
+
+        } else
+                return;
+
+        REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
+
+        if (AR_SREV_9462_20_OR_LATER(ah)) {
+                REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
+                              AR_GLB_DS_JTAG_DISABLE, 1);
+                REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
+                              AR_GLB_WLAN_UART_INTF_EN, 0);
+                REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL,
+                            ATH_MCI_CONFIG_MCI_OBS_GPIO);
+        }
+
+        REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_GPIO_OBS_SEL, 0);
+        REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL, 1);
+        REG_WRITE(ah, AR_OBS, 0x4b);
+        REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL1, 0x03);
+        REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL2, 0x01);
+        REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_LSB, 0x02);
+        REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_MSB, 0x03);
+        REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS,
+                      AR_PHY_TEST_CTL_DEBUGPORT_SEL, 0x07);
+}
+
+static bool ar9003_mci_send_coex_bt_flags(struct ath_hw *ah, bool wait_done,
+                                                u8 opcode, u32 bt_flags)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        u32 pld[4] = {0, 0, 0, 0};
+
+        MCI_GPM_SET_TYPE_OPCODE(pld,
+                        MCI_GPM_COEX_AGENT, MCI_GPM_COEX_BT_UPDATE_FLAGS);
+
+        *(((u8 *)pld) + MCI_GPM_COEX_B_BT_FLAGS_OP)  = opcode;
+        *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 0) = bt_flags & 0xFF;
+        *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 1) = (bt_flags >> 8) & 0xFF;
+        *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 2) = (bt_flags >> 16) & 0xFF;
+        *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 3) = (bt_flags >> 24) & 0xFF;
+
+        ath_dbg(common, ATH_DBG_MCI,
+                "MCI BT_MCI_FLAGS: Send Coex BT Update Flags %s 0x%08x\n",
+                (opcode == MCI_GPM_COEX_BT_FLAGS_READ) ? "READ" :
+                ((opcode == MCI_GPM_COEX_BT_FLAGS_SET) ? "SET" : "CLEAR"),
+                                                                bt_flags);
+
+        return ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16,
+                                                        wait_done, true);
+}
+
+void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
+                      bool is_full_sleep)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 regval, thresh;
+
+        ath_dbg(common, ATH_DBG_MCI, "MCI full_sleep = %d, is_2g = %d\n",
+                is_full_sleep, is_2g);
+
+        /*
+         * GPM buffer and scheduling message buffer are not allocated
+         */
+
+        if (!mci->gpm_addr && !mci->sched_addr) {
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI GPM and schedule buffers are not allocated");
+                return;
+        }
+
+        if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) {
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI it's deadbeef, quit mci_reset\n");
+                return;
+        }
+
+        /* Program MCI DMA related registers */
+        REG_WRITE(ah, AR_MCI_GPM_0, mci->gpm_addr);
+        REG_WRITE(ah, AR_MCI_GPM_1, mci->gpm_len);
+        REG_WRITE(ah, AR_MCI_SCHD_TABLE_0, mci->sched_addr);
+
+        /*
+        * To avoid MCI state machine be affected by incoming remote MCI msgs,
+        * MCI mode will be enabled later, right before reset the MCI TX and RX.
+        */
+
+        regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |
+                 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) |
+                 SM(1, AR_BTCOEX_CTRL_PA_SHARED) |
+                 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) |
+                 SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
+                 SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK) |
+                 SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) |
+                 SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) |
+                 SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
+
+        if (is_2g && (AR_SREV_9462_20(ah)) &&
+                !(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) {
+
+                regval |= SM(1, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
+                ath_dbg(common, ATH_DBG_MCI,
+                                "MCI sched one step look ahead\n");
+
+                if (!(mci->config &
+                      ATH_MCI_CONFIG_DISABLE_AGGR_THRESH)) {
+
+                        thresh = MS(mci->config,
+                                    ATH_MCI_CONFIG_AGGR_THRESH);
+                        thresh &= 7;
+                        regval |= SM(1,
+                                     AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN);
+                        regval |= SM(thresh, AR_BTCOEX_CTRL_AGGR_THRESH);
+
+                        REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
+                                      AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
+                        REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
+                                      AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
+
+                } else
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI sched aggr thresh: off\n");
+        } else
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI SCHED one step look ahead off\n");
+
+        if (AR_SREV_9462_10(ah))
+                regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10);
+
+        REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
+
+        if (AR_SREV_9462_20(ah)) {
+                REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
+                            AR_BTCOEX_CTRL_SPDT_ENABLE);
+                REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3,
+                              AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT, 20);
+        }
+
+        REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 1);
+        REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
+
+        thresh = MS(mci->config, ATH_MCI_CONFIG_CLK_DIV);
+        REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, thresh);
+        REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
+
+        /* Resetting the Rx and Tx paths of MCI */
+        regval = REG_READ(ah, AR_MCI_COMMAND2);
+        regval |= SM(1, AR_MCI_COMMAND2_RESET_TX);
+        REG_WRITE(ah, AR_MCI_COMMAND2, regval);
+
+        udelay(1);
+
+        regval &= ~SM(1, AR_MCI_COMMAND2_RESET_TX);
+        REG_WRITE(ah, AR_MCI_COMMAND2, regval);
+
+        if (is_full_sleep) {
+                ar9003_mci_mute_bt(ah);
+                udelay(100);
+        }
+
+        regval |= SM(1, AR_MCI_COMMAND2_RESET_RX);
+        REG_WRITE(ah, AR_MCI_COMMAND2, regval);
+        udelay(1);
+        regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX);
+        REG_WRITE(ah, AR_MCI_COMMAND2, regval);
+
+        ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL);
+        REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE,
+                  (SM(0xe801, AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR) |
+                   SM(0x0000, AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM)));
+
+        REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
+                        AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
+
+        if (AR_SREV_9462_20_OR_LATER(ah))
+                ar9003_mci_observation_set_up(ah);
+
+        mci->ready = true;
+        ar9003_mci_prep_interface(ah);
+
+        if (en_int)
+                ar9003_mci_enable_interrupt(ah);
+}
+
+void ar9003_mci_mute_bt(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        /* disable all MCI messages */
+        REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000);
+        REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff);
+        REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff);
+        REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff);
+        REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff);
+        REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
+
+        /* wait pending HW messages to flush out */
+        udelay(10);
+
+        /*
+         * Send LNA_TAKE and SYS_SLEEPING when
+         * 1. reset not after resuming from full sleep
+         * 2. before reset MCI RX, to quiet BT and avoid MCI RX misalignment
+         */
+
+        ath_dbg(common, ATH_DBG_MCI, "MCI Send LNA take\n");
+        ar9003_mci_send_lna_take(ah, true);
+
+        udelay(5);
+
+        ath_dbg(common, ATH_DBG_MCI, "MCI Send sys sleeping\n");
+        ar9003_mci_send_sys_sleeping(ah, true);
+}
+
+void ar9003_mci_sync_bt_state(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 cur_bt_state;
+
+        cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL);
+
+        if (mci->bt_state != cur_bt_state) {
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI BT state mismatches. old: %d, new: %d\n",
+                        mci->bt_state, cur_bt_state);
+                mci->bt_state = cur_bt_state;
+        }
+
+        if (mci->bt_state != MCI_BT_SLEEP) {
+
+                ar9003_mci_send_coex_version_query(ah, true);
+                ar9003_mci_send_coex_wlan_channels(ah, true);
+
+                if (mci->unhalt_bt_gpm == true) {
+                        ath_dbg(common, ATH_DBG_MCI, "MCI unhalt BT GPM");
+                        ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
+                }
+        }
+}
+
+static void ar9003_mci_send_2g5g_status(struct ath_hw *ah, bool wait_done)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 new_flags, to_set, to_clear;
+
+        if (AR_SREV_9462_20(ah) &&
+            mci->update_2g5g &&
+            (mci->bt_state != MCI_BT_SLEEP)) {
+
+                if (mci->is_2g) {
+                        new_flags = MCI_2G_FLAGS;
+                        to_clear = MCI_2G_FLAGS_CLEAR_MASK;
+                        to_set = MCI_2G_FLAGS_SET_MASK;
+                } else {
+                        new_flags = MCI_5G_FLAGS;
+                        to_clear = MCI_5G_FLAGS_CLEAR_MASK;
+                        to_set = MCI_5G_FLAGS_SET_MASK;
+                }
+
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI BT_MCI_FLAGS: %s 0x%08x clr=0x%08x, set=0x%08x\n",
+                mci->is_2g ? "2G" : "5G", new_flags, to_clear, to_set);
+
+                if (to_clear)
+                        ar9003_mci_send_coex_bt_flags(ah, wait_done,
+                                        MCI_GPM_COEX_BT_FLAGS_CLEAR, to_clear);
+
+                if (to_set)
+                        ar9003_mci_send_coex_bt_flags(ah, wait_done,
+                                        MCI_GPM_COEX_BT_FLAGS_SET, to_set);
+        }
+
+        if (AR_SREV_9462_10(ah) && (mci->bt_state != MCI_BT_SLEEP))
+                mci->update_2g5g = false;
+}
+
+static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header,
+                                        u32 *payload, bool queue)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u8 type, opcode;
+
+        if (queue) {
+
+                if (payload)
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI ERROR: Send fail: %02x: %02x %02x %02x\n",
+                                header,
+                                *(((u8 *)payload) + 4),
+                                *(((u8 *)payload) + 5),
+                                *(((u8 *)payload) + 6));
+                else
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI ERROR: Send fail: %02x\n", header);
+        }
+
+        /* check if the message is to be queued */
+        if (header != MCI_GPM)
+                return;
+
+        type = MCI_GPM_TYPE(payload);
+        opcode = MCI_GPM_OPCODE(payload);
+
+        if (type != MCI_GPM_COEX_AGENT)
+                return;
+
+        switch (opcode) {
+        case MCI_GPM_COEX_BT_UPDATE_FLAGS:
+
+                if (AR_SREV_9462_10(ah))
+                        break;
+
+                if (*(((u8 *)payload) + MCI_GPM_COEX_B_BT_FLAGS_OP) ==
+                                MCI_GPM_COEX_BT_FLAGS_READ)
+                        break;
+
+                mci->update_2g5g = queue;
+
+                if (queue)
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI BT_MCI_FLAGS: 2G5G status <queued> %s.\n",
+                                mci->is_2g ? "2G" : "5G");
+                else
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI BT_MCI_FLAGS: 2G5G status <sent> %s.\n",
+                                mci->is_2g ? "2G" : "5G");
+
+                break;
+
+        case MCI_GPM_COEX_WLAN_CHANNELS:
+
+                mci->wlan_channels_update = queue;
+                if (queue)
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI WLAN channel map <queued>\n");
+                else
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI WLAN channel map <sent>\n");
+                break;
+
+        case MCI_GPM_COEX_HALT_BT_GPM:
+
+                if (*(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) ==
+                                MCI_GPM_COEX_BT_GPM_UNHALT) {
+
+                        mci->unhalt_bt_gpm = queue;
+
+                        if (queue)
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI UNHALT BT GPM <queued>\n");
+                        else {
+                                mci->halted_bt_gpm = false;
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI UNHALT BT GPM <sent>\n");
+                        }
+                }
+
+                if (*(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) ==
+                                MCI_GPM_COEX_BT_GPM_HALT) {
+
+                        mci->halted_bt_gpm = !queue;
+
+                        if (queue)
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI HALT BT GPM <not sent>\n");
+                        else
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI UNHALT BT GPM <sent>\n");
+                }
+
+                break;
+        default:
+                break;
+        }
+}
+
+void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+
+        if (mci->update_2g5g) {
+                if (mci->is_2g) {
+
+                        ar9003_mci_send_2g5g_status(ah, true);
+                        ath_dbg(common, ATH_DBG_MCI, "MCI Send LNA trans\n");
+                        ar9003_mci_send_lna_transfer(ah, true);
+                        udelay(5);
+
+                        REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
+                                    AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
+
+                        if (AR_SREV_9462_20(ah)) {
+                                REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL,
+                                            AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
+                                if (!(mci->config &
+                                      ATH_MCI_CONFIG_DISABLE_OSLA)) {
+                                        REG_SET_BIT(ah, AR_BTCOEX_CTRL,
+                                        AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
+                                }
+                        }
+                } else {
+                        ath_dbg(common, ATH_DBG_MCI, "MCI Send LNA take\n");
+                        ar9003_mci_send_lna_take(ah, true);
+                        udelay(5);
+
+                        REG_SET_BIT(ah, AR_MCI_TX_CTRL,
+                                    AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
+
+                        if (AR_SREV_9462_20(ah)) {
+                                REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
+                                            AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
+                                REG_CLR_BIT(ah, AR_BTCOEX_CTRL,
+                                        AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
+                        }
+
+                        ar9003_mci_send_2g5g_status(ah, true);
+                }
+        }
+}
+
+bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
+                             u32 *payload, u8 len, bool wait_done,
+                             bool check_bt)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        bool msg_sent = false;
+        u32 regval;
+        u32 saved_mci_int_en;
+        int i;
+
+        saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
+        regval = REG_READ(ah, AR_BTCOEX_CTRL);
+
+        if ((regval == 0xdeadbeef) || !(regval & AR_BTCOEX_CTRL_MCI_MODE_EN)) {
+
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Not sending 0x%x. MCI is not enabled. "
+                        "full_sleep = %d\n", header,
+                        (ah->power_mode == ATH9K_PM_FULL_SLEEP) ? 1 : 0);
+
+                ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
+                return false;
+
+        } else if (check_bt && (mci->bt_state == MCI_BT_SLEEP)) {
+
+                ath_dbg(common, ATH_DBG_MCI,
+                "MCI Don't send message 0x%x. BT is in sleep state\n", header);
+
+                ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
+                return false;
+        }
+
+        if (wait_done)
+                REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
+
+        /* Need to clear SW_MSG_DONE raw bit before wait */
+
+        REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
+                  (AR_MCI_INTERRUPT_SW_MSG_DONE |
+                   AR_MCI_INTERRUPT_MSG_FAIL_MASK));
+
+        if (payload) {
+                for (i = 0; (i * 4) < len; i++)
+                        REG_WRITE(ah, (AR_MCI_TX_PAYLOAD0 + i * 4),
+                                  *(payload + i));
+        }
+
+        REG_WRITE(ah, AR_MCI_COMMAND0,
+                  (SM((flag & MCI_FLAG_DISABLE_TIMESTAMP),
+                      AR_MCI_COMMAND0_DISABLE_TIMESTAMP) |
+                   SM(len, AR_MCI_COMMAND0_LEN) |
+                   SM(header, AR_MCI_COMMAND0_HEADER)));
+
+        if (wait_done &&
+            !(ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RAW,
+                                        AR_MCI_INTERRUPT_SW_MSG_DONE, 500)))
+                ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
+        else {
+                ar9003_mci_queue_unsent_gpm(ah, header, payload, false);
+                msg_sent = true;
+        }
+
+        if (wait_done)
+                REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
+
+        return msg_sent;
+}
+EXPORT_SYMBOL(ar9003_mci_send_message);
+
+void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
+                      u16 len, u32 sched_addr)
+{
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        void *sched_buf = (void *)((char *) gpm_buf + (sched_addr - gpm_addr));
+
+        mci->gpm_addr = gpm_addr;
+        mci->gpm_buf = gpm_buf;
+        mci->gpm_len = len;
+        mci->sched_addr = sched_addr;
+        mci->sched_buf = sched_buf;
+
+        ar9003_mci_reset(ah, true, true, true);
+}
+EXPORT_SYMBOL(ar9003_mci_setup);
+
+void ar9003_mci_cleanup(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        /* Turn off MCI and Jupiter mode. */
+        REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00);
+        ath_dbg(common, ATH_DBG_MCI, "MCI ar9003_mci_cleanup\n");
+        ar9003_mci_disable_interrupt(ah);
+}
+EXPORT_SYMBOL(ar9003_mci_cleanup);
+
+static void ar9003_mci_process_gpm_extra(struct ath_hw *ah, u8 gpm_type,
+                                         u8 gpm_opcode, u32 *p_gpm)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u8 *p_data = (u8 *) p_gpm;
+
+        if (gpm_type != MCI_GPM_COEX_AGENT)
+                return;
+
+        switch (gpm_opcode) {
+        case MCI_GPM_COEX_VERSION_QUERY:
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Recv GPM COEX Version Query\n");
+                ar9003_mci_send_coex_version_response(ah, true);
+                break;
+        case MCI_GPM_COEX_VERSION_RESPONSE:
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Recv GPM COEX Version Response\n");
+                mci->bt_ver_major =
+                        *(p_data + MCI_GPM_COEX_B_MAJOR_VERSION);
+                mci->bt_ver_minor =
+                        *(p_data + MCI_GPM_COEX_B_MINOR_VERSION);
+                mci->bt_version_known = true;
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI BT Coex version: %d.%d\n",
+                        mci->bt_ver_major,
+                        mci->bt_ver_minor);
+                break;
+        case MCI_GPM_COEX_STATUS_QUERY:
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Recv GPM COEX Status Query = 0x%02X.\n",
+                        *(p_data + MCI_GPM_COEX_B_WLAN_BITMAP));
+                mci->wlan_channels_update = true;
+                ar9003_mci_send_coex_wlan_channels(ah, true);
+                break;
+        case MCI_GPM_COEX_BT_PROFILE_INFO:
+                mci->query_bt = true;
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Recv GPM COEX BT_Profile_Info\n");
+                break;
+        case MCI_GPM_COEX_BT_STATUS_UPDATE:
+                mci->query_bt = true;
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Recv GPM COEX BT_Status_Update "
+                        "SEQ=%d (drop&query)\n", *(p_gpm + 3));
+                break;
+        default:
+                break;
+        }
+}
+
+u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
+                            u8 gpm_opcode, int time_out)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 *p_gpm = NULL, mismatch = 0, more_data;
+        u32 offset;
+        u8 recv_type = 0, recv_opcode = 0;
+        bool b_is_bt_cal_done = (gpm_type == MCI_GPM_BT_CAL_DONE);
+
+        more_data = time_out ? MCI_GPM_NOMORE : MCI_GPM_MORE;
+
+        while (time_out > 0) {
+                if (p_gpm) {
+                        MCI_GPM_RECYCLE(p_gpm);
+                        p_gpm = NULL;
+                }
+
+                if (more_data != MCI_GPM_MORE)
+                        time_out = ar9003_mci_wait_for_interrupt(ah,
+                                        AR_MCI_INTERRUPT_RX_MSG_RAW,
+                                        AR_MCI_INTERRUPT_RX_MSG_GPM,
+                                        time_out);
+
+                if (!time_out)
+                        break;
+
+                offset = ar9003_mci_state(ah,
+                                MCI_STATE_NEXT_GPM_OFFSET, &more_data);
+
+                if (offset == MCI_GPM_INVALID)
+                        continue;
+
+                p_gpm = (u32 *) (mci->gpm_buf + offset);
+                recv_type = MCI_GPM_TYPE(p_gpm);
+                recv_opcode = MCI_GPM_OPCODE(p_gpm);
+
+                if (MCI_GPM_IS_CAL_TYPE(recv_type)) {
+
+                        if (recv_type == gpm_type) {
+
+                                if ((gpm_type == MCI_GPM_BT_CAL_DONE) &&
+                                    !b_is_bt_cal_done) {
+                                        gpm_type = MCI_GPM_BT_CAL_GRANT;
+                                        ath_dbg(common, ATH_DBG_MCI,
+                                                "MCI Recv BT_CAL_DONE"
+                                                "wait BT_CAL_GRANT\n");
+                                        continue;
+                                }
+
+                                break;
+                        }
+                } else if ((recv_type == gpm_type) &&
+                           (recv_opcode == gpm_opcode))
+                        break;
+
+                /* not expected message */
+
+                /*
+                 * check if it's cal_grant
+                 *
+                 * When we're waiting for cal_grant in reset routine,
+                 * it's possible that BT sends out cal_request at the
+                 * same time. Since BT's calibration doesn't happen
+                 * that often, we'll let BT completes calibration then
+                 * we continue to wait for cal_grant from BT.
+                 * Orginal: Wait BT_CAL_GRANT.
+                 * New: Receive BT_CAL_REQ -> send WLAN_CAL_GRANT->wait
+                 * BT_CAL_DONE -> Wait BT_CAL_GRANT.
+                 */
+
+                if ((gpm_type == MCI_GPM_BT_CAL_GRANT) &&
+                    (recv_type == MCI_GPM_BT_CAL_REQ)) {
+
+                        u32 payload[4] = {0, 0, 0, 0};
+
+                        gpm_type = MCI_GPM_BT_CAL_DONE;
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI Rcv BT_CAL_REQ, send WLAN_CAL_GRANT\n");
+
+                        MCI_GPM_SET_CAL_TYPE(payload,
+                                        MCI_GPM_WLAN_CAL_GRANT);
+
+                        ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
+                                                false, false);
+
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI now wait for BT_CAL_DONE\n");
+
+                        continue;
+                } else {
+                        ath_dbg(common, ATH_DBG_MCI, "MCI GPM subtype"
+                                        "not match 0x%x\n", *(p_gpm + 1));
+                        mismatch++;
+                        ar9003_mci_process_gpm_extra(ah, recv_type,
+                                        recv_opcode, p_gpm);
+                }
+        }
+        if (p_gpm) {
+                MCI_GPM_RECYCLE(p_gpm);
+                p_gpm = NULL;
+        }
+
+        if (time_out <= 0) {
+                time_out = 0;
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI GPM received timeout, mismatch = %d\n", mismatch);
+        } else
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Receive GPM type=0x%x, code=0x%x\n",
+                        gpm_type, gpm_opcode);
+
+        while (more_data == MCI_GPM_MORE) {
+
+                ath_dbg(common, ATH_DBG_MCI, "MCI discard remaining GPM\n");
+                offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET,
+                                          &more_data);
+
+                if (offset == MCI_GPM_INVALID)
+                        break;
+
+                p_gpm = (u32 *) (mci->gpm_buf + offset);
+                recv_type = MCI_GPM_TYPE(p_gpm);
+                recv_opcode = MCI_GPM_OPCODE(p_gpm);
+
+                if (!MCI_GPM_IS_CAL_TYPE(recv_type))
+                        ar9003_mci_process_gpm_extra(ah, recv_type,
+                                                     recv_opcode, p_gpm);
+
+                MCI_GPM_RECYCLE(p_gpm);
+        }
+
+        return time_out;
+}
+
+u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
+        u32 value = 0, more_gpm = 0, gpm_ptr;
+        u8 query_type;
+
+        switch (state_type) {
+        case MCI_STATE_ENABLE:
+                if (mci->ready) {
+
+                        value = REG_READ(ah, AR_BTCOEX_CTRL);
+
+                        if ((value == 0xdeadbeef) || (value == 0xffffffff))
+                                value = 0;
+                }
+                value &= AR_BTCOEX_CTRL_MCI_MODE_EN;
+                break;
+        case MCI_STATE_INIT_GPM_OFFSET:
+                value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI GPM initial WRITE_PTR=%d\n", value);
+                mci->gpm_idx = value;
+                break;
+        case MCI_STATE_NEXT_GPM_OFFSET:
+        case MCI_STATE_LAST_GPM_OFFSET:
+                /*
+                * This could be useful to avoid new GPM message interrupt which
+                * may lead to spurious interrupt after power sleep, or multiple
+                * entry of ath_mci_intr().
+                * Adding empty GPM check by returning HAL_MCI_GPM_INVALID can
+                * alleviate this effect, but clearing GPM RX interrupt bit is
+                * safe, because whether this is called from hw or driver code
+                * there must be an interrupt bit set/triggered initially
+                */
+                REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
+                          AR_MCI_INTERRUPT_RX_MSG_GPM);
+
+                gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
+                value = gpm_ptr;
+
+                if (value == 0)
+                        value = mci->gpm_len - 1;
+                else if (value >= mci->gpm_len) {
+                        if (value != 0xFFFF) {
+                                value = 0;
+                                ath_dbg(common, ATH_DBG_MCI, "MCI GPM offset"
+                                        "out of range\n");
+                        }
+                } else
+                        value--;
+
+                if (value == 0xFFFF) {
+                        value = MCI_GPM_INVALID;
+                        more_gpm = MCI_GPM_NOMORE;
+                        ath_dbg(common, ATH_DBG_MCI, "MCI GPM ptr invalid"
+                                "@ptr=%d, offset=%d, more=GPM_NOMORE\n",
+                                gpm_ptr, value);
+                } else if (state_type == MCI_STATE_NEXT_GPM_OFFSET) {
+
+                        if (gpm_ptr == mci->gpm_idx) {
+                                value = MCI_GPM_INVALID;
+                                more_gpm = MCI_GPM_NOMORE;
+
+                                ath_dbg(common, ATH_DBG_MCI, "MCI GPM message"
+                                        "not available @ptr=%d, @offset=%d,"
+                                        "more=GPM_NOMORE\n", gpm_ptr, value);
+                        } else {
+                                for (;;) {
+
+                                        u32 temp_index;
+
+                                        /* skip reserved GPM if any */
+
+                                        if (value != mci->gpm_idx)
+                                                more_gpm = MCI_GPM_MORE;
+                                        else
+                                                more_gpm = MCI_GPM_NOMORE;
+
+                                        temp_index = mci->gpm_idx;
+                                        mci->gpm_idx++;
+
+                                        if (mci->gpm_idx >=
+                                            mci->gpm_len)
+                                                mci->gpm_idx = 0;
+
+                                        ath_dbg(common, ATH_DBG_MCI,
+                                                "MCI GPM message got ptr=%d,"
+                                                "@offset=%d, more=%d\n",
+                                                gpm_ptr, temp_index,
+                                                (more_gpm == MCI_GPM_MORE));
+
+                                        if (ar9003_mci_is_gpm_valid(ah,
+                                                                temp_index)) {
+                                                value = temp_index;
+                                                break;
+                                        }
+
+                                        if (more_gpm == MCI_GPM_NOMORE) {
+                                                value = MCI_GPM_INVALID;
+                                                break;
+                                        }
+                                }
+                        }
+                        if (p_data)
+                                *p_data = more_gpm;
+                        }
+
+                        if (value != MCI_GPM_INVALID)
+                                value <<= 4;
+
+                        break;
+        case MCI_STATE_LAST_SCHD_MSG_OFFSET:
+                value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
+                                    AR_MCI_RX_LAST_SCHD_MSG_INDEX);
+                /* Make it in bytes */
+                value <<= 4;
+                break;
+
+        case MCI_STATE_REMOTE_SLEEP:
+                value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
+                           AR_MCI_RX_REMOTE_SLEEP) ?
+                        MCI_BT_SLEEP : MCI_BT_AWAKE;
+                break;
+
+        case MCI_STATE_CONT_RSSI_POWER:
+                value = MS(mci->cont_status, AR_MCI_CONT_RSSI_POWER);
+                        break;
+
+        case MCI_STATE_CONT_PRIORITY:
+                value = MS(mci->cont_status, AR_MCI_CONT_RRIORITY);
+                break;
+
+        case MCI_STATE_CONT_TXRX:
+                value = MS(mci->cont_status, AR_MCI_CONT_TXRX);
+                break;
+
+        case MCI_STATE_BT:
+                value = mci->bt_state;
+                break;
+
+        case MCI_STATE_SET_BT_SLEEP:
+                mci->bt_state = MCI_BT_SLEEP;
+                break;
+
+        case MCI_STATE_SET_BT_AWAKE:
+                mci->bt_state = MCI_BT_AWAKE;
+                ar9003_mci_send_coex_version_query(ah, true);
+                ar9003_mci_send_coex_wlan_channels(ah, true);
+
+                if (mci->unhalt_bt_gpm) {
+
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI unhalt BT GPM\n");
+                        ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
+                }
+
+                ar9003_mci_2g5g_switch(ah, true);
+                break;
+
+        case MCI_STATE_SET_BT_CAL_START:
+                mci->bt_state = MCI_BT_CAL_START;
+                break;
+
+        case MCI_STATE_SET_BT_CAL:
+                mci->bt_state = MCI_BT_CAL;
+                break;
+
+        case MCI_STATE_RESET_REQ_WAKE:
+                ar9003_mci_reset_req_wakeup(ah);
+                mci->update_2g5g = true;
+
+                if ((AR_SREV_9462_20_OR_LATER(ah)) &&
+                    (mci->config & ATH_MCI_CONFIG_MCI_OBS_MASK)) {
+                        /* Check if we still have control of the GPIOs */
+                        if ((REG_READ(ah, AR_GLB_GPIO_CONTROL) &
+                                      ATH_MCI_CONFIG_MCI_OBS_GPIO) !=
+                                        ATH_MCI_CONFIG_MCI_OBS_GPIO) {
+
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI reconfigure observation");
+                                ar9003_mci_observation_set_up(ah);
+                        }
+                }
+                break;
+
+        case MCI_STATE_SEND_WLAN_COEX_VERSION:
+                ar9003_mci_send_coex_version_response(ah, true);
+                break;
+
+        case MCI_STATE_SET_BT_COEX_VERSION:
+
+                if (!p_data)
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI Set BT Coex version with NULL data!!\n");
+                else {
+                        mci->bt_ver_major = (*p_data >> 8) & 0xff;
+                        mci->bt_ver_minor = (*p_data) & 0xff;
+                        mci->bt_version_known = true;
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI BT version set: %d.%d\n",
+                                mci->bt_ver_major,
+                                mci->bt_ver_minor);
+                }
+                break;
+
+        case MCI_STATE_SEND_WLAN_CHANNELS:
+                if (p_data) {
+                        if (((mci->wlan_channels[1] & 0xffff0000) ==
+                             (*(p_data + 1) & 0xffff0000)) &&
+                            (mci->wlan_channels[2] == *(p_data + 2)) &&
+                            (mci->wlan_channels[3] == *(p_data + 3)))
+                                break;
+
+                        mci->wlan_channels[0] = *p_data++;
+                        mci->wlan_channels[1] = *p_data++;
+                        mci->wlan_channels[2] = *p_data++;
+                        mci->wlan_channels[3] = *p_data++;
+                }
+                mci->wlan_channels_update = true;
+                ar9003_mci_send_coex_wlan_channels(ah, true);
+                break;
+
+        case MCI_STATE_SEND_VERSION_QUERY:
+                ar9003_mci_send_coex_version_query(ah, true);
+                break;
+
+        case MCI_STATE_SEND_STATUS_QUERY:
+                query_type = (AR_SREV_9462_10(ah)) ?
+                                MCI_GPM_COEX_QUERY_BT_ALL_INFO :
+                                MCI_GPM_COEX_QUERY_BT_TOPOLOGY;
+
+                ar9003_mci_send_coex_bt_status_query(ah, true, query_type);
+                break;
+
+        case MCI_STATE_NEED_FLUSH_BT_INFO:
+                        /*
+                         * btcoex_hw.mci.unhalt_bt_gpm means whether it's
+                         * needed to send UNHALT message. It's set whenever
+                         * there's a request to send HALT message.
+                         * mci_halted_bt_gpm means whether HALT message is sent
+                         * out successfully.
+                         *
+                         * Checking (mci_unhalt_bt_gpm == false) instead of
+                         * checking (ah->mci_halted_bt_gpm == false) will make
+                         * sure currently is in UNHALT-ed mode and BT can
+                         * respond to status query.
+                         */
+                        value = (!mci->unhalt_bt_gpm &&
+                                 mci->need_flush_btinfo) ? 1 : 0;
+                        if (p_data)
+                                mci->need_flush_btinfo =
+                                        (*p_data != 0) ? true : false;
+                        break;
+
+        case MCI_STATE_RECOVER_RX:
+
+                ath_dbg(common, ATH_DBG_MCI, "MCI hw RECOVER_RX\n");
+                ar9003_mci_prep_interface(ah);
+                mci->query_bt = true;
+                mci->need_flush_btinfo = true;
+                ar9003_mci_send_coex_wlan_channels(ah, true);
+                ar9003_mci_2g5g_switch(ah, true);
+                break;
+
+        case MCI_STATE_NEED_FTP_STOMP:
+                value = !(mci->config & ATH_MCI_CONFIG_DISABLE_FTP_STOMP);
+                break;
+
+        case MCI_STATE_NEED_TUNING:
+                value = !(mci->config & ATH_MCI_CONFIG_DISABLE_TUNING);
+                break;
+
+        default:
+                break;
+
+        }
+
+        return value;
+}
+EXPORT_SYMBOL(ar9003_mci_state);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mci.h b/drivers/net/wireless/ath/ath9k/ar9003_mci.h
new file mode 100644
index 000000000000..798da116a44c
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mci.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef AR9003_MCI_H
+#define AR9003_MCI_H
+
+#define MCI_FLAG_DISABLE_TIMESTAMP      0x00000001      /* Disable time stamp */
+
+/* Default remote BT device MCI COEX version */
+#define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT  3
+#define MCI_GPM_COEX_MINOR_VERSION_DEFAULT  0
+
+/* Local WLAN MCI COEX version */
+#define MCI_GPM_COEX_MAJOR_VERSION_WLAN     3
+#define MCI_GPM_COEX_MINOR_VERSION_WLAN     0
+
+enum mci_gpm_coex_query_type {
+        MCI_GPM_COEX_QUERY_BT_ALL_INFO      = BIT(0),
+        MCI_GPM_COEX_QUERY_BT_TOPOLOGY      = BIT(1),
+        MCI_GPM_COEX_QUERY_BT_DEBUG         = BIT(2),
+};
+
+enum mci_gpm_coex_halt_bt_gpm {
+        MCI_GPM_COEX_BT_GPM_UNHALT,
+        MCI_GPM_COEX_BT_GPM_HALT
+};
+
+enum mci_gpm_coex_bt_update_flags_op {
+        MCI_GPM_COEX_BT_FLAGS_READ,
+        MCI_GPM_COEX_BT_FLAGS_SET,
+        MCI_GPM_COEX_BT_FLAGS_CLEAR
+};
+
+#define MCI_NUM_BT_CHANNELS     79
+
+#define MCI_BT_MCI_FLAGS_UPDATE_CORR          0x00000002
+#define MCI_BT_MCI_FLAGS_UPDATE_HDR           0x00000004
+#define MCI_BT_MCI_FLAGS_UPDATE_PLD           0x00000008
+#define MCI_BT_MCI_FLAGS_LNA_CTRL             0x00000010
+#define MCI_BT_MCI_FLAGS_DEBUG                0x00000020
+#define MCI_BT_MCI_FLAGS_SCHED_MSG            0x00000040
+#define MCI_BT_MCI_FLAGS_CONT_MSG             0x00000080
+#define MCI_BT_MCI_FLAGS_COEX_GPM             0x00000100
+#define MCI_BT_MCI_FLAGS_CPU_INT_MSG          0x00000200
+#define MCI_BT_MCI_FLAGS_MCI_MODE             0x00000400
+#define MCI_BT_MCI_FLAGS_AR9462_MODE          0x00001000
+#define MCI_BT_MCI_FLAGS_OTHER                0x00010000
+
+#define MCI_DEFAULT_BT_MCI_FLAGS              0x00011dde
+
+#define MCI_TOGGLE_BT_MCI_FLAGS  (MCI_BT_MCI_FLAGS_UPDATE_CORR | \
+                                  MCI_BT_MCI_FLAGS_UPDATE_HDR  | \
+                                  MCI_BT_MCI_FLAGS_UPDATE_PLD  | \
+                                  MCI_BT_MCI_FLAGS_MCI_MODE)
+
+#define MCI_2G_FLAGS_CLEAR_MASK   0x00000000
+#define MCI_2G_FLAGS_SET_MASK     MCI_TOGGLE_BT_MCI_FLAGS
+#define MCI_2G_FLAGS              MCI_DEFAULT_BT_MCI_FLAGS
+
+#define MCI_5G_FLAGS_CLEAR_MASK   MCI_TOGGLE_BT_MCI_FLAGS
+#define MCI_5G_FLAGS_SET_MASK     0x00000000
+#define MCI_5G_FLAGS              (MCI_DEFAULT_BT_MCI_FLAGS & \
+                                   ~MCI_TOGGLE_BT_MCI_FLAGS)
+
+/*
+ * Default value for AR9462 is 0x00002201
+ */
+#define ATH_MCI_CONFIG_CONCUR_TX            0x00000003
+#define ATH_MCI_CONFIG_MCI_OBS_MCI          0x00000004
+#define ATH_MCI_CONFIG_MCI_OBS_TXRX         0x00000008
+#define ATH_MCI_CONFIG_MCI_OBS_BT           0x00000010
+#define ATH_MCI_CONFIG_DISABLE_MCI_CAL      0x00000020
+#define ATH_MCI_CONFIG_DISABLE_OSLA         0x00000040
+#define ATH_MCI_CONFIG_DISABLE_FTP_STOMP    0x00000080
+#define ATH_MCI_CONFIG_AGGR_THRESH          0x00000700
+#define ATH_MCI_CONFIG_AGGR_THRESH_S        8
+#define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH  0x00000800
+#define ATH_MCI_CONFIG_CLK_DIV              0x00003000
+#define ATH_MCI_CONFIG_CLK_DIV_S            12
+#define ATH_MCI_CONFIG_DISABLE_TUNING       0x00004000
+#define ATH_MCI_CONFIG_MCI_WEIGHT_DBG       0x40000000
+#define ATH_MCI_CONFIG_DISABLE_MCI          0x80000000
+
+#define ATH_MCI_CONFIG_MCI_OBS_MASK     (ATH_MCI_CONFIG_MCI_OBS_MCI  | \
+                                         ATH_MCI_CONFIG_MCI_OBS_TXRX | \
+                                         ATH_MCI_CONFIG_MCI_OBS_BT)
+#define ATH_MCI_CONFIG_MCI_OBS_GPIO     0x0000002F
+
+#endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index 0c462c904cbe..a4450cba0653 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -14,6 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/export.h>
 #include "hw.h"
 #include "ar9003_phy.h"
 
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 04b060af5087..e41d26939ab8 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -14,6 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/export.h>
 #include "hw.h"
 #include "ar9003_phy.h"
 
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 497d7461838a..ed64114571fc 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -490,6 +490,8 @@
 #define AR_PHY_TEST_CTL_TSTADC_EN_S       8
 #define AR_PHY_TEST_CTL_RX_OBS_SEL        0x3C00
 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S      10
+#define AR_PHY_TEST_CTL_DEBUGPORT_SEL     0xe0000000
+#define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S   29
 
 
 #define AR_PHY_TSTDAC            (AR_SM_BASE + 0x168)
@@ -1001,6 +1003,7 @@
 
 /* GLB Registers */
 #define AR_GLB_BASE     0x20000
+#define AR_GLB_GPIO_CONTROL     (AR_GLB_BASE)
 #define AR_PHY_GLB_CONTROL      (AR_GLB_BASE + 0x44)
 #define AR_GLB_SCRATCH(_ah)     (AR_GLB_BASE + \
                                         (AR_SREV_9462_20(_ah) ? 0x4c : 0x50))
diff --git a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
index 259a6f312afb..dc2054f0378e 100644
--- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
@@ -41,24 +41,24 @@ static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
 
 static const u32 ar9462_2p0_baseband_postamble[][5] = {
         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
-        {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
-        {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
-        {0x00009824, 0x5ac640de, 0x5ac640d0, 0x5ac640d0, 0x5ac640de},
-        {0x00009828, 0x0796be89, 0x0696b081, 0x0696b881, 0x0796be89},
+        {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
+        {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a01ae},
+        {0x00009824, 0x5ac640de, 0x5ac640d0, 0x5ac640d0, 0x63c640da},
+        {0x00009828, 0x0796be89, 0x0696b081, 0x0696b881, 0x09143e81},
         {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
         {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
         {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
         {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},
         {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020},
-        {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
-        {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x92c84d2e},
-        {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e},
+        {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000d8},
+        {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec86d2e},
+        {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3376605e, 0x33795d5e},
         {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
         {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
         {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
-        {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c782},
-        {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
+        {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
+        {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27},
         {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
         {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
         {0x0000a204, 0x013187c0, 0x013187c4, 0x013187c4, 0x013187c0},
@@ -81,6 +81,15 @@ static const u32 ar9462_2p0_baseband_postamble[][5] = {
         {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
         {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
         {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a3a4, 0x00000010, 0x00000010, 0x00000000, 0x00000000},
+        {0x0000a3a8, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa},
+        {0x0000a3ac, 0xaaaaaa00, 0xaaaaaa30, 0xaaaaaa00, 0xaaaaaa00},
+        {0x0000a41c, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce},
+        {0x0000a420, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce},
+        {0x0000a424, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce},
+        {0x0000a428, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce},
+        {0x0000a42c, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce},
+        {0x0000a430, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce},
         {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
         {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x00100000},
         {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -1107,11 +1116,11 @@ static const u32 ar9462_2p0_baseband_core[][2] = {
         {0x00009e30, 0x06336f77},
         {0x00009e34, 0x6af6532f},
         {0x00009e38, 0x0cc80c00},
-        {0x00009e40, 0x0d261820},
+        {0x00009e40, 0x15262820},
         {0x00009e4c, 0x00001004},
         {0x00009e50, 0x00ff03f1},
-        {0x00009e54, 0xe4c355c7},
-        {0x00009e58, 0xfd897735},
+        {0x00009e54, 0xe4c555c2},
+        {0x00009e58, 0xfd857722},
         {0x00009e5c, 0xe9198724},
         {0x00009fc0, 0x803e4788},
         {0x00009fc4, 0x0001efb5},
@@ -1142,9 +1151,6 @@ static const u32 ar9462_2p0_baseband_core[][2] = {
         {0x0000a398, 0x001f0e0f},
         {0x0000a39c, 0x0075393f},
         {0x0000a3a0, 0xb79f6427},
-        {0x0000a3a4, 0x00000000},
-        {0x0000a3a8, 0xaaaaaaaa},
-        {0x0000a3ac, 0x3c466478},
         {0x0000a3c0, 0x20202020},
         {0x0000a3c4, 0x22222220},
         {0x0000a3c8, 0x20200020},
@@ -1167,12 +1173,6 @@ static const u32 ar9462_2p0_baseband_core[][2] = {
         {0x0000a40c, 0x00820820},
         {0x0000a414, 0x1ce739ce},
         {0x0000a418, 0x2d001dce},
-        {0x0000a41c, 0x1ce739ce},
-        {0x0000a420, 0x000001ce},
-        {0x0000a424, 0x1ce739ce},
-        {0x0000a428, 0x000001ce},
-        {0x0000a42c, 0x1ce739ce},
-        {0x0000a430, 0x1ce739ce},
         {0x0000a434, 0x00000000},
         {0x0000a438, 0x00001801},
         {0x0000a43c, 0x00100000},
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 93b45b4b3033..130e5dba9555 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -159,6 +159,9 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 /* return block-ack bitmap index given sequence and starting sequence */
 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 
+/* return the seqno for _start + _offset */
+#define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
+
 /* returns delimiter padding required given the packet length */
 #define ATH_AGGR_GET_NDELIM(_len)                                       \
        (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
@@ -238,6 +241,7 @@ struct ath_atx_tid {
         struct ath_node *an;
         struct ath_atx_ac *ac;
         unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
+        int bar_index;
         u16 seq_start;
         u16 seq_next;
         u16 baw_size;
@@ -252,9 +256,9 @@ struct ath_atx_tid {
 struct ath_node {
 #ifdef CONFIG_ATH9K_DEBUGFS
         struct list_head list; /* for sc->nodes */
+#endif
         struct ieee80211_sta *sta; /* station struct we're part of */
         struct ieee80211_vif *vif; /* interface with which we're associated */
-#endif
         struct ath_atx_tid tid[WME_NUM_TID];
         struct ath_atx_ac ac[WME_NUM_AC];
         int ps_key;
@@ -276,7 +280,6 @@ struct ath_tx_control {
 };
 
 #define ATH_TX_ERROR        0x01
-#define ATH_TX_BAR          0x02
 
 /**
  * @txq_map:  Index is mac80211 queue number.  This is
@@ -462,7 +465,7 @@ void ath9k_btcoex_timer_pause(struct ath_softc *sc);
 #define ATH_LED_PIN_9287                8
 #define ATH_LED_PIN_9300                10
 #define ATH_LED_PIN_9485                6
-#define ATH_LED_PIN_9462                0
+#define ATH_LED_PIN_9462                4
 
 #ifdef CONFIG_MAC80211_LEDS
 void ath_init_leds(struct ath_softc *sc);
@@ -542,7 +545,7 @@ struct ath_ant_comb {
 #define DEFAULT_CACHELINE       32
 #define ATH_REGCLASSIDS_MAX     10
 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
-#define ATH_MAX_SW_RETRIES      10
+#define ATH_MAX_SW_RETRIES      30
 #define ATH_CHAN_MAX            255
 
 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
@@ -647,6 +650,7 @@ struct ath_softc {
         struct delayed_work tx_complete_work;
         struct delayed_work hw_pll_work;
         struct ath_btcoex btcoex;
+        struct ath_mci_coex mci_coex;
 
         struct ath_descdma txsdma;
 
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index 5a6361da9818..bbb20810ec10 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -14,13 +14,14 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/export.h>
 #include "hw.h"
 
 enum ath_bt_mode {
         ATH_BT_COEX_MODE_LEGACY,        /* legacy rx_clear mode */
         ATH_BT_COEX_MODE_UNSLOTTED,     /* untimed/unslotted mode */
         ATH_BT_COEX_MODE_SLOTTED,       /* slotted mode */
-        ATH_BT_COEX_MODE_DISALBED,      /* coexistence disabled */
+        ATH_BT_COEX_MODE_DISABLED,      /* coexistence disabled */
 };
 
 struct ath_btcoex_config {
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.h b/drivers/net/wireless/ath/ath9k/btcoex.h
index d5e5db1faad9..278361c867ca 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.h
+++ b/drivers/net/wireless/ath/ath9k/btcoex.h
@@ -54,8 +54,39 @@ enum ath_btcoex_scheme {
         ATH_BTCOEX_CFG_MCI,
 };
 
+struct ath9k_hw_mci {
+        u32 raw_intr;
+        u32 rx_msg_intr;
+        u32 cont_status;
+        u32 gpm_addr;
+        u32 gpm_len;
+        u32 gpm_idx;
+        u32 sched_addr;
+        u32 wlan_channels[4];
+        u32 wlan_cal_seq;
+        u32 wlan_cal_done;
+        u32 config;
+        u8 *gpm_buf;
+        u8 *sched_buf;
+        bool ready;
+        bool update_2g5g;
+        bool is_2g;
+        bool query_bt;
+        bool unhalt_bt_gpm; /* need send UNHALT */
+        bool halted_bt_gpm; /* HALT sent */
+        bool need_flush_btinfo;
+        bool bt_version_known;
+        bool wlan_channels_update;
+        u8 wlan_ver_major;
+        u8 wlan_ver_minor;
+        u8 bt_ver_major;
+        u8 bt_ver_minor;
+        u8 bt_state;
+};
+
 struct ath_btcoex_hw {
         enum ath_btcoex_scheme scheme;
+        struct ath9k_hw_mci mci;
         bool enabled;
         u8 wlanactive_gpio;
         u8 btactive_gpio;
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index ebaf304f464b..99538810a312 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -16,6 +16,7 @@
 
 #include "hw.h"
 #include "hw-ops.h"
+#include <linux/export.h>
 
 /* Common calibration code */
 
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index 8e7e57ccbe9a..68d972bf232d 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -16,6 +16,7 @@
 
 #include <linux/slab.h>
 #include <linux/vmalloc.h>
+#include <linux/export.h>
 #include <asm/unaligned.h>
 
 #include "ath9k.h"
@@ -855,7 +856,7 @@ void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
         sc->debug.stats.txstats[qnum].tx_bytes_all += bf->bf_mpdu->len;
 
         if (bf_isampdu(bf)) {
-                if (flags & ATH_TX_BAR)
+                if (flags & ATH_TX_ERROR)
                         TX_STAT_INC(qnum, a_xretries);
                 else
                         TX_STAT_INC(qnum, a_completed);
@@ -1629,6 +1630,9 @@ int ath9k_init_debug(struct ath_hw *ah)
         debugfs_create_file("debug", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
                             sc, &fops_debug);
 #endif
+
+        ath9k_dfs_init_debug(sc);
+
         debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
                             &fops_dma);
         debugfs_create_file("interrupt", S_IRUSR, sc->debug.debugfs_phy, sc,
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index 356352ac2d6e..776a24ada600 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -19,6 +19,7 @@
 
 #include "hw.h"
 #include "rc.h"
+#include "dfs_debug.h"
 
 struct ath_txq;
 struct ath_buf;
@@ -187,6 +188,7 @@ struct ath_stats {
         struct ath_interrupt_stats istats;
         struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
         struct ath_rx_stats rxstats;
+        struct ath_dfs_stats dfs_stats;
         u32 reset[__RESET_TYPE_MAX];
 };
 
diff --git a/drivers/net/wireless/ath/ath9k/dfs.c b/drivers/net/wireless/ath/ath9k/dfs.c
new file mode 100644
index 000000000000..e4e84a9e6273
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/dfs.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
+ * Copyright (c) 2011 Neratec Solutions AG
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "hw.h"
+#include "hw-ops.h"
+#include "ath9k.h"
+#include "dfs.h"
+#include "dfs_debug.h"
+
+/*
+ * TODO: move into or synchronize this with generic header
+ *       as soon as IF is defined
+ */
+struct dfs_radar_pulse {
+        u16 freq;
+        u64 ts;
+        u32 width;
+        u8 rssi;
+};
+
+/* internal struct to pass radar data */
+struct ath_radar_data {
+        u8 pulse_bw_info;
+        u8 rssi;
+        u8 ext_rssi;
+        u8 pulse_length_ext;
+        u8 pulse_length_pri;
+};
+
+/* convert pulse duration to usecs, considering clock mode */
+static u32 dur_to_usecs(struct ath_hw *ah, u32 dur)
+{
+        const u32 AR93X_NSECS_PER_DUR = 800;
+        const u32 AR93X_NSECS_PER_DUR_FAST = (8000 / 11);
+        u32 nsecs;
+
+        if (IS_CHAN_A_FAST_CLOCK(ah, ah->curchan))
+                nsecs = dur * AR93X_NSECS_PER_DUR_FAST;
+        else
+                nsecs = dur * AR93X_NSECS_PER_DUR;
+
+        return (nsecs + 500) / 1000;
+}
+
+#define PRI_CH_RADAR_FOUND 0x01
+#define EXT_CH_RADAR_FOUND 0x02
+static bool
+ath9k_postprocess_radar_event(struct ath_softc *sc,
+                              struct ath_radar_data *are,
+                              struct dfs_radar_pulse *drp)
+{
+        u8 rssi;
+        u16 dur;
+
+        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_DFS,
+                "pulse_bw_info=0x%x, pri,ext len/rssi=(%u/%u, %u/%u)\n",
+                are->pulse_bw_info,
+                are->pulse_length_pri, are->rssi,
+                are->pulse_length_ext, are->ext_rssi);
+
+        /*
+         * Only the last 2 bits of the BW info are relevant, they indicate
+         * which channel the radar was detected in.
+         */
+        are->pulse_bw_info &= 0x03;
+
+        switch (are->pulse_bw_info) {
+        case PRI_CH_RADAR_FOUND:
+                /* radar in ctrl channel */
+                dur = are->pulse_length_pri;
+                DFS_STAT_INC(sc, pri_phy_errors);
+                /*
+                 * cannot use ctrl channel RSSI
+                 * if extension channel is stronger
+                 */
+                rssi = (are->ext_rssi >= (are->rssi + 3)) ? 0 : are->rssi;
+                break;
+        case EXT_CH_RADAR_FOUND:
+                /* radar in extension channel */
+                dur = are->pulse_length_ext;
+                DFS_STAT_INC(sc, ext_phy_errors);
+                /*
+                 * cannot use extension channel RSSI
+                 * if control channel is stronger
+                 */
+                rssi = (are->rssi >= (are->ext_rssi + 12)) ? 0 : are->ext_rssi;
+                break;
+        case (PRI_CH_RADAR_FOUND | EXT_CH_RADAR_FOUND):
+                /*
+                 * Conducted testing, when pulse is on DC, both pri and ext
+                 * durations are reported to be same
+                 *
+                 * Radiated testing, when pulse is on DC, different pri and
+                 * ext durations are reported, so take the larger of the two
+                 */
+                if (are->pulse_length_ext >= are->pulse_length_pri)
+                        dur = are->pulse_length_ext;
+                else
+                        dur = are->pulse_length_pri;
+                DFS_STAT_INC(sc, dc_phy_errors);
+
+                /* when both are present use stronger one */
+                rssi = (are->rssi < are->ext_rssi) ? are->ext_rssi : are->rssi;
+                break;
+        default:
+                /*
+                 * Bogus bandwidth info was received in descriptor,
+                 * so ignore this PHY error
+                 */
+                DFS_STAT_INC(sc, bwinfo_discards);
+                return false;
+        }
+
+        if (rssi == 0) {
+                DFS_STAT_INC(sc, rssi_discards);
+                return false;
+        }
+
+        /*
+         * TODO: check chirping pulses
+         *       checks for chirping are dependent on the DFS regulatory domain
+         *       used, which is yet TBD
+         */
+
+        /* convert duration to usecs */
+        drp->width = dur_to_usecs(sc->sc_ah, dur);
+        drp->rssi = rssi;
+
+        DFS_STAT_INC(sc, pulses_detected);
+        return true;
+}
+#undef PRI_CH_RADAR_FOUND
+#undef EXT_CH_RADAR_FOUND
+
+/*
+ * DFS: check PHY-error for radar pulse and feed the detector
+ */
+void ath9k_dfs_process_phyerr(struct ath_softc *sc, void *data,
+                              struct ath_rx_status *rs, u64 mactime)
+{
+        struct ath_radar_data ard;
+        u16 datalen;
+        char *vdata_end;
+        struct dfs_radar_pulse drp;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        if ((!(rs->rs_phyerr != ATH9K_PHYERR_RADAR)) &&
+            (!(rs->rs_phyerr != ATH9K_PHYERR_FALSE_RADAR_EXT))) {
+                ath_dbg(common, ATH_DBG_DFS,
+                        "Error: rs_phyer=0x%x not a radar error\n",
+                        rs->rs_phyerr);
+                return;
+        }
+
+        datalen = rs->rs_datalen;
+        if (datalen == 0) {
+                DFS_STAT_INC(sc, datalen_discards);
+                return;
+        }
+
+        ard.rssi = rs->rs_rssi_ctl0;
+        ard.ext_rssi = rs->rs_rssi_ext0;
+
+        /*
+         * hardware stores this as 8 bit signed value.
+         * we will cap it at 0 if it is a negative number
+         */
+        if (ard.rssi & 0x80)
+                ard.rssi = 0;
+        if (ard.ext_rssi & 0x80)
+                ard.ext_rssi = 0;
+
+        vdata_end = (char *)data + datalen;
+        ard.pulse_bw_info = vdata_end[-1];
+        ard.pulse_length_ext = vdata_end[-2];
+        ard.pulse_length_pri = vdata_end[-3];
+
+        ath_dbg(common, ATH_DBG_DFS,
+                "bw_info=%d, length_pri=%d, length_ext=%d, "
+                "rssi_pri=%d, rssi_ext=%d\n",
+                ard.pulse_bw_info, ard.pulse_length_pri, ard.pulse_length_ext,
+                ard.rssi, ard.ext_rssi);
+
+        drp.freq = ah->curchan->channel;
+        drp.ts = mactime;
+        if (ath9k_postprocess_radar_event(sc, &ard, &drp)) {
+                static u64 last_ts;
+                ath_dbg(common, ATH_DBG_DFS,
+                        "ath9k_dfs_process_phyerr: channel=%d, ts=%llu, "
+                        "width=%d, rssi=%d, delta_ts=%llu\n",
+                        drp.freq, drp.ts, drp.width, drp.rssi, drp.ts-last_ts);
+                last_ts = drp.ts;
+                /*
+                 * TODO: forward pulse to pattern detector
+                 *
+                 * ieee80211_add_radar_pulse(drp.freq, drp.ts,
+                 *                           drp.width, drp.rssi);
+                 */
+        }
+}
diff --git a/drivers/net/wireless/ath/ath9k/dfs.h b/drivers/net/wireless/ath/ath9k/dfs.h
new file mode 100644
index 000000000000..c2412857f122
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/dfs.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
+ * Copyright (c) 2011 Neratec Solutions AG
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef ATH9K_DFS_H
+#define ATH9K_DFS_H
+
+#if defined(CONFIG_ATH9K_DFS_CERTIFIED)
+/**
+ * ath9k_dfs_process_phyerr - process radar PHY error
+ * @sc: ath_softc
+ * @data: RX payload data
+ * @rs: RX status after processing descriptor
+ * @mactime: receive time
+ *
+ * This function is called whenever the HW DFS module detects a radar
+ * pulse and reports it as a PHY error.
+ *
+ * The radar information provided as raw payload data is validated and
+ * filtered for false pulses. Events passing all tests are forwarded to
+ * the upper layer for pattern detection.
+ */
+void ath9k_dfs_process_phyerr(struct ath_softc *sc, void *data,
+                              struct ath_rx_status *rs, u64 mactime);
+#else
+static inline void ath9k_dfs_process_phyerr(struct ath_softc *sc, void *data,
+                                            struct ath_rx_status *rs, u64 mactime) { }
+#endif
+
+#endif /* ATH9K_DFS_H */
diff --git a/drivers/net/wireless/ath/ath9k/dfs_debug.c b/drivers/net/wireless/ath/ath9k/dfs_debug.c
new file mode 100644
index 000000000000..106d031d834a
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/dfs_debug.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
+ * Copyright (c) 2011 Neratec Solutions AG
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/export.h>
+
+#include "ath9k.h"
+#include "dfs_debug.h"
+
+#define ATH9K_DFS_STAT(s, p) \
+        len += snprintf(buf + len, size - len, "%28s : %10u\n", s, \
+                        sc->debug.stats.dfs_stats.p);
+
+static ssize_t read_file_dfs(struct file *file, char __user *user_buf,
+                             size_t count, loff_t *ppos)
+{
+        struct ath_softc *sc = file->private_data;
+        struct ath9k_hw_version *hw_ver = &sc->sc_ah->hw_version;
+        char *buf;
+        unsigned int len = 0, size = 8000;
+        ssize_t retval = 0;
+
+        buf = kzalloc(size, GFP_KERNEL);
+        if (buf == NULL)
+                return -ENOMEM;
+
+        len += snprintf(buf + len, size - len, "DFS support for "
+                        "macVersion = 0x%x, macRev = 0x%x: %s\n",
+                        hw_ver->macVersion, hw_ver->macRev,
+                        (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_DFS) ?
+                                        "enabled" : "disabled");
+        ATH9K_DFS_STAT("DFS pulses detected     ", pulses_detected);
+        ATH9K_DFS_STAT("Datalen discards        ", datalen_discards);
+        ATH9K_DFS_STAT("RSSI discards           ", rssi_discards);
+        ATH9K_DFS_STAT("BW info discards        ", bwinfo_discards);
+        ATH9K_DFS_STAT("Primary channel pulses  ", pri_phy_errors);
+        ATH9K_DFS_STAT("Secondary channel pulses", ext_phy_errors);
+        ATH9K_DFS_STAT("Dual channel pulses     ", dc_phy_errors);
+
+        if (len > size)
+                len = size;
+
+        retval = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return retval;
+}
+
+static int ath9k_dfs_debugfs_open(struct inode *inode, struct file *file)
+{
+        file->private_data = inode->i_private;
+
+        return 0;
+}
+
+static const struct file_operations fops_dfs_stats = {
+        .read = read_file_dfs,
+        .open = ath9k_dfs_debugfs_open,
+        .owner = THIS_MODULE,
+        .llseek = default_llseek,
+};
+
+void ath9k_dfs_init_debug(struct ath_softc *sc)
+{
+        debugfs_create_file("dfs_stats", S_IRUSR,
+                            sc->debug.debugfs_phy, sc, &fops_dfs_stats);
+}
diff --git a/drivers/net/wireless/ath/ath9k/dfs_debug.h b/drivers/net/wireless/ath/ath9k/dfs_debug.h
new file mode 100644
index 000000000000..6e1e2a71659e
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/dfs_debug.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2008-2011 Atheros Communications Inc.
+ * Copyright (c) 2011 Neratec Solutions AG
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef DFS_DEBUG_H
+#define DFS_DEBUG_H
+
+#include "hw.h"
+
+/**
+ * struct ath_dfs_stats - DFS Statistics
+ *
+ * @pulses_detected:  No. of pulses detected so far
+ * @datalen_discards: No. of pulses discarded due to invalid datalen
+ * @rssi_discards:    No. of pulses discarded due to invalid RSSI
+ * @bwinfo_discards:  No. of pulses discarded due to invalid BW info
+ * @pri_phy_errors:   No. of pulses reported for primary channel
+ * @ext_phy_errors:   No. of pulses reported for extension channel
+ * @dc_phy_errors:    No. of pulses reported for primary + extension channel
+ */
+struct ath_dfs_stats {
+        u32 pulses_detected;
+        u32 datalen_discards;
+        u32 rssi_discards;
+        u32 bwinfo_discards;
+        u32 pri_phy_errors;
+        u32 ext_phy_errors;
+        u32 dc_phy_errors;
+};
+
+#if defined(CONFIG_ATH9K_DFS_DEBUGFS)
+
+#define DFS_STAT_INC(sc, c) (sc->debug.stats.dfs_stats.c++)
+void ath9k_dfs_init_debug(struct ath_softc *sc);
+
+#else
+
+#define DFS_STAT_INC(sc, c) do { } while (0)
+static inline void ath9k_dfs_init_debug(struct ath_softc *sc) { }
+
+#endif /* CONFIG_ATH9K_DFS_DEBUGFS */
+
+#endif /* DFS_DEBUG_H */
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 9a7520f987f0..61fcab0e2d76 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -473,7 +473,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 
         int i;
         u16 twiceMinEdgePower;
-        u16 twiceMaxEdgePower = MAX_RATE_POWER;
+        u16 twiceMaxEdgePower;
         u16 scaledPower = 0, minCtlPower;
         u16 numCtlModes;
         const u16 *pCtlMode;
@@ -542,9 +542,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
                 else
                         freq = centers.ctl_center;
 
-                if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
-                    ah->eep_ops->get_eeprom_rev(ah) <= 2)
-                        twiceMaxEdgePower = MAX_RATE_POWER;
+                twiceMaxEdgePower = MAX_RATE_POWER;
 
                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
                              pEepData->ctlIndex[i]; i++) {
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index 4f5c50a87ce3..0981c073471d 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -569,7 +569,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6
 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   10
 
-        u16 twiceMaxEdgePower = MAX_RATE_POWER;
+        u16 twiceMaxEdgePower;
         int i;
         struct cal_ctl_data_ar9287 *rep;
         struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
@@ -669,6 +669,7 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
                 else
                         freq = centers.ctl_center;
 
+                twiceMaxEdgePower = MAX_RATE_POWER;
                 /* Walk through the CTL indices stored in EEPROM */
                 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
                         struct cal_ctl_edges *pRdEdgesPower;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index 81e629671679..55a21d39167c 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -1000,7 +1000,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */
 
         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
-        u16 twiceMaxEdgePower = MAX_RATE_POWER;
+        u16 twiceMaxEdgePower;
         int i;
         struct cal_ctl_data *rep;
         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
@@ -1121,9 +1121,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
                 else
                         freq = centers.ctl_center;
 
-                if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
-                    ah->eep_ops->get_eeprom_rev(ah) <= 2)
-                        twiceMaxEdgePower = MAX_RATE_POWER;
+                twiceMaxEdgePower = MAX_RATE_POWER;
 
                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
                         if ((((cfgCtl & ~CTL_MODE_M) |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index 0b9a0e8a4958..f8ce4ea6f65c 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -808,7 +808,8 @@ void ath9k_htc_ani_work(struct work_struct *work)
         }
 
         /* Verify whether we must check ANI */
-        if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
+        if (ah->config.enable_ani &&
+            (timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
                 aniflag = true;
                 common->ani.checkani_timer = timestamp;
         }
@@ -838,7 +839,7 @@ set_timer:
         * short calibration and long calibration.
         */
         cal_interval = ATH_LONG_CALINTERVAL;
-        if (priv->ah->config.enable_ani)
+        if (ah->config.enable_ani)
                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
         if (!common->ani.caldone)
                 cal_interval = min(cal_interval, (u32)short_cal_interval);
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
index e74c233757a2..c4ad0b06bdbc 100644
--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
@@ -212,4 +212,13 @@ static inline int ath9k_hw_fast_chan_change(struct ath_hw *ah,
         return ath9k_hw_private_ops(ah)->fast_chan_change(ah, chan,
                                                           ini_reloaded);
 }
+
+static inline void ath9k_hw_set_radar_params(struct ath_hw *ah)
+{
+        if (!ath9k_hw_private_ops(ah)->set_radar_params)
+                return;
+
+        ath9k_hw_private_ops(ah)->set_radar_params(ah, &ah->radar_conf);
+}
+
 #endif /* ATH9K_HW_OPS_H */
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 27471f80d8b2..8cda9a1513a7 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -16,6 +16,7 @@
 
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/module.h>
 #include <asm/unaligned.h>
 
 #include "hw.h"
@@ -503,7 +504,7 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
                 return ecode;
         }
 
-        if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
+        if (ah->config.enable_ani) {
                 ath9k_hw_ani_setup(ah);
                 ath9k_hw_ani_init(ah);
         }
@@ -609,6 +610,10 @@ static int __ath9k_hw_init(struct ath_hw *ah)
         if (!AR_SREV_9300_20_OR_LATER(ah))
                 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
 
+        /* disable ANI for 9340 */
+        if (AR_SREV_9340(ah))
+                ah->config.enable_ani = false;
+
         ath9k_hw_init_mode_regs(ah);
 
         if (!ah->is_pciexpress)
@@ -1349,6 +1354,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
 
 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
 {
+        bool ret = false;
 
         if (AR_SREV_9300_20_OR_LATER(ah)) {
                 REG_WRITE(ah, AR_WA, ah->WARegVal);
@@ -1360,13 +1366,20 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
 
         switch (type) {
         case ATH9K_RESET_POWER_ON:
-                return ath9k_hw_set_reset_power_on(ah);
+                ret = ath9k_hw_set_reset_power_on(ah);
+                break;
         case ATH9K_RESET_WARM:
         case ATH9K_RESET_COLD:
-                return ath9k_hw_set_reset(ah, type);
+                ret = ath9k_hw_set_reset(ah, type);
+                break;
         default:
-                return false;
+                break;
         }
+
+        if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
+                REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
+
+        return ret;
 }
 
 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
@@ -1505,6 +1518,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                    struct ath9k_hw_cal_data *caldata, bool bChannelChange)
 {
         struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
         u32 saveLedState;
         struct ath9k_channel *curchan = ah->curchan;
         u32 saveDefAntenna;
@@ -1512,6 +1526,53 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         u64 tsf = 0;
         int i, r;
         bool allow_fbs = false;
+        bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
+        bool save_fullsleep = ah->chip_fullsleep;
+
+        if (mci) {
+
+                ar9003_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan));
+
+                if (mci_hw->bt_state == MCI_BT_CAL_START) {
+                        u32 payload[4] = {0, 0, 0, 0};
+
+                        ath_dbg(common, ATH_DBG_MCI, "MCI stop rx for BT CAL");
+
+                        mci_hw->bt_state = MCI_BT_CAL;
+
+                        /*
+                         * MCI FIX: disable mci interrupt here. This is to avoid
+                         * SW_MSG_DONE or RX_MSG bits to trigger MCI_INT and
+                         * lead to mci_intr reentry.
+                         */
+
+                        ar9003_mci_disable_interrupt(ah);
+
+                        ath_dbg(common, ATH_DBG_MCI, "send WLAN_CAL_GRANT");
+                        MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT);
+                        ar9003_mci_send_message(ah, MCI_GPM, 0, payload,
+                                                16, true, false);
+
+                        ath_dbg(common, ATH_DBG_MCI, "\nMCI BT is calibrating");
+
+                        /* Wait BT calibration to be completed for 25ms */
+
+                        if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE,
+                                                                  0, 25000))
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI got BT_CAL_DONE\n");
+                        else
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI ### BT cal takes to long, force"
+                                        "bt_state to be bt_awake\n");
+                        mci_hw->bt_state = MCI_BT_AWAKE;
+                        /* MCI FIX: enable mci interrupt here */
+                        ar9003_mci_enable_interrupt(ah);
+
+                        return true;
+                }
+        }
+
 
         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
                 return -EIO;
@@ -1549,12 +1610,29 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                 if (ath9k_hw_channel_change(ah, chan)) {
                         ath9k_hw_loadnf(ah, ah->curchan);
                         ath9k_hw_start_nfcal(ah, true);
+                        if (mci && mci_hw->ready)
+                                ar9003_mci_2g5g_switch(ah, true);
+
                         if (AR_SREV_9271(ah))
                                 ar9002_hw_load_ani_reg(ah, chan);
                         return 0;
                 }
         }
 
+        if (mci) {
+                ar9003_mci_disable_interrupt(ah);
+
+                if (mci_hw->ready && !save_fullsleep) {
+                        ar9003_mci_mute_bt(ah);
+                        udelay(20);
+                        REG_WRITE(ah, AR_BTCOEX_CTRL, 0);
+                }
+
+                mci_hw->bt_state = MCI_BT_SLEEP;
+                mci_hw->ready = false;
+        }
+
+
         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
         if (saveDefAntenna == 0)
                 saveDefAntenna = 1;
@@ -1610,6 +1688,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         if (r)
                 return r;
 
+        if (mci)
+                ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
+
         /*
          * Some AR91xx SoC devices frequently fail to accept TSF writes
          * right after the chip reset. When that happens, write a new
@@ -1727,6 +1808,55 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         ath9k_hw_loadnf(ah, chan);
         ath9k_hw_start_nfcal(ah, true);
 
+        if (mci && mci_hw->ready) {
+
+                if (IS_CHAN_2GHZ(chan) &&
+                    (mci_hw->bt_state == MCI_BT_SLEEP)) {
+
+                        if (ar9003_mci_check_int(ah,
+                            AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) ||
+                            ar9003_mci_check_int(ah,
+                            AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) {
+
+                                /*
+                                 * BT is sleeping. Check if BT wakes up during
+                                 * WLAN calibration. If BT wakes up during
+                                 * WLAN calibration, need to go through all
+                                 * message exchanges again and recal.
+                                 */
+
+                                ath_dbg(common, ATH_DBG_MCI, "MCI BT wakes up"
+                                        "during WLAN calibration\n");
+
+                                REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
+                                          AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET |
+                                          AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE);
+                                ath_dbg(common, ATH_DBG_MCI, "MCI send"
+                                        "REMOTE_RESET\n");
+                                ar9003_mci_remote_reset(ah, true);
+                                ar9003_mci_send_sys_waking(ah, true);
+                                udelay(1);
+                                if (IS_CHAN_2GHZ(chan))
+                                        ar9003_mci_send_lna_transfer(ah, true);
+
+                                mci_hw->bt_state = MCI_BT_AWAKE;
+
+                                ath_dbg(common, ATH_DBG_MCI, "MCI re-cal\n");
+
+                                if (caldata) {
+                                        caldata->done_txiqcal_once = false;
+                                        caldata->done_txclcal_once = false;
+                                        caldata->rtt_hist.num_readings = 0;
+                                }
+
+                                if (!ath9k_hw_init_cal(ah, chan))
+                                        return -EIO;
+
+                        }
+                }
+                ar9003_mci_enable_interrupt(ah);
+        }
+
         ENABLE_REGWRITE_BUFFER(ah);
 
         ath9k_hw_restore_chainmask(ah);
@@ -1769,6 +1899,21 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         if (ah->btcoex_hw.enabled)
                 ath9k_hw_btcoex_enable(ah);
 
+        if (mci && mci_hw->ready) {
+                /*
+                 * check BT state again to make
+                 * sure it's not changed.
+                 */
+
+                ar9003_mci_sync_bt_state(ah);
+                ar9003_mci_2g5g_switch(ah, true);
+
+                if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
+                                (mci_hw->query_bt == true)) {
+                        mci_hw->need_flush_btinfo = true;
+                }
+        }
+
         if (AR_SREV_9300_20_OR_LATER(ah)) {
                 ar9003_hw_bb_watchdog_config(ah);
 
@@ -1826,7 +1971,8 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
         }
 
         /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
-        REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
+        if (AR_SREV_9300_20_OR_LATER(ah))
+                REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
 }
 
 /*
@@ -1932,6 +2078,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
 {
         struct ath_common *common = ath9k_hw_common(ah);
+        struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
         int status = true, setChip = true;
         static const char *modes[] = {
                 "AWAKE",
@@ -1949,12 +2096,35 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
         switch (mode) {
         case ATH9K_PM_AWAKE:
                 status = ath9k_hw_set_power_awake(ah, setChip);
+
+                if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
+                        REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
+
                 break;
         case ATH9K_PM_FULL_SLEEP:
+
+                if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) {
+                        if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) &&
+                                (mci->bt_state != MCI_BT_SLEEP) &&
+                                !mci->halted_bt_gpm) {
+                                ath_dbg(common, ATH_DBG_MCI, "MCI halt BT GPM"
+                                                "(full_sleep)");
+                                ar9003_mci_send_coex_halt_bt_gpm(ah,
+                                                                 true, true);
+                        }
+
+                        mci->ready = false;
+                        REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
+                }
+
                 ath9k_set_power_sleep(ah, setChip);
                 ah->chip_fullsleep = true;
                 break;
         case ATH9K_PM_NETWORK_SLEEP:
+
+                if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
+                        REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
+
                 ath9k_set_power_network_sleep(ah, setChip);
                 break;
         default:
@@ -2107,6 +2277,30 @@ static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
                 return chip_chainmask;
 }
 
+/**
+ * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
+ * @ah: the atheros hardware data structure
+ *
+ * We enable DFS support upstream on chipsets which have passed a series
+ * of tests. The testing requirements are going to be documented. Desired
+ * test requirements are documented at:
+ *
+ * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
+ *
+ * Once a new chipset gets properly tested an individual commit can be used
+ * to document the testing for DFS for that chipset.
+ */
+static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
+{
+
+        switch (ah->hw_version.macVersion) {
+        /* AR9580 will likely be our first target to get testing on */
+        case AR_SREV_VERSION_9580:
+        default:
+                return false;
+        }
+}
+
 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
 {
         struct ath9k_hw_capabilities *pCap = &ah->caps;
@@ -2147,6 +2341,8 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
 
         if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
                 chip_chainmask = 1;
+        else if (AR_SREV_9462(ah))
+                chip_chainmask = 3;
         else if (!AR_SREV_9280_20_OR_LATER(ah))
                 chip_chainmask = 7;
         else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
@@ -2203,12 +2399,10 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
         else
                 pCap->num_gpio_pins = AR_NUM_GPIO;
 
-        if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
-                pCap->hw_caps |= ATH9K_HW_CAP_CST;
+        if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
-        } else {
+        else
                 pCap->rts_aggr_limit = (8 * 1024);
-        }
 
 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
@@ -2232,7 +2426,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
 
         if (common->btcoex_enabled) {
-                if (AR_SREV_9300_20_OR_LATER(ah)) {
+                if (AR_SREV_9462(ah))
+                        btcoex_hw->scheme = ATH_BTCOEX_CFG_MCI;
+                else if (AR_SREV_9300_20_OR_LATER(ah)) {
                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
                         btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
                         btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
@@ -2316,6 +2512,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                 pCap->pcie_lcr_offset = 0x80;
         }
 
+        if (ath9k_hw_dfs_tested(ah))
+                pCap->hw_caps |= ATH9K_HW_CAP_DFS;
+
         tx_chainmask = pCap->tx_chainmask;
         rx_chainmask = pCap->rx_chainmask;
         while (tx_chainmask || rx_chainmask) {
@@ -2330,7 +2529,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
 
         if (AR_SREV_9300_20_OR_LATER(ah)) {
                 ah->enabled_cals |= TX_IQ_CAL;
-                if (!AR_SREV_9330(ah))
+                if (AR_SREV_9485_OR_LATER(ah))
                         ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
         }
         if (AR_SREV_9462(ah))
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 3cb878c28ccf..615cc839f0de 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -126,6 +126,16 @@
 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL  4
 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
+#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA      0x16
+#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK       0x17
+#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA        0x18
+#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK         0x19
+#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX           0x14
+#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX           0x13
+#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX           9
+#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX           8
+#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE      0x1d
+#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA        0x1e
 
 #define AR_GPIOD_MASK               0x00001FFF
 #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
@@ -186,21 +196,21 @@ enum ath_ini_subsys {
 enum ath9k_hw_caps {
         ATH9K_HW_CAP_HT                         = BIT(0),
         ATH9K_HW_CAP_RFSILENT                   = BIT(1),
-        ATH9K_HW_CAP_CST                        = BIT(2),
-        ATH9K_HW_CAP_AUTOSLEEP                  = BIT(4),
-        ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(5),
-        ATH9K_HW_CAP_EDMA                       = BIT(6),
-        ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(7),
-        ATH9K_HW_CAP_LDPC                       = BIT(8),
-        ATH9K_HW_CAP_FASTCLOCK                  = BIT(9),
-        ATH9K_HW_CAP_SGI_20                     = BIT(10),
-        ATH9K_HW_CAP_PAPRD                      = BIT(11),
-        ATH9K_HW_CAP_ANT_DIV_COMB               = BIT(12),
-        ATH9K_HW_CAP_2GHZ                       = BIT(13),
-        ATH9K_HW_CAP_5GHZ                       = BIT(14),
-        ATH9K_HW_CAP_APM                        = BIT(15),
-        ATH9K_HW_CAP_RTT                        = BIT(16),
-        ATH9K_HW_CAP_MCI                        = BIT(17),
+        ATH9K_HW_CAP_AUTOSLEEP                  = BIT(2),
+        ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(3),
+        ATH9K_HW_CAP_EDMA                       = BIT(4),
+        ATH9K_HW_CAP_RAC_SUPPORTED              = BIT(5),
+        ATH9K_HW_CAP_LDPC                       = BIT(6),
+        ATH9K_HW_CAP_FASTCLOCK                  = BIT(7),
+        ATH9K_HW_CAP_SGI_20                     = BIT(8),
+        ATH9K_HW_CAP_PAPRD                      = BIT(9),
+        ATH9K_HW_CAP_ANT_DIV_COMB               = BIT(10),
+        ATH9K_HW_CAP_2GHZ                       = BIT(11),
+        ATH9K_HW_CAP_5GHZ                       = BIT(12),
+        ATH9K_HW_CAP_APM                        = BIT(13),
+        ATH9K_HW_CAP_RTT                        = BIT(14),
+        ATH9K_HW_CAP_MCI                        = BIT(15),
+        ATH9K_HW_CAP_DFS                        = BIT(16),
 };
 
 struct ath9k_hw_capabilities {
@@ -266,6 +276,7 @@ enum ath9k_int {
         ATH9K_INT_TX = 0x00000040,
         ATH9K_INT_TXDESC = 0x00000080,
         ATH9K_INT_TIM_TIMER = 0x00000100,
+        ATH9K_INT_MCI = 0x00000200,
         ATH9K_INT_BB_WATCHDOG = 0x00000400,
         ATH9K_INT_TXURN = 0x00000800,
         ATH9K_INT_MIB = 0x00001000,
@@ -417,6 +428,25 @@ enum ath9k_rx_qtype {
         ATH9K_RX_QUEUE_MAX,
 };
 
+enum mci_message_header {               /* length of payload */
+        MCI_LNA_CTRL     = 0x10,        /* len = 0 */
+        MCI_CONT_NACK    = 0x20,        /* len = 0 */
+        MCI_CONT_INFO    = 0x30,        /* len = 4 */
+        MCI_CONT_RST     = 0x40,        /* len = 0 */
+        MCI_SCHD_INFO    = 0x50,        /* len = 16 */
+        MCI_CPU_INT      = 0x60,        /* len = 4 */
+        MCI_SYS_WAKING   = 0x70,        /* len = 0 */
+        MCI_GPM          = 0x80,        /* len = 16 */
+        MCI_LNA_INFO     = 0x90,        /* len = 1 */
+        MCI_LNA_STATE    = 0x94,
+        MCI_LNA_TAKE     = 0x98,
+        MCI_LNA_TRANS    = 0x9c,
+        MCI_SYS_SLEEPING = 0xa0,        /* len = 0 */
+        MCI_REQ_WAKE     = 0xc0,        /* len = 0 */
+        MCI_DEBUG_16     = 0xfe,        /* len = 2 */
+        MCI_REMOTE_RESET = 0xff         /* len = 16 */
+};
+
 enum ath_mci_gpm_coex_profile_type {
         MCI_GPM_COEX_PROFILE_UNKNOWN,
         MCI_GPM_COEX_PROFILE_RFCOMM,
@@ -427,6 +457,132 @@ enum ath_mci_gpm_coex_profile_type {
         MCI_GPM_COEX_PROFILE_MAX
 };
 
+/* MCI GPM/Coex opcode/type definitions */
+enum {
+        MCI_GPM_COEX_W_GPM_PAYLOAD      = 1,
+        MCI_GPM_COEX_B_GPM_TYPE         = 4,
+        MCI_GPM_COEX_B_GPM_OPCODE       = 5,
+        /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
+        MCI_GPM_WLAN_CAL_W_SEQUENCE     = 2,
+
+        /* MCI_GPM_COEX_VERSION_QUERY */
+        /* MCI_GPM_COEX_VERSION_RESPONSE */
+        MCI_GPM_COEX_B_MAJOR_VERSION    = 6,
+        MCI_GPM_COEX_B_MINOR_VERSION    = 7,
+        /* MCI_GPM_COEX_STATUS_QUERY */
+        MCI_GPM_COEX_B_BT_BITMAP        = 6,
+        MCI_GPM_COEX_B_WLAN_BITMAP      = 7,
+        /* MCI_GPM_COEX_HALT_BT_GPM */
+        MCI_GPM_COEX_B_HALT_STATE       = 6,
+        /* MCI_GPM_COEX_WLAN_CHANNELS */
+        MCI_GPM_COEX_B_CHANNEL_MAP      = 6,
+        /* MCI_GPM_COEX_BT_PROFILE_INFO */
+        MCI_GPM_COEX_B_PROFILE_TYPE     = 6,
+        MCI_GPM_COEX_B_PROFILE_LINKID   = 7,
+        MCI_GPM_COEX_B_PROFILE_STATE    = 8,
+        MCI_GPM_COEX_B_PROFILE_ROLE     = 9,
+        MCI_GPM_COEX_B_PROFILE_RATE     = 10,
+        MCI_GPM_COEX_B_PROFILE_VOTYPE   = 11,
+        MCI_GPM_COEX_H_PROFILE_T        = 12,
+        MCI_GPM_COEX_B_PROFILE_W        = 14,
+        MCI_GPM_COEX_B_PROFILE_A        = 15,
+        /* MCI_GPM_COEX_BT_STATUS_UPDATE */
+        MCI_GPM_COEX_B_STATUS_TYPE      = 6,
+        MCI_GPM_COEX_B_STATUS_LINKID    = 7,
+        MCI_GPM_COEX_B_STATUS_STATE     = 8,
+        /* MCI_GPM_COEX_BT_UPDATE_FLAGS */
+        MCI_GPM_COEX_W_BT_FLAGS         = 6,
+        MCI_GPM_COEX_B_BT_FLAGS_OP      = 10
+};
+
+enum mci_gpm_subtype {
+        MCI_GPM_BT_CAL_REQ      = 0,
+        MCI_GPM_BT_CAL_GRANT    = 1,
+        MCI_GPM_BT_CAL_DONE     = 2,
+        MCI_GPM_WLAN_CAL_REQ    = 3,
+        MCI_GPM_WLAN_CAL_GRANT  = 4,
+        MCI_GPM_WLAN_CAL_DONE   = 5,
+        MCI_GPM_COEX_AGENT      = 0x0c,
+        MCI_GPM_RSVD_PATTERN    = 0xfe,
+        MCI_GPM_RSVD_PATTERN32  = 0xfefefefe,
+        MCI_GPM_BT_DEBUG        = 0xff
+};
+
+enum mci_bt_state {
+        MCI_BT_SLEEP,
+        MCI_BT_AWAKE,
+        MCI_BT_CAL_START,
+        MCI_BT_CAL
+};
+
+/* Type of state query */
+enum mci_state_type {
+        MCI_STATE_ENABLE,
+        MCI_STATE_INIT_GPM_OFFSET,
+        MCI_STATE_NEXT_GPM_OFFSET,
+        MCI_STATE_LAST_GPM_OFFSET,
+        MCI_STATE_BT,
+        MCI_STATE_SET_BT_SLEEP,
+        MCI_STATE_SET_BT_AWAKE,
+        MCI_STATE_SET_BT_CAL_START,
+        MCI_STATE_SET_BT_CAL,
+        MCI_STATE_LAST_SCHD_MSG_OFFSET,
+        MCI_STATE_REMOTE_SLEEP,
+        MCI_STATE_CONT_RSSI_POWER,
+        MCI_STATE_CONT_PRIORITY,
+        MCI_STATE_CONT_TXRX,
+        MCI_STATE_RESET_REQ_WAKE,
+        MCI_STATE_SEND_WLAN_COEX_VERSION,
+        MCI_STATE_SET_BT_COEX_VERSION,
+        MCI_STATE_SEND_WLAN_CHANNELS,
+        MCI_STATE_SEND_VERSION_QUERY,
+        MCI_STATE_SEND_STATUS_QUERY,
+        MCI_STATE_NEED_FLUSH_BT_INFO,
+        MCI_STATE_SET_CONCUR_TX_PRI,
+        MCI_STATE_RECOVER_RX,
+        MCI_STATE_NEED_FTP_STOMP,
+        MCI_STATE_NEED_TUNING,
+        MCI_STATE_DEBUG,
+        MCI_STATE_MAX
+};
+
+enum mci_gpm_coex_opcode {
+        MCI_GPM_COEX_VERSION_QUERY,
+        MCI_GPM_COEX_VERSION_RESPONSE,
+        MCI_GPM_COEX_STATUS_QUERY,
+        MCI_GPM_COEX_HALT_BT_GPM,
+        MCI_GPM_COEX_WLAN_CHANNELS,
+        MCI_GPM_COEX_BT_PROFILE_INFO,
+        MCI_GPM_COEX_BT_STATUS_UPDATE,
+        MCI_GPM_COEX_BT_UPDATE_FLAGS
+};
+
+#define MCI_GPM_NOMORE  0
+#define MCI_GPM_MORE    1
+#define MCI_GPM_INVALID 0xffffffff
+
+#define MCI_GPM_RECYCLE(_p_gpm) do {                      \
+        *(((u32 *)_p_gpm) + MCI_GPM_COEX_W_GPM_PAYLOAD) = \
+                                MCI_GPM_RSVD_PATTERN32;   \
+} while (0)
+
+#define MCI_GPM_TYPE(_p_gpm)    \
+        (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
+
+#define MCI_GPM_OPCODE(_p_gpm)  \
+        (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
+
+#define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) do {                       \
+        *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\
+} while (0)
+
+#define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) do {               \
+        *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff;    \
+        *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\
+} while (0)
+
+#define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
+
 struct ath9k_beacon_state {
         u32 bs_nexttbtt;
         u32 bs_nextdtim;
@@ -954,7 +1110,6 @@ bool ath9k_hw_disable(struct ath_hw *ah);
 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
 void ath9k_hw_setopmode(struct ath_hw *ah);
 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
-void ath9k_hw_setbssidmask(struct ath_hw *ah);
 void ath9k_hw_write_associd(struct ath_hw *ah);
 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
@@ -1047,6 +1202,32 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
 
+bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
+                             u32 *payload, u8 len, bool wait_done,
+                             bool check_bt);
+void ar9003_mci_mute_bt(struct ath_hw *ah);
+u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data);
+void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
+                      u16 len, u32 sched_addr);
+void ar9003_mci_cleanup(struct ath_hw *ah);
+void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt,
+                                      bool wait_done);
+u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
+                            u8 gpm_opcode, int time_out);
+void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g);
+void ar9003_mci_disable_interrupt(struct ath_hw *ah);
+void ar9003_mci_enable_interrupt(struct ath_hw *ah);
+void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done);
+void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
+                      bool is_full_sleep);
+bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints);
+void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done);
+void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done);
+void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done);
+void ar9003_mci_sync_bt_state(struct ath_hw *ah);
+void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
+                              u32 *rx_msg_intr);
+
 #define ATH9K_CLOCK_RATE_CCK            22
 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 5cb0599b01c2..c5df98139c4d 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -17,6 +17,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include <linux/ath9k_platform.h>
+#include <linux/module.h>
 
 #include "ath9k.h"
 
@@ -257,6 +258,8 @@ static void setup_ht_cap(struct ath_softc *sc,
 
         if (AR_SREV_9330(ah) || AR_SREV_9485(ah))
                 max_streams = 1;
+        else if (AR_SREV_9462(ah))
+                max_streams = 2;
         else if (AR_SREV_9300_20_OR_LATER(ah))
                 max_streams = 3;
         else
@@ -294,9 +297,22 @@ static int ath9k_reg_notifier(struct wiphy *wiphy,
 {
         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
         struct ath_softc *sc = hw->priv;
-        struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
+        int ret;
+
+        ret = ath_reg_notifier_apply(wiphy, request, reg);
+
+        /* Set tx power */
+        if (ah->curchan) {
+                sc->config.txpowlimit = 2 * ah->curchan->chan->max_power;
+                ath9k_ps_wakeup(sc);
+                ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
+                sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
+                ath9k_ps_restore(sc);
+        }
 
-        return ath_reg_notifier_apply(wiphy, request, reg);
+        return ret;
 }
 
 /*
@@ -407,6 +423,7 @@ fail:
 static int ath9k_init_btcoex(struct ath_softc *sc)
 {
         struct ath_txq *txq;
+        struct ath_hw *ah = sc->sc_ah;
         int r;
 
         switch (sc->sc_ah->btcoex_hw.scheme) {
@@ -423,8 +440,37 @@ static int ath9k_init_btcoex(struct ath_softc *sc)
                 txq = sc->tx.txq_map[WME_AC_BE];
                 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
+                break;
+        case ATH_BTCOEX_CFG_MCI:
+                sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
                 sc->btcoex.duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE;
                 INIT_LIST_HEAD(&sc->btcoex.mci.info);
+
+                r = ath_mci_setup(sc);
+                if (r)
+                        return r;
+
+                if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) {
+                        ah->btcoex_hw.mci.ready = false;
+                        ah->btcoex_hw.mci.bt_state = 0;
+                        ah->btcoex_hw.mci.bt_ver_major = 3;
+                        ah->btcoex_hw.mci.bt_ver_minor = 0;
+                        ah->btcoex_hw.mci.bt_version_known = false;
+                        ah->btcoex_hw.mci.update_2g5g = true;
+                        ah->btcoex_hw.mci.is_2g = true;
+                        ah->btcoex_hw.mci.wlan_channels_update = false;
+                        ah->btcoex_hw.mci.wlan_channels[0] = 0x00000000;
+                        ah->btcoex_hw.mci.wlan_channels[1] = 0xffffffff;
+                        ah->btcoex_hw.mci.wlan_channels[2] = 0xffffffff;
+                        ah->btcoex_hw.mci.wlan_channels[3] = 0x7fffffff;
+                        ah->btcoex_hw.mci.query_bt = true;
+                        ah->btcoex_hw.mci.unhalt_bt_gpm = true;
+                        ah->btcoex_hw.mci.halted_bt_gpm = false;
+                        ah->btcoex_hw.mci.need_flush_btinfo = false;
+                        ah->btcoex_hw.mci.wlan_cal_seq = 0;
+                        ah->btcoex_hw.mci.wlan_cal_done = 0;
+                        ah->btcoex_hw.mci.config = 0x2201;
+                }
                 break;
         default:
                 WARN_ON(1);
@@ -838,6 +884,9 @@ static void ath9k_deinit_softc(struct ath_softc *sc)
             sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
                 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
 
+        if (sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_MCI)
+                ath_mci_cleanup(sc);
+
         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
                 if (ATH_TXQ_SETUP(sc, i))
                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 6a8fdf33a527..0e4fbb3bea33 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -16,6 +16,7 @@
 
 #include "hw.h"
 #include "hw-ops.h"
+#include <linux/export.h>
 
 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
                                         struct ath9k_tx_queue_info *qi)
@@ -759,7 +760,10 @@ bool ath9k_hw_intrpend(struct ath_hw *ah)
                 return true;
 
         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
-        if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
+
+        if (((host_isr & AR_INTR_MAC_IRQ) ||
+             (host_isr & AR_INTR_ASYNC_MASK_MCI)) &&
+            (host_isr != AR_INTR_SPURIOUS))
                 return true;
 
         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
@@ -797,6 +801,7 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
         u32 sync_default = AR_INTR_SYNC_DEFAULT;
+        u32 async_mask;
 
         if (!(ah->imask & ATH9K_INT_GLOBAL))
                 return;
@@ -811,13 +816,16 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
         if (AR_SREV_9340(ah))
                 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
 
+        async_mask = AR_INTR_MAC_IRQ;
+
+        if (ah->imask & ATH9K_INT_MCI)
+                async_mask |= AR_INTR_ASYNC_MASK_MCI;
+
         ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
         REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
         if (!AR_SREV_9100(ah)) {
-                REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
-                          AR_INTR_MAC_IRQ);
-                REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
-
+                REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask);
+                REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask);
 
                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
                 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index e43c41cff25b..7fbc4bdd4efe 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -118,7 +118,7 @@ void ath9k_ps_restore(struct ath_softc *sc)
         if (--sc->ps_usecount != 0)
                 goto unlock;
 
-        if (sc->ps_idle)
+        if (sc->ps_idle && (sc->ps_flags & PS_WAIT_FOR_TX_ACK))
                 mode = ATH9K_PM_FULL_SLEEP;
         else if (sc->ps_enabled &&
                  !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
@@ -286,7 +286,7 @@ static bool ath_complete_reset(struct ath_softc *sc, bool start)
                         ath_start_ani(common);
         }
 
-        if (ath9k_hw_ops(ah)->antdiv_comb_conf_get && sc->ant_rx != 3) {
+        if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) {
                 struct ath_hw_antcomb_conf div_ant_conf;
                 u8 lna_conf;
 
@@ -332,7 +332,8 @@ static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
                 hchan = ah->curchan;
         }
 
-        if (fastcc && !ath9k_hw_check_alive(ah))
+        if (fastcc && (ah->chip_fullsleep ||
+            !ath9k_hw_check_alive(ah)))
                 fastcc = false;
 
         if (!ath_prepare_reset(sc, retry_tx, flush))
@@ -561,7 +562,6 @@ void ath_ani_calibrate(unsigned long data)
         /* Long calibration runs independently of short calibration. */
         if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
                 longcal = true;
-                ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
                 common->ani.longcal_timer = timestamp;
         }
 
@@ -569,8 +569,6 @@ void ath_ani_calibrate(unsigned long data)
         if (!common->ani.caldone) {
                 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
                         shortcal = true;
-                        ath_dbg(common, ATH_DBG_ANI,
-                                "shortcal @%lu\n", jiffies);
                         common->ani.shortcal_timer = timestamp;
                         common->ani.resetcal_timer = timestamp;
                 }
@@ -584,8 +582,9 @@ void ath_ani_calibrate(unsigned long data)
         }
 
         /* Verify whether we must check ANI */
-        if ((timestamp - common->ani.checkani_timer) >=
-             ah->config.ani_poll_interval) {
+        if (sc->sc_ah->config.enable_ani
+            && (timestamp - common->ani.checkani_timer) >=
+            ah->config.ani_poll_interval) {
                 aniflag = true;
                 common->ani.checkani_timer = timestamp;
         }
@@ -605,6 +604,11 @@ void ath_ani_calibrate(unsigned long data)
                                                 ah->rxchainmask, longcal);
         }
 
+        ath_dbg(common, ATH_DBG_ANI,
+                "Calibration @%lu finished: %s %s %s, caldone: %s\n", jiffies,
+                longcal ? "long" : "", shortcal ? "short" : "",
+                aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
+
         ath9k_ps_restore(sc);
 
 set_timer:
@@ -640,9 +644,9 @@ static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
         spin_lock(&sc->nodes_lock);
         list_add(&an->list, &sc->nodes);
         spin_unlock(&sc->nodes_lock);
+#endif
         an->sta = sta;
         an->vif = vif;
-#endif
         if (sc->sc_flags & SC_OP_TXAGGR) {
                 ath_tx_node_init(sc, an);
                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
@@ -742,6 +746,9 @@ void ath9k_tasklet(unsigned long data)
                 if (status & ATH9K_INT_GENTIMER)
                         ath_gen_timer_isr(sc->sc_ah);
 
+        if (status & ATH9K_INT_MCI)
+                ath_mci_intr(sc);
+
 out:
         /* re-enable hardware interrupt */
         ath9k_hw_enable_interrupts(ah);
@@ -764,7 +771,8 @@ irqreturn_t ath_isr(int irq, void *dev)
                 ATH9K_INT_BMISS |               \
                 ATH9K_INT_CST |                 \
                 ATH9K_INT_TSFOOR |              \
-                ATH9K_INT_GENTIMER)
+                ATH9K_INT_GENTIMER |            \
+                ATH9K_INT_MCI)
 
         struct ath_softc *sc = dev;
         struct ath_hw *ah = sc->sc_ah;
@@ -882,82 +890,6 @@ chip_reset:
 #undef SCHED_INTR
 }
 
-static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
-{
-        struct ath_hw *ah = sc->sc_ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ieee80211_channel *channel = hw->conf.channel;
-        int r;
-
-        ath9k_ps_wakeup(sc);
-        spin_lock_bh(&sc->sc_pcu_lock);
-        atomic_set(&ah->intr_ref_cnt, -1);
-
-        ath9k_hw_configpcipowersave(ah, false);
-
-        if (!ah->curchan)
-                ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
-
-        r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
-        if (r) {
-                ath_err(common,
-                        "Unable to reset channel (%u MHz), reset status %d\n",
-                        channel->center_freq, r);
-        }
-
-        ath_complete_reset(sc, true);
-
-        /* Enable LED */
-        ath9k_hw_cfg_output(ah, ah->led_pin,
-                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
-        ath9k_hw_set_gpio(ah, ah->led_pin, 0);
-
-        spin_unlock_bh(&sc->sc_pcu_lock);
-
-        ath9k_ps_restore(sc);
-}
-
-void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
-{
-        struct ath_hw *ah = sc->sc_ah;
-        struct ieee80211_channel *channel = hw->conf.channel;
-        int r;
-
-        ath9k_ps_wakeup(sc);
-
-        ath_cancel_work(sc);
-
-        spin_lock_bh(&sc->sc_pcu_lock);
-
-        /*
-         * Keep the LED on when the radio is disabled
-         * during idle unassociated state.
-         */
-        if (!sc->ps_idle) {
-                ath9k_hw_set_gpio(ah, ah->led_pin, 1);
-                ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
-        }
-
-        ath_prepare_reset(sc, false, true);
-
-        if (!ah->curchan)
-                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
-
-        r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
-        if (r) {
-                ath_err(ath9k_hw_common(sc->sc_ah),
-                        "Unable to reset channel (%u MHz), reset status %d\n",
-                        channel->center_freq, r);
-        }
-
-        ath9k_hw_phy_disable(ah);
-
-        ath9k_hw_configpcipowersave(ah, true);
-
-        spin_unlock_bh(&sc->sc_pcu_lock);
-        ath9k_ps_restore(sc);
-}
-
 static int ath_reset(struct ath_softc *sc, bool retry_tx)
 {
         int r;
@@ -1093,6 +1025,9 @@ static int ath9k_start(struct ieee80211_hw *hw)
          * and then setup of the interrupt mask.
          */
         spin_lock_bh(&sc->sc_pcu_lock);
+
+        atomic_set(&ah->intr_ref_cnt, -1);
+
         r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
         if (r) {
                 ath_err(common,
@@ -1119,6 +1054,9 @@ static int ath9k_start(struct ieee80211_hw *hw)
         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
                 ah->imask |= ATH9K_INT_CST;
 
+        if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
+                ah->imask |= ATH9K_INT_MCI;
+
         sc->sc_flags &= ~SC_OP_INVALID;
         sc->sc_ah->is_monitoring = false;
 
@@ -1131,6 +1069,18 @@ static int ath9k_start(struct ieee80211_hw *hw)
                 goto mutex_unlock;
         }
 
+        if (ah->led_pin >= 0) {
+                ath9k_hw_cfg_output(ah, ah->led_pin,
+                                    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+                ath9k_hw_set_gpio(ah, ah->led_pin, 0);
+        }
+
+        /*
+         * Reset key cache to sane defaults (all entries cleared) instead of
+         * semi-random values after suspend/resume.
+         */
+        ath9k_cmn_init_crypto(sc->sc_ah);
+
         spin_unlock_bh(&sc->sc_pcu_lock);
 
         if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
@@ -1176,6 +1126,13 @@ static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
                 }
         }
 
+        /*
+         * Cannot tx while the hardware is in full sleep, it first needs a full
+         * chip reset to recover from that
+         */
+        if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP))
+                goto exit;
+
         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
                 /*
                  * We are using PS-Poll and mac80211 can request TX while in
@@ -1222,6 +1179,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
         struct ath_softc *sc = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
+        bool prev_idle;
 
         mutex_lock(&sc->mutex);
 
@@ -1252,35 +1210,45 @@ static void ath9k_stop(struct ieee80211_hw *hw)
          * before setting the invalid flag. */
         ath9k_hw_disable_interrupts(ah);
 
-        if (!(sc->sc_flags & SC_OP_INVALID)) {
-                ath_drain_all_txq(sc, false);
-                ath_stoprecv(sc);
-                ath9k_hw_phy_disable(ah);
-        } else
-                sc->rx.rxlink = NULL;
+        spin_unlock_bh(&sc->sc_pcu_lock);
+
+        /* we can now sync irq and kill any running tasklets, since we already
+         * disabled interrupts and not holding a spin lock */
+        synchronize_irq(sc->irq);
+        tasklet_kill(&sc->intr_tq);
+        tasklet_kill(&sc->bcon_tasklet);
+
+        prev_idle = sc->ps_idle;
+        sc->ps_idle = true;
+
+        spin_lock_bh(&sc->sc_pcu_lock);
+
+        if (ah->led_pin >= 0) {
+                ath9k_hw_set_gpio(ah, ah->led_pin, 1);
+                ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
+        }
+
+        ath_prepare_reset(sc, false, true);
 
         if (sc->rx.frag) {
                 dev_kfree_skb_any(sc->rx.frag);
                 sc->rx.frag = NULL;
         }
 
-        /* disable HAL and put h/w to sleep */
-        ath9k_hw_disable(ah);
+        if (!ah->curchan)
+                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
+
+        ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
+        ath9k_hw_phy_disable(ah);
 
-        spin_unlock_bh(&sc->sc_pcu_lock);
+        ath9k_hw_configpcipowersave(ah, true);
 
-        /* we can now sync irq and kill any running tasklets, since we already
-         * disabled interrupts and not holding a spin lock */
-        synchronize_irq(sc->irq);
-        tasklet_kill(&sc->intr_tq);
-        tasklet_kill(&sc->bcon_tasklet);
+        spin_unlock_bh(&sc->sc_pcu_lock);
 
         ath9k_ps_restore(sc);
 
-        sc->ps_idle = true;
-        ath_radio_disable(sc, hw);
-
         sc->sc_flags |= SC_OP_INVALID;
+        sc->ps_idle = prev_idle;
 
         mutex_unlock(&sc->mutex);
 
@@ -1620,8 +1588,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ieee80211_conf *conf = &hw->conf;
-        bool disable_radio = false;
 
+        ath9k_ps_wakeup(sc);
         mutex_lock(&sc->mutex);
 
         /*
@@ -1632,13 +1600,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
          */
         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
                 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
-                if (!sc->ps_idle) {
-                        ath_radio_enable(sc, hw);
-                        ath_dbg(common, ATH_DBG_CONFIG,
-                                "not-idle: enabling radio\n");
-                } else {
-                        disable_radio = true;
-                }
+                if (sc->ps_idle)
+                        ath_cancel_work(sc);
         }
 
         /*
@@ -1745,18 +1708,12 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
                 ath_dbg(common, ATH_DBG_CONFIG,
                         "Set power: %d\n", conf->power_level);
                 sc->config.txpowlimit = 2 * conf->power_level;
-                ath9k_ps_wakeup(sc);
                 ath9k_cmn_update_txpow(ah, sc->curtxpow,
                                        sc->config.txpowlimit, &sc->curtxpow);
-                ath9k_ps_restore(sc);
-        }
-
-        if (disable_radio) {
-                ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
-                ath_radio_disable(sc, hw);
         }
 
         mutex_unlock(&sc->mutex);
+        ath9k_ps_restore(sc);
 
         return 0;
 }
@@ -1916,7 +1873,8 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
         if (ath9k_modparam_nohwcrypt)
                 return -ENOSPC;
 
-        if (vif->type == NL80211_IFTYPE_ADHOC &&
+        if ((vif->type == NL80211_IFTYPE_ADHOC ||
+             vif->type == NL80211_IFTYPE_MESH_POINT) &&
             (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
              key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
@@ -2324,9 +2282,6 @@ static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
                 return;
         }
 
-        if (drop)
-                timeout = 1;
-
         for (j = 0; j < timeout; j++) {
                 bool npend = false;
 
@@ -2344,21 +2299,22 @@ static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
                 }
 
                 if (!npend)
-                    goto out;
+                    break;
         }
 
-        ath9k_ps_wakeup(sc);
-        spin_lock_bh(&sc->sc_pcu_lock);
-        drain_txq = ath_drain_all_txq(sc, false);
-        spin_unlock_bh(&sc->sc_pcu_lock);
+        if (drop) {
+                ath9k_ps_wakeup(sc);
+                spin_lock_bh(&sc->sc_pcu_lock);
+                drain_txq = ath_drain_all_txq(sc, false);
+                spin_unlock_bh(&sc->sc_pcu_lock);
 
-        if (!drain_txq)
-                ath_reset(sc, false);
+                if (!drain_txq)
+                        ath_reset(sc, false);
 
-        ath9k_ps_restore(sc);
-        ieee80211_wake_queues(hw);
+                ath9k_ps_restore(sc);
+                ieee80211_wake_queues(hw);
+        }
 
-out:
         ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
         mutex_unlock(&sc->mutex);
 }
diff --git a/drivers/net/wireless/ath/ath9k/mci.c b/drivers/net/wireless/ath/ath9k/mci.c
index 0fbb141bc302..691bf47906e2 100644
--- a/drivers/net/wireless/ath/ath9k/mci.c
+++ b/drivers/net/wireless/ath/ath9k/mci.c
@@ -14,6 +14,9 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+
 #include "ath9k.h"
 #include "mci.h"
 
@@ -181,8 +184,58 @@ static void ath_mci_update_scheme(struct ath_softc *sc)
         ath9k_btcoex_timer_resume(sc);
 }
 
-void ath_mci_process_profile(struct ath_softc *sc,
-                             struct ath_mci_profile_info *info)
+
+static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        u32 payload[4] = {0, 0, 0, 0};
+
+        switch (opcode) {
+        case MCI_GPM_BT_CAL_REQ:
+
+                ath_dbg(common, ATH_DBG_MCI, "MCI received BT_CAL_REQ\n");
+
+                if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
+                        ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL);
+                        ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
+                } else
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI State mismatches: %d\n",
+                                ar9003_mci_state(ah, MCI_STATE_BT, NULL));
+
+                break;
+
+        case MCI_GPM_BT_CAL_DONE:
+
+                ath_dbg(common, ATH_DBG_MCI, "MCI received BT_CAL_DONE\n");
+
+                if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_CAL)
+                        ath_dbg(common, ATH_DBG_MCI, "MCI error illegal!\n");
+                else
+                        ath_dbg(common, ATH_DBG_MCI, "MCI BT not in CAL state\n");
+
+                break;
+
+        case MCI_GPM_BT_CAL_GRANT:
+
+                ath_dbg(common, ATH_DBG_MCI, "MCI received BT_CAL_GRANT\n");
+
+                /* Send WLAN_CAL_DONE for now */
+                ath_dbg(common, ATH_DBG_MCI, "MCI send WLAN_CAL_DONE\n");
+                MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
+                ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
+                                        16, false, true);
+                break;
+
+        default:
+                ath_dbg(common, ATH_DBG_MCI, "MCI Unknown GPM CAL message\n");
+                break;
+        }
+}
+
+static void ath_mci_process_profile(struct ath_softc *sc,
+                                    struct ath_mci_profile_info *info)
 {
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath_btcoex *btcoex = &sc->btcoex;
@@ -208,8 +261,8 @@ void ath_mci_process_profile(struct ath_softc *sc,
         ath_mci_update_scheme(sc);
 }
 
-void ath_mci_process_status(struct ath_softc *sc,
-                            struct ath_mci_profile_status *status)
+static void ath_mci_process_status(struct ath_softc *sc,
+                                   struct ath_mci_profile_status *status)
 {
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath_btcoex *btcoex = &sc->btcoex;
@@ -252,3 +305,369 @@ void ath_mci_process_status(struct ath_softc *sc,
         if (old_num_mgmt != mci->num_mgmt)
                 ath_mci_update_scheme(sc);
 }
+
+static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_mci_profile_info profile_info;
+        struct ath_mci_profile_status profile_status;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        u32 version;
+        u8 major;
+        u8 minor;
+        u32 seq_num;
+
+        switch (opcode) {
+
+        case MCI_GPM_COEX_VERSION_QUERY:
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Recv GPM COEX Version Query.\n");
+                version = ar9003_mci_state(ah,
+                                MCI_STATE_SEND_WLAN_COEX_VERSION, NULL);
+                break;
+
+        case MCI_GPM_COEX_VERSION_RESPONSE:
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Recv GPM COEX Version Response.\n");
+                major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
+                minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI BT Coex version: %d.%d\n", major, minor);
+                version = (major << 8) + minor;
+                version = ar9003_mci_state(ah,
+                          MCI_STATE_SET_BT_COEX_VERSION, &version);
+                break;
+
+        case MCI_GPM_COEX_STATUS_QUERY:
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Recv GPM COEX Status Query = 0x%02x.\n",
+                        *(rx_payload + MCI_GPM_COEX_B_WLAN_BITMAP));
+                ar9003_mci_state(ah,
+                MCI_STATE_SEND_WLAN_CHANNELS, NULL);
+                break;
+
+        case MCI_GPM_COEX_BT_PROFILE_INFO:
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Recv GPM Coex BT profile info\n");
+                memcpy(&profile_info,
+                       (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
+
+                if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN)
+                    || (profile_info.type >=
+                                            MCI_GPM_COEX_PROFILE_MAX)) {
+
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "illegal profile type = %d,"
+                                "state = %d\n", profile_info.type,
+                                profile_info.start);
+                        break;
+                }
+
+                ath_mci_process_profile(sc, &profile_info);
+                break;
+
+        case MCI_GPM_COEX_BT_STATUS_UPDATE:
+                profile_status.is_link = *(rx_payload +
+                                           MCI_GPM_COEX_B_STATUS_TYPE);
+                profile_status.conn_handle = *(rx_payload +
+                                               MCI_GPM_COEX_B_STATUS_LINKID);
+                profile_status.is_critical = *(rx_payload +
+                                               MCI_GPM_COEX_B_STATUS_STATE);
+
+                seq_num = *((u32 *)(rx_payload + 12));
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI Recv GPM COEX BT_Status_Update: "
+                        "is_link=%d, linkId=%d, state=%d, SEQ=%d\n",
+                        profile_status.is_link, profile_status.conn_handle,
+                        profile_status.is_critical, seq_num);
+
+                ath_mci_process_status(sc, &profile_status);
+                break;
+
+        default:
+                ath_dbg(common, ATH_DBG_MCI,
+                "MCI Unknown GPM COEX message = 0x%02x\n", opcode);
+                break;
+        }
+}
+
+static int ath_mci_buf_alloc(struct ath_softc *sc, struct ath_mci_buf *buf)
+{
+        int error = 0;
+
+        buf->bf_addr = dma_alloc_coherent(sc->dev, buf->bf_len,
+                                          &buf->bf_paddr, GFP_KERNEL);
+
+        if (buf->bf_addr == NULL) {
+                error = -ENOMEM;
+                goto fail;
+        }
+
+        return 0;
+
+fail:
+        memset(buf, 0, sizeof(*buf));
+        return error;
+}
+
+static void ath_mci_buf_free(struct ath_softc *sc, struct ath_mci_buf *buf)
+{
+        if (buf->bf_addr) {
+                dma_free_coherent(sc->dev, buf->bf_len, buf->bf_addr,
+                                                        buf->bf_paddr);
+                memset(buf, 0, sizeof(*buf));
+        }
+}
+
+int ath_mci_setup(struct ath_softc *sc)
+{
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_mci_coex *mci = &sc->mci_coex;
+        int error = 0;
+
+        mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE;
+
+        if (ath_mci_buf_alloc(sc, &mci->sched_buf)) {
+                ath_dbg(common, ATH_DBG_FATAL, "MCI buffer alloc failed\n");
+                error = -ENOMEM;
+                goto fail;
+        }
+
+        mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
+
+        memset(mci->sched_buf.bf_addr, MCI_GPM_RSVD_PATTERN,
+                                                mci->sched_buf.bf_len);
+
+        mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
+        mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr +
+                                                        mci->sched_buf.bf_len;
+        mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
+
+        /* initialize the buffer */
+        memset(mci->gpm_buf.bf_addr, MCI_GPM_RSVD_PATTERN, mci->gpm_buf.bf_len);
+
+        ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
+                         mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
+                         mci->sched_buf.bf_paddr);
+fail:
+        return error;
+}
+
+void ath_mci_cleanup(struct ath_softc *sc)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_mci_coex *mci = &sc->mci_coex;
+
+        /*
+         * both schedule and gpm buffers will be released
+         */
+        ath_mci_buf_free(sc, &mci->sched_buf);
+        ar9003_mci_cleanup(ah);
+}
+
+void ath_mci_intr(struct ath_softc *sc)
+{
+        struct ath_mci_coex *mci = &sc->mci_coex;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        u32 mci_int, mci_int_rxmsg;
+        u32 offset, subtype, opcode;
+        u32 *pgpm;
+        u32 more_data = MCI_GPM_MORE;
+        bool skip_gpm = false;
+
+        ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
+
+        if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) {
+
+                ar9003_mci_state(sc->sc_ah, MCI_STATE_INIT_GPM_OFFSET, NULL);
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI interrupt but MCI disabled\n");
+
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI interrupt: intr = 0x%x, intr_rxmsg = 0x%x\n",
+                        mci_int, mci_int_rxmsg);
+                return;
+        }
+
+        if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
+                u32 payload[4] = { 0xffffffff, 0xffffffff,
+                                   0xffffffff, 0xffffff00};
+
+                /*
+                 * The following REMOTE_RESET and SYS_WAKING used to sent
+                 * only when BT wake up. Now they are always sent, as a
+                 * recovery method to reset BT MCI's RX alignment.
+                 */
+                ath_dbg(common, ATH_DBG_MCI, "MCI interrupt send REMOTE_RESET\n");
+
+                ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
+                                        payload, 16, true, false);
+                ath_dbg(common, ATH_DBG_MCI, "MCI interrupt send SYS_WAKING\n");
+                ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
+                                        NULL, 0, true, false);
+
+                mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
+                ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE, NULL);
+
+                /*
+                 * always do this for recovery and 2G/5G toggling and LNA_TRANS
+                 */
+                ath_dbg(common, ATH_DBG_MCI, "MCI Set BT state to AWAKE.\n");
+                ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL);
+        }
+
+        /* Processing SYS_WAKING/SYS_SLEEPING */
+        if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
+                mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
+
+                if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_SLEEP) {
+
+                        if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL)
+                                        == MCI_BT_SLEEP)
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI BT stays in sleep mode\n");
+                        else {
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI Set BT state to AWAKE.\n");
+                                ar9003_mci_state(ah,
+                                                 MCI_STATE_SET_BT_AWAKE, NULL);
+                        }
+                } else
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI BT stays in AWAKE mode.\n");
+        }
+
+        if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
+
+                mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
+
+                if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
+
+                        if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL)
+                                        == MCI_BT_AWAKE)
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI BT stays in AWAKE mode.\n");
+                        else {
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI SetBT state to SLEEP\n");
+                                ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP,
+                                                 NULL);
+                        }
+                } else
+                        ath_dbg(common, ATH_DBG_MCI,
+                                "MCI BT stays in SLEEP mode\n");
+        }
+
+        if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
+            (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
+
+                ath_dbg(common, ATH_DBG_MCI, "MCI RX broken, skip GPM msgs\n");
+                ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL);
+                skip_gpm = true;
+        }
+
+        if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
+
+                mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
+                offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET,
+                                          NULL);
+        }
+
+        if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
+
+                mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
+
+                while (more_data == MCI_GPM_MORE) {
+
+                        pgpm = mci->gpm_buf.bf_addr;
+                        offset = ar9003_mci_state(ah,
+                                        MCI_STATE_NEXT_GPM_OFFSET, &more_data);
+
+                        if (offset == MCI_GPM_INVALID)
+                                break;
+
+                        pgpm += (offset >> 2);
+
+                        /*
+                         * The first dword is timer.
+                         * The real data starts from 2nd dword.
+                         */
+
+                        subtype = MCI_GPM_TYPE(pgpm);
+                        opcode = MCI_GPM_OPCODE(pgpm);
+
+                        if (!skip_gpm) {
+
+                                if (MCI_GPM_IS_CAL_TYPE(subtype))
+                                        ath_mci_cal_msg(sc, subtype,
+                                                        (u8 *) pgpm);
+                                else {
+                                        switch (subtype) {
+                                        case MCI_GPM_COEX_AGENT:
+                                                ath_mci_msg(sc, opcode,
+                                                            (u8 *) pgpm);
+                                                break;
+                                        default:
+                                                break;
+                                        }
+                                }
+                        }
+                        MCI_GPM_RECYCLE(pgpm);
+                }
+        }
+
+        if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
+
+                if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
+                        mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
+
+                if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO) {
+                        mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
+                        ath_dbg(common, ATH_DBG_MCI, "MCI LNA_INFO\n");
+                }
+
+                if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
+
+                        int value_dbm = ar9003_mci_state(ah,
+                                        MCI_STATE_CONT_RSSI_POWER, NULL);
+
+                        mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
+
+                        if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL))
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI CONT_INFO: "
+                                        "(tx) pri = %d, pwr = %d dBm\n",
+                                        ar9003_mci_state(ah,
+                                                MCI_STATE_CONT_PRIORITY, NULL),
+                                        value_dbm);
+                        else
+                                ath_dbg(common, ATH_DBG_MCI,
+                                        "MCI CONT_INFO:"
+                                        "(rx) pri = %d,pwr = %d dBm\n",
+                                        ar9003_mci_state(ah,
+                                                MCI_STATE_CONT_PRIORITY, NULL),
+                                        value_dbm);
+                }
+
+                if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK) {
+                        mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
+                        ath_dbg(common, ATH_DBG_MCI, "MCI CONT_NACK\n");
+                }
+
+                if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST) {
+                        mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
+                        ath_dbg(common, ATH_DBG_MCI, "MCI CONT_RST\n");
+                }
+        }
+
+        if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
+            (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT))
+                mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
+                             AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
+
+        if (mci_int_rxmsg & 0xfffffffe)
+                ath_dbg(common, ATH_DBG_MCI,
+                        "MCI not processed mci_int_rxmsg = 0x%x\n",
+                        mci_int_rxmsg);
+}
diff --git a/drivers/net/wireless/ath/ath9k/mci.h b/drivers/net/wireless/ath/ath9k/mci.h
index 9590c61822d1..29e3e51d078f 100644
--- a/drivers/net/wireless/ath/ath9k/mci.h
+++ b/drivers/net/wireless/ath/ath9k/mci.h
@@ -17,6 +17,9 @@
 #ifndef MCI_H
 #define MCI_H
 
+#define ATH_MCI_SCHED_BUF_SIZE          (16 * 16) /* 16 entries, 4 dword each */
+#define ATH_MCI_GPM_MAX_ENTRY           16
+#define ATH_MCI_GPM_BUF_SIZE            (ATH_MCI_GPM_MAX_ENTRY * 16)
 #define ATH_MCI_DEF_BT_PERIOD           40
 #define ATH_MCI_BDR_DUTY_CYCLE          20
 #define ATH_MCI_MAX_DUTY_CYCLE          90
@@ -110,9 +113,22 @@ struct ath_mci_profile {
         u8 num_bdr;
 };
 
+
+struct ath_mci_buf {
+        void *bf_addr;          /* virtual addr of desc */
+        dma_addr_t bf_paddr;    /* physical addr of buffer */
+        u32 bf_len;             /* len of data */
+};
+
+struct ath_mci_coex {
+        atomic_t mci_cal_flag;
+        struct ath_mci_buf sched_buf;
+        struct ath_mci_buf gpm_buf;
+        u32 bt_cal_start;
+};
+
 void ath_mci_flush_profile(struct ath_mci_profile *mci);
-void ath_mci_process_profile(struct ath_softc *sc,
-                             struct ath_mci_profile_info *info);
-void ath_mci_process_status(struct ath_softc *sc,
-                            struct ath_mci_profile_status *status);
+int ath_mci_setup(struct ath_softc *sc);
+void ath_mci_cleanup(struct ath_softc *sc);
+void ath_mci_intr(struct ath_softc *sc);
 #endif
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index edb0b4b3da3a..a439edc5dc06 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -18,6 +18,7 @@
 #include <linux/pci.h>
 #include <linux/pci-aspm.h>
 #include <linux/ath9k_platform.h>
+#include <linux/module.h>
 #include "ath9k.h"
 
 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
@@ -306,12 +307,11 @@ static int ath_pci_suspend(struct device *device)
         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
         struct ath_softc *sc = hw->priv;
 
-        ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
-
         /* The device has to be moved to FULLSLEEP forcibly.
          * Otherwise the chip never moved to full sleep,
          * when no interface is up.
          */
+        ath9k_hw_disable(sc->sc_ah);
         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 
         return 0;
@@ -320,8 +320,6 @@ static int ath_pci_suspend(struct device *device)
 static int ath_pci_resume(struct device *device)
 {
         struct pci_dev *pdev = to_pci_dev(device);
-        struct ieee80211_hw *hw = pci_get_drvdata(pdev);
-        struct ath_softc *sc = hw->priv;
         u32 val;
 
         /*
@@ -333,22 +331,6 @@ static int ath_pci_resume(struct device *device)
         if ((val & 0x0000ff00) != 0)
                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 
-        ath9k_ps_wakeup(sc);
-        /* Enable LED */
-        ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
-                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
-        ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
-
-          /*
-           * Reset key cache to sane defaults (all entries cleared) instead of
-           * semi-random values after suspend/resume.
-           */
-        ath9k_cmn_init_crypto(sc->sc_ah);
-        ath9k_ps_restore(sc);
-
-        sc->ps_idle = true;
-        ath_radio_disable(sc, hw);
-
         return 0;
 }
 
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index 8448281dd069..528d5f3e868c 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -16,6 +16,7 @@
  */
 
 #include <linux/slab.h>
+#include <linux/export.h>
 
 #include "ath9k.h"
 
@@ -1270,7 +1271,9 @@ static void ath_rc_init(struct ath_softc *sc,
 
         ath_rc_priv->max_valid_rate = k;
         ath_rc_sort_validrates(rate_table, ath_rc_priv);
-        ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
+        ath_rc_priv->rate_max_phy = (k > 4) ?
+                                        ath_rc_priv->valid_rate_index[k-4] :
+                                        ath_rc_priv->valid_rate_index[k-1];
         ath_rc_priv->rate_table = rate_table;
 
         ath_dbg(common, ATH_DBG_CONFIG,
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index 67b862cdae6d..ad5176de07dc 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -475,7 +475,6 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
 
         return rfilt;
 
-#undef RX_FILTER_PRESERVE
 }
 
 int ath_startrecv(struct ath_softc *sc)
@@ -1824,6 +1823,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                 hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
                 rxs = IEEE80211_SKB_RXCB(hdr_skb);
                 if (ieee80211_is_beacon(hdr->frame_control) &&
+                    !is_zero_ether_addr(common->curbssid) &&
                     !compare_ether_addr(hdr->addr3, common->curbssid))
                         rs.is_mybeacon = true;
                 else
@@ -1838,11 +1838,6 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                 if (sc->sc_flags & SC_OP_RXFLUSH)
                         goto requeue_drop_frag;
 
-                retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
-                                                 rxs, &decrypt_error);
-                if (retval)
-                        goto requeue_drop_frag;
-
                 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
                 if (rs.rs_tstamp > tsf_lower &&
                     unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
@@ -1852,6 +1847,11 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                     unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
                         rxs->mactime += 0x100000000ULL;
 
+                retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
+                                                 rxs, &decrypt_error);
+                if (retval)
+                        goto requeue_drop_frag;
+
                 /* Ensure we always have an skb to requeue once we are done
                  * processing the current buffer's skb */
                 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
@@ -1923,15 +1923,20 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                         skb = hdr_skb;
                 }
 
-                /*
-                 * change the default rx antenna if rx diversity chooses the
-                 * other antenna 3 times in a row.
-                 */
-                if (sc->rx.defant != rs.rs_antenna) {
-                        if (++sc->rx.rxotherant >= 3)
-                                ath_setdefantenna(sc, rs.rs_antenna);
-                } else {
-                        sc->rx.rxotherant = 0;
+
+                if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
+
+                        /*
+                         * change the default rx antenna if rx diversity
+                         * chooses the other antenna 3 times in a row.
+                         */
+                        if (sc->rx.defant != rs.rs_antenna) {
+                                if (++sc->rx.rxotherant >= 3)
+                                        ath_setdefantenna(sc, rs.rs_antenna);
+                        } else {
+                                sc->rx.rxotherant = 0;
+                        }
+
                 }
 
                 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 45910975d853..6e2f18861f5d 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -1006,6 +1006,8 @@ enum {
 #define AR_INTR_ASYNC_MASK                       (AR_SREV_9340(ah) ? 0x4018 : 0x4030)
 #define AR_INTR_ASYNC_MASK_GPIO                  0xFFFC0000
 #define AR_INTR_ASYNC_MASK_GPIO_S                18
+#define AR_INTR_ASYNC_MASK_MCI                   0x00000080
+#define AR_INTR_ASYNC_MASK_MCI_S                 7
 
 #define AR_INTR_SYNC_MASK                        (AR_SREV_9340(ah) ? 0x401c : 0x4034)
 #define AR_INTR_SYNC_MASK_GPIO                   0xFFFC0000
@@ -1013,6 +1015,14 @@ enum {
 
 #define AR_INTR_ASYNC_CAUSE_CLR                  (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
 #define AR_INTR_ASYNC_CAUSE                      (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
+#define AR_INTR_ASYNC_CAUSE_MCI                  0x00000080
+#define AR_INTR_ASYNC_USED                       (AR_INTR_MAC_IRQ | \
+                                                  AR_INTR_ASYNC_CAUSE_MCI)
+
+/* Asynchronous Interrupt Enable Register */
+#define AR_INTR_ASYNC_ENABLE_MCI         0x00000080
+#define AR_INTR_ASYNC_ENABLE_MCI_S       7
+
 
 #define AR_INTR_ASYNC_ENABLE                     (AR_SREV_9340(ah) ? 0x4024 : 0x403c)
 #define AR_INTR_ASYNC_ENABLE_GPIO                0xFFFC0000
@@ -1269,6 +1279,8 @@ enum {
 #define AR_RTC_INTR_MASK \
         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)
 
+#define AR_RTC_KEEP_AWAKE       0x7034
+
 /* RTC_DERIVED_* - only for AR9100 */
 
 #define AR_RTC_DERIVED_CLK \
@@ -1555,6 +1567,8 @@ enum {
 #define AR_DIAG_FRAME_NV0           0x00020000
 #define AR_DIAG_OBS_PT_SEL1         0x000C0000
 #define AR_DIAG_OBS_PT_SEL1_S       18
+#define AR_DIAG_OBS_PT_SEL2         0x08000000
+#define AR_DIAG_OBS_PT_SEL2_S       27
 #define AR_DIAG_FORCE_RX_CLEAR      0x00100000 /* force rx_clear high */
 #define AR_DIAG_IGNORE_VIRT_CS      0x00200000
 #define AR_DIAG_FORCE_CH_IDLE_HIGH  0x00400000
@@ -1929,37 +1943,277 @@ enum {
 #define AR_PHY_AGC_CONTROL_YCOK_MAX_S           6
 
 /* MCI Registers */
-#define AR_MCI_INTERRUPT_RX_MSG_EN              0x183c
-#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET    0x00000001
-#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S  0
-#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL     0x00000002
-#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S   1
-#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK       0x00000004
-#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S     2
-#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO       0x00000008
-#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S     3
-#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST        0x00000010
-#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S      4
-#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO       0x00000020
-#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S     5
-#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT         0x00000040
-#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S       6
-#define AR_MCI_INTERRUPT_RX_MSG_GPM             0x00000100
-#define AR_MCI_INTERRUPT_RX_MSG_GPM_S           8
-#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO        0x00000200
-#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S      9
-#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING    0x00000400
-#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S  10
-#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING      0x00000800
-#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S    11
-#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE        0x00001000
-#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S      12
-#define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO  | \
+
+#define AR_MCI_COMMAND0                         0x1800
+#define AR_MCI_COMMAND0_HEADER                  0xFF
+#define AR_MCI_COMMAND0_HEADER_S                0
+#define AR_MCI_COMMAND0_LEN                     0x1f00
+#define AR_MCI_COMMAND0_LEN_S                   8
+#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP       0x2000
+#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S     13
+
+#define AR_MCI_COMMAND1                         0x1804
+
+#define AR_MCI_COMMAND2                         0x1808
+#define AR_MCI_COMMAND2_RESET_TX                0x01
+#define AR_MCI_COMMAND2_RESET_TX_S              0
+#define AR_MCI_COMMAND2_RESET_RX                0x02
+#define AR_MCI_COMMAND2_RESET_RX_S              1
+#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES     0x3FC
+#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S   2
+#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP        0x400
+#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S      10
+
+#define AR_MCI_RX_CTRL                          0x180c
+
+#define AR_MCI_TX_CTRL                          0x1810
+/* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */
+#define AR_MCI_TX_CTRL_CLK_DIV                  0x03
+#define AR_MCI_TX_CTRL_CLK_DIV_S                0
+#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE       0x04
+#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S     2
+#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ         0xFFFFF8
+#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S       3
+#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM          0xF000000
+#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S        24
+
+#define AR_MCI_MSG_ATTRIBUTES_TABLE                     0x1814
+#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM            0xFFFF
+#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S          0
+#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR         0xFFFF0000
+#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S       16
+
+#define AR_MCI_SCHD_TABLE_0                             0x1818
+#define AR_MCI_SCHD_TABLE_1                             0x181c
+#define AR_MCI_GPM_0                                    0x1820
+#define AR_MCI_GPM_1                                    0x1824
+#define AR_MCI_GPM_WRITE_PTR                            0xFFFF0000
+#define AR_MCI_GPM_WRITE_PTR_S                          16
+#define AR_MCI_GPM_BUF_LEN                              0x0000FFFF
+#define AR_MCI_GPM_BUF_LEN_S                            0
+
+#define AR_MCI_INTERRUPT_RAW                            0x1828
+#define AR_MCI_INTERRUPT_EN                             0x182c
+#define AR_MCI_INTERRUPT_SW_MSG_DONE                    0x00000001
+#define AR_MCI_INTERRUPT_SW_MSG_DONE_S                  0
+#define AR_MCI_INTERRUPT_CPU_INT_MSG                    0x00000002
+#define AR_MCI_INTERRUPT_CPU_INT_MSG_S                  1
+#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL                  0x00000004
+#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S                2
+#define AR_MCI_INTERRUPT_RX_INVALID_HDR                 0x00000008
+#define AR_MCI_INTERRUPT_RX_INVALID_HDR_S               3
+#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL                 0x00000010
+#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S               4
+#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL                 0x00000020
+#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S               5
+#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL                 0x00000080
+#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S               7
+#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL                 0x00000100
+#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S               8
+#define AR_MCI_INTERRUPT_RX_MSG                         0x00000200
+#define AR_MCI_INTERRUPT_RX_MSG_S                       9
+#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE            0x00000400
+#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S          10
+#define AR_MCI_INTERRUPT_BT_PRI                         0x07fff800
+#define AR_MCI_INTERRUPT_BT_PRI_S                       11
+#define AR_MCI_INTERRUPT_BT_PRI_THRESH                  0x08000000
+#define AR_MCI_INTERRUPT_BT_PRI_THRESH_S                27
+#define AR_MCI_INTERRUPT_BT_FREQ                        0x10000000
+#define AR_MCI_INTERRUPT_BT_FREQ_S                      28
+#define AR_MCI_INTERRUPT_BT_STOMP                       0x20000000
+#define AR_MCI_INTERRUPT_BT_STOMP_S                     29
+#define AR_MCI_INTERRUPT_BB_AIC_IRQ                     0x40000000
+#define AR_MCI_INTERRUPT_BB_AIC_IRQ_S                   30
+#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT              0x80000000
+#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S            31
+
+#define AR_MCI_INTERRUPT_DEFAULT    (AR_MCI_INTERRUPT_SW_MSG_DONE         | \
+                                     AR_MCI_INTERRUPT_RX_INVALID_HDR      | \
+                                     AR_MCI_INTERRUPT_RX_HW_MSG_FAIL      | \
+                                     AR_MCI_INTERRUPT_RX_SW_MSG_FAIL      | \
+                                     AR_MCI_INTERRUPT_TX_HW_MSG_FAIL      | \
+                                     AR_MCI_INTERRUPT_TX_SW_MSG_FAIL      | \
+                                     AR_MCI_INTERRUPT_RX_MSG              | \
+                                     AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \
+                                     AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)
+
+#define AR_MCI_INTERRUPT_MSG_FAIL_MASK (AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \
+                                        AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \
+                                        AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \
+                                        AR_MCI_INTERRUPT_TX_SW_MSG_FAIL)
+
+#define AR_MCI_REMOTE_CPU_INT                           0x1830
+#define AR_MCI_REMOTE_CPU_INT_EN                        0x1834
+#define AR_MCI_INTERRUPT_RX_MSG_RAW                     0x1838
+#define AR_MCI_INTERRUPT_RX_MSG_EN                      0x183c
+#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET            0x00000001
+#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S          0
+#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL             0x00000002
+#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S           1
+#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK               0x00000004
+#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S             2
+#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO               0x00000008
+#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S             3
+#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST                0x00000010
+#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S              4
+#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO               0x00000020
+#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S             5
+#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT                 0x00000040
+#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S               6
+#define AR_MCI_INTERRUPT_RX_MSG_GPM                     0x00000100
+#define AR_MCI_INTERRUPT_RX_MSG_GPM_S                   8
+#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO                0x00000200
+#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S              9
+#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING            0x00000400
+#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S          10
+#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING              0x00000800
+#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S            11
+#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE                0x00001000
+#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S              12
+#define AR_MCI_INTERRUPT_RX_HW_MSG_MASK  (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO  | \
                                           AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL| \
                                           AR_MCI_INTERRUPT_RX_MSG_LNA_INFO   | \
                                           AR_MCI_INTERRUPT_RX_MSG_CONT_NACK  | \
                                           AR_MCI_INTERRUPT_RX_MSG_CONT_INFO  | \
                                           AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
 
+#define AR_MCI_INTERRUPT_RX_MSG_DEFAULT (AR_MCI_INTERRUPT_RX_MSG_GPM     | \
+                                         AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET| \
+                                         AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING  | \
+                                         AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING| \
+                                         AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO   | \
+                                         AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \
+                                         AR_MCI_INTERRUPT_RX_MSG_LNA_INFO    | \
+                                         AR_MCI_INTERRUPT_RX_MSG_CONT_NACK   | \
+                                         AR_MCI_INTERRUPT_RX_MSG_CONT_INFO   | \
+                                         AR_MCI_INTERRUPT_RX_MSG_CONT_RST    | \
+                                         AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)
+
+#define AR_MCI_CPU_INT                                  0x1840
+
+#define AR_MCI_RX_STATUS                        0x1844
+#define AR_MCI_RX_LAST_SCHD_MSG_INDEX           0x00000F00
+#define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S         8
+#define AR_MCI_RX_REMOTE_SLEEP                  0x00001000
+#define AR_MCI_RX_REMOTE_SLEEP_S                12
+#define AR_MCI_RX_MCI_CLK_REQ                   0x00002000
+#define AR_MCI_RX_MCI_CLK_REQ_S                 13
+
+#define AR_MCI_CONT_STATUS                      0x1848
+#define AR_MCI_CONT_RSSI_POWER                  0x000000FF
+#define AR_MCI_CONT_RSSI_POWER_S                0
+#define AR_MCI_CONT_RRIORITY                    0x0000FF00
+#define AR_MCI_CONT_RRIORITY_S                  8
+#define AR_MCI_CONT_TXRX                        0x00010000
+#define AR_MCI_CONT_TXRX_S                      16
+
+#define AR_MCI_BT_PRI0                          0x184c
+#define AR_MCI_BT_PRI1                          0x1850
+#define AR_MCI_BT_PRI2                          0x1854
+#define AR_MCI_BT_PRI3                          0x1858
+#define AR_MCI_BT_PRI                           0x185c
+#define AR_MCI_WL_FREQ0                         0x1860
+#define AR_MCI_WL_FREQ1                         0x1864
+#define AR_MCI_WL_FREQ2                         0x1868
+#define AR_MCI_GAIN                             0x186c
+#define AR_MCI_WBTIMER1                         0x1870
+#define AR_MCI_WBTIMER2                         0x1874
+#define AR_MCI_WBTIMER3                         0x1878
+#define AR_MCI_WBTIMER4                         0x187c
+#define AR_MCI_MAXGAIN                          0x1880
+#define AR_MCI_HW_SCHD_TBL_CTL                  0x1884
+#define AR_MCI_HW_SCHD_TBL_D0                   0x1888
+#define AR_MCI_HW_SCHD_TBL_D1                   0x188c
+#define AR_MCI_HW_SCHD_TBL_D2                   0x1890
+#define AR_MCI_HW_SCHD_TBL_D3                   0x1894
+#define AR_MCI_TX_PAYLOAD0                      0x1898
+#define AR_MCI_TX_PAYLOAD1                      0x189c
+#define AR_MCI_TX_PAYLOAD2                      0x18a0
+#define AR_MCI_TX_PAYLOAD3                      0x18a4
+#define AR_BTCOEX_WBTIMER                       0x18a8
+
+#define AR_BTCOEX_CTRL                                  0x18ac
+#define AR_BTCOEX_CTRL_AR9462_MODE                      0x00000001
+#define AR_BTCOEX_CTRL_AR9462_MODE_S                    0
+#define AR_BTCOEX_CTRL_WBTIMER_EN                       0x00000002
+#define AR_BTCOEX_CTRL_WBTIMER_EN_S                     1
+#define AR_BTCOEX_CTRL_MCI_MODE_EN                      0x00000004
+#define AR_BTCOEX_CTRL_MCI_MODE_EN_S                    2
+#define AR_BTCOEX_CTRL_LNA_SHARED                       0x00000008
+#define AR_BTCOEX_CTRL_LNA_SHARED_S                     3
+#define AR_BTCOEX_CTRL_PA_SHARED                        0x00000010
+#define AR_BTCOEX_CTRL_PA_SHARED_S                      4
+#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN           0x00000020
+#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S         5
+#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN        0x00000040
+#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S      6
+#define AR_BTCOEX_CTRL_NUM_ANTENNAS                     0x00000180
+#define AR_BTCOEX_CTRL_NUM_ANTENNAS_S                   7
+#define AR_BTCOEX_CTRL_RX_CHAIN_MASK                    0x00000E00
+#define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S                  9
+#define AR_BTCOEX_CTRL_AGGR_THRESH                      0x00007000
+#define AR_BTCOEX_CTRL_AGGR_THRESH_S                    12
+#define AR_BTCOEX_CTRL_1_CHAIN_BCN                      0x00080000
+#define AR_BTCOEX_CTRL_1_CHAIN_BCN_S                    19
+#define AR_BTCOEX_CTRL_1_CHAIN_ACK                      0x00100000
+#define AR_BTCOEX_CTRL_1_CHAIN_ACK_S                    20
+#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN                   0x1FE00000
+#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S                 28
+#define AR_BTCOEX_CTRL_REDUCE_TXPWR                     0x20000000
+#define AR_BTCOEX_CTRL_REDUCE_TXPWR_S                   29
+#define AR_BTCOEX_CTRL_SPDT_ENABLE_10                   0x40000000
+#define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S                 30
+#define AR_BTCOEX_CTRL_SPDT_POLARITY                    0x80000000
+#define AR_BTCOEX_CTRL_SPDT_POLARITY_S                  31
+
+#define AR_BTCOEX_WL_WEIGHTS0                           0x18b0
+#define AR_BTCOEX_WL_WEIGHTS1                           0x18b4
+#define AR_BTCOEX_WL_WEIGHTS2                           0x18b8
+#define AR_BTCOEX_WL_WEIGHTS3                           0x18bc
+#define AR_BTCOEX_MAX_TXPWR(_x)                         (0x18c0 + ((_x) << 2))
+#define AR_BTCOEX_WL_LNA                                0x1940
+#define AR_BTCOEX_RFGAIN_CTRL                           0x1944
+
+#define AR_BTCOEX_CTRL2                                 0x1948
+#define AR_BTCOEX_CTRL2_TXPWR_THRESH                    0x0007F800
+#define AR_BTCOEX_CTRL2_TXPWR_THRESH_S                  11
+#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK                   0x00380000
+#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S                 19
+#define AR_BTCOEX_CTRL2_RX_DEWEIGHT                     0x00400000
+#define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S                   22
+#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL                    0x00800000
+#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S                  23
+#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL                  0x01000000
+#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S                24
+#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE         0x02000000
+#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S       25
+
+#define AR_BTCOEX_CTRL_SPDT_ENABLE          0x00000001
+#define AR_BTCOEX_CTRL_SPDT_ENABLE_S        0
+#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL     0x00000002
+#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S   1
+#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT   0x00000004
+#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2
+#define AR_GLB_WLAN_UART_INTF_EN            0x00020000
+#define AR_GLB_WLAN_UART_INTF_EN_S          17
+#define AR_GLB_DS_JTAG_DISABLE              0x00040000
+#define AR_GLB_DS_JTAG_DISABLE_S            18
+
+#define AR_BTCOEX_RC                    0x194c
+#define AR_BTCOEX_MAX_RFGAIN(_x)        (0x1950 + ((_x) << 2))
+#define AR_BTCOEX_DBG                   0x1a50
+#define AR_MCI_LAST_HW_MSG_HDR          0x1a54
+#define AR_MCI_LAST_HW_MSG_BDY          0x1a58
+
+#define AR_MCI_SCHD_TABLE_2             0x1a5c
+#define AR_MCI_SCHD_TABLE_2_MEM_BASED   0x00000001
+#define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0
+#define AR_MCI_SCHD_TABLE_2_HW_BASED    0x00000002
+#define AR_MCI_SCHD_TABLE_2_HW_BASED_S  1
+
+#define AR_BTCOEX_CTRL3               0x1a60
+#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT       0x00000fff
+#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S     0
+
 
 #endif
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 55d077e7135d..23e80e63bca9 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -53,7 +53,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
                             int tx_flags, struct ath_txq *txq);
 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
                                 struct ath_txq *txq, struct list_head *bf_q,
-                                struct ath_tx_status *ts, int txok, int sendbar);
+                                struct ath_tx_status *ts, int txok);
 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
                              struct list_head *head, bool internal);
 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
@@ -150,6 +150,12 @@ static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
         return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
 }
 
+static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
+{
+        ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
+                           seqno << IEEE80211_SEQ_SEQ_SHIFT);
+}
+
 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 {
         struct ath_txq *txq = tid->ac->txq;
@@ -158,28 +164,33 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
         struct list_head bf_head;
         struct ath_tx_status ts;
         struct ath_frame_info *fi;
+        bool sendbar = false;
 
         INIT_LIST_HEAD(&bf_head);
 
         memset(&ts, 0, sizeof(ts));
-        spin_lock_bh(&txq->axq_lock);
 
         while ((skb = __skb_dequeue(&tid->buf_q))) {
                 fi = get_frame_info(skb);
                 bf = fi->bf;
 
-                spin_unlock_bh(&txq->axq_lock);
                 if (bf && fi->retries) {
                         list_add_tail(&bf->list, &bf_head);
                         ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
-                        ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
+                        ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
+                        sendbar = true;
                 } else {
                         ath_tx_send_normal(sc, txq, NULL, skb);
                 }
-                spin_lock_bh(&txq->axq_lock);
         }
 
-        spin_unlock_bh(&txq->axq_lock);
+        if (tid->baw_head == tid->baw_tail) {
+                tid->state &= ~AGGR_ADDBA_COMPLETE;
+                tid->state &= ~AGGR_CLEANUP;
+        }
+
+        if (sendbar)
+                ath_send_bar(tid, tid->seq_start);
 }
 
 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
@@ -195,6 +206,8 @@ static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
         while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
                 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
                 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
+                if (tid->bar_index >= 0)
+                        tid->bar_index--;
         }
 }
 
@@ -238,9 +251,7 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
                 bf = fi->bf;
 
                 if (!bf) {
-                        spin_unlock(&txq->axq_lock);
                         ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
-                        spin_lock(&txq->axq_lock);
                         continue;
                 }
 
@@ -249,24 +260,26 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
                 if (fi->retries)
                         ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
 
-                spin_unlock(&txq->axq_lock);
-                ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
-                spin_lock(&txq->axq_lock);
+                ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
         }
 
         tid->seq_next = tid->seq_start;
         tid->baw_tail = tid->baw_head;
+        tid->bar_index = -1;
 }
 
 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
-                             struct sk_buff *skb)
+                             struct sk_buff *skb, int count)
 {
         struct ath_frame_info *fi = get_frame_info(skb);
         struct ath_buf *bf = fi->bf;
         struct ieee80211_hdr *hdr;
+        int prev = fi->retries;
 
         TX_STAT_INC(txq->axq_qnum, a_retries);
-        if (fi->retries++ > 0)
+        fi->retries += count;
+
+        if (prev > 0)
                 return;
 
         hdr = (struct ieee80211_hdr *)skb->data;
@@ -365,7 +378,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
         struct list_head bf_head;
         struct sk_buff_head bf_pending;
-        u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
+        u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
         u32 ba[WME_BA_BMP_SIZE >> 5];
         int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
         bool rc_update = true;
@@ -374,6 +387,8 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         int nframes;
         u8 tidno;
         bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
+        int i, retries;
+        int bar_index = -1;
 
         skb = bf->bf_mpdu;
         hdr = (struct ieee80211_hdr *)skb->data;
@@ -382,6 +397,10 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
 
         memcpy(rates, tx_info->control.rates, sizeof(rates));
 
+        retries = ts->ts_longretry + 1;
+        for (i = 0; i < ts->ts_rateindex; i++)
+                retries += rates[i].count;
+
         rcu_read_lock();
 
         sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
@@ -395,8 +414,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                         if (!bf->bf_stale || bf_next != NULL)
                                 list_move_tail(&bf->list, &bf_head);
 
-                        ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
-                                0, 0);
+                        ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
 
                         bf = bf_next;
                 }
@@ -406,6 +424,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         an = (struct ath_node *)sta->drv_priv;
         tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
         tid = ATH_AN_2_TID(an, tidno);
+        seq_first = tid->seq_start;
 
         /*
          * The hardware occasionally sends a tx status for the wrong TID.
@@ -455,25 +474,25 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 } else if (!isaggr && txok) {
                         /* transmit completion */
                         acked_cnt++;
+                } else if ((tid->state & AGGR_CLEANUP) || !retry) {
+                        /*
+                         * cleanup in progress, just fail
+                         * the un-acked sub-frames
+                         */
+                        txfail = 1;
+                } else if (flush) {
+                        txpending = 1;
+                } else if (fi->retries < ATH_MAX_SW_RETRIES) {
+                        if (txok || !an->sleeping)
+                                ath_tx_set_retry(sc, txq, bf->bf_mpdu,
+                                                 retries);
+
+                        txpending = 1;
                 } else {
-                        if ((tid->state & AGGR_CLEANUP) || !retry) {
-                                /*
-                                 * cleanup in progress, just fail
-                                 * the un-acked sub-frames
-                                 */
-                                txfail = 1;
-                        } else if (flush) {
-                                txpending = 1;
-                        } else if (fi->retries < ATH_MAX_SW_RETRIES) {
-                                if (txok || !an->sleeping)
-                                        ath_tx_set_retry(sc, txq, bf->bf_mpdu);
-
-                                txpending = 1;
-                        } else {
-                                txfail = 1;
-                                sendbar = 1;
-                                txfail_cnt++;
-                        }
+                        txfail = 1;
+                        txfail_cnt++;
+                        bar_index = max_t(int, bar_index,
+                                ATH_BA_INDEX(seq_first, seqno));
                 }
 
                 /*
@@ -490,9 +509,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                          * complete the acked-ones/xretried ones; update
                          * block-ack window
                          */
-                        spin_lock_bh(&txq->axq_lock);
                         ath_tx_update_baw(sc, tid, seqno);
-                        spin_unlock_bh(&txq->axq_lock);
 
                         if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
                                 memcpy(tx_info->control.rates, rates, sizeof(rates));
@@ -501,33 +518,30 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                         }
 
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
-                                !txfail, sendbar);
+                                !txfail);
                 } else {
                         /* retry the un-acked ones */
-                        if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
-                                if (bf->bf_next == NULL && bf_last->bf_stale) {
-                                        struct ath_buf *tbf;
-
-                                        tbf = ath_clone_txbuf(sc, bf_last);
-                                        /*
-                                         * Update tx baw and complete the
-                                         * frame with failed status if we
-                                         * run out of tx buf.
-                                         */
-                                        if (!tbf) {
-                                                spin_lock_bh(&txq->axq_lock);
-                                                ath_tx_update_baw(sc, tid, seqno);
-                                                spin_unlock_bh(&txq->axq_lock);
-
-                                                ath_tx_complete_buf(sc, bf, txq,
-                                                                    &bf_head,
-                                                                    ts, 0,
-                                                                    !flush);
-                                                break;
-                                        }
-
-                                        fi->bf = tbf;
+                        if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
+                            bf->bf_next == NULL && bf_last->bf_stale) {
+                                struct ath_buf *tbf;
+
+                                tbf = ath_clone_txbuf(sc, bf_last);
+                                /*
+                                 * Update tx baw and complete the
+                                 * frame with failed status if we
+                                 * run out of tx buf.
+                                 */
+                                if (!tbf) {
+                                        ath_tx_update_baw(sc, tid, seqno);
+
+                                        ath_tx_complete_buf(sc, bf, txq,
+                                                            &bf_head, ts, 0);
+                                        bar_index = max_t(int, bar_index,
+                                                ATH_BA_INDEX(seq_first, seqno));
+                                        break;
                                 }
+
+                                fi->bf = tbf;
                         }
 
                         /*
@@ -540,12 +554,18 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 bf = bf_next;
         }
 
+        if (bar_index >= 0) {
+                u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
+                ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
+                if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
+                        tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
+        }
+
         /* prepend un-acked frames to the beginning of the pending frame queue */
         if (!skb_queue_empty(&bf_pending)) {
                 if (an->sleeping)
                         ieee80211_sta_set_buffered(sta, tid->tidno, true);
 
-                spin_lock_bh(&txq->axq_lock);
                 skb_queue_splice(&bf_pending, &tid->buf_q);
                 if (!an->sleeping) {
                         ath_tx_queue_tid(txq, tid);
@@ -553,18 +573,11 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                         if (ts->ts_status & ATH9K_TXERR_FILT)
                                 tid->ac->clear_ps_filter = true;
                 }
-                spin_unlock_bh(&txq->axq_lock);
         }
 
-        if (tid->state & AGGR_CLEANUP) {
+        if (tid->state & AGGR_CLEANUP)
                 ath_tx_flush_tid(sc, tid);
 
-                if (tid->baw_head == tid->baw_tail) {
-                        tid->state &= ~AGGR_ADDBA_COMPLETE;
-                        tid->state &= ~AGGR_CLEANUP;
-                }
-        }
-
         rcu_read_unlock();
 
         if (needreset) {
@@ -618,24 +631,26 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
         max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
 
         for (i = 0; i < 4; i++) {
-                if (rates[i].count) {
-                        int modeidx;
-                        if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
-                                legacy = 1;
-                                break;
-                        }
+                int modeidx;
 
-                        if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
-                                modeidx = MCS_HT40;
-                        else
-                                modeidx = MCS_HT20;
-
-                        if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
-                                modeidx++;
+                if (!rates[i].count)
+                        continue;
 
-                        frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
-                        max_4ms_framelen = min(max_4ms_framelen, frmlen);
+                if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
+                        legacy = 1;
+                        break;
                 }
+
+                if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
+                        modeidx = MCS_HT40;
+                else
+                        modeidx = MCS_HT20;
+
+                if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
+                        modeidx++;
+
+                frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
+                max_4ms_framelen = min(max_4ms_framelen, frmlen);
         }
 
         /*
@@ -771,8 +786,6 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
 
                 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
                 seqno = bf->bf_state.seqno;
-                if (!bf_first)
-                        bf_first = bf;
 
                 /* do not step over block-ack window */
                 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
@@ -780,6 +793,21 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                         break;
                 }
 
+                if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
+                        struct ath_tx_status ts = {};
+                        struct list_head bf_head;
+
+                        INIT_LIST_HEAD(&bf_head);
+                        list_add(&bf->list, &bf_head);
+                        __skb_unlink(skb, &tid->buf_q);
+                        ath_tx_update_baw(sc, tid, seqno);
+                        ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
+                        continue;
+                }
+
+                if (!bf_first)
+                        bf_first = bf;
+
                 if (!rl) {
                         aggr_limit = ath_lookup_rate(sc, bf, tid);
                         rl = 1;
@@ -1122,6 +1150,7 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
         txtid->state |= AGGR_ADDBA_PROGRESS;
         txtid->paused = true;
         *ssn = txtid->seq_start = txtid->seq_next;
+        txtid->bar_index = -1;
 
         memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
         txtid->baw_head = txtid->baw_tail = 0;
@@ -1156,9 +1185,9 @@ void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
                 txtid->state |= AGGR_CLEANUP;
         else
                 txtid->state &= ~AGGR_ADDBA_COMPLETE;
-        spin_unlock_bh(&txq->axq_lock);
 
         ath_tx_flush_tid(sc, txtid);
+        spin_unlock_bh(&txq->axq_lock);
 }
 
 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
@@ -1400,8 +1429,6 @@ static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
 
 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
                                struct list_head *list, bool retry_tx)
-        __releases(txq->axq_lock)
-        __acquires(txq->axq_lock)
 {
         struct ath_buf *bf, *lastbf;
         struct list_head bf_head;
@@ -1428,13 +1455,11 @@ static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
                 if (bf_is_ampdu_not_probing(bf))
                         txq->axq_ampdu_depth--;
 
-                spin_unlock_bh(&txq->axq_lock);
                 if (bf_isampdu(bf))
                         ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
                                              retry_tx);
                 else
-                        ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
-                spin_lock_bh(&txq->axq_lock);
+                        ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
         }
 }
 
@@ -1561,11 +1586,9 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
                                 break;
                 }
 
-                if (!list_empty(&ac->tid_q)) {
-                        if (!ac->sched) {
-                                ac->sched = true;
-                                list_add_tail(&ac->list, &txq->axq_acq);
-                        }
+                if (!list_empty(&ac->tid_q) && !ac->sched) {
+                        ac->sched = true;
+                        list_add_tail(&ac->list, &txq->axq_acq);
                 }
 
                 if (ac == last_ac ||
@@ -1708,10 +1731,6 @@ static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
         list_add_tail(&bf->list, &bf_head);
         bf->bf_state.bf_type = 0;
 
-        /* update starting sequence number for subsequent ADDBA request */
-        if (tid)
-                INCR(tid->seq_start, IEEE80211_SEQ_MAX);
-
         bf->bf_lastbf = bf;
         ath_tx_fill_desc(sc, bf, txq, fi->framelen);
         ath_tx_txqaddbuf(sc, txq, &bf_head, false);
@@ -1819,7 +1838,6 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
         struct ath_buf *bf;
         u8 tidno;
 
-        spin_lock_bh(&txctl->txq->axq_lock);
         if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
                 ieee80211_is_data_qos(hdr->frame_control)) {
                 tidno = ieee80211_get_qos_ctl(hdr)[0] &
@@ -1838,7 +1856,7 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
         } else {
                 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
                 if (!bf)
-                        goto out;
+                        return;
 
                 bf->bf_state.bfs_paprd = txctl->paprd;
 
@@ -1847,9 +1865,6 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
 
                 ath_tx_send_normal(sc, txctl->txq, tid, skb);
         }
-
-out:
-        spin_unlock_bh(&txctl->txq->axq_lock);
 }
 
 /* Upon failure caller should free skb */
@@ -1916,9 +1931,11 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
                 ieee80211_stop_queue(sc->hw, q);
                 txq->stopped = 1;
         }
-        spin_unlock_bh(&txq->axq_lock);
 
         ath_tx_start_dma(sc, skb, txctl);
+
+        spin_unlock_bh(&txq->axq_lock);
+
         return 0;
 }
 
@@ -1937,9 +1954,6 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 
         ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
 
-        if (tx_flags & ATH_TX_BAR)
-                tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
-
         if (!(tx_flags & ATH_TX_ERROR))
                 /* Frame was ACKed */
                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
@@ -1955,7 +1969,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
                 skb_pull(skb, padsize);
         }
 
-        if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
+        if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
                 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
                 ath_dbg(common, ATH_DBG_PS,
                         "Going back to sleep after having received TX status (0x%lx)\n",
@@ -1967,7 +1981,6 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 
         q = skb_get_queue_mapping(skb);
         if (txq == sc->tx.txq_map[q]) {
-                spin_lock_bh(&txq->axq_lock);
                 if (WARN_ON(--txq->pending_frames < 0))
                         txq->pending_frames = 0;
 
@@ -1975,7 +1988,6 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
                         ieee80211_wake_queue(sc->hw, q);
                         txq->stopped = 0;
                 }
-                spin_unlock_bh(&txq->axq_lock);
         }
 
         ieee80211_tx_status(hw, skb);
@@ -1983,16 +1995,13 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 
 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
                                 struct ath_txq *txq, struct list_head *bf_q,
-                                struct ath_tx_status *ts, int txok, int sendbar)
+                                struct ath_tx_status *ts, int txok)
 {
         struct sk_buff *skb = bf->bf_mpdu;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
         unsigned long flags;
         int tx_flags = 0;
 
-        if (sendbar)
-                tx_flags = ATH_TX_BAR;
-
         if (!txok)
                 tx_flags |= ATH_TX_ERROR;
 
@@ -2084,8 +2093,6 @@ static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
                                   struct ath_tx_status *ts, struct ath_buf *bf,
                                   struct list_head *bf_head)
-        __releases(txq->axq_lock)
-        __acquires(txq->axq_lock)
 {
         int txok;
 
@@ -2095,16 +2102,12 @@ static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
         if (bf_is_ampdu_not_probing(bf))
                 txq->axq_ampdu_depth--;
 
-        spin_unlock_bh(&txq->axq_lock);
-
         if (!bf_isampdu(bf)) {
                 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
-                ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
+                ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
         } else
                 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
 
-        spin_lock_bh(&txq->axq_lock);
-
         if (sc->sc_flags & SC_OP_TXAGGR)
                 ath_txq_schedule(sc, txq);
 }
diff --git a/drivers/net/wireless/ath/carl9170/fw.c b/drivers/net/wireless/ath/carl9170/fw.c
index f4cae1cccbff..cba9d0435dc4 100644
--- a/drivers/net/wireless/ath/carl9170/fw.c
+++ b/drivers/net/wireless/ath/carl9170/fw.c
@@ -23,6 +23,7 @@
 #include <linux/kernel.h>
 #include <linux/firmware.h>
 #include <linux/crc32.h>
+#include <linux/module.h>
 #include "carl9170.h"
 #include "fwcmd.h"
 #include "version.h"
diff --git a/drivers/net/wireless/ath/carl9170/tx.c b/drivers/net/wireless/ath/carl9170/tx.c
index 59472e1605cd..d19a9ee9d057 100644
--- a/drivers/net/wireless/ath/carl9170/tx.c
+++ b/drivers/net/wireless/ath/carl9170/tx.c
@@ -314,7 +314,7 @@ static void carl9170_tx_release(struct kref *ref)
                          *    feedback either [CTL_REQ_TX_STATUS not set]
                          */
 
-                        dev_kfree_skb_any(skb);
+                        ieee80211_free_txskb(ar->hw, skb);
                         return;
                 } else {
                         /*
@@ -1432,7 +1432,7 @@ void carl9170_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
 
 err_free:
         ar->tx_dropped++;
-        dev_kfree_skb_any(skb);
+        ieee80211_free_txskb(ar->hw, skb);
 }
 
 void carl9170_tx_scheduler(struct ar9170 *ar)
diff --git a/drivers/net/wireless/ath/debug.c b/drivers/net/wireless/ath/debug.c
index 5367b1086e09..508eccf5d982 100644
--- a/drivers/net/wireless/ath/debug.c
+++ b/drivers/net/wireless/ath/debug.c
@@ -14,6 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/export.h>
 #include "ath.h"
 
 const char *ath_opmode_to_string(enum nl80211_iftype opmode)
diff --git a/drivers/net/wireless/ath/hw.c b/drivers/net/wireless/ath/hw.c
index 3f508e59f146..19befb331073 100644
--- a/drivers/net/wireless/ath/hw.c
+++ b/drivers/net/wireless/ath/hw.c
@@ -14,6 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/export.h>
 #include <asm/unaligned.h>
 
 #include "ath.h"
diff --git a/drivers/net/wireless/ath/key.c b/drivers/net/wireless/ath/key.c
index 17b0efd86f9a..4cf7c5eb4813 100644
--- a/drivers/net/wireless/ath/key.c
+++ b/drivers/net/wireless/ath/key.c
@@ -15,6 +15,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <linux/export.h>
 #include <asm/unaligned.h>
 #include <net/mac80211.h>
 
diff --git a/drivers/net/wireless/ath/regd.c b/drivers/net/wireless/ath/regd.c
index f1be57f0f5bb..10dea37431b3 100644
--- a/drivers/net/wireless/ath/regd.c
+++ b/drivers/net/wireless/ath/regd.c
@@ -15,11 +15,14 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/export.h>
 #include <net/cfg80211.h>
 #include <net/mac80211.h>
 #include "regd.h"
 #include "regd_common.h"
 
+static int __ath_regd_init(struct ath_regulatory *reg);
+
 /*
  * This is a set of common rules used by our world regulatory domains.
  * We have 12 world regulatory domains. To save space we consolidate
@@ -346,10 +349,26 @@ static void ath_reg_apply_world_flags(struct wiphy *wiphy,
         }
 }
 
+static u16 ath_regd_find_country_by_name(char *alpha2)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(allCountries); i++) {
+                if (!memcmp(allCountries[i].isoName, alpha2, 2))
+                        return allCountries[i].countryCode;
+        }
+
+        return -1;
+}
+
 int ath_reg_notifier_apply(struct wiphy *wiphy,
                            struct regulatory_request *request,
                            struct ath_regulatory *reg)
 {
+        struct ath_common *common = container_of(reg, struct ath_common,
+                                                 regulatory);
+        u16 country_code;
+
         /* We always apply this */
         ath_reg_apply_radar_flags(wiphy);
 
@@ -362,14 +381,37 @@ int ath_reg_notifier_apply(struct wiphy *wiphy,
                 return 0;
 
         switch (request->initiator) {
-        case NL80211_REGDOM_SET_BY_DRIVER:
         case NL80211_REGDOM_SET_BY_CORE:
+                /*
+                 * If common->reg_world_copy is world roaming it means we *were*
+                 * world roaming... so we now have to restore that data.
+                 */
+                if (!ath_is_world_regd(&common->reg_world_copy))
+                        break;
+
+                memcpy(reg, &common->reg_world_copy,
+                       sizeof(struct ath_regulatory));
+                break;
+        case NL80211_REGDOM_SET_BY_DRIVER:
         case NL80211_REGDOM_SET_BY_USER:
                 break;
         case NL80211_REGDOM_SET_BY_COUNTRY_IE:
-                if (ath_is_world_regd(reg))
-                        ath_reg_apply_world_flags(wiphy, request->initiator,
-                                                  reg);
+                if (!ath_is_world_regd(reg))
+                        break;
+
+                country_code = ath_regd_find_country_by_name(request->alpha2);
+                if (country_code == (u16) -1)
+                        break;
+
+                reg->current_rd = COUNTRY_ERD_FLAG;
+                reg->current_rd |= country_code;
+
+                printk(KERN_DEBUG "ath: regdomain 0x%0x updated by CountryIE\n",
+                        reg->current_rd);
+                __ath_regd_init(reg);
+
+                ath_reg_apply_world_flags(wiphy, request->initiator, reg);
+
                 break;
         }
 
@@ -507,11 +549,7 @@ static void ath_regd_sanitize(struct ath_regulatory *reg)
         reg->current_rd = 0x64;
 }
 
-int
-ath_regd_init(struct ath_regulatory *reg,
-              struct wiphy *wiphy,
-              int (*reg_notifier)(struct wiphy *wiphy,
-                                  struct regulatory_request *request))
+static int __ath_regd_init(struct ath_regulatory *reg)
 {
         struct country_code_to_enum_rd *country = NULL;
         u16 regdmn;
@@ -582,7 +620,29 @@ ath_regd_init(struct ath_regulatory *reg,
         printk(KERN_DEBUG "ath: Regpair used: 0x%0x\n",
                 reg->regpair->regDmnEnum);
 
+        return 0;
+}
+
+int
+ath_regd_init(struct ath_regulatory *reg,
+              struct wiphy *wiphy,
+              int (*reg_notifier)(struct wiphy *wiphy,
+                                  struct regulatory_request *request))
+{
+        struct ath_common *common = container_of(reg, struct ath_common,
+                                                 regulatory);
+        int r;
+
+        r = __ath_regd_init(reg);
+        if (r)
+                return r;
+
+        if (ath_is_world_regd(reg))
+                memcpy(&common->reg_world_copy, reg,
+                       sizeof(struct ath_regulatory));
+
         ath_regd_init_wiphy(reg, wiphy, reg_notifier);
+
         return 0;
 }
 EXPORT_SYMBOL(ath_regd_init);