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path: root/drivers/net/wireless/ath/ath5k/desc.h
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Diffstat (limited to 'drivers/net/wireless/ath/ath5k/desc.h')
-rw-r--r--drivers/net/wireless/ath/ath5k/desc.h124
1 files changed, 83 insertions, 41 deletions
diff --git a/drivers/net/wireless/ath/ath5k/desc.h b/drivers/net/wireless/ath/ath5k/desc.h
index cfd529b548f3..8d6c01a49ea3 100644
--- a/drivers/net/wireless/ath/ath5k/desc.h
+++ b/drivers/net/wireless/ath/ath5k/desc.h
@@ -20,25 +20,30 @@
20 * RX/TX descriptor structures 20 * RX/TX descriptor structures
21 */ 21 */
22 22
23/* 23/**
24 * Common hardware RX control descriptor 24 * struct ath5k_hw_rx_ctl - Common hardware RX control descriptor
25 * @rx_control_0: RX control word 0
26 * @rx_control_1: RX control word 1
25 */ 27 */
26struct ath5k_hw_rx_ctl { 28struct ath5k_hw_rx_ctl {
27 u32 rx_control_0; /* RX control word 0 */ 29 u32 rx_control_0;
28 u32 rx_control_1; /* RX control word 1 */ 30 u32 rx_control_1;
29} __packed __aligned(4); 31} __packed __aligned(4);
30 32
31/* RX control word 1 fields/flags */ 33/* RX control word 1 fields/flags */
32#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff /* data buffer length */ 34#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff /* data buffer length */
33#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 /* RX interrupt request */ 35#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 /* RX interrupt request */
34 36
35/* 37/**
36 * Common hardware RX status descriptor 38 * struct ath5k_hw_rx_status - Common hardware RX status descriptor
39 * @rx_status_0: RX status word 0
40 * @rx_status_1: RX status word 1
41 *
37 * 5210, 5211 and 5212 differ only in the fields and flags defined below 42 * 5210, 5211 and 5212 differ only in the fields and flags defined below
38 */ 43 */
39struct ath5k_hw_rx_status { 44struct ath5k_hw_rx_status {
40 u32 rx_status_0; /* RX status word 0 */ 45 u32 rx_status_0;
41 u32 rx_status_1; /* RX status word 1 */ 46 u32 rx_status_1;
42} __packed __aligned(4); 47} __packed __aligned(4);
43 48
44/* 5210/5211 */ 49/* 5210/5211 */
@@ -98,17 +103,36 @@ struct ath5k_hw_rx_status {
98 103
99/** 104/**
100 * enum ath5k_phy_error_code - PHY Error codes 105 * enum ath5k_phy_error_code - PHY Error codes
106 * @AR5K_RX_PHY_ERROR_UNDERRUN: Transmit underrun, [5210] No error
107 * @AR5K_RX_PHY_ERROR_TIMING: Timing error
108 * @AR5K_RX_PHY_ERROR_PARITY: Illegal parity
109 * @AR5K_RX_PHY_ERROR_RATE: Illegal rate
110 * @AR5K_RX_PHY_ERROR_LENGTH: Illegal length
111 * @AR5K_RX_PHY_ERROR_RADAR: Radar detect, [5210] 64 QAM rate
112 * @AR5K_RX_PHY_ERROR_SERVICE: Illegal service
113 * @AR5K_RX_PHY_ERROR_TOR: Transmit override receive
114 * @AR5K_RX_PHY_ERROR_OFDM_TIMING: OFDM Timing error [5212+]
115 * @AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY: OFDM Signal parity error [5212+]
116 * @AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL: OFDM Illegal rate [5212+]
117 * @AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL: OFDM Illegal length [5212+]
118 * @AR5K_RX_PHY_ERROR_OFDM_POWER_DROP: OFDM Power drop [5212+]
119 * @AR5K_RX_PHY_ERROR_OFDM_SERVICE: OFDM Service (?) [5212+]
120 * @AR5K_RX_PHY_ERROR_OFDM_RESTART: OFDM Restart (?) [5212+]
121 * @AR5K_RX_PHY_ERROR_CCK_TIMING: CCK Timing error [5212+]
122 * @AR5K_RX_PHY_ERROR_CCK_HEADER_CRC: Header CRC error [5212+]
123 * @AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL: Illegal rate [5212+]
124 * @AR5K_RX_PHY_ERROR_CCK_SERVICE: CCK Service (?) [5212+]
125 * @AR5K_RX_PHY_ERROR_CCK_RESTART: CCK Restart (?) [5212+]
101 */ 126 */
102enum ath5k_phy_error_code { 127enum ath5k_phy_error_code {
103 AR5K_RX_PHY_ERROR_UNDERRUN = 0, /* Transmit underrun, [5210] No error */ 128 AR5K_RX_PHY_ERROR_UNDERRUN = 0,
104 AR5K_RX_PHY_ERROR_TIMING = 1, /* Timing error */ 129 AR5K_RX_PHY_ERROR_TIMING = 1,
105 AR5K_RX_PHY_ERROR_PARITY = 2, /* Illegal parity */ 130 AR5K_RX_PHY_ERROR_PARITY = 2,
106 AR5K_RX_PHY_ERROR_RATE = 3, /* Illegal rate */ 131 AR5K_RX_PHY_ERROR_RATE = 3,
107 AR5K_RX_PHY_ERROR_LENGTH = 4, /* Illegal length */ 132 AR5K_RX_PHY_ERROR_LENGTH = 4,
108 AR5K_RX_PHY_ERROR_RADAR = 5, /* Radar detect, [5210] 64 QAM rate */ 133 AR5K_RX_PHY_ERROR_RADAR = 5,
109 AR5K_RX_PHY_ERROR_SERVICE = 6, /* Illegal service */ 134 AR5K_RX_PHY_ERROR_SERVICE = 6,
110 AR5K_RX_PHY_ERROR_TOR = 7, /* Transmit override receive */ 135 AR5K_RX_PHY_ERROR_TOR = 7,
111 /* these are specific to the 5212 */
112 AR5K_RX_PHY_ERROR_OFDM_TIMING = 17, 136 AR5K_RX_PHY_ERROR_OFDM_TIMING = 17,
113 AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY = 18, 137 AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY = 18,
114 AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL = 19, 138 AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL = 19,
@@ -123,12 +147,14 @@ enum ath5k_phy_error_code {
123 AR5K_RX_PHY_ERROR_CCK_RESTART = 31, 147 AR5K_RX_PHY_ERROR_CCK_RESTART = 31,
124}; 148};
125 149
126/* 150/**
127 * 5210/5211 hardware 2-word TX control descriptor 151 * struct ath5k_hw_2w_tx_ctl - 5210/5211 hardware 2-word TX control descriptor
152 * @tx_control_0: TX control word 0
153 * @tx_control_1: TX control word 1
128 */ 154 */
129struct ath5k_hw_2w_tx_ctl { 155struct ath5k_hw_2w_tx_ctl {
130 u32 tx_control_0; /* TX control word 0 */ 156 u32 tx_control_0;
131 u32 tx_control_1; /* TX control word 1 */ 157 u32 tx_control_1;
132} __packed __aligned(4); 158} __packed __aligned(4);
133 159
134/* TX control word 0 fields/flags */ 160/* TX control word 0 fields/flags */
@@ -177,14 +203,18 @@ struct ath5k_hw_2w_tx_ctl {
177#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 4 203#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 4
178#define AR5K_AR5211_TX_DESC_FRAME_TYPE_PRESP 4 204#define AR5K_AR5211_TX_DESC_FRAME_TYPE_PRESP 4
179 205
180/* 206/**
181 * 5212 hardware 4-word TX control descriptor 207 * struct ath5k_hw_4w_tx_ctl - 5212 hardware 4-word TX control descriptor
208 * @tx_control_0: TX control word 0
209 * @tx_control_1: TX control word 1
210 * @tx_control_2: TX control word 2
211 * @tx_control_3: TX control word 3
182 */ 212 */
183struct ath5k_hw_4w_tx_ctl { 213struct ath5k_hw_4w_tx_ctl {
184 u32 tx_control_0; /* TX control word 0 */ 214 u32 tx_control_0;
185 u32 tx_control_1; /* TX control word 1 */ 215 u32 tx_control_1;
186 u32 tx_control_2; /* TX control word 2 */ 216 u32 tx_control_2;
187 u32 tx_control_3; /* TX control word 3 */ 217 u32 tx_control_3;
188} __packed __aligned(4); 218} __packed __aligned(4);
189 219
190/* TX control word 0 fields/flags */ 220/* TX control word 0 fields/flags */
@@ -238,12 +268,14 @@ struct ath5k_hw_4w_tx_ctl {
238#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 /* RTS or CTS rate */ 268#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 /* RTS or CTS rate */
239#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 269#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20
240 270
241/* 271/**
242 * Common TX status descriptor 272 * struct ath5k_hw_tx_status - Common TX status descriptor
273 * @tx_status_0: TX status word 0
274 * @tx_status_1: TX status word 1
243 */ 275 */
244struct ath5k_hw_tx_status { 276struct ath5k_hw_tx_status {
245 u32 tx_status_0; /* TX status word 0 */ 277 u32 tx_status_0;
246 u32 tx_status_1; /* TX status word 1 */ 278 u32 tx_status_1;
247} __packed __aligned(4); 279} __packed __aligned(4);
248 280
249/* TX status word 0 fields/flags */ 281/* TX status word 0 fields/flags */
@@ -276,37 +308,47 @@ struct ath5k_hw_tx_status {
276#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212 0x00800000 /* [5212] compression status */ 308#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212 0x00800000 /* [5212] compression status */
277#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212 0x01000000 /* [5212] transmit antenna */ 309#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212 0x01000000 /* [5212] transmit antenna */
278 310
279/* 311/**
280 * 5210/5211 hardware TX descriptor 312 * struct ath5k_hw_5210_tx_desc - 5210/5211 hardware TX descriptor
313 * @tx_ctl: The &struct ath5k_hw_2w_tx_ctl
314 * @tx_stat: The &struct ath5k_hw_tx_status
281 */ 315 */
282struct ath5k_hw_5210_tx_desc { 316struct ath5k_hw_5210_tx_desc {
283 struct ath5k_hw_2w_tx_ctl tx_ctl; 317 struct ath5k_hw_2w_tx_ctl tx_ctl;
284 struct ath5k_hw_tx_status tx_stat; 318 struct ath5k_hw_tx_status tx_stat;
285} __packed __aligned(4); 319} __packed __aligned(4);
286 320
287/* 321/**
288 * 5212 hardware TX descriptor 322 * struct ath5k_hw_5212_tx_desc - 5212 hardware TX descriptor
323 * @tx_ctl: The &struct ath5k_hw_4w_tx_ctl
324 * @tx_stat: The &struct ath5k_hw_tx_status
289 */ 325 */
290struct ath5k_hw_5212_tx_desc { 326struct ath5k_hw_5212_tx_desc {
291 struct ath5k_hw_4w_tx_ctl tx_ctl; 327 struct ath5k_hw_4w_tx_ctl tx_ctl;
292 struct ath5k_hw_tx_status tx_stat; 328 struct ath5k_hw_tx_status tx_stat;
293} __packed __aligned(4); 329} __packed __aligned(4);
294 330
295/* 331/**
296 * Common hardware RX descriptor 332 * struct ath5k_hw_all_rx_desc - Common hardware RX descriptor
333 * @rx_ctl: The &struct ath5k_hw_rx_ctl
334 * @rx_stat: The &struct ath5k_hw_rx_status
297 */ 335 */
298struct ath5k_hw_all_rx_desc { 336struct ath5k_hw_all_rx_desc {
299 struct ath5k_hw_rx_ctl rx_ctl; 337 struct ath5k_hw_rx_ctl rx_ctl;
300 struct ath5k_hw_rx_status rx_stat; 338 struct ath5k_hw_rx_status rx_stat;
301} __packed __aligned(4); 339} __packed __aligned(4);
302 340
303/* 341/**
304 * Atheros hardware DMA descriptor 342 * struct ath5k_desc - Atheros hardware DMA descriptor
343 * @ds_link: Physical address of the next descriptor
344 * @ds_data: Physical address of data buffer (skb)
345 * @ud: Union containing hw_5xxx_tx_desc structs and hw_all_rx_desc
346 *
305 * This is read and written to by the hardware 347 * This is read and written to by the hardware
306 */ 348 */
307struct ath5k_desc { 349struct ath5k_desc {
308 u32 ds_link; /* physical address of the next descriptor */ 350 u32 ds_link;
309 u32 ds_data; /* physical address of data buffer (skb) */ 351 u32 ds_data;
310 352
311 union { 353 union {
312 struct ath5k_hw_5210_tx_desc ds_tx5210; 354 struct ath5k_hw_5210_tx_desc ds_tx5210;