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authorJohn W. Linville <linville@tuxdriver.com>2010-12-13 15:20:45 -0500
committerJohn W. Linville <linville@tuxdriver.com>2010-12-13 15:20:45 -0500
commit1d212aa96e1b63459486f729af9a3fa38768b801 (patch)
treee91e74db57a5bb7884b4681cdb788d405ec8f10f /drivers/net/wireless/ath
parent8c4877a4128e7931077b024a891a4b284d8756a3 (diff)
parentb7613370db5ba66ad81e41cd3a5417fde4d5e03c (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem
Diffstat (limited to 'drivers/net/wireless/ath')
-rw-r--r--drivers/net/wireless/ath/ath.h115
-rw-r--r--drivers/net/wireless/ath/ath5k/base.c103
-rw-r--r--drivers/net/wireless/ath/ath5k/debug.c1
-rw-r--r--drivers/net/wireless/ath/ath5k/dma.c2
-rw-r--r--drivers/net/wireless/ath/ath5k/pci.c1
-rw-r--r--drivers/net/wireless/ath/ath5k/phy.c33
-rw-r--r--drivers/net/wireless/ath/ath5k/qcu.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/ahb.c7
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c99
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c199
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_calib.c220
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_hw.c6
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_mac.c20
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_calib.c473
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c361
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c278
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mac.c16
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_paprd.c37
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c245
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h70
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9485_initvals.h943
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c79
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.c59
-rw-r--r--drivers/net/wireless/ath/ath9k/common.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/common.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c72
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c45
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c79
-rw-r--r--drivers/net/wireless/ath/ath9k/gpio.c20
-rw-r--r--drivers/net/wireless/ath/ath9k/hif_usb.c43
-rw-r--r--drivers/net/wireless/ath/ath9k/hif_usb.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/htc.h3
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_beacon.c24
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_gpio.c15
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_init.c78
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_main.c202
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_txrx.c33
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c201
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h7
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c35
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c120
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c216
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c20
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c18
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c81
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h18
-rw-r--r--drivers/net/wireless/ath/ath9k/virtual.c7
-rw-r--r--drivers/net/wireless/ath/ath9k/wmi.c12
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c100
-rw-r--r--drivers/net/wireless/ath/debug.c20
-rw-r--r--drivers/net/wireless/ath/debug.h92
-rw-r--r--drivers/net/wireless/ath/key.c28
-rw-r--r--drivers/net/wireless/ath/main.c20
57 files changed, 3240 insertions, 1756 deletions
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
index 26bdbeee424f..e43210c8585c 100644
--- a/drivers/net/wireless/ath/ath.h
+++ b/drivers/net/wireless/ath/ath.h
@@ -104,11 +104,6 @@ enum ath_cipher {
104 ATH_CIPHER_MIC = 127 104 ATH_CIPHER_MIC = 127
105}; 105};
106 106
107enum ath_drv_info {
108 AR7010_DEVICE = BIT(0),
109 AR9287_DEVICE = BIT(1),
110};
111
112/** 107/**
113 * struct ath_ops - Register read/write operations 108 * struct ath_ops - Register read/write operations
114 * 109 *
@@ -131,6 +126,7 @@ struct ath_bus_ops {
131 void (*read_cachesize)(struct ath_common *common, int *csz); 126 void (*read_cachesize)(struct ath_common *common, int *csz);
132 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 127 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
133 void (*bt_coex_prep)(struct ath_common *common); 128 void (*bt_coex_prep)(struct ath_common *common);
129 void (*extn_synch_en)(struct ath_common *common);
134}; 130};
135 131
136struct ath_common { 132struct ath_common {
@@ -152,7 +148,6 @@ struct ath_common {
152 u8 rx_chainmask; 148 u8 rx_chainmask;
153 149
154 u32 rx_bufsize; 150 u32 rx_bufsize;
155 u32 driver_info;
156 151
157 u32 keymax; 152 u32 keymax;
158 DECLARE_BITMAP(keymap, ATH_KEYMAX); 153 DECLARE_BITMAP(keymap, ATH_KEYMAX);
@@ -186,4 +181,112 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry);
186void ath_hw_cycle_counters_update(struct ath_common *common); 181void ath_hw_cycle_counters_update(struct ath_common *common);
187int32_t ath_hw_get_listen_time(struct ath_common *common); 182int32_t ath_hw_get_listen_time(struct ath_common *common);
188 183
184extern __attribute__ ((format (printf, 3, 4))) int
185ath_printk(const char *level, struct ath_common *common, const char *fmt, ...);
186
187#define ath_emerg(common, fmt, ...) \
188 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
189#define ath_alert(common, fmt, ...) \
190 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
191#define ath_crit(common, fmt, ...) \
192 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
193#define ath_err(common, fmt, ...) \
194 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
195#define ath_warn(common, fmt, ...) \
196 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
197#define ath_notice(common, fmt, ...) \
198 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
199#define ath_info(common, fmt, ...) \
200 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
201
202/**
203 * enum ath_debug_level - atheros wireless debug level
204 *
205 * @ATH_DBG_RESET: reset processing
206 * @ATH_DBG_QUEUE: hardware queue management
207 * @ATH_DBG_EEPROM: eeprom processing
208 * @ATH_DBG_CALIBRATE: periodic calibration
209 * @ATH_DBG_INTERRUPT: interrupt processing
210 * @ATH_DBG_REGULATORY: regulatory processing
211 * @ATH_DBG_ANI: adaptive noise immunitive processing
212 * @ATH_DBG_XMIT: basic xmit operation
213 * @ATH_DBG_BEACON: beacon handling
214 * @ATH_DBG_CONFIG: configuration of the hardware
215 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
216 * @ATH_DBG_PS: power save processing
217 * @ATH_DBG_HWTIMER: hardware timer handling
218 * @ATH_DBG_BTCOEX: bluetooth coexistance
219 * @ATH_DBG_BSTUCK: stuck beacons
220 * @ATH_DBG_ANY: enable all debugging
221 *
222 * The debug level is used to control the amount and type of debugging output
223 * we want to see. Each driver has its own method for enabling debugging and
224 * modifying debug level states -- but this is typically done through a
225 * module parameter 'debug' along with a respective 'debug' debugfs file
226 * entry.
227 */
228enum ATH_DEBUG {
229 ATH_DBG_RESET = 0x00000001,
230 ATH_DBG_QUEUE = 0x00000002,
231 ATH_DBG_EEPROM = 0x00000004,
232 ATH_DBG_CALIBRATE = 0x00000008,
233 ATH_DBG_INTERRUPT = 0x00000010,
234 ATH_DBG_REGULATORY = 0x00000020,
235 ATH_DBG_ANI = 0x00000040,
236 ATH_DBG_XMIT = 0x00000080,
237 ATH_DBG_BEACON = 0x00000100,
238 ATH_DBG_CONFIG = 0x00000200,
239 ATH_DBG_FATAL = 0x00000400,
240 ATH_DBG_PS = 0x00000800,
241 ATH_DBG_HWTIMER = 0x00001000,
242 ATH_DBG_BTCOEX = 0x00002000,
243 ATH_DBG_WMI = 0x00004000,
244 ATH_DBG_BSTUCK = 0x00008000,
245 ATH_DBG_ANY = 0xffffffff
246};
247
248#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
249
250#ifdef CONFIG_ATH_DEBUG
251
252#define ath_dbg(common, dbg_mask, fmt, ...) \
253({ \
254 int rtn; \
255 if ((common)->debug_mask & dbg_mask) \
256 rtn = ath_printk(KERN_DEBUG, common, fmt, \
257 ##__VA_ARGS__); \
258 else \
259 rtn = 0; \
260 \
261 rtn; \
262})
263#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
264#define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
265
266#else
267
268static inline __attribute__ ((format (printf, 3, 4))) int
269ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
270 const char *fmt, ...)
271{
272 return 0;
273}
274#define ATH_DBG_WARN(foo, arg...) do {} while (0)
275#define ATH_DBG_WARN_ON_ONCE(foo) ({ \
276 int __ret_warn_once = !!(foo); \
277 unlikely(__ret_warn_once); \
278})
279
280#endif /* CONFIG_ATH_DEBUG */
281
282/** Returns string describing opmode, or NULL if unknown mode. */
283#ifdef CONFIG_ATH_DEBUG
284const char *ath_opmode_to_string(enum nl80211_iftype opmode);
285#else
286static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
287{
288 return "UNKNOWN";
289}
290#endif
291
189#endif /* ATH_H */ 292#endif /* ATH_H */
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index 0a7071a6dd7a..4e3b97c3d7c2 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -60,7 +60,6 @@
60#include "reg.h" 60#include "reg.h"
61#include "debug.h" 61#include "debug.h"
62#include "ani.h" 62#include "ani.h"
63#include "../debug.h"
64 63
65static int modparam_nohwcrypt; 64static int modparam_nohwcrypt;
66module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 65module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
@@ -76,7 +75,6 @@ MODULE_AUTHOR("Nick Kossifidis");
76MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
77MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
78MODULE_LICENSE("Dual BSD/GPL"); 77MODULE_LICENSE("Dual BSD/GPL");
79MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
80 78
81static int ath5k_init(struct ieee80211_hw *hw); 79static int ath5k_init(struct ieee80211_hw *hw);
82static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, 80static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
@@ -1881,7 +1879,8 @@ ath5k_beacon_send(struct ath5k_softc *sc)
1881 sc->bmisscount = 0; 1879 sc->bmisscount = 0;
1882 } 1880 }
1883 1881
1884 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) { 1882 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1883 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1885 u64 tsf = ath5k_hw_get_tsf64(ah); 1884 u64 tsf = ath5k_hw_get_tsf64(ah);
1886 u32 tsftu = TSF_TO_TU(tsf); 1885 u32 tsftu = TSF_TO_TU(tsf);
1887 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval; 1886 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
@@ -1913,8 +1912,9 @@ ath5k_beacon_send(struct ath5k_softc *sc)
1913 /* NB: hw still stops DMA, so proceed */ 1912 /* NB: hw still stops DMA, so proceed */
1914 } 1913 }
1915 1914
1916 /* refresh the beacon for AP mode */ 1915 /* refresh the beacon for AP or MESH mode */
1917 if (sc->opmode == NL80211_IFTYPE_AP) 1916 if (sc->opmode == NL80211_IFTYPE_AP ||
1917 sc->opmode == NL80211_IFTYPE_MESH_POINT)
1918 ath5k_beacon_update(sc->hw, vif); 1918 ath5k_beacon_update(sc->hw, vif);
1919 1919
1920 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); 1920 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
@@ -2341,8 +2341,9 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2341 /* Initialize driver private data */ 2341 /* Initialize driver private data */
2342 SET_IEEE80211_DEV(hw, sc->dev); 2342 SET_IEEE80211_DEV(hw, sc->dev);
2343 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 2343 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2344 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2344 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2345 IEEE80211_HW_SIGNAL_DBM; 2345 IEEE80211_HW_SIGNAL_DBM |
2346 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2346 2347
2347 hw->wiphy->interface_modes = 2348 hw->wiphy->interface_modes =
2348 BIT(NL80211_IFTYPE_AP) | 2349 BIT(NL80211_IFTYPE_AP) |
@@ -2653,7 +2654,7 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2653 bool skip_pcu) 2654 bool skip_pcu)
2654{ 2655{
2655 struct ath5k_hw *ah = sc->ah; 2656 struct ath5k_hw *ah = sc->ah;
2656 int ret; 2657 int ret, ani_mode;
2657 2658
2658 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); 2659 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2659 2660
@@ -2661,9 +2662,17 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2661 synchronize_irq(sc->irq); 2662 synchronize_irq(sc->irq);
2662 stop_tasklets(sc); 2663 stop_tasklets(sc);
2663 2664
2664 if (chan) { 2665 /* Save ani mode and disable ANI durring
2665 ath5k_drain_tx_buffs(sc); 2666 * reset. If we don't we might get false
2667 * PHY error interrupts. */
2668 ani_mode = ah->ah_sc->ani_state.ani_mode;
2669 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2666 2670
2671 /* We are going to empty hw queues
2672 * so we should also free any remaining
2673 * tx buffers */
2674 ath5k_drain_tx_buffs(sc);
2675 if (chan) {
2667 sc->curchan = chan; 2676 sc->curchan = chan;
2668 sc->curband = &sc->sbands[chan->band]; 2677 sc->curband = &sc->sbands[chan->band];
2669 } 2678 }
@@ -2680,12 +2689,12 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2680 goto err; 2689 goto err;
2681 } 2690 }
2682 2691
2683 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode); 2692 ath5k_ani_init(ah, ani_mode);
2684 2693
2685 ah->ah_cal_next_full = jiffies; 2694 ah->ah_cal_next_full = jiffies;
2686 ah->ah_cal_next_ani = jiffies; 2695 ah->ah_cal_next_ani = jiffies;
2687 ah->ah_cal_next_nf = jiffies; 2696 ah->ah_cal_next_nf = jiffies;
2688 ewma_init(&ah->ah_beacon_rssi_avg, 1000, 8); 2697 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2689 2698
2690 /* 2699 /*
2691 * Change channels and update the h/w rate map if we're switching; 2700 * Change channels and update the h/w rate map if we're switching;
@@ -2790,33 +2799,46 @@ ath5k_init(struct ieee80211_hw *hw)
2790 goto err_bhal; 2799 goto err_bhal;
2791 } 2800 }
2792 2801
2793 /* This order matches mac80211's queue priority, so we can 2802 /* 5211 and 5212 usually support 10 queues but we better rely on the
2794 * directly use the mac80211 queue number without any mapping */ 2803 * capability information */
2795 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 2804 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2796 if (IS_ERR(txq)) { 2805 /* This order matches mac80211's queue priority, so we can
2797 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2806 * directly use the mac80211 queue number without any mapping */
2798 ret = PTR_ERR(txq); 2807 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2799 goto err_queues; 2808 if (IS_ERR(txq)) {
2800 } 2809 ATH5K_ERR(sc, "can't setup xmit queue\n");
2801 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 2810 ret = PTR_ERR(txq);
2802 if (IS_ERR(txq)) { 2811 goto err_queues;
2803 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2812 }
2804 ret = PTR_ERR(txq); 2813 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2805 goto err_queues; 2814 if (IS_ERR(txq)) {
2806 } 2815 ATH5K_ERR(sc, "can't setup xmit queue\n");
2807 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2816 ret = PTR_ERR(txq);
2808 if (IS_ERR(txq)) { 2817 goto err_queues;
2809 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2818 }
2810 ret = PTR_ERR(txq); 2819 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2811 goto err_queues; 2820 if (IS_ERR(txq)) {
2812 } 2821 ATH5K_ERR(sc, "can't setup xmit queue\n");
2813 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 2822 ret = PTR_ERR(txq);
2814 if (IS_ERR(txq)) { 2823 goto err_queues;
2815 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2824 }
2816 ret = PTR_ERR(txq); 2825 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2817 goto err_queues; 2826 if (IS_ERR(txq)) {
2827 ATH5K_ERR(sc, "can't setup xmit queue\n");
2828 ret = PTR_ERR(txq);
2829 goto err_queues;
2830 }
2831 hw->queues = 4;
2832 } else {
2833 /* older hardware (5210) can only support one data queue */
2834 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2835 if (IS_ERR(txq)) {
2836 ATH5K_ERR(sc, "can't setup xmit queue\n");
2837 ret = PTR_ERR(txq);
2838 goto err_queues;
2839 }
2840 hw->queues = 1;
2818 } 2841 }
2819 hw->queues = 4;
2820 2842
2821 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); 2843 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2822 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 2844 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
@@ -2977,7 +2999,8 @@ static int ath5k_add_interface(struct ieee80211_hw *hw,
2977 2999
2978 /* Assign the vap/adhoc to a beacon xmit slot. */ 3000 /* Assign the vap/adhoc to a beacon xmit slot. */
2979 if ((avf->opmode == NL80211_IFTYPE_AP) || 3001 if ((avf->opmode == NL80211_IFTYPE_AP) ||
2980 (avf->opmode == NL80211_IFTYPE_ADHOC)) { 3002 (avf->opmode == NL80211_IFTYPE_ADHOC) ||
3003 (avf->opmode == NL80211_IFTYPE_MESH_POINT)) {
2981 int slot; 3004 int slot;
2982 3005
2983 WARN_ON(list_empty(&sc->bcbuf)); 3006 WARN_ON(list_empty(&sc->bcbuf));
@@ -2996,7 +3019,7 @@ static int ath5k_add_interface(struct ieee80211_hw *hw,
2996 sc->bslot[avf->bslot] = vif; 3019 sc->bslot[avf->bslot] = vif;
2997 if (avf->opmode == NL80211_IFTYPE_AP) 3020 if (avf->opmode == NL80211_IFTYPE_AP)
2998 sc->num_ap_vifs++; 3021 sc->num_ap_vifs++;
2999 else 3022 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
3000 sc->num_adhoc_vifs++; 3023 sc->num_adhoc_vifs++;
3001 } 3024 }
3002 3025
diff --git a/drivers/net/wireless/ath/ath5k/debug.c b/drivers/net/wireless/ath/ath5k/debug.c
index 5341dd2860d3..d2f84d76bb07 100644
--- a/drivers/net/wireless/ath/ath5k/debug.c
+++ b/drivers/net/wireless/ath/ath5k/debug.c
@@ -60,7 +60,6 @@
60 60
61#include "base.h" 61#include "base.h"
62#include "debug.h" 62#include "debug.h"
63#include "../debug.h"
64 63
65static unsigned int ath5k_debug; 64static unsigned int ath5k_debug;
66module_param_named(debug, ath5k_debug, uint, 0); 65module_param_named(debug, ath5k_debug, uint, 0);
diff --git a/drivers/net/wireless/ath/ath5k/dma.c b/drivers/net/wireless/ath/ath5k/dma.c
index 82541fec9f0e..0064be7ce5c9 100644
--- a/drivers/net/wireless/ath/ath5k/dma.c
+++ b/drivers/net/wireless/ath/ath5k/dma.c
@@ -72,7 +72,7 @@ static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
72 i--) 72 i--)
73 udelay(100); 73 udelay(100);
74 74
75 if (i) 75 if (!i)
76 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA, 76 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
77 "failed to stop RX DMA !\n"); 77 "failed to stop RX DMA !\n");
78 78
diff --git a/drivers/net/wireless/ath/ath5k/pci.c b/drivers/net/wireless/ath/ath5k/pci.c
index 39f033128c5a..7f8c5b0e9d2a 100644
--- a/drivers/net/wireless/ath/ath5k/pci.c
+++ b/drivers/net/wireless/ath/ath5k/pci.c
@@ -45,6 +45,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
45 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ 45 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
46 { 0 } 46 { 0 }
47}; 47};
48MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
48 49
49/* return bus cachesize in 4B word units */ 50/* return bus cachesize in 4B word units */
50static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz) 51static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index df5cd0fd69d6..f84afb420bd8 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -2742,10 +2742,12 @@ ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2742 2742
2743/* Write PDADC values on hw */ 2743/* Write PDADC values on hw */
2744static void 2744static void
2745ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, 2745ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
2746 u8 pdcurves, u8 *pdg_to_idx)
2747{ 2746{
2747 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2748 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2748 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2749 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
2750 u8 pdcurves = ee->ee_pd_gains[ee_mode];
2749 u32 reg; 2751 u32 reg;
2750 u8 i; 2752 u8 i;
2751 2753
@@ -2992,7 +2994,7 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2992 ee->ee_pd_gains[ee_mode]); 2994 ee->ee_pd_gains[ee_mode]);
2993 2995
2994 /* Write settings on hw */ 2996 /* Write settings on hw */
2995 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx); 2997 ath5k_setup_pwr_to_pdadc_table(ah, ee_mode);
2996 2998
2997 /* Set txp.offset, note that table_min 2999 /* Set txp.offset, note that table_min
2998 * can be negative */ 3000 * can be negative */
@@ -3114,12 +3116,6 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3114 return -EINVAL; 3116 return -EINVAL;
3115 } 3117 }
3116 3118
3117 /* Reset TX power values */
3118 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3119 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3120 ah->ah_txpower.txp_min_pwr = 0;
3121 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
3122
3123 /* Initialize TX power table */ 3119 /* Initialize TX power table */
3124 switch (ah->ah_radio) { 3120 switch (ah->ah_radio) {
3125 case AR5K_RF5110: 3121 case AR5K_RF5110:
@@ -3146,11 +3142,24 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3146 * so there is no need to recalculate the powertable, we 'll 3142 * so there is no need to recalculate the powertable, we 'll
3147 * just use the cached one */ 3143 * just use the cached one */
3148 if (!fast) { 3144 if (!fast) {
3145 /* Reset TX power values */
3146 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3147 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3148 ah->ah_txpower.txp_min_pwr = 0;
3149 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
3150
3151 /* Calculate the powertable */
3149 ret = ath5k_setup_channel_powertable(ah, channel, 3152 ret = ath5k_setup_channel_powertable(ah, channel,
3150 ee_mode, type); 3153 ee_mode, type);
3151 if (ret) 3154 if (ret)
3152 return ret; 3155 return ret;
3153 } 3156 /* Write cached table on hw */
3157 } else if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
3158 ath5k_setup_pwr_to_pdadc_table(ah, ee_mode);
3159 else
3160 ath5k_setup_pcdac_table(ah);
3161
3162
3154 3163
3155 /* Limit max power if we have a CTL available */ 3164 /* Limit max power if we have a CTL available */
3156 ath5k_get_max_ctl_power(ah, channel); 3165 ath5k_get_max_ctl_power(ah, channel);
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c
index 1849eee8235c..2c9c9e793d4e 100644
--- a/drivers/net/wireless/ath/ath5k/qcu.c
+++ b/drivers/net/wireless/ath/ath5k/qcu.c
@@ -152,8 +152,8 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
152 /* 152 /*
153 * Get queue by type 153 * Get queue by type
154 */ 154 */
155 /*5210 only has 2 queues*/ 155 /* 5210 only has 2 queues */
156 if (ah->ah_version == AR5K_AR5210) { 156 if (ah->ah_capabilities.cap_queues.q_tx_num == 2) {
157 switch (queue_type) { 157 switch (queue_type) {
158 case AR5K_TX_QUEUE_DATA: 158 case AR5K_TX_QUEUE_DATA:
159 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA; 159 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 1a984b02e9e5..25a6e4417cdb 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -35,10 +35,9 @@ static bool ath_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
35 35
36 pdata = (struct ath9k_platform_data *) pdev->dev.platform_data; 36 pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;
37 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 37 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
38 ath_print(common, ATH_DBG_FATAL, 38 ath_err(common,
39 "%s: flash read failed, offset %08x " 39 "%s: flash read failed, offset %08x is out of range\n",
40 "is out of range\n", 40 __func__, off);
41 __func__, off);
42 return false; 41 return false;
43 } 42 }
44 43
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 29a045da184b..2e31c775351f 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -135,8 +135,8 @@ static void ath9k_ani_restart(struct ath_hw *ah)
135 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high; 135 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
136 } 136 }
137 137
138 ath_print(common, ATH_DBG_ANI, 138 ath_dbg(common, ATH_DBG_ANI,
139 "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base); 139 "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base);
140 140
141 ENABLE_REGWRITE_BUFFER(ah); 141 ENABLE_REGWRITE_BUFFER(ah);
142 142
@@ -267,11 +267,11 @@ static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
267 267
268 aniState->noiseFloor = BEACON_RSSI(ah); 268 aniState->noiseFloor = BEACON_RSSI(ah);
269 269
270 ath_print(common, ATH_DBG_ANI, 270 ath_dbg(common, ATH_DBG_ANI,
271 "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 271 "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
272 aniState->ofdmNoiseImmunityLevel, 272 aniState->ofdmNoiseImmunityLevel,
273 immunityLevel, aniState->noiseFloor, 273 immunityLevel, aniState->noiseFloor,
274 aniState->rssiThrLow, aniState->rssiThrHigh); 274 aniState->rssiThrLow, aniState->rssiThrHigh);
275 275
276 aniState->ofdmNoiseImmunityLevel = immunityLevel; 276 aniState->ofdmNoiseImmunityLevel = immunityLevel;
277 277
@@ -334,11 +334,11 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
334 const struct ani_cck_level_entry *entry_cck; 334 const struct ani_cck_level_entry *entry_cck;
335 335
336 aniState->noiseFloor = BEACON_RSSI(ah); 336 aniState->noiseFloor = BEACON_RSSI(ah);
337 ath_print(common, ATH_DBG_ANI, 337 ath_dbg(common, ATH_DBG_ANI,
338 "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 338 "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
339 aniState->cckNoiseImmunityLevel, immunityLevel, 339 aniState->cckNoiseImmunityLevel, immunityLevel,
340 aniState->noiseFloor, aniState->rssiThrLow, 340 aniState->noiseFloor, aniState->rssiThrLow,
341 aniState->rssiThrHigh); 341 aniState->rssiThrHigh);
342 342
343 if ((ah->opmode == NL80211_IFTYPE_STATION || 343 if ((ah->opmode == NL80211_IFTYPE_STATION ||
344 ah->opmode == NL80211_IFTYPE_ADHOC) && 344 ah->opmode == NL80211_IFTYPE_ADHOC) &&
@@ -358,7 +358,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
358 entry_cck->fir_step_level); 358 entry_cck->fir_step_level);
359 359
360 /* Skip MRC CCK for pre AR9003 families */ 360 /* Skip MRC CCK for pre AR9003 families */
361 if (!AR_SREV_9300_20_OR_LATER(ah)) 361 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
362 return; 362 return;
363 363
364 if (aniState->mrcCCKOff == entry_cck->mrc_cck_on) 364 if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
@@ -478,8 +478,8 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
478 478
479 if (ah->opmode != NL80211_IFTYPE_STATION 479 if (ah->opmode != NL80211_IFTYPE_STATION
480 && ah->opmode != NL80211_IFTYPE_ADHOC) { 480 && ah->opmode != NL80211_IFTYPE_ADHOC) {
481 ath_print(common, ATH_DBG_ANI, 481 ath_dbg(common, ATH_DBG_ANI,
482 "Reset ANI state opmode %u\n", ah->opmode); 482 "Reset ANI state opmode %u\n", ah->opmode);
483 ah->stats.ast_ani_reset++; 483 ah->stats.ast_ani_reset++;
484 484
485 if (ah->opmode == NL80211_IFTYPE_AP) { 485 if (ah->opmode == NL80211_IFTYPE_AP) {
@@ -584,16 +584,14 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
584 ATH9K_ANI_OFDM_DEF_LEVEL || 584 ATH9K_ANI_OFDM_DEF_LEVEL ||
585 aniState->cckNoiseImmunityLevel != 585 aniState->cckNoiseImmunityLevel !=
586 ATH9K_ANI_CCK_DEF_LEVEL) { 586 ATH9K_ANI_CCK_DEF_LEVEL) {
587 ath_print(common, ATH_DBG_ANI, 587 ath_dbg(common, ATH_DBG_ANI,
588 "Restore defaults: opmode %u " 588 "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
589 "chan %d Mhz/0x%x is_scanning=%d " 589 ah->opmode,
590 "ofdm:%d cck:%d\n", 590 chan->channel,
591 ah->opmode, 591 chan->channelFlags,
592 chan->channel, 592 is_scanning,
593 chan->channelFlags, 593 aniState->ofdmNoiseImmunityLevel,
594 is_scanning, 594 aniState->cckNoiseImmunityLevel);
595 aniState->ofdmNoiseImmunityLevel,
596 aniState->cckNoiseImmunityLevel);
597 595
598 ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL); 596 ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
599 ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL); 597 ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
@@ -602,16 +600,14 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
602 /* 600 /*
603 * restore historical levels for this channel 601 * restore historical levels for this channel
604 */ 602 */
605 ath_print(common, ATH_DBG_ANI, 603 ath_dbg(common, ATH_DBG_ANI,
606 "Restore history: opmode %u " 604 "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
607 "chan %d Mhz/0x%x is_scanning=%d " 605 ah->opmode,
608 "ofdm:%d cck:%d\n", 606 chan->channel,
609 ah->opmode, 607 chan->channelFlags,
610 chan->channel, 608 is_scanning,
611 chan->channelFlags, 609 aniState->ofdmNoiseImmunityLevel,
612 is_scanning, 610 aniState->cckNoiseImmunityLevel);
613 aniState->ofdmNoiseImmunityLevel,
614 aniState->cckNoiseImmunityLevel);
615 611
616 ath9k_hw_set_ofdm_nil(ah, 612 ath9k_hw_set_ofdm_nil(ah,
617 aniState->ofdmNoiseImmunityLevel); 613 aniState->ofdmNoiseImmunityLevel);
@@ -666,19 +662,17 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
666 662
667 if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) { 663 if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) {
668 if (phyCnt1 < ofdm_base) { 664 if (phyCnt1 < ofdm_base) {
669 ath_print(common, ATH_DBG_ANI, 665 ath_dbg(common, ATH_DBG_ANI,
670 "phyCnt1 0x%x, resetting " 666 "phyCnt1 0x%x, resetting counter value to 0x%x\n",
671 "counter value to 0x%x\n", 667 phyCnt1, ofdm_base);
672 phyCnt1, ofdm_base);
673 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); 668 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
674 REG_WRITE(ah, AR_PHY_ERR_MASK_1, 669 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
675 AR_PHY_ERR_OFDM_TIMING); 670 AR_PHY_ERR_OFDM_TIMING);
676 } 671 }
677 if (phyCnt2 < cck_base) { 672 if (phyCnt2 < cck_base) {
678 ath_print(common, ATH_DBG_ANI, 673 ath_dbg(common, ATH_DBG_ANI,
679 "phyCnt2 0x%x, resetting " 674 "phyCnt2 0x%x, resetting counter value to 0x%x\n",
680 "counter value to 0x%x\n", 675 phyCnt2, cck_base);
681 phyCnt2, cck_base);
682 REG_WRITE(ah, AR_PHY_ERR_2, cck_base); 676 REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
683 REG_WRITE(ah, AR_PHY_ERR_MASK_2, 677 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
684 AR_PHY_ERR_CCK_TIMING); 678 AR_PHY_ERR_CCK_TIMING);
@@ -719,13 +713,12 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
719 cckPhyErrRate = aniState->cckPhyErrCount * 1000 / 713 cckPhyErrRate = aniState->cckPhyErrCount * 1000 /
720 aniState->listenTime; 714 aniState->listenTime;
721 715
722 ath_print(common, ATH_DBG_ANI, 716 ath_dbg(common, ATH_DBG_ANI,
723 "listenTime=%d OFDM:%d errs=%d/s CCK:%d " 717 "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
724 "errs=%d/s ofdm_turn=%d\n", 718 aniState->listenTime,
725 aniState->listenTime, 719 aniState->ofdmNoiseImmunityLevel,
726 aniState->ofdmNoiseImmunityLevel, 720 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
727 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel, 721 cckPhyErrRate, aniState->ofdmsTurn);
728 cckPhyErrRate, aniState->ofdmsTurn);
729 722
730 if (aniState->listenTime > 5 * ah->aniperiod) { 723 if (aniState->listenTime > 5 * ah->aniperiod) {
731 if (ofdmPhyErrRate <= ah->config.ofdm_trig_low && 724 if (ofdmPhyErrRate <= ah->config.ofdm_trig_low &&
@@ -755,7 +748,7 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
755{ 748{
756 struct ath_common *common = ath9k_hw_common(ah); 749 struct ath_common *common = ath9k_hw_common(ah);
757 750
758 ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n"); 751 ath_dbg(common, ATH_DBG_ANI, "Enable MIB counters\n");
759 752
760 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 753 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
761 754
@@ -777,7 +770,7 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
777{ 770{
778 struct ath_common *common = ath9k_hw_common(ah); 771 struct ath_common *common = ath9k_hw_common(ah);
779 772
780 ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n"); 773 ath_dbg(common, ATH_DBG_ANI, "Disable MIB counters\n");
781 774
782 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); 775 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
783 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 776 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
@@ -852,7 +845,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
852 struct ath_common *common = ath9k_hw_common(ah); 845 struct ath_common *common = ath9k_hw_common(ah);
853 int i; 846 int i;
854 847
855 ath_print(common, ATH_DBG_ANI, "Initialize ANI\n"); 848 ath_dbg(common, ATH_DBG_ANI, "Initialize ANI\n");
856 849
857 if (use_new_ani(ah)) { 850 if (use_new_ani(ah)) {
858 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW; 851 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index 06e34d293dc8..059330aac645 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -130,9 +130,8 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
130 /* pre-reverse this field */ 130 /* pre-reverse this field */
131 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); 131 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
132 132
133 ath_print(common, ATH_DBG_CONFIG, 133 ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
134 "Force rf_pwd_icsyndiv to %1d on %4d\n", 134 new_bias, synth_freq);
135 new_bias, synth_freq);
136 135
137 /* swizzle rf_pwd_icsyndiv */ 136 /* swizzle rf_pwd_icsyndiv */
138 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); 137 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
@@ -173,8 +172,7 @@ static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
173 channelSel = ((freq - 704) * 2 - 3040) / 10; 172 channelSel = ((freq - 704) * 2 - 3040) / 10;
174 bModeSynth = 1; 173 bModeSynth = 1;
175 } else { 174 } else {
176 ath_print(common, ATH_DBG_FATAL, 175 ath_err(common, "Invalid channel %u MHz\n", freq);
177 "Invalid channel %u MHz\n", freq);
178 return -EINVAL; 176 return -EINVAL;
179 } 177 }
180 178
@@ -206,8 +204,7 @@ static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
206 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 204 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
207 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 205 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
208 } else { 206 } else {
209 ath_print(common, ATH_DBG_FATAL, 207 ath_err(common, "Invalid channel %u MHz\n", freq);
210 "Invalid channel %u MHz\n", freq);
211 return -EINVAL; 208 return -EINVAL;
212 } 209 }
213 210
@@ -448,8 +445,7 @@ static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
448#define ATH_ALLOC_BANK(bank, size) do { \ 445#define ATH_ALLOC_BANK(bank, size) do { \
449 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \ 446 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
450 if (!bank) { \ 447 if (!bank) { \
451 ath_print(common, ATH_DBG_FATAL, \ 448 ath_err(common, "Cannot allocate RF banks\n"); \
452 "Cannot allocate RF banks\n"); \
453 return -ENOMEM; \ 449 return -ENOMEM; \
454 } \ 450 } \
455 } while (0); 451 } while (0);
@@ -879,8 +875,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
879 875
880 /* Write analog registers */ 876 /* Write analog registers */
881 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 877 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
882 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 878 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
883 "ar5416SetRfRegs failed\n");
884 return -EIO; 879 return -EIO;
885 } 880 }
886 881
@@ -1058,10 +1053,9 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1058 u32 level = param; 1053 u32 level = param;
1059 1054
1060 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { 1055 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1061 ath_print(common, ATH_DBG_ANI, 1056 ath_dbg(common, ATH_DBG_ANI,
1062 "level out of range (%u > %u)\n", 1057 "level out of range (%u > %zu)\n",
1063 level, 1058 level, ARRAY_SIZE(ah->totalSizeDesired));
1064 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
1065 return false; 1059 return false;
1066 } 1060 }
1067 1061
@@ -1163,10 +1157,9 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1163 u32 level = param; 1157 u32 level = param;
1164 1158
1165 if (level >= ARRAY_SIZE(firstep)) { 1159 if (level >= ARRAY_SIZE(firstep)) {
1166 ath_print(common, ATH_DBG_ANI, 1160 ath_dbg(common, ATH_DBG_ANI,
1167 "level out of range (%u > %u)\n", 1161 "level out of range (%u > %zu)\n",
1168 level, 1162 level, ARRAY_SIZE(firstep));
1169 (unsigned) ARRAY_SIZE(firstep));
1170 return false; 1163 return false;
1171 } 1164 }
1172 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1165 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
@@ -1184,10 +1177,9 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1184 u32 level = param; 1177 u32 level = param;
1185 1178
1186 if (level >= ARRAY_SIZE(cycpwrThr1)) { 1179 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1187 ath_print(common, ATH_DBG_ANI, 1180 ath_dbg(common, ATH_DBG_ANI,
1188 "level out of range (%u > %u)\n", 1181 "level out of range (%u > %zu)\n",
1189 level, 1182 level, ARRAY_SIZE(cycpwrThr1));
1190 (unsigned) ARRAY_SIZE(cycpwrThr1));
1191 return false; 1183 return false;
1192 } 1184 }
1193 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1185 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
@@ -1203,25 +1195,22 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1203 case ATH9K_ANI_PRESENT: 1195 case ATH9K_ANI_PRESENT:
1204 break; 1196 break;
1205 default: 1197 default:
1206 ath_print(common, ATH_DBG_ANI, 1198 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1207 "invalid cmd %u\n", cmd);
1208 return false; 1199 return false;
1209 } 1200 }
1210 1201
1211 ath_print(common, ATH_DBG_ANI, "ANI parameters:\n"); 1202 ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n");
1212 ath_print(common, ATH_DBG_ANI, 1203 ath_dbg(common, ATH_DBG_ANI,
1213 "noiseImmunityLevel=%d, spurImmunityLevel=%d, " 1204 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
1214 "ofdmWeakSigDetectOff=%d\n", 1205 aniState->noiseImmunityLevel,
1215 aniState->noiseImmunityLevel, 1206 aniState->spurImmunityLevel,
1216 aniState->spurImmunityLevel, 1207 !aniState->ofdmWeakSigDetectOff);
1217 !aniState->ofdmWeakSigDetectOff); 1208 ath_dbg(common, ATH_DBG_ANI,
1218 ath_print(common, ATH_DBG_ANI, 1209 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1219 "cckWeakSigThreshold=%d, " 1210 aniState->cckWeakSigThreshold,
1220 "firstepLevel=%d, listenTime=%d\n", 1211 aniState->firstepLevel,
1221 aniState->cckWeakSigThreshold, 1212 aniState->listenTime);
1222 aniState->firstepLevel, 1213 ath_dbg(common, ATH_DBG_ANI,
1223 aniState->listenTime);
1224 ath_print(common, ATH_DBG_ANI,
1225 "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", 1214 "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1226 aniState->ofdmPhyErrCount, 1215 aniState->ofdmPhyErrCount,
1227 aniState->cckPhyErrCount); 1216 aniState->cckPhyErrCount);
@@ -1306,12 +1295,12 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1306 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1295 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1307 1296
1308 if (!on != aniState->ofdmWeakSigDetectOff) { 1297 if (!on != aniState->ofdmWeakSigDetectOff) {
1309 ath_print(common, ATH_DBG_ANI, 1298 ath_dbg(common, ATH_DBG_ANI,
1310 "** ch %d: ofdm weak signal: %s=>%s\n", 1299 "** ch %d: ofdm weak signal: %s=>%s\n",
1311 chan->channel, 1300 chan->channel,
1312 !aniState->ofdmWeakSigDetectOff ? 1301 !aniState->ofdmWeakSigDetectOff ?
1313 "on" : "off", 1302 "on" : "off",
1314 on ? "on" : "off"); 1303 on ? "on" : "off");
1315 if (on) 1304 if (on)
1316 ah->stats.ast_ani_ofdmon++; 1305 ah->stats.ast_ani_ofdmon++;
1317 else 1306 else
@@ -1324,11 +1313,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1324 u32 level = param; 1313 u32 level = param;
1325 1314
1326 if (level >= ARRAY_SIZE(firstep_table)) { 1315 if (level >= ARRAY_SIZE(firstep_table)) {
1327 ath_print(common, ATH_DBG_ANI, 1316 ath_dbg(common, ATH_DBG_ANI,
1328 "ATH9K_ANI_FIRSTEP_LEVEL: level " 1317 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1329 "out of range (%u > %u)\n", 1318 level, ARRAY_SIZE(firstep_table));
1330 level,
1331 (unsigned) ARRAY_SIZE(firstep_table));
1332 return false; 1319 return false;
1333 } 1320 }
1334 1321
@@ -1363,24 +1350,22 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1363 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2); 1350 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1364 1351
1365 if (level != aniState->firstepLevel) { 1352 if (level != aniState->firstepLevel) {
1366 ath_print(common, ATH_DBG_ANI, 1353 ath_dbg(common, ATH_DBG_ANI,
1367 "** ch %d: level %d=>%d[def:%d] " 1354 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1368 "firstep[level]=%d ini=%d\n", 1355 chan->channel,
1369 chan->channel, 1356 aniState->firstepLevel,
1370 aniState->firstepLevel, 1357 level,
1371 level, 1358 ATH9K_ANI_FIRSTEP_LVL_NEW,
1372 ATH9K_ANI_FIRSTEP_LVL_NEW, 1359 value,
1373 value, 1360 aniState->iniDef.firstep);
1374 aniState->iniDef.firstep); 1361 ath_dbg(common, ATH_DBG_ANI,
1375 ath_print(common, ATH_DBG_ANI, 1362 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1376 "** ch %d: level %d=>%d[def:%d] " 1363 chan->channel,
1377 "firstep_low[level]=%d ini=%d\n", 1364 aniState->firstepLevel,
1378 chan->channel, 1365 level,
1379 aniState->firstepLevel, 1366 ATH9K_ANI_FIRSTEP_LVL_NEW,
1380 level, 1367 value2,
1381 ATH9K_ANI_FIRSTEP_LVL_NEW, 1368 aniState->iniDef.firstepLow);
1382 value2,
1383 aniState->iniDef.firstepLow);
1384 if (level > aniState->firstepLevel) 1369 if (level > aniState->firstepLevel)
1385 ah->stats.ast_ani_stepup++; 1370 ah->stats.ast_ani_stepup++;
1386 else if (level < aniState->firstepLevel) 1371 else if (level < aniState->firstepLevel)
@@ -1393,11 +1378,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1393 u32 level = param; 1378 u32 level = param;
1394 1379
1395 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 1380 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1396 ath_print(common, ATH_DBG_ANI, 1381 ath_dbg(common, ATH_DBG_ANI,
1397 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level " 1382 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1398 "out of range (%u > %u)\n", 1383 level, ARRAY_SIZE(cycpwrThr1_table));
1399 level,
1400 (unsigned) ARRAY_SIZE(cycpwrThr1_table));
1401 return false; 1384 return false;
1402 } 1385 }
1403 /* 1386 /*
@@ -1431,24 +1414,22 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1431 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2); 1414 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
1432 1415
1433 if (level != aniState->spurImmunityLevel) { 1416 if (level != aniState->spurImmunityLevel) {
1434 ath_print(common, ATH_DBG_ANI, 1417 ath_dbg(common, ATH_DBG_ANI,
1435 "** ch %d: level %d=>%d[def:%d] " 1418 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1436 "cycpwrThr1[level]=%d ini=%d\n", 1419 chan->channel,
1437 chan->channel, 1420 aniState->spurImmunityLevel,
1438 aniState->spurImmunityLevel, 1421 level,
1439 level, 1422 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1440 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1423 value,
1441 value, 1424 aniState->iniDef.cycpwrThr1);
1442 aniState->iniDef.cycpwrThr1); 1425 ath_dbg(common, ATH_DBG_ANI,
1443 ath_print(common, ATH_DBG_ANI, 1426 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1444 "** ch %d: level %d=>%d[def:%d] " 1427 chan->channel,
1445 "cycpwrThr1Ext[level]=%d ini=%d\n", 1428 aniState->spurImmunityLevel,
1446 chan->channel, 1429 level,
1447 aniState->spurImmunityLevel, 1430 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1448 level, 1431 value2,
1449 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1432 aniState->iniDef.cycpwrThr1Ext);
1450 value2,
1451 aniState->iniDef.cycpwrThr1Ext);
1452 if (level > aniState->spurImmunityLevel) 1433 if (level > aniState->spurImmunityLevel)
1453 ah->stats.ast_ani_spurup++; 1434 ah->stats.ast_ani_spurup++;
1454 else if (level < aniState->spurImmunityLevel) 1435 else if (level < aniState->spurImmunityLevel)
@@ -1467,22 +1448,19 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1467 case ATH9K_ANI_PRESENT: 1448 case ATH9K_ANI_PRESENT:
1468 break; 1449 break;
1469 default: 1450 default:
1470 ath_print(common, ATH_DBG_ANI, 1451 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1471 "invalid cmd %u\n", cmd);
1472 return false; 1452 return false;
1473 } 1453 }
1474 1454
1475 ath_print(common, ATH_DBG_ANI, 1455 ath_dbg(common, ATH_DBG_ANI,
1476 "ANI parameters: SI=%d, ofdmWS=%s FS=%d " 1456 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1477 "MRCcck=%s listenTime=%d " 1457 aniState->spurImmunityLevel,
1478 "ofdmErrs=%d cckErrs=%d\n", 1458 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1479 aniState->spurImmunityLevel, 1459 aniState->firstepLevel,
1480 !aniState->ofdmWeakSigDetectOff ? "on" : "off", 1460 !aniState->mrcCCKOff ? "on" : "off",
1481 aniState->firstepLevel, 1461 aniState->listenTime,
1482 !aniState->mrcCCKOff ? "on" : "off", 1462 aniState->ofdmPhyErrCount,
1483 aniState->listenTime, 1463 aniState->cckPhyErrCount);
1484 aniState->ofdmPhyErrCount,
1485 aniState->cckPhyErrCount);
1486 return true; 1464 return true;
1487} 1465}
1488 1466
@@ -1528,13 +1506,12 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1528 1506
1529 iniDef = &aniState->iniDef; 1507 iniDef = &aniState->iniDef;
1530 1508
1531 ath_print(common, ATH_DBG_ANI, 1509 ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1532 "ver %d.%d opmode %u chan %d Mhz/0x%x\n", 1510 ah->hw_version.macVersion,
1533 ah->hw_version.macVersion, 1511 ah->hw_version.macRev,
1534 ah->hw_version.macRev, 1512 ah->opmode,
1535 ah->opmode, 1513 chan->channel,
1536 chan->channel, 1514 chan->channelFlags);
1537 chan->channelFlags);
1538 1515
1539 val = REG_READ(ah, AR_PHY_SFCORR); 1516 val = REG_READ(ah, AR_PHY_SFCORR);
1540 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1517 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
index 15f62cd0cc38..01880aa13e36 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
@@ -39,18 +39,18 @@ static void ar9002_hw_setup_calibration(struct ath_hw *ah,
39 switch (currCal->calData->calType) { 39 switch (currCal->calData->calType) {
40 case IQ_MISMATCH_CAL: 40 case IQ_MISMATCH_CAL:
41 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 41 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
42 ath_print(common, ATH_DBG_CALIBRATE, 42 ath_dbg(common, ATH_DBG_CALIBRATE,
43 "starting IQ Mismatch Calibration\n"); 43 "starting IQ Mismatch Calibration\n");
44 break; 44 break;
45 case ADC_GAIN_CAL: 45 case ADC_GAIN_CAL:
46 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); 46 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
47 ath_print(common, ATH_DBG_CALIBRATE, 47 ath_dbg(common, ATH_DBG_CALIBRATE,
48 "starting ADC Gain Calibration\n"); 48 "starting ADC Gain Calibration\n");
49 break; 49 break;
50 case ADC_DC_CAL: 50 case ADC_DC_CAL:
51 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); 51 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
52 ath_print(common, ATH_DBG_CALIBRATE, 52 ath_dbg(common, ATH_DBG_CALIBRATE,
53 "starting ADC DC Calibration\n"); 53 "starting ADC DC Calibration\n");
54 break; 54 break;
55 } 55 }
56 56
@@ -107,11 +107,11 @@ static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
107 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 107 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
108 ah->totalIqCorrMeas[i] += 108 ah->totalIqCorrMeas[i] +=
109 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 109 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
110 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, 110 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
111 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", 111 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
112 ah->cal_samples, i, ah->totalPowerMeasI[i], 112 ah->cal_samples, i, ah->totalPowerMeasI[i],
113 ah->totalPowerMeasQ[i], 113 ah->totalPowerMeasQ[i],
114 ah->totalIqCorrMeas[i]); 114 ah->totalIqCorrMeas[i]);
115 } 115 }
116} 116}
117 117
@@ -129,14 +129,13 @@ static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
129 ah->totalAdcQEvenPhase[i] += 129 ah->totalAdcQEvenPhase[i] +=
130 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 130 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
131 131
132 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, 132 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
133 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 133 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
134 "oddq=0x%08x; evenq=0x%08x;\n", 134 ah->cal_samples, i,
135 ah->cal_samples, i, 135 ah->totalAdcIOddPhase[i],
136 ah->totalAdcIOddPhase[i], 136 ah->totalAdcIEvenPhase[i],
137 ah->totalAdcIEvenPhase[i], 137 ah->totalAdcQOddPhase[i],
138 ah->totalAdcQOddPhase[i], 138 ah->totalAdcQEvenPhase[i]);
139 ah->totalAdcQEvenPhase[i]);
140 } 139 }
141} 140}
142 141
@@ -154,14 +153,13 @@ static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
154 ah->totalAdcDcOffsetQEvenPhase[i] += 153 ah->totalAdcDcOffsetQEvenPhase[i] +=
155 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 154 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
156 155
157 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, 156 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
158 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 157 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
159 "oddq=0x%08x; evenq=0x%08x;\n", 158 ah->cal_samples, i,
160 ah->cal_samples, i, 159 ah->totalAdcDcOffsetIOddPhase[i],
161 ah->totalAdcDcOffsetIOddPhase[i], 160 ah->totalAdcDcOffsetIEvenPhase[i],
162 ah->totalAdcDcOffsetIEvenPhase[i], 161 ah->totalAdcDcOffsetQOddPhase[i],
163 ah->totalAdcDcOffsetQOddPhase[i], 162 ah->totalAdcDcOffsetQEvenPhase[i]);
164 ah->totalAdcDcOffsetQEvenPhase[i]);
165 } 163 }
166} 164}
167 165
@@ -178,13 +176,13 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
178 powerMeasQ = ah->totalPowerMeasQ[i]; 176 powerMeasQ = ah->totalPowerMeasQ[i];
179 iqCorrMeas = ah->totalIqCorrMeas[i]; 177 iqCorrMeas = ah->totalIqCorrMeas[i];
180 178
181 ath_print(common, ATH_DBG_CALIBRATE, 179 ath_dbg(common, ATH_DBG_CALIBRATE,
182 "Starting IQ Cal and Correction for Chain %d\n", 180 "Starting IQ Cal and Correction for Chain %d\n",
183 i); 181 i);
184 182
185 ath_print(common, ATH_DBG_CALIBRATE, 183 ath_dbg(common, ATH_DBG_CALIBRATE,
186 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 184 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
187 i, ah->totalIqCorrMeas[i]); 185 i, ah->totalIqCorrMeas[i]);
188 186
189 iqCorrNeg = 0; 187 iqCorrNeg = 0;
190 188
@@ -193,12 +191,12 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
193 iqCorrNeg = 1; 191 iqCorrNeg = 1;
194 } 192 }
195 193
196 ath_print(common, ATH_DBG_CALIBRATE, 194 ath_dbg(common, ATH_DBG_CALIBRATE,
197 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); 195 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
198 ath_print(common, ATH_DBG_CALIBRATE, 196 ath_dbg(common, ATH_DBG_CALIBRATE,
199 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); 197 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
200 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", 198 ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
201 iqCorrNeg); 199 iqCorrNeg);
202 200
203 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 201 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
204 qCoffDenom = powerMeasQ / 64; 202 qCoffDenom = powerMeasQ / 64;
@@ -207,14 +205,14 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
207 (qCoffDenom != 0)) { 205 (qCoffDenom != 0)) {
208 iCoff = iqCorrMeas / iCoffDenom; 206 iCoff = iqCorrMeas / iCoffDenom;
209 qCoff = powerMeasI / qCoffDenom - 64; 207 qCoff = powerMeasI / qCoffDenom - 64;
210 ath_print(common, ATH_DBG_CALIBRATE, 208 ath_dbg(common, ATH_DBG_CALIBRATE,
211 "Chn %d iCoff = 0x%08x\n", i, iCoff); 209 "Chn %d iCoff = 0x%08x\n", i, iCoff);
212 ath_print(common, ATH_DBG_CALIBRATE, 210 ath_dbg(common, ATH_DBG_CALIBRATE,
213 "Chn %d qCoff = 0x%08x\n", i, qCoff); 211 "Chn %d qCoff = 0x%08x\n", i, qCoff);
214 212
215 iCoff = iCoff & 0x3f; 213 iCoff = iCoff & 0x3f;
216 ath_print(common, ATH_DBG_CALIBRATE, 214 ath_dbg(common, ATH_DBG_CALIBRATE,
217 "New: Chn %d iCoff = 0x%08x\n", i, iCoff); 215 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
218 if (iqCorrNeg == 0x0) 216 if (iqCorrNeg == 0x0)
219 iCoff = 0x40 - iCoff; 217 iCoff = 0x40 - iCoff;
220 218
@@ -223,9 +221,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
223 else if (qCoff <= -16) 221 else if (qCoff <= -16)
224 qCoff = -16; 222 qCoff = -16;
225 223
226 ath_print(common, ATH_DBG_CALIBRATE, 224 ath_dbg(common, ATH_DBG_CALIBRATE,
227 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", 225 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
228 i, iCoff, qCoff); 226 i, iCoff, qCoff);
229 227
230 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), 228 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
231 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 229 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
@@ -233,9 +231,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
233 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), 231 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
234 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 232 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
235 qCoff); 233 qCoff);
236 ath_print(common, ATH_DBG_CALIBRATE, 234 ath_dbg(common, ATH_DBG_CALIBRATE,
237 "IQ Cal and Correction done for Chain %d\n", 235 "IQ Cal and Correction done for Chain %d\n",
238 i); 236 i);
239 } 237 }
240 } 238 }
241 239
@@ -255,21 +253,21 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
255 qOddMeasOffset = ah->totalAdcQOddPhase[i]; 253 qOddMeasOffset = ah->totalAdcQOddPhase[i];
256 qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; 254 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
257 255
258 ath_print(common, ATH_DBG_CALIBRATE, 256 ath_dbg(common, ATH_DBG_CALIBRATE,
259 "Starting ADC Gain Cal for Chain %d\n", i); 257 "Starting ADC Gain Cal for Chain %d\n", i);
260 258
261 ath_print(common, ATH_DBG_CALIBRATE, 259 ath_dbg(common, ATH_DBG_CALIBRATE,
262 "Chn %d pwr_meas_odd_i = 0x%08x\n", i, 260 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
263 iOddMeasOffset); 261 iOddMeasOffset);
264 ath_print(common, ATH_DBG_CALIBRATE, 262 ath_dbg(common, ATH_DBG_CALIBRATE,
265 "Chn %d pwr_meas_even_i = 0x%08x\n", i, 263 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
266 iEvenMeasOffset); 264 iEvenMeasOffset);
267 ath_print(common, ATH_DBG_CALIBRATE, 265 ath_dbg(common, ATH_DBG_CALIBRATE,
268 "Chn %d pwr_meas_odd_q = 0x%08x\n", i, 266 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
269 qOddMeasOffset); 267 qOddMeasOffset);
270 ath_print(common, ATH_DBG_CALIBRATE, 268 ath_dbg(common, ATH_DBG_CALIBRATE,
271 "Chn %d pwr_meas_even_q = 0x%08x\n", i, 269 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
272 qEvenMeasOffset); 270 qEvenMeasOffset);
273 271
274 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { 272 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
275 iGainMismatch = 273 iGainMismatch =
@@ -279,20 +277,20 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
279 ((qOddMeasOffset * 32) / 277 ((qOddMeasOffset * 32) /
280 qEvenMeasOffset) & 0x3f; 278 qEvenMeasOffset) & 0x3f;
281 279
282 ath_print(common, ATH_DBG_CALIBRATE, 280 ath_dbg(common, ATH_DBG_CALIBRATE,
283 "Chn %d gain_mismatch_i = 0x%08x\n", i, 281 "Chn %d gain_mismatch_i = 0x%08x\n", i,
284 iGainMismatch); 282 iGainMismatch);
285 ath_print(common, ATH_DBG_CALIBRATE, 283 ath_dbg(common, ATH_DBG_CALIBRATE,
286 "Chn %d gain_mismatch_q = 0x%08x\n", i, 284 "Chn %d gain_mismatch_q = 0x%08x\n", i,
287 qGainMismatch); 285 qGainMismatch);
288 286
289 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 287 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
290 val &= 0xfffff000; 288 val &= 0xfffff000;
291 val |= (qGainMismatch) | (iGainMismatch << 6); 289 val |= (qGainMismatch) | (iGainMismatch << 6);
292 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 290 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
293 291
294 ath_print(common, ATH_DBG_CALIBRATE, 292 ath_dbg(common, ATH_DBG_CALIBRATE,
295 "ADC Gain Cal done for Chain %d\n", i); 293 "ADC Gain Cal done for Chain %d\n", i);
296 } 294 }
297 } 295 }
298 296
@@ -317,41 +315,41 @@ static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
317 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; 315 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
318 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; 316 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
319 317
320 ath_print(common, ATH_DBG_CALIBRATE, 318 ath_dbg(common, ATH_DBG_CALIBRATE,
321 "Starting ADC DC Offset Cal for Chain %d\n", i); 319 "Starting ADC DC Offset Cal for Chain %d\n", i);
322 320
323 ath_print(common, ATH_DBG_CALIBRATE, 321 ath_dbg(common, ATH_DBG_CALIBRATE,
324 "Chn %d pwr_meas_odd_i = %d\n", i, 322 "Chn %d pwr_meas_odd_i = %d\n", i,
325 iOddMeasOffset); 323 iOddMeasOffset);
326 ath_print(common, ATH_DBG_CALIBRATE, 324 ath_dbg(common, ATH_DBG_CALIBRATE,
327 "Chn %d pwr_meas_even_i = %d\n", i, 325 "Chn %d pwr_meas_even_i = %d\n", i,
328 iEvenMeasOffset); 326 iEvenMeasOffset);
329 ath_print(common, ATH_DBG_CALIBRATE, 327 ath_dbg(common, ATH_DBG_CALIBRATE,
330 "Chn %d pwr_meas_odd_q = %d\n", i, 328 "Chn %d pwr_meas_odd_q = %d\n", i,
331 qOddMeasOffset); 329 qOddMeasOffset);
332 ath_print(common, ATH_DBG_CALIBRATE, 330 ath_dbg(common, ATH_DBG_CALIBRATE,
333 "Chn %d pwr_meas_even_q = %d\n", i, 331 "Chn %d pwr_meas_even_q = %d\n", i,
334 qEvenMeasOffset); 332 qEvenMeasOffset);
335 333
336 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / 334 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
337 numSamples) & 0x1ff; 335 numSamples) & 0x1ff;
338 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / 336 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
339 numSamples) & 0x1ff; 337 numSamples) & 0x1ff;
340 338
341 ath_print(common, ATH_DBG_CALIBRATE, 339 ath_dbg(common, ATH_DBG_CALIBRATE,
342 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, 340 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
343 iDcMismatch); 341 iDcMismatch);
344 ath_print(common, ATH_DBG_CALIBRATE, 342 ath_dbg(common, ATH_DBG_CALIBRATE,
345 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, 343 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
346 qDcMismatch); 344 qDcMismatch);
347 345
348 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 346 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
349 val &= 0xc0000fff; 347 val &= 0xc0000fff;
350 val |= (qDcMismatch << 12) | (iDcMismatch << 21); 348 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
351 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 349 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
352 350
353 ath_print(common, ATH_DBG_CALIBRATE, 351 ath_dbg(common, ATH_DBG_CALIBRATE,
354 "ADC DC Offset Cal done for Chain %d\n", i); 352 "ADC DC Offset Cal done for Chain %d\n", i);
355 } 353 }
356 354
357 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), 355 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
@@ -540,7 +538,7 @@ static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
540 { 0x7838, 0 }, 538 { 0x7838, 0 },
541 }; 539 };
542 540
543 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n"); 541 ath_dbg(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
544 542
545 /* PA CAL is not needed for high power solution */ 543 /* PA CAL is not needed for high power solution */
546 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 544 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
@@ -721,9 +719,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
721 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 719 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
722 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, 720 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
723 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { 721 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
724 ath_print(common, ATH_DBG_CALIBRATE, "offset " 722 ath_dbg(common, ATH_DBG_CALIBRATE,
725 "calibration failed to complete in " 723 "offset calibration failed to complete in 1ms; noisy environment?\n");
726 "1ms; noisy ??\n");
727 return false; 724 return false;
728 } 725 }
729 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); 726 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
@@ -736,8 +733,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
736 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 733 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
737 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 734 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
738 0, AH_WAIT_TIMEOUT)) { 735 0, AH_WAIT_TIMEOUT)) {
739 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration " 736 ath_dbg(common, ATH_DBG_CALIBRATE,
740 "failed to complete in 1ms; noisy ??\n"); 737 "offset calibration failed to complete in 1ms; noisy environment?\n");
741 return false; 738 return false;
742 } 739 }
743 740
@@ -829,9 +826,8 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
829 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, 826 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
830 AR_PHY_AGC_CONTROL_CAL, 827 AR_PHY_AGC_CONTROL_CAL,
831 0, AH_WAIT_TIMEOUT)) { 828 0, AH_WAIT_TIMEOUT)) {
832 ath_print(common, ATH_DBG_CALIBRATE, 829 ath_dbg(common, ATH_DBG_CALIBRATE,
833 "offset calibration failed to " 830 "offset calibration failed to complete in 1ms; noisy environment?\n");
834 "complete in 1ms; noisy environment?\n");
835 return false; 831 return false;
836 } 832 }
837 833
@@ -866,19 +862,19 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
866 862
867 INIT_CAL(&ah->adcgain_caldata); 863 INIT_CAL(&ah->adcgain_caldata);
868 INSERT_CAL(ah, &ah->adcgain_caldata); 864 INSERT_CAL(ah, &ah->adcgain_caldata);
869 ath_print(common, ATH_DBG_CALIBRATE, 865 ath_dbg(common, ATH_DBG_CALIBRATE,
870 "enabling ADC Gain Calibration.\n"); 866 "enabling ADC Gain Calibration.\n");
871 867
872 INIT_CAL(&ah->adcdc_caldata); 868 INIT_CAL(&ah->adcdc_caldata);
873 INSERT_CAL(ah, &ah->adcdc_caldata); 869 INSERT_CAL(ah, &ah->adcdc_caldata);
874 ath_print(common, ATH_DBG_CALIBRATE, 870 ath_dbg(common, ATH_DBG_CALIBRATE,
875 "enabling ADC DC Calibration.\n"); 871 "enabling ADC DC Calibration.\n");
876 } 872 }
877 873
878 INIT_CAL(&ah->iq_caldata); 874 INIT_CAL(&ah->iq_caldata);
879 INSERT_CAL(ah, &ah->iq_caldata); 875 INSERT_CAL(ah, &ah->iq_caldata);
880 ath_print(common, ATH_DBG_CALIBRATE, 876 ath_dbg(common, ATH_DBG_CALIBRATE,
881 "enabling IQ Calibration.\n"); 877 "enabling IQ Calibration.\n");
882 878
883 ah->cal_list_curr = ah->cal_list; 879 ah->cal_list_curr = ah->cal_list;
884 880
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index 48261b7252d0..7d5cb204f938 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -494,9 +494,9 @@ int ar9002_hw_rf_claim(struct ath_hw *ah)
494 case AR_RAD2122_SREV_MAJOR: 494 case AR_RAD2122_SREV_MAJOR:
495 break; 495 break;
496 default: 496 default:
497 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 497 ath_err(ath9k_hw_common(ah),
498 "Radio Chip Rev 0x%02X not supported\n", 498 "Radio Chip Rev 0x%02X not supported\n",
499 val & AR_RADIO_SREV_MAJOR); 499 val & AR_RADIO_SREV_MAJOR);
500 return -EOPNOTSUPP; 500 return -EOPNOTSUPP;
501 } 501 }
502 502
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
index f0268e5eab34..f3f9c589158e 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
@@ -111,8 +111,8 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
111 } 111 }
112 112
113 if (isr & AR_ISR_RXORN) { 113 if (isr & AR_ISR_RXORN) {
114 ath_print(common, ATH_DBG_INTERRUPT, 114 ath_dbg(common, ATH_DBG_INTERRUPT,
115 "receive FIFO overrun interrupt\n"); 115 "receive FIFO overrun interrupt\n");
116 } 116 }
117 117
118 *masked |= mask2; 118 *masked |= mask2;
@@ -147,25 +147,25 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
147 147
148 if (fatal_int) { 148 if (fatal_int) {
149 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 149 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
150 ath_print(common, ATH_DBG_ANY, 150 ath_dbg(common, ATH_DBG_ANY,
151 "received PCI FATAL interrupt\n"); 151 "received PCI FATAL interrupt\n");
152 } 152 }
153 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 153 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
154 ath_print(common, ATH_DBG_ANY, 154 ath_dbg(common, ATH_DBG_ANY,
155 "received PCI PERR interrupt\n"); 155 "received PCI PERR interrupt\n");
156 } 156 }
157 *masked |= ATH9K_INT_FATAL; 157 *masked |= ATH9K_INT_FATAL;
158 } 158 }
159 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 159 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
160 ath_print(common, ATH_DBG_INTERRUPT, 160 ath_dbg(common, ATH_DBG_INTERRUPT,
161 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); 161 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
162 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 162 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
163 REG_WRITE(ah, AR_RC, 0); 163 REG_WRITE(ah, AR_RC, 0);
164 *masked |= ATH9K_INT_FATAL; 164 *masked |= ATH9K_INT_FATAL;
165 } 165 }
166 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 166 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
167 ath_print(common, ATH_DBG_INTERRUPT, 167 ath_dbg(common, ATH_DBG_INTERRUPT,
168 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 168 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
169 } 169 }
170 170
171 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 171 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
index 4c94c9ed5f81..7c3334bd396e 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -18,6 +18,16 @@
18#include "hw-ops.h" 18#include "hw-ops.h"
19#include "ar9003_phy.h" 19#include "ar9003_phy.h"
20 20
21#define MPASS 3
22#define MAX_MEASUREMENT 8
23#define MAX_DIFFERENCE 10
24
25struct coeff {
26 int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MPASS];
27 int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MPASS];
28 int iqc_coeff[2];
29};
30
21enum ar9003_cal_types { 31enum ar9003_cal_types {
22 IQ_MISMATCH_CAL = BIT(0), 32 IQ_MISMATCH_CAL = BIT(0),
23 TEMP_COMP_CAL = BIT(1), 33 TEMP_COMP_CAL = BIT(1),
@@ -40,8 +50,8 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah,
40 currCal->calData->calCountMax); 50 currCal->calData->calCountMax);
41 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 51 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
42 52
43 ath_print(common, ATH_DBG_CALIBRATE, 53 ath_dbg(common, ATH_DBG_CALIBRATE,
44 "starting IQ Mismatch Calibration\n"); 54 "starting IQ Mismatch Calibration\n");
45 55
46 /* Kick-off cal */ 56 /* Kick-off cal */
47 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); 57 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
@@ -52,8 +62,8 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah,
52 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM, 62 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
53 AR_PHY_65NM_CH0_THERM_START, 1); 63 AR_PHY_65NM_CH0_THERM_START, 1);
54 64
55 ath_print(common, ATH_DBG_CALIBRATE, 65 ath_dbg(common, ATH_DBG_CALIBRATE,
56 "starting Temperature Compensation Calibration\n"); 66 "starting Temperature Compensation Calibration\n");
57 break; 67 break;
58 } 68 }
59} 69}
@@ -181,11 +191,11 @@ static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
181 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 191 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
182 ah->totalIqCorrMeas[i] += 192 ah->totalIqCorrMeas[i] +=
183 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 193 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
184 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, 194 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
185 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", 195 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
186 ah->cal_samples, i, ah->totalPowerMeasI[i], 196 ah->cal_samples, i, ah->totalPowerMeasI[i],
187 ah->totalPowerMeasQ[i], 197 ah->totalPowerMeasQ[i],
188 ah->totalIqCorrMeas[i]); 198 ah->totalIqCorrMeas[i]);
189 } 199 }
190} 200}
191 201
@@ -207,13 +217,13 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
207 powerMeasQ = ah->totalPowerMeasQ[i]; 217 powerMeasQ = ah->totalPowerMeasQ[i];
208 iqCorrMeas = ah->totalIqCorrMeas[i]; 218 iqCorrMeas = ah->totalIqCorrMeas[i];
209 219
210 ath_print(common, ATH_DBG_CALIBRATE, 220 ath_dbg(common, ATH_DBG_CALIBRATE,
211 "Starting IQ Cal and Correction for Chain %d\n", 221 "Starting IQ Cal and Correction for Chain %d\n",
212 i); 222 i);
213 223
214 ath_print(common, ATH_DBG_CALIBRATE, 224 ath_dbg(common, ATH_DBG_CALIBRATE,
215 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 225 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
216 i, ah->totalIqCorrMeas[i]); 226 i, ah->totalIqCorrMeas[i]);
217 227
218 iqCorrNeg = 0; 228 iqCorrNeg = 0;
219 229
@@ -222,12 +232,12 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
222 iqCorrNeg = 1; 232 iqCorrNeg = 1;
223 } 233 }
224 234
225 ath_print(common, ATH_DBG_CALIBRATE, 235 ath_dbg(common, ATH_DBG_CALIBRATE,
226 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); 236 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
227 ath_print(common, ATH_DBG_CALIBRATE, 237 ath_dbg(common, ATH_DBG_CALIBRATE,
228 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); 238 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
229 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", 239 ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
230 iqCorrNeg); 240 iqCorrNeg);
231 241
232 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256; 242 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
233 qCoffDenom = powerMeasQ / 64; 243 qCoffDenom = powerMeasQ / 64;
@@ -235,10 +245,10 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
235 if ((iCoffDenom != 0) && (qCoffDenom != 0)) { 245 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
236 iCoff = iqCorrMeas / iCoffDenom; 246 iCoff = iqCorrMeas / iCoffDenom;
237 qCoff = powerMeasI / qCoffDenom - 64; 247 qCoff = powerMeasI / qCoffDenom - 64;
238 ath_print(common, ATH_DBG_CALIBRATE, 248 ath_dbg(common, ATH_DBG_CALIBRATE,
239 "Chn %d iCoff = 0x%08x\n", i, iCoff); 249 "Chn %d iCoff = 0x%08x\n", i, iCoff);
240 ath_print(common, ATH_DBG_CALIBRATE, 250 ath_dbg(common, ATH_DBG_CALIBRATE,
241 "Chn %d qCoff = 0x%08x\n", i, qCoff); 251 "Chn %d qCoff = 0x%08x\n", i, qCoff);
242 252
243 /* Force bounds on iCoff */ 253 /* Force bounds on iCoff */
244 if (iCoff >= 63) 254 if (iCoff >= 63)
@@ -259,14 +269,13 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
259 iCoff = iCoff & 0x7f; 269 iCoff = iCoff & 0x7f;
260 qCoff = qCoff & 0x7f; 270 qCoff = qCoff & 0x7f;
261 271
262 ath_print(common, ATH_DBG_CALIBRATE, 272 ath_dbg(common, ATH_DBG_CALIBRATE,
263 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", 273 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
264 i, iCoff, qCoff); 274 i, iCoff, qCoff);
265 ath_print(common, ATH_DBG_CALIBRATE, 275 ath_dbg(common, ATH_DBG_CALIBRATE,
266 "Register offset (0x%04x) " 276 "Register offset (0x%04x) before update = 0x%x\n",
267 "before update = 0x%x\n", 277 offset_array[i],
268 offset_array[i], 278 REG_READ(ah, offset_array[i]));
269 REG_READ(ah, offset_array[i]));
270 279
271 REG_RMW_FIELD(ah, offset_array[i], 280 REG_RMW_FIELD(ah, offset_array[i],
272 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, 281 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
@@ -274,33 +283,29 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
274 REG_RMW_FIELD(ah, offset_array[i], 283 REG_RMW_FIELD(ah, offset_array[i],
275 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, 284 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
276 qCoff); 285 qCoff);
277 ath_print(common, ATH_DBG_CALIBRATE, 286 ath_dbg(common, ATH_DBG_CALIBRATE,
278 "Register offset (0x%04x) QI COFF " 287 "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n",
279 "(bitfields 0x%08x) after update = 0x%x\n", 288 offset_array[i],
280 offset_array[i], 289 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
281 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, 290 REG_READ(ah, offset_array[i]));
282 REG_READ(ah, offset_array[i])); 291 ath_dbg(common, ATH_DBG_CALIBRATE,
283 ath_print(common, ATH_DBG_CALIBRATE, 292 "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n",
284 "Register offset (0x%04x) QQ COFF " 293 offset_array[i],
285 "(bitfields 0x%08x) after update = 0x%x\n", 294 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
286 offset_array[i], 295 REG_READ(ah, offset_array[i]));
287 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, 296
288 REG_READ(ah, offset_array[i])); 297 ath_dbg(common, ATH_DBG_CALIBRATE,
289 298 "IQ Cal and Correction done for Chain %d\n", i);
290 ath_print(common, ATH_DBG_CALIBRATE,
291 "IQ Cal and Correction done for Chain %d\n",
292 i);
293 } 299 }
294 } 300 }
295 301
296 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, 302 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
297 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); 303 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
298 ath_print(common, ATH_DBG_CALIBRATE, 304 ath_dbg(common, ATH_DBG_CALIBRATE,
299 "IQ Cal and Correction (offset 0x%04x) enabled " 305 "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n",
300 "(bit position 0x%08x). New Value 0x%08x\n", 306 (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
301 (unsigned) (AR_PHY_RX_IQCAL_CORR_B0), 307 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
302 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE, 308 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
303 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
304} 309}
305 310
306static const struct ath9k_percal_data iq_cal_single_sample = { 311static const struct ath9k_percal_data iq_cal_single_sample = {
@@ -340,7 +345,7 @@ static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
340 f2 = (f1 * f1 + f3 * f3) / result_shift; 345 f2 = (f1 * f1 + f3 * f3) / result_shift;
341 346
342 if (!f2) { 347 if (!f2) {
343 ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n"); 348 ath_dbg(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
344 return false; 349 return false;
345 } 350 }
346 351
@@ -461,11 +466,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
461 466
462 if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) || 467 if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
463 (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) { 468 (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
464 ath_print(common, ATH_DBG_CALIBRATE, 469 ath_dbg(common, ATH_DBG_CALIBRATE,
465 "Divide by 0:\na0_d0=%d\n" 470 "Divide by 0:\n"
466 "a0_d1=%d\na2_d0=%d\na1_d1=%d\n", 471 "a0_d0=%d\n"
467 i2_p_q2_a0_d0, i2_p_q2_a0_d1, 472 "a0_d1=%d\n"
468 i2_p_q2_a1_d0, i2_p_q2_a1_d1); 473 "a2_d0=%d\n"
474 "a1_d1=%d\n",
475 i2_p_q2_a0_d0, i2_p_q2_a0_d1,
476 i2_p_q2_a1_d0, i2_p_q2_a1_d1);
469 return false; 477 return false;
470 } 478 }
471 479
@@ -498,9 +506,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
498 mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2); 506 mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
499 507
500 if ((mag1 == 0) || (mag2 == 0)) { 508 if ((mag1 == 0) || (mag2 == 0)) {
501 ath_print(common, ATH_DBG_CALIBRATE, 509 ath_dbg(common, ATH_DBG_CALIBRATE,
502 "Divide by 0: mag1=%d, mag2=%d\n", 510 "Divide by 0: mag1=%d, mag2=%d\n",
503 mag1, mag2); 511 mag1, mag2);
504 return false; 512 return false;
505 } 513 }
506 514
@@ -517,8 +525,8 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
517 mag_a0_d0, phs_a0_d0, 525 mag_a0_d0, phs_a0_d0,
518 mag_a1_d0, 526 mag_a1_d0,
519 phs_a1_d0, solved_eq)) { 527 phs_a1_d0, solved_eq)) {
520 ath_print(common, ATH_DBG_CALIBRATE, 528 ath_dbg(common, ATH_DBG_CALIBRATE,
521 "Call to ar9003_hw_solve_iq_cal() failed.\n"); 529 "Call to ar9003_hw_solve_iq_cal() failed.\n");
522 return false; 530 return false;
523 } 531 }
524 532
@@ -527,14 +535,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
527 mag_rx = solved_eq[2]; 535 mag_rx = solved_eq[2];
528 phs_rx = solved_eq[3]; 536 phs_rx = solved_eq[3];
529 537
530 ath_print(common, ATH_DBG_CALIBRATE, 538 ath_dbg(common, ATH_DBG_CALIBRATE,
531 "chain %d: mag mismatch=%d phase mismatch=%d\n", 539 "chain %d: mag mismatch=%d phase mismatch=%d\n",
532 chain_idx, mag_tx/res_scale, phs_tx/res_scale); 540 chain_idx, mag_tx/res_scale, phs_tx/res_scale);
533 541
534 if (res_scale == mag_tx) { 542 if (res_scale == mag_tx) {
535 ath_print(common, ATH_DBG_CALIBRATE, 543 ath_dbg(common, ATH_DBG_CALIBRATE,
536 "Divide by 0: mag_tx=%d, res_scale=%d\n", 544 "Divide by 0: mag_tx=%d, res_scale=%d\n",
537 mag_tx, res_scale); 545 mag_tx, res_scale);
538 return false; 546 return false;
539 } 547 }
540 548
@@ -545,9 +553,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
545 q_q_coff = (mag_corr_tx * 128 / res_scale); 553 q_q_coff = (mag_corr_tx * 128 / res_scale);
546 q_i_coff = (phs_corr_tx * 256 / res_scale); 554 q_i_coff = (phs_corr_tx * 256 / res_scale);
547 555
548 ath_print(common, ATH_DBG_CALIBRATE, 556 ath_dbg(common, ATH_DBG_CALIBRATE,
549 "tx chain %d: mag corr=%d phase corr=%d\n", 557 "tx chain %d: mag corr=%d phase corr=%d\n",
550 chain_idx, q_q_coff, q_i_coff); 558 chain_idx, q_q_coff, q_i_coff);
551 559
552 if (q_i_coff < -63) 560 if (q_i_coff < -63)
553 q_i_coff = -63; 561 q_i_coff = -63;
@@ -560,14 +568,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
560 568
561 iqc_coeff[0] = (q_q_coff * 128) + q_i_coff; 569 iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
562 570
563 ath_print(common, ATH_DBG_CALIBRATE, 571 ath_dbg(common, ATH_DBG_CALIBRATE,
564 "tx chain %d: iq corr coeff=%x\n", 572 "tx chain %d: iq corr coeff=%x\n",
565 chain_idx, iqc_coeff[0]); 573 chain_idx, iqc_coeff[0]);
566 574
567 if (-mag_rx == res_scale) { 575 if (-mag_rx == res_scale) {
568 ath_print(common, ATH_DBG_CALIBRATE, 576 ath_dbg(common, ATH_DBG_CALIBRATE,
569 "Divide by 0: mag_rx=%d, res_scale=%d\n", 577 "Divide by 0: mag_rx=%d, res_scale=%d\n",
570 mag_rx, res_scale); 578 mag_rx, res_scale);
571 return false; 579 return false;
572 } 580 }
573 581
@@ -578,9 +586,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
578 q_q_coff = (mag_corr_rx * 128 / res_scale); 586 q_q_coff = (mag_corr_rx * 128 / res_scale);
579 q_i_coff = (phs_corr_rx * 256 / res_scale); 587 q_i_coff = (phs_corr_rx * 256 / res_scale);
580 588
581 ath_print(common, ATH_DBG_CALIBRATE, 589 ath_dbg(common, ATH_DBG_CALIBRATE,
582 "rx chain %d: mag corr=%d phase corr=%d\n", 590 "rx chain %d: mag corr=%d phase corr=%d\n",
583 chain_idx, q_q_coff, q_i_coff); 591 chain_idx, q_q_coff, q_i_coff);
584 592
585 if (q_i_coff < -63) 593 if (q_i_coff < -63)
586 q_i_coff = -63; 594 q_i_coff = -63;
@@ -593,9 +601,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
593 601
594 iqc_coeff[1] = (q_q_coff * 128) + q_i_coff; 602 iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
595 603
596 ath_print(common, ATH_DBG_CALIBRATE, 604 ath_dbg(common, ATH_DBG_CALIBRATE,
597 "rx chain %d: iq corr coeff=%x\n", 605 "rx chain %d: iq corr coeff=%x\n",
598 chain_idx, iqc_coeff[1]); 606 chain_idx, iqc_coeff[1]);
599 607
600 return true; 608 return true;
601} 609}
@@ -608,11 +616,6 @@ static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
608 AR_PHY_TX_IQCAL_STATUS_B1, 616 AR_PHY_TX_IQCAL_STATUS_B1,
609 AR_PHY_TX_IQCAL_STATUS_B2, 617 AR_PHY_TX_IQCAL_STATUS_B2,
610 }; 618 };
611 static const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
612 AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
613 AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
614 AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
615 };
616 static const u32 rx_corr[AR9300_MAX_CHAINS] = { 619 static const u32 rx_corr[AR9300_MAX_CHAINS] = {
617 AR_PHY_RX_IQCAL_CORR_B0, 620 AR_PHY_RX_IQCAL_CORR_B0,
618 AR_PHY_RX_IQCAL_CORR_B1, 621 AR_PHY_RX_IQCAL_CORR_B1,
@@ -623,11 +626,16 @@ static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
623 AR_PHY_CHAN_INFO_TAB_1, 626 AR_PHY_CHAN_INFO_TAB_1,
624 AR_PHY_CHAN_INFO_TAB_2, 627 AR_PHY_CHAN_INFO_TAB_2,
625 }; 628 };
629 u32 tx_corr_coeff[AR9300_MAX_CHAINS];
626 s32 iq_res[6]; 630 s32 iq_res[6];
627 s32 iqc_coeff[2]; 631 s32 iqc_coeff[2];
628 s32 i, j; 632 s32 i, j;
629 u32 num_chains = 0; 633 u32 num_chains = 0;
630 634
635 tx_corr_coeff[0] = AR_PHY_TX_IQCAL_CORR_COEFF_B0(0);
636 tx_corr_coeff[1] = AR_PHY_TX_IQCAL_CORR_COEFF_B1(0);
637 tx_corr_coeff[2] = AR_PHY_TX_IQCAL_CORR_COEFF_B2(0);
638
631 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 639 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
632 if (ah->txchainmask & (1 << i)) 640 if (ah->txchainmask & (1 << i))
633 num_chains++; 641 num_chains++;
@@ -643,19 +651,19 @@ static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
643 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START, 651 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
644 AR_PHY_TX_IQCAL_START_DO_CAL, 652 AR_PHY_TX_IQCAL_START_DO_CAL,
645 0, AH_WAIT_TIMEOUT)) { 653 0, AH_WAIT_TIMEOUT)) {
646 ath_print(common, ATH_DBG_CALIBRATE, 654 ath_dbg(common, ATH_DBG_CALIBRATE,
647 "Tx IQ Cal not complete.\n"); 655 "Tx IQ Cal not complete.\n");
648 goto TX_IQ_CAL_FAILED; 656 goto TX_IQ_CAL_FAILED;
649 } 657 }
650 658
651 for (i = 0; i < num_chains; i++) { 659 for (i = 0; i < num_chains; i++) {
652 ath_print(common, ATH_DBG_CALIBRATE, 660 ath_dbg(common, ATH_DBG_CALIBRATE,
653 "Doing Tx IQ Cal for chain %d.\n", i); 661 "Doing Tx IQ Cal for chain %d.\n", i);
654 662
655 if (REG_READ(ah, txiqcal_status[i]) & 663 if (REG_READ(ah, txiqcal_status[i]) &
656 AR_PHY_TX_IQCAL_STATUS_FAILED) { 664 AR_PHY_TX_IQCAL_STATUS_FAILED) {
657 ath_print(common, ATH_DBG_CALIBRATE, 665 ath_dbg(common, ATH_DBG_CALIBRATE,
658 "Tx IQ Cal failed for chain %d.\n", i); 666 "Tx IQ Cal failed for chain %d.\n", i);
659 goto TX_IQ_CAL_FAILED; 667 goto TX_IQ_CAL_FAILED;
660 } 668 }
661 669
@@ -677,20 +685,20 @@ static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
677 chan_info_tab[i] + 685 chan_info_tab[i] +
678 offset); 686 offset);
679 687
680 ath_print(common, ATH_DBG_CALIBRATE, 688 ath_dbg(common, ATH_DBG_CALIBRATE,
681 "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n", 689 "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
682 idx, iq_res[idx], idx+1, iq_res[idx+1]); 690 idx, iq_res[idx], idx+1, iq_res[idx+1]);
683 } 691 }
684 692
685 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) { 693 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
686 ath_print(common, ATH_DBG_CALIBRATE, 694 ath_dbg(common, ATH_DBG_CALIBRATE,
687 "Failed in calculation of IQ correction.\n"); 695 "Failed in calculation of IQ correction.\n");
688 goto TX_IQ_CAL_FAILED; 696 goto TX_IQ_CAL_FAILED;
689 } 697 }
690 698
691 ath_print(common, ATH_DBG_CALIBRATE, 699 ath_dbg(common, ATH_DBG_CALIBRATE,
692 "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n", 700 "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
693 iqc_coeff[0], iqc_coeff[1]); 701 iqc_coeff[0], iqc_coeff[1]);
694 702
695 REG_RMW_FIELD(ah, tx_corr_coeff[i], 703 REG_RMW_FIELD(ah, tx_corr_coeff[i],
696 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, 704 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
@@ -711,9 +719,232 @@ static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
711 return; 719 return;
712 720
713TX_IQ_CAL_FAILED: 721TX_IQ_CAL_FAILED:
714 ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n"); 722 ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
723}
724
725static bool ar9003_hw_compute_closest_pass_and_avg(int *mp_coeff, int *mp_avg)
726{
727 int diff[MPASS];
728
729 diff[0] = abs(mp_coeff[0] - mp_coeff[1]);
730 diff[1] = abs(mp_coeff[1] - mp_coeff[2]);
731 diff[2] = abs(mp_coeff[2] - mp_coeff[0]);
732
733 if (diff[0] > MAX_MEASUREMENT &&
734 diff[1] > MAX_MEASUREMENT &&
735 diff[2] > MAX_MEASUREMENT)
736 return false;
737
738 if (diff[0] <= diff[1] && diff[0] <= diff[2])
739 *mp_avg = (mp_coeff[0] + mp_coeff[1]) / 2;
740 else if (diff[1] <= diff[2])
741 *mp_avg = (mp_coeff[1] + mp_coeff[2]) / 2;
742 else
743 *mp_avg = (mp_coeff[2] + mp_coeff[0]) / 2;
744
745 return true;
715} 746}
716 747
748static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
749 u8 num_chains,
750 struct coeff *coeff)
751{
752 struct ath_common *common = ath9k_hw_common(ah);
753 int i, im, nmeasurement;
754 int magnitude, phase;
755 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
756
757 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
758 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
759 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
760 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
761 if (!AR_SREV_9485(ah)) {
762 tx_corr_coeff[i * 2][1] =
763 tx_corr_coeff[(i * 2) + 1][1] =
764 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
765
766 tx_corr_coeff[i * 2][2] =
767 tx_corr_coeff[(i * 2) + 1][2] =
768 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
769 }
770 }
771
772 /* Load the average of 2 passes */
773 for (i = 0; i < num_chains; i++) {
774 if (AR_SREV_9485(ah))
775 nmeasurement = REG_READ_FIELD(ah,
776 AR_PHY_TX_IQCAL_STATUS_B0_9485,
777 AR_PHY_CALIBRATED_GAINS_0);
778 else
779 nmeasurement = REG_READ_FIELD(ah,
780 AR_PHY_TX_IQCAL_STATUS_B0,
781 AR_PHY_CALIBRATED_GAINS_0);
782
783 if (nmeasurement > MAX_MEASUREMENT)
784 nmeasurement = MAX_MEASUREMENT;
785
786 for (im = 0; im < nmeasurement; im++) {
787 /*
788 * Determine which 2 passes are closest and compute avg
789 * magnitude
790 */
791 if (!ar9003_hw_compute_closest_pass_and_avg(coeff->mag_coeff[i][im],
792 &magnitude))
793 goto disable_txiqcal;
794
795 /*
796 * Determine which 2 passes are closest and compute avg
797 * phase
798 */
799 if (!ar9003_hw_compute_closest_pass_and_avg(coeff->phs_coeff[i][im],
800 &phase))
801 goto disable_txiqcal;
802
803 coeff->iqc_coeff[0] = (magnitude & 0x7f) |
804 ((phase & 0x7f) << 7);
805
806 if ((im % 2) == 0)
807 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
808 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
809 coeff->iqc_coeff[0]);
810 else
811 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
812 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
813 coeff->iqc_coeff[0]);
814 }
815 }
816
817 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
818 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
819 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
820 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
821
822 return;
823
824disable_txiqcal:
825 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
826 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x0);
827 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
828 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x0);
829
830 ath_dbg(common, ATH_DBG_CALIBRATE, "TX IQ Cal disabled\n");
831}
832
833static void ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
834{
835 u8 tx_gain_forced;
836
837 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1_9485,
838 AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
839 tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
840 AR_PHY_TXGAIN_FORCE);
841 if (tx_gain_forced)
842 REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
843 AR_PHY_TXGAIN_FORCE, 0);
844
845 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START_9485,
846 AR_PHY_TX_IQCAL_START_DO_CAL_9485, 1);
847}
848
849static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah)
850{
851 struct ath_common *common = ath9k_hw_common(ah);
852 const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
853 AR_PHY_TX_IQCAL_STATUS_B0_9485,
854 AR_PHY_TX_IQCAL_STATUS_B1,
855 AR_PHY_TX_IQCAL_STATUS_B2,
856 };
857 const u_int32_t chan_info_tab[] = {
858 AR_PHY_CHAN_INFO_TAB_0,
859 AR_PHY_CHAN_INFO_TAB_1,
860 AR_PHY_CHAN_INFO_TAB_2,
861 };
862 struct coeff coeff;
863 s32 iq_res[6];
864 u8 num_chains = 0;
865 int i, ip, im, j;
866 int nmeasurement;
867
868 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
869 if (ah->txchainmask & (1 << i))
870 num_chains++;
871 }
872
873 for (ip = 0; ip < MPASS; ip++) {
874 for (i = 0; i < num_chains; i++) {
875 nmeasurement = REG_READ_FIELD(ah,
876 AR_PHY_TX_IQCAL_STATUS_B0_9485,
877 AR_PHY_CALIBRATED_GAINS_0);
878 if (nmeasurement > MAX_MEASUREMENT)
879 nmeasurement = MAX_MEASUREMENT;
880
881 for (im = 0; im < nmeasurement; im++) {
882 ath_dbg(common, ATH_DBG_CALIBRATE,
883 "Doing Tx IQ Cal for chain %d.\n", i);
884
885 if (REG_READ(ah, txiqcal_status[i]) &
886 AR_PHY_TX_IQCAL_STATUS_FAILED) {
887 ath_dbg(common, ATH_DBG_CALIBRATE,
888 "Tx IQ Cal failed for chain %d.\n", i);
889 goto tx_iqcal_fail;
890 }
891
892 for (j = 0; j < 3; j++) {
893 u32 idx = 2 * j, offset = 4 * (3 * im + j);
894
895 REG_RMW_FIELD(ah,
896 AR_PHY_CHAN_INFO_MEMORY,
897 AR_PHY_CHAN_INFO_TAB_S2_READ,
898 0);
899
900 /* 32 bits */
901 iq_res[idx] = REG_READ(ah,
902 chan_info_tab[i] +
903 offset);
904
905 REG_RMW_FIELD(ah,
906 AR_PHY_CHAN_INFO_MEMORY,
907 AR_PHY_CHAN_INFO_TAB_S2_READ,
908 1);
909
910 /* 16 bits */
911 iq_res[idx + 1] = 0xffff & REG_READ(ah,
912 chan_info_tab[i] + offset);
913
914 ath_dbg(common, ATH_DBG_CALIBRATE,
915 "IQ RES[%d]=0x%x"
916 "IQ_RES[%d]=0x%x\n",
917 idx, iq_res[idx], idx + 1,
918 iq_res[idx + 1]);
919 }
920
921 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
922 coeff.iqc_coeff)) {
923 ath_dbg(common, ATH_DBG_CALIBRATE,
924 "Failed in calculation of IQ correction.\n");
925 goto tx_iqcal_fail;
926 }
927
928 coeff.mag_coeff[i][im][ip] =
929 coeff.iqc_coeff[0] & 0x7f;
930 coeff.phs_coeff[i][im][ip] =
931 (coeff.iqc_coeff[0] >> 7) & 0x7f;
932
933 if (coeff.mag_coeff[i][im][ip] > 63)
934 coeff.mag_coeff[i][im][ip] -= 128;
935 if (coeff.phs_coeff[i][im][ip] > 63)
936 coeff.phs_coeff[i][im][ip] -= 128;
937 }
938 }
939 }
940 ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains, &coeff);
941
942 return;
943
944tx_iqcal_fail:
945 ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
946 return;
947}
717static bool ar9003_hw_init_cal(struct ath_hw *ah, 948static bool ar9003_hw_init_cal(struct ath_hw *ah,
718 struct ath9k_channel *chan) 949 struct ath9k_channel *chan)
719{ 950{
@@ -721,9 +952,11 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
721 int val; 952 int val;
722 953
723 val = REG_READ(ah, AR_ENT_OTP); 954 val = REG_READ(ah, AR_ENT_OTP);
724 ath_print(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val); 955 ath_dbg(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
725 956
726 if (val & AR_ENT_OTP_CHAIN2_DISABLE) 957 if (AR_SREV_9485(ah))
958 ar9003_hw_set_chain_masks(ah, 0x1, 0x1);
959 else if (val & AR_ENT_OTP_CHAIN2_DISABLE)
727 ar9003_hw_set_chain_masks(ah, 0x3, 0x3); 960 ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
728 else 961 else
729 /* 962 /*
@@ -733,7 +966,11 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
733 ar9003_hw_set_chain_masks(ah, 0x7, 0x7); 966 ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
734 967
735 /* Do Tx IQ Calibration */ 968 /* Do Tx IQ Calibration */
736 ar9003_hw_tx_iq_cal(ah); 969 if (AR_SREV_9485(ah))
970 ar9003_hw_tx_iq_cal_run(ah);
971 else
972 ar9003_hw_tx_iq_cal(ah);
973
737 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 974 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
738 udelay(5); 975 udelay(5);
739 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 976 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
@@ -746,12 +983,14 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
746 /* Poll for offset calibration complete */ 983 /* Poll for offset calibration complete */
747 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 984 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
748 0, AH_WAIT_TIMEOUT)) { 985 0, AH_WAIT_TIMEOUT)) {
749 ath_print(common, ATH_DBG_CALIBRATE, 986 ath_dbg(common, ATH_DBG_CALIBRATE,
750 "offset calibration failed to " 987 "offset calibration failed to complete in 1ms; noisy environment?\n");
751 "complete in 1ms; noisy environment?\n");
752 return false; 988 return false;
753 } 989 }
754 990
991 if (AR_SREV_9485(ah))
992 ar9003_hw_tx_iq_cal_post_proc(ah);
993
755 /* Revert chainmasks to their original values before NF cal */ 994 /* Revert chainmasks to their original values before NF cal */
756 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 995 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
757 996
@@ -764,15 +1003,15 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
764 if (ah->supp_cals & IQ_MISMATCH_CAL) { 1003 if (ah->supp_cals & IQ_MISMATCH_CAL) {
765 INIT_CAL(&ah->iq_caldata); 1004 INIT_CAL(&ah->iq_caldata);
766 INSERT_CAL(ah, &ah->iq_caldata); 1005 INSERT_CAL(ah, &ah->iq_caldata);
767 ath_print(common, ATH_DBG_CALIBRATE, 1006 ath_dbg(common, ATH_DBG_CALIBRATE,
768 "enabling IQ Calibration.\n"); 1007 "enabling IQ Calibration.\n");
769 } 1008 }
770 1009
771 if (ah->supp_cals & TEMP_COMP_CAL) { 1010 if (ah->supp_cals & TEMP_COMP_CAL) {
772 INIT_CAL(&ah->tempCompCalData); 1011 INIT_CAL(&ah->tempCompCalData);
773 INSERT_CAL(ah, &ah->tempCompCalData); 1012 INSERT_CAL(ah, &ah->tempCompCalData);
774 ath_print(common, ATH_DBG_CALIBRATE, 1013 ath_dbg(common, ATH_DBG_CALIBRATE,
775 "enabling Temperature Compensation Calibration.\n"); 1014 "enabling Temperature Compensation Calibration.\n");
776 } 1015 }
777 1016
778 /* Initialize current pointer to first element in list */ 1017 /* Initialize current pointer to first element in list */
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index 73a8014cacb2..a16b3dae5b34 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -3035,6 +3035,8 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3035 return !!(pBase->featureEnable & BIT(5)); 3035 return !!(pBase->featureEnable & BIT(5));
3036 case EEP_CHAIN_MASK_REDUCE: 3036 case EEP_CHAIN_MASK_REDUCE:
3037 return (pBase->miscConfiguration >> 0x3) & 0x1; 3037 return (pBase->miscConfiguration >> 0x3) & 0x1;
3038 case EEP_ANT_DIV_CTL1:
3039 return le32_to_cpu(eep->base_ext1.ant_div_control);
3038 default: 3040 default:
3039 return 0; 3041 return 0;
3040 } 3042 }
@@ -3073,8 +3075,8 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3073 int i; 3075 int i;
3074 3076
3075 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { 3077 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3076 ath_print(common, ATH_DBG_EEPROM, 3078 ath_dbg(common, ATH_DBG_EEPROM,
3077 "eeprom address not in range\n"); 3079 "eeprom address not in range\n");
3078 return false; 3080 return false;
3079 } 3081 }
3080 3082
@@ -3105,8 +3107,8 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3105 return true; 3107 return true;
3106 3108
3107error: 3109error:
3108 ath_print(common, ATH_DBG_EEPROM, 3110 ath_dbg(common, ATH_DBG_EEPROM,
3109 "unable to read eeprom region at offset %d\n", address); 3111 "unable to read eeprom region at offset %d\n", address);
3110 return false; 3112 return false;
3111} 3113}
3112 3114
@@ -3190,17 +3192,15 @@ static bool ar9300_uncompress_block(struct ath_hw *ah,
3190 length &= 0xff; 3192 length &= 0xff;
3191 3193
3192 if (length > 0 && spot >= 0 && spot+length <= mdataSize) { 3194 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3193 ath_print(common, ATH_DBG_EEPROM, 3195 ath_dbg(common, ATH_DBG_EEPROM,
3194 "Restore at %d: spot=%d " 3196 "Restore at %d: spot=%d offset=%d length=%d\n",
3195 "offset=%d length=%d\n", 3197 it, spot, offset, length);
3196 it, spot, offset, length);
3197 memcpy(&mptr[spot], &block[it+2], length); 3198 memcpy(&mptr[spot], &block[it+2], length);
3198 spot += length; 3199 spot += length;
3199 } else if (length > 0) { 3200 } else if (length > 0) {
3200 ath_print(common, ATH_DBG_EEPROM, 3201 ath_dbg(common, ATH_DBG_EEPROM,
3201 "Bad restore at %d: spot=%d " 3202 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3202 "offset=%d length=%d\n", 3203 it, spot, offset, length);
3203 it, spot, offset, length);
3204 return false; 3204 return false;
3205 } 3205 }
3206 } 3206 }
@@ -3221,14 +3221,15 @@ static int ar9300_compress_decision(struct ath_hw *ah,
3221 switch (code) { 3221 switch (code) {
3222 case _CompressNone: 3222 case _CompressNone:
3223 if (length != mdata_size) { 3223 if (length != mdata_size) {
3224 ath_print(common, ATH_DBG_EEPROM, 3224 ath_dbg(common, ATH_DBG_EEPROM,
3225 "EEPROM structure size mismatch" 3225 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3226 "memory=%d eeprom=%d\n", mdata_size, length); 3226 mdata_size, length);
3227 return -1; 3227 return -1;
3228 } 3228 }
3229 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length); 3229 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3230 ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:" 3230 ath_dbg(common, ATH_DBG_EEPROM,
3231 " uncompressed, length %d\n", it, length); 3231 "restored eeprom %d: uncompressed, length %d\n",
3232 it, length);
3232 break; 3233 break;
3233 case _CompressBlock: 3234 case _CompressBlock:
3234 if (reference == 0) { 3235 if (reference == 0) {
@@ -3236,22 +3237,22 @@ static int ar9300_compress_decision(struct ath_hw *ah,
3236 } else { 3237 } else {
3237 eep = ar9003_eeprom_struct_find_by_id(reference); 3238 eep = ar9003_eeprom_struct_find_by_id(reference);
3238 if (eep == NULL) { 3239 if (eep == NULL) {
3239 ath_print(common, ATH_DBG_EEPROM, 3240 ath_dbg(common, ATH_DBG_EEPROM,
3240 "cant find reference eeprom" 3241 "cant find reference eeprom struct %d\n",
3241 "struct %d\n", reference); 3242 reference);
3242 return -1; 3243 return -1;
3243 } 3244 }
3244 memcpy(mptr, eep, mdata_size); 3245 memcpy(mptr, eep, mdata_size);
3245 } 3246 }
3246 ath_print(common, ATH_DBG_EEPROM, 3247 ath_dbg(common, ATH_DBG_EEPROM,
3247 "restore eeprom %d: block, reference %d," 3248 "restore eeprom %d: block, reference %d, length %d\n",
3248 " length %d\n", it, reference, length); 3249 it, reference, length);
3249 ar9300_uncompress_block(ah, mptr, mdata_size, 3250 ar9300_uncompress_block(ah, mptr, mdata_size,
3250 (u8 *) (word + COMP_HDR_LEN), length); 3251 (u8 *) (word + COMP_HDR_LEN), length);
3251 break; 3252 break;
3252 default: 3253 default:
3253 ath_print(common, ATH_DBG_EEPROM, "unknown compression" 3254 ath_dbg(common, ATH_DBG_EEPROM,
3254 " code %d\n", code); 3255 "unknown compression code %d\n", code);
3255 return -1; 3256 return -1;
3256 } 3257 }
3257 return 0; 3258 return 0;
@@ -3321,27 +3322,30 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3321 memcpy(mptr, &ar9300_default, mdata_size); 3322 memcpy(mptr, &ar9300_default, mdata_size);
3322 3323
3323 read = ar9300_read_eeprom; 3324 read = ar9300_read_eeprom;
3324 cptr = AR9300_BASE_ADDR; 3325 if (AR_SREV_9485(ah))
3325 ath_print(common, ATH_DBG_EEPROM, 3326 cptr = AR9300_BASE_ADDR_4K;
3327 else
3328 cptr = AR9300_BASE_ADDR;
3329 ath_dbg(common, ATH_DBG_EEPROM,
3326 "Trying EEPROM accesss at Address 0x%04x\n", cptr); 3330 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3327 if (ar9300_check_eeprom_header(ah, read, cptr)) 3331 if (ar9300_check_eeprom_header(ah, read, cptr))
3328 goto found; 3332 goto found;
3329 3333
3330 cptr = AR9300_BASE_ADDR_512; 3334 cptr = AR9300_BASE_ADDR_512;
3331 ath_print(common, ATH_DBG_EEPROM, 3335 ath_dbg(common, ATH_DBG_EEPROM,
3332 "Trying EEPROM accesss at Address 0x%04x\n", cptr); 3336 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3333 if (ar9300_check_eeprom_header(ah, read, cptr)) 3337 if (ar9300_check_eeprom_header(ah, read, cptr))
3334 goto found; 3338 goto found;
3335 3339
3336 read = ar9300_read_otp; 3340 read = ar9300_read_otp;
3337 cptr = AR9300_BASE_ADDR; 3341 cptr = AR9300_BASE_ADDR;
3338 ath_print(common, ATH_DBG_EEPROM, 3342 ath_dbg(common, ATH_DBG_EEPROM,
3339 "Trying OTP accesss at Address 0x%04x\n", cptr); 3343 "Trying OTP accesss at Address 0x%04x\n", cptr);
3340 if (ar9300_check_eeprom_header(ah, read, cptr)) 3344 if (ar9300_check_eeprom_header(ah, read, cptr))
3341 goto found; 3345 goto found;
3342 3346
3343 cptr = AR9300_BASE_ADDR_512; 3347 cptr = AR9300_BASE_ADDR_512;
3344 ath_print(common, ATH_DBG_EEPROM, 3348 ath_dbg(common, ATH_DBG_EEPROM,
3345 "Trying OTP accesss at Address 0x%04x\n", cptr); 3349 "Trying OTP accesss at Address 0x%04x\n", cptr);
3346 if (ar9300_check_eeprom_header(ah, read, cptr)) 3350 if (ar9300_check_eeprom_header(ah, read, cptr))
3347 goto found; 3351 goto found;
@@ -3349,7 +3353,7 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3349 goto fail; 3353 goto fail;
3350 3354
3351found: 3355found:
3352 ath_print(common, ATH_DBG_EEPROM, "Found valid EEPROM data"); 3356 ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
3353 3357
3354 for (it = 0; it < MSTATE; it++) { 3358 for (it = 0; it < MSTATE; it++) {
3355 if (!read(ah, cptr, word, COMP_HDR_LEN)) 3359 if (!read(ah, cptr, word, COMP_HDR_LEN))
@@ -3360,13 +3364,13 @@ found:
3360 3364
3361 ar9300_comp_hdr_unpack(word, &code, &reference, 3365 ar9300_comp_hdr_unpack(word, &code, &reference,
3362 &length, &major, &minor); 3366 &length, &major, &minor);
3363 ath_print(common, ATH_DBG_EEPROM, 3367 ath_dbg(common, ATH_DBG_EEPROM,
3364 "Found block at %x: code=%d ref=%d" 3368 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3365 "length=%d major=%d minor=%d\n", cptr, code, 3369 cptr, code, reference, length, major, minor);
3366 reference, length, major, minor); 3370 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3367 if (length >= 1024) { 3371 (AR_SREV_9485(ah) && length >= (4 * 1024))) {
3368 ath_print(common, ATH_DBG_EEPROM, 3372 ath_dbg(common, ATH_DBG_EEPROM,
3369 "Skipping bad header\n"); 3373 "Skipping bad header\n");
3370 cptr -= COMP_HDR_LEN; 3374 cptr -= COMP_HDR_LEN;
3371 continue; 3375 continue;
3372 } 3376 }
@@ -3376,14 +3380,14 @@ found:
3376 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); 3380 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3377 mchecksum = word[COMP_HDR_LEN + osize] | 3381 mchecksum = word[COMP_HDR_LEN + osize] |
3378 (word[COMP_HDR_LEN + osize + 1] << 8); 3382 (word[COMP_HDR_LEN + osize + 1] << 8);
3379 ath_print(common, ATH_DBG_EEPROM, 3383 ath_dbg(common, ATH_DBG_EEPROM,
3380 "checksum %x %x\n", checksum, mchecksum); 3384 "checksum %x %x\n", checksum, mchecksum);
3381 if (checksum == mchecksum) { 3385 if (checksum == mchecksum) {
3382 ar9300_compress_decision(ah, it, code, reference, mptr, 3386 ar9300_compress_decision(ah, it, code, reference, mptr,
3383 word, length, mdata_size); 3387 word, length, mdata_size);
3384 } else { 3388 } else {
3385 ath_print(common, ATH_DBG_EEPROM, 3389 ath_dbg(common, ATH_DBG_EEPROM,
3386 "skipping block with bad checksum\n"); 3390 "skipping block with bad checksum\n");
3387 } 3391 }
3388 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); 3392 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3389 } 3393 }
@@ -3449,9 +3453,15 @@ static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3449static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) 3453static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3450{ 3454{
3451 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz); 3455 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3452 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3456
3453 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2); 3457 if (AR_SREV_9485(ah))
3454 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1); 3458 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3459 else {
3460 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3461 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB,
3462 bias >> 2);
3463 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
3464 }
3455} 3465}
3456 3466
3457static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) 3467static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
@@ -3506,11 +3516,25 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3506 value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz); 3516 value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
3507 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value); 3517 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
3508 3518
3509 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz); 3519 if (!AR_SREV_9485(ah)) {
3510 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value); 3520 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3521 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL,
3522 value);
3523
3524 value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
3525 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL,
3526 value);
3527 }
3511 3528
3512 value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz); 3529 if (AR_SREV_9485(ah)) {
3513 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value); 3530 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3531 REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL,
3532 value);
3533 REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE,
3534 value >> 6);
3535 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE,
3536 value >> 7);
3537 }
3514} 3538}
3515 3539
3516static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) 3540static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
@@ -3630,28 +3654,101 @@ static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3630 } 3654 }
3631} 3655}
3632 3656
3657static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3658{
3659 int timeout = 100;
3660
3661 while (pmu_set != REG_READ(ah, pmu_reg)) {
3662 if (timeout-- == 0)
3663 return false;
3664 REG_WRITE(ah, pmu_reg, pmu_set);
3665 udelay(10);
3666 }
3667
3668 return true;
3669}
3670
3633static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) 3671static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3634{ 3672{
3635 int internal_regulator = 3673 int internal_regulator =
3636 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR); 3674 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3637 3675
3638 if (internal_regulator) { 3676 if (internal_regulator) {
3639 /* Internal regulator is ON. Write swreg register. */ 3677 if (AR_SREV_9485(ah)) {
3640 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); 3678 int reg_pmu_set;
3641 REG_WRITE(ah, AR_RTC_REG_CONTROL1, 3679
3642 REG_READ(ah, AR_RTC_REG_CONTROL1) & 3680 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3643 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM)); 3681 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3644 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg); 3682 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3645 /* Set REG_CONTROL1.SWREG_PROGRAM */ 3683 return;
3646 REG_WRITE(ah, AR_RTC_REG_CONTROL1, 3684
3647 REG_READ(ah, 3685 reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
3648 AR_RTC_REG_CONTROL1) | 3686 (7 << 14) | (6 << 17) | (1 << 20) |
3649 AR_RTC_REG_CONTROL1_SWREG_PROGRAM); 3687 (3 << 24) | (1 << 28);
3688
3689 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3690 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3691 return;
3692
3693 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3694 | (4 << 26);
3695 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3696 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3697 return;
3698
3699 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3700 | (1 << 21);
3701 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3702 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3703 return;
3704 } else {
3705 /* Internal regulator is ON. Write swreg register. */
3706 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3707 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3708 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3709 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3710 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3711 /* Set REG_CONTROL1.SWREG_PROGRAM */
3712 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3713 REG_READ(ah,
3714 AR_RTC_REG_CONTROL1) |
3715 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3716 }
3650 } else { 3717 } else {
3651 REG_WRITE(ah, AR_RTC_SLEEP_CLK, 3718 if (AR_SREV_9485(ah)) {
3652 (REG_READ(ah, 3719 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3653 AR_RTC_SLEEP_CLK) | 3720 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3654 AR_RTC_FORCE_SWREG_PRD)); 3721 AR_PHY_PMU2_PGM))
3722 udelay(10);
3723
3724 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3725 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3726 AR_PHY_PMU1_PWD))
3727 udelay(10);
3728 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3729 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3730 AR_PHY_PMU2_PGM))
3731 udelay(10);
3732 } else
3733 REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3734 (REG_READ(ah,
3735 AR_RTC_SLEEP_CLK) |
3736 AR_RTC_FORCE_SWREG_PRD));
3737 }
3738
3739}
3740
3741static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3742{
3743 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3744 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3745
3746 if (eep->baseEepHeader.featureEnable & 0x40) {
3747 tuning_caps_param &= 0x7f;
3748 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3749 tuning_caps_param);
3750 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3751 tuning_caps_param);
3655 } 3752 }
3656} 3753}
3657 3754
@@ -3663,6 +3760,8 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3663 ar9003_hw_drive_strength_apply(ah); 3760 ar9003_hw_drive_strength_apply(ah);
3664 ar9003_hw_atten_apply(ah, chan); 3761 ar9003_hw_atten_apply(ah, chan);
3665 ar9003_hw_internal_regulator_apply(ah); 3762 ar9003_hw_internal_regulator_apply(ah);
3763 if (AR_SREV_9485(ah))
3764 ar9003_hw_apply_tuning_caps(ah);
3666} 3765}
3667 3766
3668static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah, 3767static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
@@ -4092,22 +4191,9 @@ static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4092 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq, 4191 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4093 is2GHz) + ht40PowerIncForPdadc; 4192 is2GHz) + ht40PowerIncForPdadc;
4094 4193
4095 while (i < ar9300RateSize) { 4194 for (i = 0; i < ar9300RateSize; i++) {
4096 ath_print(common, ATH_DBG_EEPROM, 4195 ath_dbg(common, ATH_DBG_EEPROM,
4097 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); 4196 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4098 i++;
4099
4100 ath_print(common, ATH_DBG_EEPROM,
4101 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4102 i++;
4103
4104 ath_print(common, ATH_DBG_EEPROM,
4105 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4106 i++;
4107
4108 ath_print(common, ATH_DBG_EEPROM,
4109 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4110 i++;
4111 } 4197 }
4112} 4198}
4113 4199
@@ -4126,18 +4212,17 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4126 struct ath_common *common = ath9k_hw_common(ah); 4212 struct ath_common *common = ath9k_hw_common(ah);
4127 4213
4128 if (ichain >= AR9300_MAX_CHAINS) { 4214 if (ichain >= AR9300_MAX_CHAINS) {
4129 ath_print(common, ATH_DBG_EEPROM, 4215 ath_dbg(common, ATH_DBG_EEPROM,
4130 "Invalid chain index, must be less than %d\n", 4216 "Invalid chain index, must be less than %d\n",
4131 AR9300_MAX_CHAINS); 4217 AR9300_MAX_CHAINS);
4132 return -1; 4218 return -1;
4133 } 4219 }
4134 4220
4135 if (mode) { /* 5GHz */ 4221 if (mode) { /* 5GHz */
4136 if (ipier >= AR9300_NUM_5G_CAL_PIERS) { 4222 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4137 ath_print(common, ATH_DBG_EEPROM, 4223 ath_dbg(common, ATH_DBG_EEPROM,
4138 "Invalid 5GHz cal pier index, must " 4224 "Invalid 5GHz cal pier index, must be less than %d\n",
4139 "be less than %d\n", 4225 AR9300_NUM_5G_CAL_PIERS);
4140 AR9300_NUM_5G_CAL_PIERS);
4141 return -1; 4226 return -1;
4142 } 4227 }
4143 pCalPier = &(eep->calFreqPier5G[ipier]); 4228 pCalPier = &(eep->calFreqPier5G[ipier]);
@@ -4145,9 +4230,9 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4145 is2GHz = 0; 4230 is2GHz = 0;
4146 } else { 4231 } else {
4147 if (ipier >= AR9300_NUM_2G_CAL_PIERS) { 4232 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4148 ath_print(common, ATH_DBG_EEPROM, 4233 ath_dbg(common, ATH_DBG_EEPROM,
4149 "Invalid 2GHz cal pier index, must " 4234 "Invalid 2GHz cal pier index, must be less than %d\n",
4150 "be less than %d\n", AR9300_NUM_2G_CAL_PIERS); 4235 AR9300_NUM_2G_CAL_PIERS);
4151 return -1; 4236 return -1;
4152 } 4237 }
4153 4238
@@ -4176,23 +4261,27 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
4176 REG_RMW(ah, AR_PHY_TPC_11_B0, 4261 REG_RMW(ah, AR_PHY_TPC_11_B0,
4177 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4262 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4178 AR_PHY_TPC_OLPC_GAIN_DELTA); 4263 AR_PHY_TPC_OLPC_GAIN_DELTA);
4179 REG_RMW(ah, AR_PHY_TPC_11_B1, 4264 if (ah->caps.tx_chainmask & BIT(1))
4180 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4265 REG_RMW(ah, AR_PHY_TPC_11_B1,
4181 AR_PHY_TPC_OLPC_GAIN_DELTA); 4266 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4182 REG_RMW(ah, AR_PHY_TPC_11_B2, 4267 AR_PHY_TPC_OLPC_GAIN_DELTA);
4183 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4268 if (ah->caps.tx_chainmask & BIT(2))
4184 AR_PHY_TPC_OLPC_GAIN_DELTA); 4269 REG_RMW(ah, AR_PHY_TPC_11_B2,
4270 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4271 AR_PHY_TPC_OLPC_GAIN_DELTA);
4185 4272
4186 /* enable open loop power control on chip */ 4273 /* enable open loop power control on chip */
4187 REG_RMW(ah, AR_PHY_TPC_6_B0, 4274 REG_RMW(ah, AR_PHY_TPC_6_B0,
4188 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4275 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4189 AR_PHY_TPC_6_ERROR_EST_MODE); 4276 AR_PHY_TPC_6_ERROR_EST_MODE);
4190 REG_RMW(ah, AR_PHY_TPC_6_B1, 4277 if (ah->caps.tx_chainmask & BIT(1))
4191 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4278 REG_RMW(ah, AR_PHY_TPC_6_B1,
4192 AR_PHY_TPC_6_ERROR_EST_MODE); 4279 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4193 REG_RMW(ah, AR_PHY_TPC_6_B2, 4280 AR_PHY_TPC_6_ERROR_EST_MODE);
4194 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4281 if (ah->caps.tx_chainmask & BIT(2))
4195 AR_PHY_TPC_6_ERROR_EST_MODE); 4282 REG_RMW(ah, AR_PHY_TPC_6_B2,
4283 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4284 AR_PHY_TPC_6_ERROR_EST_MODE);
4196 4285
4197 /* 4286 /*
4198 * enable temperature compensation 4287 * enable temperature compensation
@@ -4297,11 +4386,11 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4297 4386
4298 /* interpolate */ 4387 /* interpolate */
4299 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { 4388 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4300 ath_print(common, ATH_DBG_EEPROM, 4389 ath_dbg(common, ATH_DBG_EEPROM,
4301 "ch=%d f=%d low=%d %d h=%d %d\n", 4390 "ch=%d f=%d low=%d %d h=%d %d\n",
4302 ichain, frequency, lfrequency[ichain], 4391 ichain, frequency, lfrequency[ichain],
4303 lcorrection[ichain], hfrequency[ichain], 4392 lcorrection[ichain], hfrequency[ichain],
4304 hcorrection[ichain]); 4393 hcorrection[ichain]);
4305 /* they're the same, so just pick one */ 4394 /* they're the same, so just pick one */
4306 if (hfrequency[ichain] == lfrequency[ichain]) { 4395 if (hfrequency[ichain] == lfrequency[ichain]) {
4307 correction[ichain] = lcorrection[ichain]; 4396 correction[ichain] = lcorrection[ichain];
@@ -4353,9 +4442,9 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4353 ar9003_hw_power_control_override(ah, frequency, correction, voltage, 4442 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4354 temperature); 4443 temperature);
4355 4444
4356 ath_print(common, ATH_DBG_EEPROM, 4445 ath_dbg(common, ATH_DBG_EEPROM,
4357 "for frequency=%d, calibration correction = %d %d %d\n", 4446 "for frequency=%d, calibration correction = %d %d %d\n",
4358 frequency, correction[0], correction[1], correction[2]); 4447 frequency, correction[0], correction[1], correction[2]);
4359 4448
4360 return 0; 4449 return 0;
4361} 4450}
@@ -4560,11 +4649,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4560 else 4649 else
4561 freq = centers.ctl_center; 4650 freq = centers.ctl_center;
4562 4651
4563 ath_print(common, ATH_DBG_REGULATORY, 4652 ath_dbg(common, ATH_DBG_REGULATORY,
4564 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " 4653 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4565 "EXT_ADDITIVE %d\n", 4654 ctlMode, numCtlModes, isHt40CtlMode,
4566 ctlMode, numCtlModes, isHt40CtlMode, 4655 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4567 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4568 4656
4569 /* walk through each CTL index stored in EEPROM */ 4657 /* walk through each CTL index stored in EEPROM */
4570 if (is2ghz) { 4658 if (is2ghz) {
@@ -4576,12 +4664,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4576 } 4664 }
4577 4665
4578 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { 4666 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4579 ath_print(common, ATH_DBG_REGULATORY, 4667 ath_dbg(common, ATH_DBG_REGULATORY,
4580 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x " 4668 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4581 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " 4669 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4582 "chan %dn", 4670 chan->channel);
4583 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4584 chan->channel);
4585 4671
4586 /* 4672 /*
4587 * compare test group from regulatory 4673 * compare test group from regulatory
@@ -4620,11 +4706,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4620 4706
4621 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 4707 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4622 4708
4623 ath_print(common, ATH_DBG_REGULATORY, 4709 ath_dbg(common, ATH_DBG_REGULATORY,
4624 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d " 4710 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4625 "sP %d minCtlPwr %d\n", 4711 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4626 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, 4712 scaledPower, minCtlPower);
4627 scaledPower, minCtlPower);
4628 4713
4629 /* Apply ctl mode to correct target power set */ 4714 /* Apply ctl mode to correct target power set */
4630 switch (pCtlMode[ctlMode]) { 4715 switch (pCtlMode[ctlMode]) {
@@ -4699,18 +4784,8 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4699 return; 4784 return;
4700 4785
4701 for (i = 0; i < ar9300RateSize; i++) { 4786 for (i = 0; i < ar9300RateSize; i++) {
4702 ath_print(common, ATH_DBG_EEPROM, 4787 ath_dbg(common, ATH_DBG_EEPROM,
4703 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]); 4788 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4704 i++;
4705 ath_print(common, ATH_DBG_EEPROM,
4706 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4707 i++;
4708 ath_print(common, ATH_DBG_EEPROM,
4709 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4710 i++;
4711 ath_print(common, ATH_DBG_EEPROM,
4712 "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]);
4713 i++;
4714 } 4789 }
4715 4790
4716 /* 4791 /*
@@ -4758,6 +4833,16 @@ s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4758 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */ 4833 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4759} 4834}
4760 4835
4836u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
4837{
4838 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4839
4840 if (is_2ghz)
4841 return eep->modalHeader2G.spurChans;
4842 else
4843 return eep->modalHeader5G.spurChans;
4844}
4845
4761const struct eeprom_ops eep_ar9300_ops = { 4846const struct eeprom_ops eep_ar9300_ops = {
4762 .check_eeprom = ath9k_hw_ar9300_check_eeprom, 4847 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4763 .get_eeprom = ath9k_hw_ar9300_get_eeprom, 4848 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 9c1463307f0c..33503217dab3 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -78,6 +78,7 @@
78#define AR9300_EEPROM_SIZE (16*1024) 78#define AR9300_EEPROM_SIZE (16*1024)
79#define FIXED_CCA_THRESHOLD 15 79#define FIXED_CCA_THRESHOLD 15
80 80
81#define AR9300_BASE_ADDR_4K 0xfff
81#define AR9300_BASE_ADDR 0x3ff 82#define AR9300_BASE_ADDR 0x3ff
82#define AR9300_BASE_ADDR_512 0x1ff 83#define AR9300_BASE_ADDR_512 0x1ff
83 84
@@ -342,4 +343,5 @@ struct ar9300_eeprom {
342s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah); 343s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
343s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah); 344s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
344 345
346u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
345#endif 347#endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index c2a057156bfa..21a5bfe354a0 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -17,6 +17,7 @@
17#include "hw.h" 17#include "hw.h"
18#include "ar9003_mac.h" 18#include "ar9003_mac.h"
19#include "ar9003_2p2_initvals.h" 19#include "ar9003_2p2_initvals.h"
20#include "ar9485_initvals.h"
20 21
21/* General hardware code for the AR9003 hadware family */ 22/* General hardware code for the AR9003 hadware family */
22 23
@@ -24,6 +25,7 @@ static bool ar9003_hw_macversion_supported(u32 macversion)
24{ 25{
25 switch (macversion) { 26 switch (macversion) {
26 case AR_SREV_VERSION_9300: 27 case AR_SREV_VERSION_9300:
28 case AR_SREV_VERSION_9485:
27 return true; 29 return true;
28 default: 30 default:
29 break; 31 break;
@@ -38,72 +40,134 @@ static bool ar9003_hw_macversion_supported(u32 macversion)
38 */ 40 */
39static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 41static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
40{ 42{
41 /* mac */ 43 if (AR_SREV_9485(ah)) {
42 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 44 /* mac */
43 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 45 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
44 ar9300_2p2_mac_core, 46 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
45 ARRAY_SIZE(ar9300_2p2_mac_core), 2); 47 ar9485_1_0_mac_core,
46 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 48 ARRAY_SIZE(ar9485_1_0_mac_core), 2);
47 ar9300_2p2_mac_postamble, 49 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
48 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5); 50 ar9485_1_0_mac_postamble,
49 51 ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
50 /* bb */ 52
51 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 53 /* bb */
52 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 54 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
53 ar9300_2p2_baseband_core, 55 ARRAY_SIZE(ar9485_1_0), 2);
54 ARRAY_SIZE(ar9300_2p2_baseband_core), 2); 56 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
55 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 57 ar9485_1_0_baseband_core,
56 ar9300_2p2_baseband_postamble, 58 ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
57 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5); 59 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
58 60 ar9485_1_0_baseband_postamble,
59 /* radio */ 61 ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
60 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 62
61 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 63 /* radio */
62 ar9300_2p2_radio_core, 64 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
63 ARRAY_SIZE(ar9300_2p2_radio_core), 2); 65 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
64 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 66 ar9485_1_0_radio_core,
65 ar9300_2p2_radio_postamble, 67 ARRAY_SIZE(ar9485_1_0_radio_core), 2);
66 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5); 68 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
67 69 ar9485_1_0_radio_postamble,
68 /* soc */ 70 ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
69 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 71
70 ar9300_2p2_soc_preamble, 72 /* soc */
71 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2); 73 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
72 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 74 ar9485_1_0_soc_preamble,
73 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 75 ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
74 ar9300_2p2_soc_postamble, 76 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
75 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5); 77 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
76 78
77 /* rx/tx gain */ 79 /* rx/tx gain */
78 INIT_INI_ARRAY(&ah->iniModesRxGain, 80 INIT_INI_ARRAY(&ah->iniModesRxGain,
79 ar9300Common_rx_gain_table_2p2, 81 ar9485Common_rx_gain_1_0,
80 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2); 82 ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
81 INIT_INI_ARRAY(&ah->iniModesTxGain, 83 INIT_INI_ARRAY(&ah->iniModesTxGain,
82 ar9300Modes_lowest_ob_db_tx_gain_table_2p2, 84 ar9485Modes_lowest_ob_db_tx_gain_1_0,
83 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2), 85 ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
84 5); 86 5);
85 87
86 /* Load PCIE SERDES settings from INI */ 88 /* Load PCIE SERDES settings from INI */
87 89
88 /* Awake Setting */ 90 /* Awake Setting */
89 91
90 INIT_INI_ARRAY(&ah->iniPcieSerdes, 92 INIT_INI_ARRAY(&ah->iniPcieSerdes,
91 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, 93 ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
92 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2), 94 ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
93 2); 95 2);
94 96
95 /* Sleep Setting */ 97 /* Sleep Setting */
96 98
97 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 99 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
98 ar9300PciePhy_clkreq_enable_L1_2p2, 100 ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1,
99 ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2), 101 ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1),
100 2); 102 2);
101 103 } else {
102 /* Fast clock modal settings */ 104 /* mac */
103 INIT_INI_ARRAY(&ah->iniModesAdditional, 105 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
104 ar9300Modes_fast_clock_2p2, 106 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
105 ARRAY_SIZE(ar9300Modes_fast_clock_2p2), 107 ar9300_2p2_mac_core,
106 3); 108 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
109 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
110 ar9300_2p2_mac_postamble,
111 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
112
113 /* bb */
114 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
115 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
116 ar9300_2p2_baseband_core,
117 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
118 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
119 ar9300_2p2_baseband_postamble,
120 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
121
122 /* radio */
123 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
124 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
125 ar9300_2p2_radio_core,
126 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
127 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
128 ar9300_2p2_radio_postamble,
129 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
130
131 /* soc */
132 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
133 ar9300_2p2_soc_preamble,
134 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
135 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
136 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
137 ar9300_2p2_soc_postamble,
138 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
139
140 /* rx/tx gain */
141 INIT_INI_ARRAY(&ah->iniModesRxGain,
142 ar9300Common_rx_gain_table_2p2,
143 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
144 INIT_INI_ARRAY(&ah->iniModesTxGain,
145 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
146 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
147 5);
148
149 /* Load PCIE SERDES settings from INI */
150
151 /* Awake Setting */
152
153 INIT_INI_ARRAY(&ah->iniPcieSerdes,
154 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
155 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
156 2);
157
158 /* Sleep Setting */
159
160 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
161 ar9300PciePhy_clkreq_enable_L1_2p2,
162 ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
163 2);
164
165 /* Fast clock modal settings */
166 INIT_INI_ARRAY(&ah->iniModesAdditional,
167 ar9300Modes_fast_clock_2p2,
168 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
169 3);
170 }
107} 171}
108 172
109static void ar9003_tx_gain_table_apply(struct ath_hw *ah) 173static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
@@ -111,22 +175,52 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
111 switch (ar9003_hw_get_tx_gain_idx(ah)) { 175 switch (ar9003_hw_get_tx_gain_idx(ah)) {
112 case 0: 176 case 0:
113 default: 177 default:
114 INIT_INI_ARRAY(&ah->iniModesTxGain, 178 if (AR_SREV_9485(ah))
115 ar9300Modes_lowest_ob_db_tx_gain_table_2p2, 179 INIT_INI_ARRAY(&ah->iniModesTxGain,
116 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2), 180 ar9485Modes_lowest_ob_db_tx_gain_1_0,
117 5); 181 ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
182 5);
183 else
184 INIT_INI_ARRAY(&ah->iniModesTxGain,
185 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
186 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
187 5);
118 break; 188 break;
119 case 1: 189 case 1:
120 INIT_INI_ARRAY(&ah->iniModesTxGain, 190 if (AR_SREV_9485(ah))
121 ar9300Modes_high_ob_db_tx_gain_table_2p2, 191 INIT_INI_ARRAY(&ah->iniModesTxGain,
122 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2), 192 ar9485Modes_high_ob_db_tx_gain_1_0,
123 5); 193 ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
194 5);
195 else
196 INIT_INI_ARRAY(&ah->iniModesTxGain,
197 ar9300Modes_high_ob_db_tx_gain_table_2p2,
198 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
199 5);
124 break; 200 break;
125 case 2: 201 case 2:
126 INIT_INI_ARRAY(&ah->iniModesTxGain, 202 if (AR_SREV_9485(ah))
127 ar9300Modes_low_ob_db_tx_gain_table_2p2, 203 INIT_INI_ARRAY(&ah->iniModesTxGain,
128 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2), 204 ar9485Modes_low_ob_db_tx_gain_1_0,
129 5); 205 ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
206 5);
207 else
208 INIT_INI_ARRAY(&ah->iniModesTxGain,
209 ar9300Modes_low_ob_db_tx_gain_table_2p2,
210 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
211 5);
212 break;
213 case 3:
214 if (AR_SREV_9485(ah))
215 INIT_INI_ARRAY(&ah->iniModesTxGain,
216 ar9485Modes_high_power_tx_gain_1_0,
217 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_0),
218 5);
219 else
220 INIT_INI_ARRAY(&ah->iniModesTxGain,
221 ar9300Modes_high_power_tx_gain_table_2p2,
222 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
223 5);
130 break; 224 break;
131 } 225 }
132} 226}
@@ -136,16 +230,28 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
136 switch (ar9003_hw_get_rx_gain_idx(ah)) { 230 switch (ar9003_hw_get_rx_gain_idx(ah)) {
137 case 0: 231 case 0:
138 default: 232 default:
139 INIT_INI_ARRAY(&ah->iniModesRxGain, 233 if (AR_SREV_9485(ah))
140 ar9300Common_rx_gain_table_2p2, 234 INIT_INI_ARRAY(&ah->iniModesRxGain,
141 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 235 ar9485Common_rx_gain_1_0,
142 2); 236 ARRAY_SIZE(ar9485Common_rx_gain_1_0),
237 2);
238 else
239 INIT_INI_ARRAY(&ah->iniModesRxGain,
240 ar9300Common_rx_gain_table_2p2,
241 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
242 2);
143 break; 243 break;
144 case 1: 244 case 1:
145 INIT_INI_ARRAY(&ah->iniModesRxGain, 245 if (AR_SREV_9485(ah))
146 ar9300Common_wo_xlna_rx_gain_table_2p2, 246 INIT_INI_ARRAY(&ah->iniModesRxGain,
147 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2), 247 ar9485Common_wo_xlna_rx_gain_1_0,
148 2); 248 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_0),
249 2);
250 else
251 INIT_INI_ARRAY(&ah->iniModesRxGain,
252 ar9300Common_wo_xlna_rx_gain_table_2p2,
253 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
254 2);
149 break; 255 break;
150 } 256 }
151} 257}
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index f5896aa30005..bfba6a2b741d 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -182,8 +182,8 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
182 } 182 }
183 183
184 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 184 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
185 ath_print(common, ATH_DBG_INTERRUPT, 185 ath_dbg(common, ATH_DBG_INTERRUPT,
186 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 186 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
187 187
188 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 188 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
189 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 189 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
@@ -249,8 +249,8 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
249 249
250 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || 250 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
251 (MS(ads->ds_info, AR_TxRxDesc) != 1)) { 251 (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
252 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 252 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
253 "Tx Descriptor error %x\n", ads->ds_info); 253 "Tx Descriptor error %x\n", ads->ds_info);
254 memset(ads, 0, sizeof(*ads)); 254 memset(ads, 0, sizeof(*ads));
255 return -EIO; 255 return -EIO;
256 } 256 }
@@ -658,10 +658,10 @@ void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
658 memset((void *) ah->ts_ring, 0, 658 memset((void *) ah->ts_ring, 0,
659 ah->ts_size * sizeof(struct ar9003_txs)); 659 ah->ts_size * sizeof(struct ar9003_txs));
660 660
661 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 661 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
662 "TS Start 0x%x End 0x%x Virt %p, Size %d\n", 662 "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
663 ah->ts_paddr_start, ah->ts_paddr_end, 663 ah->ts_paddr_start, ah->ts_paddr_end,
664 ah->ts_ring, ah->ts_size); 664 ah->ts_ring, ah->ts_size);
665 665
666 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); 666 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
667 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); 667 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index 850bc9866c19..74cff4365c43 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -21,10 +21,12 @@ void ar9003_paprd_enable(struct ath_hw *ah, bool val)
21{ 21{
22 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0, 22 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
23 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); 23 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
24 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1, 24 if (ah->caps.tx_chainmask & BIT(1))
25 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); 25 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1,
26 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2, 26 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
27 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); 27 if (ah->caps.tx_chainmask & BIT(2))
28 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2,
29 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
28} 30}
29EXPORT_SYMBOL(ar9003_paprd_enable); 31EXPORT_SYMBOL(ar9003_paprd_enable);
30 32
@@ -57,7 +59,8 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
57 REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask); 59 REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask);
58 REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask); 60 REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask);
59 61
60 for (i = 0; i < 3; i++) { 62
63 for (i = 0; i < ah->caps.max_txchains; i++) {
61 REG_RMW_FIELD(ah, ctrl0[i], 64 REG_RMW_FIELD(ah, ctrl0[i],
62 AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK, 1); 65 AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK, 1);
63 REG_RMW_FIELD(ah, ctrl1[i], 66 REG_RMW_FIELD(ah, ctrl1[i],
@@ -102,8 +105,14 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
102 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7); 105 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
103 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 106 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
104 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1); 107 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
105 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 108 if (AR_SREV_9485(ah))
106 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -6); 109 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
110 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
111 -3);
112 else
113 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
114 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
115 -6);
107 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 116 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
108 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, 117 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE,
109 -15); 118 -15);
@@ -620,13 +629,15 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah,
620 AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, 629 AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
621 training_power); 630 training_power);
622 631
623 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1, 632 if (ah->caps.tx_chainmask & BIT(1))
624 AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, 633 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1,
625 training_power); 634 AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
635 training_power);
626 636
627 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2, 637 if (ah->caps.tx_chainmask & BIT(2))
628 AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL, 638 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2,
629 training_power); 639 AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
640 training_power);
630} 641}
631EXPORT_SYMBOL(ar9003_paprd_populate_single_table); 642EXPORT_SYMBOL(ar9003_paprd_populate_single_table);
632 643
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index b34a9e91edd8..da4a571304da 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -75,7 +75,10 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
75 freq = centers.synth_center; 75 freq = centers.synth_center;
76 76
77 if (freq < 4800) { /* 2 GHz, fractional mode */ 77 if (freq < 4800) { /* 2 GHz, fractional mode */
78 channelSel = CHANSEL_2G(freq); 78 if (AR_SREV_9485(ah))
79 channelSel = CHANSEL_2G_9485(freq);
80 else
81 channelSel = CHANSEL_2G(freq);
79 /* Set to 2G mode */ 82 /* Set to 2G mode */
80 bMode = 1; 83 bMode = 1;
81 } else { 84 } else {
@@ -131,21 +134,50 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
131 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; 134 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
132 int cur_bb_spur, negative = 0, cck_spur_freq; 135 int cur_bb_spur, negative = 0, cck_spur_freq;
133 int i; 136 int i;
137 int range, max_spur_cnts, synth_freq;
138 u8 *spur_fbin_ptr = NULL;
134 139
135 /* 140 /*
136 * Need to verify range +/- 10 MHz in control channel, otherwise spur 141 * Need to verify range +/- 10 MHz in control channel, otherwise spur
137 * is out-of-band and can be ignored. 142 * is out-of-band and can be ignored.
138 */ 143 */
139 144
140 for (i = 0; i < 4; i++) { 145 if (AR_SREV_9485(ah)) {
146 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
147 IS_CHAN_2GHZ(chan));
148 if (spur_fbin_ptr[0] == 0) /* No spur */
149 return;
150 max_spur_cnts = 5;
151 if (IS_CHAN_HT40(chan)) {
152 range = 19;
153 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
154 AR_PHY_GC_DYN2040_PRI_CH) == 0)
155 synth_freq = chan->channel + 10;
156 else
157 synth_freq = chan->channel - 10;
158 } else {
159 range = 10;
160 synth_freq = chan->channel;
161 }
162 } else {
163 range = 10;
164 max_spur_cnts = 4;
165 synth_freq = chan->channel;
166 }
167
168 for (i = 0; i < max_spur_cnts; i++) {
141 negative = 0; 169 negative = 0;
142 cur_bb_spur = spur_freq[i] - chan->channel; 170 if (AR_SREV_9485(ah))
171 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
172 IS_CHAN_2GHZ(chan)) - synth_freq;
173 else
174 cur_bb_spur = spur_freq[i] - synth_freq;
143 175
144 if (cur_bb_spur < 0) { 176 if (cur_bb_spur < 0) {
145 negative = 1; 177 negative = 1;
146 cur_bb_spur = -cur_bb_spur; 178 cur_bb_spur = -cur_bb_spur;
147 } 179 }
148 if (cur_bb_spur < 10) { 180 if (cur_bb_spur < range) {
149 cck_spur_freq = (int)((cur_bb_spur << 19) / 11); 181 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
150 182
151 if (negative == 1) 183 if (negative == 1)
@@ -824,12 +856,12 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
824 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 856 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
825 857
826 if (!on != aniState->ofdmWeakSigDetectOff) { 858 if (!on != aniState->ofdmWeakSigDetectOff) {
827 ath_print(common, ATH_DBG_ANI, 859 ath_dbg(common, ATH_DBG_ANI,
828 "** ch %d: ofdm weak signal: %s=>%s\n", 860 "** ch %d: ofdm weak signal: %s=>%s\n",
829 chan->channel, 861 chan->channel,
830 !aniState->ofdmWeakSigDetectOff ? 862 !aniState->ofdmWeakSigDetectOff ?
831 "on" : "off", 863 "on" : "off",
832 on ? "on" : "off"); 864 on ? "on" : "off");
833 if (on) 865 if (on)
834 ah->stats.ast_ani_ofdmon++; 866 ah->stats.ast_ani_ofdmon++;
835 else 867 else
@@ -842,11 +874,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
842 u32 level = param; 874 u32 level = param;
843 875
844 if (level >= ARRAY_SIZE(firstep_table)) { 876 if (level >= ARRAY_SIZE(firstep_table)) {
845 ath_print(common, ATH_DBG_ANI, 877 ath_dbg(common, ATH_DBG_ANI,
846 "ATH9K_ANI_FIRSTEP_LEVEL: level " 878 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
847 "out of range (%u > %u)\n", 879 level, ARRAY_SIZE(firstep_table));
848 level,
849 (unsigned) ARRAY_SIZE(firstep_table));
850 return false; 880 return false;
851 } 881 }
852 882
@@ -881,24 +911,22 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
881 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); 911 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
882 912
883 if (level != aniState->firstepLevel) { 913 if (level != aniState->firstepLevel) {
884 ath_print(common, ATH_DBG_ANI, 914 ath_dbg(common, ATH_DBG_ANI,
885 "** ch %d: level %d=>%d[def:%d] " 915 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
886 "firstep[level]=%d ini=%d\n", 916 chan->channel,
887 chan->channel, 917 aniState->firstepLevel,
888 aniState->firstepLevel, 918 level,
889 level, 919 ATH9K_ANI_FIRSTEP_LVL_NEW,
890 ATH9K_ANI_FIRSTEP_LVL_NEW, 920 value,
891 value, 921 aniState->iniDef.firstep);
892 aniState->iniDef.firstep); 922 ath_dbg(common, ATH_DBG_ANI,
893 ath_print(common, ATH_DBG_ANI, 923 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
894 "** ch %d: level %d=>%d[def:%d] " 924 chan->channel,
895 "firstep_low[level]=%d ini=%d\n", 925 aniState->firstepLevel,
896 chan->channel, 926 level,
897 aniState->firstepLevel, 927 ATH9K_ANI_FIRSTEP_LVL_NEW,
898 level, 928 value2,
899 ATH9K_ANI_FIRSTEP_LVL_NEW, 929 aniState->iniDef.firstepLow);
900 value2,
901 aniState->iniDef.firstepLow);
902 if (level > aniState->firstepLevel) 930 if (level > aniState->firstepLevel)
903 ah->stats.ast_ani_stepup++; 931 ah->stats.ast_ani_stepup++;
904 else if (level < aniState->firstepLevel) 932 else if (level < aniState->firstepLevel)
@@ -911,11 +939,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
911 u32 level = param; 939 u32 level = param;
912 940
913 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 941 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
914 ath_print(common, ATH_DBG_ANI, 942 ath_dbg(common, ATH_DBG_ANI,
915 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level " 943 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
916 "out of range (%u > %u)\n", 944 level, ARRAY_SIZE(cycpwrThr1_table));
917 level,
918 (unsigned) ARRAY_SIZE(cycpwrThr1_table));
919 return false; 945 return false;
920 } 946 }
921 /* 947 /*
@@ -949,24 +975,22 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
949 AR_PHY_EXT_CYCPWR_THR1, value2); 975 AR_PHY_EXT_CYCPWR_THR1, value2);
950 976
951 if (level != aniState->spurImmunityLevel) { 977 if (level != aniState->spurImmunityLevel) {
952 ath_print(common, ATH_DBG_ANI, 978 ath_dbg(common, ATH_DBG_ANI,
953 "** ch %d: level %d=>%d[def:%d] " 979 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
954 "cycpwrThr1[level]=%d ini=%d\n", 980 chan->channel,
955 chan->channel, 981 aniState->spurImmunityLevel,
956 aniState->spurImmunityLevel, 982 level,
957 level, 983 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
958 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 984 value,
959 value, 985 aniState->iniDef.cycpwrThr1);
960 aniState->iniDef.cycpwrThr1); 986 ath_dbg(common, ATH_DBG_ANI,
961 ath_print(common, ATH_DBG_ANI, 987 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
962 "** ch %d: level %d=>%d[def:%d] " 988 chan->channel,
963 "cycpwrThr1Ext[level]=%d ini=%d\n", 989 aniState->spurImmunityLevel,
964 chan->channel, 990 level,
965 aniState->spurImmunityLevel, 991 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
966 level, 992 value2,
967 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 993 aniState->iniDef.cycpwrThr1Ext);
968 value2,
969 aniState->iniDef.cycpwrThr1Ext);
970 if (level > aniState->spurImmunityLevel) 994 if (level > aniState->spurImmunityLevel)
971 ah->stats.ast_ani_spurup++; 995 ah->stats.ast_ani_spurup++;
972 else if (level < aniState->spurImmunityLevel) 996 else if (level < aniState->spurImmunityLevel)
@@ -986,11 +1010,11 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
986 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1010 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
987 AR_PHY_MRC_CCK_MUX_REG, is_on); 1011 AR_PHY_MRC_CCK_MUX_REG, is_on);
988 if (!is_on != aniState->mrcCCKOff) { 1012 if (!is_on != aniState->mrcCCKOff) {
989 ath_print(common, ATH_DBG_ANI, 1013 ath_dbg(common, ATH_DBG_ANI,
990 "** ch %d: MRC CCK: %s=>%s\n", 1014 "** ch %d: MRC CCK: %s=>%s\n",
991 chan->channel, 1015 chan->channel,
992 !aniState->mrcCCKOff ? "on" : "off", 1016 !aniState->mrcCCKOff ? "on" : "off",
993 is_on ? "on" : "off"); 1017 is_on ? "on" : "off");
994 if (is_on) 1018 if (is_on)
995 ah->stats.ast_ani_ccklow++; 1019 ah->stats.ast_ani_ccklow++;
996 else 1020 else
@@ -1002,22 +1026,19 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
1002 case ATH9K_ANI_PRESENT: 1026 case ATH9K_ANI_PRESENT:
1003 break; 1027 break;
1004 default: 1028 default:
1005 ath_print(common, ATH_DBG_ANI, 1029 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1006 "invalid cmd %u\n", cmd);
1007 return false; 1030 return false;
1008 } 1031 }
1009 1032
1010 ath_print(common, ATH_DBG_ANI, 1033 ath_dbg(common, ATH_DBG_ANI,
1011 "ANI parameters: SI=%d, ofdmWS=%s FS=%d " 1034 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1012 "MRCcck=%s listenTime=%d " 1035 aniState->spurImmunityLevel,
1013 "ofdmErrs=%d cckErrs=%d\n", 1036 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1014 aniState->spurImmunityLevel, 1037 aniState->firstepLevel,
1015 !aniState->ofdmWeakSigDetectOff ? "on" : "off", 1038 !aniState->mrcCCKOff ? "on" : "off",
1016 aniState->firstepLevel, 1039 aniState->listenTime,
1017 !aniState->mrcCCKOff ? "on" : "off", 1040 aniState->ofdmPhyErrCount,
1018 aniState->listenTime, 1041 aniState->cckPhyErrCount);
1019 aniState->ofdmPhyErrCount,
1020 aniState->cckPhyErrCount);
1021 return true; 1042 return true;
1022} 1043}
1023 1044
@@ -1074,13 +1095,13 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1074 aniState = &ah->curchan->ani; 1095 aniState = &ah->curchan->ani;
1075 iniDef = &aniState->iniDef; 1096 iniDef = &aniState->iniDef;
1076 1097
1077 ath_print(common, ATH_DBG_ANI, 1098 ath_dbg(common, ATH_DBG_ANI,
1078 "ver %d.%d opmode %u chan %d Mhz/0x%x\n", 1099 "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1079 ah->hw_version.macVersion, 1100 ah->hw_version.macVersion,
1080 ah->hw_version.macRev, 1101 ah->hw_version.macRev,
1081 ah->opmode, 1102 ah->opmode,
1082 chan->channel, 1103 chan->channel,
1083 chan->channelFlags); 1104 chan->channelFlags);
1084 1105
1085 val = REG_READ(ah, AR_PHY_SFCORR); 1106 val = REG_READ(ah, AR_PHY_SFCORR);
1086 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1107 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
@@ -1216,7 +1237,7 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1216 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 1237 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1217 AR_PHY_WATCHDOG_IDLE_ENABLE)); 1238 AR_PHY_WATCHDOG_IDLE_ENABLE));
1218 1239
1219 ath_print(common, ATH_DBG_RESET, "Disabled BB Watchdog\n"); 1240 ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
1220 return; 1241 return;
1221 } 1242 }
1222 1243
@@ -1252,9 +1273,9 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1252 AR_PHY_WATCHDOG_IDLE_MASK | 1273 AR_PHY_WATCHDOG_IDLE_MASK |
1253 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); 1274 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1254 1275
1255 ath_print(common, ATH_DBG_RESET, 1276 ath_dbg(common, ATH_DBG_RESET,
1256 "Enabled BB Watchdog timeout (%u ms)\n", 1277 "Enabled BB Watchdog timeout (%u ms)\n",
1257 idle_tmo_ms); 1278 idle_tmo_ms);
1258} 1279}
1259 1280
1260void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) 1281void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
@@ -1282,37 +1303,35 @@ void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1282 return; 1303 return;
1283 1304
1284 status = ah->bb_watchdog_last_status; 1305 status = ah->bb_watchdog_last_status;
1285 ath_print(common, ATH_DBG_RESET, 1306 ath_dbg(common, ATH_DBG_RESET,
1286 "\n==== BB update: BB status=0x%08x ====\n", status); 1307 "\n==== BB update: BB status=0x%08x ====\n", status);
1287 ath_print(common, ATH_DBG_RESET, 1308 ath_dbg(common, ATH_DBG_RESET,
1288 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " 1309 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1289 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1310 MS(status, AR_PHY_WATCHDOG_INFO),
1290 MS(status, AR_PHY_WATCHDOG_INFO), 1311 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1291 MS(status, AR_PHY_WATCHDOG_DET_HANG), 1312 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1292 MS(status, AR_PHY_WATCHDOG_RADAR_SM), 1313 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1293 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM), 1314 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1294 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM), 1315 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1295 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM), 1316 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1296 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM), 1317 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1297 MS(status, AR_PHY_WATCHDOG_AGC_SM), 1318 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1298 MS(status,AR_PHY_WATCHDOG_SRCH_SM)); 1319
1299 1320 ath_dbg(common, ATH_DBG_RESET,
1300 ath_print(common, ATH_DBG_RESET, 1321 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1301 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1322 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1302 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), 1323 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1303 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); 1324 ath_dbg(common, ATH_DBG_RESET,
1304 ath_print(common, ATH_DBG_RESET, 1325 "** BB mode: BB_gen_controls=0x%08x **\n",
1305 "** BB mode: BB_gen_controls=0x%08x **\n", 1326 REG_READ(ah, AR_PHY_GEN_CTRL));
1306 REG_READ(ah, AR_PHY_GEN_CTRL));
1307 1327
1308#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) 1328#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1309 if (common->cc_survey.cycles) 1329 if (common->cc_survey.cycles)
1310 ath_print(common, ATH_DBG_RESET, 1330 ath_dbg(common, ATH_DBG_RESET,
1311 "** BB busy times: rx_clear=%d%%, " 1331 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1312 "rx_frame=%d%%, tx_frame=%d%% **\n", 1332 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1313 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1314 1333
1315 ath_print(common, ATH_DBG_RESET, 1334 ath_dbg(common, ATH_DBG_RESET,
1316 "==== BB update: done ====\n\n"); 1335 "==== BB update: done ====\n\n");
1317} 1336}
1318EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); 1337EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 3394dfe52b42..6f811c7ada05 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -260,7 +260,13 @@
260#define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c) 260#define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c)
261#define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20) 261#define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20)
262#define AR_PHY_RESTART (AR_AGC_BASE + 0x24) 262#define AR_PHY_RESTART (AR_AGC_BASE + 0x24)
263
263#define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28) 264#define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28)
265#define AR_ANT_DIV_CTRL_ALL 0x7e000000
266#define AR_ANT_DIV_CTRL_ALL_S 25
267#define AR_ANT_DIV_ENABLE 0x1000000
268#define AR_ANT_DIV_ENABLE_S 24
269
264#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c) 270#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
265#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30) 271#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)
266#define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34) 272#define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34)
@@ -271,7 +277,11 @@
271#define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48) 277#define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
272#define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180) 278#define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180)
273#define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184) 279#define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184)
280
274#define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0) 281#define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0)
282#define AR_FAST_DIV_ENABLE 0x2000
283#define AR_FAST_DIV_ENABLE_S 13
284
275#define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4) 285#define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4)
276#define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8) 286#define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8)
277 287
@@ -536,10 +546,18 @@
536 546
537#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300) 547#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
538 548
549#define AR_PHY_TX_IQCAL_START_9485 (AR_SM_BASE + 0x3c4)
550#define AR_PHY_TX_IQCAL_START_DO_CAL_9485 0x80000000
551#define AR_PHY_TX_IQCAL_START_DO_CAL_9485_S 31
552#define AR_PHY_TX_IQCAL_CONTROL_1_9485 (AR_SM_BASE + 0x3c8)
553#define AR_PHY_TX_IQCAL_STATUS_B0_9485 (AR_SM_BASE + 0x3f0)
554
539#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448) 555#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448)
540#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440) 556#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440)
541#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c) 557#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c)
542#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 (AR_SM_BASE + 0x450) 558#define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \
559 (AR_SREV_9485(ah) ? \
560 0x3d0 : 0x450) + ((_i) << 2))
543 561
544#define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0) 562#define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
545#define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4) 563#define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
@@ -568,7 +586,7 @@
568#define AR_PHY_65NM_CH0_BIAS2 0x160c4 586#define AR_PHY_65NM_CH0_BIAS2 0x160c4
569#define AR_PHY_65NM_CH0_BIAS4 0x160cc 587#define AR_PHY_65NM_CH0_BIAS4 0x160cc
570#define AR_PHY_65NM_CH0_RXTX4 0x1610c 588#define AR_PHY_65NM_CH0_RXTX4 0x1610c
571#define AR_PHY_65NM_CH0_THERM 0x16290 589#define AR_PHY_65NM_CH0_THERM (AR_SREV_9485(ah) ? 0x1628c : 0x16290)
572 590
573#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 591#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
574#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 592#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
@@ -584,6 +602,24 @@
584#define AR_PHY_65NM_CH2_RXTX1 0x16900 602#define AR_PHY_65NM_CH2_RXTX1 0x16900
585#define AR_PHY_65NM_CH2_RXTX2 0x16904 603#define AR_PHY_65NM_CH2_RXTX2 0x16904
586 604
605#define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
606#define AR_CH0_TOP2_XPABIASLVL 0xf000
607#define AR_CH0_TOP2_XPABIASLVL_S 12
608
609#define AR_CH0_XTAL (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
610#define AR_CH0_XTAL_CAPINDAC 0x7f000000
611#define AR_CH0_XTAL_CAPINDAC_S 24
612#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
613#define AR_CH0_XTAL_CAPOUTDAC_S 17
614
615#define AR_PHY_PMU1 0x16c40
616#define AR_PHY_PMU1_PWD 0x1
617#define AR_PHY_PMU1_PWD_S 0
618
619#define AR_PHY_PMU2 0x16c44
620#define AR_PHY_PMU2_PGM 0x00200000
621#define AR_PHY_PMU2_PGM_S 21
622
587#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000 623#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
588#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19 624#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19
589#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000 625#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
@@ -683,6 +719,7 @@
683#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1 719#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
684#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001 720#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
685#define AR_PHY_TXGAIN_FORCE 0x00000001 721#define AR_PHY_TXGAIN_FORCE 0x00000001
722#define AR_PHY_TXGAIN_FORCE_S 0
686#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00 723#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
687#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10 724#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
688#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000 725#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
@@ -725,8 +762,13 @@
725#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0 762#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
726 763
727#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001 764#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
728#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff 765#define AR_PHY_CALIBRATED_GAINS_0 0x3e
729#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0 766#define AR_PHY_CALIBRATED_GAINS_0_S 1
767
768#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE 0x00003fff
769#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S 0
770#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x0fffc000
771#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 14
730 772
731#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000 773#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
732#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28 774#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
@@ -785,7 +827,7 @@
785#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220) 827#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
786#define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240) 828#define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240)
787#define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c) 829#define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c)
788#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 (AR_SM1_BASE + 0x450) 830#define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM_BASE + 0x450 + ((_i) << 2))
789 831
790/* 832/*
791 * Channel 2 Register Map 833 * Channel 2 Register Map
@@ -838,7 +880,7 @@
838#define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220) 880#define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
839#define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240) 881#define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240)
840#define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c) 882#define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c)
841#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 (AR_SM2_BASE + 0x450) 883#define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i) (AR_SM2_BASE + 0x450 + ((_i) << 2))
842 884
843#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001 885#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
844 886
@@ -945,7 +987,9 @@
945#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000 987#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000
946#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17 988#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17
947 989
948#define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + 0x490) 990#define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + \
991 (AR_SREV_9485(ah) ? \
992 0x580 : 0x490))
949#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001 993#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001
950#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0 994#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0
951#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e 995#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e
@@ -961,11 +1005,15 @@
961#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000 1005#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000
962#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12 1006#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12
963 1007
964#define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + 0x494) 1008#define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + \
1009 (AR_SREV_9485(ah) ? \
1010 0x584 : 0x494))
965#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF 1011#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF
966#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0 1012#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0
967 1013
968#define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + 0x498) 1014#define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + \
1015 (AR_SREV_9485(ah) ? \
1016 0x588 : 0x498))
969#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f 1017#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f
970#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0 1018#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0
971#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0 1019#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0
@@ -981,7 +1029,9 @@
981#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000 1029#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000
982#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29 1030#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29
983 1031
984#define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + 0x49c) 1032#define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + \
1033 (AR_SREV_9485(ah) ? \
1034 0x58c : 0x49c))
985#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000 1035#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000
986#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16 1036#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16
987#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000 1037#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000
diff --git a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
new file mode 100644
index 000000000000..70de3d89a7b5
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
@@ -0,0 +1,943 @@
1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef INITVALS_9485_H
18#define INITVALS_9485_H
19
20static const u32 ar9485Common_1_0[][2] = {
21 /* Addr allmodes */
22 {0x00007010, 0x00000022},
23 {0x00007020, 0x00000000},
24 {0x00007034, 0x00000002},
25 {0x00007038, 0x000004c2},
26};
27
28static const u32 ar9485_1_0_mac_postamble[][5] = {
29 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
30 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
31 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
32 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
33 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
34 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
35 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
36 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
37 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
38};
39
40static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
41 /* Addr allmodes */
42 {0x00018c00, 0x10212e5e},
43 {0x00018c04, 0x000801d8},
44 {0x00018c08, 0x0000580c},
45};
46
47static const u32 ar9485Common_wo_xlna_rx_gain_1_0[][2] = {
48 /* Addr allmodes */
49 {0x0000a000, 0x00010000},
50 {0x0000a004, 0x00030002},
51 {0x0000a008, 0x00050004},
52 {0x0000a00c, 0x00810080},
53 {0x0000a010, 0x01800082},
54 {0x0000a014, 0x01820181},
55 {0x0000a018, 0x01840183},
56 {0x0000a01c, 0x01880185},
57 {0x0000a020, 0x018a0189},
58 {0x0000a024, 0x02850284},
59 {0x0000a028, 0x02890288},
60 {0x0000a02c, 0x03850384},
61 {0x0000a030, 0x03890388},
62 {0x0000a034, 0x038b038a},
63 {0x0000a038, 0x038d038c},
64 {0x0000a03c, 0x03910390},
65 {0x0000a040, 0x03930392},
66 {0x0000a044, 0x03950394},
67 {0x0000a048, 0x00000396},
68 {0x0000a04c, 0x00000000},
69 {0x0000a050, 0x00000000},
70 {0x0000a054, 0x00000000},
71 {0x0000a058, 0x00000000},
72 {0x0000a05c, 0x00000000},
73 {0x0000a060, 0x00000000},
74 {0x0000a064, 0x00000000},
75 {0x0000a068, 0x00000000},
76 {0x0000a06c, 0x00000000},
77 {0x0000a070, 0x00000000},
78 {0x0000a074, 0x00000000},
79 {0x0000a078, 0x00000000},
80 {0x0000a07c, 0x00000000},
81 {0x0000a080, 0x28282828},
82 {0x0000a084, 0x28282828},
83 {0x0000a088, 0x28282828},
84 {0x0000a08c, 0x28282828},
85 {0x0000a090, 0x28282828},
86 {0x0000a094, 0x21212128},
87 {0x0000a098, 0x171c1c1c},
88 {0x0000a09c, 0x02020212},
89 {0x0000a0a0, 0x00000202},
90 {0x0000a0a4, 0x00000000},
91 {0x0000a0a8, 0x00000000},
92 {0x0000a0ac, 0x00000000},
93 {0x0000a0b0, 0x00000000},
94 {0x0000a0b4, 0x00000000},
95 {0x0000a0b8, 0x00000000},
96 {0x0000a0bc, 0x00000000},
97 {0x0000a0c0, 0x001f0000},
98 {0x0000a0c4, 0x111f1100},
99 {0x0000a0c8, 0x111d111e},
100 {0x0000a0cc, 0x111b111c},
101 {0x0000a0d0, 0x22032204},
102 {0x0000a0d4, 0x22012202},
103 {0x0000a0d8, 0x221f2200},
104 {0x0000a0dc, 0x221d221e},
105 {0x0000a0e0, 0x33013302},
106 {0x0000a0e4, 0x331f3300},
107 {0x0000a0e8, 0x4402331e},
108 {0x0000a0ec, 0x44004401},
109 {0x0000a0f0, 0x441e441f},
110 {0x0000a0f4, 0x55015502},
111 {0x0000a0f8, 0x551f5500},
112 {0x0000a0fc, 0x6602551e},
113 {0x0000a100, 0x66006601},
114 {0x0000a104, 0x661e661f},
115 {0x0000a108, 0x7703661d},
116 {0x0000a10c, 0x77017702},
117 {0x0000a110, 0x00007700},
118 {0x0000a114, 0x00000000},
119 {0x0000a118, 0x00000000},
120 {0x0000a11c, 0x00000000},
121 {0x0000a120, 0x00000000},
122 {0x0000a124, 0x00000000},
123 {0x0000a128, 0x00000000},
124 {0x0000a12c, 0x00000000},
125 {0x0000a130, 0x00000000},
126 {0x0000a134, 0x00000000},
127 {0x0000a138, 0x00000000},
128 {0x0000a13c, 0x00000000},
129 {0x0000a140, 0x001f0000},
130 {0x0000a144, 0x111f1100},
131 {0x0000a148, 0x111d111e},
132 {0x0000a14c, 0x111b111c},
133 {0x0000a150, 0x22032204},
134 {0x0000a154, 0x22012202},
135 {0x0000a158, 0x221f2200},
136 {0x0000a15c, 0x221d221e},
137 {0x0000a160, 0x33013302},
138 {0x0000a164, 0x331f3300},
139 {0x0000a168, 0x4402331e},
140 {0x0000a16c, 0x44004401},
141 {0x0000a170, 0x441e441f},
142 {0x0000a174, 0x55015502},
143 {0x0000a178, 0x551f5500},
144 {0x0000a17c, 0x6602551e},
145 {0x0000a180, 0x66006601},
146 {0x0000a184, 0x661e661f},
147 {0x0000a188, 0x7703661d},
148 {0x0000a18c, 0x77017702},
149 {0x0000a190, 0x00007700},
150 {0x0000a194, 0x00000000},
151 {0x0000a198, 0x00000000},
152 {0x0000a19c, 0x00000000},
153 {0x0000a1a0, 0x00000000},
154 {0x0000a1a4, 0x00000000},
155 {0x0000a1a8, 0x00000000},
156 {0x0000a1ac, 0x00000000},
157 {0x0000a1b0, 0x00000000},
158 {0x0000a1b4, 0x00000000},
159 {0x0000a1b8, 0x00000000},
160 {0x0000a1bc, 0x00000000},
161 {0x0000a1c0, 0x00000000},
162 {0x0000a1c4, 0x00000000},
163 {0x0000a1c8, 0x00000000},
164 {0x0000a1cc, 0x00000000},
165 {0x0000a1d0, 0x00000000},
166 {0x0000a1d4, 0x00000000},
167 {0x0000a1d8, 0x00000000},
168 {0x0000a1dc, 0x00000000},
169 {0x0000a1e0, 0x00000000},
170 {0x0000a1e4, 0x00000000},
171 {0x0000a1e8, 0x00000000},
172 {0x0000a1ec, 0x00000000},
173 {0x0000a1f0, 0x00000396},
174 {0x0000a1f4, 0x00000396},
175 {0x0000a1f8, 0x00000396},
176 {0x0000a1fc, 0x00000296},
177};
178
179static const u32 ar9485Modes_high_power_tx_gain_1_0[][5] = {
180 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
181 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
182 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
183 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
184 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
185 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
186 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
187 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
188 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
189 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
190 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
191 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
192 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
193 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
194 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
195 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
196 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
197 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
198 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
199 {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
200 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
201 {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
202 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
203 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
204 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
205 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
206 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
207 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
208 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
209 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
210 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
211 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
212 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
213 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
214 {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
215};
216
217static const u32 ar9485_1_0[][2] = {
218 /* Addr allmodes */
219 {0x0000a580, 0x00000000},
220 {0x0000a584, 0x00000000},
221 {0x0000a588, 0x00000000},
222 {0x0000a58c, 0x00000000},
223 {0x0000a590, 0x00000000},
224 {0x0000a594, 0x00000000},
225 {0x0000a598, 0x00000000},
226 {0x0000a59c, 0x00000000},
227 {0x0000a5a0, 0x00000000},
228 {0x0000a5a4, 0x00000000},
229 {0x0000a5a8, 0x00000000},
230 {0x0000a5ac, 0x00000000},
231 {0x0000a5b0, 0x00000000},
232 {0x0000a5b4, 0x00000000},
233 {0x0000a5b8, 0x00000000},
234 {0x0000a5bc, 0x00000000},
235};
236
237static const u32 ar9485_1_0_radio_core[][2] = {
238 /* Addr allmodes */
239 {0x00016000, 0x36db6db6},
240 {0x00016004, 0x6db6db40},
241 {0x00016008, 0x73800000},
242 {0x0001600c, 0x00000000},
243 {0x00016040, 0x7f80fff8},
244 {0x00016048, 0x6c92426e},
245 {0x0001604c, 0x000f0278},
246 {0x00016050, 0x6db6db6c},
247 {0x00016054, 0x6db60000},
248 {0x00016080, 0x00080000},
249 {0x00016084, 0x0e48048c},
250 {0x00016088, 0x14214514},
251 {0x0001608c, 0x119f081e},
252 {0x00016090, 0x24926490},
253 {0x00016098, 0xd28b3330},
254 {0x000160a0, 0xc2108ffe},
255 {0x000160a4, 0x812fc370},
256 {0x000160a8, 0x423c8000},
257 {0x000160b4, 0x92480040},
258 {0x000160c0, 0x006db6db},
259 {0x000160c4, 0x0186db60},
260 {0x000160c8, 0x6db6db6c},
261 {0x000160cc, 0x6de6fbe0},
262 {0x000160d0, 0xf7dfcf3c},
263 {0x00016100, 0x04cb0001},
264 {0x00016104, 0xfff80015},
265 {0x00016108, 0x00080010},
266 {0x00016144, 0x01884080},
267 {0x00016148, 0x00008040},
268 {0x00016180, 0x08453333},
269 {0x00016184, 0x18e82f01},
270 {0x00016188, 0x00000000},
271 {0x0001618c, 0x00000000},
272 {0x00016240, 0x08400000},
273 {0x00016244, 0x1bf90f00},
274 {0x00016248, 0x00000000},
275 {0x0001624c, 0x00000000},
276 {0x00016280, 0x01000015},
277 {0x00016284, 0x00d30000},
278 {0x00016288, 0x00318000},
279 {0x0001628c, 0x50000000},
280 {0x00016290, 0x4b96210f},
281 {0x00016380, 0x00000000},
282 {0x00016384, 0x00000000},
283 {0x00016388, 0x00800700},
284 {0x0001638c, 0x00800700},
285 {0x00016390, 0x00800700},
286 {0x00016394, 0x00000000},
287 {0x00016398, 0x00000000},
288 {0x0001639c, 0x00000000},
289 {0x000163a0, 0x00000001},
290 {0x000163a4, 0x00000001},
291 {0x000163a8, 0x00000000},
292 {0x000163ac, 0x00000000},
293 {0x000163b0, 0x00000000},
294 {0x000163b4, 0x00000000},
295 {0x000163b8, 0x00000000},
296 {0x000163bc, 0x00000000},
297 {0x000163c0, 0x000000a0},
298 {0x000163c4, 0x000c0000},
299 {0x000163c8, 0x14021402},
300 {0x000163cc, 0x00001402},
301 {0x000163d0, 0x00000000},
302 {0x000163d4, 0x00000000},
303 {0x00016c40, 0x1319c178},
304 {0x00016c44, 0x10000000},
305};
306
307static const u32 ar9485Modes_lowest_ob_db_tx_gain_1_0[][5] = {
308 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
309 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
310 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
311 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
312 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
313 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
314 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
315 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
316 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
317 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
318 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
319 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
320 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
321 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
322 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
323 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
324 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
325 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
326 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
327 {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
328 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
329 {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
330 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
331 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
332 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
333 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
334 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
335 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
336 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
337 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
338 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
339 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
340 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
341 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
342 {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
343};
344
345static const u32 ar9485_1_0_baseband_core[][2] = {
346 /* Addr allmodes */
347 {0x00009800, 0xafe68e30},
348 {0x00009804, 0xfd14e000},
349 {0x00009808, 0x9c0a8f6b},
350 {0x0000980c, 0x04800000},
351 {0x00009814, 0x9280c00a},
352 {0x00009818, 0x00000000},
353 {0x0000981c, 0x00020028},
354 {0x00009834, 0x5f3ca3de},
355 {0x00009838, 0x0108ecff},
356 {0x0000983c, 0x14750600},
357 {0x00009880, 0x201fff00},
358 {0x00009884, 0x00001042},
359 {0x000098a4, 0x00200400},
360 {0x000098b0, 0x52440bbe},
361 {0x000098bc, 0x00000002},
362 {0x000098d0, 0x004b6a8e},
363 {0x000098d4, 0x00000820},
364 {0x000098dc, 0x00000000},
365 {0x000098f0, 0x00000000},
366 {0x000098f4, 0x00000000},
367 {0x00009c04, 0x00000000},
368 {0x00009c08, 0x03200000},
369 {0x00009c0c, 0x00000000},
370 {0x00009c10, 0x00000000},
371 {0x00009c14, 0x00046384},
372 {0x00009c18, 0x05b6b440},
373 {0x00009c1c, 0x00b6b440},
374 {0x00009d00, 0xc080a333},
375 {0x00009d04, 0x40206c10},
376 {0x00009d08, 0x009c4060},
377 {0x00009d0c, 0x1883800a},
378 {0x00009d10, 0x01834061},
379 {0x00009d14, 0x00c00400},
380 {0x00009d18, 0x00000000},
381 {0x00009d1c, 0x00000000},
382 {0x00009e08, 0x0038233c},
383 {0x00009e24, 0x990bb515},
384 {0x00009e28, 0x0a6f0000},
385 {0x00009e30, 0x06336f77},
386 {0x00009e34, 0x6af6532f},
387 {0x00009e38, 0x0cc80c00},
388 {0x00009e40, 0x0d261820},
389 {0x00009e4c, 0x00001004},
390 {0x00009e50, 0x00ff03f1},
391 {0x00009fc0, 0x80be4788},
392 {0x00009fc4, 0x0001efb5},
393 {0x00009fcc, 0x40000014},
394 {0x0000a20c, 0x00000000},
395 {0x0000a210, 0x00000000},
396 {0x0000a220, 0x00000000},
397 {0x0000a224, 0x00000000},
398 {0x0000a228, 0x10002310},
399 {0x0000a23c, 0x00000000},
400 {0x0000a244, 0x0c000000},
401 {0x0000a2a0, 0x00000001},
402 {0x0000a2c0, 0x00000001},
403 {0x0000a2c8, 0x00000000},
404 {0x0000a2cc, 0x18c43433},
405 {0x0000a2d4, 0x00000000},
406 {0x0000a2dc, 0x00000000},
407 {0x0000a2e0, 0x00000000},
408 {0x0000a2e4, 0x00000000},
409 {0x0000a2e8, 0x00000000},
410 {0x0000a2ec, 0x00000000},
411 {0x0000a2f0, 0x00000000},
412 {0x0000a2f4, 0x00000000},
413 {0x0000a2f8, 0x00000000},
414 {0x0000a344, 0x00000000},
415 {0x0000a34c, 0x00000000},
416 {0x0000a350, 0x0000a000},
417 {0x0000a364, 0x00000000},
418 {0x0000a370, 0x00000000},
419 {0x0000a390, 0x00000001},
420 {0x0000a394, 0x00000444},
421 {0x0000a398, 0x001f0e0f},
422 {0x0000a39c, 0x0075393f},
423 {0x0000a3a0, 0xb79f6427},
424 {0x0000a3a4, 0x00000000},
425 {0x0000a3a8, 0xaaaaaaaa},
426 {0x0000a3ac, 0x3c466478},
427 {0x0000a3c0, 0x20202020},
428 {0x0000a3c4, 0x22222220},
429 {0x0000a3c8, 0x20200020},
430 {0x0000a3cc, 0x20202020},
431 {0x0000a3d0, 0x20202020},
432 {0x0000a3d4, 0x20202020},
433 {0x0000a3d8, 0x20202020},
434 {0x0000a3dc, 0x20202020},
435 {0x0000a3e0, 0x20202020},
436 {0x0000a3e4, 0x20202020},
437 {0x0000a3e8, 0x20202020},
438 {0x0000a3ec, 0x20202020},
439 {0x0000a3f0, 0x00000000},
440 {0x0000a3f4, 0x00000006},
441 {0x0000a3f8, 0x0cdbd380},
442 {0x0000a3fc, 0x000f0f01},
443 {0x0000a400, 0x8fa91f01},
444 {0x0000a404, 0x00000000},
445 {0x0000a408, 0x0e79e5c6},
446 {0x0000a40c, 0x00820820},
447 {0x0000a414, 0x1ce739ce},
448 {0x0000a418, 0x2d0011ce},
449 {0x0000a41c, 0x1ce739ce},
450 {0x0000a420, 0x000001ce},
451 {0x0000a424, 0x1ce739ce},
452 {0x0000a428, 0x000001ce},
453 {0x0000a42c, 0x1ce739ce},
454 {0x0000a430, 0x1ce739ce},
455 {0x0000a434, 0x00000000},
456 {0x0000a438, 0x00001801},
457 {0x0000a43c, 0x00000000},
458 {0x0000a440, 0x00000000},
459 {0x0000a444, 0x00000000},
460 {0x0000a448, 0x04000000},
461 {0x0000a44c, 0x00000001},
462 {0x0000a450, 0x00010000},
463 {0x0000a458, 0x00000000},
464 {0x0000a5c4, 0x3fad9d74},
465 {0x0000a5c8, 0x0048060a},
466 {0x0000a5cc, 0x00000637},
467 {0x0000a760, 0x03020100},
468 {0x0000a764, 0x09080504},
469 {0x0000a768, 0x0d0c0b0a},
470 {0x0000a76c, 0x13121110},
471 {0x0000a770, 0x31301514},
472 {0x0000a774, 0x35343332},
473 {0x0000a778, 0x00000036},
474 {0x0000a780, 0x00000838},
475 {0x0000a7c0, 0x00000000},
476 {0x0000a7c4, 0xfffffffc},
477 {0x0000a7c8, 0x00000000},
478 {0x0000a7cc, 0x00000000},
479 {0x0000a7d0, 0x00000000},
480 {0x0000a7d4, 0x00000004},
481 {0x0000a7dc, 0x00000001},
482};
483
484static const u32 ar9485Modes_high_ob_db_tx_gain_1_0[][5] = {
485 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
486 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
487 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
488 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
489 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
490 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
491 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
492 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
493 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
494 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
495 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
496 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
497 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
498 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
499 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
500 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
501 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
502 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
503 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
504 {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
505 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
506 {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
507 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
508 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
509 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
510 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
511 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
512 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
513 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
514 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
515 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
516 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
517 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
518 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
519 {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
520};
521
522static const u32 ar9485Common_rx_gain_1_0[][2] = {
523 /* Addr allmodes */
524 {0x0000a000, 0x00010000},
525 {0x0000a004, 0x00030002},
526 {0x0000a008, 0x00050004},
527 {0x0000a00c, 0x00810080},
528 {0x0000a010, 0x01800082},
529 {0x0000a014, 0x01820181},
530 {0x0000a018, 0x01840183},
531 {0x0000a01c, 0x01880185},
532 {0x0000a020, 0x018a0189},
533 {0x0000a024, 0x02850284},
534 {0x0000a028, 0x02890288},
535 {0x0000a02c, 0x03850384},
536 {0x0000a030, 0x03890388},
537 {0x0000a034, 0x038b038a},
538 {0x0000a038, 0x038d038c},
539 {0x0000a03c, 0x03910390},
540 {0x0000a040, 0x03930392},
541 {0x0000a044, 0x03950394},
542 {0x0000a048, 0x00000396},
543 {0x0000a04c, 0x00000000},
544 {0x0000a050, 0x00000000},
545 {0x0000a054, 0x00000000},
546 {0x0000a058, 0x00000000},
547 {0x0000a05c, 0x00000000},
548 {0x0000a060, 0x00000000},
549 {0x0000a064, 0x00000000},
550 {0x0000a068, 0x00000000},
551 {0x0000a06c, 0x00000000},
552 {0x0000a070, 0x00000000},
553 {0x0000a074, 0x00000000},
554 {0x0000a078, 0x00000000},
555 {0x0000a07c, 0x00000000},
556 {0x0000a080, 0x28282828},
557 {0x0000a084, 0x28282828},
558 {0x0000a088, 0x28282828},
559 {0x0000a08c, 0x28282828},
560 {0x0000a090, 0x28282828},
561 {0x0000a094, 0x21212128},
562 {0x0000a098, 0x171c1c1c},
563 {0x0000a09c, 0x02020212},
564 {0x0000a0a0, 0x00000202},
565 {0x0000a0a4, 0x00000000},
566 {0x0000a0a8, 0x00000000},
567 {0x0000a0ac, 0x00000000},
568 {0x0000a0b0, 0x00000000},
569 {0x0000a0b4, 0x00000000},
570 {0x0000a0b8, 0x00000000},
571 {0x0000a0bc, 0x00000000},
572 {0x0000a0c0, 0x001f0000},
573 {0x0000a0c4, 0x111f1100},
574 {0x0000a0c8, 0x111d111e},
575 {0x0000a0cc, 0x111b111c},
576 {0x0000a0d0, 0x22032204},
577 {0x0000a0d4, 0x22012202},
578 {0x0000a0d8, 0x221f2200},
579 {0x0000a0dc, 0x221d221e},
580 {0x0000a0e0, 0x33013302},
581 {0x0000a0e4, 0x331f3300},
582 {0x0000a0e8, 0x4402331e},
583 {0x0000a0ec, 0x44004401},
584 {0x0000a0f0, 0x441e441f},
585 {0x0000a0f4, 0x55015502},
586 {0x0000a0f8, 0x551f5500},
587 {0x0000a0fc, 0x6602551e},
588 {0x0000a100, 0x66006601},
589 {0x0000a104, 0x661e661f},
590 {0x0000a108, 0x7703661d},
591 {0x0000a10c, 0x77017702},
592 {0x0000a110, 0x00007700},
593 {0x0000a114, 0x00000000},
594 {0x0000a118, 0x00000000},
595 {0x0000a11c, 0x00000000},
596 {0x0000a120, 0x00000000},
597 {0x0000a124, 0x00000000},
598 {0x0000a128, 0x00000000},
599 {0x0000a12c, 0x00000000},
600 {0x0000a130, 0x00000000},
601 {0x0000a134, 0x00000000},
602 {0x0000a138, 0x00000000},
603 {0x0000a13c, 0x00000000},
604 {0x0000a140, 0x001f0000},
605 {0x0000a144, 0x111f1100},
606 {0x0000a148, 0x111d111e},
607 {0x0000a14c, 0x111b111c},
608 {0x0000a150, 0x22032204},
609 {0x0000a154, 0x22012202},
610 {0x0000a158, 0x221f2200},
611 {0x0000a15c, 0x221d221e},
612 {0x0000a160, 0x33013302},
613 {0x0000a164, 0x331f3300},
614 {0x0000a168, 0x4402331e},
615 {0x0000a16c, 0x44004401},
616 {0x0000a170, 0x441e441f},
617 {0x0000a174, 0x55015502},
618 {0x0000a178, 0x551f5500},
619 {0x0000a17c, 0x6602551e},
620 {0x0000a180, 0x66006601},
621 {0x0000a184, 0x661e661f},
622 {0x0000a188, 0x7703661d},
623 {0x0000a18c, 0x77017702},
624 {0x0000a190, 0x00007700},
625 {0x0000a194, 0x00000000},
626 {0x0000a198, 0x00000000},
627 {0x0000a19c, 0x00000000},
628 {0x0000a1a0, 0x00000000},
629 {0x0000a1a4, 0x00000000},
630 {0x0000a1a8, 0x00000000},
631 {0x0000a1ac, 0x00000000},
632 {0x0000a1b0, 0x00000000},
633 {0x0000a1b4, 0x00000000},
634 {0x0000a1b8, 0x00000000},
635 {0x0000a1bc, 0x00000000},
636 {0x0000a1c0, 0x00000000},
637 {0x0000a1c4, 0x00000000},
638 {0x0000a1c8, 0x00000000},
639 {0x0000a1cc, 0x00000000},
640 {0x0000a1d0, 0x00000000},
641 {0x0000a1d4, 0x00000000},
642 {0x0000a1d8, 0x00000000},
643 {0x0000a1dc, 0x00000000},
644 {0x0000a1e0, 0x00000000},
645 {0x0000a1e4, 0x00000000},
646 {0x0000a1e8, 0x00000000},
647 {0x0000a1ec, 0x00000000},
648 {0x0000a1f0, 0x00000396},
649 {0x0000a1f4, 0x00000396},
650 {0x0000a1f8, 0x00000396},
651 {0x0000a1fc, 0x00000296},
652};
653
654static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
655 /* Addr allmodes */
656 {0x00018c00, 0x10252e5e},
657 {0x00018c04, 0x000801d8},
658 {0x00018c08, 0x0000580c},
659};
660
661static const u32 ar9485_1_0_pcie_phy_clkreq_enable_L1[][2] = {
662 /* Addr allmodes */
663 {0x00018c00, 0x10253e5e},
664 {0x00018c04, 0x000801d8},
665 {0x00018c08, 0x0000580c},
666};
667
668static const u32 ar9485_1_0_soc_preamble[][2] = {
669 /* Addr allmodes */
670 {0x000040a4, 0x00a0c9c9},
671 {0x00007048, 0x00000004},
672};
673
674static const u32 ar9485_fast_clock_1_0_baseband_postamble[][3] = {
675 /* Addr 5G_HT20 5G_HT40 */
676 {0x00009e00, 0x03721821, 0x03721821},
677 {0x0000a230, 0x0000400b, 0x00004016},
678 {0x0000a254, 0x00000898, 0x00001130},
679};
680
681static const u32 ar9485_1_0_baseband_postamble[][5] = {
682 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
683 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
684 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
685 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
686 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
687 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
688 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
689 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
690 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
691 {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
692 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
693 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e},
694 {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
695 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
696 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
697 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
698 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
699 {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
700 {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
701 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
702 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
703 {0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0},
704 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
705 {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
706 {0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff},
707 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
708 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
709 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
710 {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
711 {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
712 {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
713 {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
714 {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
715 {0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0},
716 {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
717 {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
718 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
719 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
720 {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
721 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
722 {0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
723 {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
724};
725
726static const u32 ar9485Modes_low_ob_db_tx_gain_1_0[][5] = {
727 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
728 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
729 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
730 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
731 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
732 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
733 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
734 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
735 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
736 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
737 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
738 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
739 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
740 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
741 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
742 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
743 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
744 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
745 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
746 {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
747 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
748 {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
749 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
750 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
751 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
752 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
753 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
754 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
755 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
756 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
757 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
758 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
759 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
760 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
761 {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
762};
763
764static const u32 ar9485_1_0_pcie_phy_clkreq_disable_L1[][2] = {
765 /* Addr allmodes */
766 {0x00018c00, 0x10213e5e},
767 {0x00018c04, 0x000801d8},
768 {0x00018c08, 0x0000580c},
769};
770
771static const u32 ar9485_1_0_radio_postamble[][2] = {
772 /* Addr allmodes */
773 {0x0001609c, 0x0b283f31},
774 {0x000160ac, 0x24611800},
775 {0x000160b0, 0x03284f3e},
776 {0x0001610c, 0x00170000},
777 {0x00016140, 0x10804008},
778};
779
780static const u32 ar9485_1_0_mac_core[][2] = {
781 /* Addr allmodes */
782 {0x00000008, 0x00000000},
783 {0x00000030, 0x00020085},
784 {0x00000034, 0x00000005},
785 {0x00000040, 0x00000000},
786 {0x00000044, 0x00000000},
787 {0x00000048, 0x00000008},
788 {0x0000004c, 0x00000010},
789 {0x00000050, 0x00000000},
790 {0x00001040, 0x002ffc0f},
791 {0x00001044, 0x002ffc0f},
792 {0x00001048, 0x002ffc0f},
793 {0x0000104c, 0x002ffc0f},
794 {0x00001050, 0x002ffc0f},
795 {0x00001054, 0x002ffc0f},
796 {0x00001058, 0x002ffc0f},
797 {0x0000105c, 0x002ffc0f},
798 {0x00001060, 0x002ffc0f},
799 {0x00001064, 0x002ffc0f},
800 {0x000010f0, 0x00000100},
801 {0x00001270, 0x00000000},
802 {0x000012b0, 0x00000000},
803 {0x000012f0, 0x00000000},
804 {0x0000143c, 0x00000000},
805 {0x0000147c, 0x00000000},
806 {0x00008000, 0x00000000},
807 {0x00008004, 0x00000000},
808 {0x00008008, 0x00000000},
809 {0x0000800c, 0x00000000},
810 {0x00008018, 0x00000000},
811 {0x00008020, 0x00000000},
812 {0x00008038, 0x00000000},
813 {0x0000803c, 0x00000000},
814 {0x00008040, 0x00000000},
815 {0x00008044, 0x00000000},
816 {0x00008048, 0x00000000},
817 {0x0000804c, 0xffffffff},
818 {0x00008054, 0x00000000},
819 {0x00008058, 0x00000000},
820 {0x0000805c, 0x000fc78f},
821 {0x00008060, 0x0000000f},
822 {0x00008064, 0x00000000},
823 {0x00008070, 0x00000310},
824 {0x00008074, 0x00000020},
825 {0x00008078, 0x00000000},
826 {0x0000809c, 0x0000000f},
827 {0x000080a0, 0x00000000},
828 {0x000080a4, 0x02ff0000},
829 {0x000080a8, 0x0e070605},
830 {0x000080ac, 0x0000000d},
831 {0x000080b0, 0x00000000},
832 {0x000080b4, 0x00000000},
833 {0x000080b8, 0x00000000},
834 {0x000080bc, 0x00000000},
835 {0x000080c0, 0x2a800000},
836 {0x000080c4, 0x06900168},
837 {0x000080c8, 0x13881c20},
838 {0x000080cc, 0x01f40000},
839 {0x000080d0, 0x00252500},
840 {0x000080d4, 0x00a00000},
841 {0x000080d8, 0x00400000},
842 {0x000080dc, 0x00000000},
843 {0x000080e0, 0xffffffff},
844 {0x000080e4, 0x0000ffff},
845 {0x000080e8, 0x3f3f3f3f},
846 {0x000080ec, 0x00000000},
847 {0x000080f0, 0x00000000},
848 {0x000080f4, 0x00000000},
849 {0x000080fc, 0x00020000},
850 {0x00008100, 0x00000000},
851 {0x00008108, 0x00000052},
852 {0x0000810c, 0x00000000},
853 {0x00008110, 0x00000000},
854 {0x00008114, 0x000007ff},
855 {0x00008118, 0x000000aa},
856 {0x0000811c, 0x00003210},
857 {0x00008124, 0x00000000},
858 {0x00008128, 0x00000000},
859 {0x0000812c, 0x00000000},
860 {0x00008130, 0x00000000},
861 {0x00008134, 0x00000000},
862 {0x00008138, 0x00000000},
863 {0x0000813c, 0x0000ffff},
864 {0x00008144, 0xffffffff},
865 {0x00008168, 0x00000000},
866 {0x0000816c, 0x00000000},
867 {0x00008170, 0x18486200},
868 {0x00008174, 0x33332210},
869 {0x00008178, 0x00000000},
870 {0x0000817c, 0x00020000},
871 {0x000081c0, 0x00000000},
872 {0x000081c4, 0x33332210},
873 {0x000081c8, 0x00000000},
874 {0x000081cc, 0x00000000},
875 {0x000081d4, 0x00000000},
876 {0x000081ec, 0x00000000},
877 {0x000081f0, 0x00000000},
878 {0x000081f4, 0x00000000},
879 {0x000081f8, 0x00000000},
880 {0x000081fc, 0x00000000},
881 {0x00008240, 0x00100000},
882 {0x00008244, 0x0010f400},
883 {0x00008248, 0x00000800},
884 {0x0000824c, 0x0001e800},
885 {0x00008250, 0x00000000},
886 {0x00008254, 0x00000000},
887 {0x00008258, 0x00000000},
888 {0x0000825c, 0x40000000},
889 {0x00008260, 0x00080922},
890 {0x00008264, 0x9ca00010},
891 {0x00008268, 0xffffffff},
892 {0x0000826c, 0x0000ffff},
893 {0x00008270, 0x00000000},
894 {0x00008274, 0x40000000},
895 {0x00008278, 0x003e4180},
896 {0x0000827c, 0x00000004},
897 {0x00008284, 0x0000002c},
898 {0x00008288, 0x0000002c},
899 {0x0000828c, 0x000000ff},
900 {0x00008294, 0x00000000},
901 {0x00008298, 0x00000000},
902 {0x0000829c, 0x00000000},
903 {0x00008300, 0x00000140},
904 {0x00008314, 0x00000000},
905 {0x0000831c, 0x0000010d},
906 {0x00008328, 0x00000000},
907 {0x0000832c, 0x00000007},
908 {0x00008330, 0x00000302},
909 {0x00008334, 0x00000700},
910 {0x00008338, 0x00ff0000},
911 {0x0000833c, 0x02400000},
912 {0x00008340, 0x000107ff},
913 {0x00008344, 0xa248105b},
914 {0x00008348, 0x008f0000},
915 {0x0000835c, 0x00000000},
916 {0x00008360, 0xffffffff},
917 {0x00008364, 0xffffffff},
918 {0x00008368, 0x00000000},
919 {0x00008370, 0x00000000},
920 {0x00008374, 0x000000ff},
921 {0x00008378, 0x00000000},
922 {0x0000837c, 0x00000000},
923 {0x00008380, 0xffffffff},
924 {0x00008384, 0xffffffff},
925 {0x00008390, 0xffffffff},
926 {0x00008394, 0xffffffff},
927 {0x00008398, 0x00000000},
928 {0x0000839c, 0x00000000},
929 {0x000083a0, 0x00000000},
930 {0x000083a4, 0x0000fa14},
931 {0x000083a8, 0x000f0c00},
932 {0x000083ac, 0x33332210},
933 {0x000083b0, 0x33332210},
934 {0x000083b4, 0x33332210},
935 {0x000083b8, 0x33332210},
936 {0x000083bc, 0x00000000},
937 {0x000083c0, 0x00000000},
938 {0x000083c4, 0x00000000},
939 {0x000083c8, 0x00000000},
940 {0x000083cc, 0x00000200},
941 {0x000083d0, 0x000301ff},
942};
943#endif
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 4210a9306955..9b5501f90010 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -311,7 +311,7 @@ void ath_rx_cleanup(struct ath_softc *sc);
311int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 311int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
312struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 312struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
313void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 313void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
314void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); 314bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
315void ath_draintxq(struct ath_softc *sc, 315void ath_draintxq(struct ath_softc *sc,
316 struct ath_txq *txq, bool retry_tx); 316 struct ath_txq *txq, bool retry_tx);
317void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 317void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 47bedd82e9a9..5e108c086904 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -46,8 +46,8 @@ int ath_beaconq_config(struct ath_softc *sc)
46 } 46 }
47 47
48 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) { 48 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
49 ath_print(common, ATH_DBG_FATAL, 49 ath_err(common,
50 "Unable to update h/w beacon queue parameters\n"); 50 "Unable to update h/w beacon queue parameters\n");
51 return 0; 51 return 0;
52 } else { 52 } else {
53 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq); 53 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
@@ -120,11 +120,11 @@ static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
120 memset(&txctl, 0, sizeof(struct ath_tx_control)); 120 memset(&txctl, 0, sizeof(struct ath_tx_control));
121 txctl.txq = sc->beacon.cabq; 121 txctl.txq = sc->beacon.cabq;
122 122
123 ath_print(common, ATH_DBG_XMIT, 123 ath_dbg(common, ATH_DBG_XMIT,
124 "transmitting CABQ packet, skb: %p\n", skb); 124 "transmitting CABQ packet, skb: %p\n", skb);
125 125
126 if (ath_tx_start(hw, skb, &txctl) != 0) { 126 if (ath_tx_start(hw, skb, &txctl) != 0) {
127 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n"); 127 ath_dbg(common, ATH_DBG_XMIT, "CABQ TX failed\n");
128 dev_kfree_skb_any(skb); 128 dev_kfree_skb_any(skb);
129 } 129 }
130} 130}
@@ -189,8 +189,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
189 dev_kfree_skb_any(skb); 189 dev_kfree_skb_any(skb);
190 bf->bf_mpdu = NULL; 190 bf->bf_mpdu = NULL;
191 bf->bf_buf_addr = 0; 191 bf->bf_buf_addr = 0;
192 ath_print(common, ATH_DBG_FATAL, 192 ath_err(common, "dma_mapping_error on beaconing\n");
193 "dma_mapping_error on beaconing\n");
194 return NULL; 193 return NULL;
195 } 194 }
196 195
@@ -210,8 +209,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
210 209
211 if (skb && cabq_depth) { 210 if (skb && cabq_depth) {
212 if (sc->nvifs > 1) { 211 if (sc->nvifs > 1) {
213 ath_print(common, ATH_DBG_BEACON, 212 ath_dbg(common, ATH_DBG_BEACON,
214 "Flushing previous cabq traffic\n"); 213 "Flushing previous cabq traffic\n");
215 ath_draintxq(sc, cabq, false); 214 ath_draintxq(sc, cabq, false);
216 } 215 }
217 } 216 }
@@ -283,7 +282,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
283 /* NB: the beacon data buffer must be 32-bit aligned. */ 282 /* NB: the beacon data buffer must be 32-bit aligned. */
284 skb = ieee80211_beacon_get(sc->hw, vif); 283 skb = ieee80211_beacon_get(sc->hw, vif);
285 if (skb == NULL) { 284 if (skb == NULL) {
286 ath_print(common, ATH_DBG_BEACON, "cannot get skb\n"); 285 ath_dbg(common, ATH_DBG_BEACON, "cannot get skb\n");
287 return -ENOMEM; 286 return -ENOMEM;
288 } 287 }
289 288
@@ -307,10 +306,9 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
307 tsfadjust = intval * avp->av_bslot / ATH_BCBUF; 306 tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
308 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); 307 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
309 308
310 ath_print(common, ATH_DBG_BEACON, 309 ath_dbg(common, ATH_DBG_BEACON,
311 "stagger beacons, bslot %d intval " 310 "stagger beacons, bslot %d intval %u tsfadjust %llu\n",
312 "%u tsfadjust %llu\n", 311 avp->av_bslot, intval, (unsigned long long)tsfadjust);
313 avp->av_bslot, intval, (unsigned long long)tsfadjust);
314 312
315 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp = 313 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
316 avp->tsf_adjust; 314 avp->tsf_adjust;
@@ -324,8 +322,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
324 dev_kfree_skb_any(skb); 322 dev_kfree_skb_any(skb);
325 bf->bf_mpdu = NULL; 323 bf->bf_mpdu = NULL;
326 bf->bf_buf_addr = 0; 324 bf->bf_buf_addr = 0;
327 ath_print(common, ATH_DBG_FATAL, 325 ath_err(common, "dma_mapping_error on beacon alloc\n");
328 "dma_mapping_error on beacon alloc\n");
329 return -ENOMEM; 326 return -ENOMEM;
330 } 327 }
331 328
@@ -382,13 +379,13 @@ void ath_beacon_tasklet(unsigned long data)
382 sc->beacon.bmisscnt++; 379 sc->beacon.bmisscnt++;
383 380
384 if (sc->beacon.bmisscnt < BSTUCK_THRESH) { 381 if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
385 ath_print(common, ATH_DBG_BSTUCK, 382 ath_dbg(common, ATH_DBG_BSTUCK,
386 "missed %u consecutive beacons\n", 383 "missed %u consecutive beacons\n",
387 sc->beacon.bmisscnt); 384 sc->beacon.bmisscnt);
388 ath9k_hw_bstuck_nfcal(ah); 385 ath9k_hw_bstuck_nfcal(ah);
389 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { 386 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
390 ath_print(common, ATH_DBG_BSTUCK, 387 ath_dbg(common, ATH_DBG_BSTUCK,
391 "beacon is officially stuck\n"); 388 "beacon is officially stuck\n");
392 sc->sc_flags |= SC_OP_TSF_RESET; 389 sc->sc_flags |= SC_OP_TSF_RESET;
393 ath_reset(sc, true); 390 ath_reset(sc, true);
394 } 391 }
@@ -397,9 +394,9 @@ void ath_beacon_tasklet(unsigned long data)
397 } 394 }
398 395
399 if (sc->beacon.bmisscnt != 0) { 396 if (sc->beacon.bmisscnt != 0) {
400 ath_print(common, ATH_DBG_BSTUCK, 397 ath_dbg(common, ATH_DBG_BSTUCK,
401 "resume beacon xmit after %u misses\n", 398 "resume beacon xmit after %u misses\n",
402 sc->beacon.bmisscnt); 399 sc->beacon.bmisscnt);
403 sc->beacon.bmisscnt = 0; 400 sc->beacon.bmisscnt = 0;
404 } 401 }
405 402
@@ -425,9 +422,9 @@ void ath_beacon_tasklet(unsigned long data)
425 vif = sc->beacon.bslot[slot]; 422 vif = sc->beacon.bslot[slot];
426 aphy = sc->beacon.bslot_aphy[slot]; 423 aphy = sc->beacon.bslot_aphy[slot];
427 424
428 ath_print(common, ATH_DBG_BEACON, 425 ath_dbg(common, ATH_DBG_BEACON,
429 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n", 426 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
430 slot, tsf, tsftu, intval, vif); 427 slot, tsf, tsftu, intval, vif);
431 428
432 bfaddr = 0; 429 bfaddr = 0;
433 if (vif) { 430 if (vif) {
@@ -469,8 +466,8 @@ void ath_beacon_tasklet(unsigned long data)
469 * are still pending on the queue. 466 * are still pending on the queue.
470 */ 467 */
471 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) { 468 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
472 ath_print(common, ATH_DBG_FATAL, 469 ath_err(common, "beacon queue %u did not stop?\n",
473 "beacon queue %u did not stop?\n", sc->beacon.beaconq); 470 sc->beacon.beaconq);
474 } 471 }
475 472
476 /* NB: cabq traffic should already be queued and primed */ 473 /* NB: cabq traffic should already be queued and primed */
@@ -556,8 +553,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
556 553
557 /* No need to configure beacon if we are not associated */ 554 /* No need to configure beacon if we are not associated */
558 if (!common->curaid) { 555 if (!common->curaid) {
559 ath_print(common, ATH_DBG_BEACON, 556 ath_dbg(common, ATH_DBG_BEACON,
560 "STA is not yet associated..skipping beacon config\n"); 557 "STA is not yet associated..skipping beacon config\n");
561 return; 558 return;
562 } 559 }
563 560
@@ -650,11 +647,11 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
650 /* TSF out of range threshold fixed at 1 second */ 647 /* TSF out of range threshold fixed at 1 second */
651 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; 648 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
652 649
653 ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); 650 ath_dbg(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
654 ath_print(common, ATH_DBG_BEACON, 651 ath_dbg(common, ATH_DBG_BEACON,
655 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", 652 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
656 bs.bs_bmissthreshold, bs.bs_sleepduration, 653 bs.bs_bmissthreshold, bs.bs_sleepduration,
657 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); 654 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
658 655
659 /* Set the computed STA beacon timers */ 656 /* Set the computed STA beacon timers */
660 657
@@ -690,9 +687,9 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
690 nexttbtt += intval; 687 nexttbtt += intval;
691 } while (nexttbtt < tsftu); 688 } while (nexttbtt < tsftu);
692 689
693 ath_print(common, ATH_DBG_BEACON, 690 ath_dbg(common, ATH_DBG_BEACON,
694 "IBSS nexttbtt %u intval %u (%u)\n", 691 "IBSS nexttbtt %u intval %u (%u)\n",
695 nexttbtt, intval, conf->beacon_interval); 692 nexttbtt, intval, conf->beacon_interval);
696 693
697 /* 694 /*
698 * In IBSS mode enable the beacon timers but only enable SWBA interrupts 695 * In IBSS mode enable the beacon timers but only enable SWBA interrupts
@@ -755,8 +752,8 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
755 ath_beacon_config_sta(sc, cur_conf); 752 ath_beacon_config_sta(sc, cur_conf);
756 break; 753 break;
757 default: 754 default:
758 ath_print(common, ATH_DBG_CONFIG, 755 ath_dbg(common, ATH_DBG_CONFIG,
759 "Unsupported beaconing mode\n"); 756 "Unsupported beaconing mode\n");
760 return; 757 return;
761 } 758 }
762 759
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 6d509484b5f6..b68a1acbddd0 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -97,12 +97,12 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
97 if (h[i].privNF > limit->max) { 97 if (h[i].privNF > limit->max) {
98 high_nf_mid = true; 98 high_nf_mid = true;
99 99
100 ath_print(common, ATH_DBG_CALIBRATE, 100 ath_dbg(common, ATH_DBG_CALIBRATE,
101 "NFmid[%d] (%d) > MAX (%d), %s\n", 101 "NFmid[%d] (%d) > MAX (%d), %s\n",
102 i, h[i].privNF, limit->max, 102 i, h[i].privNF, limit->max,
103 (cal->nfcal_interference ? 103 (cal->nfcal_interference ?
104 "not corrected (due to interference)" : 104 "not corrected (due to interference)" :
105 "correcting to MAX")); 105 "correcting to MAX"));
106 106
107 /* 107 /*
108 * Normally we limit the average noise floor by the 108 * Normally we limit the average noise floor by the
@@ -180,18 +180,18 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
180 return true; 180 return true;
181 181
182 if (currCal->calState != CAL_DONE) { 182 if (currCal->calState != CAL_DONE) {
183 ath_print(common, ATH_DBG_CALIBRATE, 183 ath_dbg(common, ATH_DBG_CALIBRATE,
184 "Calibration state incorrect, %d\n", 184 "Calibration state incorrect, %d\n",
185 currCal->calState); 185 currCal->calState);
186 return true; 186 return true;
187 } 187 }
188 188
189 if (!(ah->supp_cals & currCal->calData->calType)) 189 if (!(ah->supp_cals & currCal->calData->calType))
190 return true; 190 return true;
191 191
192 ath_print(common, ATH_DBG_CALIBRATE, 192 ath_dbg(common, ATH_DBG_CALIBRATE,
193 "Resetting Cal %d state for channel %u\n", 193 "Resetting Cal %d state for channel %u\n",
194 currCal->calData->calType, conf->channel->center_freq); 194 currCal->calData->calType, conf->channel->center_freq);
195 195
196 ah->caldata->CalValid &= ~currCal->calData->calType; 196 ah->caldata->CalValid &= ~currCal->calData->calType;
197 currCal->calState = CAL_WAITING; 197 currCal->calState = CAL_WAITING;
@@ -279,9 +279,9 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
279 * noisefloor until the next calibration timer. 279 * noisefloor until the next calibration timer.
280 */ 280 */
281 if (j == 1000) { 281 if (j == 1000) {
282 ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf " 282 ath_dbg(common, ATH_DBG_ANY,
283 "to load: AR_PHY_AGC_CONTROL=0x%x\n", 283 "Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
284 REG_READ(ah, AR_PHY_AGC_CONTROL)); 284 REG_READ(ah, AR_PHY_AGC_CONTROL));
285 return; 285 return;
286 } 286 }
287 287
@@ -318,19 +318,19 @@ static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
318 if (!nf[i]) 318 if (!nf[i])
319 continue; 319 continue;
320 320
321 ath_print(common, ATH_DBG_CALIBRATE, 321 ath_dbg(common, ATH_DBG_CALIBRATE,
322 "NF calibrated [%s] [chain %d] is %d\n", 322 "NF calibrated [%s] [chain %d] is %d\n",
323 (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]); 323 (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
324 324
325 if (nf[i] > ATH9K_NF_TOO_HIGH) { 325 if (nf[i] > ATH9K_NF_TOO_HIGH) {
326 ath_print(common, ATH_DBG_CALIBRATE, 326 ath_dbg(common, ATH_DBG_CALIBRATE,
327 "NF[%d] (%d) > MAX (%d), correcting to MAX", 327 "NF[%d] (%d) > MAX (%d), correcting to MAX\n",
328 i, nf[i], ATH9K_NF_TOO_HIGH); 328 i, nf[i], ATH9K_NF_TOO_HIGH);
329 nf[i] = limit->max; 329 nf[i] = limit->max;
330 } else if (nf[i] < limit->min) { 330 } else if (nf[i] < limit->min) {
331 ath_print(common, ATH_DBG_CALIBRATE, 331 ath_dbg(common, ATH_DBG_CALIBRATE,
332 "NF[%d] (%d) < MIN (%d), correcting to NOM", 332 "NF[%d] (%d) < MIN (%d), correcting to NOM\n",
333 i, nf[i], limit->min); 333 i, nf[i], limit->min);
334 nf[i] = limit->nominal; 334 nf[i] = limit->nominal;
335 } 335 }
336 } 336 }
@@ -347,8 +347,8 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
347 347
348 chan->channelFlags &= (~CHANNEL_CW_INT); 348 chan->channelFlags &= (~CHANNEL_CW_INT);
349 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 349 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
350 ath_print(common, ATH_DBG_CALIBRATE, 350 ath_dbg(common, ATH_DBG_CALIBRATE,
351 "NF did not complete in calibration window\n"); 351 "NF did not complete in calibration window\n");
352 return false; 352 return false;
353 } 353 }
354 354
@@ -357,10 +357,9 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
357 nf = nfarray[0]; 357 nf = nfarray[0];
358 if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh) 358 if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
359 && nf > nfThresh) { 359 && nf > nfThresh) {
360 ath_print(common, ATH_DBG_CALIBRATE, 360 ath_dbg(common, ATH_DBG_CALIBRATE,
361 "noise floor failed detected; " 361 "noise floor failed detected; detected %d, threshold %d\n",
362 "detected %d, threshold %d\n", 362 nf, nfThresh);
363 nf, nfThresh);
364 chan->channelFlags |= CHANNEL_CW_INT; 363 chan->channelFlags |= CHANNEL_CW_INT;
365 } 364 }
366 365
diff --git a/drivers/net/wireless/ath/ath9k/common.c b/drivers/net/wireless/ath/ath9k/common.c
index 48b07c319a7f..df1998d48253 100644
--- a/drivers/net/wireless/ath/ath9k/common.c
+++ b/drivers/net/wireless/ath/ath9k/common.c
@@ -180,8 +180,8 @@ void ath9k_cmn_btcoex_bt_stomp(struct ath_common *common,
180 AR_STOMP_NONE_WLAN_WGHT); 180 AR_STOMP_NONE_WLAN_WGHT);
181 break; 181 break;
182 default: 182 default:
183 ath_print(common, ATH_DBG_BTCOEX, 183 ath_dbg(common, ATH_DBG_BTCOEX,
184 "Invalid Stomptype\n"); 184 "Invalid Stomptype\n");
185 break; 185 break;
186 } 186 }
187 187
diff --git a/drivers/net/wireless/ath/ath9k/common.h b/drivers/net/wireless/ath/ath9k/common.h
index 4c04ee85ff0e..a126bddebb0a 100644
--- a/drivers/net/wireless/ath/ath9k/common.h
+++ b/drivers/net/wireless/ath/ath9k/common.h
@@ -17,7 +17,6 @@
17#include <net/mac80211.h> 17#include <net/mac80211.h>
18 18
19#include "../ath.h" 19#include "../ath.h"
20#include "../debug.h"
21 20
22#include "hw.h" 21#include "hw.h"
23#include "hw-ops.h" 22#include "hw-ops.h"
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index 2bbf94d0191e..fda533cfd881 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -273,8 +273,8 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
273 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; 273 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
274 break; 274 break;
275 default: 275 default:
276 ath_print(common, ATH_DBG_EEPROM, 276 ath_dbg(common, ATH_DBG_EEPROM,
277 "Invalid chainmask configuration\n"); 277 "Invalid chainmask configuration\n");
278 break; 278 break;
279 } 279 }
280} 280}
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index c2481b3ac7e6..939fc7af86f8 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -37,14 +37,14 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
37 eep_start_loc = 64; 37 eep_start_loc = 64;
38 38
39 if (!ath9k_hw_use_flash(ah)) { 39 if (!ath9k_hw_use_flash(ah)) {
40 ath_print(common, ATH_DBG_EEPROM, 40 ath_dbg(common, ATH_DBG_EEPROM,
41 "Reading from EEPROM, not flash\n"); 41 "Reading from EEPROM, not flash\n");
42 } 42 }
43 43
44 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { 44 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
45 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) { 45 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
46 ath_print(common, ATH_DBG_EEPROM, 46 ath_dbg(common, ATH_DBG_EEPROM,
47 "Unable to read eeprom region\n"); 47 "Unable to read eeprom region\n");
48 return false; 48 return false;
49 } 49 }
50 eep_data++; 50 eep_data++;
@@ -69,13 +69,12 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
69 if (!ath9k_hw_use_flash(ah)) { 69 if (!ath9k_hw_use_flash(ah)) {
70 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, 70 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
71 &magic)) { 71 &magic)) {
72 ath_print(common, ATH_DBG_FATAL, 72 ath_err(common, "Reading Magic # failed\n");
73 "Reading Magic # failed\n");
74 return false; 73 return false;
75 } 74 }
76 75
77 ath_print(common, ATH_DBG_EEPROM, 76 ath_dbg(common, ATH_DBG_EEPROM,
78 "Read Magic = 0x%04X\n", magic); 77 "Read Magic = 0x%04X\n", magic);
79 78
80 if (magic != AR5416_EEPROM_MAGIC) { 79 if (magic != AR5416_EEPROM_MAGIC) {
81 magic2 = swab16(magic); 80 magic2 = swab16(magic);
@@ -90,16 +89,15 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
90 eepdata++; 89 eepdata++;
91 } 90 }
92 } else { 91 } else {
93 ath_print(common, ATH_DBG_FATAL, 92 ath_err(common,
94 "Invalid EEPROM Magic. " 93 "Invalid EEPROM Magic. Endianness mismatch.\n");
95 "endianness mismatch.\n");
96 return -EINVAL; 94 return -EINVAL;
97 } 95 }
98 } 96 }
99 } 97 }
100 98
101 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", 99 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
102 need_swap ? "True" : "False"); 100 need_swap ? "True" : "False");
103 101
104 if (need_swap) 102 if (need_swap)
105 el = swab16(ah->eeprom.map4k.baseEepHeader.length); 103 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
@@ -120,8 +118,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
120 u32 integer; 118 u32 integer;
121 u16 word; 119 u16 word;
122 120
123 ath_print(common, ATH_DBG_EEPROM, 121 ath_dbg(common, ATH_DBG_EEPROM,
124 "EEPROM Endianness is not native.. Changing\n"); 122 "EEPROM Endianness is not native.. Changing\n");
125 123
126 word = swab16(eep->baseEepHeader.length); 124 word = swab16(eep->baseEepHeader.length);
127 eep->baseEepHeader.length = word; 125 eep->baseEepHeader.length = word;
@@ -163,9 +161,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
163 161
164 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 162 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
165 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 163 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
166 ath_print(common, ATH_DBG_FATAL, 164 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
167 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 165 sum, ah->eep_ops->get_eeprom_ver(ah));
168 sum, ah->eep_ops->get_eeprom_ver(ah));
169 return -EINVAL; 166 return -EINVAL;
170 } 167 }
171 168
@@ -488,21 +485,20 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
488 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 485 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
489 REG_WRITE(ah, regOffset, reg32); 486 REG_WRITE(ah, regOffset, reg32);
490 487
491 ath_print(common, ATH_DBG_EEPROM, 488 ath_dbg(common, ATH_DBG_EEPROM,
492 "PDADC (%d,%4x): %4.4x %8.8x\n", 489 "PDADC (%d,%4x): %4.4x %8.8x\n",
493 i, regChainOffset, regOffset, 490 i, regChainOffset, regOffset,
494 reg32); 491 reg32);
495 ath_print(common, ATH_DBG_EEPROM, 492 ath_dbg(common, ATH_DBG_EEPROM,
496 "PDADC: Chain %d | " 493 "PDADC: Chain %d | "
497 "PDADC %3d Value %3d | " 494 "PDADC %3d Value %3d | "
498 "PDADC %3d Value %3d | " 495 "PDADC %3d Value %3d | "
499 "PDADC %3d Value %3d | " 496 "PDADC %3d Value %3d | "
500 "PDADC %3d Value %3d |\n", 497 "PDADC %3d Value %3d |\n",
501 i, 4 * j, pdadcValues[4 * j], 498 i, 4 * j, pdadcValues[4 * j],
502 4 * j + 1, pdadcValues[4 * j + 1], 499 4 * j + 1, pdadcValues[4 * j + 1],
503 4 * j + 2, pdadcValues[4 * j + 2], 500 4 * j + 2, pdadcValues[4 * j + 2],
504 4 * j + 3, 501 4 * j + 3, pdadcValues[4 * j + 3]);
505 pdadcValues[4 * j + 3]);
506 502
507 regOffset += 4; 503 regOffset += 4;
508 } 504 }
@@ -1181,17 +1177,17 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1181 1177
1182 u16 spur_val = AR_NO_SPUR; 1178 u16 spur_val = AR_NO_SPUR;
1183 1179
1184 ath_print(common, ATH_DBG_ANI, 1180 ath_dbg(common, ATH_DBG_ANI,
1185 "Getting spur idx %d is2Ghz. %d val %x\n", 1181 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1186 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1182 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1187 1183
1188 switch (ah->config.spurmode) { 1184 switch (ah->config.spurmode) {
1189 case SPUR_DISABLE: 1185 case SPUR_DISABLE:
1190 break; 1186 break;
1191 case SPUR_ENABLE_IOCTL: 1187 case SPUR_ENABLE_IOCTL:
1192 spur_val = ah->config.spurchans[i][is2GHz]; 1188 spur_val = ah->config.spurchans[i][is2GHz];
1193 ath_print(common, ATH_DBG_ANI, 1189 ath_dbg(common, ATH_DBG_ANI,
1194 "Getting spur val from new loc. %d\n", spur_val); 1190 "Getting spur val from new loc. %d\n", spur_val);
1195 break; 1191 break;
1196 case SPUR_ENABLE_EEPROM: 1192 case SPUR_ENABLE_EEPROM:
1197 spur_val = EEP_MAP4K_SPURCHAN; 1193 spur_val = EEP_MAP4K_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index bcb9ed39c047..065402f2e402 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -37,21 +37,21 @@ static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
37 int addr, eep_start_loc; 37 int addr, eep_start_loc;
38 eep_data = (u16 *)eep; 38 eep_data = (u16 *)eep;
39 39
40 if (!common->driver_info) 40 if (common->bus_ops->ath_bus_type == ATH_USB)
41 eep_start_loc = AR9287_EEP_START_LOC;
42 else
43 eep_start_loc = AR9287_HTC_EEP_START_LOC; 41 eep_start_loc = AR9287_HTC_EEP_START_LOC;
42 else
43 eep_start_loc = AR9287_EEP_START_LOC;
44 44
45 if (!ath9k_hw_use_flash(ah)) { 45 if (!ath9k_hw_use_flash(ah)) {
46 ath_print(common, ATH_DBG_EEPROM, 46 ath_dbg(common, ATH_DBG_EEPROM,
47 "Reading from EEPROM, not flash\n"); 47 "Reading from EEPROM, not flash\n");
48 } 48 }
49 49
50 for (addr = 0; addr < NUM_EEP_WORDS; addr++) { 50 for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
51 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, 51 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
52 eep_data)) { 52 eep_data)) {
53 ath_print(common, ATH_DBG_EEPROM, 53 ath_dbg(common, ATH_DBG_EEPROM,
54 "Unable to read eeprom region\n"); 54 "Unable to read eeprom region\n");
55 return false; 55 return false;
56 } 56 }
57 eep_data++; 57 eep_data++;
@@ -72,13 +72,12 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
72 if (!ath9k_hw_use_flash(ah)) { 72 if (!ath9k_hw_use_flash(ah)) {
73 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, 73 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
74 &magic)) { 74 &magic)) {
75 ath_print(common, ATH_DBG_FATAL, 75 ath_err(common, "Reading Magic # failed\n");
76 "Reading Magic # failed\n");
77 return false; 76 return false;
78 } 77 }
79 78
80 ath_print(common, ATH_DBG_EEPROM, 79 ath_dbg(common, ATH_DBG_EEPROM,
81 "Read Magic = 0x%04X\n", magic); 80 "Read Magic = 0x%04X\n", magic);
82 81
83 if (magic != AR5416_EEPROM_MAGIC) { 82 if (magic != AR5416_EEPROM_MAGIC) {
84 magic2 = swab16(magic); 83 magic2 = swab16(magic);
@@ -93,16 +92,15 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
93 eepdata++; 92 eepdata++;
94 } 93 }
95 } else { 94 } else {
96 ath_print(common, ATH_DBG_FATAL, 95 ath_err(common,
97 "Invalid EEPROM Magic. " 96 "Invalid EEPROM Magic. Endianness mismatch.\n");
98 "Endianness mismatch.\n");
99 return -EINVAL; 97 return -EINVAL;
100 } 98 }
101 } 99 }
102 } 100 }
103 101
104 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", 102 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
105 need_swap ? "True" : "False"); 103 need_swap ? "True" : "False");
106 104
107 if (need_swap) 105 if (need_swap)
108 el = swab16(ah->eeprom.map9287.baseEepHeader.length); 106 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
@@ -160,9 +158,8 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
160 158
161 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER 159 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
162 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 160 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
163 ath_print(common, ATH_DBG_FATAL, 161 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
164 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 162 sum, ah->eep_ops->get_eeprom_ver(ah));
165 sum, ah->eep_ops->get_eeprom_ver(ah));
166 return -EINVAL; 163 return -EINVAL;
167 } 164 }
168 165
@@ -1152,17 +1149,17 @@ static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
1152 struct ath_common *common = ath9k_hw_common(ah); 1149 struct ath_common *common = ath9k_hw_common(ah);
1153 u16 spur_val = AR_NO_SPUR; 1150 u16 spur_val = AR_NO_SPUR;
1154 1151
1155 ath_print(common, ATH_DBG_ANI, 1152 ath_dbg(common, ATH_DBG_ANI,
1156 "Getting spur idx %d is2Ghz. %d val %x\n", 1153 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1157 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1154 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1158 1155
1159 switch (ah->config.spurmode) { 1156 switch (ah->config.spurmode) {
1160 case SPUR_DISABLE: 1157 case SPUR_DISABLE:
1161 break; 1158 break;
1162 case SPUR_ENABLE_IOCTL: 1159 case SPUR_ENABLE_IOCTL:
1163 spur_val = ah->config.spurchans[i][is2GHz]; 1160 spur_val = ah->config.spurchans[i][is2GHz];
1164 ath_print(common, ATH_DBG_ANI, 1161 ath_dbg(common, ATH_DBG_ANI,
1165 "Getting spur val from new loc. %d\n", spur_val); 1162 "Getting spur val from new loc. %d\n", spur_val);
1166 break; 1163 break;
1167 case SPUR_ENABLE_EEPROM: 1164 case SPUR_ENABLE_EEPROM:
1168 spur_val = EEP_MAP9287_SPURCHAN; 1165 spur_val = EEP_MAP9287_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index 45f70b2404a1..5bfa031545f4 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -96,8 +96,8 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
96 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { 96 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
97 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc, 97 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
98 eep_data)) { 98 eep_data)) {
99 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 99 ath_err(ath9k_hw_common(ah),
100 "Unable to read eeprom region\n"); 100 "Unable to read eeprom region\n");
101 return false; 101 return false;
102 } 102 }
103 eep_data++; 103 eep_data++;
@@ -117,13 +117,13 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
117 int i, addr, size; 117 int i, addr, size;
118 118
119 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 119 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
120 ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n"); 120 ath_err(common, "Reading Magic # failed\n");
121 return false; 121 return false;
122 } 122 }
123 123
124 if (!ath9k_hw_use_flash(ah)) { 124 if (!ath9k_hw_use_flash(ah)) {
125 ath_print(common, ATH_DBG_EEPROM, 125 ath_dbg(common, ATH_DBG_EEPROM,
126 "Read Magic = 0x%04X\n", magic); 126 "Read Magic = 0x%04X\n", magic);
127 127
128 if (magic != AR5416_EEPROM_MAGIC) { 128 if (magic != AR5416_EEPROM_MAGIC) {
129 magic2 = swab16(magic); 129 magic2 = swab16(magic);
@@ -139,16 +139,15 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
139 eepdata++; 139 eepdata++;
140 } 140 }
141 } else { 141 } else {
142 ath_print(common, ATH_DBG_FATAL, 142 ath_err(common,
143 "Invalid EEPROM Magic. " 143 "Invalid EEPROM Magic. Endianness mismatch.\n");
144 "Endianness mismatch.\n");
145 return -EINVAL; 144 return -EINVAL;
146 } 145 }
147 } 146 }
148 } 147 }
149 148
150 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", 149 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
151 need_swap ? "True" : "False"); 150 need_swap ? "True" : "False");
152 151
153 if (need_swap) 152 if (need_swap)
154 el = swab16(ah->eeprom.def.baseEepHeader.length); 153 el = swab16(ah->eeprom.def.baseEepHeader.length);
@@ -169,8 +168,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
169 u32 integer, j; 168 u32 integer, j;
170 u16 word; 169 u16 word;
171 170
172 ath_print(common, ATH_DBG_EEPROM, 171 ath_dbg(common, ATH_DBG_EEPROM,
173 "EEPROM Endianness is not native.. Changing.\n"); 172 "EEPROM Endianness is not native.. Changing.\n");
174 173
175 word = swab16(eep->baseEepHeader.length); 174 word = swab16(eep->baseEepHeader.length);
176 eep->baseEepHeader.length = word; 175 eep->baseEepHeader.length = word;
@@ -216,8 +215,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
216 215
217 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 216 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
218 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 217 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
219 ath_print(common, ATH_DBG_FATAL, 218 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
220 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
221 sum, ah->eep_ops->get_eeprom_ver(ah)); 219 sum, ah->eep_ops->get_eeprom_ver(ah));
222 return -EINVAL; 220 return -EINVAL;
223 } 221 }
@@ -966,20 +964,19 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
966 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 964 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
967 REG_WRITE(ah, regOffset, reg32); 965 REG_WRITE(ah, regOffset, reg32);
968 966
969 ath_print(common, ATH_DBG_EEPROM, 967 ath_dbg(common, ATH_DBG_EEPROM,
970 "PDADC (%d,%4x): %4.4x %8.8x\n", 968 "PDADC (%d,%4x): %4.4x %8.8x\n",
971 i, regChainOffset, regOffset, 969 i, regChainOffset, regOffset,
972 reg32); 970 reg32);
973 ath_print(common, ATH_DBG_EEPROM, 971 ath_dbg(common, ATH_DBG_EEPROM,
974 "PDADC: Chain %d | PDADC %3d " 972 "PDADC: Chain %d | PDADC %3d "
975 "Value %3d | PDADC %3d Value %3d | " 973 "Value %3d | PDADC %3d Value %3d | "
976 "PDADC %3d Value %3d | PDADC %3d " 974 "PDADC %3d Value %3d | PDADC %3d "
977 "Value %3d |\n", 975 "Value %3d |\n",
978 i, 4 * j, pdadcValues[4 * j], 976 i, 4 * j, pdadcValues[4 * j],
979 4 * j + 1, pdadcValues[4 * j + 1], 977 4 * j + 1, pdadcValues[4 * j + 1],
980 4 * j + 2, pdadcValues[4 * j + 2], 978 4 * j + 2, pdadcValues[4 * j + 2],
981 4 * j + 3, 979 4 * j + 3, pdadcValues[4 * j + 3]);
982 pdadcValues[4 * j + 3]);
983 980
984 regOffset += 4; 981 regOffset += 4;
985 } 982 }
@@ -1066,15 +1063,19 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
1066 case 1: 1063 case 1:
1067 break; 1064 break;
1068 case 2: 1065 case 2:
1069 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; 1066 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
1067 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
1068 else
1069 scaledPower = 0;
1070 break; 1070 break;
1071 case 3: 1071 case 3:
1072 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; 1072 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
1073 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
1074 else
1075 scaledPower = 0;
1073 break; 1076 break;
1074 } 1077 }
1075 1078
1076 scaledPower = max((u16)0, scaledPower);
1077
1078 if (IS_CHAN_2GHZ(chan)) { 1079 if (IS_CHAN_2GHZ(chan)) {
1079 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - 1080 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1080 SUB_NUM_CTL_MODES_AT_2G_40; 1081 SUB_NUM_CTL_MODES_AT_2G_40;
@@ -1319,8 +1320,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1319 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; 1320 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1320 break; 1321 break;
1321 default: 1322 default:
1322 ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM, 1323 ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1323 "Invalid chainmask configuration\n"); 1324 "Invalid chainmask configuration\n");
1324 break; 1325 break;
1325 } 1326 }
1326 1327
@@ -1461,17 +1462,17 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1461 1462
1462 u16 spur_val = AR_NO_SPUR; 1463 u16 spur_val = AR_NO_SPUR;
1463 1464
1464 ath_print(common, ATH_DBG_ANI, 1465 ath_dbg(common, ATH_DBG_ANI,
1465 "Getting spur idx %d is2Ghz. %d val %x\n", 1466 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1466 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1467 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1467 1468
1468 switch (ah->config.spurmode) { 1469 switch (ah->config.spurmode) {
1469 case SPUR_DISABLE: 1470 case SPUR_DISABLE:
1470 break; 1471 break;
1471 case SPUR_ENABLE_IOCTL: 1472 case SPUR_ENABLE_IOCTL:
1472 spur_val = ah->config.spurchans[i][is2GHz]; 1473 spur_val = ah->config.spurchans[i][is2GHz];
1473 ath_print(common, ATH_DBG_ANI, 1474 ath_dbg(common, ATH_DBG_ANI,
1474 "Getting spur val from new loc. %d\n", spur_val); 1475 "Getting spur val from new loc. %d\n", spur_val);
1475 break; 1476 break;
1476 case SPUR_ENABLE_EEPROM: 1477 case SPUR_ENABLE_EEPROM:
1477 spur_val = EEP_DEF_SPURCHAN; 1478 spur_val = EEP_DEF_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c
index 6a1a482f9dc3..133764069246 100644
--- a/drivers/net/wireless/ath/ath9k/gpio.c
+++ b/drivers/net/wireless/ath/ath9k/gpio.c
@@ -103,8 +103,8 @@ static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
103 103
104 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev); 104 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
105 if (ret) 105 if (ret)
106 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, 106 ath_err(ath9k_hw_common(sc->sc_ah),
107 "Failed to register led:%s", led->name); 107 "Failed to register led:%s", led->name);
108 else 108 else
109 led->registered = 1; 109 led->registered = 1;
110 return ret; 110 return ret;
@@ -236,13 +236,13 @@ static void ath_detect_bt_priority(struct ath_softc *sc)
236 sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN); 236 sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN);
237 /* Detect if colocated bt started scanning */ 237 /* Detect if colocated bt started scanning */
238 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { 238 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
239 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX, 239 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
240 "BT scan detected"); 240 "BT scan detected\n");
241 sc->sc_flags |= (SC_OP_BT_SCAN | 241 sc->sc_flags |= (SC_OP_BT_SCAN |
242 SC_OP_BT_PRIORITY_DETECTED); 242 SC_OP_BT_PRIORITY_DETECTED);
243 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { 243 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
244 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX, 244 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
245 "BT priority traffic detected"); 245 "BT priority traffic detected\n");
246 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED; 246 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
247 } 247 }
248 248
@@ -331,8 +331,8 @@ static void ath_btcoex_no_stomp_timer(void *arg)
331 struct ath_common *common = ath9k_hw_common(ah); 331 struct ath_common *common = ath9k_hw_common(ah);
332 bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN; 332 bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN;
333 333
334 ath_print(common, ATH_DBG_BTCOEX, 334 ath_dbg(common, ATH_DBG_BTCOEX,
335 "no stomp timer running\n"); 335 "no stomp timer running\n");
336 336
337 spin_lock_bh(&btcoex->btcoex_lock); 337 spin_lock_bh(&btcoex->btcoex_lock);
338 338
@@ -378,8 +378,8 @@ void ath9k_btcoex_timer_resume(struct ath_softc *sc)
378 struct ath_btcoex *btcoex = &sc->btcoex; 378 struct ath_btcoex *btcoex = &sc->btcoex;
379 struct ath_hw *ah = sc->sc_ah; 379 struct ath_hw *ah = sc->sc_ah;
380 380
381 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX, 381 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
382 "Starting btcoex timers"); 382 "Starting btcoex timers\n");
383 383
384 /* make sure duty cycle timer is also stopped when resuming */ 384 /* make sure duty cycle timer is also stopped when resuming */
385 if (btcoex->hw_timer_enabled) 385 if (btcoex->hw_timer_enabled)
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
index 8946e8ad1b85..d0918bd23b8e 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -28,16 +28,7 @@ MODULE_FIRMWARE(FIRMWARE_AR9271);
28static struct usb_device_id ath9k_hif_usb_ids[] = { 28static struct usb_device_id ath9k_hif_usb_ids[] = {
29 { USB_DEVICE(0x0cf3, 0x9271) }, /* Atheros */ 29 { USB_DEVICE(0x0cf3, 0x9271) }, /* Atheros */
30 { USB_DEVICE(0x0cf3, 0x1006) }, /* Atheros */ 30 { USB_DEVICE(0x0cf3, 0x1006) }, /* Atheros */
31 { USB_DEVICE(0x0cf3, 0x7010),
32 .driver_info = AR7010_DEVICE },
33 /* Atheros */
34 { USB_DEVICE(0x0cf3, 0x7015),
35 .driver_info = AR7010_DEVICE | AR9287_DEVICE },
36 /* Atheros */
37 { USB_DEVICE(0x0846, 0x9030) }, /* Netgear N150 */ 31 { USB_DEVICE(0x0846, 0x9030) }, /* Netgear N150 */
38 { USB_DEVICE(0x0846, 0x9018),
39 .driver_info = AR7010_DEVICE },
40 /* Netgear WNDA3200 */
41 { USB_DEVICE(0x07D1, 0x3A10) }, /* Dlink Wireless 150 */ 32 { USB_DEVICE(0x07D1, 0x3A10) }, /* Dlink Wireless 150 */
42 { USB_DEVICE(0x13D3, 0x3327) }, /* Azurewave */ 33 { USB_DEVICE(0x13D3, 0x3327) }, /* Azurewave */
43 { USB_DEVICE(0x13D3, 0x3328) }, /* Azurewave */ 34 { USB_DEVICE(0x13D3, 0x3328) }, /* Azurewave */
@@ -46,13 +37,20 @@ static struct usb_device_id ath9k_hif_usb_ids[] = {
46 { USB_DEVICE(0x13D3, 0x3349) }, /* Azurewave */ 37 { USB_DEVICE(0x13D3, 0x3349) }, /* Azurewave */
47 { USB_DEVICE(0x13D3, 0x3350) }, /* Azurewave */ 38 { USB_DEVICE(0x13D3, 0x3350) }, /* Azurewave */
48 { USB_DEVICE(0x04CA, 0x4605) }, /* Liteon */ 39 { USB_DEVICE(0x04CA, 0x4605) }, /* Liteon */
49 { USB_DEVICE(0x083A, 0xA704),
50 .driver_info = AR7010_DEVICE },
51 /* SMC Networks */
52 { USB_DEVICE(0x040D, 0x3801) }, /* VIA */ 40 { USB_DEVICE(0x040D, 0x3801) }, /* VIA */
41
42 { USB_DEVICE(0x0cf3, 0x7015),
43 .driver_info = AR9287_USB }, /* Atheros */
53 { USB_DEVICE(0x1668, 0x1200), 44 { USB_DEVICE(0x1668, 0x1200),
54 .driver_info = AR7010_DEVICE | AR9287_DEVICE }, 45 .driver_info = AR9287_USB }, /* Verizon */
55 /* Verizon */ 46
47 { USB_DEVICE(0x0cf3, 0x7010),
48 .driver_info = AR9280_USB }, /* Atheros */
49 { USB_DEVICE(0x0846, 0x9018),
50 .driver_info = AR9280_USB }, /* Netgear WNDA3200 */
51 { USB_DEVICE(0x083A, 0xA704),
52 .driver_info = AR9280_USB }, /* SMC Networks */
53
56 { }, 54 { },
57}; 55};
58 56
@@ -818,7 +816,7 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev,
818 } 816 }
819 kfree(buf); 817 kfree(buf);
820 818
821 if (drv_info & AR7010_DEVICE) 819 if (IS_AR7010_DEVICE(drv_info))
822 firm_offset = AR7010_FIRMWARE_TEXT; 820 firm_offset = AR7010_FIRMWARE_TEXT;
823 else 821 else
824 firm_offset = AR9271_FIRMWARE_TEXT; 822 firm_offset = AR9271_FIRMWARE_TEXT;
@@ -887,9 +885,9 @@ static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev, u32 drv_info)
887 885
888 return 0; 886 return 0;
889 887
890err_fw_download:
891 ath9k_hif_usb_dealloc_urbs(hif_dev);
892err_urb: 888err_urb:
889 ath9k_hif_usb_dealloc_urbs(hif_dev);
890err_fw_download:
893 release_firmware(hif_dev->firmware); 891 release_firmware(hif_dev->firmware);
894err_fw_req: 892err_fw_req:
895 hif_dev->firmware = NULL; 893 hif_dev->firmware = NULL;
@@ -934,7 +932,7 @@ static int ath9k_hif_usb_probe(struct usb_interface *interface,
934 932
935 /* Find out which firmware to load */ 933 /* Find out which firmware to load */
936 934
937 if (id->driver_info & AR7010_DEVICE) 935 if (IS_AR7010_DEVICE(id->driver_info))
938 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x0202) 936 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x0202)
939 hif_dev->fw_name = FIRMWARE_AR7010_1_1; 937 hif_dev->fw_name = FIRMWARE_AR7010_1_1;
940 else 938 else
@@ -1017,6 +1015,13 @@ static int ath9k_hif_usb_suspend(struct usb_interface *interface,
1017{ 1015{
1018 struct hif_device_usb *hif_dev = usb_get_intfdata(interface); 1016 struct hif_device_usb *hif_dev = usb_get_intfdata(interface);
1019 1017
1018 /*
1019 * The device has to be set to FULLSLEEP mode in case no
1020 * interface is up.
1021 */
1022 if (!(hif_dev->flags & HIF_USB_START))
1023 ath9k_htc_suspend(hif_dev->htc_handle);
1024
1020 ath9k_hif_usb_dealloc_urbs(hif_dev); 1025 ath9k_hif_usb_dealloc_urbs(hif_dev);
1021 1026
1022 return 0; 1027 return 0;
@@ -1034,7 +1039,7 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
1034 1039
1035 if (hif_dev->firmware) { 1040 if (hif_dev->firmware) {
1036 ret = ath9k_hif_usb_download_fw(hif_dev, 1041 ret = ath9k_hif_usb_download_fw(hif_dev,
1037 htc_handle->drv_priv->ah->common.driver_info); 1042 htc_handle->drv_priv->ah->hw_version.usbdev);
1038 if (ret) 1043 if (ret)
1039 goto fail_resume; 1044 goto fail_resume;
1040 } else { 1045 } else {
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.h b/drivers/net/wireless/ath/ath9k/hif_usb.h
index 2daf97b11c08..e4a5e2e79541 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.h
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.h
@@ -17,6 +17,8 @@
17#ifndef HTC_USB_H 17#ifndef HTC_USB_H
18#define HTC_USB_H 18#define HTC_USB_H
19 19
20#define IS_AR7010_DEVICE(_v) (((_v) == AR9280_USB) || ((_v) == AR9287_USB))
21
20#define AR9271_FIRMWARE 0x501000 22#define AR9271_FIRMWARE 0x501000
21#define AR9271_FIRMWARE_TEXT 0x903000 23#define AR9271_FIRMWARE_TEXT 0x903000
22#define AR7010_FIRMWARE_TEXT 0x906000 24#define AR7010_FIRMWARE_TEXT 0x906000
diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
index afe39a911906..fdf9d5fe8cc0 100644
--- a/drivers/net/wireless/ath/ath9k/htc.h
+++ b/drivers/net/wireless/ath/ath9k/htc.h
@@ -455,6 +455,8 @@ u32 ath9k_htc_calcrxfilter(struct ath9k_htc_priv *priv);
455void ath9k_htc_ps_wakeup(struct ath9k_htc_priv *priv); 455void ath9k_htc_ps_wakeup(struct ath9k_htc_priv *priv);
456void ath9k_htc_ps_restore(struct ath9k_htc_priv *priv); 456void ath9k_htc_ps_restore(struct ath9k_htc_priv *priv);
457void ath9k_ps_work(struct work_struct *work); 457void ath9k_ps_work(struct work_struct *work);
458bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
459 enum ath9k_power_mode mode);
458 460
459void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv); 461void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv);
460void ath9k_init_leds(struct ath9k_htc_priv *priv); 462void ath9k_init_leds(struct ath9k_htc_priv *priv);
@@ -464,6 +466,7 @@ int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
464 u16 devid, char *product, u32 drv_info); 466 u16 devid, char *product, u32 drv_info);
465void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug); 467void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug);
466#ifdef CONFIG_PM 468#ifdef CONFIG_PM
469void ath9k_htc_suspend(struct htc_target *htc_handle);
467int ath9k_htc_resume(struct htc_target *htc_handle); 470int ath9k_htc_resume(struct htc_target *htc_handle);
468#endif 471#endif
469#ifdef CONFIG_ATH9K_HTC_DEBUGFS 472#ifdef CONFIG_ATH9K_HTC_DEBUGFS
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
index 1b72aa482ac7..87cc65a78a3f 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
@@ -123,11 +123,11 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
123 /* TSF out of range threshold fixed at 1 second */ 123 /* TSF out of range threshold fixed at 1 second */
124 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; 124 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
125 125
126 ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); 126 ath_dbg(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
127 ath_print(common, ATH_DBG_BEACON, 127 ath_dbg(common, ATH_DBG_BEACON,
128 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", 128 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
129 bs.bs_bmissthreshold, bs.bs_sleepduration, 129 bs.bs_bmissthreshold, bs.bs_sleepduration,
130 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); 130 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
131 131
132 /* Set the computed STA beacon timers */ 132 /* Set the computed STA beacon timers */
133 133
@@ -154,9 +154,9 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
154 if (priv->op_flags & OP_ENABLE_BEACON) 154 if (priv->op_flags & OP_ENABLE_BEACON)
155 imask |= ATH9K_INT_SWBA; 155 imask |= ATH9K_INT_SWBA;
156 156
157 ath_print(common, ATH_DBG_BEACON, 157 ath_dbg(common, ATH_DBG_BEACON,
158 "IBSS Beacon config, intval: %d, imask: 0x%x\n", 158 "IBSS Beacon config, intval: %d, imask: 0x%x\n",
159 bss_conf->beacon_interval, imask); 159 bss_conf->beacon_interval, imask);
160 160
161 WMI_CMD(WMI_DISABLE_INTR_CMDID); 161 WMI_CMD(WMI_DISABLE_INTR_CMDID);
162 ath9k_hw_beaconinit(priv->ah, nexttbtt, intval); 162 ath9k_hw_beaconinit(priv->ah, nexttbtt, intval);
@@ -246,8 +246,8 @@ void ath9k_htc_beaconq_config(struct ath9k_htc_priv *priv)
246 qi.tqi_cwmax = qi_be.tqi_cwmax; 246 qi.tqi_cwmax = qi_be.tqi_cwmax;
247 247
248 if (!ath9k_hw_set_txq_props(ah, priv->beaconq, &qi)) { 248 if (!ath9k_hw_set_txq_props(ah, priv->beaconq, &qi)) {
249 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 249 ath_err(ath9k_hw_common(ah),
250 "Unable to update beacon queue %u!\n", qnum); 250 "Unable to update beacon queue %u!\n", qnum);
251 } else { 251 } else {
252 ath9k_hw_resettxqueue(ah, priv->beaconq); 252 ath9k_hw_resettxqueue(ah, priv->beaconq);
253 } 253 }
@@ -278,8 +278,8 @@ void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv,
278 ath9k_htc_beacon_config_adhoc(priv, cur_conf); 278 ath9k_htc_beacon_config_adhoc(priv, cur_conf);
279 break; 279 break;
280 default: 280 default:
281 ath_print(common, ATH_DBG_CONFIG, 281 ath_dbg(common, ATH_DBG_CONFIG,
282 "Unsupported beaconing mode\n"); 282 "Unsupported beaconing mode\n");
283 return; 283 return;
284 } 284 }
285} 285}
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
index 50eec9a3b88c..283ff97ed446 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
@@ -20,13 +20,13 @@ static void ath_detect_bt_priority(struct ath9k_htc_priv *priv)
20 priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN); 20 priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN);
21 /* Detect if colocated bt started scanning */ 21 /* Detect if colocated bt started scanning */
22 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { 22 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
23 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX, 23 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
24 "BT scan detected"); 24 "BT scan detected\n");
25 priv->op_flags |= (OP_BT_SCAN | 25 priv->op_flags |= (OP_BT_SCAN |
26 OP_BT_PRIORITY_DETECTED); 26 OP_BT_PRIORITY_DETECTED);
27 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { 27 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
28 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX, 28 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
29 "BT priority traffic detected"); 29 "BT priority traffic detected\n");
30 priv->op_flags |= OP_BT_PRIORITY_DETECTED; 30 priv->op_flags |= OP_BT_PRIORITY_DETECTED;
31 } 31 }
32 32
@@ -83,8 +83,8 @@ static void ath_btcoex_duty_cycle_work(struct work_struct *work)
83 struct ath_common *common = ath9k_hw_common(ah); 83 struct ath_common *common = ath9k_hw_common(ah);
84 bool is_btscan = priv->op_flags & OP_BT_SCAN; 84 bool is_btscan = priv->op_flags & OP_BT_SCAN;
85 85
86 ath_print(common, ATH_DBG_BTCOEX, 86 ath_dbg(common, ATH_DBG_BTCOEX,
87 "time slice work for bt and wlan\n"); 87 "time slice work for bt and wlan\n");
88 88
89 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan) 89 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan)
90 ath9k_cmn_btcoex_bt_stomp(common, ATH_BTCOEX_STOMP_NONE); 90 ath9k_cmn_btcoex_bt_stomp(common, ATH_BTCOEX_STOMP_NONE);
@@ -114,8 +114,7 @@ void ath_htc_resume_btcoex_work(struct ath9k_htc_priv *priv)
114 struct ath_btcoex *btcoex = &priv->btcoex; 114 struct ath_btcoex *btcoex = &priv->btcoex;
115 struct ath_hw *ah = priv->ah; 115 struct ath_hw *ah = priv->ah;
116 116
117 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX, 117 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, "Starting btcoex work\n");
118 "Starting btcoex work");
119 118
120 btcoex->bt_priority_cnt = 0; 119 btcoex->bt_priority_cnt = 0;
121 btcoex->bt_priority_time = jiffies; 120 btcoex->bt_priority_time = jiffies;
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index 071d0c974747..0f6be350fd3c 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -246,7 +246,7 @@ static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
246 * the HIF layer, shouldn't matter much. 246 * the HIF layer, shouldn't matter much.
247 */ 247 */
248 248
249 if (drv_info & AR7010_DEVICE) 249 if (IS_AR7010_DEVICE(drv_info))
250 priv->htc->credits = 45; 250 priv->htc->credits = 45;
251 else 251 else
252 priv->htc->credits = 33; 252 priv->htc->credits = 33;
@@ -288,9 +288,9 @@ static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
288 (u8 *) &val, sizeof(val), 288 (u8 *) &val, sizeof(val),
289 100); 289 100);
290 if (unlikely(r)) { 290 if (unlikely(r)) {
291 ath_print(common, ATH_DBG_WMI, 291 ath_dbg(common, ATH_DBG_WMI,
292 "REGISTER READ FAILED: (0x%04x, %d)\n", 292 "REGISTER READ FAILED: (0x%04x, %d)\n",
293 reg_offset, r); 293 reg_offset, r);
294 return -EIO; 294 return -EIO;
295 } 295 }
296 296
@@ -313,9 +313,9 @@ static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
313 (u8 *) &val, sizeof(val), 313 (u8 *) &val, sizeof(val),
314 100); 314 100);
315 if (unlikely(r)) { 315 if (unlikely(r)) {
316 ath_print(common, ATH_DBG_WMI, 316 ath_dbg(common, ATH_DBG_WMI,
317 "REGISTER WRITE FAILED:(0x%04x, %d)\n", 317 "REGISTER WRITE FAILED:(0x%04x, %d)\n",
318 reg_offset, r); 318 reg_offset, r);
319 } 319 }
320} 320}
321 321
@@ -345,9 +345,9 @@ static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
345 (u8 *) &rsp_status, sizeof(rsp_status), 345 (u8 *) &rsp_status, sizeof(rsp_status),
346 100); 346 100);
347 if (unlikely(r)) { 347 if (unlikely(r)) {
348 ath_print(common, ATH_DBG_WMI, 348 ath_dbg(common, ATH_DBG_WMI,
349 "REGISTER WRITE FAILED, multi len: %d\n", 349 "REGISTER WRITE FAILED, multi len: %d\n",
350 priv->wmi->multi_write_idx); 350 priv->wmi->multi_write_idx);
351 } 351 }
352 priv->wmi->multi_write_idx = 0; 352 priv->wmi->multi_write_idx = 0;
353 } 353 }
@@ -395,9 +395,9 @@ static void ath9k_regwrite_flush(void *hw_priv)
395 (u8 *) &rsp_status, sizeof(rsp_status), 395 (u8 *) &rsp_status, sizeof(rsp_status),
396 100); 396 100);
397 if (unlikely(r)) { 397 if (unlikely(r)) {
398 ath_print(common, ATH_DBG_WMI, 398 ath_dbg(common, ATH_DBG_WMI,
399 "REGISTER WRITE FAILED, multi len: %d\n", 399 "REGISTER WRITE FAILED, multi len: %d\n",
400 priv->wmi->multi_write_idx); 400 priv->wmi->multi_write_idx);
401 } 401 }
402 priv->wmi->multi_write_idx = 0; 402 priv->wmi->multi_write_idx = 0;
403 } 403 }
@@ -469,9 +469,9 @@ static void setup_ht_cap(struct ath9k_htc_priv *priv,
469 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2); 469 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2);
470 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2); 470 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2);
471 471
472 ath_print(common, ATH_DBG_CONFIG, 472 ath_dbg(common, ATH_DBG_CONFIG,
473 "TX streams %d, RX streams: %d\n", 473 "TX streams %d, RX streams: %d\n",
474 tx_streams, rx_streams); 474 tx_streams, rx_streams);
475 475
476 if (tx_streams != rx_streams) { 476 if (tx_streams != rx_streams) {
477 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 477 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
@@ -495,37 +495,31 @@ static int ath9k_init_queues(struct ath9k_htc_priv *priv)
495 495
496 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah); 496 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
497 if (priv->beaconq == -1) { 497 if (priv->beaconq == -1) {
498 ath_print(common, ATH_DBG_FATAL, 498 ath_err(common, "Unable to setup BEACON xmit queue\n");
499 "Unable to setup BEACON xmit queue\n");
500 goto err; 499 goto err;
501 } 500 }
502 501
503 priv->cabq = ath9k_htc_cabq_setup(priv); 502 priv->cabq = ath9k_htc_cabq_setup(priv);
504 if (priv->cabq == -1) { 503 if (priv->cabq == -1) {
505 ath_print(common, ATH_DBG_FATAL, 504 ath_err(common, "Unable to setup CAB xmit queue\n");
506 "Unable to setup CAB xmit queue\n");
507 goto err; 505 goto err;
508 } 506 }
509 507
510 if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) { 508 if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
511 ath_print(common, ATH_DBG_FATAL, 509 ath_err(common, "Unable to setup xmit queue for BE traffic\n");
512 "Unable to setup xmit queue for BE traffic\n");
513 goto err; 510 goto err;
514 } 511 }
515 512
516 if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) { 513 if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
517 ath_print(common, ATH_DBG_FATAL, 514 ath_err(common, "Unable to setup xmit queue for BK traffic\n");
518 "Unable to setup xmit queue for BK traffic\n");
519 goto err; 515 goto err;
520 } 516 }
521 if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) { 517 if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
522 ath_print(common, ATH_DBG_FATAL, 518 ath_err(common, "Unable to setup xmit queue for VI traffic\n");
523 "Unable to setup xmit queue for VI traffic\n");
524 goto err; 519 goto err;
525 } 520 }
526 if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) { 521 if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
527 ath_print(common, ATH_DBG_FATAL, 522 ath_err(common, "Unable to setup xmit queue for VO traffic\n");
528 "Unable to setup xmit queue for VO traffic\n");
529 goto err; 523 goto err;
530 } 524 }
531 525
@@ -543,9 +537,9 @@ static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
543 /* Get the hardware key cache size. */ 537 /* Get the hardware key cache size. */
544 common->keymax = priv->ah->caps.keycache_size; 538 common->keymax = priv->ah->caps.keycache_size;
545 if (common->keymax > ATH_KEYMAX) { 539 if (common->keymax > ATH_KEYMAX) {
546 ath_print(common, ATH_DBG_ANY, 540 ath_dbg(common, ATH_DBG_ANY,
547 "Warning, using only %u entries in %u key cache\n", 541 "Warning, using only %u entries in %u key cache\n",
548 ATH_KEYMAX, common->keymax); 542 ATH_KEYMAX, common->keymax);
549 common->keymax = ATH_KEYMAX; 543 common->keymax = ATH_KEYMAX;
550 } 544 }
551 545
@@ -636,6 +630,7 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
636 630
637 ah->hw_version.devid = devid; 631 ah->hw_version.devid = devid;
638 ah->hw_version.subsysid = 0; /* FIXME */ 632 ah->hw_version.subsysid = 0; /* FIXME */
633 ah->hw_version.usbdev = drv_info;
639 ah->ah_flags |= AH_USE_EEPROM; 634 ah->ah_flags |= AH_USE_EEPROM;
640 priv->ah = ah; 635 priv->ah = ah;
641 636
@@ -646,7 +641,6 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
646 common->hw = priv->hw; 641 common->hw = priv->hw;
647 common->priv = priv; 642 common->priv = priv;
648 common->debug_mask = ath9k_debug; 643 common->debug_mask = ath9k_debug;
649 common->driver_info = drv_info;
650 644
651 spin_lock_init(&priv->wmi->wmi_lock); 645 spin_lock_init(&priv->wmi->wmi_lock);
652 spin_lock_init(&priv->beacon_lock); 646 spin_lock_init(&priv->beacon_lock);
@@ -670,16 +664,15 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
670 664
671 ret = ath9k_hw_init(ah); 665 ret = ath9k_hw_init(ah);
672 if (ret) { 666 if (ret) {
673 ath_print(common, ATH_DBG_FATAL, 667 ath_err(common,
674 "Unable to initialize hardware; " 668 "Unable to initialize hardware; initialization status: %d\n",
675 "initialization status: %d\n", ret); 669 ret);
676 goto err_hw; 670 goto err_hw;
677 } 671 }
678 672
679 ret = ath9k_htc_init_debug(ah); 673 ret = ath9k_htc_init_debug(ah);
680 if (ret) { 674 if (ret) {
681 ath_print(common, ATH_DBG_FATAL, 675 ath_err(common, "Unable to create debugfs files\n");
682 "Unable to create debugfs files\n");
683 goto err_debug; 676 goto err_debug;
684 } 677 }
685 678
@@ -721,7 +714,8 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
721 IEEE80211_HW_HAS_RATE_CONTROL | 714 IEEE80211_HW_HAS_RATE_CONTROL |
722 IEEE80211_HW_RX_INCLUDES_FCS | 715 IEEE80211_HW_RX_INCLUDES_FCS |
723 IEEE80211_HW_SUPPORTS_PS | 716 IEEE80211_HW_SUPPORTS_PS |
724 IEEE80211_HW_PS_NULLFUNC_STACK; 717 IEEE80211_HW_PS_NULLFUNC_STACK |
718 IEEE80211_HW_NEED_DTIM_PERIOD;
725 719
726 hw->wiphy->interface_modes = 720 hw->wiphy->interface_modes =
727 BIT(NL80211_IFTYPE_STATION) | 721 BIT(NL80211_IFTYPE_STATION) |
@@ -888,6 +882,12 @@ void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
888} 882}
889 883
890#ifdef CONFIG_PM 884#ifdef CONFIG_PM
885
886void ath9k_htc_suspend(struct htc_target *htc_handle)
887{
888 ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
889}
890
891int ath9k_htc_resume(struct htc_target *htc_handle) 891int ath9k_htc_resume(struct htc_target *htc_handle)
892{ 892{
893 struct ath9k_htc_priv *priv = htc_handle->drv_priv; 893 struct ath9k_htc_priv *priv = htc_handle->drv_priv;
@@ -898,7 +898,7 @@ int ath9k_htc_resume(struct htc_target *htc_handle)
898 return ret; 898 return ret;
899 899
900 ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid, 900 ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
901 priv->ah->common.driver_info); 901 priv->ah->hw_version.usbdev);
902 return ret; 902 return ret;
903} 903}
904#endif 904#endif
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index 8266ce1f02e3..20ea75a44e52 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -63,8 +63,8 @@ static enum htc_phymode ath9k_htc_get_curmode(struct ath9k_htc_priv *priv,
63 return mode; 63 return mode;
64} 64}
65 65
66static bool ath9k_htc_setpower(struct ath9k_htc_priv *priv, 66bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
67 enum ath9k_power_mode mode) 67 enum ath9k_power_mode mode)
68{ 68{
69 bool ret; 69 bool ret;
70 70
@@ -143,18 +143,18 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
143 WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID); 143 WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
144 WMI_CMD(WMI_STOP_RECV_CMDID); 144 WMI_CMD(WMI_STOP_RECV_CMDID);
145 145
146 ath_print(common, ATH_DBG_CONFIG, 146 ath_dbg(common, ATH_DBG_CONFIG,
147 "(%u MHz) -> (%u MHz), HT: %d, HT40: %d fastcc: %d\n", 147 "(%u MHz) -> (%u MHz), HT: %d, HT40: %d fastcc: %d\n",
148 priv->ah->curchan->channel, 148 priv->ah->curchan->channel,
149 channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf), 149 channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf),
150 fastcc); 150 fastcc);
151 151
152 caldata = &priv->caldata[channel->hw_value]; 152 caldata = &priv->caldata[channel->hw_value];
153 ret = ath9k_hw_reset(ah, hchan, caldata, fastcc); 153 ret = ath9k_hw_reset(ah, hchan, caldata, fastcc);
154 if (ret) { 154 if (ret) {
155 ath_print(common, ATH_DBG_FATAL, 155 ath_err(common,
156 "Unable to reset channel (%u Mhz) " 156 "Unable to reset channel (%u Mhz) reset status %d\n",
157 "reset status %d\n", channel->center_freq, ret); 157 channel->center_freq, ret);
158 goto err; 158 goto err;
159 } 159 }
160 160
@@ -263,15 +263,16 @@ static int ath9k_htc_add_station(struct ath9k_htc_priv *priv,
263 WMI_CMD_BUF(WMI_NODE_CREATE_CMDID, &tsta); 263 WMI_CMD_BUF(WMI_NODE_CREATE_CMDID, &tsta);
264 if (ret) { 264 if (ret) {
265 if (sta) 265 if (sta)
266 ath_print(common, ATH_DBG_FATAL, 266 ath_err(common,
267 "Unable to add station entry for: %pM\n", sta->addr); 267 "Unable to add station entry for: %pM\n",
268 sta->addr);
268 return ret; 269 return ret;
269 } 270 }
270 271
271 if (sta) 272 if (sta)
272 ath_print(common, ATH_DBG_CONFIG, 273 ath_dbg(common, ATH_DBG_CONFIG,
273 "Added a station entry for: %pM (idx: %d)\n", 274 "Added a station entry for: %pM (idx: %d)\n",
274 sta->addr, tsta.sta_index); 275 sta->addr, tsta.sta_index);
275 276
276 priv->nstations++; 277 priv->nstations++;
277 return 0; 278 return 0;
@@ -296,16 +297,16 @@ static int ath9k_htc_remove_station(struct ath9k_htc_priv *priv,
296 WMI_CMD_BUF(WMI_NODE_REMOVE_CMDID, &sta_idx); 297 WMI_CMD_BUF(WMI_NODE_REMOVE_CMDID, &sta_idx);
297 if (ret) { 298 if (ret) {
298 if (sta) 299 if (sta)
299 ath_print(common, ATH_DBG_FATAL, 300 ath_err(common,
300 "Unable to remove station entry for: %pM\n", 301 "Unable to remove station entry for: %pM\n",
301 sta->addr); 302 sta->addr);
302 return ret; 303 return ret;
303 } 304 }
304 305
305 if (sta) 306 if (sta)
306 ath_print(common, ATH_DBG_CONFIG, 307 ath_dbg(common, ATH_DBG_CONFIG,
307 "Removed a station entry for: %pM (idx: %d)\n", 308 "Removed a station entry for: %pM (idx: %d)\n",
308 sta->addr, sta_idx); 309 sta->addr, sta_idx);
309 310
310 priv->nstations--; 311 priv->nstations--;
311 return 0; 312 return 0;
@@ -390,8 +391,8 @@ static int ath9k_htc_send_rate_cmd(struct ath9k_htc_priv *priv,
390 391
391 WMI_CMD_BUF(WMI_RC_RATE_UPDATE_CMDID, trate); 392 WMI_CMD_BUF(WMI_RC_RATE_UPDATE_CMDID, trate);
392 if (ret) { 393 if (ret) {
393 ath_print(common, ATH_DBG_FATAL, 394 ath_err(common,
394 "Unable to initialize Rate information on target\n"); 395 "Unable to initialize Rate information on target\n");
395 } 396 }
396 397
397 return ret; 398 return ret;
@@ -408,9 +409,9 @@ static void ath9k_htc_init_rate(struct ath9k_htc_priv *priv,
408 ath9k_htc_setup_rate(priv, sta, &trate); 409 ath9k_htc_setup_rate(priv, sta, &trate);
409 ret = ath9k_htc_send_rate_cmd(priv, &trate); 410 ret = ath9k_htc_send_rate_cmd(priv, &trate);
410 if (!ret) 411 if (!ret)
411 ath_print(common, ATH_DBG_CONFIG, 412 ath_dbg(common, ATH_DBG_CONFIG,
412 "Updated target sta: %pM, rate caps: 0x%X\n", 413 "Updated target sta: %pM, rate caps: 0x%X\n",
413 sta->addr, be32_to_cpu(trate.capflags)); 414 sta->addr, be32_to_cpu(trate.capflags));
414} 415}
415 416
416static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv, 417static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv,
@@ -435,9 +436,9 @@ static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv,
435 436
436 ret = ath9k_htc_send_rate_cmd(priv, &trate); 437 ret = ath9k_htc_send_rate_cmd(priv, &trate);
437 if (!ret) 438 if (!ret)
438 ath_print(common, ATH_DBG_CONFIG, 439 ath_dbg(common, ATH_DBG_CONFIG,
439 "Updated target sta: %pM, rate caps: 0x%X\n", 440 "Updated target sta: %pM, rate caps: 0x%X\n",
440 bss_conf->bssid, be32_to_cpu(trate.capflags)); 441 bss_conf->bssid, be32_to_cpu(trate.capflags));
441} 442}
442 443
443static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv, 444static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv,
@@ -464,14 +465,14 @@ static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv,
464 465
465 WMI_CMD_BUF(WMI_TX_AGGR_ENABLE_CMDID, &aggr); 466 WMI_CMD_BUF(WMI_TX_AGGR_ENABLE_CMDID, &aggr);
466 if (ret) 467 if (ret)
467 ath_print(common, ATH_DBG_CONFIG, 468 ath_dbg(common, ATH_DBG_CONFIG,
468 "Unable to %s TX aggregation for (%pM, %d)\n", 469 "Unable to %s TX aggregation for (%pM, %d)\n",
469 (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid); 470 (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid);
470 else 471 else
471 ath_print(common, ATH_DBG_CONFIG, 472 ath_dbg(common, ATH_DBG_CONFIG,
472 "%s TX aggregation for (%pM, %d)\n", 473 "%s TX aggregation for (%pM, %d)\n",
473 (aggr.aggr_enable) ? "Starting" : "Stopping", 474 (aggr.aggr_enable) ? "Starting" : "Stopping",
474 sta->addr, tid); 475 sta->addr, tid);
475 476
476 spin_lock_bh(&priv->tx_lock); 477 spin_lock_bh(&priv->tx_lock);
477 ista->tid_state[tid] = (aggr.aggr_enable && !ret) ? AGGR_START : AGGR_STOP; 478 ista->tid_state[tid] = (aggr.aggr_enable && !ret) ? AGGR_START : AGGR_STOP;
@@ -724,7 +725,7 @@ void ath9k_ani_work(struct work_struct *work)
724 /* Long calibration runs independently of short calibration. */ 725 /* Long calibration runs independently of short calibration. */
725 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { 726 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
726 longcal = true; 727 longcal = true;
727 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); 728 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
728 common->ani.longcal_timer = timestamp; 729 common->ani.longcal_timer = timestamp;
729 } 730 }
730 731
@@ -733,8 +734,8 @@ void ath9k_ani_work(struct work_struct *work)
733 if ((timestamp - common->ani.shortcal_timer) >= 734 if ((timestamp - common->ani.shortcal_timer) >=
734 short_cal_interval) { 735 short_cal_interval) {
735 shortcal = true; 736 shortcal = true;
736 ath_print(common, ATH_DBG_ANI, 737 ath_dbg(common, ATH_DBG_ANI,
737 "shortcal @%lu\n", jiffies); 738 "shortcal @%lu\n", jiffies);
738 common->ani.shortcal_timer = timestamp; 739 common->ani.shortcal_timer = timestamp;
739 common->ani.resetcal_timer = timestamp; 740 common->ani.resetcal_timer = timestamp;
740 } 741 }
@@ -895,8 +896,8 @@ static int ath9k_register_led(struct ath9k_htc_priv *priv, struct ath_led *led,
895 896
896 ret = led_classdev_register(wiphy_dev(priv->hw->wiphy), &led->led_cdev); 897 ret = led_classdev_register(wiphy_dev(priv->hw->wiphy), &led->led_cdev);
897 if (ret) 898 if (ret)
898 ath_print(ath9k_hw_common(priv->ah), ATH_DBG_FATAL, 899 ath_err(ath9k_hw_common(priv->ah),
899 "Failed to register led:%s", led->name); 900 "Failed to register led:%s", led->name);
900 else 901 else
901 led->registered = 1; 902 led->registered = 1;
902 903
@@ -1024,9 +1025,9 @@ static void ath9k_htc_radio_enable(struct ieee80211_hw *hw)
1024 /* Reset the HW */ 1025 /* Reset the HW */
1025 ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 1026 ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
1026 if (ret) { 1027 if (ret) {
1027 ath_print(common, ATH_DBG_FATAL, 1028 ath_err(common,
1028 "Unable to reset hardware; reset status %d " 1029 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1029 "(freq %u MHz)\n", ret, ah->curchan->channel); 1030 ret, ah->curchan->channel);
1030 } 1031 }
1031 1032
1032 ath_update_txpow(priv); 1033 ath_update_txpow(priv);
@@ -1087,9 +1088,9 @@ static void ath9k_htc_radio_disable(struct ieee80211_hw *hw)
1087 /* Reset the HW */ 1088 /* Reset the HW */
1088 ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 1089 ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
1089 if (ret) { 1090 if (ret) {
1090 ath_print(common, ATH_DBG_FATAL, 1091 ath_err(common,
1091 "Unable to reset hardware; reset status %d " 1092 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1092 "(freq %u MHz)\n", ret, ah->curchan->channel); 1093 ret, ah->curchan->channel);
1093 } 1094 }
1094 1095
1095 /* Disable the PHY */ 1096 /* Disable the PHY */
@@ -1124,15 +1125,15 @@ static int ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1124 ret = ath9k_htc_tx_start(priv, skb); 1125 ret = ath9k_htc_tx_start(priv, skb);
1125 if (ret != 0) { 1126 if (ret != 0) {
1126 if (ret == -ENOMEM) { 1127 if (ret == -ENOMEM) {
1127 ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT, 1128 ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
1128 "Stopping TX queues\n"); 1129 "Stopping TX queues\n");
1129 ieee80211_stop_queues(hw); 1130 ieee80211_stop_queues(hw);
1130 spin_lock_bh(&priv->tx_lock); 1131 spin_lock_bh(&priv->tx_lock);
1131 priv->tx_queues_stop = true; 1132 priv->tx_queues_stop = true;
1132 spin_unlock_bh(&priv->tx_lock); 1133 spin_unlock_bh(&priv->tx_lock);
1133 } else { 1134 } else {
1134 ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT, 1135 ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
1135 "Tx failed"); 1136 "Tx failed\n");
1136 } 1137 }
1137 goto fail_tx; 1138 goto fail_tx;
1138 } 1139 }
@@ -1158,9 +1159,9 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
1158 1159
1159 mutex_lock(&priv->mutex); 1160 mutex_lock(&priv->mutex);
1160 1161
1161 ath_print(common, ATH_DBG_CONFIG, 1162 ath_dbg(common, ATH_DBG_CONFIG,
1162 "Starting driver with initial channel: %d MHz\n", 1163 "Starting driver with initial channel: %d MHz\n",
1163 curchan->center_freq); 1164 curchan->center_freq);
1164 1165
1165 /* Ensure that HW is awake before flushing RX */ 1166 /* Ensure that HW is awake before flushing RX */
1166 ath9k_htc_setpower(priv, ATH9K_PM_AWAKE); 1167 ath9k_htc_setpower(priv, ATH9K_PM_AWAKE);
@@ -1175,9 +1176,9 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
1175 ath9k_hw_htc_resetinit(ah); 1176 ath9k_hw_htc_resetinit(ah);
1176 ret = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 1177 ret = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
1177 if (ret) { 1178 if (ret) {
1178 ath_print(common, ATH_DBG_FATAL, 1179 ath_err(common,
1179 "Unable to reset hardware; reset status %d " 1180 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1180 "(freq %u MHz)\n", ret, curchan->center_freq); 1181 ret, curchan->center_freq);
1181 mutex_unlock(&priv->mutex); 1182 mutex_unlock(&priv->mutex);
1182 return ret; 1183 return ret;
1183 } 1184 }
@@ -1223,7 +1224,7 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
1223 mutex_lock(&priv->mutex); 1224 mutex_lock(&priv->mutex);
1224 1225
1225 if (priv->op_flags & OP_INVALID) { 1226 if (priv->op_flags & OP_INVALID) {
1226 ath_print(common, ATH_DBG_ANY, "Device not present\n"); 1227 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
1227 mutex_unlock(&priv->mutex); 1228 mutex_unlock(&priv->mutex);
1228 return; 1229 return;
1229 } 1230 }
@@ -1243,11 +1244,10 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
1243 /* Remove monitor interface here */ 1244 /* Remove monitor interface here */
1244 if (ah->opmode == NL80211_IFTYPE_MONITOR) { 1245 if (ah->opmode == NL80211_IFTYPE_MONITOR) {
1245 if (ath9k_htc_remove_monitor_interface(priv)) 1246 if (ath9k_htc_remove_monitor_interface(priv))
1246 ath_print(common, ATH_DBG_FATAL, 1247 ath_err(common, "Unable to remove monitor interface\n");
1247 "Unable to remove monitor interface\n");
1248 else 1248 else
1249 ath_print(common, ATH_DBG_CONFIG, 1249 ath_dbg(common, ATH_DBG_CONFIG,
1250 "Monitor interface removed\n"); 1250 "Monitor interface removed\n");
1251 } 1251 }
1252 1252
1253 if (ah->btcoex_hw.enabled) { 1253 if (ah->btcoex_hw.enabled) {
@@ -1264,7 +1264,7 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
1264 1264
1265 priv->op_flags |= OP_INVALID; 1265 priv->op_flags |= OP_INVALID;
1266 1266
1267 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); 1267 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
1268 mutex_unlock(&priv->mutex); 1268 mutex_unlock(&priv->mutex);
1269} 1269}
1270 1270
@@ -1298,14 +1298,14 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
1298 hvif.opmode = cpu_to_be32(HTC_M_IBSS); 1298 hvif.opmode = cpu_to_be32(HTC_M_IBSS);
1299 break; 1299 break;
1300 default: 1300 default:
1301 ath_print(common, ATH_DBG_FATAL, 1301 ath_err(common,
1302 "Interface type %d not yet supported\n", vif->type); 1302 "Interface type %d not yet supported\n", vif->type);
1303 ret = -EOPNOTSUPP; 1303 ret = -EOPNOTSUPP;
1304 goto out; 1304 goto out;
1305 } 1305 }
1306 1306
1307 ath_print(common, ATH_DBG_CONFIG, 1307 ath_dbg(common, ATH_DBG_CONFIG,
1308 "Attach a VIF of type: %d\n", vif->type); 1308 "Attach a VIF of type: %d\n", vif->type);
1309 1309
1310 priv->ah->opmode = vif->type; 1310 priv->ah->opmode = vif->type;
1311 1311
@@ -1328,8 +1328,8 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
1328 1328
1329 ret = ath9k_htc_update_cap_target(priv); 1329 ret = ath9k_htc_update_cap_target(priv);
1330 if (ret) 1330 if (ret)
1331 ath_print(common, ATH_DBG_CONFIG, "Failed to update" 1331 ath_dbg(common, ATH_DBG_CONFIG,
1332 " capability in target \n"); 1332 "Failed to update capability in target\n");
1333 1333
1334 priv->vif = vif; 1334 priv->vif = vif;
1335out: 1335out:
@@ -1349,7 +1349,7 @@ static void ath9k_htc_remove_interface(struct ieee80211_hw *hw,
1349 int ret = 0; 1349 int ret = 0;
1350 u8 cmd_rsp; 1350 u8 cmd_rsp;
1351 1351
1352 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); 1352 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
1353 1353
1354 mutex_lock(&priv->mutex); 1354 mutex_lock(&priv->mutex);
1355 ath9k_htc_ps_wakeup(priv); 1355 ath9k_htc_ps_wakeup(priv);
@@ -1386,8 +1386,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1386 mutex_unlock(&priv->htc_pm_lock); 1386 mutex_unlock(&priv->htc_pm_lock);
1387 1387
1388 if (enable_radio) { 1388 if (enable_radio) {
1389 ath_print(common, ATH_DBG_CONFIG, 1389 ath_dbg(common, ATH_DBG_CONFIG,
1390 "not-idle: enabling radio\n"); 1390 "not-idle: enabling radio\n");
1391 ath9k_htc_setpower(priv, ATH9K_PM_AWAKE); 1391 ath9k_htc_setpower(priv, ATH9K_PM_AWAKE);
1392 ath9k_htc_radio_enable(hw); 1392 ath9k_htc_radio_enable(hw);
1393 } 1393 }
@@ -1397,21 +1397,21 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1397 struct ieee80211_channel *curchan = hw->conf.channel; 1397 struct ieee80211_channel *curchan = hw->conf.channel;
1398 int pos = curchan->hw_value; 1398 int pos = curchan->hw_value;
1399 1399
1400 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", 1400 ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1401 curchan->center_freq); 1401 curchan->center_freq);
1402 1402
1403 ath9k_cmn_update_ichannel(&priv->ah->channels[pos], 1403 ath9k_cmn_update_ichannel(&priv->ah->channels[pos],
1404 hw->conf.channel, 1404 hw->conf.channel,
1405 hw->conf.channel_type); 1405 hw->conf.channel_type);
1406 1406
1407 if (ath9k_htc_set_channel(priv, hw, &priv->ah->channels[pos]) < 0) { 1407 if (ath9k_htc_set_channel(priv, hw, &priv->ah->channels[pos]) < 0) {
1408 ath_print(common, ATH_DBG_FATAL, 1408 ath_err(common, "Unable to set channel\n");
1409 "Unable to set channel\n");
1410 mutex_unlock(&priv->mutex); 1409 mutex_unlock(&priv->mutex);
1411 return -EINVAL; 1410 return -EINVAL;
1412 } 1411 }
1413 1412
1414 } 1413 }
1414
1415 if (changed & IEEE80211_CONF_CHANGE_PS) { 1415 if (changed & IEEE80211_CONF_CHANGE_PS) {
1416 if (conf->flags & IEEE80211_CONF_PS) { 1416 if (conf->flags & IEEE80211_CONF_PS) {
1417 ath9k_htc_setpower(priv, ATH9K_PM_NETWORK_SLEEP); 1417 ath9k_htc_setpower(priv, ATH9K_PM_NETWORK_SLEEP);
@@ -1423,14 +1423,18 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1423 } 1423 }
1424 } 1424 }
1425 1425
1426 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1427 priv->txpowlimit = 2 * conf->power_level;
1428 ath_update_txpow(priv);
1429 }
1430
1426 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1431 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1427 if (conf->flags & IEEE80211_CONF_MONITOR) { 1432 if (conf->flags & IEEE80211_CONF_MONITOR) {
1428 if (ath9k_htc_add_monitor_interface(priv)) 1433 if (ath9k_htc_add_monitor_interface(priv))
1429 ath_print(common, ATH_DBG_FATAL, 1434 ath_err(common, "Failed to set monitor mode\n");
1430 "Failed to set monitor mode\n");
1431 else 1435 else
1432 ath_print(common, ATH_DBG_CONFIG, 1436 ath_dbg(common, ATH_DBG_CONFIG,
1433 "HW opmode set to Monitor mode\n"); 1437 "HW opmode set to Monitor mode\n");
1434 } 1438 }
1435 } 1439 }
1436 1440
@@ -1442,8 +1446,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1442 } 1446 }
1443 mutex_unlock(&priv->htc_pm_lock); 1447 mutex_unlock(&priv->htc_pm_lock);
1444 1448
1445 ath_print(common, ATH_DBG_CONFIG, 1449 ath_dbg(common, ATH_DBG_CONFIG,
1446 "idle: disabling radio\n"); 1450 "idle: disabling radio\n");
1447 ath9k_htc_radio_disable(hw); 1451 ath9k_htc_radio_disable(hw);
1448 } 1452 }
1449 1453
@@ -1480,8 +1484,8 @@ static void ath9k_htc_configure_filter(struct ieee80211_hw *hw,
1480 rfilt = ath9k_htc_calcrxfilter(priv); 1484 rfilt = ath9k_htc_calcrxfilter(priv);
1481 ath9k_hw_setrxfilter(priv->ah, rfilt); 1485 ath9k_hw_setrxfilter(priv->ah, rfilt);
1482 1486
1483 ath_print(ath9k_hw_common(priv->ah), ATH_DBG_CONFIG, 1487 ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_CONFIG,
1484 "Set HW RX filter: 0x%x\n", rfilt); 1488 "Set HW RX filter: 0x%x\n", rfilt);
1485 1489
1486 ath9k_htc_ps_restore(priv); 1490 ath9k_htc_ps_restore(priv);
1487 mutex_unlock(&priv->mutex); 1491 mutex_unlock(&priv->mutex);
@@ -1544,15 +1548,14 @@ static int ath9k_htc_conf_tx(struct ieee80211_hw *hw, u16 queue,
1544 1548
1545 qnum = get_hw_qnum(queue, priv->hwq_map); 1549 qnum = get_hw_qnum(queue, priv->hwq_map);
1546 1550
1547 ath_print(common, ATH_DBG_CONFIG, 1551 ath_dbg(common, ATH_DBG_CONFIG,
1548 "Configure tx [queue/hwq] [%d/%d], " 1552 "Configure tx [queue/hwq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1549 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1553 queue, qnum, params->aifs, params->cw_min,
1550 queue, qnum, params->aifs, params->cw_min, 1554 params->cw_max, params->txop);
1551 params->cw_max, params->txop);
1552 1555
1553 ret = ath_htc_txq_update(priv, qnum, &qi); 1556 ret = ath_htc_txq_update(priv, qnum, &qi);
1554 if (ret) { 1557 if (ret) {
1555 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); 1558 ath_err(common, "TXQ Update failed\n");
1556 goto out; 1559 goto out;
1557 } 1560 }
1558 1561
@@ -1580,7 +1583,7 @@ static int ath9k_htc_set_key(struct ieee80211_hw *hw,
1580 return -ENOSPC; 1583 return -ENOSPC;
1581 1584
1582 mutex_lock(&priv->mutex); 1585 mutex_lock(&priv->mutex);
1583 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); 1586 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
1584 ath9k_htc_ps_wakeup(priv); 1587 ath9k_htc_ps_wakeup(priv);
1585 1588
1586 switch (cmd) { 1589 switch (cmd) {
@@ -1626,7 +1629,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
1626 if (changed & BSS_CHANGED_ASSOC) { 1629 if (changed & BSS_CHANGED_ASSOC) {
1627 common->curaid = bss_conf->assoc ? 1630 common->curaid = bss_conf->assoc ?
1628 bss_conf->aid : 0; 1631 bss_conf->aid : 0;
1629 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", 1632 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
1630 bss_conf->assoc); 1633 bss_conf->assoc);
1631 1634
1632 if (bss_conf->assoc) { 1635 if (bss_conf->assoc) {
@@ -1643,9 +1646,9 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
1643 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1646 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1644 ath9k_hw_write_associd(ah); 1647 ath9k_hw_write_associd(ah);
1645 1648
1646 ath_print(common, ATH_DBG_CONFIG, 1649 ath_dbg(common, ATH_DBG_CONFIG,
1647 "BSSID: %pM aid: 0x%x\n", 1650 "BSSID: %pM aid: 0x%x\n",
1648 common->curbssid, common->curaid); 1651 common->curbssid, common->curaid);
1649 } 1652 }
1650 1653
1651 if ((changed & BSS_CHANGED_BEACON_INT) || 1654 if ((changed & BSS_CHANGED_BEACON_INT) ||
@@ -1663,8 +1666,8 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
1663 } 1666 }
1664 1667
1665 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 1668 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1666 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", 1669 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1667 bss_conf->use_short_preamble); 1670 bss_conf->use_short_preamble);
1668 if (bss_conf->use_short_preamble) 1671 if (bss_conf->use_short_preamble)
1669 priv->op_flags |= OP_PREAMBLE_SHORT; 1672 priv->op_flags |= OP_PREAMBLE_SHORT;
1670 else 1673 else
@@ -1672,8 +1675,8 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
1672 } 1675 }
1673 1676
1674 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 1677 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1675 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", 1678 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1676 bss_conf->use_cts_prot); 1679 bss_conf->use_cts_prot);
1677 if (bss_conf->use_cts_prot && 1680 if (bss_conf->use_cts_prot &&
1678 hw->conf.channel->band != IEEE80211_BAND_5GHZ) 1681 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1679 priv->op_flags |= OP_PROTECT_ENABLE; 1682 priv->op_flags |= OP_PROTECT_ENABLE;
@@ -1764,8 +1767,7 @@ static int ath9k_htc_ampdu_action(struct ieee80211_hw *hw,
1764 spin_unlock_bh(&priv->tx_lock); 1767 spin_unlock_bh(&priv->tx_lock);
1765 break; 1768 break;
1766 default: 1769 default:
1767 ath_print(ath9k_hw_common(priv->ah), ATH_DBG_FATAL, 1770 ath_err(ath9k_hw_common(priv->ah), "Unknown AMPDU action\n");
1768 "Unknown AMPDU action\n");
1769 } 1771 }
1770 1772
1771 return ret; 1773 return ret;
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
index 77958675b55f..31fad82239b3 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
@@ -69,8 +69,8 @@ int ath_htc_txq_update(struct ath9k_htc_priv *priv, int qnum,
69 qi.tqi_readyTime = qinfo->tqi_readyTime; 69 qi.tqi_readyTime = qinfo->tqi_readyTime;
70 70
71 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 71 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
72 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 72 ath_err(ath9k_hw_common(ah),
73 "Unable to update hardware queue %u!\n", qnum); 73 "Unable to update hardware queue %u!\n", qnum);
74 error = -EIO; 74 error = -EIO;
75 } else { 75 } else {
76 ath9k_hw_resettxqueue(ah, qnum); 76 ath9k_hw_resettxqueue(ah, qnum);
@@ -270,8 +270,8 @@ void ath9k_tx_tasklet(unsigned long data)
270 if (priv->tx_queues_stop) { 270 if (priv->tx_queues_stop) {
271 priv->tx_queues_stop = false; 271 priv->tx_queues_stop = false;
272 spin_unlock_bh(&priv->tx_lock); 272 spin_unlock_bh(&priv->tx_lock);
273 ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT, 273 ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
274 "Waking up TX queues\n"); 274 "Waking up TX queues\n");
275 ieee80211_wake_queues(priv->hw); 275 ieee80211_wake_queues(priv->hw);
276 return; 276 return;
277 } 277 }
@@ -296,8 +296,7 @@ void ath9k_htc_txep(void *drv_priv, struct sk_buff *skb,
296 (ep_id == priv->data_vo_ep)) { 296 (ep_id == priv->data_vo_ep)) {
297 skb_pull(skb, sizeof(struct tx_frame_hdr)); 297 skb_pull(skb, sizeof(struct tx_frame_hdr));
298 } else { 298 } else {
299 ath_print(common, ATH_DBG_FATAL, 299 ath_err(common, "Unsupported TX EPID: %d\n", ep_id);
300 "Unsupported TX EPID: %d\n", ep_id);
301 dev_kfree_skb_any(skb); 300 dev_kfree_skb_any(skb);
302 return; 301 return;
303 } 302 }
@@ -337,9 +336,8 @@ bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv, int subtype)
337 return false; 336 return false;
338 337
339 if (qnum >= ARRAY_SIZE(priv->hwq_map)) { 338 if (qnum >= ARRAY_SIZE(priv->hwq_map)) {
340 ath_print(common, ATH_DBG_FATAL, 339 ath_err(common, "qnum %u out of range, max %zu!\n",
341 "qnum %u out of range, max %u!\n", 340 qnum, ARRAY_SIZE(priv->hwq_map));
342 qnum, (unsigned int)ARRAY_SIZE(priv->hwq_map));
343 ath9k_hw_releasetxqueue(ah, qnum); 341 ath9k_hw_releasetxqueue(ah, qnum);
344 return false; 342 return false;
345 } 343 }
@@ -490,8 +488,7 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
490 __le16 fc; 488 __le16 fc;
491 489
492 if (skb->len <= HTC_RX_FRAME_HEADER_SIZE) { 490 if (skb->len <= HTC_RX_FRAME_HEADER_SIZE) {
493 ath_print(common, ATH_DBG_FATAL, 491 ath_err(common, "Corrupted RX frame, dropping\n");
494 "Corrupted RX frame, dropping\n");
495 goto rx_next; 492 goto rx_next;
496 } 493 }
497 494
@@ -499,10 +496,9 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
499 496
500 if (be16_to_cpu(rxstatus->rs_datalen) - 497 if (be16_to_cpu(rxstatus->rs_datalen) -
501 (skb->len - HTC_RX_FRAME_HEADER_SIZE) != 0) { 498 (skb->len - HTC_RX_FRAME_HEADER_SIZE) != 0) {
502 ath_print(common, ATH_DBG_FATAL, 499 ath_err(common,
503 "Corrupted RX data len, dropping " 500 "Corrupted RX data len, dropping (dlen: %d, skblen: %d)\n",
504 "(dlen: %d, skblen: %d)\n", 501 rxstatus->rs_datalen, skb->len);
505 rxstatus->rs_datalen, skb->len);
506 goto rx_next; 502 goto rx_next;
507 } 503 }
508 504
@@ -685,8 +681,8 @@ void ath9k_htc_rxep(void *drv_priv, struct sk_buff *skb,
685 spin_unlock(&priv->rx.rxbuflock); 681 spin_unlock(&priv->rx.rxbuflock);
686 682
687 if (rxbuf == NULL) { 683 if (rxbuf == NULL) {
688 ath_print(common, ATH_DBG_ANY, 684 ath_dbg(common, ATH_DBG_ANY,
689 "No free RX buffer\n"); 685 "No free RX buffer\n");
690 goto err; 686 goto err;
691 } 687 }
692 688
@@ -728,8 +724,7 @@ int ath9k_rx_init(struct ath9k_htc_priv *priv)
728 for (i = 0; i < ATH9K_HTC_RXBUF; i++) { 724 for (i = 0; i < ATH9K_HTC_RXBUF; i++) {
729 rxbuf = kzalloc(sizeof(struct ath9k_htc_rxbuf), GFP_KERNEL); 725 rxbuf = kzalloc(sizeof(struct ath9k_htc_rxbuf), GFP_KERNEL);
730 if (rxbuf == NULL) { 726 if (rxbuf == NULL) {
731 ath_print(common, ATH_DBG_FATAL, 727 ath_err(common, "Unable to allocate RX buffers\n");
732 "Unable to allocate RX buffers\n");
733 goto err; 728 goto err;
734 } 729 }
735 list_add_tail(&rxbuf->list, &priv->rx.rxbuf); 730 list_add_tail(&rxbuf->list, &priv->rx.rxbuf);
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 9b1ee7fc05c1..516227fa668e 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -129,9 +129,9 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
129 udelay(AH_TIME_QUANTUM); 129 udelay(AH_TIME_QUANTUM);
130 } 130 }
131 131
132 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, 132 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val); 134 timeout, reg, REG_READ(ah, reg), mask, val);
135 135
136 return false; 136 return false;
137} 137}
@@ -211,8 +211,8 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
211 } 211 }
212 break; 212 break;
213 default: 213 default:
214 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 214 ath_err(ath9k_hw_common(ah),
215 "Unknown phy %u (rate ix %u)\n", phy, rateix); 215 "Unknown phy %u (rate ix %u)\n", phy, rateix);
216 txTime = 0; 216 txTime = 0;
217 break; 217 break;
218 } 218 }
@@ -331,11 +331,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
331 REG_WRITE(ah, addr, wrData); 331 REG_WRITE(ah, addr, wrData);
332 rdData = REG_READ(ah, addr); 332 rdData = REG_READ(ah, addr);
333 if (rdData != wrData) { 333 if (rdData != wrData) {
334 ath_print(common, ATH_DBG_FATAL, 334 ath_err(common,
335 "address test failed " 335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
336 "addr: 0x%08x - wr:0x%08x != " 336 addr, wrData, rdData);
337 "rd:0x%08x\n",
338 addr, wrData, rdData);
339 return false; 337 return false;
340 } 338 }
341 } 339 }
@@ -344,11 +342,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
344 REG_WRITE(ah, addr, wrData); 342 REG_WRITE(ah, addr, wrData);
345 rdData = REG_READ(ah, addr); 343 rdData = REG_READ(ah, addr);
346 if (wrData != rdData) { 344 if (wrData != rdData) {
347 ath_print(common, ATH_DBG_FATAL, 345 ath_err(common,
348 "address test failed " 346 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
349 "addr: 0x%08x - wr:0x%08x != " 347 addr, wrData, rdData);
350 "rd:0x%08x\n",
351 addr, wrData, rdData);
352 return false; 348 return false;
353 } 349 }
354 } 350 }
@@ -469,16 +465,15 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
469 if (ecode != 0) 465 if (ecode != 0)
470 return ecode; 466 return ecode;
471 467
472 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, 468 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
473 "Eeprom VER: %d, REV: %d\n", 469 "Eeprom VER: %d, REV: %d\n",
474 ah->eep_ops->get_eeprom_ver(ah), 470 ah->eep_ops->get_eeprom_ver(ah),
475 ah->eep_ops->get_eeprom_rev(ah)); 471 ah->eep_ops->get_eeprom_rev(ah));
476 472
477 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 473 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
478 if (ecode) { 474 if (ecode) {
479 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 475 ath_err(ath9k_hw_common(ah),
480 "Failed allocating banks for " 476 "Failed allocating banks for external radio\n");
481 "external radio\n");
482 ath9k_hw_rf_free_ext_banks(ah); 477 ath9k_hw_rf_free_ext_banks(ah);
483 return ecode; 478 return ecode;
484 } 479 }
@@ -509,8 +504,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
509 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 504 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
510 505
511 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 506 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
512 ath_print(common, ATH_DBG_FATAL, 507 ath_err(common, "Couldn't reset chip\n");
513 "Couldn't reset chip\n");
514 return -EIO; 508 return -EIO;
515 } 509 }
516 510
@@ -520,7 +514,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
520 ath9k_hw_attach_ops(ah); 514 ath9k_hw_attach_ops(ah);
521 515
522 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 516 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
523 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 517 ath_err(common, "Couldn't wakeup chip\n");
524 return -EIO; 518 return -EIO;
525 } 519 }
526 520
@@ -536,7 +530,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
536 } 530 }
537 } 531 }
538 532
539 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 533 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
540 ah->config.serialize_regmode); 534 ah->config.serialize_regmode);
541 535
542 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 536 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
@@ -545,10 +539,9 @@ static int __ath9k_hw_init(struct ath_hw *ah)
545 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 539 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
546 540
547 if (!ath9k_hw_macversion_supported(ah)) { 541 if (!ath9k_hw_macversion_supported(ah)) {
548 ath_print(common, ATH_DBG_FATAL, 542 ath_err(common,
549 "Mac Chip Rev 0x%02x.%x is not supported by " 543 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
550 "this driver\n", ah->hw_version.macVersion, 544 ah->hw_version.macVersion, ah->hw_version.macRev);
551 ah->hw_version.macRev);
552 return -EOPNOTSUPP; 545 return -EOPNOTSUPP;
553 } 546 }
554 547
@@ -594,8 +587,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
594 587
595 r = ath9k_hw_init_macaddr(ah); 588 r = ath9k_hw_init_macaddr(ah);
596 if (r) { 589 if (r) {
597 ath_print(common, ATH_DBG_FATAL, 590 ath_err(common, "Failed to initialize MAC address\n");
598 "Failed to initialize MAC address\n");
599 return r; 591 return r;
600 } 592 }
601 593
@@ -629,21 +621,21 @@ int ath9k_hw_init(struct ath_hw *ah)
629 case AR9287_DEVID_PCIE: 621 case AR9287_DEVID_PCIE:
630 case AR2427_DEVID_PCIE: 622 case AR2427_DEVID_PCIE:
631 case AR9300_DEVID_PCIE: 623 case AR9300_DEVID_PCIE:
624 case AR9300_DEVID_AR9485_PCIE:
632 break; 625 break;
633 default: 626 default:
634 if (common->bus_ops->ath_bus_type == ATH_USB) 627 if (common->bus_ops->ath_bus_type == ATH_USB)
635 break; 628 break;
636 ath_print(common, ATH_DBG_FATAL, 629 ath_err(common, "Hardware device ID 0x%04x not supported\n",
637 "Hardware device ID 0x%04x not supported\n", 630 ah->hw_version.devid);
638 ah->hw_version.devid);
639 return -EOPNOTSUPP; 631 return -EOPNOTSUPP;
640 } 632 }
641 633
642 ret = __ath9k_hw_init(ah); 634 ret = __ath9k_hw_init(ah);
643 if (ret) { 635 if (ret) {
644 ath_print(common, ATH_DBG_FATAL, 636 ath_err(common,
645 "Unable to initialize hardware; " 637 "Unable to initialize hardware; initialization status: %d\n",
646 "initialization status: %d\n", ret); 638 ret);
647 return ret; 639 return ret;
648 } 640 }
649 641
@@ -675,7 +667,12 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
675static void ath9k_hw_init_pll(struct ath_hw *ah, 667static void ath9k_hw_init_pll(struct ath_hw *ah,
676 struct ath9k_channel *chan) 668 struct ath9k_channel *chan)
677{ 669{
678 u32 pll = ath9k_hw_compute_pll_control(ah, chan); 670 u32 pll;
671
672 if (AR_SREV_9485(ah))
673 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
674
675 pll = ath9k_hw_compute_pll_control(ah, chan);
679 676
680 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 677 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
681 678
@@ -767,8 +764,8 @@ static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
767static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 764static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
768{ 765{
769 if (tu > 0xFFFF) { 766 if (tu > 0xFFFF) {
770 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 767 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
771 "bad global tx timeout %u\n", tu); 768 "bad global tx timeout %u\n", tu);
772 ah->globaltxtimeout = (u32) -1; 769 ah->globaltxtimeout = (u32) -1;
773 return false; 770 return false;
774 } else { 771 } else {
@@ -785,8 +782,8 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
785 int slottime; 782 int slottime;
786 int sifstime; 783 int sifstime;
787 784
788 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 785 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
789 ah->misc_mode); 786 ah->misc_mode);
790 787
791 if (ah->misc_mode != 0) 788 if (ah->misc_mode != 0)
792 REG_WRITE(ah, AR_PCU_MISC, 789 REG_WRITE(ah, AR_PCU_MISC,
@@ -1029,8 +1026,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1029 1026
1030 REG_WRITE(ah, AR_RTC_RC, 0); 1027 REG_WRITE(ah, AR_RTC_RC, 0);
1031 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1028 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1032 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1029 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1033 "RTC stuck in MAC reset\n"); 1030 "RTC stuck in MAC reset\n");
1034 return false; 1031 return false;
1035 } 1032 }
1036 1033
@@ -1076,8 +1073,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1076 AR_RTC_STATUS_M, 1073 AR_RTC_STATUS_M,
1077 AR_RTC_STATUS_ON, 1074 AR_RTC_STATUS_ON,
1078 AH_WAIT_TIMEOUT)) { 1075 AH_WAIT_TIMEOUT)) {
1079 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1076 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1080 "RTC not waking up\n"); 1077 "RTC not waking up\n");
1081 return false; 1078 return false;
1082 } 1079 }
1083 1080
@@ -1137,16 +1134,14 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1137 1134
1138 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1135 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1139 if (ath9k_hw_numtxpending(ah, qnum)) { 1136 if (ath9k_hw_numtxpending(ah, qnum)) {
1140 ath_print(common, ATH_DBG_QUEUE, 1137 ath_dbg(common, ATH_DBG_QUEUE,
1141 "Transmit frames pending on " 1138 "Transmit frames pending on queue %d\n", qnum);
1142 "queue %d\n", qnum);
1143 return false; 1139 return false;
1144 } 1140 }
1145 } 1141 }
1146 1142
1147 if (!ath9k_hw_rfbus_req(ah)) { 1143 if (!ath9k_hw_rfbus_req(ah)) {
1148 ath_print(common, ATH_DBG_FATAL, 1144 ath_err(common, "Could not kill baseband RX\n");
1149 "Could not kill baseband RX\n");
1150 return false; 1145 return false;
1151 } 1146 }
1152 1147
@@ -1154,8 +1149,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1154 1149
1155 r = ath9k_hw_rf_set_freq(ah, chan); 1150 r = ath9k_hw_rf_set_freq(ah, chan);
1156 if (r) { 1151 if (r) {
1157 ath_print(common, ATH_DBG_FATAL, 1152 ath_err(common, "Failed to set channel\n");
1158 "Failed to set channel\n");
1159 return false; 1153 return false;
1160 } 1154 }
1161 ath9k_hw_set_clockrate(ah); 1155 ath9k_hw_set_clockrate(ah);
@@ -1222,7 +1216,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1222 if (!ah->chip_fullsleep) { 1216 if (!ah->chip_fullsleep) {
1223 ath9k_hw_abortpcurecv(ah); 1217 ath9k_hw_abortpcurecv(ah);
1224 if (!ath9k_hw_stopdmarecv(ah)) { 1218 if (!ath9k_hw_stopdmarecv(ah)) {
1225 ath_print(common, ATH_DBG_XMIT, 1219 ath_dbg(common, ATH_DBG_XMIT,
1226 "Failed to stop receive dma\n"); 1220 "Failed to stop receive dma\n");
1227 bChannelChange = false; 1221 bChannelChange = false;
1228 } 1222 }
@@ -1287,7 +1281,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1287 } 1281 }
1288 1282
1289 if (!ath9k_hw_chip_reset(ah, chan)) { 1283 if (!ath9k_hw_chip_reset(ah, chan)) {
1290 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); 1284 ath_err(common, "Chip reset failed\n");
1291 return -EINVAL; 1285 return -EINVAL;
1292 } 1286 }
1293 1287
@@ -1434,13 +1428,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1434 u32 mask; 1428 u32 mask;
1435 mask = REG_READ(ah, AR_CFG); 1429 mask = REG_READ(ah, AR_CFG);
1436 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1430 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1437 ath_print(common, ATH_DBG_RESET, 1431 ath_dbg(common, ATH_DBG_RESET,
1438 "CFG Byte Swap Set 0x%x\n", mask); 1432 "CFG Byte Swap Set 0x%x\n", mask);
1439 } else { 1433 } else {
1440 mask = 1434 mask =
1441 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1435 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1442 REG_WRITE(ah, AR_CFG, mask); 1436 REG_WRITE(ah, AR_CFG, mask);
1443 ath_print(common, ATH_DBG_RESET, 1437 ath_dbg(common, ATH_DBG_RESET,
1444 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1438 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1445 } 1439 }
1446 } else { 1440 } else {
@@ -1568,9 +1562,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1568 AR_RTC_FORCE_WAKE_EN); 1562 AR_RTC_FORCE_WAKE_EN);
1569 } 1563 }
1570 if (i == 0) { 1564 if (i == 0) {
1571 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1565 ath_err(ath9k_hw_common(ah),
1572 "Failed to wakeup in %uus\n", 1566 "Failed to wakeup in %uus\n",
1573 POWER_UP_TIME / 20); 1567 POWER_UP_TIME / 20);
1574 return false; 1568 return false;
1575 } 1569 }
1576 } 1570 }
@@ -1594,8 +1588,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1594 if (ah->power_mode == mode) 1588 if (ah->power_mode == mode)
1595 return status; 1589 return status;
1596 1590
1597 ath_print(common, ATH_DBG_RESET, "%s -> %s\n", 1591 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1598 modes[ah->power_mode], modes[mode]); 1592 modes[ah->power_mode], modes[mode]);
1599 1593
1600 switch (mode) { 1594 switch (mode) {
1601 case ATH9K_PM_AWAKE: 1595 case ATH9K_PM_AWAKE:
@@ -1609,12 +1603,18 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1609 ath9k_set_power_network_sleep(ah, setChip); 1603 ath9k_set_power_network_sleep(ah, setChip);
1610 break; 1604 break;
1611 default: 1605 default:
1612 ath_print(common, ATH_DBG_FATAL, 1606 ath_err(common, "Unknown power mode %u\n", mode);
1613 "Unknown power mode %u\n", mode);
1614 return false; 1607 return false;
1615 } 1608 }
1616 ah->power_mode = mode; 1609 ah->power_mode = mode;
1617 1610
1611 /*
1612 * XXX: If this warning never comes up after a while then
1613 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1614 * ath9k_hw_setpower() return type void.
1615 */
1616 ATH_DBG_WARN_ON_ONCE(!status);
1617
1618 return status; 1618 return status;
1619} 1619}
1620EXPORT_SYMBOL(ath9k_hw_setpower); 1620EXPORT_SYMBOL(ath9k_hw_setpower);
@@ -1669,9 +1669,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1669 flags |= AR_TBTT_TIMER_EN; 1669 flags |= AR_TBTT_TIMER_EN;
1670 break; 1670 break;
1671 } 1671 }
1672 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, 1672 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1673 "%s: unsupported opmode: %d\n", 1673 "%s: unsupported opmode: %d\n",
1674 __func__, ah->opmode); 1674 __func__, ah->opmode);
1675 return; 1675 return;
1676 break; 1676 break;
1677 } 1677 }
@@ -1727,10 +1727,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1727 else 1727 else
1728 nextTbtt = bs->bs_nexttbtt; 1728 nextTbtt = bs->bs_nexttbtt;
1729 1729
1730 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 1730 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1731 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 1731 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1732 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1732 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1733 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1733 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1734 1734
1735 ENABLE_REGWRITE_BUFFER(ah); 1735 ENABLE_REGWRITE_BUFFER(ah);
1736 1736
@@ -1776,7 +1776,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1776 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 1776 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1777 1777
1778 u16 capField = 0, eeval; 1778 u16 capField = 0, eeval;
1779 u8 ant_div_ctl1; 1779 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1780 1780
1781 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 1781 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1782 regulatory->current_rd = eeval; 1782 regulatory->current_rd = eeval;
@@ -1795,14 +1795,14 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1795 regulatory->current_rd += 5; 1795 regulatory->current_rd += 5;
1796 else if (regulatory->current_rd == 0x41) 1796 else if (regulatory->current_rd == 0x41)
1797 regulatory->current_rd = 0x43; 1797 regulatory->current_rd = 0x43;
1798 ath_print(common, ATH_DBG_REGULATORY, 1798 ath_dbg(common, ATH_DBG_REGULATORY,
1799 "regdomain mapped to 0x%x\n", regulatory->current_rd); 1799 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1800 } 1800 }
1801 1801
1802 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 1802 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1803 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 1803 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1804 ath_print(common, ATH_DBG_FATAL, 1804 ath_err(common,
1805 "no band has been marked as supported in EEPROM.\n"); 1805 "no band has been marked as supported in EEPROM\n");
1806 return -EINVAL; 1806 return -EINVAL;
1807 } 1807 }
1808 1808
@@ -1940,8 +1940,10 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1940 } 1940 }
1941 1941
1942 if (AR_SREV_9300_20_OR_LATER(ah)) { 1942 if (AR_SREV_9300_20_OR_LATER(ah)) {
1943 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC | 1943 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1944 ATH9K_HW_CAP_FASTCLOCK; 1944 if (!AR_SREV_9485(ah))
1945 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1946
1945 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 1947 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1946 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 1948 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1947 pCap->rx_status_len = sizeof(struct ar9003_rxs); 1949 pCap->rx_status_len = sizeof(struct ar9003_rxs);
@@ -1981,6 +1983,23 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1981 1983
1982 1984
1983 1985
1986 if (AR_SREV_9485_10(ah)) {
1987 pCap->pcie_lcr_extsync_en = true;
1988 pCap->pcie_lcr_offset = 0x80;
1989 }
1990
1991 tx_chainmask = pCap->tx_chainmask;
1992 rx_chainmask = pCap->rx_chainmask;
1993 while (tx_chainmask || rx_chainmask) {
1994 if (tx_chainmask & BIT(0))
1995 pCap->max_txchains++;
1996 if (rx_chainmask & BIT(0))
1997 pCap->max_rxchains++;
1998
1999 tx_chainmask >>= 1;
2000 rx_chainmask >>= 1;
2001 }
2002
1984 return 0; 2003 return 0;
1985} 2004}
1986 2005
@@ -2257,8 +2276,8 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
2257{ 2276{
2258 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2277 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2259 AH_TSF_WRITE_TIMEOUT)) 2278 AH_TSF_WRITE_TIMEOUT))
2260 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 2279 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2261 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2280 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2262 2281
2263 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2282 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2264} 2283}
@@ -2348,9 +2367,9 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2348 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2367 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2349 2368
2350 if (timer == NULL) { 2369 if (timer == NULL) {
2351 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2370 ath_err(ath9k_hw_common(ah),
2352 "Failed to allocate memory" 2371 "Failed to allocate memory for hw timer[%d]\n",
2353 "for hw timer[%d]\n", timer_index); 2372 timer_index);
2354 return NULL; 2373 return NULL;
2355 } 2374 }
2356 2375
@@ -2379,9 +2398,9 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2379 2398
2380 tsf = ath9k_hw_gettsf32(ah); 2399 tsf = ath9k_hw_gettsf32(ah);
2381 2400
2382 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2401 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2383 "curent tsf %x period %x" 2402 "current tsf %x period %x timer_next %x\n",
2384 "timer_next %x\n", tsf, timer_period, timer_next); 2403 tsf, timer_period, timer_next);
2385 2404
2386 /* 2405 /*
2387 * Pull timer_next forward if the current TSF already passed it 2406 * Pull timer_next forward if the current TSF already passed it
@@ -2461,8 +2480,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
2461 index = rightmost_index(timer_table, &thresh_mask); 2480 index = rightmost_index(timer_table, &thresh_mask);
2462 timer = timer_table->timers[index]; 2481 timer = timer_table->timers[index];
2463 BUG_ON(!timer); 2482 BUG_ON(!timer);
2464 ath_print(common, ATH_DBG_HWTIMER, 2483 ath_dbg(common, ATH_DBG_HWTIMER,
2465 "TSF overflow for Gen timer %d\n", index); 2484 "TSF overflow for Gen timer %d\n", index);
2466 timer->overflow(timer->arg); 2485 timer->overflow(timer->arg);
2467 } 2486 }
2468 2487
@@ -2470,8 +2489,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
2470 index = rightmost_index(timer_table, &trigger_mask); 2489 index = rightmost_index(timer_table, &trigger_mask);
2471 timer = timer_table->timers[index]; 2490 timer = timer_table->timers[index];
2472 BUG_ON(!timer); 2491 BUG_ON(!timer);
2473 ath_print(common, ATH_DBG_HWTIMER, 2492 ath_dbg(common, ATH_DBG_HWTIMER,
2474 "Gen timer[%d] trigger\n", index); 2493 "Gen timer[%d] trigger\n", index);
2475 timer->trigger(timer->arg); 2494 timer->trigger(timer->arg);
2476 } 2495 }
2477} 2496}
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 5fcfa48a45df..d83cc3b4685b 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -30,7 +30,6 @@
30#include "btcoex.h" 30#include "btcoex.h"
31 31
32#include "../regd.h" 32#include "../regd.h"
33#include "../debug.h"
34 33
35#define ATHEROS_VENDOR_ID 0x168c 34#define ATHEROS_VENDOR_ID 0x168c
36 35
@@ -44,6 +43,7 @@
44#define AR9287_DEVID_PCI 0x002d 43#define AR9287_DEVID_PCI 0x002d
45#define AR9287_DEVID_PCIE 0x002e 44#define AR9287_DEVID_PCIE 0x002e
46#define AR9300_DEVID_PCIE 0x0030 45#define AR9300_DEVID_PCIE 0x0030
46#define AR9300_DEVID_AR9485_PCIE 0x0032
47 47
48#define AR5416_AR9100_DEVID 0x000b 48#define AR5416_AR9100_DEVID 0x000b
49 49
@@ -199,6 +199,8 @@ struct ath9k_hw_capabilities {
199 u16 rts_aggr_limit; 199 u16 rts_aggr_limit;
200 u8 tx_chainmask; 200 u8 tx_chainmask;
201 u8 rx_chainmask; 201 u8 rx_chainmask;
202 u8 max_txchains;
203 u8 max_rxchains;
202 u16 tx_triglevel_max; 204 u16 tx_triglevel_max;
203 u16 reg_cap; 205 u16 reg_cap;
204 u8 num_gpio_pins; 206 u8 num_gpio_pins;
@@ -209,6 +211,8 @@ struct ath9k_hw_capabilities {
209 u8 rx_status_len; 211 u8 rx_status_len;
210 u8 tx_desc_len; 212 u8 tx_desc_len;
211 u8 txs_len; 213 u8 txs_len;
214 u16 pcie_lcr_offset;
215 bool pcie_lcr_extsync_en;
212}; 216};
213 217
214struct ath9k_ops_config { 218struct ath9k_ops_config {
@@ -442,6 +446,7 @@ struct ath9k_hw_version {
442 u16 analog5GhzRev; 446 u16 analog5GhzRev;
443 u16 analog2GhzRev; 447 u16 analog2GhzRev;
444 u16 subsysid; 448 u16 subsysid;
449 enum ath_usb_dev usbdev;
445}; 450};
446 451
447/* Generic TSF timer definitions */ 452/* Generic TSF timer definitions */
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 918308a28410..b2983ce19dfb 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -210,7 +210,9 @@ static void setup_ht_cap(struct ath_softc *sc,
210 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 210 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
211 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 211 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
212 212
213 if (AR_SREV_9300_20_OR_LATER(ah)) 213 if (AR_SREV_9485(ah))
214 max_streams = 1;
215 else if (AR_SREV_9300_20_OR_LATER(ah))
214 max_streams = 3; 216 max_streams = 3;
215 else 217 else
216 max_streams = 2; 218 max_streams = 2;
@@ -226,9 +228,9 @@ static void setup_ht_cap(struct ath_softc *sc,
226 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams); 228 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
227 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams); 229 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
228 230
229 ath_print(common, ATH_DBG_CONFIG, 231 ath_dbg(common, ATH_DBG_CONFIG,
230 "TX streams %d, RX streams: %d\n", 232 "TX streams %d, RX streams: %d\n",
231 tx_streams, rx_streams); 233 tx_streams, rx_streams);
232 234
233 if (tx_streams != rx_streams) { 235 if (tx_streams != rx_streams) {
234 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 236 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
@@ -271,8 +273,8 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
271 struct ath_buf *bf; 273 struct ath_buf *bf;
272 int i, bsize, error, desc_len; 274 int i, bsize, error, desc_len;
273 275
274 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", 276 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
275 name, nbuf, ndesc); 277 name, nbuf, ndesc);
276 278
277 INIT_LIST_HEAD(head); 279 INIT_LIST_HEAD(head);
278 280
@@ -283,8 +285,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
283 285
284 /* ath_desc must be a multiple of DWORDs */ 286 /* ath_desc must be a multiple of DWORDs */
285 if ((desc_len % 4) != 0) { 287 if ((desc_len % 4) != 0) {
286 ath_print(common, ATH_DBG_FATAL, 288 ath_err(common, "ath_desc not DWORD aligned\n");
287 "ath_desc not DWORD aligned\n");
288 BUG_ON((desc_len % 4) != 0); 289 BUG_ON((desc_len % 4) != 0);
289 error = -ENOMEM; 290 error = -ENOMEM;
290 goto fail; 291 goto fail;
@@ -318,9 +319,9 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
318 goto fail; 319 goto fail;
319 } 320 }
320 ds = (u8 *) dd->dd_desc; 321 ds = (u8 *) dd->dd_desc;
321 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 322 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
322 name, ds, (u32) dd->dd_desc_len, 323 name, ds, (u32) dd->dd_desc_len,
323 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 324 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
324 325
325 /* allocate buffers */ 326 /* allocate buffers */
326 bsize = sizeof(struct ath_buf) * nbuf; 327 bsize = sizeof(struct ath_buf) * nbuf;
@@ -374,9 +375,9 @@ static void ath9k_init_crypto(struct ath_softc *sc)
374 /* Get the hardware key cache size. */ 375 /* Get the hardware key cache size. */
375 common->keymax = sc->sc_ah->caps.keycache_size; 376 common->keymax = sc->sc_ah->caps.keycache_size;
376 if (common->keymax > ATH_KEYMAX) { 377 if (common->keymax > ATH_KEYMAX) {
377 ath_print(common, ATH_DBG_ANY, 378 ath_dbg(common, ATH_DBG_ANY,
378 "Warning, using only %u entries in %u key cache\n", 379 "Warning, using only %u entries in %u key cache\n",
379 ATH_KEYMAX, common->keymax); 380 ATH_KEYMAX, common->keymax);
380 common->keymax = ATH_KEYMAX; 381 common->keymax = ATH_KEYMAX;
381 } 382 }
382 383
@@ -641,7 +642,8 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
641 IEEE80211_HW_SUPPORTS_PS | 642 IEEE80211_HW_SUPPORTS_PS |
642 IEEE80211_HW_PS_NULLFUNC_STACK | 643 IEEE80211_HW_PS_NULLFUNC_STACK |
643 IEEE80211_HW_SPECTRUM_MGMT | 644 IEEE80211_HW_SPECTRUM_MGMT |
644 IEEE80211_HW_REPORTS_TX_ACK_STATUS; 645 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
646 IEEE80211_HW_NEED_DTIM_PERIOD;
645 647
646 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 648 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
647 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; 649 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
@@ -736,8 +738,7 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
736 738
737 error = ath9k_init_debug(ah); 739 error = ath9k_init_debug(ah);
738 if (error) { 740 if (error) {
739 ath_print(common, ATH_DBG_FATAL, 741 ath_err(common, "Unable to create debugfs files\n");
740 "Unable to create debugfs files\n");
741 goto error_world; 742 goto error_world;
742 } 743 }
743 744
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index b04b37b1124b..e3d2ebf00e2e 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -20,11 +20,11 @@
20static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, 20static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
21 struct ath9k_tx_queue_info *qi) 21 struct ath9k_tx_queue_info *qi)
22{ 22{
23 ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT, 23 ath_dbg(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
24 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", 24 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
25 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, 25 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
26 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, 26 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
27 ah->txurn_interrupt_mask); 27 ah->txurn_interrupt_mask);
28 28
29 ENABLE_REGWRITE_BUFFER(ah); 29 ENABLE_REGWRITE_BUFFER(ah);
30 30
@@ -56,8 +56,8 @@ EXPORT_SYMBOL(ath9k_hw_puttxbuf);
56 56
57void ath9k_hw_txstart(struct ath_hw *ah, u32 q) 57void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
58{ 58{
59 ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE, 59 ath_dbg(ath9k_hw_common(ah), ATH_DBG_QUEUE,
60 "Enable TXE on queue: %u\n", q); 60 "Enable TXE on queue: %u\n", q);
61 REG_WRITE(ah, AR_Q_TXE, 1 << q); 61 REG_WRITE(ah, AR_Q_TXE, 1 << q);
62} 62}
63EXPORT_SYMBOL(ath9k_hw_txstart); 63EXPORT_SYMBOL(ath9k_hw_txstart);
@@ -154,15 +154,15 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
154 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; 154 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
155 155
156 if (q >= pCap->total_queues) { 156 if (q >= pCap->total_queues) {
157 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, " 157 ath_dbg(common, ATH_DBG_QUEUE,
158 "invalid queue: %u\n", q); 158 "Stopping TX DMA, invalid queue: %u\n", q);
159 return false; 159 return false;
160 } 160 }
161 161
162 qi = &ah->txq[q]; 162 qi = &ah->txq[q];
163 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 163 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
164 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, " 164 ath_dbg(common, ATH_DBG_QUEUE,
165 "inactive queue: %u\n", q); 165 "Stopping TX DMA, inactive queue: %u\n", q);
166 return false; 166 return false;
167 } 167 }
168 168
@@ -175,9 +175,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
175 } 175 }
176 176
177 if (ath9k_hw_numtxpending(ah, q)) { 177 if (ath9k_hw_numtxpending(ah, q)) {
178 ath_print(common, ATH_DBG_QUEUE, 178 ath_dbg(common, ATH_DBG_QUEUE,
179 "%s: Num of pending TX Frames %d on Q %d\n", 179 "%s: Num of pending TX Frames %d on Q %d\n",
180 __func__, ath9k_hw_numtxpending(ah, q), q); 180 __func__, ath9k_hw_numtxpending(ah, q), q);
181 181
182 for (j = 0; j < 2; j++) { 182 for (j = 0; j < 2; j++) {
183 tsfLow = REG_READ(ah, AR_TSF_L32); 183 tsfLow = REG_READ(ah, AR_TSF_L32);
@@ -191,9 +191,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
191 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) 191 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
192 break; 192 break;
193 193
194 ath_print(common, ATH_DBG_QUEUE, 194 ath_dbg(common, ATH_DBG_QUEUE,
195 "TSF has moved while trying to set " 195 "TSF has moved while trying to set quiet time TSF: 0x%08x\n",
196 "quiet time TSF: 0x%08x\n", tsfLow); 196 tsfLow);
197 } 197 }
198 198
199 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 199 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
@@ -204,9 +204,8 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
204 wait = wait_time; 204 wait = wait_time;
205 while (ath9k_hw_numtxpending(ah, q)) { 205 while (ath9k_hw_numtxpending(ah, q)) {
206 if ((--wait) == 0) { 206 if ((--wait) == 0) {
207 ath_print(common, ATH_DBG_FATAL, 207 ath_err(common,
208 "Failed to stop TX DMA in 100 " 208 "Failed to stop TX DMA in 100 msec after killing last frame\n");
209 "msec after killing last frame\n");
210 break; 209 break;
211 } 210 }
212 udelay(ATH9K_TIME_QUANTUM); 211 udelay(ATH9K_TIME_QUANTUM);
@@ -239,19 +238,19 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
239 struct ath9k_tx_queue_info *qi; 238 struct ath9k_tx_queue_info *qi;
240 239
241 if (q >= pCap->total_queues) { 240 if (q >= pCap->total_queues) {
242 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, " 241 ath_dbg(common, ATH_DBG_QUEUE,
243 "invalid queue: %u\n", q); 242 "Set TXQ properties, invalid queue: %u\n", q);
244 return false; 243 return false;
245 } 244 }
246 245
247 qi = &ah->txq[q]; 246 qi = &ah->txq[q];
248 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 247 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
249 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, " 248 ath_dbg(common, ATH_DBG_QUEUE,
250 "inactive queue: %u\n", q); 249 "Set TXQ properties, inactive queue: %u\n", q);
251 return false; 250 return false;
252 } 251 }
253 252
254 ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q); 253 ath_dbg(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
255 254
256 qi->tqi_ver = qinfo->tqi_ver; 255 qi->tqi_ver = qinfo->tqi_ver;
257 qi->tqi_subtype = qinfo->tqi_subtype; 256 qi->tqi_subtype = qinfo->tqi_subtype;
@@ -310,15 +309,15 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
310 struct ath9k_tx_queue_info *qi; 309 struct ath9k_tx_queue_info *qi;
311 310
312 if (q >= pCap->total_queues) { 311 if (q >= pCap->total_queues) {
313 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, " 312 ath_dbg(common, ATH_DBG_QUEUE,
314 "invalid queue: %u\n", q); 313 "Get TXQ properties, invalid queue: %u\n", q);
315 return false; 314 return false;
316 } 315 }
317 316
318 qi = &ah->txq[q]; 317 qi = &ah->txq[q];
319 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 318 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
320 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, " 319 ath_dbg(common, ATH_DBG_QUEUE,
321 "inactive queue: %u\n", q); 320 "Get TXQ properties, inactive queue: %u\n", q);
322 return false; 321 return false;
323 } 322 }
324 323
@@ -368,23 +367,20 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
368 ATH9K_TX_QUEUE_INACTIVE) 367 ATH9K_TX_QUEUE_INACTIVE)
369 break; 368 break;
370 if (q == pCap->total_queues) { 369 if (q == pCap->total_queues) {
371 ath_print(common, ATH_DBG_FATAL, 370 ath_err(common, "No available TX queue\n");
372 "No available TX queue\n");
373 return -1; 371 return -1;
374 } 372 }
375 break; 373 break;
376 default: 374 default:
377 ath_print(common, ATH_DBG_FATAL, 375 ath_err(common, "Invalid TX queue type: %u\n", type);
378 "Invalid TX queue type: %u\n", type);
379 return -1; 376 return -1;
380 } 377 }
381 378
382 ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q); 379 ath_dbg(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
383 380
384 qi = &ah->txq[q]; 381 qi = &ah->txq[q];
385 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 382 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
386 ath_print(common, ATH_DBG_FATAL, 383 ath_err(common, "TX queue: %u already active\n", q);
387 "TX queue: %u already active\n", q);
388 return -1; 384 return -1;
389 } 385 }
390 memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); 386 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -416,18 +412,18 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
416 struct ath9k_tx_queue_info *qi; 412 struct ath9k_tx_queue_info *qi;
417 413
418 if (q >= pCap->total_queues) { 414 if (q >= pCap->total_queues) {
419 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, " 415 ath_dbg(common, ATH_DBG_QUEUE,
420 "invalid queue: %u\n", q); 416 "Release TXQ, invalid queue: %u\n", q);
421 return false; 417 return false;
422 } 418 }
423 qi = &ah->txq[q]; 419 qi = &ah->txq[q];
424 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 420 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
425 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, " 421 ath_dbg(common, ATH_DBG_QUEUE,
426 "inactive queue: %u\n", q); 422 "Release TXQ, inactive queue: %u\n", q);
427 return false; 423 return false;
428 } 424 }
429 425
430 ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q); 426 ath_dbg(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
431 427
432 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 428 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
433 ah->txok_interrupt_mask &= ~(1 << q); 429 ah->txok_interrupt_mask &= ~(1 << q);
@@ -450,19 +446,19 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
450 u32 cwMin, chanCwMin, value; 446 u32 cwMin, chanCwMin, value;
451 447
452 if (q >= pCap->total_queues) { 448 if (q >= pCap->total_queues) {
453 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, " 449 ath_dbg(common, ATH_DBG_QUEUE,
454 "invalid queue: %u\n", q); 450 "Reset TXQ, invalid queue: %u\n", q);
455 return false; 451 return false;
456 } 452 }
457 453
458 qi = &ah->txq[q]; 454 qi = &ah->txq[q];
459 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 455 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
460 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, " 456 ath_dbg(common, ATH_DBG_QUEUE,
461 "inactive queue: %u\n", q); 457 "Reset TXQ, inactive queue: %u\n", q);
462 return true; 458 return true;
463 } 459 }
464 460
465 ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q); 461 ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
466 462
467 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { 463 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
468 if (chan && IS_CHAN_B(chan)) 464 if (chan && IS_CHAN_B(chan))
@@ -702,8 +698,7 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
702 rs->rs_phyerr = phyerr; 698 rs->rs_phyerr = phyerr;
703 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr) 699 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
704 rs->rs_status |= ATH9K_RXERR_DECRYPT; 700 rs->rs_status |= ATH9K_RXERR_DECRYPT;
705 else if ((ads.ds_rxstatus8 & AR_MichaelErr) && 701 else if (ads.ds_rxstatus8 & AR_MichaelErr)
706 rs->rs_keyix != ATH9K_RXKEYIX_INVALID)
707 rs->rs_status |= ATH9K_RXERR_MIC; 702 rs->rs_status |= ATH9K_RXERR_MIC;
708 else if (ads.ds_rxstatus8 & AR_KeyMiss) 703 else if (ads.ds_rxstatus8 & AR_KeyMiss)
709 rs->rs_status |= ATH9K_RXERR_DECRYPT; 704 rs->rs_status |= ATH9K_RXERR_DECRYPT;
@@ -735,9 +730,9 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
735 AR_DIAG_RX_ABORT)); 730 AR_DIAG_RX_ABORT));
736 731
737 reg = REG_READ(ah, AR_OBS_BUS_1); 732 reg = REG_READ(ah, AR_OBS_BUS_1);
738 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 733 ath_err(ath9k_hw_common(ah),
739 "RX failed to go idle in 10 ms RXSM=0x%x\n", 734 "RX failed to go idle in 10 ms RXSM=0x%x\n",
740 reg); 735 reg);
741 736
742 return false; 737 return false;
743 } 738 }
@@ -791,12 +786,11 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
791 } 786 }
792 787
793 if (i == 0) { 788 if (i == 0) {
794 ath_print(common, ATH_DBG_FATAL, 789 ath_err(common,
795 "DMA failed to stop in %d ms " 790 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
796 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", 791 AH_RX_STOP_DMA_TIMEOUT / 1000,
797 AH_RX_STOP_DMA_TIMEOUT / 1000, 792 REG_READ(ah, AR_CR),
798 REG_READ(ah, AR_CR), 793 REG_READ(ah, AR_DIAG_SW));
799 REG_READ(ah, AR_DIAG_SW));
800 return false; 794 return false;
801 } else { 795 } else {
802 return true; 796 return true;
@@ -844,7 +838,7 @@ void ath9k_hw_disable_interrupts(struct ath_hw *ah)
844{ 838{
845 struct ath_common *common = ath9k_hw_common(ah); 839 struct ath_common *common = ath9k_hw_common(ah);
846 840
847 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n"); 841 ath_dbg(common, ATH_DBG_INTERRUPT, "disable IER\n");
848 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 842 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
849 (void) REG_READ(ah, AR_IER); 843 (void) REG_READ(ah, AR_IER);
850 if (!AR_SREV_9100(ah)) { 844 if (!AR_SREV_9100(ah)) {
@@ -864,7 +858,7 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
864 if (!(ah->imask & ATH9K_INT_GLOBAL)) 858 if (!(ah->imask & ATH9K_INT_GLOBAL))
865 return; 859 return;
866 860
867 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n"); 861 ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
868 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 862 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
869 if (!AR_SREV_9100(ah)) { 863 if (!AR_SREV_9100(ah)) {
870 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 864 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
@@ -877,8 +871,8 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
877 REG_WRITE(ah, AR_INTR_SYNC_MASK, 871 REG_WRITE(ah, AR_INTR_SYNC_MASK,
878 AR_INTR_SYNC_DEFAULT); 872 AR_INTR_SYNC_DEFAULT);
879 } 873 }
880 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", 874 ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
881 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); 875 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
882} 876}
883EXPORT_SYMBOL(ath9k_hw_enable_interrupts); 877EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
884 878
@@ -892,7 +886,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
892 if (!(ints & ATH9K_INT_GLOBAL)) 886 if (!(ints & ATH9K_INT_GLOBAL))
893 ath9k_hw_enable_interrupts(ah); 887 ath9k_hw_enable_interrupts(ah);
894 888
895 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 889 ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
896 890
897 /* TODO: global int Ref count */ 891 /* TODO: global int Ref count */
898 mask = ints & ATH9K_INT_COMMON; 892 mask = ints & ATH9K_INT_COMMON;
@@ -953,7 +947,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
953 mask2 |= AR_IMR_S2_CST; 947 mask2 |= AR_IMR_S2_CST;
954 } 948 }
955 949
956 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); 950 ath_dbg(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
957 REG_WRITE(ah, AR_IMR, mask); 951 REG_WRITE(ah, AR_IMR, mask);
958 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | 952 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
959 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | 953 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index f026a031713b..daa3c9feca66 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -246,9 +246,10 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
246 * the relevant bits of the h/w. 246 * the relevant bits of the h/w.
247 */ 247 */
248 ath9k_hw_disable_interrupts(ah); 248 ath9k_hw_disable_interrupts(ah);
249 ath_drain_all_txq(sc, false); 249 stopped = ath_drain_all_txq(sc, false);
250 250
251 stopped = ath_stoprecv(sc); 251 if (!ath_stoprecv(sc))
252 stopped = false;
252 253
253 /* XXX: do not flush receive queue here. We don't want 254 /* XXX: do not flush receive queue here. We don't want
254 * to flush data frames already in queue because of 255 * to flush data frames already in queue because of
@@ -260,24 +261,22 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
260 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) 261 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
261 caldata = &aphy->caldata; 262 caldata = &aphy->caldata;
262 263
263 ath_print(common, ATH_DBG_CONFIG, 264 ath_dbg(common, ATH_DBG_CONFIG,
264 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", 265 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
265 sc->sc_ah->curchan->channel, 266 sc->sc_ah->curchan->channel,
266 channel->center_freq, conf_is_ht40(conf), 267 channel->center_freq, conf_is_ht40(conf),
267 fastcc); 268 fastcc);
268 269
269 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 270 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
270 if (r) { 271 if (r) {
271 ath_print(common, ATH_DBG_FATAL, 272 ath_err(common,
272 "Unable to reset channel (%u MHz), " 273 "Unable to reset channel (%u MHz), reset status %d\n",
273 "reset status %d\n", 274 channel->center_freq, r);
274 channel->center_freq, r);
275 goto ps_restore; 275 goto ps_restore;
276 } 276 }
277 277
278 if (ath_startrecv(sc) != 0) { 278 if (ath_startrecv(sc) != 0) {
279 ath_print(common, ATH_DBG_FATAL, 279 ath_err(common, "Unable to restart recv logic\n");
280 "Unable to restart recv logic\n");
281 r = -EIO; 280 r = -EIO;
282 goto ps_restore; 281 goto ps_restore;
283 } 282 }
@@ -389,10 +388,9 @@ void ath_paprd_calibrate(struct work_struct *work)
389 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); 388 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
390 sc->paprd_pending = false; 389 sc->paprd_pending = false;
391 if (!time_left) { 390 if (!time_left) {
392 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, 391 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
393 "Timeout waiting for paprd training on " 392 "Timeout waiting for paprd training on TX chain %d\n",
394 "TX chain %d\n", 393 chain);
395 chain);
396 goto fail_paprd; 394 goto fail_paprd;
397 } 395 }
398 396
@@ -451,7 +449,7 @@ void ath_ani_calibrate(unsigned long data)
451 /* Long calibration runs independently of short calibration. */ 449 /* Long calibration runs independently of short calibration. */
452 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { 450 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
453 longcal = true; 451 longcal = true;
454 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); 452 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
455 common->ani.longcal_timer = timestamp; 453 common->ani.longcal_timer = timestamp;
456 } 454 }
457 455
@@ -459,8 +457,8 @@ void ath_ani_calibrate(unsigned long data)
459 if (!common->ani.caldone) { 457 if (!common->ani.caldone) {
460 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { 458 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
461 shortcal = true; 459 shortcal = true;
462 ath_print(common, ATH_DBG_ANI, 460 ath_dbg(common, ATH_DBG_ANI,
463 "shortcal @%lu\n", jiffies); 461 "shortcal @%lu\n", jiffies);
464 common->ani.shortcal_timer = timestamp; 462 common->ani.shortcal_timer = timestamp;
465 common->ani.resetcal_timer = timestamp; 463 common->ani.resetcal_timer = timestamp;
466 } 464 }
@@ -544,10 +542,10 @@ void ath_update_chainmask(struct ath_softc *sc, int is_ht)
544 common->rx_chainmask = 1; 542 common->rx_chainmask = 1;
545 } 543 }
546 544
547 ath_print(common, ATH_DBG_CONFIG, 545 ath_dbg(common, ATH_DBG_CONFIG,
548 "tx chmask: %d, rx chmask: %d\n", 546 "tx chmask: %d, rx chmask: %d\n",
549 common->tx_chainmask, 547 common->tx_chainmask,
550 common->rx_chainmask); 548 common->rx_chainmask);
551} 549}
552 550
553static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) 551static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
@@ -643,8 +641,8 @@ void ath9k_tasklet(unsigned long data)
643 * TSF sync does not look correct; remain awake to sync with 641 * TSF sync does not look correct; remain awake to sync with
644 * the next Beacon. 642 * the next Beacon.
645 */ 643 */
646 ath_print(common, ATH_DBG_PS, 644 ath_dbg(common, ATH_DBG_PS,
647 "TSFOOR - Sync with next Beacon\n"); 645 "TSFOOR - Sync with next Beacon\n");
648 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 646 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
649 } 647 }
650 648
@@ -768,6 +766,8 @@ irqreturn_t ath_isr(int irq, void *dev)
768 766
769 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 767 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
770 if (status & ATH9K_INT_TIM_TIMER) { 768 if (status & ATH9K_INT_TIM_TIMER) {
769 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
770 goto chip_reset;
771 /* Clear RxAbort bit so that we can 771 /* Clear RxAbort bit so that we can
772 * receive frames */ 772 * receive frames */
773 ath9k_setpower(sc, ATH9K_PM_AWAKE); 773 ath9k_setpower(sc, ATH9K_PM_AWAKE);
@@ -842,9 +842,9 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
842 struct ath_common *common = ath9k_hw_common(ah); 842 struct ath_common *common = ath9k_hw_common(ah);
843 843
844 if (bss_conf->assoc) { 844 if (bss_conf->assoc) {
845 ath_print(common, ATH_DBG_CONFIG, 845 ath_dbg(common, ATH_DBG_CONFIG,
846 "Bss Info ASSOC %d, bssid: %pM\n", 846 "Bss Info ASSOC %d, bssid: %pM\n",
847 bss_conf->aid, common->curbssid); 847 bss_conf->aid, common->curbssid);
848 848
849 /* New association, store aid */ 849 /* New association, store aid */
850 common->curaid = bss_conf->aid; 850 common->curaid = bss_conf->aid;
@@ -867,7 +867,7 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
867 sc->sc_flags |= SC_OP_ANI_RUN; 867 sc->sc_flags |= SC_OP_ANI_RUN;
868 ath_start_ani(common); 868 ath_start_ani(common);
869 } else { 869 } else {
870 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); 870 ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
871 common->curaid = 0; 871 common->curaid = 0;
872 /* Stop ANI */ 872 /* Stop ANI */
873 sc->sc_flags &= ~SC_OP_ANI_RUN; 873 sc->sc_flags &= ~SC_OP_ANI_RUN;
@@ -892,16 +892,14 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
892 892
893 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 893 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
894 if (r) { 894 if (r) {
895 ath_print(common, ATH_DBG_FATAL, 895 ath_err(common,
896 "Unable to reset channel (%u MHz), " 896 "Unable to reset channel (%u MHz), reset status %d\n",
897 "reset status %d\n", 897 channel->center_freq, r);
898 channel->center_freq, r);
899 } 898 }
900 899
901 ath_update_txpow(sc); 900 ath_update_txpow(sc);
902 if (ath_startrecv(sc) != 0) { 901 if (ath_startrecv(sc) != 0) {
903 ath_print(common, ATH_DBG_FATAL, 902 ath_err(common, "Unable to restart recv logic\n");
904 "Unable to restart recv logic\n");
905 spin_unlock_bh(&sc->sc_pcu_lock); 903 spin_unlock_bh(&sc->sc_pcu_lock);
906 return; 904 return;
907 } 905 }
@@ -955,10 +953,9 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
955 953
956 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 954 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
957 if (r) { 955 if (r) {
958 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, 956 ath_err(ath9k_hw_common(sc->sc_ah),
959 "Unable to reset channel (%u MHz), " 957 "Unable to reset channel (%u MHz), reset status %d\n",
960 "reset status %d\n", 958 channel->center_freq, r);
961 channel->center_freq, r);
962 } 959 }
963 960
964 ath9k_hw_phy_disable(ah); 961 ath9k_hw_phy_disable(ah);
@@ -993,12 +990,11 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
993 990
994 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); 991 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
995 if (r) 992 if (r)
996 ath_print(common, ATH_DBG_FATAL, 993 ath_err(common,
997 "Unable to reset hardware; reset status %d\n", r); 994 "Unable to reset hardware; reset status %d\n", r);
998 995
999 if (ath_startrecv(sc) != 0) 996 if (ath_startrecv(sc) != 0)
1000 ath_print(common, ATH_DBG_FATAL, 997 ath_err(common, "Unable to start recv logic\n");
1001 "Unable to start recv logic\n");
1002 998
1003 /* 999 /*
1004 * We may be doing a reset in response to a request 1000 * We may be doing a reset in response to a request
@@ -1070,9 +1066,9 @@ static int ath9k_start(struct ieee80211_hw *hw)
1070 struct ath9k_channel *init_channel; 1066 struct ath9k_channel *init_channel;
1071 int r; 1067 int r;
1072 1068
1073 ath_print(common, ATH_DBG_CONFIG, 1069 ath_dbg(common, ATH_DBG_CONFIG,
1074 "Starting driver with initial channel: %d MHz\n", 1070 "Starting driver with initial channel: %d MHz\n",
1075 curchan->center_freq); 1071 curchan->center_freq);
1076 1072
1077 mutex_lock(&sc->mutex); 1073 mutex_lock(&sc->mutex);
1078 1074
@@ -1116,10 +1112,9 @@ static int ath9k_start(struct ieee80211_hw *hw)
1116 spin_lock_bh(&sc->sc_pcu_lock); 1112 spin_lock_bh(&sc->sc_pcu_lock);
1117 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 1113 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
1118 if (r) { 1114 if (r) {
1119 ath_print(common, ATH_DBG_FATAL, 1115 ath_err(common,
1120 "Unable to reset hardware; reset status %d " 1116 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1121 "(freq %u MHz)\n", r, 1117 r, curchan->center_freq);
1122 curchan->center_freq);
1123 spin_unlock_bh(&sc->sc_pcu_lock); 1118 spin_unlock_bh(&sc->sc_pcu_lock);
1124 goto mutex_unlock; 1119 goto mutex_unlock;
1125 } 1120 }
@@ -1138,8 +1133,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1138 * here except setup the interrupt mask. 1133 * here except setup the interrupt mask.
1139 */ 1134 */
1140 if (ath_startrecv(sc) != 0) { 1135 if (ath_startrecv(sc) != 0) {
1141 ath_print(common, ATH_DBG_FATAL, 1136 ath_err(common, "Unable to start recv logic\n");
1142 "Unable to start recv logic\n");
1143 r = -EIO; 1137 r = -EIO;
1144 spin_unlock_bh(&sc->sc_pcu_lock); 1138 spin_unlock_bh(&sc->sc_pcu_lock);
1145 goto mutex_unlock; 1139 goto mutex_unlock;
@@ -1188,6 +1182,9 @@ static int ath9k_start(struct ieee80211_hw *hw)
1188 1182
1189 pm_qos_update_request(&sc->pm_qos_req, 55); 1183 pm_qos_update_request(&sc->pm_qos_req, 55);
1190 1184
1185 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1186 common->bus_ops->extn_synch_en(common);
1187
1191mutex_unlock: 1188mutex_unlock:
1192 mutex_unlock(&sc->mutex); 1189 mutex_unlock(&sc->mutex);
1193 1190
@@ -1204,9 +1201,9 @@ static int ath9k_tx(struct ieee80211_hw *hw,
1204 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1201 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1205 1202
1206 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { 1203 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
1207 ath_print(common, ATH_DBG_XMIT, 1204 ath_dbg(common, ATH_DBG_XMIT,
1208 "ath9k: %s: TX in unexpected wiphy state " 1205 "ath9k: %s: TX in unexpected wiphy state %d\n",
1209 "%d\n", wiphy_name(hw->wiphy), aphy->state); 1206 wiphy_name(hw->wiphy), aphy->state);
1210 goto exit; 1207 goto exit;
1211 } 1208 }
1212 1209
@@ -1218,8 +1215,8 @@ static int ath9k_tx(struct ieee80211_hw *hw,
1218 if (ieee80211_is_data(hdr->frame_control) && 1215 if (ieee80211_is_data(hdr->frame_control) &&
1219 !ieee80211_is_nullfunc(hdr->frame_control) && 1216 !ieee80211_is_nullfunc(hdr->frame_control) &&
1220 !ieee80211_has_pm(hdr->frame_control)) { 1217 !ieee80211_has_pm(hdr->frame_control)) {
1221 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " 1218 ath_dbg(common, ATH_DBG_PS,
1222 "while in PS mode\n"); 1219 "Add PM=1 for a TX frame while in PS mode\n");
1223 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1220 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1224 } 1221 }
1225 } 1222 }
@@ -1234,12 +1231,12 @@ static int ath9k_tx(struct ieee80211_hw *hw,
1234 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 1231 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1235 ath9k_hw_setrxabort(sc->sc_ah, 0); 1232 ath9k_hw_setrxabort(sc->sc_ah, 0);
1236 if (ieee80211_is_pspoll(hdr->frame_control)) { 1233 if (ieee80211_is_pspoll(hdr->frame_control)) {
1237 ath_print(common, ATH_DBG_PS, 1234 ath_dbg(common, ATH_DBG_PS,
1238 "Sending PS-Poll to pick a buffered frame\n"); 1235 "Sending PS-Poll to pick a buffered frame\n");
1239 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 1236 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
1240 } else { 1237 } else {
1241 ath_print(common, ATH_DBG_PS, 1238 ath_dbg(common, ATH_DBG_PS,
1242 "Wake up to complete TX\n"); 1239 "Wake up to complete TX\n");
1243 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 1240 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
1244 } 1241 }
1245 /* 1242 /*
@@ -1253,10 +1250,10 @@ static int ath9k_tx(struct ieee80211_hw *hw,
1253 memset(&txctl, 0, sizeof(struct ath_tx_control)); 1250 memset(&txctl, 0, sizeof(struct ath_tx_control));
1254 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 1251 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
1255 1252
1256 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); 1253 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
1257 1254
1258 if (ath_tx_start(hw, skb, &txctl) != 0) { 1255 if (ath_tx_start(hw, skb, &txctl) != 0) {
1259 ath_print(common, ATH_DBG_XMIT, "TX failed\n"); 1256 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
1260 goto exit; 1257 goto exit;
1261 } 1258 }
1262 1259
@@ -1296,7 +1293,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
1296 } 1293 }
1297 1294
1298 if (sc->sc_flags & SC_OP_INVALID) { 1295 if (sc->sc_flags & SC_OP_INVALID) {
1299 ath_print(common, ATH_DBG_ANY, "Device not present\n"); 1296 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
1300 mutex_unlock(&sc->mutex); 1297 mutex_unlock(&sc->mutex);
1301 return; 1298 return;
1302 } 1299 }
@@ -1345,7 +1342,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
1345 1342
1346 mutex_unlock(&sc->mutex); 1343 mutex_unlock(&sc->mutex);
1347 1344
1348 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); 1345 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
1349} 1346}
1350 1347
1351static int ath9k_add_interface(struct ieee80211_hw *hw, 1348static int ath9k_add_interface(struct ieee80211_hw *hw,
@@ -1378,14 +1375,14 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
1378 ic_opmode = vif->type; 1375 ic_opmode = vif->type;
1379 break; 1376 break;
1380 default: 1377 default:
1381 ath_print(common, ATH_DBG_FATAL, 1378 ath_err(common, "Interface type %d not yet supported\n",
1382 "Interface type %d not yet supported\n", vif->type); 1379 vif->type);
1383 ret = -EOPNOTSUPP; 1380 ret = -EOPNOTSUPP;
1384 goto out; 1381 goto out;
1385 } 1382 }
1386 1383
1387 ath_print(common, ATH_DBG_CONFIG, 1384 ath_dbg(common, ATH_DBG_CONFIG,
1388 "Attach a VIF of type: %d\n", ic_opmode); 1385 "Attach a VIF of type: %d\n", ic_opmode);
1389 1386
1390 /* Set the VIF opmode */ 1387 /* Set the VIF opmode */
1391 avp->av_opmode = ic_opmode; 1388 avp->av_opmode = ic_opmode;
@@ -1438,10 +1435,8 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
1438 struct ath_softc *sc = aphy->sc; 1435 struct ath_softc *sc = aphy->sc;
1439 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1436 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1440 struct ath_vif *avp = (void *)vif->drv_priv; 1437 struct ath_vif *avp = (void *)vif->drv_priv;
1441 bool bs_valid = false;
1442 int i;
1443 1438
1444 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); 1439 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
1445 1440
1446 mutex_lock(&sc->mutex); 1441 mutex_lock(&sc->mutex);
1447 1442
@@ -1453,26 +1448,21 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
1453 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || 1448 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
1454 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || 1449 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
1455 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { 1450 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
1451 /* Disable SWBA interrupt */
1452 sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
1456 ath9k_ps_wakeup(sc); 1453 ath9k_ps_wakeup(sc);
1454 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
1457 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1455 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1458 ath9k_ps_restore(sc); 1456 ath9k_ps_restore(sc);
1457 tasklet_kill(&sc->bcon_tasklet);
1459 } 1458 }
1460 1459
1461 ath_beacon_return(sc, avp); 1460 ath_beacon_return(sc, avp);
1462 sc->sc_flags &= ~SC_OP_BEACONS; 1461 sc->sc_flags &= ~SC_OP_BEACONS;
1463 1462
1464 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { 1463 if (sc->nbcnvifs) {
1465 if (sc->beacon.bslot[i] == vif) { 1464 /* Re-enable SWBA interrupt */
1466 printk(KERN_DEBUG "%s: vif had allocated beacon " 1465 sc->sc_ah->imask |= ATH9K_INT_SWBA;
1467 "slot\n", __func__);
1468 sc->beacon.bslot[i] = NULL;
1469 sc->beacon.bslot_aphy[i] = NULL;
1470 } else if (sc->beacon.bslot[i])
1471 bs_valid = true;
1472 }
1473 if (!bs_valid && (sc->sc_ah->imask & ATH9K_INT_SWBA)) {
1474 /* Disable SWBA interrupt */
1475 sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
1476 ath9k_ps_wakeup(sc); 1466 ath9k_ps_wakeup(sc);
1477 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask); 1467 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
1478 ath9k_ps_restore(sc); 1468 ath9k_ps_restore(sc);
@@ -1556,8 +1546,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1556 if (enable_radio) { 1546 if (enable_radio) {
1557 sc->ps_idle = false; 1547 sc->ps_idle = false;
1558 ath_radio_enable(sc, hw); 1548 ath_radio_enable(sc, hw);
1559 ath_print(common, ATH_DBG_CONFIG, 1549 ath_dbg(common, ATH_DBG_CONFIG,
1560 "not-idle: enabling radio\n"); 1550 "not-idle: enabling radio\n");
1561 } 1551 }
1562 } 1552 }
1563 1553
@@ -1579,12 +1569,12 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1579 1569
1580 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1570 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1581 if (conf->flags & IEEE80211_CONF_MONITOR) { 1571 if (conf->flags & IEEE80211_CONF_MONITOR) {
1582 ath_print(common, ATH_DBG_CONFIG, 1572 ath_dbg(common, ATH_DBG_CONFIG,
1583 "Monitor mode is enabled\n"); 1573 "Monitor mode is enabled\n");
1584 sc->sc_ah->is_monitoring = true; 1574 sc->sc_ah->is_monitoring = true;
1585 } else { 1575 } else {
1586 ath_print(common, ATH_DBG_CONFIG, 1576 ath_dbg(common, ATH_DBG_CONFIG,
1587 "Monitor mode is disabled\n"); 1577 "Monitor mode is disabled\n");
1588 sc->sc_ah->is_monitoring = false; 1578 sc->sc_ah->is_monitoring = false;
1589 } 1579 }
1590 } 1580 }
@@ -1616,8 +1606,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1616 goto skip_chan_change; 1606 goto skip_chan_change;
1617 } 1607 }
1618 1608
1619 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", 1609 ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1620 curchan->center_freq); 1610 curchan->center_freq);
1621 1611
1622 /* XXX: remove me eventualy */ 1612 /* XXX: remove me eventualy */
1623 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); 1613 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
@@ -1650,8 +1640,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1650 } 1640 }
1651 1641
1652 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1642 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1653 ath_print(common, ATH_DBG_FATAL, 1643 ath_err(common, "Unable to set channel\n");
1654 "Unable to set channel\n");
1655 mutex_unlock(&sc->mutex); 1644 mutex_unlock(&sc->mutex);
1656 return -EINVAL; 1645 return -EINVAL;
1657 } 1646 }
@@ -1676,7 +1665,7 @@ skip_chan_change:
1676 spin_unlock_bh(&sc->wiphy_lock); 1665 spin_unlock_bh(&sc->wiphy_lock);
1677 1666
1678 if (disable_radio) { 1667 if (disable_radio) {
1679 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); 1668 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1680 sc->ps_idle = true; 1669 sc->ps_idle = true;
1681 ath_radio_disable(sc, hw); 1670 ath_radio_disable(sc, hw);
1682 } 1671 }
@@ -1715,8 +1704,8 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
1715 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1704 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1716 ath9k_ps_restore(sc); 1705 ath9k_ps_restore(sc);
1717 1706
1718 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, 1707 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1719 "Set HW RX filter: 0x%x\n", rfilt); 1708 "Set HW RX filter: 0x%x\n", rfilt);
1720} 1709}
1721 1710
1722static int ath9k_sta_add(struct ieee80211_hw *hw, 1711static int ath9k_sta_add(struct ieee80211_hw *hw,
@@ -1767,15 +1756,14 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
1767 qi.tqi_cwmax = params->cw_max; 1756 qi.tqi_cwmax = params->cw_max;
1768 qi.tqi_burstTime = params->txop; 1757 qi.tqi_burstTime = params->txop;
1769 1758
1770 ath_print(common, ATH_DBG_CONFIG, 1759 ath_dbg(common, ATH_DBG_CONFIG,
1771 "Configure tx [queue/halq] [%d/%d], " 1760 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1772 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1761 queue, txq->axq_qnum, params->aifs, params->cw_min,
1773 queue, txq->axq_qnum, params->aifs, params->cw_min, 1762 params->cw_max, params->txop);
1774 params->cw_max, params->txop);
1775 1763
1776 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1764 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1777 if (ret) 1765 if (ret)
1778 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); 1766 ath_err(common, "TXQ Update failed\n");
1779 1767
1780 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) 1768 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1781 if (queue == WME_AC_BE && !ret) 1769 if (queue == WME_AC_BE && !ret)
@@ -1802,7 +1790,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
1802 1790
1803 mutex_lock(&sc->mutex); 1791 mutex_lock(&sc->mutex);
1804 ath9k_ps_wakeup(sc); 1792 ath9k_ps_wakeup(sc);
1805 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); 1793 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
1806 1794
1807 switch (cmd) { 1795 switch (cmd) {
1808 case SET_KEY: 1796 case SET_KEY:
@@ -1861,9 +1849,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1861 if (vif->type == NL80211_IFTYPE_ADHOC) 1849 if (vif->type == NL80211_IFTYPE_ADHOC)
1862 ath_update_chainmask(sc, 0); 1850 ath_update_chainmask(sc, 0);
1863 1851
1864 ath_print(common, ATH_DBG_CONFIG, 1852 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
1865 "BSSID: %pM aid: 0x%x\n", 1853 common->curbssid, common->curaid);
1866 common->curbssid, common->curaid);
1867 1854
1868 /* need to reconfigure the beacon */ 1855 /* need to reconfigure the beacon */
1869 sc->sc_flags &= ~SC_OP_BEACONS ; 1856 sc->sc_flags &= ~SC_OP_BEACONS ;
@@ -1919,8 +1906,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1919 } 1906 }
1920 1907
1921 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 1908 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1922 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", 1909 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1923 bss_conf->use_short_preamble); 1910 bss_conf->use_short_preamble);
1924 if (bss_conf->use_short_preamble) 1911 if (bss_conf->use_short_preamble)
1925 sc->sc_flags |= SC_OP_PREAMBLE_SHORT; 1912 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1926 else 1913 else
@@ -1928,8 +1915,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1928 } 1915 }
1929 1916
1930 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 1917 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1931 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", 1918 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1932 bss_conf->use_cts_prot); 1919 bss_conf->use_cts_prot);
1933 if (bss_conf->use_cts_prot && 1920 if (bss_conf->use_cts_prot &&
1934 hw->conf.channel->band != IEEE80211_BAND_5GHZ) 1921 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1935 sc->sc_flags |= SC_OP_PROTECT_ENABLE; 1922 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
@@ -1938,7 +1925,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1938 } 1925 }
1939 1926
1940 if (changed & BSS_CHANGED_ASSOC) { 1927 if (changed & BSS_CHANGED_ASSOC) {
1941 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", 1928 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
1942 bss_conf->assoc); 1929 bss_conf->assoc);
1943 ath9k_bss_assoc_info(sc, hw, vif, bss_conf); 1930 ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
1944 } 1931 }
@@ -2024,8 +2011,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2024 ath9k_ps_restore(sc); 2011 ath9k_ps_restore(sc);
2025 break; 2012 break;
2026 default: 2013 default:
2027 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, 2014 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2028 "Unknown AMPDU action\n");
2029 } 2015 }
2030 2016
2031 local_bh_enable(); 2017 local_bh_enable();
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index 09f69a9617f4..747b2871e48f 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -30,6 +30,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
30 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 30 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
31 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 31 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
32 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ 32 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
33 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
33 { 0 } 34 { 0 }
34}; 35};
35 36
@@ -59,10 +60,9 @@ static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
59 60
60 if (pdata) { 61 if (pdata) {
61 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 62 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
62 ath_print(common, ATH_DBG_FATAL, 63 ath_err(common,
63 "%s: eeprom read failed, offset %08x " 64 "%s: eeprom read failed, offset %08x is out of range\n",
64 "is out of range\n", 65 __func__, off);
65 __func__, off);
66 } 66 }
67 67
68 *data = pdata->eeprom_data[off]; 68 *data = pdata->eeprom_data[off];
@@ -104,11 +104,23 @@ static void ath_pci_bt_coex_prep(struct ath_common *common)
104 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm); 104 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
105} 105}
106 106
107static void ath_pci_extn_synch_enable(struct ath_common *common)
108{
109 struct ath_softc *sc = (struct ath_softc *) common->priv;
110 struct pci_dev *pdev = to_pci_dev(sc->dev);
111 u8 lnkctl;
112
113 pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
114 lnkctl |= PCI_EXP_LNKCTL_ES;
115 pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
116}
117
107static const struct ath_bus_ops ath_pci_bus_ops = { 118static const struct ath_bus_ops ath_pci_bus_ops = {
108 .ath_bus_type = ATH_PCI, 119 .ath_bus_type = ATH_PCI,
109 .read_cachesize = ath_pci_read_cachesize, 120 .read_cachesize = ath_pci_read_cachesize,
110 .eeprom_read = ath_pci_eeprom_read, 121 .eeprom_read = ath_pci_eeprom_read,
111 .bt_coex_prep = ath_pci_bt_coex_prep, 122 .bt_coex_prep = ath_pci_bt_coex_prep,
123 .extn_synch_en = ath_pci_extn_synch_enable,
112}; 124};
113 125
114static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 126static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index 17969af842f6..5e3d7496986e 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -19,6 +19,7 @@
19 19
20#define CHANSEL_DIV 15 20#define CHANSEL_DIV 15
21#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) 21#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV)
22#define CHANSEL_2G_9485(_freq) ((((_freq) * 0x10000) - 215) / CHANSEL_DIV)
22#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) 23#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV)
23 24
24#define AR_PHY_BASE 0x9800 25#define AR_PHY_BASE 0x9800
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index 3e6ea3bc3d89..2061a755a026 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -1184,7 +1184,7 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
1184 return &ar5416_11na_ratetable; 1184 return &ar5416_11na_ratetable;
1185 return &ar5416_11a_ratetable; 1185 return &ar5416_11a_ratetable;
1186 default: 1186 default:
1187 ath_print(common, ATH_DBG_CONFIG, "Invalid band\n"); 1187 ath_dbg(common, ATH_DBG_CONFIG, "Invalid band\n");
1188 return NULL; 1188 return NULL;
1189 } 1189 }
1190} 1190}
@@ -1259,9 +1259,9 @@ static void ath_rc_init(struct ath_softc *sc,
1259 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4]; 1259 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
1260 ath_rc_priv->rate_table = rate_table; 1260 ath_rc_priv->rate_table = rate_table;
1261 1261
1262 ath_print(common, ATH_DBG_CONFIG, 1262 ath_dbg(common, ATH_DBG_CONFIG,
1263 "RC Initialized with capabilities: 0x%x\n", 1263 "RC Initialized with capabilities: 0x%x\n",
1264 ath_rc_priv->ht_cap); 1264 ath_rc_priv->ht_cap);
1265} 1265}
1266 1266
1267static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta, 1267static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta,
@@ -1463,9 +1463,9 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
1463 oper_cw40, oper_sgi); 1463 oper_cw40, oper_sgi);
1464 ath_rc_init(sc, priv_sta, sband, sta, rate_table); 1464 ath_rc_init(sc, priv_sta, sband, sta, rate_table);
1465 1465
1466 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, 1466 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1467 "Operating HT Bandwidth changed to: %d\n", 1467 "Operating HT Bandwidth changed to: %d\n",
1468 sc->hw->conf.channel_type); 1468 sc->hw->conf.channel_type);
1469 } 1469 }
1470 } 1470 }
1471} 1471}
@@ -1576,8 +1576,8 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
1576 1576
1577 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp); 1577 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
1578 if (!rate_priv) { 1578 if (!rate_priv) {
1579 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, 1579 ath_err(ath9k_hw_common(sc->sc_ah),
1580 "Unable to allocate private rc structure\n"); 1580 "Unable to allocate private rc structure\n");
1581 return NULL; 1581 return NULL;
1582 } 1582 }
1583 1583
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index 262c81595f6d..00ebed3f9158 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -165,7 +165,7 @@ static void ath_rx_addbuffer_edma(struct ath_softc *sc,
165 u32 nbuf = 0; 165 u32 nbuf = 0;
166 166
167 if (list_empty(&sc->rx.rxbuf)) { 167 if (list_empty(&sc->rx.rxbuf)) {
168 ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n"); 168 ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
169 return; 169 return;
170 } 170 }
171 171
@@ -269,7 +269,7 @@ static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
269 dev_kfree_skb_any(skb); 269 dev_kfree_skb_any(skb);
270 bf->bf_mpdu = NULL; 270 bf->bf_mpdu = NULL;
271 bf->bf_buf_addr = 0; 271 bf->bf_buf_addr = 0;
272 ath_print(common, ATH_DBG_FATAL, 272 ath_err(common,
273 "dma_mapping_error() on RX init\n"); 273 "dma_mapping_error() on RX init\n");
274 error = -ENOMEM; 274 error = -ENOMEM;
275 goto rx_init_fail; 275 goto rx_init_fail;
@@ -327,17 +327,17 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
327 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN, 327 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
328 min(common->cachelsz, (u16)64)); 328 min(common->cachelsz, (u16)64));
329 329
330 ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", 330 ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
331 common->cachelsz, common->rx_bufsize); 331 common->cachelsz, common->rx_bufsize);
332 332
333 /* Initialize rx descriptors */ 333 /* Initialize rx descriptors */
334 334
335 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, 335 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
336 "rx", nbufs, 1, 0); 336 "rx", nbufs, 1, 0);
337 if (error != 0) { 337 if (error != 0) {
338 ath_print(common, ATH_DBG_FATAL, 338 ath_err(common,
339 "failed to allocate rx descriptors: %d\n", 339 "failed to allocate rx descriptors: %d\n",
340 error); 340 error);
341 goto err; 341 goto err;
342 } 342 }
343 343
@@ -358,8 +358,8 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
358 dev_kfree_skb_any(skb); 358 dev_kfree_skb_any(skb);
359 bf->bf_mpdu = NULL; 359 bf->bf_mpdu = NULL;
360 bf->bf_buf_addr = 0; 360 bf->bf_buf_addr = 0;
361 ath_print(common, ATH_DBG_FATAL, 361 ath_err(common,
362 "dma_mapping_error() on RX init\n"); 362 "dma_mapping_error() on RX init\n");
363 error = -ENOMEM; 363 error = -ENOMEM;
364 goto err; 364 goto err;
365 } 365 }
@@ -528,8 +528,12 @@ bool ath_stoprecv(struct ath_softc *sc)
528 sc->rx.rxlink = NULL; 528 sc->rx.rxlink = NULL;
529 spin_unlock_bh(&sc->rx.rxbuflock); 529 spin_unlock_bh(&sc->rx.rxbuflock);
530 530
531 ATH_DBG_WARN(!stopped, "Could not stop RX, we could be " 531 if (unlikely(!stopped)) {
532 "confusing the DMA engine when we start RX up\n"); 532 ath_err(ath9k_hw_common(sc->sc_ah),
533 "Could not stop RX, we could be "
534 "confusing the DMA engine when we start RX up\n");
535 ATH_DBG_WARN_ON_ONCE(!stopped);
536 }
533 return stopped; 537 return stopped;
534} 538}
535 539
@@ -590,9 +594,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
590 594
591 if (sc->ps_flags & PS_BEACON_SYNC) { 595 if (sc->ps_flags & PS_BEACON_SYNC) {
592 sc->ps_flags &= ~PS_BEACON_SYNC; 596 sc->ps_flags &= ~PS_BEACON_SYNC;
593 ath_print(common, ATH_DBG_PS, 597 ath_dbg(common, ATH_DBG_PS,
594 "Reconfigure Beacon timers based on " 598 "Reconfigure Beacon timers based on timestamp from the AP\n");
595 "timestamp from the AP\n");
596 ath_beacon_config(sc, NULL); 599 ath_beacon_config(sc, NULL);
597 } 600 }
598 601
@@ -604,8 +607,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
604 * a backup trigger for returning into NETWORK SLEEP state, 607 * a backup trigger for returning into NETWORK SLEEP state,
605 * so we are waiting for it as well. 608 * so we are waiting for it as well.
606 */ 609 */
607 ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating " 610 ath_dbg(common, ATH_DBG_PS,
608 "buffered broadcast/multicast frame(s)\n"); 611 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
609 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; 612 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
610 return; 613 return;
611 } 614 }
@@ -617,8 +620,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
617 * been delivered. 620 * been delivered.
618 */ 621 */
619 sc->ps_flags &= ~PS_WAIT_FOR_CAB; 622 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
620 ath_print(common, ATH_DBG_PS, 623 ath_dbg(common, ATH_DBG_PS,
621 "PS wait for CAB frames timed out\n"); 624 "PS wait for CAB frames timed out\n");
622 } 625 }
623} 626}
624 627
@@ -643,15 +646,14 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
643 * point. 646 * point.
644 */ 647 */
645 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); 648 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
646 ath_print(common, ATH_DBG_PS, 649 ath_dbg(common, ATH_DBG_PS,
647 "All PS CAB frames received, back to sleep\n"); 650 "All PS CAB frames received, back to sleep\n");
648 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && 651 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
649 !is_multicast_ether_addr(hdr->addr1) && 652 !is_multicast_ether_addr(hdr->addr1) &&
650 !ieee80211_has_morefrags(hdr->frame_control)) { 653 !ieee80211_has_morefrags(hdr->frame_control)) {
651 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; 654 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
652 ath_print(common, ATH_DBG_PS, 655 ath_dbg(common, ATH_DBG_PS,
653 "Going back to sleep after having received " 656 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
654 "PS-Poll data (0x%lx)\n",
655 sc->ps_flags & (PS_WAIT_FOR_BEACON | 657 sc->ps_flags & (PS_WAIT_FOR_BEACON |
656 PS_WAIT_FOR_CAB | 658 PS_WAIT_FOR_CAB |
657 PS_WAIT_FOR_PSPOLL_DATA | 659 PS_WAIT_FOR_PSPOLL_DATA |
@@ -660,8 +662,7 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
660} 662}
661 663
662static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw, 664static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
663 struct ath_softc *sc, struct sk_buff *skb, 665 struct ath_softc *sc, struct sk_buff *skb)
664 struct ieee80211_rx_status *rxs)
665{ 666{
666 struct ieee80211_hdr *hdr; 667 struct ieee80211_hdr *hdr;
667 668
@@ -840,6 +841,10 @@ static bool ath9k_rx_accept(struct ath_common *common,
840 struct ath_rx_status *rx_stats, 841 struct ath_rx_status *rx_stats,
841 bool *decrypt_error) 842 bool *decrypt_error)
842{ 843{
844#define is_mc_or_valid_tkip_keyix ((is_mc || \
845 (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \
846 test_bit(rx_stats->rs_keyix, common->tkip_keymap))))
847
843 struct ath_hw *ah = common->ah; 848 struct ath_hw *ah = common->ah;
844 __le16 fc; 849 __le16 fc;
845 u8 rx_status_len = ah->caps.rx_status_len; 850 u8 rx_status_len = ah->caps.rx_status_len;
@@ -881,15 +886,18 @@ static bool ath9k_rx_accept(struct ath_common *common,
881 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) { 886 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
882 *decrypt_error = true; 887 *decrypt_error = true;
883 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) { 888 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
889 bool is_mc;
884 /* 890 /*
885 * The MIC error bit is only valid if the frame 891 * The MIC error bit is only valid if the frame
886 * is not a control frame or fragment, and it was 892 * is not a control frame or fragment, and it was
887 * decrypted using a valid TKIP key. 893 * decrypted using a valid TKIP key.
888 */ 894 */
895 is_mc = !!is_multicast_ether_addr(hdr->addr1);
896
889 if (!ieee80211_is_ctl(fc) && 897 if (!ieee80211_is_ctl(fc) &&
890 !ieee80211_has_morefrags(fc) && 898 !ieee80211_has_morefrags(fc) &&
891 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) && 899 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
892 test_bit(rx_stats->rs_keyix, common->tkip_keymap)) 900 is_mc_or_valid_tkip_keyix)
893 rxs->flag |= RX_FLAG_MMIC_ERROR; 901 rxs->flag |= RX_FLAG_MMIC_ERROR;
894 else 902 else
895 rx_stats->rs_status &= ~ATH9K_RXERR_MIC; 903 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
@@ -953,8 +961,9 @@ static int ath9k_process_rate(struct ath_common *common,
953 * No valid hardware bitrate found -- we should not get here 961 * No valid hardware bitrate found -- we should not get here
954 * because hardware has already validated this frame as OK. 962 * because hardware has already validated this frame as OK.
955 */ 963 */
956 ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected " 964 ath_dbg(common, ATH_DBG_XMIT,
957 "0x%02x using 1 Mbit\n", rx_stats->rs_rate); 965 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
966 rx_stats->rs_rate);
958 967
959 return -EINVAL; 968 return -EINVAL;
960} 969}
@@ -1618,7 +1627,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1618 struct ath_hw *ah = sc->sc_ah; 1627 struct ath_hw *ah = sc->sc_ah;
1619 struct ath_common *common = ath9k_hw_common(ah); 1628 struct ath_common *common = ath9k_hw_common(ah);
1620 /* 1629 /*
1621 * The hw can techncically differ from common->hw when using ath9k 1630 * The hw can technically differ from common->hw when using ath9k
1622 * virtual wiphy so to account for that we iterate over the active 1631 * virtual wiphy so to account for that we iterate over the active
1623 * wiphys and find the appropriate wiphy and therefore hw. 1632 * wiphys and find the appropriate wiphy and therefore hw.
1624 */ 1633 */
@@ -1725,9 +1734,8 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1725 dev_kfree_skb_any(requeue_skb); 1734 dev_kfree_skb_any(requeue_skb);
1726 bf->bf_mpdu = NULL; 1735 bf->bf_mpdu = NULL;
1727 bf->bf_buf_addr = 0; 1736 bf->bf_buf_addr = 0;
1728 ath_print(common, ATH_DBG_FATAL, 1737 ath_err(common, "dma_mapping_error() on RX\n");
1729 "dma_mapping_error() on RX\n"); 1738 ath_rx_send_to_mac80211(hw, sc, skb);
1730 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
1731 break; 1739 break;
1732 } 1740 }
1733 1741
@@ -1743,17 +1751,18 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1743 } 1751 }
1744 1752
1745 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1753 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1746 if (unlikely(ath9k_check_auto_sleep(sc) || 1754
1747 (sc->ps_flags & (PS_WAIT_FOR_BEACON | 1755 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1748 PS_WAIT_FOR_CAB | 1756 PS_WAIT_FOR_CAB |
1749 PS_WAIT_FOR_PSPOLL_DATA)))) 1757 PS_WAIT_FOR_PSPOLL_DATA)) ||
1758 unlikely(ath9k_check_auto_sleep(sc)))
1750 ath_rx_ps(sc, skb); 1759 ath_rx_ps(sc, skb);
1751 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1760 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1752 1761
1753 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 1762 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
1754 ath_ant_comb_scan(sc, &rs); 1763 ath_ant_comb_scan(sc, &rs);
1755 1764
1756 ath_rx_send_to_mac80211(hw, sc, skb, rxs); 1765 ath_rx_send_to_mac80211(hw, sc, skb);
1757 1766
1758requeue: 1767requeue:
1759 if (edma) { 1768 if (edma) {
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index c2472edab5e0..4df5659c6c16 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -787,6 +787,8 @@
787#define AR_SREV_REVISION_9271_11 1 787#define AR_SREV_REVISION_9271_11 1
788#define AR_SREV_VERSION_9300 0x1c0 788#define AR_SREV_VERSION_9300 0x1c0
789#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */ 789#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
790#define AR_SREV_VERSION_9485 0x240
791#define AR_SREV_REVISION_9485_10 0
790 792
791#define AR_SREV_5416(_ah) \ 793#define AR_SREV_5416(_ah) \
792 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 794 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@@ -859,12 +861,24 @@
859 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \ 861 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
860 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20))) 862 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20)))
861 863
864#define AR_SREV_9485(_ah) \
865 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))
866#define AR_SREV_9485_10(_ah) \
867 (AR_SREV_9485(_ah) && \
868 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10))
869
862#define AR_SREV_9285E_20(_ah) \ 870#define AR_SREV_9285E_20(_ah) \
863 (AR_SREV_9285_12_OR_LATER(_ah) && \ 871 (AR_SREV_9285_12_OR_LATER(_ah) && \
864 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 872 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
865 873
874enum ath_usb_dev {
875 AR9280_USB = 1, /* AR7010 + AR9280, UB94 */
876 AR9287_USB = 2, /* AR7010 + AR9287, UB95 */
877};
878
866#define AR_DEVID_7010(_ah) \ 879#define AR_DEVID_7010(_ah) \
867 ((_ah)->common.driver_info & AR7010_DEVICE) 880 (((_ah)->hw_version.usbdev == AR9280_USB) || \
881 ((_ah)->hw_version.usbdev == AR9287_USB))
868 882
869#define AR_RADIO_SREV_MAJOR 0xf0 883#define AR_RADIO_SREV_MAJOR 0xf0
870#define AR_RAD5133_SREV_MAJOR 0xc0 884#define AR_RAD5133_SREV_MAJOR 0xc0
@@ -1106,6 +1120,8 @@ enum {
1106#define AR_RTC_PLL_CONTROL \ 1120#define AR_RTC_PLL_CONTROL \
1107 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014) 1121 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
1108 1122
1123#define AR_RTC_PLL_CONTROL2 0x703c
1124
1109#define AR_RTC_PLL_DIV 0x0000001f 1125#define AR_RTC_PLL_DIV 0x0000001f
1110#define AR_RTC_PLL_DIV_S 0 1126#define AR_RTC_PLL_DIV_S 0
1111#define AR_RTC_PLL_DIV2 0x00000020 1127#define AR_RTC_PLL_DIV2 0x00000020
diff --git a/drivers/net/wireless/ath/ath9k/virtual.c b/drivers/net/wireless/ath/ath9k/virtual.c
index d5442c3745cc..fbfbc8239971 100644
--- a/drivers/net/wireless/ath/ath9k/virtual.c
+++ b/drivers/net/wireless/ath/ath9k/virtual.c
@@ -656,10 +656,9 @@ void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle)
656 struct ath_softc *sc = aphy->sc; 656 struct ath_softc *sc = aphy->sc;
657 657
658 aphy->idle = idle; 658 aphy->idle = idle;
659 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, 659 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
660 "Marking %s as %s\n", 660 "Marking %s as %sidle\n",
661 wiphy_name(aphy->hw->wiphy), 661 wiphy_name(aphy->hw->wiphy), idle ? "" : "not-");
662 idle ? "idle" : "not-idle");
663} 662}
664/* Only bother starting a queue on an active virtual wiphy */ 663/* Only bother starting a queue on an active virtual wiphy */
665bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue) 664bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue)
diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c
index 93a8bda09c25..8f42ea78198c 100644
--- a/drivers/net/wireless/ath/ath9k/wmi.c
+++ b/drivers/net/wireless/ath/ath9k/wmi.c
@@ -125,7 +125,7 @@ void ath9k_wmi_tasklet(unsigned long data)
125 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *)data; 125 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *)data;
126 struct ath_common *common = ath9k_hw_common(priv->ah); 126 struct ath_common *common = ath9k_hw_common(priv->ah);
127 127
128 ath_print(common, ATH_DBG_WMI, "SWBA Event received\n"); 128 ath_dbg(common, ATH_DBG_WMI, "SWBA Event received\n");
129 129
130 ath9k_htc_swba(priv, priv->wmi->beacon_pending); 130 ath9k_htc_swba(priv, priv->wmi->beacon_pending);
131 131
@@ -286,9 +286,9 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
286 286
287 time_left = wait_for_completion_timeout(&wmi->cmd_wait, timeout); 287 time_left = wait_for_completion_timeout(&wmi->cmd_wait, timeout);
288 if (!time_left) { 288 if (!time_left) {
289 ath_print(common, ATH_DBG_WMI, 289 ath_dbg(common, ATH_DBG_WMI,
290 "Timeout waiting for WMI command: %s\n", 290 "Timeout waiting for WMI command: %s\n",
291 wmi_cmd_to_name(cmd_id)); 291 wmi_cmd_to_name(cmd_id));
292 mutex_unlock(&wmi->op_mutex); 292 mutex_unlock(&wmi->op_mutex);
293 return -ETIMEDOUT; 293 return -ETIMEDOUT;
294 } 294 }
@@ -298,8 +298,8 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
298 return 0; 298 return 0;
299 299
300out: 300out:
301 ath_print(common, ATH_DBG_WMI, 301 ath_dbg(common, ATH_DBG_WMI,
302 "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id)); 302 "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id));
303 mutex_unlock(&wmi->op_mutex); 303 mutex_unlock(&wmi->op_mutex);
304 kfree_skb(skb); 304 kfree_skb(skb);
305 305
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 821d3679c6ff..43c0109f202c 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -985,9 +985,8 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
985 return NULL; 985 return NULL;
986 } 986 }
987 if (qnum >= ARRAY_SIZE(sc->tx.txq)) { 987 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
988 ath_print(common, ATH_DBG_FATAL, 988 ath_err(common, "qnum %u out of range, max %zu!\n",
989 "qnum %u out of range, max %u!\n", 989 qnum, ARRAY_SIZE(sc->tx.txq));
990 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
991 ath9k_hw_releasetxqueue(ah, qnum); 990 ath9k_hw_releasetxqueue(ah, qnum);
992 return NULL; 991 return NULL;
993 } 992 }
@@ -1038,8 +1037,8 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
1038 qi.tqi_readyTime = qinfo->tqi_readyTime; 1037 qi.tqi_readyTime = qinfo->tqi_readyTime;
1039 1038
1040 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1039 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1041 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, 1040 ath_err(ath9k_hw_common(sc->sc_ah),
1042 "Unable to update hardware queue %u!\n", qnum); 1041 "Unable to update hardware queue %u!\n", qnum);
1043 error = -EIO; 1042 error = -EIO;
1044 } else { 1043 } else {
1045 ath9k_hw_resettxqueue(ah, qnum); 1044 ath9k_hw_resettxqueue(ah, qnum);
@@ -1172,7 +1171,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1172 } 1171 }
1173} 1172}
1174 1173
1175void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1174bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1176{ 1175{
1177 struct ath_hw *ah = sc->sc_ah; 1176 struct ath_hw *ah = sc->sc_ah;
1178 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1177 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
@@ -1180,7 +1179,7 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1180 int i, npend = 0; 1179 int i, npend = 0;
1181 1180
1182 if (sc->sc_flags & SC_OP_INVALID) 1181 if (sc->sc_flags & SC_OP_INVALID)
1183 return; 1182 return true;
1184 1183
1185 /* Stop beacon queue */ 1184 /* Stop beacon queue */
1186 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1185 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
@@ -1194,23 +1193,15 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1194 } 1193 }
1195 } 1194 }
1196 1195
1197 if (npend) { 1196 if (npend)
1198 int r; 1197 ath_err(common, "Failed to stop TX DMA!\n");
1199
1200 ath_print(common, ATH_DBG_FATAL,
1201 "Failed to stop TX DMA. Resetting hardware!\n");
1202
1203 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
1204 if (r)
1205 ath_print(common, ATH_DBG_FATAL,
1206 "Unable to reset hardware; reset status %d\n",
1207 r);
1208 }
1209 1198
1210 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1199 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1211 if (ATH_TXQ_SETUP(sc, i)) 1200 if (ATH_TXQ_SETUP(sc, i))
1212 ath_draintxq(sc, &sc->tx.txq[i], retry_tx); 1201 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1213 } 1202 }
1203
1204 return !npend;
1214} 1205}
1215 1206
1216void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1207void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
@@ -1287,8 +1278,8 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1287 1278
1288 bf = list_first_entry(head, struct ath_buf, list); 1279 bf = list_first_entry(head, struct ath_buf, list);
1289 1280
1290 ath_print(common, ATH_DBG_QUEUE, 1281 ath_dbg(common, ATH_DBG_QUEUE,
1291 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); 1282 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1292 1283
1293 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1284 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1294 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) { 1285 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
@@ -1296,32 +1287,29 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1296 return; 1287 return;
1297 } 1288 }
1298 if (!list_empty(&txq->txq_fifo[txq->txq_headidx])) 1289 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1299 ath_print(common, ATH_DBG_XMIT, 1290 ath_dbg(common, ATH_DBG_XMIT,
1300 "Initializing tx fifo %d which " 1291 "Initializing tx fifo %d which is non-empty\n",
1301 "is non-empty\n", 1292 txq->txq_headidx);
1302 txq->txq_headidx);
1303 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]); 1293 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1304 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]); 1294 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1305 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 1295 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1306 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1296 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1307 ath_print(common, ATH_DBG_XMIT, 1297 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1308 "TXDP[%u] = %llx (%p)\n", 1298 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1309 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1310 } else { 1299 } else {
1311 list_splice_tail_init(head, &txq->axq_q); 1300 list_splice_tail_init(head, &txq->axq_q);
1312 1301
1313 if (txq->axq_link == NULL) { 1302 if (txq->axq_link == NULL) {
1314 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1303 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1315 ath_print(common, ATH_DBG_XMIT, 1304 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1316 "TXDP[%u] = %llx (%p)\n", 1305 txq->axq_qnum, ito64(bf->bf_daddr),
1317 txq->axq_qnum, ito64(bf->bf_daddr), 1306 bf->bf_desc);
1318 bf->bf_desc);
1319 } else { 1307 } else {
1320 *txq->axq_link = bf->bf_daddr; 1308 *txq->axq_link = bf->bf_daddr;
1321 ath_print(common, ATH_DBG_XMIT, 1309 ath_dbg(common, ATH_DBG_XMIT,
1322 "link[%u] (%p)=%llx (%p)\n", 1310 "link[%u] (%p)=%llx (%p)\n",
1323 txq->axq_qnum, txq->axq_link, 1311 txq->axq_qnum, txq->axq_link,
1324 ito64(bf->bf_daddr), bf->bf_desc); 1312 ito64(bf->bf_daddr), bf->bf_desc);
1325 } 1313 }
1326 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc, 1314 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1327 &txq->axq_link); 1315 &txq->axq_link);
@@ -1648,7 +1636,7 @@ static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1648 1636
1649 bf = ath_tx_get_buffer(sc); 1637 bf = ath_tx_get_buffer(sc);
1650 if (!bf) { 1638 if (!bf) {
1651 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n"); 1639 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1652 return NULL; 1640 return NULL;
1653 } 1641 }
1654 1642
@@ -1663,8 +1651,8 @@ static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1663 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 1651 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1664 bf->bf_mpdu = NULL; 1652 bf->bf_mpdu = NULL;
1665 bf->bf_buf_addr = 0; 1653 bf->bf_buf_addr = 0;
1666 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, 1654 ath_err(ath9k_hw_common(sc->sc_ah),
1667 "dma_mapping_error() on TX\n"); 1655 "dma_mapping_error() on TX\n");
1668 ath_tx_return_buffer(sc, bf); 1656 ath_tx_return_buffer(sc, bf);
1669 return NULL; 1657 return NULL;
1670 } 1658 }
@@ -1745,7 +1733,10 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1745 int frmlen = skb->len + FCS_LEN; 1733 int frmlen = skb->len + FCS_LEN;
1746 int q; 1734 int q;
1747 1735
1748 txctl->an = (struct ath_node *)sta->drv_priv; 1736 /* NOTE: sta can be NULL according to net/mac80211.h */
1737 if (sta)
1738 txctl->an = (struct ath_node *)sta->drv_priv;
1739
1749 if (info->control.hw_key) 1740 if (info->control.hw_key)
1750 frmlen += info->control.hw_key->icv_len; 1741 frmlen += info->control.hw_key->icv_len;
1751 1742
@@ -1811,7 +1802,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1811 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 1802 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1812 int q, padpos, padsize; 1803 int q, padpos, padsize;
1813 1804
1814 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); 1805 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1815 1806
1816 if (aphy) 1807 if (aphy)
1817 hw = aphy->hw; 1808 hw = aphy->hw;
@@ -1837,9 +1828,8 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1837 1828
1838 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) { 1829 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1839 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 1830 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1840 ath_print(common, ATH_DBG_PS, 1831 ath_dbg(common, ATH_DBG_PS,
1841 "Going back to sleep after having " 1832 "Going back to sleep after having received TX status (0x%lx)\n",
1842 "received TX status (0x%lx)\n",
1843 sc->ps_flags & (PS_WAIT_FOR_BEACON | 1833 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1844 PS_WAIT_FOR_CAB | 1834 PS_WAIT_FOR_CAB |
1845 PS_WAIT_FOR_PSPOLL_DATA | 1835 PS_WAIT_FOR_PSPOLL_DATA |
@@ -1988,9 +1978,9 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1988 int status; 1978 int status;
1989 int qnum; 1979 int qnum;
1990 1980
1991 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", 1981 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1992 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 1982 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1993 txq->axq_link); 1983 txq->axq_link);
1994 1984
1995 for (;;) { 1985 for (;;) {
1996 spin_lock_bh(&txq->axq_lock); 1986 spin_lock_bh(&txq->axq_lock);
@@ -2105,8 +2095,8 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
2105 } 2095 }
2106 2096
2107 if (needreset) { 2097 if (needreset) {
2108 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, 2098 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2109 "tx hung, resetting the chip\n"); 2099 "tx hung, resetting the chip\n");
2110 ath9k_ps_wakeup(sc); 2100 ath9k_ps_wakeup(sc);
2111 ath_reset(sc, true); 2101 ath_reset(sc, true);
2112 ath9k_ps_restore(sc); 2102 ath9k_ps_restore(sc);
@@ -2148,8 +2138,8 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
2148 if (status == -EINPROGRESS) 2138 if (status == -EINPROGRESS)
2149 break; 2139 break;
2150 if (status == -EIO) { 2140 if (status == -EIO) {
2151 ath_print(common, ATH_DBG_XMIT, 2141 ath_dbg(common, ATH_DBG_XMIT,
2152 "Error processing tx status\n"); 2142 "Error processing tx status\n");
2153 break; 2143 break;
2154 } 2144 }
2155 2145
@@ -2260,16 +2250,16 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
2260 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2250 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2261 "tx", nbufs, 1, 1); 2251 "tx", nbufs, 1, 1);
2262 if (error != 0) { 2252 if (error != 0) {
2263 ath_print(common, ATH_DBG_FATAL, 2253 ath_err(common,
2264 "Failed to allocate tx descriptors: %d\n", error); 2254 "Failed to allocate tx descriptors: %d\n", error);
2265 goto err; 2255 goto err;
2266 } 2256 }
2267 2257
2268 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2258 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2269 "beacon", ATH_BCBUF, 1, 1); 2259 "beacon", ATH_BCBUF, 1, 1);
2270 if (error != 0) { 2260 if (error != 0) {
2271 ath_print(common, ATH_DBG_FATAL, 2261 ath_err(common,
2272 "Failed to allocate beacon descriptors: %d\n", error); 2262 "Failed to allocate beacon descriptors: %d\n", error);
2273 goto err; 2263 goto err;
2274 } 2264 }
2275 2265
diff --git a/drivers/net/wireless/ath/debug.c b/drivers/net/wireless/ath/debug.c
index a9600ba8ceaa..5367b1086e09 100644
--- a/drivers/net/wireless/ath/debug.c
+++ b/drivers/net/wireless/ath/debug.c
@@ -15,26 +15,6 @@
15 */ 15 */
16 16
17#include "ath.h" 17#include "ath.h"
18#include "debug.h"
19
20void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
21{
22 struct va_format vaf;
23 va_list args;
24
25 if (likely(!(common->debug_mask & dbg_mask)))
26 return;
27
28 va_start(args, fmt);
29
30 vaf.fmt = fmt;
31 vaf.va = &args;
32
33 printk(KERN_DEBUG "ath: %pV", &vaf);
34
35 va_end(args);
36}
37EXPORT_SYMBOL(ath_print);
38 18
39const char *ath_opmode_to_string(enum nl80211_iftype opmode) 19const char *ath_opmode_to_string(enum nl80211_iftype opmode)
40{ 20{
diff --git a/drivers/net/wireless/ath/debug.h b/drivers/net/wireless/ath/debug.h
deleted file mode 100644
index f207007ee391..000000000000
--- a/drivers/net/wireless/ath/debug.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH_DEBUG_H
18#define ATH_DEBUG_H
19
20#include "ath.h"
21
22/**
23 * enum ath_debug_level - atheros wireless debug level
24 *
25 * @ATH_DBG_RESET: reset processing
26 * @ATH_DBG_QUEUE: hardware queue management
27 * @ATH_DBG_EEPROM: eeprom processing
28 * @ATH_DBG_CALIBRATE: periodic calibration
29 * @ATH_DBG_INTERRUPT: interrupt processing
30 * @ATH_DBG_REGULATORY: regulatory processing
31 * @ATH_DBG_ANI: adaptive noise immunitive processing
32 * @ATH_DBG_XMIT: basic xmit operation
33 * @ATH_DBG_BEACON: beacon handling
34 * @ATH_DBG_CONFIG: configuration of the hardware
35 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
36 * @ATH_DBG_PS: power save processing
37 * @ATH_DBG_HWTIMER: hardware timer handling
38 * @ATH_DBG_BTCOEX: bluetooth coexistance
39 * @ATH_DBG_BSTUCK: stuck beacons
40 * @ATH_DBG_ANY: enable all debugging
41 *
42 * The debug level is used to control the amount and type of debugging output
43 * we want to see. Each driver has its own method for enabling debugging and
44 * modifying debug level states -- but this is typically done through a
45 * module parameter 'debug' along with a respective 'debug' debugfs file
46 * entry.
47 */
48enum ATH_DEBUG {
49 ATH_DBG_RESET = 0x00000001,
50 ATH_DBG_QUEUE = 0x00000002,
51 ATH_DBG_EEPROM = 0x00000004,
52 ATH_DBG_CALIBRATE = 0x00000008,
53 ATH_DBG_INTERRUPT = 0x00000010,
54 ATH_DBG_REGULATORY = 0x00000020,
55 ATH_DBG_ANI = 0x00000040,
56 ATH_DBG_XMIT = 0x00000080,
57 ATH_DBG_BEACON = 0x00000100,
58 ATH_DBG_CONFIG = 0x00000200,
59 ATH_DBG_FATAL = 0x00000400,
60 ATH_DBG_PS = 0x00000800,
61 ATH_DBG_HWTIMER = 0x00001000,
62 ATH_DBG_BTCOEX = 0x00002000,
63 ATH_DBG_WMI = 0x00004000,
64 ATH_DBG_BSTUCK = 0x00008000,
65 ATH_DBG_ANY = 0xffffffff
66};
67
68#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
69
70#ifdef CONFIG_ATH_DEBUG
71void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
72 __attribute__ ((format (printf, 3, 4)));
73#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
74#else
75static inline void __attribute__ ((format (printf, 3, 4)))
76ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
77{
78}
79#define ATH_DBG_WARN(foo, arg)
80#endif /* CONFIG_ATH_DEBUG */
81
82/** Returns string describing opmode, or NULL if unknown mode. */
83#ifdef CONFIG_ATH_DEBUG
84const char *ath_opmode_to_string(enum nl80211_iftype opmode);
85#else
86static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
87{
88 return "UNKNOWN";
89}
90#endif
91
92#endif /* ATH_DEBUG_H */
diff --git a/drivers/net/wireless/ath/key.c b/drivers/net/wireless/ath/key.c
index 62e3dac8f92a..29a2961af5fc 100644
--- a/drivers/net/wireless/ath/key.c
+++ b/drivers/net/wireless/ath/key.c
@@ -20,7 +20,6 @@
20 20
21#include "ath.h" 21#include "ath.h"
22#include "reg.h" 22#include "reg.h"
23#include "debug.h"
24 23
25#define REG_READ (common->ops->read) 24#define REG_READ (common->ops->read)
26#define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) 25#define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg)
@@ -37,8 +36,7 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry)
37 void *ah = common->ah; 36 void *ah = common->ah;
38 37
39 if (entry >= common->keymax) { 38 if (entry >= common->keymax) {
40 ath_print(common, ATH_DBG_FATAL, 39 ath_err(common, "keycache entry %u out of range\n", entry);
41 "keychache entry %u out of range\n", entry);
42 return false; 40 return false;
43 } 41 }
44 42
@@ -75,8 +73,7 @@ static bool ath_hw_keysetmac(struct ath_common *common,
75 void *ah = common->ah; 73 void *ah = common->ah;
76 74
77 if (entry >= common->keymax) { 75 if (entry >= common->keymax) {
78 ath_print(common, ATH_DBG_FATAL, 76 ath_err(common, "keycache entry %u out of range\n", entry);
79 "keychache entry %u out of range\n", entry);
80 return false; 77 return false;
81 } 78 }
82 79
@@ -117,8 +114,7 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
117 u32 keyType; 114 u32 keyType;
118 115
119 if (entry >= common->keymax) { 116 if (entry >= common->keymax) {
120 ath_print(common, ATH_DBG_FATAL, 117 ath_err(common, "keycache entry %u out of range\n", entry);
121 "keycache entry %u out of range\n", entry);
122 return false; 118 return false;
123 } 119 }
124 120
@@ -128,8 +124,8 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
128 break; 124 break;
129 case ATH_CIPHER_AES_CCM: 125 case ATH_CIPHER_AES_CCM:
130 if (!(common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)) { 126 if (!(common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)) {
131 ath_print(common, ATH_DBG_ANY, 127 ath_dbg(common, ATH_DBG_ANY,
132 "AES-CCM not supported by this mac rev\n"); 128 "AES-CCM not supported by this mac rev\n");
133 return false; 129 return false;
134 } 130 }
135 keyType = AR_KEYTABLE_TYPE_CCM; 131 keyType = AR_KEYTABLE_TYPE_CCM;
@@ -137,15 +133,15 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
137 case ATH_CIPHER_TKIP: 133 case ATH_CIPHER_TKIP:
138 keyType = AR_KEYTABLE_TYPE_TKIP; 134 keyType = AR_KEYTABLE_TYPE_TKIP;
139 if (entry + 64 >= common->keymax) { 135 if (entry + 64 >= common->keymax) {
140 ath_print(common, ATH_DBG_ANY, 136 ath_dbg(common, ATH_DBG_ANY,
141 "entry %u inappropriate for TKIP\n", entry); 137 "entry %u inappropriate for TKIP\n", entry);
142 return false; 138 return false;
143 } 139 }
144 break; 140 break;
145 case ATH_CIPHER_WEP: 141 case ATH_CIPHER_WEP:
146 if (k->kv_len < WLAN_KEY_LEN_WEP40) { 142 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
147 ath_print(common, ATH_DBG_ANY, 143 ath_dbg(common, ATH_DBG_ANY,
148 "WEP key length %u too small\n", k->kv_len); 144 "WEP key length %u too small\n", k->kv_len);
149 return false; 145 return false;
150 } 146 }
151 if (k->kv_len <= WLAN_KEY_LEN_WEP40) 147 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
@@ -159,8 +155,7 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
159 keyType = AR_KEYTABLE_TYPE_CLR; 155 keyType = AR_KEYTABLE_TYPE_CLR;
160 break; 156 break;
161 default: 157 default:
162 ath_print(common, ATH_DBG_FATAL, 158 ath_err(common, "cipher %u not supported\n", k->kv_type);
163 "cipher %u not supported\n", k->kv_type);
164 return false; 159 return false;
165 } 160 }
166 161
@@ -341,8 +336,7 @@ static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
341 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); 336 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
342 if (!ath_hw_set_keycache_entry(common, keyix, hk, NULL)) { 337 if (!ath_hw_set_keycache_entry(common, keyix, hk, NULL)) {
343 /* TX MIC entry failed. No need to proceed further */ 338 /* TX MIC entry failed. No need to proceed further */
344 ath_print(common, ATH_DBG_FATAL, 339 ath_err(common, "Setting TX MIC Key Failed\n");
345 "Setting TX MIC Key Failed\n");
346 return 0; 340 return 0;
347 } 341 }
348 342
diff --git a/drivers/net/wireless/ath/main.c b/drivers/net/wireless/ath/main.c
index 487193f1de1a..c325202fdc5f 100644
--- a/drivers/net/wireless/ath/main.c
+++ b/drivers/net/wireless/ath/main.c
@@ -56,3 +56,23 @@ struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
56 return skb; 56 return skb;
57} 57}
58EXPORT_SYMBOL(ath_rxbuf_alloc); 58EXPORT_SYMBOL(ath_rxbuf_alloc);
59
60int ath_printk(const char *level, struct ath_common *common,
61 const char *fmt, ...)
62{
63 struct va_format vaf;
64 va_list args;
65 int rtn;
66
67 va_start(args, fmt);
68
69 vaf.fmt = fmt;
70 vaf.va = &args;
71
72 rtn = printk("%sath: %pV", level, &vaf);
73
74 va_end(args);
75
76 return rtn;
77}
78EXPORT_SYMBOL(ath_printk);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-01 15:25:03 -0500