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path: root/drivers/net/wireless/ath/ath9k/ar9002_calib.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9002_calib.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_calib.c220
1 files changed, 108 insertions, 112 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
index 15f62cd0cc38..01880aa13e36 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
@@ -39,18 +39,18 @@ static void ar9002_hw_setup_calibration(struct ath_hw *ah,
39 switch (currCal->calData->calType) { 39 switch (currCal->calData->calType) {
40 case IQ_MISMATCH_CAL: 40 case IQ_MISMATCH_CAL:
41 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 41 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
42 ath_print(common, ATH_DBG_CALIBRATE, 42 ath_dbg(common, ATH_DBG_CALIBRATE,
43 "starting IQ Mismatch Calibration\n"); 43 "starting IQ Mismatch Calibration\n");
44 break; 44 break;
45 case ADC_GAIN_CAL: 45 case ADC_GAIN_CAL:
46 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); 46 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
47 ath_print(common, ATH_DBG_CALIBRATE, 47 ath_dbg(common, ATH_DBG_CALIBRATE,
48 "starting ADC Gain Calibration\n"); 48 "starting ADC Gain Calibration\n");
49 break; 49 break;
50 case ADC_DC_CAL: 50 case ADC_DC_CAL:
51 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); 51 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
52 ath_print(common, ATH_DBG_CALIBRATE, 52 ath_dbg(common, ATH_DBG_CALIBRATE,
53 "starting ADC DC Calibration\n"); 53 "starting ADC DC Calibration\n");
54 break; 54 break;
55 } 55 }
56 56
@@ -107,11 +107,11 @@ static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
107 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 107 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
108 ah->totalIqCorrMeas[i] += 108 ah->totalIqCorrMeas[i] +=
109 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 109 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
110 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, 110 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
111 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", 111 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
112 ah->cal_samples, i, ah->totalPowerMeasI[i], 112 ah->cal_samples, i, ah->totalPowerMeasI[i],
113 ah->totalPowerMeasQ[i], 113 ah->totalPowerMeasQ[i],
114 ah->totalIqCorrMeas[i]); 114 ah->totalIqCorrMeas[i]);
115 } 115 }
116} 116}
117 117
@@ -129,14 +129,13 @@ static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
129 ah->totalAdcQEvenPhase[i] += 129 ah->totalAdcQEvenPhase[i] +=
130 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 130 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
131 131
132 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, 132 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
133 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 133 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
134 "oddq=0x%08x; evenq=0x%08x;\n", 134 ah->cal_samples, i,
135 ah->cal_samples, i, 135 ah->totalAdcIOddPhase[i],
136 ah->totalAdcIOddPhase[i], 136 ah->totalAdcIEvenPhase[i],
137 ah->totalAdcIEvenPhase[i], 137 ah->totalAdcQOddPhase[i],
138 ah->totalAdcQOddPhase[i], 138 ah->totalAdcQEvenPhase[i]);
139 ah->totalAdcQEvenPhase[i]);
140 } 139 }
141} 140}
142 141
@@ -154,14 +153,13 @@ static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
154 ah->totalAdcDcOffsetQEvenPhase[i] += 153 ah->totalAdcDcOffsetQEvenPhase[i] +=
155 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 154 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
156 155
157 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, 156 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
158 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 157 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
159 "oddq=0x%08x; evenq=0x%08x;\n", 158 ah->cal_samples, i,
160 ah->cal_samples, i, 159 ah->totalAdcDcOffsetIOddPhase[i],
161 ah->totalAdcDcOffsetIOddPhase[i], 160 ah->totalAdcDcOffsetIEvenPhase[i],
162 ah->totalAdcDcOffsetIEvenPhase[i], 161 ah->totalAdcDcOffsetQOddPhase[i],
163 ah->totalAdcDcOffsetQOddPhase[i], 162 ah->totalAdcDcOffsetQEvenPhase[i]);
164 ah->totalAdcDcOffsetQEvenPhase[i]);
165 } 163 }
166} 164}
167 165
@@ -178,13 +176,13 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
178 powerMeasQ = ah->totalPowerMeasQ[i]; 176 powerMeasQ = ah->totalPowerMeasQ[i];
179 iqCorrMeas = ah->totalIqCorrMeas[i]; 177 iqCorrMeas = ah->totalIqCorrMeas[i];
180 178
181 ath_print(common, ATH_DBG_CALIBRATE, 179 ath_dbg(common, ATH_DBG_CALIBRATE,
182 "Starting IQ Cal and Correction for Chain %d\n", 180 "Starting IQ Cal and Correction for Chain %d\n",
183 i); 181 i);
184 182
185 ath_print(common, ATH_DBG_CALIBRATE, 183 ath_dbg(common, ATH_DBG_CALIBRATE,
186 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 184 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
187 i, ah->totalIqCorrMeas[i]); 185 i, ah->totalIqCorrMeas[i]);
188 186
189 iqCorrNeg = 0; 187 iqCorrNeg = 0;
190 188
@@ -193,12 +191,12 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
193 iqCorrNeg = 1; 191 iqCorrNeg = 1;
194 } 192 }
195 193
196 ath_print(common, ATH_DBG_CALIBRATE, 194 ath_dbg(common, ATH_DBG_CALIBRATE,
197 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); 195 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
198 ath_print(common, ATH_DBG_CALIBRATE, 196 ath_dbg(common, ATH_DBG_CALIBRATE,
199 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); 197 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
200 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", 198 ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
201 iqCorrNeg); 199 iqCorrNeg);
202 200
203 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 201 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
204 qCoffDenom = powerMeasQ / 64; 202 qCoffDenom = powerMeasQ / 64;
@@ -207,14 +205,14 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
207 (qCoffDenom != 0)) { 205 (qCoffDenom != 0)) {
208 iCoff = iqCorrMeas / iCoffDenom; 206 iCoff = iqCorrMeas / iCoffDenom;
209 qCoff = powerMeasI / qCoffDenom - 64; 207 qCoff = powerMeasI / qCoffDenom - 64;
210 ath_print(common, ATH_DBG_CALIBRATE, 208 ath_dbg(common, ATH_DBG_CALIBRATE,
211 "Chn %d iCoff = 0x%08x\n", i, iCoff); 209 "Chn %d iCoff = 0x%08x\n", i, iCoff);
212 ath_print(common, ATH_DBG_CALIBRATE, 210 ath_dbg(common, ATH_DBG_CALIBRATE,
213 "Chn %d qCoff = 0x%08x\n", i, qCoff); 211 "Chn %d qCoff = 0x%08x\n", i, qCoff);
214 212
215 iCoff = iCoff & 0x3f; 213 iCoff = iCoff & 0x3f;
216 ath_print(common, ATH_DBG_CALIBRATE, 214 ath_dbg(common, ATH_DBG_CALIBRATE,
217 "New: Chn %d iCoff = 0x%08x\n", i, iCoff); 215 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
218 if (iqCorrNeg == 0x0) 216 if (iqCorrNeg == 0x0)
219 iCoff = 0x40 - iCoff; 217 iCoff = 0x40 - iCoff;
220 218
@@ -223,9 +221,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
223 else if (qCoff <= -16) 221 else if (qCoff <= -16)
224 qCoff = -16; 222 qCoff = -16;
225 223
226 ath_print(common, ATH_DBG_CALIBRATE, 224 ath_dbg(common, ATH_DBG_CALIBRATE,
227 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", 225 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
228 i, iCoff, qCoff); 226 i, iCoff, qCoff);
229 227
230 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), 228 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
231 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 229 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
@@ -233,9 +231,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
233 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), 231 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
234 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 232 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
235 qCoff); 233 qCoff);
236 ath_print(common, ATH_DBG_CALIBRATE, 234 ath_dbg(common, ATH_DBG_CALIBRATE,
237 "IQ Cal and Correction done for Chain %d\n", 235 "IQ Cal and Correction done for Chain %d\n",
238 i); 236 i);
239 } 237 }
240 } 238 }
241 239
@@ -255,21 +253,21 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
255 qOddMeasOffset = ah->totalAdcQOddPhase[i]; 253 qOddMeasOffset = ah->totalAdcQOddPhase[i];
256 qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; 254 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
257 255
258 ath_print(common, ATH_DBG_CALIBRATE, 256 ath_dbg(common, ATH_DBG_CALIBRATE,
259 "Starting ADC Gain Cal for Chain %d\n", i); 257 "Starting ADC Gain Cal for Chain %d\n", i);
260 258
261 ath_print(common, ATH_DBG_CALIBRATE, 259 ath_dbg(common, ATH_DBG_CALIBRATE,
262 "Chn %d pwr_meas_odd_i = 0x%08x\n", i, 260 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
263 iOddMeasOffset); 261 iOddMeasOffset);
264 ath_print(common, ATH_DBG_CALIBRATE, 262 ath_dbg(common, ATH_DBG_CALIBRATE,
265 "Chn %d pwr_meas_even_i = 0x%08x\n", i, 263 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
266 iEvenMeasOffset); 264 iEvenMeasOffset);
267 ath_print(common, ATH_DBG_CALIBRATE, 265 ath_dbg(common, ATH_DBG_CALIBRATE,
268 "Chn %d pwr_meas_odd_q = 0x%08x\n", i, 266 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
269 qOddMeasOffset); 267 qOddMeasOffset);
270 ath_print(common, ATH_DBG_CALIBRATE, 268 ath_dbg(common, ATH_DBG_CALIBRATE,
271 "Chn %d pwr_meas_even_q = 0x%08x\n", i, 269 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
272 qEvenMeasOffset); 270 qEvenMeasOffset);
273 271
274 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { 272 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
275 iGainMismatch = 273 iGainMismatch =
@@ -279,20 +277,20 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
279 ((qOddMeasOffset * 32) / 277 ((qOddMeasOffset * 32) /
280 qEvenMeasOffset) & 0x3f; 278 qEvenMeasOffset) & 0x3f;
281 279
282 ath_print(common, ATH_DBG_CALIBRATE, 280 ath_dbg(common, ATH_DBG_CALIBRATE,
283 "Chn %d gain_mismatch_i = 0x%08x\n", i, 281 "Chn %d gain_mismatch_i = 0x%08x\n", i,
284 iGainMismatch); 282 iGainMismatch);
285 ath_print(common, ATH_DBG_CALIBRATE, 283 ath_dbg(common, ATH_DBG_CALIBRATE,
286 "Chn %d gain_mismatch_q = 0x%08x\n", i, 284 "Chn %d gain_mismatch_q = 0x%08x\n", i,
287 qGainMismatch); 285 qGainMismatch);
288 286
289 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 287 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
290 val &= 0xfffff000; 288 val &= 0xfffff000;
291 val |= (qGainMismatch) | (iGainMismatch << 6); 289 val |= (qGainMismatch) | (iGainMismatch << 6);
292 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 290 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
293 291
294 ath_print(common, ATH_DBG_CALIBRATE, 292 ath_dbg(common, ATH_DBG_CALIBRATE,
295 "ADC Gain Cal done for Chain %d\n", i); 293 "ADC Gain Cal done for Chain %d\n", i);
296 } 294 }
297 } 295 }
298 296
@@ -317,41 +315,41 @@ static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
317 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; 315 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
318 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; 316 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
319 317
320 ath_print(common, ATH_DBG_CALIBRATE, 318 ath_dbg(common, ATH_DBG_CALIBRATE,
321 "Starting ADC DC Offset Cal for Chain %d\n", i); 319 "Starting ADC DC Offset Cal for Chain %d\n", i);
322 320
323 ath_print(common, ATH_DBG_CALIBRATE, 321 ath_dbg(common, ATH_DBG_CALIBRATE,
324 "Chn %d pwr_meas_odd_i = %d\n", i, 322 "Chn %d pwr_meas_odd_i = %d\n", i,
325 iOddMeasOffset); 323 iOddMeasOffset);
326 ath_print(common, ATH_DBG_CALIBRATE, 324 ath_dbg(common, ATH_DBG_CALIBRATE,
327 "Chn %d pwr_meas_even_i = %d\n", i, 325 "Chn %d pwr_meas_even_i = %d\n", i,
328 iEvenMeasOffset); 326 iEvenMeasOffset);
329 ath_print(common, ATH_DBG_CALIBRATE, 327 ath_dbg(common, ATH_DBG_CALIBRATE,
330 "Chn %d pwr_meas_odd_q = %d\n", i, 328 "Chn %d pwr_meas_odd_q = %d\n", i,
331 qOddMeasOffset); 329 qOddMeasOffset);
332 ath_print(common, ATH_DBG_CALIBRATE, 330 ath_dbg(common, ATH_DBG_CALIBRATE,
333 "Chn %d pwr_meas_even_q = %d\n", i, 331 "Chn %d pwr_meas_even_q = %d\n", i,
334 qEvenMeasOffset); 332 qEvenMeasOffset);
335 333
336 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / 334 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
337 numSamples) & 0x1ff; 335 numSamples) & 0x1ff;
338 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / 336 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
339 numSamples) & 0x1ff; 337 numSamples) & 0x1ff;
340 338
341 ath_print(common, ATH_DBG_CALIBRATE, 339 ath_dbg(common, ATH_DBG_CALIBRATE,
342 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, 340 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
343 iDcMismatch); 341 iDcMismatch);
344 ath_print(common, ATH_DBG_CALIBRATE, 342 ath_dbg(common, ATH_DBG_CALIBRATE,
345 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, 343 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
346 qDcMismatch); 344 qDcMismatch);
347 345
348 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 346 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
349 val &= 0xc0000fff; 347 val &= 0xc0000fff;
350 val |= (qDcMismatch << 12) | (iDcMismatch << 21); 348 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
351 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 349 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
352 350
353 ath_print(common, ATH_DBG_CALIBRATE, 351 ath_dbg(common, ATH_DBG_CALIBRATE,
354 "ADC DC Offset Cal done for Chain %d\n", i); 352 "ADC DC Offset Cal done for Chain %d\n", i);
355 } 353 }
356 354
357 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), 355 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
@@ -540,7 +538,7 @@ static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
540 { 0x7838, 0 }, 538 { 0x7838, 0 },
541 }; 539 };
542 540
543 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n"); 541 ath_dbg(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
544 542
545 /* PA CAL is not needed for high power solution */ 543 /* PA CAL is not needed for high power solution */
546 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 544 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
@@ -721,9 +719,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
721 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 719 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
722 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, 720 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
723 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { 721 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
724 ath_print(common, ATH_DBG_CALIBRATE, "offset " 722 ath_dbg(common, ATH_DBG_CALIBRATE,
725 "calibration failed to complete in " 723 "offset calibration failed to complete in 1ms; noisy environment?\n");
726 "1ms; noisy ??\n");
727 return false; 724 return false;
728 } 725 }
729 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); 726 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
@@ -736,8 +733,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
736 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 733 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
737 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 734 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
738 0, AH_WAIT_TIMEOUT)) { 735 0, AH_WAIT_TIMEOUT)) {
739 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration " 736 ath_dbg(common, ATH_DBG_CALIBRATE,
740 "failed to complete in 1ms; noisy ??\n"); 737 "offset calibration failed to complete in 1ms; noisy environment?\n");
741 return false; 738 return false;
742 } 739 }
743 740
@@ -829,9 +826,8 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
829 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, 826 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
830 AR_PHY_AGC_CONTROL_CAL, 827 AR_PHY_AGC_CONTROL_CAL,
831 0, AH_WAIT_TIMEOUT)) { 828 0, AH_WAIT_TIMEOUT)) {
832 ath_print(common, ATH_DBG_CALIBRATE, 829 ath_dbg(common, ATH_DBG_CALIBRATE,
833 "offset calibration failed to " 830 "offset calibration failed to complete in 1ms; noisy environment?\n");
834 "complete in 1ms; noisy environment?\n");
835 return false; 831 return false;
836 } 832 }
837 833
@@ -866,19 +862,19 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
866 862
867 INIT_CAL(&ah->adcgain_caldata); 863 INIT_CAL(&ah->adcgain_caldata);
868 INSERT_CAL(ah, &ah->adcgain_caldata); 864 INSERT_CAL(ah, &ah->adcgain_caldata);
869 ath_print(common, ATH_DBG_CALIBRATE, 865 ath_dbg(common, ATH_DBG_CALIBRATE,
870 "enabling ADC Gain Calibration.\n"); 866 "enabling ADC Gain Calibration.\n");
871 867
872 INIT_CAL(&ah->adcdc_caldata); 868 INIT_CAL(&ah->adcdc_caldata);
873 INSERT_CAL(ah, &ah->adcdc_caldata); 869 INSERT_CAL(ah, &ah->adcdc_caldata);
874 ath_print(common, ATH_DBG_CALIBRATE, 870 ath_dbg(common, ATH_DBG_CALIBRATE,
875 "enabling ADC DC Calibration.\n"); 871 "enabling ADC DC Calibration.\n");
876 } 872 }
877 873
878 INIT_CAL(&ah->iq_caldata); 874 INIT_CAL(&ah->iq_caldata);
879 INSERT_CAL(ah, &ah->iq_caldata); 875 INSERT_CAL(ah, &ah->iq_caldata);
880 ath_print(common, ATH_DBG_CALIBRATE, 876 ath_dbg(common, ATH_DBG_CALIBRATE,
881 "enabling IQ Calibration.\n"); 877 "enabling IQ Calibration.\n");
882 878
883 ah->cal_list_curr = ah->cal_list; 879 ah->cal_list_curr = ah->cal_list;
884 880
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-02 17:30:19 -0500