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authorDavid S. Miller <davem@davemloft.net>2010-12-23 13:13:30 -0500
committerDavid S. Miller <davem@davemloft.net>2010-12-23 13:13:30 -0500
commita130883d9528eefb66285728ba6a232d8fff9465 (patch)
tree304b63e59d910be2ee2798404fe4a940bdfdd2af /drivers/net/wireless/ath/ath9k
parentd9f4fbaf7053af43e6c72909c2aff18654717aed (diff)
parent65a6538a56d4c7ae8465f2a8420ddc65877b6779 (diff)
Merge branch 'for-davem' of ssh://master.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
Diffstat (limited to 'drivers/net/wireless/ath/ath9k')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c13
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_hw.c19
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_mac.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h104
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_calib.c225
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c136
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.h44
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c13
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mac.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_paprd.c125
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c28
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h8
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h5
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c215
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h57
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c209
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c213
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c211
-rw-r--r--drivers/net/wireless/ath/ath9k/hif_usb.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_main.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_txrx.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/hw-ops.h5
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c57
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h18
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c5
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c220
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c3
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/virtual.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c30
30 files changed, 856 insertions, 1119 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index 059330aac645..ffcf44a4058b 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -961,18 +961,6 @@ static void ar5008_hw_rfbus_done(struct ath_hw *ah)
961 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 961 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
962} 962}
963 963
964static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
965{
966 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
967 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
968
969 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
970 AR_GPIO_INPUT_MUX2_RFSILENT);
971
972 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
973 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
974}
975
976static void ar5008_restore_chainmask(struct ath_hw *ah) 964static void ar5008_restore_chainmask(struct ath_hw *ah)
977{ 965{
978 int rx_chainmask = ah->rxchainmask; 966 int rx_chainmask = ah->rxchainmask;
@@ -1629,7 +1617,6 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1629 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; 1617 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1630 priv_ops->rfbus_req = ar5008_hw_rfbus_req; 1618 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1631 priv_ops->rfbus_done = ar5008_hw_rfbus_done; 1619 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1632 priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
1633 priv_ops->restore_chainmask = ar5008_restore_chainmask; 1620 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1634 priv_ops->set_diversity = ar5008_set_diversity; 1621 priv_ops->set_diversity = ar5008_set_diversity;
1635 priv_ops->do_getnf = ar5008_hw_do_getnf; 1622 priv_ops->do_getnf = ar5008_hw_do_getnf;
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index 7d5cb204f938..fdb5a835fdcf 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -26,24 +26,6 @@ MODULE_PARM_DESC(nohwcrypt, "Force new ANI for AR5008, AR9001, AR9002");
26 26
27/* General hardware code for the A5008/AR9001/AR9002 hadware families */ 27/* General hardware code for the A5008/AR9001/AR9002 hadware families */
28 28
29static bool ar9002_hw_macversion_supported(u32 macversion)
30{
31 switch (macversion) {
32 case AR_SREV_VERSION_5416_PCI:
33 case AR_SREV_VERSION_5416_PCIE:
34 case AR_SREV_VERSION_9160:
35 case AR_SREV_VERSION_9100:
36 case AR_SREV_VERSION_9280:
37 case AR_SREV_VERSION_9285:
38 case AR_SREV_VERSION_9287:
39 case AR_SREV_VERSION_9271:
40 return true;
41 default:
42 break;
43 }
44 return false;
45}
46
47static void ar9002_hw_init_mode_regs(struct ath_hw *ah) 29static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
48{ 30{
49 if (AR_SREV_9271(ah)) { 31 if (AR_SREV_9271(ah)) {
@@ -565,7 +547,6 @@ void ar9002_hw_attach_ops(struct ath_hw *ah)
565 547
566 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs; 548 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
567 priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs; 549 priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
568 priv_ops->macversion_supported = ar9002_hw_macversion_supported;
569 550
570 ops->config_pci_powersave = ar9002_hw_configpcipowersave; 551 ops->config_pci_powersave = ar9002_hw_configpcipowersave;
571 552
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
index f3f9c589158e..399ab3bb299b 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
@@ -283,7 +283,6 @@ static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
283{ 283{
284 struct ar5416_desc *ads = AR5416DESC(ds); 284 struct ar5416_desc *ads = AR5416DESC(ds);
285 285
286 txPower += ah->txpower_indexoffset;
287 if (txPower > 63) 286 if (txPower > 63)
288 txPower = 63; 287 txPower = 63;
289 288
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index a14a5e43cf56..81f9cf294dec 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -34,9 +34,9 @@ static const u32 ar9300_2p2_radio_postamble[][5] = {
34 34
35static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = { 35static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
36 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 36 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
37 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x00637800, 0x00637800}, 37 {0x0000a2dc, 0x00033800, 0x00033800, 0x00637800, 0x00637800},
38 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03838000, 0x03838000}, 38 {0x0000a2e0, 0x0003c000, 0x0003c000, 0x03838000, 0x03838000},
39 {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03fc0000, 0x03fc0000}, 39 {0x0000a2e4, 0x03fc0000, 0x03fc0000, 0x03fc0000, 0x03fc0000},
40 {0x0000a2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 40 {0x0000a2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
41 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, 41 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
42 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 42 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -56,21 +56,21 @@ static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
56 {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24}, 56 {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
57 {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640}, 57 {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
58 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660}, 58 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
59 {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861}, 59 {0x0000a544, 0x52022470, 0x52022470, 0x3f001861, 0x3f001861},
60 {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81}, 60 {0x0000a548, 0x55022490, 0x55022490, 0x43001a81, 0x43001a81},
61 {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x47001a83, 0x47001a83}, 61 {0x0000a54c, 0x59022492, 0x59022492, 0x47001a83, 0x47001a83},
62 {0x0000a550, 0x61024a6c, 0x61024a6c, 0x4a001c84, 0x4a001c84}, 62 {0x0000a550, 0x5d022692, 0x5d022692, 0x4a001c84, 0x4a001c84},
63 {0x0000a554, 0x66026a6c, 0x66026a6c, 0x4e001ce3, 0x4e001ce3}, 63 {0x0000a554, 0x61022892, 0x61022892, 0x4e001ce3, 0x4e001ce3},
64 {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x52001ce5, 0x52001ce5}, 64 {0x0000a558, 0x65024890, 0x65024890, 0x52001ce5, 0x52001ce5},
65 {0x0000a55c, 0x7002708c, 0x7002708c, 0x56001ce9, 0x56001ce9}, 65 {0x0000a55c, 0x69024892, 0x69024892, 0x56001ce9, 0x56001ce9},
66 {0x0000a560, 0x7302b08a, 0x7302b08a, 0x5a001ceb, 0x5a001ceb}, 66 {0x0000a560, 0x6e024c92, 0x6e024c92, 0x5a001ceb, 0x5a001ceb},
67 {0x0000a564, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec}, 67 {0x0000a564, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
68 {0x0000a568, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec}, 68 {0x0000a568, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
69 {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec}, 69 {0x0000a56c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
70 {0x0000a570, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec}, 70 {0x0000a570, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
71 {0x0000a574, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec}, 71 {0x0000a574, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
72 {0x0000a578, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec}, 72 {0x0000a578, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
73 {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec}, 73 {0x0000a57c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
74 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000}, 74 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
75 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002}, 75 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
76 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004}, 76 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
@@ -88,44 +88,44 @@ static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
88 {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24}, 88 {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
89 {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640}, 89 {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
90 {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660}, 90 {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
91 {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861}, 91 {0x0000a5c4, 0x52822470, 0x52822470, 0x3f801861, 0x3f801861},
92 {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81}, 92 {0x0000a5c8, 0x55822490, 0x55822490, 0x43801a81, 0x43801a81},
93 {0x0000a5cc, 0x5c82486b, 0x5c82486b, 0x47801a83, 0x47801a83}, 93 {0x0000a5cc, 0x59822492, 0x59822492, 0x47801a83, 0x47801a83},
94 {0x0000a5d0, 0x61824a6c, 0x61824a6c, 0x4a801c84, 0x4a801c84}, 94 {0x0000a5d0, 0x5d822692, 0x5d822692, 0x4a801c84, 0x4a801c84},
95 {0x0000a5d4, 0x66826a6c, 0x66826a6c, 0x4e801ce3, 0x4e801ce3}, 95 {0x0000a5d4, 0x61822892, 0x61822892, 0x4e801ce3, 0x4e801ce3},
96 {0x0000a5d8, 0x6b826e6c, 0x6b826e6c, 0x52801ce5, 0x52801ce5}, 96 {0x0000a5d8, 0x65824890, 0x65824890, 0x52801ce5, 0x52801ce5},
97 {0x0000a5dc, 0x7082708c, 0x7082708c, 0x56801ce9, 0x56801ce9}, 97 {0x0000a5dc, 0x69824892, 0x69824892, 0x56801ce9, 0x56801ce9},
98 {0x0000a5e0, 0x7382b08a, 0x7382b08a, 0x5a801ceb, 0x5a801ceb}, 98 {0x0000a5e0, 0x6e824c92, 0x6e824c92, 0x5a801ceb, 0x5a801ceb},
99 {0x0000a5e4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec}, 99 {0x0000a5e4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
100 {0x0000a5e8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec}, 100 {0x0000a5e8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
101 {0x0000a5ec, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec}, 101 {0x0000a5ec, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
102 {0x0000a5f0, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec}, 102 {0x0000a5f0, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
103 {0x0000a5f4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec}, 103 {0x0000a5f4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
104 {0x0000a5f8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec}, 104 {0x0000a5f8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
105 {0x0000a5fc, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec}, 105 {0x0000a5fc, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
106 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 106 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
107 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 107 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
108 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 108 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
109 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 109 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
110 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 110 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
111 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000}, 111 {0x0000a614, 0x02004000, 0x02004000, 0x01404000, 0x01404000},
112 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501}, 112 {0x0000a618, 0x02004801, 0x02004801, 0x01404501, 0x01404501},
113 {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501}, 113 {0x0000a61c, 0x02808a02, 0x02808a02, 0x02008501, 0x02008501},
114 {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03}, 114 {0x0000a620, 0x0380ce03, 0x0380ce03, 0x0280ca03, 0x0280ca03},
115 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04}, 115 {0x0000a624, 0x04411104, 0x04411104, 0x03010c04, 0x03010c04},
116 {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04}, 116 {0x0000a628, 0x04411104, 0x04411104, 0x04014c04, 0x04014c04},
117 {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005}, 117 {0x0000a62c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
118 {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, 118 {0x0000a630, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
119 {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, 119 {0x0000a634, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
120 {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, 120 {0x0000a638, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
121 {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005}, 121 {0x0000a63c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
122 {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x00637800, 0x00637800}, 122 {0x0000b2dc, 0x00033800, 0x00033800, 0x00637800, 0x00637800},
123 {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03838000, 0x03838000}, 123 {0x0000b2e0, 0x0003c000, 0x0003c000, 0x03838000, 0x03838000},
124 {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03fc0000, 0x03fc0000}, 124 {0x0000b2e4, 0x03fc0000, 0x03fc0000, 0x03fc0000, 0x03fc0000},
125 {0x0000b2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 125 {0x0000b2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
126 {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x00637800, 0x00637800}, 126 {0x0000c2dc, 0x00033800, 0x00033800, 0x00637800, 0x00637800},
127 {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03838000, 0x03838000}, 127 {0x0000c2e0, 0x0003c000, 0x0003c000, 0x03838000, 0x03838000},
128 {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03fc0000, 0x03fc0000}, 128 {0x0000c2e4, 0x03fc0000, 0x03fc0000, 0x03fc0000, 0x03fc0000},
129 {0x0000c2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 129 {0x0000c2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
130 {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4}, 130 {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
131 {0x00016048, 0x62480001, 0x62480001, 0x62480001, 0x62480001}, 131 {0x00016048, 0x62480001, 0x62480001, 0x62480001, 0x62480001},
@@ -638,6 +638,7 @@ static const u32 ar9300_2p2_baseband_postamble[][5] = {
638 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, 638 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
639 {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0}, 639 {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0},
640 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, 640 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
641 {0x0000a22c, 0x01026a2f, 0x01026a2f, 0x01026a2f, 0x01026a2f},
641 {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b}, 642 {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
642 {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff}, 643 {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
643 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018}, 644 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
@@ -680,7 +681,7 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
680 {0x0000981c, 0x00020028}, 681 {0x0000981c, 0x00020028},
681 {0x00009834, 0x6400a290}, 682 {0x00009834, 0x6400a290},
682 {0x00009838, 0x0108ecff}, 683 {0x00009838, 0x0108ecff},
683 {0x0000983c, 0x14750600}, 684 {0x0000983c, 0x0d000600},
684 {0x00009880, 0x201fff00}, 685 {0x00009880, 0x201fff00},
685 {0x00009884, 0x00001042}, 686 {0x00009884, 0x00001042},
686 {0x000098a4, 0x00200400}, 687 {0x000098a4, 0x00200400},
@@ -722,7 +723,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
722 {0x0000a220, 0x00000000}, 723 {0x0000a220, 0x00000000},
723 {0x0000a224, 0x00000000}, 724 {0x0000a224, 0x00000000},
724 {0x0000a228, 0x10002310}, 725 {0x0000a228, 0x10002310},
725 {0x0000a22c, 0x01036a27},
726 {0x0000a23c, 0x00000000}, 726 {0x0000a23c, 0x00000000},
727 {0x0000a244, 0x0c000000}, 727 {0x0000a244, 0x0c000000},
728 {0x0000a2a0, 0x00000001}, 728 {0x0000a2a0, 0x00000001},
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
index 7c3334bd396e..4a4cd88429c0 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -608,120 +608,6 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
608 return true; 608 return true;
609} 609}
610 610
611static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
612{
613 struct ath_common *common = ath9k_hw_common(ah);
614 static const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
615 AR_PHY_TX_IQCAL_STATUS_B0,
616 AR_PHY_TX_IQCAL_STATUS_B1,
617 AR_PHY_TX_IQCAL_STATUS_B2,
618 };
619 static const u32 rx_corr[AR9300_MAX_CHAINS] = {
620 AR_PHY_RX_IQCAL_CORR_B0,
621 AR_PHY_RX_IQCAL_CORR_B1,
622 AR_PHY_RX_IQCAL_CORR_B2,
623 };
624 static const u_int32_t chan_info_tab[] = {
625 AR_PHY_CHAN_INFO_TAB_0,
626 AR_PHY_CHAN_INFO_TAB_1,
627 AR_PHY_CHAN_INFO_TAB_2,
628 };
629 u32 tx_corr_coeff[AR9300_MAX_CHAINS];
630 s32 iq_res[6];
631 s32 iqc_coeff[2];
632 s32 i, j;
633 u32 num_chains = 0;
634
635 tx_corr_coeff[0] = AR_PHY_TX_IQCAL_CORR_COEFF_B0(0);
636 tx_corr_coeff[1] = AR_PHY_TX_IQCAL_CORR_COEFF_B1(0);
637 tx_corr_coeff[2] = AR_PHY_TX_IQCAL_CORR_COEFF_B2(0);
638
639 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
640 if (ah->txchainmask & (1 << i))
641 num_chains++;
642 }
643
644 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
645 AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
646 DELPT);
647 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
648 AR_PHY_TX_IQCAL_START_DO_CAL,
649 AR_PHY_TX_IQCAL_START_DO_CAL);
650
651 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
652 AR_PHY_TX_IQCAL_START_DO_CAL,
653 0, AH_WAIT_TIMEOUT)) {
654 ath_dbg(common, ATH_DBG_CALIBRATE,
655 "Tx IQ Cal not complete.\n");
656 goto TX_IQ_CAL_FAILED;
657 }
658
659 for (i = 0; i < num_chains; i++) {
660 ath_dbg(common, ATH_DBG_CALIBRATE,
661 "Doing Tx IQ Cal for chain %d.\n", i);
662
663 if (REG_READ(ah, txiqcal_status[i]) &
664 AR_PHY_TX_IQCAL_STATUS_FAILED) {
665 ath_dbg(common, ATH_DBG_CALIBRATE,
666 "Tx IQ Cal failed for chain %d.\n", i);
667 goto TX_IQ_CAL_FAILED;
668 }
669
670 for (j = 0; j < 3; j++) {
671 u_int8_t idx = 2 * j,
672 offset = 4 * j;
673
674 REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
675 AR_PHY_CHAN_INFO_TAB_S2_READ, 0);
676
677 /* 32 bits */
678 iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset);
679
680 REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
681 AR_PHY_CHAN_INFO_TAB_S2_READ, 1);
682
683 /* 16 bits */
684 iq_res[idx+1] = 0xffff & REG_READ(ah,
685 chan_info_tab[i] +
686 offset);
687
688 ath_dbg(common, ATH_DBG_CALIBRATE,
689 "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
690 idx, iq_res[idx], idx+1, iq_res[idx+1]);
691 }
692
693 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
694 ath_dbg(common, ATH_DBG_CALIBRATE,
695 "Failed in calculation of IQ correction.\n");
696 goto TX_IQ_CAL_FAILED;
697 }
698
699 ath_dbg(common, ATH_DBG_CALIBRATE,
700 "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
701 iqc_coeff[0], iqc_coeff[1]);
702
703 REG_RMW_FIELD(ah, tx_corr_coeff[i],
704 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
705 iqc_coeff[0]);
706 REG_RMW_FIELD(ah, rx_corr[i],
707 AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
708 iqc_coeff[1] >> 7);
709 REG_RMW_FIELD(ah, rx_corr[i],
710 AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
711 iqc_coeff[1]);
712 }
713
714 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
715 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
716 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
717 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
718
719 return;
720
721TX_IQ_CAL_FAILED:
722 ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
723}
724
725static bool ar9003_hw_compute_closest_pass_and_avg(int *mp_coeff, int *mp_avg) 611static bool ar9003_hw_compute_closest_pass_and_avg(int *mp_coeff, int *mp_avg)
726{ 612{
727 int diff[MPASS]; 613 int diff[MPASS];
@@ -730,9 +616,9 @@ static bool ar9003_hw_compute_closest_pass_and_avg(int *mp_coeff, int *mp_avg)
730 diff[1] = abs(mp_coeff[1] - mp_coeff[2]); 616 diff[1] = abs(mp_coeff[1] - mp_coeff[2]);
731 diff[2] = abs(mp_coeff[2] - mp_coeff[0]); 617 diff[2] = abs(mp_coeff[2] - mp_coeff[0]);
732 618
733 if (diff[0] > MAX_MEASUREMENT && 619 if (diff[0] > MAX_DIFFERENCE &&
734 diff[1] > MAX_MEASUREMENT && 620 diff[1] > MAX_DIFFERENCE &&
735 diff[2] > MAX_MEASUREMENT) 621 diff[2] > MAX_DIFFERENCE)
736 return false; 622 return false;
737 623
738 if (diff[0] <= diff[1] && diff[0] <= diff[2]) 624 if (diff[0] <= diff[1] && diff[0] <= diff[2])
@@ -830,6 +716,111 @@ disable_txiqcal:
830 ath_dbg(common, ATH_DBG_CALIBRATE, "TX IQ Cal disabled\n"); 716 ath_dbg(common, ATH_DBG_CALIBRATE, "TX IQ Cal disabled\n");
831} 717}
832 718
719static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
720{
721 struct ath_common *common = ath9k_hw_common(ah);
722 static const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
723 AR_PHY_TX_IQCAL_STATUS_B0,
724 AR_PHY_TX_IQCAL_STATUS_B1,
725 AR_PHY_TX_IQCAL_STATUS_B2,
726 };
727 static const u32 chan_info_tab[] = {
728 AR_PHY_CHAN_INFO_TAB_0,
729 AR_PHY_CHAN_INFO_TAB_1,
730 AR_PHY_CHAN_INFO_TAB_2,
731 };
732 struct coeff coeff;
733 s32 iq_res[6];
734 s32 i, j, ip, im, nmeasurement;
735 u8 nchains = get_streams(common->tx_chainmask);
736
737 for (ip = 0; ip < MPASS; ip++) {
738 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
739 AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
740 DELPT);
741 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
742 AR_PHY_TX_IQCAL_START_DO_CAL,
743 AR_PHY_TX_IQCAL_START_DO_CAL);
744
745 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
746 AR_PHY_TX_IQCAL_START_DO_CAL,
747 0, AH_WAIT_TIMEOUT)) {
748 ath_dbg(common, ATH_DBG_CALIBRATE,
749 "Tx IQ Cal not complete.\n");
750 goto TX_IQ_CAL_FAILED;
751 }
752
753 nmeasurement = REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_STATUS_B0,
754 AR_PHY_CALIBRATED_GAINS_0);
755 if (nmeasurement > MAX_MEASUREMENT)
756 nmeasurement = MAX_MEASUREMENT;
757
758 for (i = 0; i < nchains; i++) {
759 ath_dbg(common, ATH_DBG_CALIBRATE,
760 "Doing Tx IQ Cal for chain %d.\n", i);
761 for (im = 0; im < nmeasurement; im++) {
762 if (REG_READ(ah, txiqcal_status[i]) &
763 AR_PHY_TX_IQCAL_STATUS_FAILED) {
764 ath_dbg(common, ATH_DBG_CALIBRATE,
765 "Tx IQ Cal failed for chain %d.\n", i);
766 goto TX_IQ_CAL_FAILED;
767 }
768
769 for (j = 0; j < 3; j++) {
770 u8 idx = 2 * j,
771 offset = 4 * (3 * im + j);
772
773 REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
774 AR_PHY_CHAN_INFO_TAB_S2_READ,
775 0);
776
777 /* 32 bits */
778 iq_res[idx] = REG_READ(ah,
779 chan_info_tab[i] +
780 offset);
781
782 REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
783 AR_PHY_CHAN_INFO_TAB_S2_READ,
784 1);
785
786 /* 16 bits */
787 iq_res[idx+1] = 0xffff & REG_READ(ah,
788 chan_info_tab[i] +
789 offset);
790
791 ath_dbg(common, ATH_DBG_CALIBRATE,
792 "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
793 idx, iq_res[idx], idx+1, iq_res[idx+1]);
794 }
795
796 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
797 coeff.iqc_coeff)) {
798 ath_dbg(common, ATH_DBG_CALIBRATE,
799 "Failed in calculation of IQ correction.\n");
800 goto TX_IQ_CAL_FAILED;
801 }
802 coeff.mag_coeff[i][im][ip] =
803 coeff.iqc_coeff[0] & 0x7f;
804 coeff.phs_coeff[i][im][ip] =
805 (coeff.iqc_coeff[0] >> 7) & 0x7f;
806
807 if (coeff.mag_coeff[i][im][ip] > 63)
808 coeff.mag_coeff[i][im][ip] -= 128;
809 if (coeff.phs_coeff[i][im][ip] > 63)
810 coeff.phs_coeff[i][im][ip] -= 128;
811
812 }
813 }
814 }
815
816 ar9003_hw_tx_iqcal_load_avg_2_passes(ah, nchains, &coeff);
817
818 return;
819
820TX_IQ_CAL_FAILED:
821 ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
822}
823
833static void ar9003_hw_tx_iq_cal_run(struct ath_hw *ah) 824static void ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
834{ 825{
835 u8 tx_gain_forced; 826 u8 tx_gain_forced;
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index a16b3dae5b34..466d2bf02eab 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -73,7 +73,7 @@ static const struct ar9300_eeprom ar9300_default = {
73 .regDmn = { LE16(0), LE16(0x1f) }, 73 .regDmn = { LE16(0), LE16(0x1f) },
74 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 74 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
75 .opCapFlags = { 75 .opCapFlags = {
76 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 76 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
77 .eepMisc = 0, 77 .eepMisc = 0,
78 }, 78 },
79 .rfSilent = 0, 79 .rfSilent = 0,
@@ -650,7 +650,7 @@ static const struct ar9300_eeprom ar9300_x113 = {
650 .regDmn = { LE16(0), LE16(0x1f) }, 650 .regDmn = { LE16(0), LE16(0x1f) },
651 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 651 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
652 .opCapFlags = { 652 .opCapFlags = {
653 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 653 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
654 .eepMisc = 0, 654 .eepMisc = 0,
655 }, 655 },
656 .rfSilent = 0, 656 .rfSilent = 0,
@@ -1228,7 +1228,7 @@ static const struct ar9300_eeprom ar9300_h112 = {
1228 .regDmn = { LE16(0), LE16(0x1f) }, 1228 .regDmn = { LE16(0), LE16(0x1f) },
1229 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 1229 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1230 .opCapFlags = { 1230 .opCapFlags = {
1231 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 1231 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1232 .eepMisc = 0, 1232 .eepMisc = 0,
1233 }, 1233 },
1234 .rfSilent = 0, 1234 .rfSilent = 0,
@@ -1806,7 +1806,7 @@ static const struct ar9300_eeprom ar9300_x112 = {
1806 .regDmn = { LE16(0), LE16(0x1f) }, 1806 .regDmn = { LE16(0), LE16(0x1f) },
1807 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 1807 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1808 .opCapFlags = { 1808 .opCapFlags = {
1809 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 1809 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1810 .eepMisc = 0, 1810 .eepMisc = 0,
1811 }, 1811 },
1812 .rfSilent = 0, 1812 .rfSilent = 0,
@@ -2383,7 +2383,7 @@ static const struct ar9300_eeprom ar9300_h116 = {
2383 .regDmn = { LE16(0), LE16(0x1f) }, 2383 .regDmn = { LE16(0), LE16(0x1f) },
2384 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */ 2384 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2385 .opCapFlags = { 2385 .opCapFlags = {
2386 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 2386 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2387 .eepMisc = 0, 2387 .eepMisc = 0,
2388 }, 2388 },
2389 .rfSilent = 0, 2389 .rfSilent = 0,
@@ -2975,7 +2975,7 @@ static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2975 2975
2976static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) 2976static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2977{ 2977{
2978 if (fbin == AR9300_BCHAN_UNUSED) 2978 if (fbin == AR5416_BCHAN_UNUSED)
2979 return fbin; 2979 return fbin;
2980 2980
2981 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 2981 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
@@ -3428,18 +3428,6 @@ static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3428 return 0; 3428 return 0;
3429} 3429}
3430 3430
3431static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
3432 enum ath9k_hal_freq_band freq_band)
3433{
3434 return 1;
3435}
3436
3437static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
3438 struct ath9k_channel *chan)
3439{
3440 return -EINVAL;
3441}
3442
3443static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz) 3431static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3444{ 3432{
3445 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3433 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
@@ -4486,7 +4474,7 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4486 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]); 4474 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4487 } 4475 }
4488 4476
4489 return AR9300_MAX_RATE_POWER; 4477 return MAX_RATE_POWER;
4490} 4478}
4491 4479
4492/* 4480/*
@@ -4495,7 +4483,7 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4495static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, 4483static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4496 u16 freq, int idx, bool is2GHz) 4484 u16 freq, int idx, bool is2GHz)
4497{ 4485{
4498 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER; 4486 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4499 u8 *ctl_freqbin = is2GHz ? 4487 u8 *ctl_freqbin = is2GHz ?
4500 &eep->ctl_freqbin_2G[idx][0] : 4488 &eep->ctl_freqbin_2G[idx][0] :
4501 &eep->ctl_freqbin_5G[idx][0]; 4489 &eep->ctl_freqbin_5G[idx][0];
@@ -4505,7 +4493,7 @@ static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4505 4493
4506 /* Get the edge power */ 4494 /* Get the edge power */
4507 for (edge = 0; 4495 for (edge = 0;
4508 (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED); 4496 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4509 edge++) { 4497 edge++) {
4510 /* 4498 /*
4511 * If there's an exact channel match or an inband flag set 4499 * If there's an exact channel match or an inband flag set
@@ -4543,9 +4531,9 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4543 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 4531 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4544 struct ath_common *common = ath9k_hw_common(ah); 4532 struct ath_common *common = ath9k_hw_common(ah);
4545 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; 4533 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4546 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER; 4534 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4547 static const u16 tpScaleReductionTable[5] = { 4535 static const u16 tpScaleReductionTable[5] = {
4548 0, 3, 6, 9, AR9300_MAX_RATE_POWER 4536 0, 3, 6, 9, MAX_RATE_POWER
4549 }; 4537 };
4550 int i; 4538 int i;
4551 int16_t twiceLargestAntenna; 4539 int16_t twiceLargestAntenna;
@@ -4756,6 +4744,16 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4756 } /* end ctl mode checking */ 4744 } /* end ctl mode checking */
4757} 4745}
4758 4746
4747static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4748{
4749 u8 mod_idx = mcs_idx % 8;
4750
4751 if (mod_idx <= 3)
4752 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4753 else
4754 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4755}
4756
4759static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, 4757static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4760 struct ath9k_channel *chan, u16 cfgCtl, 4758 struct ath9k_channel *chan, u16 cfgCtl,
4761 u8 twiceAntennaReduction, 4759 u8 twiceAntennaReduction,
@@ -4764,16 +4762,70 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4764{ 4762{
4765 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 4763 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4766 struct ath_common *common = ath9k_hw_common(ah); 4764 struct ath_common *common = ath9k_hw_common(ah);
4765 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4766 struct ar9300_modal_eep_header *modal_hdr;
4767 u8 targetPowerValT2[ar9300RateSize]; 4767 u8 targetPowerValT2[ar9300RateSize];
4768 unsigned int i = 0; 4768 u8 target_power_val_t2_eep[ar9300RateSize];
4769 unsigned int i = 0, paprd_scale_factor = 0;
4770 u8 pwr_idx, min_pwridx = 0;
4769 4771
4770 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2); 4772 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4773
4774 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4775 if (IS_CHAN_2GHZ(chan))
4776 modal_hdr = &eep->modalHeader2G;
4777 else
4778 modal_hdr = &eep->modalHeader5G;
4779
4780 ah->paprd_ratemask =
4781 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
4782 AR9300_PAPRD_RATE_MASK;
4783
4784 ah->paprd_ratemask_ht40 =
4785 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
4786 AR9300_PAPRD_RATE_MASK;
4787
4788 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
4789 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
4790 ALL_TARGET_HT20_0_8_16;
4791
4792 if (!ah->paprd_table_write_done) {
4793 memcpy(target_power_val_t2_eep, targetPowerValT2,
4794 sizeof(targetPowerValT2));
4795 for (i = 0; i < 24; i++) {
4796 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
4797 if (ah->paprd_ratemask & (1 << i)) {
4798 if (targetPowerValT2[pwr_idx] &&
4799 targetPowerValT2[pwr_idx] ==
4800 target_power_val_t2_eep[pwr_idx])
4801 targetPowerValT2[pwr_idx] -=
4802 paprd_scale_factor;
4803 }
4804 }
4805 }
4806 memcpy(target_power_val_t2_eep, targetPowerValT2,
4807 sizeof(targetPowerValT2));
4808 }
4809
4771 ar9003_hw_set_power_per_rate_table(ah, chan, 4810 ar9003_hw_set_power_per_rate_table(ah, chan,
4772 targetPowerValT2, cfgCtl, 4811 targetPowerValT2, cfgCtl,
4773 twiceAntennaReduction, 4812 twiceAntennaReduction,
4774 twiceMaxRegulatoryPower, 4813 twiceMaxRegulatoryPower,
4775 powerLimit); 4814 powerLimit);
4776 4815
4816 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4817 for (i = 0; i < ar9300RateSize; i++) {
4818 if ((ah->paprd_ratemask & (1 << i)) &&
4819 (abs(targetPowerValT2[i] -
4820 target_power_val_t2_eep[i]) >
4821 paprd_scale_factor)) {
4822 ah->paprd_ratemask &= ~(1 << i);
4823 ath_dbg(common, ATH_DBG_EEPROM,
4824 "paprd disabled for mcs %d\n", i);
4825 }
4826 }
4827 }
4828
4777 regulatory->max_power_level = 0; 4829 regulatory->max_power_level = 0;
4778 for (i = 0; i < ar9300RateSize; i++) { 4830 for (i = 0; i < ar9300RateSize; i++) {
4779 if (targetPowerValT2[i] > regulatory->max_power_level) 4831 if (targetPowerValT2[i] > regulatory->max_power_level)
@@ -4811,6 +4863,19 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4811 /* Write target power array to registers */ 4863 /* Write target power array to registers */
4812 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2); 4864 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
4813 ar9003_hw_calibration_apply(ah, chan->channel); 4865 ar9003_hw_calibration_apply(ah, chan->channel);
4866
4867 if (IS_CHAN_2GHZ(chan)) {
4868 if (IS_CHAN_HT40(chan))
4869 i = ALL_TARGET_HT40_0_8_16;
4870 else
4871 i = ALL_TARGET_HT20_0_8_16;
4872 } else {
4873 if (IS_CHAN_HT40(chan))
4874 i = ALL_TARGET_HT40_7;
4875 else
4876 i = ALL_TARGET_HT20_7;
4877 }
4878 ah->paprd_target_power = targetPowerValT2[i];
4814} 4879}
4815 4880
4816static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah, 4881static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
@@ -4843,14 +4908,33 @@ u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
4843 return eep->modalHeader5G.spurChans; 4908 return eep->modalHeader5G.spurChans;
4844} 4909}
4845 4910
4911unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
4912 struct ath9k_channel *chan)
4913{
4914 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4915
4916 if (IS_CHAN_2GHZ(chan))
4917 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
4918 AR9300_PAPRD_SCALE_1);
4919 else {
4920 if (chan->channel >= 5700)
4921 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
4922 AR9300_PAPRD_SCALE_1);
4923 else if (chan->channel >= 5400)
4924 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
4925 AR9300_PAPRD_SCALE_2);
4926 else
4927 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
4928 AR9300_PAPRD_SCALE_1);
4929 }
4930}
4931
4846const struct eeprom_ops eep_ar9300_ops = { 4932const struct eeprom_ops eep_ar9300_ops = {
4847 .check_eeprom = ath9k_hw_ar9300_check_eeprom, 4933 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4848 .get_eeprom = ath9k_hw_ar9300_get_eeprom, 4934 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
4849 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom, 4935 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
4850 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver, 4936 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
4851 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev, 4937 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
4852 .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
4853 .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
4854 .set_board_values = ath9k_hw_ar9300_set_board_values, 4938 .set_board_values = ath9k_hw_ar9300_set_board_values,
4855 .set_addac = ath9k_hw_ar9300_set_addac, 4939 .set_addac = ath9k_hw_ar9300_set_addac,
4856 .set_txpower = ath9k_hw_ar9300_set_txpower, 4940 .set_txpower = ath9k_hw_ar9300_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 33503217dab3..afb0b5ee1865 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -20,47 +20,22 @@
20/* #define AR9300_NUM_CTLS 21 */ 20/* #define AR9300_NUM_CTLS 21 */
21#define AR9300_NUM_CTLS_5G 9 21#define AR9300_NUM_CTLS_5G 9
22#define AR9300_NUM_CTLS_2G 12 22#define AR9300_NUM_CTLS_2G 12
23#define AR9300_CTL_MODE_M 0xF
24#define AR9300_NUM_BAND_EDGES_5G 8 23#define AR9300_NUM_BAND_EDGES_5G 8
25#define AR9300_NUM_BAND_EDGES_2G 4 24#define AR9300_NUM_BAND_EDGES_2G 4
26#define AR9300_NUM_PD_GAINS 4
27#define AR9300_PD_GAINS_IN_MASK 4
28#define AR9300_PD_GAIN_ICEPTS 5
29#define AR9300_EEPROM_MODAL_SPURS 5
30#define AR9300_MAX_RATE_POWER 63
31#define AR9300_NUM_PDADC_VALUES 128
32#define AR9300_NUM_RATES 16
33#define AR9300_BCHAN_UNUSED 0xFF
34#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
35#define AR9300_OPFLAGS_11A 0x01
36#define AR9300_OPFLAGS_11G 0x02
37#define AR9300_OPFLAGS_5G_HT40 0x04
38#define AR9300_OPFLAGS_2G_HT40 0x08
39#define AR9300_OPFLAGS_5G_HT20 0x10
40#define AR9300_OPFLAGS_2G_HT20 0x20
41#define AR9300_EEPMISC_BIG_ENDIAN 0x01 25#define AR9300_EEPMISC_BIG_ENDIAN 0x01
42#define AR9300_EEPMISC_WOW 0x02 26#define AR9300_EEPMISC_WOW 0x02
43#define AR9300_CUSTOMER_DATA_SIZE 20 27#define AR9300_CUSTOMER_DATA_SIZE 20
44 28
45#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
46#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x)) 29#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
47#define AR9300_MAX_CHAINS 3 30#define AR9300_MAX_CHAINS 3
48#define AR9300_ANT_16S 25 31#define AR9300_ANT_16S 25
49#define AR9300_FUTURE_MODAL_SZ 6 32#define AR9300_FUTURE_MODAL_SZ 6
50 33
51#define AR9300_NUM_ANT_CHAIN_FIELDS 7 34#define AR9300_PAPRD_RATE_MASK 0x01ffffff
52#define AR9300_NUM_ANT_COMMON_FIELDS 4 35#define AR9300_PAPRD_SCALE_1 0x0e000000
53#define AR9300_SIZE_ANT_CHAIN_FIELD 3 36#define AR9300_PAPRD_SCALE_1_S 25
54#define AR9300_SIZE_ANT_COMMON_FIELD 4 37#define AR9300_PAPRD_SCALE_2 0x70000000
55#define AR9300_ANT_CHAIN_MASK 0x7 38#define AR9300_PAPRD_SCALE_2_S 28
56#define AR9300_ANT_COMMON_MASK 0xf
57#define AR9300_CHAIN_0_IDX 0
58#define AR9300_CHAIN_1_IDX 1
59#define AR9300_CHAIN_2_IDX 2
60
61#define AR928X_NUM_ANT_CHAIN_FIELDS 6
62#define AR928X_SIZE_ANT_CHAIN_FIELD 2
63#define AR928X_ANT_CHAIN_MASK 0x3
64 39
65/* Delta from which to start power to pdadc table */ 40/* Delta from which to start power to pdadc table */
66/* This offset is used in both open loop and closed loop power control 41/* This offset is used in both open loop and closed loop power control
@@ -71,12 +46,8 @@
71 */ 46 */
72#define AR9300_PWR_TABLE_OFFSET 0 47#define AR9300_PWR_TABLE_OFFSET 0
73 48
74/* enable flags for voltage and temp compensation */
75#define ENABLE_TEMP_COMPENSATION 0x01
76#define ENABLE_VOLT_COMPENSATION 0x02
77/* byte addressable */ 49/* byte addressable */
78#define AR9300_EEPROM_SIZE (16*1024) 50#define AR9300_EEPROM_SIZE (16*1024)
79#define FIXED_CCA_THRESHOLD 15
80 51
81#define AR9300_BASE_ADDR_4K 0xfff 52#define AR9300_BASE_ADDR_4K 0xfff
82#define AR9300_BASE_ADDR 0x3ff 53#define AR9300_BASE_ADDR 0x3ff
@@ -226,7 +197,7 @@ struct ar9300_modal_eep_header {
226 int8_t tempSlope; 197 int8_t tempSlope;
227 int8_t voltSlope; 198 int8_t voltSlope;
228 /* spur channels in usual fbin coding format */ 199 /* spur channels in usual fbin coding format */
229 u8 spurChans[AR9300_EEPROM_MODAL_SPURS]; 200 u8 spurChans[AR_EEPROM_MODAL_SPURS];
230 /* 3 Check if the register is per chain */ 201 /* 3 Check if the register is per chain */
231 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS]; 202 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
232 u8 ob[AR9300_MAX_CHAINS]; 203 u8 ob[AR9300_MAX_CHAINS];
@@ -344,4 +315,7 @@ s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
344s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah); 315s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
345 316
346u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz); 317u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
318
319unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
320 struct ath9k_channel *chan);
347#endif 321#endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 21a5bfe354a0..6137634e46ca 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -21,18 +21,6 @@
21 21
22/* General hardware code for the AR9003 hadware family */ 22/* General hardware code for the AR9003 hadware family */
23 23
24static bool ar9003_hw_macversion_supported(u32 macversion)
25{
26 switch (macversion) {
27 case AR_SREV_VERSION_9300:
28 case AR_SREV_VERSION_9485:
29 return true;
30 default:
31 break;
32 }
33 return false;
34}
35
36/* 24/*
37 * The AR9003 family uses a new INI format (pre, core, post 25 * The AR9003 family uses a new INI format (pre, core, post
38 * arrays per subsystem). This provides support for the 26 * arrays per subsystem). This provides support for the
@@ -322,7 +310,6 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
322 310
323 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs; 311 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
324 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs; 312 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
325 priv_ops->macversion_supported = ar9003_hw_macversion_supported;
326 313
327 ops->config_pci_powersave = ar9003_hw_configpcipowersave; 314 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
328 315
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index bfba6a2b741d..b6e4ee48ef78 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -322,7 +322,6 @@ static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
322 if (txpower > ah->txpower_limit) 322 if (txpower > ah->txpower_limit)
323 txpower = ah->txpower_limit; 323 txpower = ah->txpower_limit;
324 324
325 txpower += ah->txpower_indexoffset;
326 if (txpower > 63) 325 if (txpower > 63)
327 txpower = 63; 326 txpower = 63;
328 327
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index 74cff4365c43..356d2fd78822 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -19,6 +19,20 @@
19 19
20void ar9003_paprd_enable(struct ath_hw *ah, bool val) 20void ar9003_paprd_enable(struct ath_hw *ah, bool val)
21{ 21{
22 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
23 struct ath9k_channel *chan = ah->curchan;
24
25 if (val) {
26 ah->paprd_table_write_done = true;
27
28 ah->eep_ops->set_txpower(ah, chan,
29 ath9k_regd_get_ctl(regulatory, chan),
30 chan->chan->max_antenna_gain * 2,
31 chan->chan->max_power * 2,
32 min((u32) MAX_RATE_POWER,
33 (u32) regulatory->power_limit), false);
34 }
35
22 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0, 36 REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
23 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val); 37 AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
24 if (ah->caps.tx_chainmask & BIT(1)) 38 if (ah->caps.tx_chainmask & BIT(1))
@@ -30,10 +44,63 @@ void ar9003_paprd_enable(struct ath_hw *ah, bool val)
30} 44}
31EXPORT_SYMBOL(ar9003_paprd_enable); 45EXPORT_SYMBOL(ar9003_paprd_enable);
32 46
33static void ar9003_paprd_setup_single_table(struct ath_hw *ah) 47static int ar9003_get_training_power_2g(struct ath_hw *ah)
48{
49 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
50 struct ar9300_modal_eep_header *hdr = &eep->modalHeader2G;
51 unsigned int power, scale, delta;
52
53 scale = MS(le32_to_cpu(hdr->papdRateMaskHt20), AR9300_PAPRD_SCALE_1);
54 power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
55 AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
56
57 delta = abs((int) ah->paprd_target_power - (int) power);
58 if (delta > scale)
59 return -1;
60
61 if (delta < 4)
62 power -= 4 - delta;
63
64 return power;
65}
66
67static int ar9003_get_training_power_5g(struct ath_hw *ah)
34{ 68{
69 struct ath_common *common = ath9k_hw_common(ah);
35 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 70 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
36 struct ar9300_modal_eep_header *hdr; 71 struct ar9300_modal_eep_header *hdr = &eep->modalHeader5G;
72 struct ath9k_channel *chan = ah->curchan;
73 unsigned int power, scale, delta;
74
75 if (chan->channel >= 5700)
76 scale = MS(le32_to_cpu(hdr->papdRateMaskHt20),
77 AR9300_PAPRD_SCALE_1);
78 else if (chan->channel >= 5400)
79 scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
80 AR9300_PAPRD_SCALE_2);
81 else
82 scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
83 AR9300_PAPRD_SCALE_1);
84
85 if (IS_CHAN_HT40(chan))
86 power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE8,
87 AR_PHY_POWERTX_RATE8_POWERTXHT40_5);
88 else
89 power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE6,
90 AR_PHY_POWERTX_RATE6_POWERTXHT20_5);
91
92 power += scale;
93 delta = abs((int) ah->paprd_target_power - (int) power);
94 if (delta > scale)
95 return -1;
96
97 power += 2 * get_streams(common->tx_chainmask);
98 return power;
99}
100
101static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
102{
103 struct ath_common *common = ath9k_hw_common(ah);
37 static const u32 ctrl0[3] = { 104 static const u32 ctrl0[3] = {
38 AR_PHY_PAPRD_CTRL0_B0, 105 AR_PHY_PAPRD_CTRL0_B0,
39 AR_PHY_PAPRD_CTRL0_B1, 106 AR_PHY_PAPRD_CTRL0_B1,
@@ -44,21 +111,30 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
44 AR_PHY_PAPRD_CTRL1_B1, 111 AR_PHY_PAPRD_CTRL1_B1,
45 AR_PHY_PAPRD_CTRL1_B2 112 AR_PHY_PAPRD_CTRL1_B2
46 }; 113 };
47 u32 am_mask, ht40_mask; 114 int training_power;
48 int i; 115 int i;
49 116
50 if (ah->curchan && IS_CHAN_5GHZ(ah->curchan)) 117 if (IS_CHAN_2GHZ(ah->curchan))
51 hdr = &eep->modalHeader5G; 118 training_power = ar9003_get_training_power_2g(ah);
52 else 119 else
53 hdr = &eep->modalHeader2G; 120 training_power = ar9003_get_training_power_5g(ah);
54
55 am_mask = le32_to_cpu(hdr->papdRateMaskHt20);
56 ht40_mask = le32_to_cpu(hdr->papdRateMaskHt40);
57
58 REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK, am_mask);
59 REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask);
60 REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask);
61 121
122 if (training_power < 0) {
123 ath_dbg(common, ATH_DBG_CALIBRATE,
124 "PAPRD target power delta out of range");
125 return -ERANGE;
126 }
127 ah->paprd_training_power = training_power;
128 ath_dbg(common, ATH_DBG_CALIBRATE,
129 "Training power: %d, Target power: %d\n",
130 ah->paprd_training_power, ah->paprd_target_power);
131
132 REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK,
133 ah->paprd_ratemask);
134 REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK,
135 ah->paprd_ratemask);
136 REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK,
137 ah->paprd_ratemask_ht40);
62 138
63 for (i = 0; i < ah->caps.max_txchains; i++) { 139 for (i = 0; i < ah->caps.max_txchains; i++) {
64 REG_RMW_FIELD(ah, ctrl0[i], 140 REG_RMW_FIELD(ah, ctrl0[i],
@@ -141,6 +217,7 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
141 AR_PHY_PAPRD_PRE_POST_SCALING, 185706); 217 AR_PHY_PAPRD_PRE_POST_SCALING, 185706);
142 REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_7_B0, 218 REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_7_B0,
143 AR_PHY_PAPRD_PRE_POST_SCALING, 175487); 219 AR_PHY_PAPRD_PRE_POST_SCALING, 175487);
220 return 0;
144} 221}
145 222
146static void ar9003_paprd_get_gain_table(struct ath_hw *ah) 223static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
@@ -595,15 +672,10 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah,
595{ 672{
596 u32 *paprd_table_val = caldata->pa_table[chain]; 673 u32 *paprd_table_val = caldata->pa_table[chain];
597 u32 small_signal_gain = caldata->small_signal_gain[chain]; 674 u32 small_signal_gain = caldata->small_signal_gain[chain];
598 u32 training_power; 675 u32 training_power = ah->paprd_training_power;
599 u32 reg = 0; 676 u32 reg = 0;
600 int i; 677 int i;
601 678
602 training_power =
603 REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
604 AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
605 training_power -= 4;
606
607 if (chain == 0) 679 if (chain == 0)
608 reg = AR_PHY_PAPRD_MEM_TAB_B0; 680 reg = AR_PHY_PAPRD_MEM_TAB_B0;
609 else if (chain == 1) 681 else if (chain == 1)
@@ -643,14 +715,8 @@ EXPORT_SYMBOL(ar9003_paprd_populate_single_table);
643 715
644int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain) 716int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain)
645{ 717{
646
647 unsigned int i, desired_gain, gain_index; 718 unsigned int i, desired_gain, gain_index;
648 unsigned int train_power; 719 unsigned int train_power = ah->paprd_training_power;
649
650 train_power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
651 AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
652
653 train_power = train_power - 4;
654 720
655 desired_gain = ar9003_get_desired_gain(ah, chain, train_power); 721 desired_gain = ar9003_get_desired_gain(ah, chain, train_power);
656 722
@@ -716,7 +782,12 @@ EXPORT_SYMBOL(ar9003_paprd_create_curve);
716 782
717int ar9003_paprd_init_table(struct ath_hw *ah) 783int ar9003_paprd_init_table(struct ath_hw *ah)
718{ 784{
719 ar9003_paprd_setup_single_table(ah); 785 int ret;
786
787 ret = ar9003_paprd_setup_single_table(ah);
788 if (ret < 0)
789 return ret;
790
720 ar9003_paprd_get_gain_table(ah); 791 ar9003_paprd_get_gain_table(ah);
721 return 0; 792 return 0;
722} 793}
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index da4a571304da..8d60f4f09acc 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -578,10 +578,7 @@ static void ar9003_hw_prog_ini(struct ath_hw *ah,
578 u32 reg = INI_RA(iniArr, i, 0); 578 u32 reg = INI_RA(iniArr, i, 0);
579 u32 val = INI_RA(iniArr, i, column); 579 u32 val = INI_RA(iniArr, i, column);
580 580
581 if (reg >= 0x16000 && reg < 0x17000) 581 REG_WRITE(ah, reg, val);
582 ath9k_hw_analog_shift_regwrite(ah, reg, val);
583 else
584 REG_WRITE(ah, reg, val);
585 582
586 DO_DELAY(regWrites); 583 DO_DELAY(regWrites);
587 } 584 }
@@ -748,28 +745,6 @@ static void ar9003_hw_rfbus_done(struct ath_hw *ah)
748 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 745 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
749} 746}
750 747
751/*
752 * Set the interrupt and GPIO values so the ISR can disable RF
753 * on a switch signal. Assumes GPIO port and interrupt polarity
754 * are set prior to call.
755 */
756static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
757{
758 /* Connect rfsilent_bb_l to baseband */
759 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
760 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
761 /* Set input mux for rfsilent_bb_l to GPIO #0 */
762 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
763 AR_GPIO_INPUT_MUX2_RFSILENT);
764
765 /*
766 * Configure the desired GPIO port for input and
767 * enable baseband rf silence.
768 */
769 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
770 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
771}
772
773static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value) 748static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
774{ 749{
775 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT); 750 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
@@ -1206,7 +1181,6 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1206 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; 1181 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1207 priv_ops->rfbus_req = ar9003_hw_rfbus_req; 1182 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1208 priv_ops->rfbus_done = ar9003_hw_rfbus_done; 1183 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1209 priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
1210 priv_ops->set_diversity = ar9003_hw_set_diversity; 1184 priv_ops->set_diversity = ar9003_hw_set_diversity;
1211 priv_ops->ani_control = ar9003_hw_ani_control; 1185 priv_ops->ani_control = ar9003_hw_ani_control;
1212 priv_ops->do_getnf = ar9003_hw_do_getnf; 1186 priv_ops->do_getnf = ar9003_hw_do_getnf;
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 6f811c7ada05..59bab6bd8a74 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -1090,6 +1090,14 @@
1090#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F 1090#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F
1091#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0 1091#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0
1092 1092
1093#define AR_PHY_POWERTX_RATE6 (AR_SM_BASE + 0x1d4)
1094#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5 0x3F00
1095#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S 8
1096
1097#define AR_PHY_POWERTX_RATE8 (AR_SM_BASE + 0x1dc)
1098#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F00
1099#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8
1100
1093void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); 1101void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1094 1102
1095#endif /* AR9003_PHY_H */ 1103#endif /* AR9003_PHY_H */
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 9b5501f90010..2c31f5142eda 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -57,6 +57,8 @@ struct ath_node;
57 57
58#define A_MAX(a, b) ((a) > (b) ? (a) : (b)) 58#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
59 59
60#define ATH9K_PM_QOS_DEFAULT_VALUE 55
61
60#define TSF_TO_TU(_h,_l) \ 62#define TSF_TO_TU(_h,_l) \
61 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 63 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
62 64
@@ -187,6 +189,7 @@ struct ath_txq {
187 struct list_head axq_q; 189 struct list_head axq_q;
188 spinlock_t axq_lock; 190 spinlock_t axq_lock;
189 u32 axq_depth; 191 u32 axq_depth;
192 u32 axq_ampdu_depth;
190 bool stopped; 193 bool stopped;
191 bool axq_tx_inprogress; 194 bool axq_tx_inprogress;
192 struct list_head axq_acq; 195 struct list_head axq_acq;
@@ -663,6 +666,7 @@ static inline void ath_read_cachesize(struct ath_common *common, int *csz)
663extern struct ieee80211_ops ath9k_ops; 666extern struct ieee80211_ops ath9k_ops;
664extern int modparam_nohwcrypt; 667extern int modparam_nohwcrypt;
665extern int led_blink; 668extern int led_blink;
669extern int ath9k_pm_qos_value;
666 670
667irqreturn_t ath_isr(int irq, void *dev); 671irqreturn_t ath_isr(int irq, void *dev);
668int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, 672int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
@@ -671,7 +675,6 @@ void ath9k_deinit_device(struct ath_softc *sc);
671void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 675void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
672void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, 676void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
673 struct ath9k_channel *ichan); 677 struct ath9k_channel *ichan);
674void ath_update_chainmask(struct ath_softc *sc, int is_ht);
675int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 678int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
676 struct ath9k_channel *hchan); 679 struct ath9k_channel *hchan);
677 680
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index fda533cfd881..d05163159572 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -234,7 +234,7 @@ void ath9k_hw_get_target_powers(struct ath_hw *ah,
234u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, 234u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
235 bool is2GHz, int num_band_edges) 235 bool is2GHz, int num_band_edges)
236{ 236{
237 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 237 u16 twiceMaxEdgePower = MAX_RATE_POWER;
238 int i; 238 int i;
239 239
240 for (i = 0; (i < num_band_edges) && 240 for (i = 0; (i < num_band_edges) &&
@@ -279,6 +279,219 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
279 } 279 }
280} 280}
281 281
282void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
283 struct ath9k_channel *chan,
284 void *pRawDataSet,
285 u8 *bChans, u16 availPiers,
286 u16 tPdGainOverlap,
287 u16 *pPdGainBoundaries, u8 *pPDADCValues,
288 u16 numXpdGains)
289{
290 int i, j, k;
291 int16_t ss;
292 u16 idxL = 0, idxR = 0, numPiers;
293 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
294 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
295 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
296 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
297 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
298 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
299
300 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
301 u8 minPwrT4[AR5416_NUM_PD_GAINS];
302 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
303 int16_t vpdStep;
304 int16_t tmpVal;
305 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
306 bool match;
307 int16_t minDelta = 0;
308 struct chan_centers centers;
309 int pdgain_boundary_default;
310 struct cal_data_per_freq *data_def = pRawDataSet;
311 struct cal_data_per_freq_4k *data_4k = pRawDataSet;
312 struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
313 bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
314 int intercepts;
315
316 if (AR_SREV_9287(ah))
317 intercepts = AR9287_PD_GAIN_ICEPTS;
318 else
319 intercepts = AR5416_PD_GAIN_ICEPTS;
320
321 memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
322 ath9k_hw_get_channel_centers(ah, chan, &centers);
323
324 for (numPiers = 0; numPiers < availPiers; numPiers++) {
325 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
326 break;
327 }
328
329 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
330 IS_CHAN_2GHZ(chan)),
331 bChans, numPiers, &idxL, &idxR);
332
333 if (match) {
334 if (AR_SREV_9287(ah)) {
335 /* FIXME: array overrun? */
336 for (i = 0; i < numXpdGains; i++) {
337 minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
338 maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
339 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
340 data_9287[idxL].pwrPdg[i],
341 data_9287[idxL].vpdPdg[i],
342 intercepts,
343 vpdTableI[i]);
344 }
345 } else if (eeprom_4k) {
346 for (i = 0; i < numXpdGains; i++) {
347 minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
348 maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
349 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
350 data_4k[idxL].pwrPdg[i],
351 data_4k[idxL].vpdPdg[i],
352 intercepts,
353 vpdTableI[i]);
354 }
355 } else {
356 for (i = 0; i < numXpdGains; i++) {
357 minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
358 maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
359 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
360 data_def[idxL].pwrPdg[i],
361 data_def[idxL].vpdPdg[i],
362 intercepts,
363 vpdTableI[i]);
364 }
365 }
366 } else {
367 for (i = 0; i < numXpdGains; i++) {
368 if (AR_SREV_9287(ah)) {
369 pVpdL = data_9287[idxL].vpdPdg[i];
370 pPwrL = data_9287[idxL].pwrPdg[i];
371 pVpdR = data_9287[idxR].vpdPdg[i];
372 pPwrR = data_9287[idxR].pwrPdg[i];
373 } else if (eeprom_4k) {
374 pVpdL = data_4k[idxL].vpdPdg[i];
375 pPwrL = data_4k[idxL].pwrPdg[i];
376 pVpdR = data_4k[idxR].vpdPdg[i];
377 pPwrR = data_4k[idxR].pwrPdg[i];
378 } else {
379 pVpdL = data_def[idxL].vpdPdg[i];
380 pPwrL = data_def[idxL].pwrPdg[i];
381 pVpdR = data_def[idxR].vpdPdg[i];
382 pPwrR = data_def[idxR].pwrPdg[i];
383 }
384
385 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
386
387 maxPwrT4[i] =
388 min(pPwrL[intercepts - 1],
389 pPwrR[intercepts - 1]);
390
391
392 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
393 pPwrL, pVpdL,
394 intercepts,
395 vpdTableL[i]);
396 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
397 pPwrR, pVpdR,
398 intercepts,
399 vpdTableR[i]);
400
401 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
402 vpdTableI[i][j] =
403 (u8)(ath9k_hw_interpolate((u16)
404 FREQ2FBIN(centers.
405 synth_center,
406 IS_CHAN_2GHZ
407 (chan)),
408 bChans[idxL], bChans[idxR],
409 vpdTableL[i][j], vpdTableR[i][j]));
410 }
411 }
412 }
413
414 k = 0;
415
416 for (i = 0; i < numXpdGains; i++) {
417 if (i == (numXpdGains - 1))
418 pPdGainBoundaries[i] =
419 (u16)(maxPwrT4[i] / 2);
420 else
421 pPdGainBoundaries[i] =
422 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
423
424 pPdGainBoundaries[i] =
425 min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
426
427 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
428 minDelta = pPdGainBoundaries[0] - 23;
429 pPdGainBoundaries[0] = 23;
430 } else {
431 minDelta = 0;
432 }
433
434 if (i == 0) {
435 if (AR_SREV_9280_20_OR_LATER(ah))
436 ss = (int16_t)(0 - (minPwrT4[i] / 2));
437 else
438 ss = 0;
439 } else {
440 ss = (int16_t)((pPdGainBoundaries[i - 1] -
441 (minPwrT4[i] / 2)) -
442 tPdGainOverlap + 1 + minDelta);
443 }
444 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
445 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
446
447 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
448 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
449 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
450 ss++;
451 }
452
453 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
454 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
455 (minPwrT4[i] / 2));
456 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
457 tgtIndex : sizeCurrVpdTable;
458
459 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
460 pPDADCValues[k++] = vpdTableI[i][ss++];
461 }
462
463 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
464 vpdTableI[i][sizeCurrVpdTable - 2]);
465 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
466
467 if (tgtIndex >= maxIndex) {
468 while ((ss <= tgtIndex) &&
469 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
470 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
471 (ss - maxIndex + 1) * vpdStep));
472 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
473 255 : tmpVal);
474 ss++;
475 }
476 }
477 }
478
479 if (eeprom_4k)
480 pdgain_boundary_default = 58;
481 else
482 pdgain_boundary_default = pPdGainBoundaries[i - 1];
483
484 while (i < AR5416_PD_GAINS_IN_MASK) {
485 pPdGainBoundaries[i] = pdgain_boundary_default;
486 i++;
487 }
488
489 while (k < AR5416_NUM_PDADC_VALUES) {
490 pPDADCValues[k] = pPDADCValues[k - 1];
491 k++;
492 }
493}
494
282int ath9k_hw_eeprom_init(struct ath_hw *ah) 495int ath9k_hw_eeprom_init(struct ath_hw *ah)
283{ 496{
284 int status; 497 int status;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index 8b9885b5243f..f6f09d1378f4 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -17,6 +17,8 @@
17#ifndef EEPROM_H 17#ifndef EEPROM_H
18#define EEPROM_H 18#define EEPROM_H
19 19
20#define AR_EEPROM_MODAL_SPURS 5
21
20#include "../ath.h" 22#include "../ath.h"
21#include <net/cfg80211.h> 23#include <net/cfg80211.h>
22#include "ar9003_eeprom.h" 24#include "ar9003_eeprom.h"
@@ -149,8 +151,6 @@
149#define AR5416_NUM_PD_GAINS 4 151#define AR5416_NUM_PD_GAINS 4
150#define AR5416_PD_GAINS_IN_MASK 4 152#define AR5416_PD_GAINS_IN_MASK 4
151#define AR5416_PD_GAIN_ICEPTS 5 153#define AR5416_PD_GAIN_ICEPTS 5
152#define AR5416_EEPROM_MODAL_SPURS 5
153#define AR5416_MAX_RATE_POWER 63
154#define AR5416_NUM_PDADC_VALUES 128 154#define AR5416_NUM_PDADC_VALUES 128
155#define AR5416_BCHAN_UNUSED 0xFF 155#define AR5416_BCHAN_UNUSED 0xFF
156#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 156#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
@@ -175,8 +175,6 @@
175#define AR5416_EEP4K_NUM_CTLS 12 175#define AR5416_EEP4K_NUM_CTLS 12
176#define AR5416_EEP4K_NUM_BAND_EDGES 4 176#define AR5416_EEP4K_NUM_BAND_EDGES 4
177#define AR5416_EEP4K_NUM_PD_GAINS 2 177#define AR5416_EEP4K_NUM_PD_GAINS 2
178#define AR5416_EEP4K_PD_GAINS_IN_MASK 4
179#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
180#define AR5416_EEP4K_MAX_CHAINS 1 178#define AR5416_EEP4K_MAX_CHAINS 1
181 179
182#define AR9280_TX_GAIN_TABLE_SIZE 22 180#define AR9280_TX_GAIN_TABLE_SIZE 22
@@ -198,35 +196,12 @@
198#define AR9287_NUM_2G_40_TARGET_POWERS 3 196#define AR9287_NUM_2G_40_TARGET_POWERS 3
199#define AR9287_NUM_CTLS 12 197#define AR9287_NUM_CTLS 12
200#define AR9287_NUM_BAND_EDGES 4 198#define AR9287_NUM_BAND_EDGES 4
201#define AR9287_NUM_PD_GAINS 4
202#define AR9287_PD_GAINS_IN_MASK 4
203#define AR9287_PD_GAIN_ICEPTS 1 199#define AR9287_PD_GAIN_ICEPTS 1
204#define AR9287_EEPROM_MODAL_SPURS 5
205#define AR9287_MAX_RATE_POWER 63
206#define AR9287_NUM_PDADC_VALUES 128
207#define AR9287_NUM_RATES 16
208#define AR9287_BCHAN_UNUSED 0xFF
209#define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
210#define AR9287_OPFLAGS_11A 0x01
211#define AR9287_OPFLAGS_11G 0x02
212#define AR9287_OPFLAGS_2G_HT40 0x08
213#define AR9287_OPFLAGS_2G_HT20 0x20
214#define AR9287_OPFLAGS_5G_HT40 0x04
215#define AR9287_OPFLAGS_5G_HT20 0x10
216#define AR9287_EEPMISC_BIG_ENDIAN 0x01 200#define AR9287_EEPMISC_BIG_ENDIAN 0x01
217#define AR9287_EEPMISC_WOW 0x02 201#define AR9287_EEPMISC_WOW 0x02
218#define AR9287_MAX_CHAINS 2 202#define AR9287_MAX_CHAINS 2
219#define AR9287_ANT_16S 32 203#define AR9287_ANT_16S 32
220#define AR9287_custdatasize 20 204
221
222#define AR9287_NUM_ANT_CHAIN_FIELDS 6
223#define AR9287_NUM_ANT_COMMON_FIELDS 4
224#define AR9287_SIZE_ANT_CHAIN_FIELD 2
225#define AR9287_SIZE_ANT_COMMON_FIELD 4
226#define AR9287_ANT_CHAIN_MASK 0x3
227#define AR9287_ANT_COMMON_MASK 0xf
228#define AR9287_CHAIN_0_IDX 0
229#define AR9287_CHAIN_1_IDX 1
230#define AR9287_DATA_SZ 32 205#define AR9287_DATA_SZ 32
231 206
232#define AR9287_PWR_TABLE_OFFSET_DB -5 207#define AR9287_PWR_TABLE_OFFSET_DB -5
@@ -396,7 +371,7 @@ struct modal_eep_header {
396 u16 xpaBiasLvlFreq[3]; 371 u16 xpaBiasLvlFreq[3];
397 u8 futureModal[6]; 372 u8 futureModal[6];
398 373
399 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; 374 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
400} __packed; 375} __packed;
401 376
402struct calDataPerFreqOpLoop { 377struct calDataPerFreqOpLoop {
@@ -464,7 +439,7 @@ struct modal_eep_4k_header {
464 u8 db2_4:4, reserved:4; 439 u8 db2_4:4, reserved:4;
465#endif 440#endif
466 u8 futureModal[4]; 441 u8 futureModal[4];
467 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; 442 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
468} __packed; 443} __packed;
469 444
470struct base_eep_ar9287_header { 445struct base_eep_ar9287_header {
@@ -522,7 +497,7 @@ struct modal_eep_ar9287_header {
522 u8 ob_qam; 497 u8 ob_qam;
523 u8 ob_pal_off; 498 u8 ob_pal_off;
524 u8 futureModal[30]; 499 u8 futureModal[30];
525 struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS]; 500 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
526} __packed; 501} __packed;
527 502
528struct cal_data_per_freq { 503struct cal_data_per_freq {
@@ -531,8 +506,8 @@ struct cal_data_per_freq {
531} __packed; 506} __packed;
532 507
533struct cal_data_per_freq_4k { 508struct cal_data_per_freq_4k {
534 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; 509 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
535 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; 510 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
536} __packed; 511} __packed;
537 512
538struct cal_target_power_leg { 513struct cal_target_power_leg {
@@ -558,8 +533,8 @@ struct cal_data_op_loop_ar9287 {
558} __packed; 533} __packed;
559 534
560struct cal_data_per_freq_ar9287 { 535struct cal_data_per_freq_ar9287 {
561 u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 536 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
562 u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 537 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
563} __packed; 538} __packed;
564 539
565union cal_data_per_freq_ar9287_u { 540union cal_data_per_freq_ar9287_u {
@@ -674,10 +649,6 @@ struct eeprom_ops {
674 bool (*fill_eeprom)(struct ath_hw *hw); 649 bool (*fill_eeprom)(struct ath_hw *hw);
675 int (*get_eeprom_ver)(struct ath_hw *hw); 650 int (*get_eeprom_ver)(struct ath_hw *hw);
676 int (*get_eeprom_rev)(struct ath_hw *hw); 651 int (*get_eeprom_rev)(struct ath_hw *hw);
677 u8 (*get_num_ant_config)(struct ath_hw *hw,
678 enum ath9k_hal_freq_band band);
679 u32 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
680 struct ath9k_channel *chan);
681 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); 652 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
682 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); 653 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
683 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, 654 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
@@ -716,6 +687,14 @@ u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
716void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah); 687void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
717int ath9k_hw_eeprom_init(struct ath_hw *ah); 688int ath9k_hw_eeprom_init(struct ath_hw *ah);
718 689
690void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
691 struct ath9k_channel *chan,
692 void *pRawDataSet,
693 u8 *bChans, u16 availPiers,
694 u16 tPdGainOverlap,
695 u16 *pPdGainBoundaries, u8 *pPDADCValues,
696 u16 numXpdGains);
697
719#define ar5416_get_ntxchains(_txchainmask) \ 698#define ar5416_get_ntxchains(_txchainmask) \
720 (((_txchainmask >> 2) & 1) + \ 699 (((_txchainmask >> 2) & 1) + \
721 ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 700 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 939fc7af86f8..fbdff7e47952 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -153,7 +153,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
153 eep->modalHeader.antCtrlChain[i] = integer; 153 eep->modalHeader.antCtrlChain[i] = integer;
154 } 154 }
155 155
156 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 156 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
157 word = swab16(eep->modalHeader.spurChans[i].spurChan); 157 word = swab16(eep->modalHeader.spurChans[i].spurChan);
158 eep->modalHeader.spurChans[i].spurChan = word; 158 eep->modalHeader.spurChans[i].spurChan = word;
159 } 159 }
@@ -227,173 +227,6 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
227 } 227 }
228} 228}
229 229
230static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
231 struct ath9k_channel *chan,
232 struct cal_data_per_freq_4k *pRawDataSet,
233 u8 *bChans, u16 availPiers,
234 u16 tPdGainOverlap,
235 u16 *pPdGainBoundaries, u8 *pPDADCValues,
236 u16 numXpdGains)
237{
238#define TMP_VAL_VPD_TABLE \
239 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
240 int i, j, k;
241 int16_t ss;
242 u16 idxL = 0, idxR = 0, numPiers;
243 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
244 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
245 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
246 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
247 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
248 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
249
250 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
251 u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
252 u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
253 int16_t vpdStep;
254 int16_t tmpVal;
255 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
256 bool match;
257 int16_t minDelta = 0;
258 struct chan_centers centers;
259#define PD_GAIN_BOUNDARY_DEFAULT 58;
260
261 memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
262 ath9k_hw_get_channel_centers(ah, chan, &centers);
263
264 for (numPiers = 0; numPiers < availPiers; numPiers++) {
265 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
266 break;
267 }
268
269 match = ath9k_hw_get_lower_upper_index(
270 (u8)FREQ2FBIN(centers.synth_center,
271 IS_CHAN_2GHZ(chan)), bChans, numPiers,
272 &idxL, &idxR);
273
274 if (match) {
275 for (i = 0; i < numXpdGains; i++) {
276 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
277 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
278 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
279 pRawDataSet[idxL].pwrPdg[i],
280 pRawDataSet[idxL].vpdPdg[i],
281 AR5416_EEP4K_PD_GAIN_ICEPTS,
282 vpdTableI[i]);
283 }
284 } else {
285 for (i = 0; i < numXpdGains; i++) {
286 pVpdL = pRawDataSet[idxL].vpdPdg[i];
287 pPwrL = pRawDataSet[idxL].pwrPdg[i];
288 pVpdR = pRawDataSet[idxR].vpdPdg[i];
289 pPwrR = pRawDataSet[idxR].pwrPdg[i];
290
291 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
292
293 maxPwrT4[i] =
294 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
295 pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
296
297
298 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
299 pPwrL, pVpdL,
300 AR5416_EEP4K_PD_GAIN_ICEPTS,
301 vpdTableL[i]);
302 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
303 pPwrR, pVpdR,
304 AR5416_EEP4K_PD_GAIN_ICEPTS,
305 vpdTableR[i]);
306
307 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
308 vpdTableI[i][j] =
309 (u8)(ath9k_hw_interpolate((u16)
310 FREQ2FBIN(centers.
311 synth_center,
312 IS_CHAN_2GHZ
313 (chan)),
314 bChans[idxL], bChans[idxR],
315 vpdTableL[i][j], vpdTableR[i][j]));
316 }
317 }
318 }
319
320 k = 0;
321
322 for (i = 0; i < numXpdGains; i++) {
323 if (i == (numXpdGains - 1))
324 pPdGainBoundaries[i] =
325 (u16)(maxPwrT4[i] / 2);
326 else
327 pPdGainBoundaries[i] =
328 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
329
330 pPdGainBoundaries[i] =
331 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
332
333 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
334 minDelta = pPdGainBoundaries[0] - 23;
335 pPdGainBoundaries[0] = 23;
336 } else {
337 minDelta = 0;
338 }
339
340 if (i == 0) {
341 if (AR_SREV_9280_20_OR_LATER(ah))
342 ss = (int16_t)(0 - (minPwrT4[i] / 2));
343 else
344 ss = 0;
345 } else {
346 ss = (int16_t)((pPdGainBoundaries[i - 1] -
347 (minPwrT4[i] / 2)) -
348 tPdGainOverlap + 1 + minDelta);
349 }
350 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
351 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
352
353 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
354 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
355 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
356 ss++;
357 }
358
359 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
360 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
361 (minPwrT4[i] / 2));
362 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
363 tgtIndex : sizeCurrVpdTable;
364
365 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
366 pPDADCValues[k++] = vpdTableI[i][ss++];
367
368 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
369 vpdTableI[i][sizeCurrVpdTable - 2]);
370 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
371
372 if (tgtIndex >= maxIndex) {
373 while ((ss <= tgtIndex) &&
374 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
375 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
376 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
377 255 : tmpVal);
378 ss++;
379 }
380 }
381 }
382
383 while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
384 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
385 i++;
386 }
387
388 while (k < AR5416_NUM_PDADC_VALUES) {
389 pPDADCValues[k] = pPDADCValues[k - 1];
390 k++;
391 }
392
393 return;
394#undef TMP_VAL_VPD_TABLE
395}
396
397static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, 230static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
398 struct ath9k_channel *chan, 231 struct ath9k_channel *chan,
399 int16_t *pTxPowerIndexOffset) 232 int16_t *pTxPowerIndexOffset)
@@ -404,7 +237,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
404 u8 *pCalBChans = NULL; 237 u8 *pCalBChans = NULL;
405 u16 pdGainOverlap_t2; 238 u16 pdGainOverlap_t2;
406 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; 239 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
407 u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK]; 240 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
408 u16 numPiers, i, j; 241 u16 numPiers, i, j;
409 u16 numXpdGain, xpdMask; 242 u16 numXpdGain, xpdMask;
410 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 }; 243 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
@@ -426,12 +259,12 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
426 259
427 numXpdGain = 0; 260 numXpdGain = 0;
428 261
429 for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) { 262 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
430 if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) { 263 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
431 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS) 264 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
432 break; 265 break;
433 xpdGainValues[numXpdGain] = 266 xpdGainValues[numXpdGain] =
434 (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i); 267 (u16)(AR5416_PD_GAINS_IN_MASK - i);
435 numXpdGain++; 268 numXpdGain++;
436 } 269 }
437 } 270 }
@@ -455,7 +288,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
455 if (pEepData->baseEepHeader.txMask & (1 << i)) { 288 if (pEepData->baseEepHeader.txMask & (1 << i)) {
456 pRawDataset = pEepData->calPierData2G[i]; 289 pRawDataset = pEepData->calPierData2G[i];
457 290
458 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan, 291 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
459 pRawDataset, pCalBChans, 292 pRawDataset, pCalBChans,
460 numPiers, pdGainOverlap_t2, 293 numPiers, pdGainOverlap_t2,
461 gainBoundaries, 294 gainBoundaries,
@@ -528,7 +361,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
528 int i; 361 int i;
529 int16_t twiceLargestAntenna; 362 int16_t twiceLargestAntenna;
530 u16 twiceMinEdgePower; 363 u16 twiceMinEdgePower;
531 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 364 u16 twiceMaxEdgePower = MAX_RATE_POWER;
532 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 365 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
533 u16 numCtlModes; 366 u16 numCtlModes;
534 const u16 *pCtlMode; 367 const u16 *pCtlMode;
@@ -537,7 +370,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
537 struct cal_ctl_data_4k *rep; 370 struct cal_ctl_data_4k *rep;
538 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 371 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
539 static const u16 tpScaleReductionTable[5] = 372 static const u16 tpScaleReductionTable[5] =
540 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 373 { 0, 3, 6, 9, MAX_RATE_POWER };
541 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { 374 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
542 0, { 0, 0, 0, 0} 375 0, { 0, 0, 0, 0}
543 }; 376 };
@@ -613,7 +446,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
613 446
614 if (ah->eep_ops->get_eeprom_ver(ah) == 14 && 447 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
615 ah->eep_ops->get_eeprom_rev(ah) <= 2) 448 ah->eep_ops->get_eeprom_rev(ah) <= 2)
616 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 449 twiceMaxEdgePower = MAX_RATE_POWER;
617 450
618 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) && 451 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
619 pEepData->ctlIndex[i]; i++) { 452 pEepData->ctlIndex[i]; i++) {
@@ -752,8 +585,8 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
752 regulatory->max_power_level = 0; 585 regulatory->max_power_level = 0;
753 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 586 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
754 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 587 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
755 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 588 if (ratesArray[i] > MAX_RATE_POWER)
756 ratesArray[i] = AR5416_MAX_RATE_POWER; 589 ratesArray[i] = MAX_RATE_POWER;
757 590
758 if (ratesArray[i] > regulatory->max_power_level) 591 if (ratesArray[i] > regulatory->max_power_level)
759 regulatory->max_power_level = ratesArray[i]; 592 regulatory->max_power_level = ratesArray[i];
@@ -937,8 +770,7 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
937 pModal = &eep->modalHeader; 770 pModal = &eep->modalHeader;
938 txRxAttenLocal = 23; 771 txRxAttenLocal = 23;
939 772
940 REG_WRITE(ah, AR_PHY_SWITCH_COM, 773 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
941 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
942 774
943 /* Single chain for 4K EEPROM*/ 775 /* Single chain for 4K EEPROM*/
944 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal); 776 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
@@ -1154,21 +986,6 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1154 } 986 }
1155} 987}
1156 988
1157static u32 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1158 struct ath9k_channel *chan)
1159{
1160 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1161 struct modal_eep_4k_header *pModal = &eep->modalHeader;
1162
1163 return pModal->antCtrlCommon;
1164}
1165
1166static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1167 enum ath9k_hal_freq_band freq_band)
1168{
1169 return 1;
1170}
1171
1172static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) 989static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1173{ 990{
1174#define EEP_MAP4K_SPURCHAN \ 991#define EEP_MAP4K_SPURCHAN \
@@ -1205,8 +1022,6 @@ const struct eeprom_ops eep_4k_ops = {
1205 .fill_eeprom = ath9k_hw_4k_fill_eeprom, 1022 .fill_eeprom = ath9k_hw_4k_fill_eeprom,
1206 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver, 1023 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
1207 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev, 1024 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
1208 .get_num_ant_config = ath9k_hw_4k_get_num_ant_config,
1209 .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1210 .set_board_values = ath9k_hw_4k_set_board_values, 1025 .set_board_values = ath9k_hw_4k_set_board_values,
1211 .set_addac = ath9k_hw_4k_set_addac, 1026 .set_addac = ath9k_hw_4k_set_addac,
1212 .set_txpower = ath9k_hw_4k_set_txpower, 1027 .set_txpower = ath9k_hw_4k_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index 065402f2e402..9b6bc8a953bc 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -150,7 +150,7 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
150 eep->modalHeader.antCtrlChain[i] = integer; 150 eep->modalHeader.antCtrlChain[i] = integer;
151 } 151 }
152 152
153 for (i = 0; i < AR9287_EEPROM_MODAL_SPURS; i++) { 153 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
154 word = swab16(eep->modalHeader.spurChans[i].spurChan); 154 word = swab16(eep->modalHeader.spurChans[i].spurChan);
155 eep->modalHeader.spurChans[i].spurChan = word; 155 eep->modalHeader.spurChans[i].spurChan = word;
156 } 156 }
@@ -220,163 +220,6 @@ static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
220 } 220 }
221} 221}
222 222
223static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah,
224 struct ath9k_channel *chan,
225 struct cal_data_per_freq_ar9287 *pRawDataSet,
226 u8 *bChans, u16 availPiers,
227 u16 tPdGainOverlap,
228 u16 *pPdGainBoundaries,
229 u8 *pPDADCValues,
230 u16 numXpdGains)
231{
232#define TMP_VAL_VPD_TABLE \
233 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
234
235 int i, j, k;
236 int16_t ss;
237 u16 idxL = 0, idxR = 0, numPiers;
238 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
239 u8 minPwrT4[AR9287_NUM_PD_GAINS];
240 u8 maxPwrT4[AR9287_NUM_PD_GAINS];
241 int16_t vpdStep;
242 int16_t tmpVal;
243 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
244 bool match;
245 int16_t minDelta = 0;
246 struct chan_centers centers;
247 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
248 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
249 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
250 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
251 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
252 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
253
254 memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
255 ath9k_hw_get_channel_centers(ah, chan, &centers);
256
257 for (numPiers = 0; numPiers < availPiers; numPiers++) {
258 if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
259 break;
260 }
261
262 match = ath9k_hw_get_lower_upper_index(
263 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
264 bChans, numPiers, &idxL, &idxR);
265
266 if (match) {
267 for (i = 0; i < numXpdGains; i++) {
268 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
269 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
270 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
271 pRawDataSet[idxL].pwrPdg[i],
272 pRawDataSet[idxL].vpdPdg[i],
273 AR9287_PD_GAIN_ICEPTS,
274 vpdTableI[i]);
275 }
276 } else {
277 for (i = 0; i < numXpdGains; i++) {
278 pVpdL = pRawDataSet[idxL].vpdPdg[i];
279 pPwrL = pRawDataSet[idxL].pwrPdg[i];
280 pVpdR = pRawDataSet[idxR].vpdPdg[i];
281 pPwrR = pRawDataSet[idxR].pwrPdg[i];
282
283 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
284
285 maxPwrT4[i] = min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1],
286 pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
287
288 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
289 pPwrL, pVpdL,
290 AR9287_PD_GAIN_ICEPTS,
291 vpdTableL[i]);
292 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
293 pPwrR, pVpdR,
294 AR9287_PD_GAIN_ICEPTS,
295 vpdTableR[i]);
296
297 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
298 vpdTableI[i][j] = (u8)(ath9k_hw_interpolate(
299 (u16)FREQ2FBIN(centers. synth_center,
300 IS_CHAN_2GHZ(chan)),
301 bChans[idxL], bChans[idxR],
302 vpdTableL[i][j], vpdTableR[i][j]));
303 }
304 }
305 }
306
307 k = 0;
308
309 for (i = 0; i < numXpdGains; i++) {
310 if (i == (numXpdGains - 1))
311 pPdGainBoundaries[i] =
312 (u16)(maxPwrT4[i] / 2);
313 else
314 pPdGainBoundaries[i] =
315 (u16)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
316
317 pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER,
318 pPdGainBoundaries[i]);
319
320
321 minDelta = 0;
322
323 if (i == 0) {
324 if (AR_SREV_9280_20_OR_LATER(ah))
325 ss = (int16_t)(0 - (minPwrT4[i] / 2));
326 else
327 ss = 0;
328 } else {
329 ss = (int16_t)((pPdGainBoundaries[i-1] -
330 (minPwrT4[i] / 2)) -
331 tPdGainOverlap + 1 + minDelta);
332 }
333
334 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
335 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
336
337 while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) {
338 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
339 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
340 ss++;
341 }
342
343 sizeCurrVpdTable = (u8)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
344 tgtIndex = (u8)(pPdGainBoundaries[i] +
345 tPdGainOverlap - (minPwrT4[i] / 2));
346 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
347 tgtIndex : sizeCurrVpdTable;
348
349 while ((ss < maxIndex) && (k < (AR9287_NUM_PDADC_VALUES - 1)))
350 pPDADCValues[k++] = vpdTableI[i][ss++];
351
352 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
353 vpdTableI[i][sizeCurrVpdTable - 2]);
354 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
355
356 if (tgtIndex > maxIndex) {
357 while ((ss <= tgtIndex) &&
358 (k < (AR9287_NUM_PDADC_VALUES - 1))) {
359 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
360 pPDADCValues[k++] =
361 (u8)((tmpVal > 255) ? 255 : tmpVal);
362 ss++;
363 }
364 }
365 }
366
367 while (i < AR9287_PD_GAINS_IN_MASK) {
368 pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
369 i++;
370 }
371
372 while (k < AR9287_NUM_PDADC_VALUES) {
373 pPDADCValues[k] = pPDADCValues[k-1];
374 k++;
375 }
376
377#undef TMP_VAL_VPD_TABLE
378}
379
380static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah, 223static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
381 struct ath9k_channel *chan, 224 struct ath9k_channel *chan,
382 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop, 225 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
@@ -389,7 +232,7 @@ static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
389 ath9k_hw_get_channel_centers(ah, chan, &centers); 232 ath9k_hw_get_channel_centers(ah, chan, &centers);
390 233
391 for (numPiers = 0; numPiers < availPiers; numPiers++) { 234 for (numPiers = 0; numPiers < availPiers; numPiers++) {
392 if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED) 235 if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
393 break; 236 break;
394 } 237 }
395 238
@@ -455,11 +298,11 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
455 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; 298 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
456 u8 *pCalBChans = NULL; 299 u8 *pCalBChans = NULL;
457 u16 pdGainOverlap_t2; 300 u16 pdGainOverlap_t2;
458 u8 pdadcValues[AR9287_NUM_PDADC_VALUES]; 301 u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
459 u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK]; 302 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
460 u16 numPiers = 0, i, j; 303 u16 numPiers = 0, i, j;
461 u16 numXpdGain, xpdMask; 304 u16 numXpdGain, xpdMask;
462 u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0}; 305 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
463 u32 reg32, regOffset, regChainOffset, regval; 306 u32 reg32, regOffset, regChainOffset, regval;
464 int16_t modalIdx, diff = 0; 307 int16_t modalIdx, diff = 0;
465 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 308 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
@@ -487,12 +330,12 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
487 numXpdGain = 0; 330 numXpdGain = 0;
488 331
489 /* Calculate the value of xpdgains from the xpdGain Mask */ 332 /* Calculate the value of xpdgains from the xpdGain Mask */
490 for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) { 333 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
491 if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) { 334 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
492 if (numXpdGain >= AR9287_NUM_PD_GAINS) 335 if (numXpdGain >= AR5416_NUM_PD_GAINS)
493 break; 336 break;
494 xpdGainValues[numXpdGain] = 337 xpdGainValues[numXpdGain] =
495 (u16)(AR9287_PD_GAINS_IN_MASK-i); 338 (u16)(AR5416_PD_GAINS_IN_MASK-i);
496 numXpdGain++; 339 numXpdGain++;
497 } 340 }
498 } 341 }
@@ -525,7 +368,7 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
525 (struct cal_data_per_freq_ar9287 *) 368 (struct cal_data_per_freq_ar9287 *)
526 pEepData->calPierData2G[i]; 369 pEepData->calPierData2G[i];
527 370
528 ath9k_hw_get_ar9287_gain_boundaries_pdadcs(ah, chan, 371 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
529 pRawDataset, 372 pRawDataset,
530 pCalBChans, numPiers, 373 pCalBChans, numPiers,
531 pdGainOverlap_t2, 374 pdGainOverlap_t2,
@@ -561,13 +404,13 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
561 (int32_t)AR9287_PWR_TABLE_OFFSET_DB); 404 (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
562 diff *= 2; 405 diff *= 2;
563 406
564 for (j = 0; j < ((u16)AR9287_NUM_PDADC_VALUES-diff); j++) 407 for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
565 pdadcValues[j] = pdadcValues[j+diff]; 408 pdadcValues[j] = pdadcValues[j+diff];
566 409
567 for (j = (u16)(AR9287_NUM_PDADC_VALUES-diff); 410 for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
568 j < AR9287_NUM_PDADC_VALUES; j++) 411 j < AR5416_NUM_PDADC_VALUES; j++)
569 pdadcValues[j] = 412 pdadcValues[j] =
570 pdadcValues[AR9287_NUM_PDADC_VALUES-diff]; 413 pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
571 } 414 }
572 415
573 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 416 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
@@ -610,9 +453,9 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
610#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 453#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
611 454
612 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 455 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
613 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 456 u16 twiceMaxEdgePower = MAX_RATE_POWER;
614 static const u16 tpScaleReductionTable[5] = 457 static const u16 tpScaleReductionTable[5] =
615 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 458 { 0, 3, 6, 9, MAX_RATE_POWER };
616 int i; 459 int i;
617 int16_t twiceLargestAntenna; 460 int16_t twiceLargestAntenna;
618 struct cal_ctl_data_ar9287 *rep; 461 struct cal_ctl_data_ar9287 *rep;
@@ -877,8 +720,8 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
877 regulatory->max_power_level = 0; 720 regulatory->max_power_level = 0;
878 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 721 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
879 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 722 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
880 if (ratesArray[i] > AR9287_MAX_RATE_POWER) 723 if (ratesArray[i] > MAX_RATE_POWER)
881 ratesArray[i] = AR9287_MAX_RATE_POWER; 724 ratesArray[i] = MAX_RATE_POWER;
882 725
883 if (ratesArray[i] > regulatory->max_power_level) 726 if (ratesArray[i] > regulatory->max_power_level)
884 regulatory->max_power_level = ratesArray[i]; 727 regulatory->max_power_level = ratesArray[i];
@@ -1023,8 +866,7 @@ static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
1023 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3); 866 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
1024 } 867 }
1025 868
1026 REG_WRITE(ah, AR_PHY_SWITCH_COM, 869 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
1027 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1028 870
1029 for (i = 0; i < AR9287_MAX_CHAINS; i++) { 871 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
1030 regChainOffset = i * 0x1000; 872 regChainOffset = i * 0x1000;
@@ -1125,21 +967,6 @@ static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
1125 pModal->xpaBiasLvl); 967 pModal->xpaBiasLvl);
1126} 968}
1127 969
1128static u8 ath9k_hw_ar9287_get_num_ant_config(struct ath_hw *ah,
1129 enum ath9k_hal_freq_band freq_band)
1130{
1131 return 1;
1132}
1133
1134static u32 ath9k_hw_ar9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
1135 struct ath9k_channel *chan)
1136{
1137 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
1138 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
1139
1140 return pModal->antCtrlCommon;
1141}
1142
1143static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah, 970static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
1144 u16 i, bool is2GHz) 971 u16 i, bool is2GHz)
1145{ 972{
@@ -1177,8 +1004,6 @@ const struct eeprom_ops eep_ar9287_ops = {
1177 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom, 1004 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom,
1178 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver, 1005 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
1179 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev, 1006 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
1180 .get_num_ant_config = ath9k_hw_ar9287_get_num_ant_config,
1181 .get_eeprom_antenna_cfg = ath9k_hw_ar9287_get_eeprom_antenna_cfg,
1182 .set_board_values = ath9k_hw_ar9287_set_board_values, 1007 .set_board_values = ath9k_hw_ar9287_set_board_values,
1183 .set_addac = ath9k_hw_ar9287_set_addac, 1008 .set_addac = ath9k_hw_ar9287_set_addac,
1184 .set_txpower = ath9k_hw_ar9287_set_txpower, 1009 .set_txpower = ath9k_hw_ar9287_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index 5bfa031545f4..088f141f2006 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -206,7 +206,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
206 pModal->antCtrlChain[i] = integer; 206 pModal->antCtrlChain[i] = integer;
207 } 207 }
208 208
209 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 209 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
210 word = swab16(pModal->spurChans[i].spurChan); 210 word = swab16(pModal->spurChans[i].spurChan);
211 pModal->spurChans[i].spurChan = word; 211 pModal->spurChans[i].spurChan = word;
212 } 212 }
@@ -374,8 +374,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
374 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 374 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
375 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; 375 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
376 376
377 REG_WRITE(ah, AR_PHY_SWITCH_COM, 377 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
378 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
379 378
380 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 379 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
381 if (AR_SREV_9280(ah)) { 380 if (AR_SREV_9280(ah)) {
@@ -588,168 +587,6 @@ static void ath9k_hw_def_set_addac(struct ath_hw *ah,
588#undef XPA_LVL_FREQ 587#undef XPA_LVL_FREQ
589} 588}
590 589
591static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
592 struct ath9k_channel *chan,
593 struct cal_data_per_freq *pRawDataSet,
594 u8 *bChans, u16 availPiers,
595 u16 tPdGainOverlap,
596 u16 *pPdGainBoundaries, u8 *pPDADCValues,
597 u16 numXpdGains)
598{
599 int i, j, k;
600 int16_t ss;
601 u16 idxL = 0, idxR = 0, numPiers;
602 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
603 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
604 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
605 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
606 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
607 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
608
609 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
610 u8 minPwrT4[AR5416_NUM_PD_GAINS];
611 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
612 int16_t vpdStep;
613 int16_t tmpVal;
614 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
615 bool match;
616 int16_t minDelta = 0;
617 struct chan_centers centers;
618
619 memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
620 ath9k_hw_get_channel_centers(ah, chan, &centers);
621
622 for (numPiers = 0; numPiers < availPiers; numPiers++) {
623 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
624 break;
625 }
626
627 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
628 IS_CHAN_2GHZ(chan)),
629 bChans, numPiers, &idxL, &idxR);
630
631 if (match) {
632 for (i = 0; i < numXpdGains; i++) {
633 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
634 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
635 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
636 pRawDataSet[idxL].pwrPdg[i],
637 pRawDataSet[idxL].vpdPdg[i],
638 AR5416_PD_GAIN_ICEPTS,
639 vpdTableI[i]);
640 }
641 } else {
642 for (i = 0; i < numXpdGains; i++) {
643 pVpdL = pRawDataSet[idxL].vpdPdg[i];
644 pPwrL = pRawDataSet[idxL].pwrPdg[i];
645 pVpdR = pRawDataSet[idxR].vpdPdg[i];
646 pPwrR = pRawDataSet[idxR].pwrPdg[i];
647
648 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
649
650 maxPwrT4[i] =
651 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
652 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
653
654
655 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
656 pPwrL, pVpdL,
657 AR5416_PD_GAIN_ICEPTS,
658 vpdTableL[i]);
659 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
660 pPwrR, pVpdR,
661 AR5416_PD_GAIN_ICEPTS,
662 vpdTableR[i]);
663
664 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
665 vpdTableI[i][j] =
666 (u8)(ath9k_hw_interpolate((u16)
667 FREQ2FBIN(centers.
668 synth_center,
669 IS_CHAN_2GHZ
670 (chan)),
671 bChans[idxL], bChans[idxR],
672 vpdTableL[i][j], vpdTableR[i][j]));
673 }
674 }
675 }
676
677 k = 0;
678
679 for (i = 0; i < numXpdGains; i++) {
680 if (i == (numXpdGains - 1))
681 pPdGainBoundaries[i] =
682 (u16)(maxPwrT4[i] / 2);
683 else
684 pPdGainBoundaries[i] =
685 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
686
687 pPdGainBoundaries[i] =
688 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
689
690 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
691 minDelta = pPdGainBoundaries[0] - 23;
692 pPdGainBoundaries[0] = 23;
693 } else {
694 minDelta = 0;
695 }
696
697 if (i == 0) {
698 if (AR_SREV_9280_20_OR_LATER(ah))
699 ss = (int16_t)(0 - (minPwrT4[i] / 2));
700 else
701 ss = 0;
702 } else {
703 ss = (int16_t)((pPdGainBoundaries[i - 1] -
704 (minPwrT4[i] / 2)) -
705 tPdGainOverlap + 1 + minDelta);
706 }
707 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
708 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
709
710 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
711 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
712 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
713 ss++;
714 }
715
716 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
717 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
718 (minPwrT4[i] / 2));
719 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
720 tgtIndex : sizeCurrVpdTable;
721
722 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
723 pPDADCValues[k++] = vpdTableI[i][ss++];
724 }
725
726 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
727 vpdTableI[i][sizeCurrVpdTable - 2]);
728 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
729
730 if (tgtIndex >= maxIndex) {
731 while ((ss <= tgtIndex) &&
732 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
733 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
734 (ss - maxIndex + 1) * vpdStep));
735 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
736 255 : tmpVal);
737 ss++;
738 }
739 }
740 }
741
742 while (i < AR5416_PD_GAINS_IN_MASK) {
743 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
744 i++;
745 }
746
747 while (k < AR5416_NUM_PDADC_VALUES) {
748 pPDADCValues[k] = pPDADCValues[k - 1];
749 k++;
750 }
751}
752
753static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah, 590static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
754 u16 *gb, 591 u16 *gb,
755 u16 numXpdGain, 592 u16 numXpdGain,
@@ -782,7 +619,7 @@ static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
782 /* Because of a hardware limitation, ensure the gain boundary 619 /* Because of a hardware limitation, ensure the gain boundary
783 * is not larger than (63 - overlap) 620 * is not larger than (63 - overlap)
784 */ 621 */
785 gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2); 622 gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
786 623
787 for (k = 0; k < numXpdGain; k++) 624 for (k = 0; k < numXpdGain; k++)
788 gb[k] = (u16)min(gb_limit, gb[k]); 625 gb[k] = (u16)min(gb_limit, gb[k]);
@@ -916,7 +753,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
916 ath9k_olc_get_pdadcs(ah, pcdacIdx, 753 ath9k_olc_get_pdadcs(ah, pcdacIdx,
917 txPower/2, pdadcValues); 754 txPower/2, pdadcValues);
918 } else { 755 } else {
919 ath9k_hw_get_def_gain_boundaries_pdadcs(ah, 756 ath9k_hw_get_gain_boundaries_pdadcs(ah,
920 chan, pRawDataset, 757 chan, pRawDataset,
921 pCalBChans, numPiers, 758 pCalBChans, numPiers,
922 pdGainOverlap_t2, 759 pdGainOverlap_t2,
@@ -1001,9 +838,9 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
1001 838
1002 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 839 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1003 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; 840 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1004 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 841 u16 twiceMaxEdgePower = MAX_RATE_POWER;
1005 static const u16 tpScaleReductionTable[5] = 842 static const u16 tpScaleReductionTable[5] =
1006 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 843 { 0, 3, 6, 9, MAX_RATE_POWER };
1007 844
1008 int i; 845 int i;
1009 int16_t twiceLargestAntenna; 846 int16_t twiceLargestAntenna;
@@ -1148,7 +985,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
1148 985
1149 if (ah->eep_ops->get_eeprom_ver(ah) == 14 && 986 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1150 ah->eep_ops->get_eeprom_rev(ah) <= 2) 987 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1151 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 988 twiceMaxEdgePower = MAX_RATE_POWER;
1152 989
1153 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 990 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1154 if ((((cfgCtl & ~CTL_MODE_M) | 991 if ((((cfgCtl & ~CTL_MODE_M) |
@@ -1293,8 +1130,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1293 regulatory->max_power_level = 0; 1130 regulatory->max_power_level = 0;
1294 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 1131 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1295 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 1132 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1296 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 1133 if (ratesArray[i] > MAX_RATE_POWER)
1297 ratesArray[i] = AR5416_MAX_RATE_POWER; 1134 ratesArray[i] = MAX_RATE_POWER;
1298 if (ratesArray[i] > regulatory->max_power_level) 1135 if (ratesArray[i] > regulatory->max_power_level)
1299 regulatory->max_power_level = ratesArray[i]; 1136 regulatory->max_power_level = ratesArray[i];
1300 } 1137 }
@@ -1426,34 +1263,6 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1426 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); 1263 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1427} 1264}
1428 1265
1429static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1430 enum ath9k_hal_freq_band freq_band)
1431{
1432 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1433 struct modal_eep_header *pModal =
1434 &(eep->modalHeader[freq_band]);
1435 struct base_eep_header *pBase = &eep->baseEepHeader;
1436 u8 num_ant_config;
1437
1438 num_ant_config = 1;
1439
1440 if (pBase->version >= 0x0E0D &&
1441 (pModal->lna_ctl & LNA_CTL_USE_ANT1))
1442 num_ant_config += 1;
1443
1444 return num_ant_config;
1445}
1446
1447static u32 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1448 struct ath9k_channel *chan)
1449{
1450 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1451 struct modal_eep_header *pModal =
1452 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1453
1454 return pModal->antCtrlCommon;
1455}
1456
1457static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) 1266static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1458{ 1267{
1459#define EEP_DEF_SPURCHAN \ 1268#define EEP_DEF_SPURCHAN \
@@ -1490,8 +1299,6 @@ const struct eeprom_ops eep_def_ops = {
1490 .fill_eeprom = ath9k_hw_def_fill_eeprom, 1299 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1491 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver, 1300 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1492 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev, 1301 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
1493 .get_num_ant_config = ath9k_hw_def_get_num_ant_config,
1494 .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1495 .set_board_values = ath9k_hw_def_set_board_values, 1302 .set_board_values = ath9k_hw_def_set_board_values,
1496 .set_addac = ath9k_hw_def_set_addac, 1303 .set_addac = ath9k_hw_def_set_addac,
1497 .set_txpower = ath9k_hw_def_set_txpower, 1304 .set_txpower = ath9k_hw_def_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
index d0918bd23b8e..22b68b3c8566 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -38,6 +38,7 @@ static struct usb_device_id ath9k_hif_usb_ids[] = {
38 { USB_DEVICE(0x13D3, 0x3350) }, /* Azurewave */ 38 { USB_DEVICE(0x13D3, 0x3350) }, /* Azurewave */
39 { USB_DEVICE(0x04CA, 0x4605) }, /* Liteon */ 39 { USB_DEVICE(0x04CA, 0x4605) }, /* Liteon */
40 { USB_DEVICE(0x040D, 0x3801) }, /* VIA */ 40 { USB_DEVICE(0x040D, 0x3801) }, /* VIA */
41 { USB_DEVICE(0x0cf3, 0xb003) }, /* Ubiquiti WifiStation Ext */
41 42
42 { USB_DEVICE(0x0cf3, 0x7015), 43 { USB_DEVICE(0x0cf3, 0x7015),
43 .driver_info = AR9287_USB }, /* Atheros */ 44 .driver_info = AR9287_USB }, /* Atheros */
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index 20ea75a44e52..dd17909bd903 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -1170,9 +1170,6 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
1170 /* setup initial channel */ 1170 /* setup initial channel */
1171 init_channel = ath9k_cmn_get_curchannel(hw, ah); 1171 init_channel = ath9k_cmn_get_curchannel(hw, ah);
1172 1172
1173 /* Reset SERDES registers */
1174 ath9k_hw_configpcipowersave(ah, 0, 0);
1175
1176 ath9k_hw_htc_resetinit(ah); 1173 ath9k_hw_htc_resetinit(ah);
1177 ret = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 1174 ret = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
1178 if (ret) { 1175 if (ret) {
@@ -1258,7 +1255,6 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
1258 1255
1259 ath9k_hw_phy_disable(ah); 1256 ath9k_hw_phy_disable(ah);
1260 ath9k_hw_disable(ah); 1257 ath9k_hw_disable(ah);
1261 ath9k_hw_configpcipowersave(ah, 1, 1);
1262 ath9k_htc_ps_restore(priv); 1258 ath9k_htc_ps_restore(priv);
1263 ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP); 1259 ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
1264 1260
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
index 31fad82239b3..33f36029fa4f 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
@@ -251,7 +251,7 @@ void ath9k_tx_tasklet(unsigned long data)
251 ista = (struct ath9k_htc_sta *)sta->drv_priv; 251 ista = (struct ath9k_htc_sta *)sta->drv_priv;
252 252
253 if (ath9k_htc_check_tx_aggr(priv, ista, tid)) { 253 if (ath9k_htc_check_tx_aggr(priv, ista, tid)) {
254 ieee80211_start_tx_ba_session(sta, tid); 254 ieee80211_start_tx_ba_session(sta, tid, 0);
255 spin_lock_bh(&priv->tx_lock); 255 spin_lock_bh(&priv->tx_lock);
256 ista->tid_state[tid] = AGGR_PROGRESS; 256 ista->tid_state[tid] = AGGR_PROGRESS;
257 spin_unlock_bh(&priv->tx_lock); 257 spin_unlock_bh(&priv->tx_lock);
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
index 0a4ad348b699..c8f254fe0f0b 100644
--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
@@ -223,11 +223,6 @@ static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
223 return ath9k_hw_private_ops(ah)->rfbus_done(ah); 223 return ath9k_hw_private_ops(ah)->rfbus_done(ah);
224} 224}
225 225
226static inline void ath9k_enable_rfkill(struct ath_hw *ah)
227{
228 return ath9k_hw_private_ops(ah)->enable_rfkill(ah);
229}
230
231static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah) 226static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
232{ 227{
233 if (!ath9k_hw_private_ops(ah)->restore_chainmask) 228 if (!ath9k_hw_private_ops(ah)->restore_chainmask)
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 516227fa668e..4b51ed47fe69 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -54,13 +54,6 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55} 55}
56 56
57static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
58{
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
60
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
62}
63
64static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan) 58 struct ath9k_channel *chan)
66{ 59{
@@ -284,11 +277,9 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
284 277
285static void ath9k_hw_disablepcie(struct ath_hw *ah) 278static void ath9k_hw_disablepcie(struct ath_hw *ah)
286{ 279{
287 if (AR_SREV_9100(ah)) 280 if (!AR_SREV_5416(ah))
288 return; 281 return;
289 282
290 ENABLE_REGWRITE_BUFFER(ah);
291
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
@@ -300,8 +291,6 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
300 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
301 292
302 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
303
304 REGWRITE_BUFFER_FLUSH(ah);
305} 294}
306 295
307/* This should work for all families including legacy */ 296/* This should work for all families including legacy */
@@ -418,9 +407,8 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
418 ah->sta_id1_defaults = 407 ah->sta_id1_defaults =
419 AR_STA_ID1_CRPT_MIC_ENABLE | 408 AR_STA_ID1_CRPT_MIC_ENABLE |
420 AR_STA_ID1_MCAST_KSRCH; 409 AR_STA_ID1_MCAST_KSRCH;
421 ah->beacon_interval = 100;
422 ah->enable_32kHz_clock = DONT_USE_32KHZ; 410 ah->enable_32kHz_clock = DONT_USE_32KHZ;
423 ah->slottime = (u32) -1; 411 ah->slottime = 20;
424 ah->globaltxtimeout = (u32) -1; 412 ah->globaltxtimeout = (u32) -1;
425 ah->power_mode = ATH9K_PM_UNDEFINED; 413 ah->power_mode = ATH9K_PM_UNDEFINED;
426} 414}
@@ -538,7 +526,19 @@ static int __ath9k_hw_init(struct ath_hw *ah)
538 else 526 else
539 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 527 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
540 528
541 if (!ath9k_hw_macversion_supported(ah)) { 529 switch (ah->hw_version.macVersion) {
530 case AR_SREV_VERSION_5416_PCI:
531 case AR_SREV_VERSION_5416_PCIE:
532 case AR_SREV_VERSION_9160:
533 case AR_SREV_VERSION_9100:
534 case AR_SREV_VERSION_9280:
535 case AR_SREV_VERSION_9285:
536 case AR_SREV_VERSION_9287:
537 case AR_SREV_VERSION_9271:
538 case AR_SREV_VERSION_9300:
539 case AR_SREV_VERSION_9485:
540 break;
541 default:
542 ath_err(common, 542 ath_err(common,
543 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 543 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
544 ah->hw_version.macVersion, ah->hw_version.macRev); 544 ah->hw_version.macVersion, ah->hw_version.macRev);
@@ -808,7 +808,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
808 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 808 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
809 acktimeout += 64 - sifstime - ah->slottime; 809 acktimeout += 64 - sifstime - ah->slottime;
810 810
811 ath9k_hw_setslottime(ah, slottime); 811 ath9k_hw_setslottime(ah, ah->slottime);
812 ath9k_hw_set_ack_timeout(ah, acktimeout); 812 ath9k_hw_set_ack_timeout(ah, acktimeout);
813 ath9k_hw_set_cts_timeout(ah, acktimeout); 813 ath9k_hw_set_cts_timeout(ah, acktimeout);
814 if (ah->globaltxtimeout != (u32) -1) 814 if (ah->globaltxtimeout != (u32) -1)
@@ -1272,6 +1272,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1272 1272
1273 ath9k_hw_mark_phy_inactive(ah); 1273 ath9k_hw_mark_phy_inactive(ah);
1274 1274
1275 ah->paprd_table_write_done = false;
1276
1275 /* Only required on the first reset */ 1277 /* Only required on the first reset */
1276 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1278 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1277 REG_WRITE(ah, 1279 REG_WRITE(ah,
@@ -1383,7 +1385,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1383 ath9k_hw_init_qos(ah); 1385 ath9k_hw_init_qos(ah);
1384 1386
1385 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1387 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1386 ath9k_enable_rfkill(ah); 1388 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1387 1389
1388 ath9k_hw_init_global_settings(ah); 1390 ath9k_hw_init_global_settings(ah);
1389 1391
@@ -1627,17 +1629,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1627{ 1629{
1628 int flags = 0; 1630 int flags = 0;
1629 1631
1630 ah->beacon_interval = beacon_period;
1631
1632 ENABLE_REGWRITE_BUFFER(ah); 1632 ENABLE_REGWRITE_BUFFER(ah);
1633 1633
1634 switch (ah->opmode) { 1634 switch (ah->opmode) {
1635 case NL80211_IFTYPE_STATION:
1636 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1637 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1638 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1639 flags |= AR_TBTT_TIMER_EN;
1640 break;
1641 case NL80211_IFTYPE_ADHOC: 1635 case NL80211_IFTYPE_ADHOC:
1642 case NL80211_IFTYPE_MESH_POINT: 1636 case NL80211_IFTYPE_MESH_POINT:
1643 REG_SET_BIT(ah, AR_TXCFG, 1637 REG_SET_BIT(ah, AR_TXCFG,
@@ -1661,14 +1655,6 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1661 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1655 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1662 break; 1656 break;
1663 default: 1657 default:
1664 if (ah->is_monitoring) {
1665 REG_WRITE(ah, AR_NEXT_TBTT_TIMER,
1666 TU_TO_USEC(next_beacon));
1667 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1668 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1669 flags |= AR_TBTT_TIMER_EN;
1670 break;
1671 }
1672 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, 1658 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1673 "%s: unsupported opmode: %d\n", 1659 "%s: unsupported opmode: %d\n",
1674 __func__, ah->opmode); 1660 __func__, ah->opmode);
@@ -1920,11 +1906,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1920 AR_SREV_5416(ah)) 1906 AR_SREV_5416(ah))
1921 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 1907 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
1922 1908
1923 pCap->num_antcfg_5ghz =
1924 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
1925 pCap->num_antcfg_2ghz =
1926 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
1927
1928 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) { 1909 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1929 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; 1910 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1930 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 1911 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index d83cc3b4685b..b8ffaa5dc650 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -204,8 +204,6 @@ struct ath9k_hw_capabilities {
204 u16 tx_triglevel_max; 204 u16 tx_triglevel_max;
205 u16 reg_cap; 205 u16 reg_cap;
206 u8 num_gpio_pins; 206 u8 num_gpio_pins;
207 u8 num_antcfg_2ghz;
208 u8 num_antcfg_5ghz;
209 u8 rx_hp_qdepth; 207 u8 rx_hp_qdepth;
210 u8 rx_lp_qdepth; 208 u8 rx_lp_qdepth;
211 u8 rx_status_len; 209 u8 rx_status_len;
@@ -238,7 +236,6 @@ struct ath9k_ops_config {
238#define SPUR_DISABLE 0 236#define SPUR_DISABLE 0
239#define SPUR_ENABLE_IOCTL 1 237#define SPUR_ENABLE_IOCTL 1
240#define SPUR_ENABLE_EEPROM 2 238#define SPUR_ENABLE_EEPROM 2
241#define AR_EEPROM_MODAL_SPURS 5
242#define AR_SPUR_5413_1 1640 239#define AR_SPUR_5413_1 1640
243#define AR_SPUR_5413_2 1200 240#define AR_SPUR_5413_2 1200
244#define AR_NO_SPUR 0x8000 241#define AR_NO_SPUR 0x8000
@@ -535,7 +532,6 @@ struct ath_hw_radar_conf {
535 * 532 *
536 * @init_mode_regs: Initializes mode registers 533 * @init_mode_regs: Initializes mode registers
537 * @init_mode_gain_regs: Initialize TX/RX gain registers 534 * @init_mode_gain_regs: Initialize TX/RX gain registers
538 * @macversion_supported: If this specific mac revision is supported
539 * 535 *
540 * @rf_set_freq: change frequency 536 * @rf_set_freq: change frequency
541 * @spur_mitigate_freq: spur mitigation 537 * @spur_mitigate_freq: spur mitigation
@@ -557,7 +553,6 @@ struct ath_hw_private_ops {
557 553
558 void (*init_mode_regs)(struct ath_hw *ah); 554 void (*init_mode_regs)(struct ath_hw *ah);
559 void (*init_mode_gain_regs)(struct ath_hw *ah); 555 void (*init_mode_gain_regs)(struct ath_hw *ah);
560 bool (*macversion_supported)(u32 macversion);
561 void (*setup_calibration)(struct ath_hw *ah, 556 void (*setup_calibration)(struct ath_hw *ah,
562 struct ath9k_cal_list *currCal); 557 struct ath9k_cal_list *currCal);
563 558
@@ -581,7 +576,6 @@ struct ath_hw_private_ops {
581 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 576 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
582 bool (*rfbus_req)(struct ath_hw *ah); 577 bool (*rfbus_req)(struct ath_hw *ah);
583 void (*rfbus_done)(struct ath_hw *ah); 578 void (*rfbus_done)(struct ath_hw *ah);
584 void (*enable_rfkill)(struct ath_hw *ah);
585 void (*restore_chainmask)(struct ath_hw *ah); 579 void (*restore_chainmask)(struct ath_hw *ah);
586 void (*set_diversity)(struct ath_hw *ah, bool value); 580 void (*set_diversity)(struct ath_hw *ah, bool value);
587 u32 (*compute_pll_control)(struct ath_hw *ah, 581 u32 (*compute_pll_control)(struct ath_hw *ah,
@@ -767,9 +761,7 @@ struct ath_hw {
767 u32 *bank6Temp; 761 u32 *bank6Temp;
768 762
769 u8 txpower_limit; 763 u8 txpower_limit;
770 int16_t txpower_indexoffset;
771 int coverage_class; 764 int coverage_class;
772 u32 beacon_interval;
773 u32 slottime; 765 u32 slottime;
774 u32 globaltxtimeout; 766 u32 globaltxtimeout;
775 767
@@ -840,6 +832,11 @@ struct ath_hw {
840 u32 bb_watchdog_last_status; 832 u32 bb_watchdog_last_status;
841 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 833 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
842 834
835 unsigned int paprd_target_power;
836 unsigned int paprd_training_power;
837 unsigned int paprd_ratemask;
838 unsigned int paprd_ratemask_ht40;
839 bool paprd_table_write_done;
843 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 840 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
844 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 841 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
845 /* 842 /*
@@ -873,6 +870,11 @@ static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
873 return &ah->ops; 870 return &ah->ops;
874} 871}
875 872
873static inline u8 get_streams(int mask)
874{
875 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
876}
877
876/* Initialization, Detach, Reset */ 878/* Initialization, Detach, Reset */
877const char *ath9k_hw_probe(u16 vendorid, u16 devid); 879const char *ath9k_hw_probe(u16 vendorid, u16 devid);
878void ath9k_hw_deinit(struct ath_hw *ah); 880void ath9k_hw_deinit(struct ath_hw *ah);
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index b2983ce19dfb..b0e5e716b167 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -41,9 +41,14 @@ static int ath9k_btcoex_enable;
41module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 41module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
42MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 42MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
43 43
44int ath9k_pm_qos_value = ATH9K_PM_QOS_DEFAULT_VALUE;
45module_param_named(pmqos, ath9k_pm_qos_value, int, S_IRUSR | S_IRGRP | S_IROTH);
46MODULE_PARM_DESC(pmqos, "User specified PM-QOS value");
47
44/* We use the hw_value as an index into our private channel structure */ 48/* We use the hw_value as an index into our private channel structure */
45 49
46#define CHAN2G(_freq, _idx) { \ 50#define CHAN2G(_freq, _idx) { \
51 .band = IEEE80211_BAND_2GHZ, \
47 .center_freq = (_freq), \ 52 .center_freq = (_freq), \
48 .hw_value = (_idx), \ 53 .hw_value = (_idx), \
49 .max_power = 20, \ 54 .max_power = 20, \
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index daa3c9feca66..8a1691db166d 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -320,6 +320,42 @@ static void ath_paprd_activate(struct ath_softc *sc)
320 ath9k_ps_restore(sc); 320 ath9k_ps_restore(sc);
321} 321}
322 322
323static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
324{
325 struct ieee80211_hw *hw = sc->hw;
326 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
327 struct ath_tx_control txctl;
328 int time_left;
329
330 memset(&txctl, 0, sizeof(txctl));
331 txctl.txq = sc->tx.txq_map[WME_AC_BE];
332
333 memset(tx_info, 0, sizeof(*tx_info));
334 tx_info->band = hw->conf.channel->band;
335 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
336 tx_info->control.rates[0].idx = 0;
337 tx_info->control.rates[0].count = 1;
338 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
339 tx_info->control.rates[1].idx = -1;
340
341 init_completion(&sc->paprd_complete);
342 sc->paprd_pending = true;
343 txctl.paprd = BIT(chain);
344 if (ath_tx_start(hw, skb, &txctl) != 0)
345 return false;
346
347 time_left = wait_for_completion_timeout(&sc->paprd_complete,
348 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
349 sc->paprd_pending = false;
350
351 if (!time_left)
352 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
353 "Timeout waiting for paprd training on TX chain %d\n",
354 chain);
355
356 return !!time_left;
357}
358
323void ath_paprd_calibrate(struct work_struct *work) 359void ath_paprd_calibrate(struct work_struct *work)
324{ 360{
325 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); 361 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
@@ -327,28 +363,23 @@ void ath_paprd_calibrate(struct work_struct *work)
327 struct ath_hw *ah = sc->sc_ah; 363 struct ath_hw *ah = sc->sc_ah;
328 struct ieee80211_hdr *hdr; 364 struct ieee80211_hdr *hdr;
329 struct sk_buff *skb = NULL; 365 struct sk_buff *skb = NULL;
330 struct ieee80211_tx_info *tx_info;
331 int band = hw->conf.channel->band;
332 struct ieee80211_supported_band *sband = &sc->sbands[band];
333 struct ath_tx_control txctl;
334 struct ath9k_hw_cal_data *caldata = ah->caldata; 366 struct ath9k_hw_cal_data *caldata = ah->caldata;
335 struct ath_common *common = ath9k_hw_common(ah); 367 struct ath_common *common = ath9k_hw_common(ah);
336 int ftype; 368 int ftype;
337 int chain_ok = 0; 369 int chain_ok = 0;
338 int chain; 370 int chain;
339 int len = 1800; 371 int len = 1800;
340 int time_left;
341 int i;
342 372
343 if (!caldata) 373 if (!caldata)
344 return; 374 return;
345 375
376 if (ar9003_paprd_init_table(ah) < 0)
377 return;
378
346 skb = alloc_skb(len, GFP_KERNEL); 379 skb = alloc_skb(len, GFP_KERNEL);
347 if (!skb) 380 if (!skb)
348 return; 381 return;
349 382
350 tx_info = IEEE80211_SKB_CB(skb);
351
352 skb_put(skb, len); 383 skb_put(skb, len);
353 memset(skb->data, 0, len); 384 memset(skb->data, 0, len);
354 hdr = (struct ieee80211_hdr *)skb->data; 385 hdr = (struct ieee80211_hdr *)skb->data;
@@ -359,40 +390,25 @@ void ath_paprd_calibrate(struct work_struct *work)
359 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); 390 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
360 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); 391 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
361 392
362 memset(&txctl, 0, sizeof(txctl));
363 txctl.txq = sc->tx.txq_map[WME_AC_BE];
364
365 ath9k_ps_wakeup(sc); 393 ath9k_ps_wakeup(sc);
366 ar9003_paprd_init_table(ah);
367 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { 394 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
368 if (!(common->tx_chainmask & BIT(chain))) 395 if (!(common->tx_chainmask & BIT(chain)))
369 continue; 396 continue;
370 397
371 chain_ok = 0; 398 chain_ok = 0;
372 memset(tx_info, 0, sizeof(*tx_info));
373 tx_info->band = band;
374 399
375 for (i = 0; i < 4; i++) { 400 ath_dbg(common, ATH_DBG_CALIBRATE,
376 tx_info->control.rates[i].idx = sband->n_bitrates - 1; 401 "Sending PAPRD frame for thermal measurement "
377 tx_info->control.rates[i].count = 6; 402 "on chain %d\n", chain);
378 } 403 if (!ath_paprd_send_frame(sc, skb, chain))
404 goto fail_paprd;
379 405
380 init_completion(&sc->paprd_complete);
381 sc->paprd_pending = true;
382 ar9003_paprd_setup_gain_table(ah, chain); 406 ar9003_paprd_setup_gain_table(ah, chain);
383 txctl.paprd = BIT(chain);
384 if (ath_tx_start(hw, skb, &txctl) != 0)
385 break;
386 407
387 time_left = wait_for_completion_timeout(&sc->paprd_complete, 408 ath_dbg(common, ATH_DBG_CALIBRATE,
388 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); 409 "Sending PAPRD training frame on chain %d\n", chain);
389 sc->paprd_pending = false; 410 if (!ath_paprd_send_frame(sc, skb, chain))
390 if (!time_left) {
391 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
392 "Timeout waiting for paprd training on TX chain %d\n",
393 chain);
394 goto fail_paprd; 411 goto fail_paprd;
395 }
396 412
397 if (!ar9003_paprd_is_done(ah)) 413 if (!ar9003_paprd_is_done(ah))
398 break; 414 break;
@@ -517,37 +533,11 @@ set_timer:
517 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { 533 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
518 if (!ah->caldata->paprd_done) 534 if (!ah->caldata->paprd_done)
519 ieee80211_queue_work(sc->hw, &sc->paprd_work); 535 ieee80211_queue_work(sc->hw, &sc->paprd_work);
520 else 536 else if (!ah->paprd_table_write_done)
521 ath_paprd_activate(sc); 537 ath_paprd_activate(sc);
522 } 538 }
523} 539}
524 540
525/*
526 * Update tx/rx chainmask. For legacy association,
527 * hard code chainmask to 1x1, for 11n association, use
528 * the chainmask configuration, for bt coexistence, use
529 * the chainmask configuration even in legacy mode.
530 */
531void ath_update_chainmask(struct ath_softc *sc, int is_ht)
532{
533 struct ath_hw *ah = sc->sc_ah;
534 struct ath_common *common = ath9k_hw_common(ah);
535
536 if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
537 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
538 common->tx_chainmask = ah->caps.tx_chainmask;
539 common->rx_chainmask = ah->caps.rx_chainmask;
540 } else {
541 common->tx_chainmask = 1;
542 common->rx_chainmask = 1;
543 }
544
545 ath_dbg(common, ATH_DBG_CONFIG,
546 "tx chmask: %d, rx chmask: %d\n",
547 common->tx_chainmask,
548 common->rx_chainmask);
549}
550
551static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) 541static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
552{ 542{
553 struct ath_node *an; 543 struct ath_node *an;
@@ -900,8 +890,7 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
900 ath_update_txpow(sc); 890 ath_update_txpow(sc);
901 if (ath_startrecv(sc) != 0) { 891 if (ath_startrecv(sc) != 0) {
902 ath_err(common, "Unable to restart recv logic\n"); 892 ath_err(common, "Unable to restart recv logic\n");
903 spin_unlock_bh(&sc->sc_pcu_lock); 893 goto out;
904 return;
905 } 894 }
906 if (sc->sc_flags & SC_OP_BEACONS) 895 if (sc->sc_flags & SC_OP_BEACONS)
907 ath_beacon_config(sc, NULL); /* restart beacons */ 896 ath_beacon_config(sc, NULL); /* restart beacons */
@@ -915,6 +904,7 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
915 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 904 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
916 905
917 ieee80211_wake_queues(hw); 906 ieee80211_wake_queues(hw);
907out:
918 spin_unlock_bh(&sc->sc_pcu_lock); 908 spin_unlock_bh(&sc->sc_pcu_lock);
919 909
920 ath9k_ps_restore(sc); 910 ath9k_ps_restore(sc);
@@ -1180,7 +1170,11 @@ static int ath9k_start(struct ieee80211_hw *hw)
1180 ath9k_btcoex_timer_resume(sc); 1170 ath9k_btcoex_timer_resume(sc);
1181 } 1171 }
1182 1172
1183 pm_qos_update_request(&sc->pm_qos_req, 55); 1173 /* User has the option to provide pm-qos value as a module
1174 * parameter rather than using the default value of
1175 * 'ATH9K_PM_QOS_DEFAULT_VALUE'.
1176 */
1177 pm_qos_update_request(&sc->pm_qos_req, ath9k_pm_qos_value);
1184 1178
1185 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) 1179 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1186 common->bus_ops->extn_synch_en(common); 1180 common->bus_ops->extn_synch_en(common);
@@ -1333,8 +1327,8 @@ static void ath9k_stop(struct ieee80211_hw *hw)
1333 1327
1334 ath9k_ps_restore(sc); 1328 ath9k_ps_restore(sc);
1335 1329
1336 /* Finally, put the chip in FULL SLEEP mode */ 1330 sc->ps_idle = true;
1337 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); 1331 ath_radio_disable(sc, hw);
1338 1332
1339 sc->sc_flags |= SC_OP_INVALID; 1333 sc->sc_flags |= SC_OP_INVALID;
1340 1334
@@ -1428,13 +1422,78 @@ out:
1428 return ret; 1422 return ret;
1429} 1423}
1430 1424
1425static void ath9k_reclaim_beacon(struct ath_softc *sc,
1426 struct ieee80211_vif *vif)
1427{
1428 struct ath_vif *avp = (void *)vif->drv_priv;
1429
1430 /* Disable SWBA interrupt */
1431 sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
1432 ath9k_ps_wakeup(sc);
1433 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
1434 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1435 tasklet_kill(&sc->bcon_tasklet);
1436 ath9k_ps_restore(sc);
1437
1438 ath_beacon_return(sc, avp);
1439 sc->sc_flags &= ~SC_OP_BEACONS;
1440
1441 if (sc->nbcnvifs > 0) {
1442 /* Re-enable beaconing */
1443 sc->sc_ah->imask |= ATH9K_INT_SWBA;
1444 ath9k_ps_wakeup(sc);
1445 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
1446 ath9k_ps_restore(sc);
1447 }
1448}
1449
1450static int ath9k_change_interface(struct ieee80211_hw *hw,
1451 struct ieee80211_vif *vif,
1452 enum nl80211_iftype new_type,
1453 bool p2p)
1454{
1455 struct ath_wiphy *aphy = hw->priv;
1456 struct ath_softc *sc = aphy->sc;
1457 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1458
1459 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1460 mutex_lock(&sc->mutex);
1461
1462 switch (new_type) {
1463 case NL80211_IFTYPE_AP:
1464 case NL80211_IFTYPE_ADHOC:
1465 if (sc->nbcnvifs >= ATH_BCBUF) {
1466 ath_err(common, "No beacon slot available\n");
1467 return -ENOBUFS;
1468 }
1469 break;
1470 case NL80211_IFTYPE_STATION:
1471 /* Stop ANI */
1472 sc->sc_flags &= ~SC_OP_ANI_RUN;
1473 del_timer_sync(&common->ani.timer);
1474 if ((vif->type == NL80211_IFTYPE_AP) ||
1475 (vif->type == NL80211_IFTYPE_ADHOC))
1476 ath9k_reclaim_beacon(sc, vif);
1477 break;
1478 default:
1479 ath_err(common, "Interface type %d not yet supported\n",
1480 vif->type);
1481 mutex_unlock(&sc->mutex);
1482 return -ENOTSUPP;
1483 }
1484 vif->type = new_type;
1485 vif->p2p = p2p;
1486
1487 mutex_unlock(&sc->mutex);
1488 return 0;
1489}
1490
1431static void ath9k_remove_interface(struct ieee80211_hw *hw, 1491static void ath9k_remove_interface(struct ieee80211_hw *hw,
1432 struct ieee80211_vif *vif) 1492 struct ieee80211_vif *vif)
1433{ 1493{
1434 struct ath_wiphy *aphy = hw->priv; 1494 struct ath_wiphy *aphy = hw->priv;
1435 struct ath_softc *sc = aphy->sc; 1495 struct ath_softc *sc = aphy->sc;
1436 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1496 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1437 struct ath_vif *avp = (void *)vif->drv_priv;
1438 1497
1439 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); 1498 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
1440 1499
@@ -1447,26 +1506,8 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
1447 /* Reclaim beacon resources */ 1506 /* Reclaim beacon resources */
1448 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || 1507 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
1449 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || 1508 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
1450 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { 1509 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT))
1451 /* Disable SWBA interrupt */ 1510 ath9k_reclaim_beacon(sc, vif);
1452 sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
1453 ath9k_ps_wakeup(sc);
1454 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
1455 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1456 ath9k_ps_restore(sc);
1457 tasklet_kill(&sc->bcon_tasklet);
1458 }
1459
1460 ath_beacon_return(sc, avp);
1461 sc->sc_flags &= ~SC_OP_BEACONS;
1462
1463 if (sc->nbcnvifs) {
1464 /* Re-enable SWBA interrupt */
1465 sc->sc_ah->imask |= ATH9K_INT_SWBA;
1466 ath9k_ps_wakeup(sc);
1467 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
1468 ath9k_ps_restore(sc);
1469 }
1470 1511
1471 sc->nvifs--; 1512 sc->nvifs--;
1472 1513
@@ -1612,8 +1653,6 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1612 /* XXX: remove me eventualy */ 1653 /* XXX: remove me eventualy */
1613 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); 1654 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
1614 1655
1615 ath_update_chainmask(sc, conf_is_ht(conf));
1616
1617 /* update survey stats for the old channel before switching */ 1656 /* update survey stats for the old channel before switching */
1618 spin_lock_irqsave(&common->cc_lock, flags); 1657 spin_lock_irqsave(&common->cc_lock, flags);
1619 ath_update_survey_stats(sc); 1658 ath_update_survey_stats(sc);
@@ -1845,10 +1884,6 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1845 /* Set aggregation protection mode parameters */ 1884 /* Set aggregation protection mode parameters */
1846 sc->config.ath_aggr_prot = 0; 1885 sc->config.ath_aggr_prot = 0;
1847 1886
1848 /* Only legacy IBSS for now */
1849 if (vif->type == NL80211_IFTYPE_ADHOC)
1850 ath_update_chainmask(sc, 0);
1851
1852 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n", 1887 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
1853 common->curbssid, common->curaid); 1888 common->curbssid, common->curaid);
1854 1889
@@ -1940,7 +1975,9 @@ static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1940 struct ath_softc *sc = aphy->sc; 1975 struct ath_softc *sc = aphy->sc;
1941 1976
1942 mutex_lock(&sc->mutex); 1977 mutex_lock(&sc->mutex);
1978 ath9k_ps_wakeup(sc);
1943 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1979 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1980 ath9k_ps_restore(sc);
1944 mutex_unlock(&sc->mutex); 1981 mutex_unlock(&sc->mutex);
1945 1982
1946 return tsf; 1983 return tsf;
@@ -1952,7 +1989,9 @@ static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
1952 struct ath_softc *sc = aphy->sc; 1989 struct ath_softc *sc = aphy->sc;
1953 1990
1954 mutex_lock(&sc->mutex); 1991 mutex_lock(&sc->mutex);
1992 ath9k_ps_wakeup(sc);
1955 ath9k_hw_settsf64(sc->sc_ah, tsf); 1993 ath9k_hw_settsf64(sc->sc_ah, tsf);
1994 ath9k_ps_restore(sc);
1956 mutex_unlock(&sc->mutex); 1995 mutex_unlock(&sc->mutex);
1957} 1996}
1958 1997
@@ -2111,6 +2150,7 @@ struct ieee80211_ops ath9k_ops = {
2111 .start = ath9k_start, 2150 .start = ath9k_start,
2112 .stop = ath9k_stop, 2151 .stop = ath9k_stop,
2113 .add_interface = ath9k_add_interface, 2152 .add_interface = ath9k_add_interface,
2153 .change_interface = ath9k_change_interface,
2114 .remove_interface = ath9k_remove_interface, 2154 .remove_interface = ath9k_remove_interface,
2115 .config = ath9k_config, 2155 .config = ath9k_config,
2116 .configure_filter = ath9k_configure_filter, 2156 .configure_filter = ath9k_configure_filter,
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index 747b2871e48f..7ca8499249ec 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -309,6 +309,9 @@ static int ath_pci_resume(struct device *device)
309 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 309 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
310 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); 310 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
311 311
312 sc->ps_idle = true;
313 ath_radio_disable(sc, hw);
314
312 return 0; 315 return 0;
313} 316}
314 317
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index 2061a755a026..896d12986b1e 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -1373,7 +1373,7 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1373 an = (struct ath_node *)sta->drv_priv; 1373 an = (struct ath_node *)sta->drv_priv;
1374 1374
1375 if(ath_tx_aggr_check(sc, an, tid)) 1375 if(ath_tx_aggr_check(sc, an, tid))
1376 ieee80211_start_tx_ba_session(sta, tid); 1376 ieee80211_start_tx_ba_session(sta, tid, 0);
1377 } 1377 }
1378 } 1378 }
1379 1379
diff --git a/drivers/net/wireless/ath/ath9k/virtual.c b/drivers/net/wireless/ath/ath9k/virtual.c
index fbfbc8239971..2dc7095e56d1 100644
--- a/drivers/net/wireless/ath/ath9k/virtual.c
+++ b/drivers/net/wireless/ath/ath9k/virtual.c
@@ -288,7 +288,6 @@ void ath9k_wiphy_chan_work(struct work_struct *work)
288 /* sync hw configuration for hw code */ 288 /* sync hw configuration for hw code */
289 common->hw = aphy->hw; 289 common->hw = aphy->hw;
290 290
291 ath_update_chainmask(sc, sc->chan_is_ht);
292 if (ath_set_channel(sc, aphy->hw, 291 if (ath_set_channel(sc, aphy->hw,
293 &sc->sc_ah->channels[sc->chan_idx]) < 0) { 292 &sc->sc_ah->channels[sc->chan_idx]) < 0) {
294 printk(KERN_DEBUG "ath9k: Failed to set channel for new " 293 printk(KERN_DEBUG "ath9k: Failed to set channel for new "
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 43c0109f202c..332d1feb5c18 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -838,7 +838,7 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
838 ath_tx_txqaddbuf(sc, txq, &bf_q); 838 ath_tx_txqaddbuf(sc, txq, &bf_q);
839 TX_STAT_INC(txq->axq_qnum, a_aggr); 839 TX_STAT_INC(txq->axq_qnum, a_aggr);
840 840
841 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && 841 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
842 status != ATH_AGGR_BAW_CLOSED); 842 status != ATH_AGGR_BAW_CLOSED);
843} 843}
844 844
@@ -999,6 +999,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
999 INIT_LIST_HEAD(&txq->axq_acq); 999 INIT_LIST_HEAD(&txq->axq_acq);
1000 spin_lock_init(&txq->axq_lock); 1000 spin_lock_init(&txq->axq_lock);
1001 txq->axq_depth = 0; 1001 txq->axq_depth = 0;
1002 txq->axq_ampdu_depth = 0;
1002 txq->axq_tx_inprogress = false; 1003 txq->axq_tx_inprogress = false;
1003 sc->tx.txqsetup |= 1<<qnum; 1004 sc->tx.txqsetup |= 1<<qnum;
1004 1005
@@ -1068,6 +1069,12 @@ int ath_cabq_update(struct ath_softc *sc)
1068 return 0; 1069 return 0;
1069} 1070}
1070 1071
1072static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1073{
1074 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1075 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1076}
1077
1071/* 1078/*
1072 * Drain a given TX queue (could be Beacon or Data) 1079 * Drain a given TX queue (could be Beacon or Data)
1073 * 1080 *
@@ -1126,7 +1133,8 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1126 } 1133 }
1127 1134
1128 txq->axq_depth--; 1135 txq->axq_depth--;
1129 1136 if (bf_is_ampdu_not_probing(bf))
1137 txq->axq_ampdu_depth--;
1130 spin_unlock_bh(&txq->axq_lock); 1138 spin_unlock_bh(&txq->axq_lock);
1131 1139
1132 if (bf_isampdu(bf)) 1140 if (bf_isampdu(bf))
@@ -1316,6 +1324,8 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1316 ath9k_hw_txstart(ah, txq->axq_qnum); 1324 ath9k_hw_txstart(ah, txq->axq_qnum);
1317 } 1325 }
1318 txq->axq_depth++; 1326 txq->axq_depth++;
1327 if (bf_is_ampdu_not_probing(bf))
1328 txq->axq_ampdu_depth++;
1319} 1329}
1320 1330
1321static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, 1331static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
@@ -1336,7 +1346,7 @@ static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1336 */ 1346 */
1337 if (!list_empty(&tid->buf_q) || tid->paused || 1347 if (!list_empty(&tid->buf_q) || tid->paused ||
1338 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) || 1348 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1339 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { 1349 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1340 /* 1350 /*
1341 * Add this frame to software queue for scheduling later 1351 * Add this frame to software queue for scheduling later
1342 * for aggregation. 1352 * for aggregation.
@@ -1685,17 +1695,20 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1685 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1695 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1686 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1696 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1687 struct list_head bf_head; 1697 struct list_head bf_head;
1688 struct ath_atx_tid *tid; 1698 struct ath_atx_tid *tid = NULL;
1689 u8 tidno; 1699 u8 tidno;
1690 1700
1691 spin_lock_bh(&txctl->txq->axq_lock); 1701 spin_lock_bh(&txctl->txq->axq_lock);
1692 1702
1693 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && txctl->an) { 1703 if (ieee80211_is_data_qos(hdr->frame_control) && txctl->an) {
1694 tidno = ieee80211_get_qos_ctl(hdr)[0] & 1704 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1695 IEEE80211_QOS_CTL_TID_MASK; 1705 IEEE80211_QOS_CTL_TID_MASK;
1696 tid = ATH_AN_2_TID(txctl->an, tidno); 1706 tid = ATH_AN_2_TID(txctl->an, tidno);
1697 1707
1698 WARN_ON(tid->ac->txq != txctl->txq); 1708 WARN_ON(tid->ac->txq != txctl->txq);
1709 }
1710
1711 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1699 /* 1712 /*
1700 * Try aggregation if it's a unicast data frame 1713 * Try aggregation if it's a unicast data frame
1701 * and the destination is HT capable. 1714 * and the destination is HT capable.
@@ -1712,7 +1725,7 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1712 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc, 1725 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1713 bf->bf_state.bfs_paprd); 1726 bf->bf_state.bfs_paprd);
1714 1727
1715 ath_tx_send_normal(sc, txctl->txq, NULL, &bf_head); 1728 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
1716 } 1729 }
1717 1730
1718 spin_unlock_bh(&txctl->txq->axq_lock); 1731 spin_unlock_bh(&txctl->txq->axq_lock);
@@ -2037,6 +2050,9 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2037 txq->axq_tx_inprogress = false; 2050 txq->axq_tx_inprogress = false;
2038 if (bf_held) 2051 if (bf_held)
2039 list_del(&bf_held->list); 2052 list_del(&bf_held->list);
2053
2054 if (bf_is_ampdu_not_probing(bf))
2055 txq->axq_ampdu_depth--;
2040 spin_unlock_bh(&txq->axq_lock); 2056 spin_unlock_bh(&txq->axq_lock);
2041 2057
2042 if (bf_held) 2058 if (bf_held)
@@ -2165,6 +2181,8 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
2165 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2181 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2166 txq->axq_depth--; 2182 txq->axq_depth--;
2167 txq->axq_tx_inprogress = false; 2183 txq->axq_tx_inprogress = false;
2184 if (bf_is_ampdu_not_probing(bf))
2185 txq->axq_ampdu_depth--;
2168 spin_unlock_bh(&txq->axq_lock); 2186 spin_unlock_bh(&txq->axq_lock);
2169 2187
2170 txok = !(txs.ts_status & ATH9K_TXERR_MASK); 2188 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-06 23:49:18 -0500