diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_eeprom.h')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_eeprom.h | 44 |
1 files changed, 9 insertions, 35 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h index 33503217dab3..afb0b5ee1865 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h | |||
@@ -20,47 +20,22 @@ | |||
20 | /* #define AR9300_NUM_CTLS 21 */ | 20 | /* #define AR9300_NUM_CTLS 21 */ |
21 | #define AR9300_NUM_CTLS_5G 9 | 21 | #define AR9300_NUM_CTLS_5G 9 |
22 | #define AR9300_NUM_CTLS_2G 12 | 22 | #define AR9300_NUM_CTLS_2G 12 |
23 | #define AR9300_CTL_MODE_M 0xF | ||
24 | #define AR9300_NUM_BAND_EDGES_5G 8 | 23 | #define AR9300_NUM_BAND_EDGES_5G 8 |
25 | #define AR9300_NUM_BAND_EDGES_2G 4 | 24 | #define AR9300_NUM_BAND_EDGES_2G 4 |
26 | #define AR9300_NUM_PD_GAINS 4 | ||
27 | #define AR9300_PD_GAINS_IN_MASK 4 | ||
28 | #define AR9300_PD_GAIN_ICEPTS 5 | ||
29 | #define AR9300_EEPROM_MODAL_SPURS 5 | ||
30 | #define AR9300_MAX_RATE_POWER 63 | ||
31 | #define AR9300_NUM_PDADC_VALUES 128 | ||
32 | #define AR9300_NUM_RATES 16 | ||
33 | #define AR9300_BCHAN_UNUSED 0xFF | ||
34 | #define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64 | ||
35 | #define AR9300_OPFLAGS_11A 0x01 | ||
36 | #define AR9300_OPFLAGS_11G 0x02 | ||
37 | #define AR9300_OPFLAGS_5G_HT40 0x04 | ||
38 | #define AR9300_OPFLAGS_2G_HT40 0x08 | ||
39 | #define AR9300_OPFLAGS_5G_HT20 0x10 | ||
40 | #define AR9300_OPFLAGS_2G_HT20 0x20 | ||
41 | #define AR9300_EEPMISC_BIG_ENDIAN 0x01 | 25 | #define AR9300_EEPMISC_BIG_ENDIAN 0x01 |
42 | #define AR9300_EEPMISC_WOW 0x02 | 26 | #define AR9300_EEPMISC_WOW 0x02 |
43 | #define AR9300_CUSTOMER_DATA_SIZE 20 | 27 | #define AR9300_CUSTOMER_DATA_SIZE 20 |
44 | 28 | ||
45 | #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) | ||
46 | #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x)) | 29 | #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x)) |
47 | #define AR9300_MAX_CHAINS 3 | 30 | #define AR9300_MAX_CHAINS 3 |
48 | #define AR9300_ANT_16S 25 | 31 | #define AR9300_ANT_16S 25 |
49 | #define AR9300_FUTURE_MODAL_SZ 6 | 32 | #define AR9300_FUTURE_MODAL_SZ 6 |
50 | 33 | ||
51 | #define AR9300_NUM_ANT_CHAIN_FIELDS 7 | 34 | #define AR9300_PAPRD_RATE_MASK 0x01ffffff |
52 | #define AR9300_NUM_ANT_COMMON_FIELDS 4 | 35 | #define AR9300_PAPRD_SCALE_1 0x0e000000 |
53 | #define AR9300_SIZE_ANT_CHAIN_FIELD 3 | 36 | #define AR9300_PAPRD_SCALE_1_S 25 |
54 | #define AR9300_SIZE_ANT_COMMON_FIELD 4 | 37 | #define AR9300_PAPRD_SCALE_2 0x70000000 |
55 | #define AR9300_ANT_CHAIN_MASK 0x7 | 38 | #define AR9300_PAPRD_SCALE_2_S 28 |
56 | #define AR9300_ANT_COMMON_MASK 0xf | ||
57 | #define AR9300_CHAIN_0_IDX 0 | ||
58 | #define AR9300_CHAIN_1_IDX 1 | ||
59 | #define AR9300_CHAIN_2_IDX 2 | ||
60 | |||
61 | #define AR928X_NUM_ANT_CHAIN_FIELDS 6 | ||
62 | #define AR928X_SIZE_ANT_CHAIN_FIELD 2 | ||
63 | #define AR928X_ANT_CHAIN_MASK 0x3 | ||
64 | 39 | ||
65 | /* Delta from which to start power to pdadc table */ | 40 | /* Delta from which to start power to pdadc table */ |
66 | /* This offset is used in both open loop and closed loop power control | 41 | /* This offset is used in both open loop and closed loop power control |
@@ -71,12 +46,8 @@ | |||
71 | */ | 46 | */ |
72 | #define AR9300_PWR_TABLE_OFFSET 0 | 47 | #define AR9300_PWR_TABLE_OFFSET 0 |
73 | 48 | ||
74 | /* enable flags for voltage and temp compensation */ | ||
75 | #define ENABLE_TEMP_COMPENSATION 0x01 | ||
76 | #define ENABLE_VOLT_COMPENSATION 0x02 | ||
77 | /* byte addressable */ | 49 | /* byte addressable */ |
78 | #define AR9300_EEPROM_SIZE (16*1024) | 50 | #define AR9300_EEPROM_SIZE (16*1024) |
79 | #define FIXED_CCA_THRESHOLD 15 | ||
80 | 51 | ||
81 | #define AR9300_BASE_ADDR_4K 0xfff | 52 | #define AR9300_BASE_ADDR_4K 0xfff |
82 | #define AR9300_BASE_ADDR 0x3ff | 53 | #define AR9300_BASE_ADDR 0x3ff |
@@ -226,7 +197,7 @@ struct ar9300_modal_eep_header { | |||
226 | int8_t tempSlope; | 197 | int8_t tempSlope; |
227 | int8_t voltSlope; | 198 | int8_t voltSlope; |
228 | /* spur channels in usual fbin coding format */ | 199 | /* spur channels in usual fbin coding format */ |
229 | u8 spurChans[AR9300_EEPROM_MODAL_SPURS]; | 200 | u8 spurChans[AR_EEPROM_MODAL_SPURS]; |
230 | /* 3 Check if the register is per chain */ | 201 | /* 3 Check if the register is per chain */ |
231 | int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS]; | 202 | int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS]; |
232 | u8 ob[AR9300_MAX_CHAINS]; | 203 | u8 ob[AR9300_MAX_CHAINS]; |
@@ -344,4 +315,7 @@ s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah); | |||
344 | s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah); | 315 | s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah); |
345 | 316 | ||
346 | u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz); | 317 | u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz); |
318 | |||
319 | unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, | ||
320 | struct ath9k_channel *chan); | ||
347 | #endif | 321 | #endif |