ath9k_hw: Add AR9565 HW support

Various parts of the code require AR9565 checks,
this patch adds them.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 11 insertions, 9 deletions

diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 36386265b8ab..6539d2acb5e8 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -602,6 +602,11 @@ static int __ath9k_hw_init(struct ath_hw *ah)
         if (AR_SREV_9462(ah))
                 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
 
+        if (AR_SREV_9565(ah)) {
+                ah->WARegVal |= AR_WA_BIT22;
+                REG_WRITE(ah, AR_WA, ah->WARegVal);
+        }
+
         ath9k_hw_init_defaults(ah);
         ath9k_hw_init_config(ah);
 
@@ -802,8 +807,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
 {
         u32 pll;
 
-        if (AR_SREV_9485(ah)) {
-
+        if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
                 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
                 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
                               AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
@@ -2036,7 +2040,7 @@ static void ath9k_set_power_sleep(struct ath_hw *ah)
 {
         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
 
-        if (AR_SREV_9462(ah)) {
+        if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
                 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
                 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
                 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
@@ -2491,7 +2495,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
 
         if (AR_SREV_9300_20_OR_LATER(ah)) {
                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
-                if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
+                if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
                         pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
 
                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
@@ -2574,14 +2578,12 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                         ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
         }
 
-        if (AR_SREV_9462(ah)) {
-
+        if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
                 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
                         pCap->hw_caps |= ATH9K_HW_CAP_MCI;
 
                 if (AR_SREV_9462_20(ah))
                         pCap->hw_caps |= ATH9K_HW_CAP_RTT;
-
         }
 
 
@@ -2747,7 +2749,7 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
 
         ENABLE_REGWRITE_BUFFER(ah);
 
-        if (AR_SREV_9462(ah))
+        if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
                 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
 
         REG_WRITE(ah, AR_RX_FILTER, bits);
@@ -3044,7 +3046,7 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
                     gen_tmr_configuration[timer->index].mode_mask);
 
-        if (AR_SREV_9462(ah)) {
+        if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
                 /*
                  * Starting from AR9462, each generic timer can select which tsf
                  * to use. But we still follow the old rule, 0 - 7 use tsf and